Add lm3s6918 system timer logic

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@1773 42af7a65-404d-4744-a932-0658087f49c3

6 files changed, 1434 insertions, 2 deletions

diff --git a/nuttx/arch/arm/src/common/cortexm3_nvic.h b/nuttx/arch/arm/src/common/cortexm3_nvic.h
new file mode 100644
index 000000000..d0982a75a
--- /dev/null
+++ b/nuttx/arch/arm/src/common/cortexm3_nvic.h
@@ -0,0 +1,371 @@
+/************************************************************************************
+ * arch/arm/src/common/cortexm3_nvic.h
+ *
+ *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_COMMON_CORTEXM3_NVIC_H
+#define __ARCH_ARM_SRC_COMMON_CORTEXM3_NVIC_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+
+/* NVIC base address ****************************************************************/
+
+#define CORTEXM3_NVIC_BASE              0xe000e000
+
+/* NVIC register offsets ************************************************************/
+
+#define NVIC_INTCTRL_TYPE_OFFSET        0x0004 /* Interrupt controller type */
+#define NVIC_SYSTICK_CTRL_OFFSET        0x0010 /* SysTick control and status register */
+#define NVIC_SYSTICK_RELOAD_OFFSET      0x0014 /* SysTick reload value register */
+#define NVIC_SYSTICK_CURRENT_OFFSET     0x0018 /* SysTick current value register */
+#define NVIC_SYSTICK_CALIB_OFFSET       0x001c /* SysTick calibration value register */
+
+#define NVIC_IRQ_ENABLE_OFFSET(n)       (0x0100 + 4*((n) >> 5))
+#define NVIC_IRQ0_31_ENABLE_OFFSET      0x0100 /* IRQ 0-31 set enable register */
+#define NVIC_IRQ32_63_ENABLE_OFFSET     0x0104 /* IRQ 32-63 set enable register */
+#define NVIC_IRQ64_95_ENABLE_OFFSET     0x0108 /* IRQ 64-95 set enable register */
+#define NVIC_IRQ96_127_ENABLE_OFFSET    0x010c /* IRQ 96-127 set enable register */
+#define NVIC_IRQ128_159_ENABLE_OFFSET   0x0110 /* IRQ 128-159 set enable register */
+#define NVIC_IRQ160_191_ENABLE_OFFSET   0x0114 /* IRQ 160-191 set enable register */
+#define NVIC_IRQ192_223_ENABLE_OFFSET   0x0118 /* IRQ 192-223 set enable register */
+#define NVIC_IRQ224_239_ENABLE_OFFSET   0x011c /* IRQ 224-239 set enable register */
+
+#define NVIC_IRQ_CLEAR_OFFSET(n)        (0x0180 + 4*((n) >> 5))
+#define NVIC_IRQ0_31_CLEAR_OFFSET       0x0180 /* IRQ 0-31 clear enable register */
+#define NVIC_IRQ32_63_CLEAR_OFFSET      0x0184 /* IRQ 32-63 clear enable register */
+#define NVIC_IRQ64_95_CLEAR_OFFSET      0x0188 /* IRQ 64-95 clear enable register */
+#define NVIC_IRQ96_127_CLEAR_OFFSET     0x018c /* IRQ 96-127 clear enable register */
+#define NVIC_IRQ128_159_CLEAR_OFFSET    0x0190 /* IRQ 128-159 clear enable register */
+#define NVIC_IRQ160_191_CLEAR_OFFSET    0x0194 /* IRQ 160-191 clear enable register */
+#define NVIC_IRQ192_223_CLEAR_OFFSET    0x0198 /* IRQ 192-223 clear enable register */
+#define NVIC_IRQ224_239_CLEAR_OFFSET    0x019c /* IRQ 224-2391 clear enable register */
+
+#define NVIC_IRQ_PEND_OFFSET(n)         (0x0200 + 4*((n) >> 5))
+#define NVIC_IRQ0_31_PEND_OFFSET        0x0200 /* IRQ 0-31 set pending register */
+#define NVIC_IRQ32_63_PEND_OFFSET       0x0204 /* IRQ 32-63 set pending register */
+#define NVIC_IRQ64_95_PEND_OFFSET       0x0208 /* IRQ 64-95 set pending register */
+#define NVIC_IRQ96_127_PEND_OFFSET      0x020c /* IRQ 96-127 set pending register */
+#define NVIC_IRQ128_159_PEND_OFFSET     0x0210 /* IRQ 128-159 set pending register */
+#define NVIC_IRQ160_191_PEND_OFFSET     0x0214 /* IRQ 160-191 set pending register */
+#define NVIC_IRQ192_223_PEND_OFFSET     0x0218 /* IRQ 192-2231 set pending register */
+#define NVIC_IRQ224_239_PEND_OFFSET     0x021c /* IRQ 224-2391 set pending register */
+
+#define NVIC_IRQ_CLRPEND_OFFSET(n)      (0x0280 + 4*((n) >> 5))
+#define NVIC_IRQ0_31_CLRPEND_OFFSET     0x0280 /* IRQ 0-31 clear pending register */
+#define NVIC_IRQ32_63_CLRPEND_OFFSET    0x0284 /* IRQ 32-63 clear pending register */
+#define NVIC_IRQ64_95_CLRPEND_OFFSET    0x0288 /* IRQ 64-95 clear pending register */
+#define NVIC_IRQ96_127_CLRPEND_OFFSET   0x028c /* IRQ 96-127 clear pending register */
+#define NVIC_IRQ128_159_CLRPEND_OFFSET  0x0290 /* IRQ 128-159 clear pending register */
+#define NVIC_IRQ160_191_CLRPEND_OFFSET  0x0294 /* IRQ 160-191 clear pending register */
+#define NVIC_IRQ192_223_CLRPEND_OFFSET  0x0298 /* IRQ 192-223 clear pending register */
+#define NVIC_IRQ224_239_CLRPEND_OFFSET  0x029c /* IRQ 224-239 clear pending register */
+
+#define NVIC_IRQ_ACTIVE_OFFSET(n)       (0x0300 + 4*((n) >> 5))
+#define NVIC_IRQ0_31_ACTIVE_OFFSET      0x0300 /* IRQ 0-31 active bit register */
+#define NVIC_IRQ32_63_ACTIVE_OFFSET     0x0304 /* IRQ 32-63 active bit register */
+#define NVIC_IRQ64_95_ACTIVE_OFFSET     0x0308 /* IRQ 64-95 active bit register */
+#define NVIC_IRQ96_127_ACTIVE_OFFSET    0x030c /* IRQ 96-127 active bit register */
+#define NVIC_IRQ128_159_ACTIVE_OFFSET   0x0310 /* IRQ 128-159 active bit register */
+#define NVIC_IRQ160_191_ACTIVE_OFFSET   0x0314 /* IRQ 160-191 active bit register */
+#define NVIC_IRQ192_223_ACTIVE_OFFSET   0x0318 /* IRQ 192-223 active bit register */
+#define NVIC_IRQ224_239_ACTIVE_OFFSET   0x031c /* IRQ 224-239 active bit register */
+
+#define NVIC_IRQ_PRIORITY_OFFSET(n)     (0x0400 + 4*((n) >> 5))
+#define NVIC_IRQ0_31_PRIORITY_OFFSET    0x0400 /* IRQ 0-31 priority register */
+#define NVIC_IRQ32_63_PRIORITY_OFFSET   0x0404 /* IRQ 32-63 priority register */
+#define NVIC_IRQ64_95_PRIORITY_OFFSET   0x0408 /* IRQ 64-95 priority register */
+#define NVIC_IRQ96_127_PRIORITY_OFFSET  0x040c /* IRQ 96-127 priority register */
+#define NVIC_IRQ128_159_PRIORITY_OFFSET 0x0410 /* IRQ 128-159 priority register */
+#define NVIC_IRQ160_191_PRIORITY_OFFSET 0x0414 /* IRQ 160-191 priority register */
+#define NVIC_IRQ192_223_PRIORITY_OFFSET 0x0418 /* IRQ 192-223 priority register */
+#define NVIC_IRQ224_239_PRIORITY_OFFSET 0x041c /* IRQ 224-239 priority register */
+
+#define NVIC_CPUID_BASE_OFFSET          0x0d00 /* CPUID base register */
+#define NVIC_INTCTRL_OFFSET             0x0d04 /* Interrupt control state register */
+#define NVIC_VECTAB_OFFSET              0x0d08 /* Vector table offset register */
+#define NVIC_AIRC_OFFSET                0x0d0c /* Application interrupt/reset contol registr */
+#define NVIC_SYSCON_OFFSET              0x0d10 /* System control register */
+#define NVIC_CFGCON_OFFSET              0x0d14 /* Configuration control register */
+#define NVIC_SYSH4_7_PRIORITY_OFFSET    0x0d18 /* System handlers 4-7 priority register */
+#define NVIC_SYSH8_11_PRIORITY_OFFSET   0x0d1c /* System handler 8-11 priority register */
+#define NVIC_SYSH12_15_PRIORITY_OFFSET  0x0d20 /* System handler 12-15 priority register */
+#define NVIC_SYSHCON_OFFSET             0x0d24 /* System handler control and state register */
+#define NVIC_CFAULTS_OFFSET             0x0d28 /* Configurable fault status register */
+#define NVIC_HFAULTS_OFFSET             0x0d2c /* Hard fault status register */
+#define NVIC_DFAULTS_OFFSET             0x0d30 /* Debug fault status register */
+#define NVIC_MEMMANAGE_ADDR_OFFSET      0x0d34 /* Mem manage address register */
+#define NVIC_BFAULT_ADDR_OFFSET         0x0d38 /* Bus fault address register */
+#define NVIC_AFAULTS_OFFSET             0x0d3c /* Auxiliary fault status register */
+#define NVIC_PFR0_OFFSET                0x0d40 /* Processor feature register 0 */
+#define NVIC_PFR1_OFFSET                0x0d44 /* Processor feature register 1 */
+#define NVIC_DFR0_OFFSET                0x0d48 /* Debug feature register 0 */
+#define NVIC_AFR0_OFFSET                0x0d4c /* Auxiliary feature register 0 */
+#define NVIC_MMFR0_OFFSET               0x0d50 /* Memory model feature register 0 */
+#define NVIC_MMFR1_OFFSET               0x0d54 /* Memory model feature register 1 */
+#define NVIC_MMFR2_OFFSET               0x0d58 /* Memory model feature register 2 */
+#define NVIC_MMFR3_OFFSET               0x0d5c /* Memory model feature register 3 */
+#define NVIC_ISAR0_OFFSET               0x0d60 /* ISA feature register 0 */
+#define NVIC_ISAR1_OFFSET               0x0d64 /* ISA feature register 1 */
+#define NVIC_ISAR2_OFFSET               0x0d68 /* ISA feature register 2 */
+#define NVIC_ISAR3_OFFSET               0x0d6c /* ISA feature register 3 */
+#define NVIC_ISAR4_OFFSET               0x0d70 /* ISA feature register 4 */
+#define NVIC_STIR_OFFSET                0x0f00 /* Software trigger interrupt register */
+#define NVIC_PID4_OFFSET                0x0fd0 /* Peripheral identification register (PID4) */
+#define NVIC_PID5_OFFSET                0x0fd4 /* Peripheral identification register (PID5) */
+#define NVIC_PID6_OFFSET                0x0fd8 /* Peripheral identification register (PID6) */
+#define NVIC_PID7_OFFSET                0x0fdc /* Peripheral identification register (PID7) */
+#define NVIC_PID0_OFFSET                0x0fe0 /* Peripheral identification register bits 7:0 (PID0) */
+#define NVIC_PID1_OFFSET                0x0fe4 /* Peripheral identification register bits 15:8 (PID1) */
+#define NVIC_PID2_OFFSET                0x0fe8 /* Peripheral identification register bits 23:16 (PID2) */
+#define NVIC_PID3_OFFSET                0x0fec /* Peripheral identification register bits 23:16 (PID3) */
+#define NVIC_CID0_OFFSET                0x0ff0 /* Component identification register bits 7:0 (CID0) */
+#define NVIC_CID1_OFFSET                0x0ff4 /* Component identification register bits 15:8 (CID0) */
+#define NVIC_CID2_OFFSET                0x0ff8 /* Component identification register bits 23:16 (CID0) */
+#define NVIC_CID3_OFFSET                0x0ffc /* Component identification register bits 23:16 (CID0) */
+
+/* NVIC register addresses **********************************************************/
+
+#define NVIC_INTCTRL_TYPE             (CORTEXM3_NVIC_BASE + NVIC_INTCTRL_TYPE_OFFSET)
+#define NVIC_SYSTICK_CTRL             (CORTEXM3_NVIC_BASE + NVIC_SYSTICK_CTRL_OFFSET)
+#define NVIC_SYSTICK_RELOAD           (CORTEXM3_NVIC_BASE + NVIC_SYSTICK_RELOAD_OFFSET)
+#define NVIC_SYSTICK_CURRENT          (CORTEXM3_NVIC_BASE + NVIC_SYSTICK_CURRENT_OFFSET)
+#define NVIC_SYSTICK_CALIB            (CORTEXM3_NVIC_BASE + NVIC_SYSTICK_CALIB_OFFSET)
+
+#define NVIC_IRQ_ENABLE(n)            (CORTEXM3_NVIC_BASE + NVIC_IRQ_ENABLE_OFFSET(n))
+#define NVIC_IRQ0_31_ENABLE           (CORTEXM3_NVIC_BASE + NVIC_IRQ0_31_ENABLE_OFFSET)
+#define NVIC_IRQ32_63_ENABLE          (CORTEXM3_NVIC_BASE + NVIC_IRQ32_63_ENABLE_OFFSET)
+#define NVIC_IRQ64_95_ENABLE          (CORTEXM3_NVIC_BASE + NVIC_IRQ64_95_ENABLE_OFFSET)
+#define NVIC_IRQ96_127_ENABLE         (CORTEXM3_NVIC_BASE + NVIC_IRQ96_127_ENABLE_OFFSET)
+#define NVIC_IRQ128_159_ENABLE        (CORTEXM3_NVIC_BASE + NVIC_IRQ128_159_ENABLE_OFFSET)
+#define NVIC_IRQ160_191_ENABLE        (CORTEXM3_NVIC_BASE + NVIC_IRQ160_191_ENABLE_OFFSET)
+#define NVIC_IRQ192_223_ENABLE        (CORTEXM3_NVIC_BASE + NVIC_IRQ192_223_ENABLE_OFFSET)
+#define NVIC_IRQ224_239_ENABLE        (CORTEXM3_NVIC_BASE + NVIC_IRQ224_239_ENABLE_OFFSET)
+
+#define NVIC_IRQ_CLEAR(n)             (CORTEXM3_NVIC_BASE + NVIC_IRQ_CLEAR_OFFSET(n))
+#define NVIC_IRQ0_31_CLEAR            (CORTEXM3_NVIC_BASE + NVIC_IRQ0_31_CLEAR_OFFSET)
+#define NVIC_IRQ32_63_CLEAR           (CORTEXM3_NVIC_BASE + NVIC_IRQ32_63_CLEAR_OFFSET)
+#define NVIC_IRQ64_95_CLEAR           (CORTEXM3_NVIC_BASE + NVIC_IRQ64_95_CLEAR_OFFSET)
+#define NVIC_IRQ96_127_CLEAR          (CORTEXM3_NVIC_BASE + NVIC_IRQ96_127_CLEAR_OFFSET)
+#define NVIC_IRQ128_159_CLEAR         (CORTEXM3_NVIC_BASE + NVIC_IRQ128_159_CLEAR_OFFSET)
+#define NVIC_IRQ160_191_CLEAR         (CORTEXM3_NVIC_BASE + NVIC_IRQ160_191_CLEAR_OFFSET)
+#define NVIC_IRQ192_223_CLEAR         (CORTEXM3_NVIC_BASE + NVIC_IRQ192_223_CLEAR_OFFSET)
+#define NVIC_IRQ224_239_CLEAR         (CORTEXM3_NVIC_BASE + NVIC_IRQ224_239_CLEAR_OFFSET)
+
+#define NVIC_IRQ_PEND(n)              (CORTEXM3_NVIC_BASE + NVIC_IRQ_PEND_OFFSET(n))
+#define NVIC_IRQ0_31_PEND             (CORTEXM3_NVIC_BASE + NVIC_IRQ0_31_PEND_OFFSET)
+#define NVIC_IRQ32_63_PEND            (CORTEXM3_NVIC_BASE + NVIC_IRQ32_63_PEND_OFFSET)
+#define NVIC_IRQ64_95_PEND            (CORTEXM3_NVIC_BASE + NVIC_IRQ64_95_PEND_OFFSET)
+#define NVIC_IRQ96_127_PEND           (CORTEXM3_NVIC_BASE + NVIC_IRQ96_127_PEND_OFFSET)
+#define NVIC_IRQ128_159_PEND          (CORTEXM3_NVIC_BASE + NVIC_IRQ128_159_PEND_OFFSET)
+#define NVIC_IRQ160_191_PEND          (CORTEXM3_NVIC_BASE + NVIC_IRQ160_191_PEND_OFFSET)
+#define NVIC_IRQ192_223_PEND          (CORTEXM3_NVIC_BASE + NVIC_IRQ192_223_PEND_OFFSET)
+#define NVIC_IRQ224_239_PEND          (CORTEXM3_NVIC_BASE + NVIC_IRQ224_239_PEND_OFFSET)
+
+#define NVIC_IRQ_CLRPEND(n)           (CORTEXM3_NVIC_BASE + NVIC_IRQ_CLRPEND_OFFSET(n))
+#define NVIC_IRQ0_31_CLRPEND          (CORTEXM3_NVIC_BASE + NVIC_IRQ0_31_CLRPEND_OFFSET)
+#define NVIC_IRQ32_63_CLRPEND         (CORTEXM3_NVIC_BASE + NVIC_IRQ32_63_CLRPEND_OFFSET)
+#define NVIC_IRQ64_95_CLRPEND         (CORTEXM3_NVIC_BASE + NVIC_IRQ64_95_CLRPEND_OFFSET)
+#define NVIC_IRQ96_127_CLRPEND        (CORTEXM3_NVIC_BASE + NVIC_IRQ96_127_CLRPEND_OFFSET)
+#define NVIC_IRQ128_159_CLRPEND       (CORTEXM3_NVIC_BASE + NVIC_IRQ128_159_CLRPEND_OFFSET)
+#define NVIC_IRQ160_191_CLRPEND       (CORTEXM3_NVIC_BASE + NVIC_IRQ160_191_CLRPEND_OFFSET)
+#define NVIC_IRQ192_223_CLRPEND       (CORTEXM3_NVIC_BASE + NVIC_IRQ192_223_CLRPEND_OFFSET)
+#define NVIC_IRQ224_239_CLRPEND       (CORTEXM3_NVIC_BASE + NVIC_IRQ224_239_CLRPEND_OFFSET)
+
+#define NVIC_IRQ_ACTIVE(n)            (CORTEXM3_NVIC_BASE + NVIC_IRQ_ACTIVE_OFFSET(n))
+#define NVIC_IRQ0_31_ACTIVE           (CORTEXM3_NVIC_BASE + NVIC_IRQ0_31_ACTIVE_OFFSET)
+#define NVIC_IRQ32_63_ACTIVE          (CORTEXM3_NVIC_BASE + NVIC_IRQ32_63_ACTIVE_OFFSET)
+#define NVIC_IRQ64_95_ACTIVE          (CORTEXM3_NVIC_BASE + NVIC_IRQ64_95_ACTIVE_OFFSET)
+#define NVIC_IRQ96_127_ACTIVE         (CORTEXM3_NVIC_BASE + NVIC_IRQ96_127_ACTIVE_OFFSET)
+#define NVIC_IRQ128_159_ACTIVE        (CORTEXM3_NVIC_BASE + NVIC_IRQ128_159_ACTIVE_OFFSET)
+#define NVIC_IRQ160_191_ACTIVE        (CORTEXM3_NVIC_BASE + NVIC_IRQ160_191_ACTIVE_OFFSET)
+#define NVIC_IRQ192_223_ACTIVE        (CORTEXM3_NVIC_BASE + NVIC_IRQ192_223_ACTIVE_OFFSET)
+#define NVIC_IRQ224_239_ACTIVE        (CORTEXM3_NVIC_BASE + NVIC_IRQ224_239_ACTIVE_OFFSET)
+
+#define NVIC_IRQ_PRIORITY(n)          (CORTEXM3_NVIC_BASE + NVIC_IRQ_PRIORITY_OFFSET(n))
+#define NVIC_IRQ0_31_PRIORITY         (CORTEXM3_NVIC_BASE + NVIC_IRQ0_31_PRIORITY_OFFSET)
+#define NVIC_IRQ32_63_PRIORITY        (CORTEXM3_NVIC_BASE + NVIC_IRQ32_63_PRIORITY_OFFSET)
+#define NVIC_IRQ64_95_PRIORITY        (CORTEXM3_NVIC_BASE + NVIC_IRQ64_95_PRIORITY_OFFSET)
+#define NVIC_IRQ96_127_PRIORITY       (CORTEXM3_NVIC_BASE + NVIC_IRQ96_127_PRIORITY_OFFSET)
+#define NVIC_IRQ128_159_PRIORITY      (CORTEXM3_NVIC_BASE + NVIC_IRQ128_159_PRIORITY_OFFSET)
+#define NVIC_IRQ160_191_PRIORITY      (CORTEXM3_NVIC_BASE + NVIC_IRQ160_191_PRIORITY_OFFSET)
+#define NVIC_IRQ192_223_PRIORITY      (CORTEXM3_NVIC_BASE + NVIC_IRQ192_223_PRIORITY_OFFSET)
+#define NVIC_IRQ224_239_PRIORITY      (CORTEXM3_NVIC_BASE + NVIC_IRQ224_239_PRIORITY_OFFSET)
+
+#define NVIC_CPUID_BASE               (CORTEXM3_NVIC_BASE + NVIC_CPUID_BASE_OFFSET)
+#define NVIC_INTCTRL                  (CORTEXM3_NVIC_BASE + NVIC_INTCTRL_OFFSET)
+#define NVIC_VECTAB                   (CORTEXM3_NVIC_BASE + NVIC_VECTAB_OFFSET)
+#define NVIC_AIRC                     (CORTEXM3_NVIC_BASE + NVIC_AIRC_OFFSET)
+#define NVIC_SYSCON                   (CORTEXM3_NVIC_BASE + NVIC_SYSCON_OFFSET)
+#define NVIC_CFGCON                   (CORTEXM3_NVIC_BASE + NVIC_CFGCON_OFFSET)
+#define NVIC_SYSH4_7_PRIORITY         (CORTEXM3_NVIC_BASE + NVIC_SYSH4_7_PRIORITY_OFFSET)
+#define NVIC_SYSH8_11_PRIORITY        (CORTEXM3_NVIC_BASE + NVIC_SYSH8_11_PRIORITY_OFFSET)
+#define NVIC_SYSH12_15_PRIORITY       (CORTEXM3_NVIC_BASE + NVIC_SYSH12_15_PRIORITY_OFFSET)
+#define NVIC_SYSHCON                  (CORTEXM3_NVIC_BASE + NVIC_SYSHCON_OFFSET)
+#define NVIC_CFAULTS                  (CORTEXM3_NVIC_BASE + NVIC_CFAULTS_OFFSET)
+#define NVIC_HFAULTS                  (CORTEXM3_NVIC_BASE + NVIC_HFAULTS_OFFSET)
+#define NVIC_DFAULTS                  (CORTEXM3_NVIC_BASE + NVIC_DFAULTS_OFFSET)
+#define NVIC_MEMMANAGE_ADDR           (CORTEXM3_NVIC_BASE + NVIC_MEMMANAGE_ADDR_OFFSET)
+#define NVIC_BFAULT_ADDR              (CORTEXM3_NVIC_BASE + NVIC_BFAULT_ADDR_OFFSET)
+#define NVIC_AFAULTS                  (CORTEXM3_NVIC_BASE + NVIC_AFAULTS_OFFSET)
+#define NVIC_PFR0                     (CORTEXM3_NVIC_BASE + NVIC_PFR0_OFFSET)
+#define NVIC_PFR1                     (CORTEXM3_NVIC_BASE + NVIC_PFR1_OFFSET)
+#define NVIC_DFR0                     (CORTEXM3_NVIC_BASE + NVIC_DFR0_OFFSET)
+#define NVIC_AFR0                     (CORTEXM3_NVIC_BASE + NVIC_AFR0_OFFSET)
+#define NVIC_MMFR0                    (CORTEXM3_NVIC_BASE + NVIC_MMFR0_OFFSET)
+#define NVIC_MMFR1                    (CORTEXM3_NVIC_BASE + NVIC_MMFR1_OFFSET)
+#define NVIC_MMFR2                    (CORTEXM3_NVIC_BASE + NVIC_MMFR2_OFFSET)
+#define NVIC_MMFR3                    (CORTEXM3_NVIC_BASE + NVIC_MMFR3_OFFSET)
+#define NVIC_ISAR0                    (CORTEXM3_NVIC_BASE + NVIC_ISAR0_OFFSET)
+#define NVIC_ISAR1                    (CORTEXM3_NVIC_BASE + NVIC_ISAR1_OFFSET)
+#define NVIC_ISAR2                    (CORTEXM3_NVIC_BASE + NVIC_ISAR2_OFFSET)
+#define NVIC_ISAR3                    (CORTEXM3_NVIC_BASE + NVIC_ISAR3_OFFSET)
+#define NVIC_ISAR4                    (CORTEXM3_NVIC_BASE + NVIC_ISAR4_OFFSET)
+#define NVIC_STIR                     (CORTEXM3_NVIC_BASE + NVIC_STIR_OFFSET)
+#define NVIC_PID4                     (CORTEXM3_NVIC_BASE + NVIC_PID4_OFFSET)
+#define NVIC_PID5                     (CORTEXM3_NVIC_BASE + NVIC_PID5_OFFSET)
+#define NVIC_PID6                     (CORTEXM3_NVIC_BASE + NVIC_PID6_OFFSET)
+#define NVIC_PID7                     (CORTEXM3_NVIC_BASE + NVIC_PID7_OFFSET)
+#define NVIC_PID0                     (CORTEXM3_NVIC_BASE + NVIC_PID0_OFFSET)
+#define NVIC_PID1                     (CORTEXM3_NVIC_BASE + NVIC_PID1_OFFSET)
+#define NVIC_PID2                     (CORTEXM3_NVIC_BASE + NVIC_PID2_OFFSET)
+#define NVIC_PID3                     (CORTEXM3_NVIC_BASE + NVIC_PID3_OFFSET)
+#define NVIC_CID0                     (CORTEXM3_NVIC_BASE + NVIC_CID0_OFFSET)
+#define NVIC_CID1                     (CORTEXM3_NVIC_BASE + NVIC_CID1_OFFSET)
+#define NVIC_CID2                     (CORTEXM3_NVIC_BASE + NVIC_CID2_OFFSET)
+#define NVIC_CID3                     (CORTEXM3_NVIC_BASE + NVIC_CID3_OFFSET)
+
+/* NVIC register bit definitions ****************************************************/
+
+/* Interrrupt controller type (INCTCTL_TYPE) */
+
+#define NVIC_INTCTRL_TYPE_INTLINESNUM_SHIFT 0    /* Bits 4-0: Number of interrupt intputs / 32 */
+#define NVIC_INTCTRL_TYPE_INTLINESNUM_MASK  (0x1f << NVIC_INTCTRL_TYPE_INTLINESNUM_SHIFT)
+
+/* SysTick control and status register (SYSTICK_CTRL) */
+
+#define NVIC_SYSTICK_CTRL_ENABLE       (1 << 0)  /* Bit 0:  Enable */
+#define NVIC_SYSTICK_CTRL_TICKINT      (1 << 1)  /* Bit 1:  Tick interrupt */
+#define NVIC_SYSTICK_CTRL_CLKSOURCE    (1 << 2)  /* Bit 2:  Clock source */
+#define NVIC_SYSTICK_CTRL_COUNTFLAG    (1 << 16) /* Bit 16: Count Flag */
+
+/* SysTick reload value register (SYSTICK_RELOAD) */
+
+#define NVIC_SYSTICK_RELOAD_SHIFT      0         /* Bits 23-0: Timer reload value */
+#define NVIC_SYSTICK_RELOAD_MASK       (0x00ffffff << NVIC_SYSTICK_RELOAD_SHIFT)
+
+/* SysTick current value registe (SYSTICK_CURRENT) */
+
+#define NVIC_SYSTICK_CURRENT_SHIFT     0         /* Bits 23-0: Timer current value */
+#define NVIC_SYSTICK_CURRENT_MASK      (0x00ffffff << NVIC_SYSTICK_RELOAD_SHIFT)
+
+/* SysTick calibration value register (SYSTICK_CALIB) */
+
+#define NVIC_SYSTICK_CALIB_TENMS_SHIFT 0        /* Bits 23-0: Calibration value */
+#define NVIC_SYSTICK_CALIB_TENMS_MASK  (0x00ffffff << NVIC_SYSTICK_CALIB_TENMS_SHIFT)
+#define NVIC_SYSTICK_CALIB_SKEW        (1 << 30) /* Bit 30: Calibration value inexact */
+#define NVIC_SYSTICK_CALIB_NOREF       (1 << 31) /* Bit 31: No external reference clock */
+
+/* Interrupt control state register (INTCTRL) */
+
+#define NVIC_INTCTRL_NMIPENDSET        (1 << 31) /* Bit 31: Set pending NMI bit */
+#define NVIC_INTCTRL_PENDSVSET         (1 << 28) /* Bit 28: Set pending PendSV bit */
+#define NVIC_INTCTRL_PENDSVCLR         (1 << 27) /* Bit 27: Clear pending PendSV bit */
+#define NVIC_INTCTRL_PENDSTSET         (1 << 26) /* Bit 26: Set pending SysTick bit */
+#define NVIC_INTCTRL_PENDSTCLR         (1 << 25) /* Bit 25: Clear pending SysTick bit */
+#define NVIC_INTCTRL_ISPREEMPOT        (1 << 23) /* Bit 23: Pending active next cycle */
+#define NVIC_INTCTRL_ISRPENDING        (1 << 22) /* Bit 22: Interrupt pending flag */
+#define NVIC_INTCTRL_VECTPENDING_SHIFT 12        /* Bits 21-12: Pending ISR number field */
+#define NVIC_INTCTRL_VECTPENDING_MASK  (0x3ff << NVIC_INTCTRL_VECTPENDING_SHIFT)
+#define NVIC_INTCTRL_RETTOBASE         (1 << 11) /* Bit 11: no other exceptions pending */
+#define NVIC_INTCTRL_VECTACTIVE_SHIFT  0         /* Bits 8-0: Active ISR number */
+#define NVIC_INTCTRL_VECTACTIVE_MASK   (0x1ff << NVIC_INTCTRL_VECTACTIVE_SHIFT)
+
+/* System handler 4-7 priority register */
+
+#define NVIC_SYSH_PRIORITY_DEFAULT     15
+
+#define NVIC_SYSH_PRIORITY_PR4_SHIFT   0
+#define NVIC_SYSH_PRIORITY_PR4_MASK    (0xff << NVIC_SYSH_PRIORITY_PR4_SHIFT)
+#define NVIC_SYSH_PRIORITY_PR5_SHIFT   8
+#define NVIC_SYSH_PRIORITY_PR5_MASK    (0xff << NVIC_SYSH_PRIORITY_PR5_SHIFT)
+#define NVIC_SYSH_PRIORITY_PR6_SHIFT   16
+#define NVIC_SYSH_PRIORITY_PR6_MASK    (0xff << NVIC_SYSH_PRIORITY_PR6_SHIFT)
+#define NVIC_SYSH_PRIORITY_PR7_SHIFT   24
+#define NVIC_SYSH_PRIORITY_PR7_MASK    (0xff << NVIC_SYSH_PRIORITY_PR7_SHIFT)
+
+/* System handler 8-11 priority register */
+
+#define NVIC_SYSH_PRIORITY_PR8_SHIFT 0
+#define NVIC_SYSH_PRIORITY_PR8_MASK  (0xff << NVIC_SYSH_PRIORITY_PR8_SHIFT)
+#define NVIC_SYSH_PRIORITY_PR9_SHIFT 8
+#define NVIC_SYSH_PRIORITY_PR9_MASK  (0xff << NVIC_SYSH_PRIORITY_PR9_SHIFT)
+#define NVIC_SYSH_PRIORITY_PR10_SHIFT 16
+#define NVIC_SYSH_PRIORITY_PR10_MASK  (0xff << NVIC_SYSH_PRIORITY_PR10_SHIFT)
+#define NVIC_SYSH_PRIORITY_PR11_SHIFT 24
+#define NVIC_SYSH_PRIORITY_PR11_MASK  (0xff << NVIC_SYSH_PRIORITY_PR11_SHIFT)
+
+/* System handler 12-15 priority register */
+
+#define NVIC_SYSH_PRIORITY_PR12_SHIFT 0
+#define NVIC_SYSH_PRIORITY_PR12_MASK  (0xff << NVIC_SYSH_PRIORITY_PR12_SHIFT)
+#define NVIC_SYSH_PRIORITY_PR13_SHIFT 8
+#define NVIC_SYSH_PRIORITY_PR13_MASK  (0xff << NVIC_SYSH_PRIORITY_PR13_SHIFT)
+#define NVIC_SYSH_PRIORITY_PR14_SHIFT 16
+#define NVIC_SYSH_PRIORITY_PR14_MASK  (0xff << NVIC_SYSH_PRIORITY_PR14_SHIFT)
+#define NVIC_SYSH_PRIORITY_PR15_SHIFT 24
+#define NVIC_SYSH_PRIORITY_PR15_MASK  (0xff << NVIC_SYSH_PRIORITY_PR15_SHIFT)
+
+
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Function Prototypes
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_COMMON_CORTEXM3_NVIC_H */
diff --git a/nuttx/arch/arm/src/lm3s/Make.defs b/nuttx/arch/arm/src/lm3s/Make.defs
index 525e052db..b312d330c 100644
--- a/nuttx/arch/arm/src/lm3s/Make.defs
+++ b/nuttx/arch/arm/src/lm3s/Make.defs
@@ -46,7 +46,8 @@ CMN_CSRCS	= up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c \
 		  up_undefinedinsn.c up_usestack.c
 
 CHIP_ASRCS	= 
-CHIP_CSRCS	= lm3s_start.c lm3s_syscontrol.c lm3s_irq.c lm3s_lowputc.c lm3s_serial.c
+CHIP_CSRCS	= lm3s_start.c lm3s_syscontrol.c lm3s_irq.c lm3s_timerisr.c \
+		  lm3s_lowputc.c lm3s_serial.c
 
 ifdef CONFIG_NET
 CHIP_CSRCS	+= lm3s_ethernet.c
diff --git a/nuttx/arch/arm/src/lm3s/chip.h b/nuttx/arch/arm/src/lm3s/chip.h
index 9613e4c07..a5175a49f 100644
--- a/nuttx/arch/arm/src/lm3s/chip.h
+++ b/nuttx/arch/arm/src/lm3s/chip.h
@@ -47,6 +47,7 @@
 #include "lm3s_syscontrol.h"    /* System control module */
 #include "lm3s_gpio.h"          /* GPIO module */
 #include "lm3s_uart.h"          /* UART peripherals */
+#include "cortexm3_nvic.h"      /* Nested, vectored interrupt controller */
 
 /************************************************************************************
  * Definitions
diff --git a/nuttx/arch/arm/src/lm3s/lm3s_memorymap.h b/nuttx/arch/arm/src/lm3s/lm3s_memorymap.h
index df8fc0460..0b4401069 100644
--- a/nuttx/arch/arm/src/lm3s/lm3s_memorymap.h
+++ b/nuttx/arch/arm/src/lm3s/lm3s_memorymap.h
@@ -129,7 +129,7 @@
  ************************************************************************************/
 
 /************************************************************************************
- * Public Functions
+ * Public Function Prototypes
  ************************************************************************************/
 
 #endif /* __ARCH_ARM_SRC_LM3S_LM3S_MEMORYMAP_H */
diff --git a/nuttx/arch/arm/src/lm3s/lm3s_serial.c b/nuttx/arch/arm/src/lm3s/lm3s_serial.c
new file mode 100644
index 000000000..71a877e3f
--- /dev/null
+++ b/nuttx/arch/arm/src/lm3s/lm3s_serial.c
@@ -0,0 +1,919 @@
+/****************************************************************************
+ * arch/arm/src/lm3s/lm3s_serial.c
+ *
+ *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include <unistd.h>
+#include <semaphore.h>
+#include <string.h>
+#include <errno.h>
+#include <debug.h>
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+#include <nuttx/serial.h>
+#include <arch/serial.h>
+
+#include "chip.h"
+#include "up_arch.h"
+#include "up_internal.h"
+
+#ifdef CONFIG_USE_SERIALDRIVER
+
+/****************************************************************************
+ * Definitions
+ ****************************************************************************/
+
+/* Some sanity checks *******************************************************/
+
+/* Is there a UART enabled? */
+
+#if defined(CONFIG_UART0_DISABLE) && defined(CONFIG_UART1_DISABLE)
+#  error "No UARTs enabled"
+#endif
+
+/* Is there a serial console? */
+
+#if defined(CONFIG_UART0_SERIAL_CONSOLE) && !defined(CONFIG_UART0_DISABLE)
+#  undef CONFIG_UART1_SERIAL_CONSOLE
+#  define HAVE_CONSOLE 1
+#elif defined(CONFIG_UART1_SERIAL_CONSOLE) && !defined(CONFIG_UART1_DISABLE)
+#  undef CONFIG_UART0_SERIAL_CONSOLE
+#  define HAVE_CONSOLE 1
+#else
+#  warning "No valid CONFIG_UARTn_SERIAL_CONSOLE Setting"
+#  undef CONFIG_UART0_SERIAL_CONSOLE
+#  undef CONFIG_UART1_SERIAL_CONSOLE
+#  undef HAVE_CONSOLE
+#endif
+
+/* Which UART with be tty0/console and which tty1? */
+
+#if defined(CONFIG_UART0_SERIAL_CONSOLE)
+#  define CONSOLE_DEV     g_uart0port     /* UART0 is console */
+#  define TTYS0_DEV       g_uart0port     /* UART0 is ttyS0 */
+#  ifndef CONFIG_UART1_DISABLE
+#    define TTYS1_DEV     g_uart1port     /* UART1 is ttyS1 */
+#  elif
+#    undef TTYS1_DEV                      /* No ttyS1 */
+#  endif
+#elif defined(CONFIG_UART1_SERIAL_CONSOLE)
+#  define CONSOLE_DEV     g_uart1port     /* UART1 is console */
+#  define TTYS0_DEV       g_uart1port     /* UART1 is ttyS0 */
+#  ifndef CONFIG_UART0_DISABLE
+#    define TTYS1_DEV     g_uart0port     /* UART0 is ttyS1 */
+#  elif
+#    undef TTYS1_DEV                      /* No ttyS1 */
+#  endif
+#elif !defined(CONFIG_UART0_DISABLE)
+#  undef  CONSOLE_DEV                     /* No console device */
+#  define TTYS0_DEV       g_uart1port     /* UART1 is ttyS0 */
+#  ifndef CONFIG_UART1_DISABLE
+#    define TTYS1_DEV     g_uart1port     /* UART1 is ttyS1 */
+#  elif
+#    undef TTYS1_DEV                      /* No ttyS1 */
+#  endif
+#elif !defined(CONFIG_UART1_DISABLE)
+#  undef  CONSOLE_DEV                     /* No console device */
+#  define TTYS0_DEV       g_uart1port     /* UART1 is ttyS0 */
+#  undef  TTYS1_DEV                       /* No ttyS1 */
+#else
+#  error "No valid TTY devices"
+#  undef  CONSOLE_DEV                     /* No console device */
+#  undef  TTYS0_DEV                       /* No ttyS0 */
+#  undef  TTYS1_DEV                       /* No ttyS1 */
+#endif
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+struct up_dev_s
+{
+  uint32  uartbase;  /* Base address of UART registers */
+  uint32  baud;      /* Configured baud */
+  uint32  im;        /* Saved IM value */
+  ubyte   irq;       /* IRQ associated with this UART */
+  ubyte   parity;    /* 0=none, 1=odd, 2=even */
+  ubyte   bits;      /* Number of bits (7 or 8) */
+  boolean stopbits2; /* TRUE: Configure with 2 stop bits instead of 1 */
+};
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+static int     up_setup(struct uart_dev_s *dev);
+static void    up_shutdown(struct uart_dev_s *dev);
+static int     up_attach(struct uart_dev_s *dev);
+static void    up_detach(struct uart_dev_s *dev);
+static int     up_interrupt(int irq, void *context);
+static int     up_ioctl(struct file *filep, int cmd, unsigned long arg);
+static int     up_receive(struct uart_dev_s *dev, uint32 *status);
+static void    up_rxint(struct uart_dev_s *dev, boolean enable);
+static boolean up_rxavailable(struct uart_dev_s *dev);
+static void    up_send(struct uart_dev_s *dev, int ch);
+static void    up_txint(struct uart_dev_s *dev, boolean enable);
+static boolean up_txready(struct uart_dev_s *dev);
+static boolean up_txempty(struct uart_dev_s *dev);
+
+/****************************************************************************
+ * Private Variables
+ ****************************************************************************/
+
+struct uart_ops_s g_uart_ops =
+{
+  .setup          = up_setup,
+  .shutdown       = up_shutdown,
+  .attach         = up_attach,
+  .detach         = up_detach,
+  .ioctl          = up_ioctl,
+  .receive        = up_receive,
+  .rxint          = up_rxint,
+  .rxavailable    = up_rxavailable,
+  .send           = up_send,
+  .txint          = up_txint,
+  .txready        = up_txready,
+  .txempty        = up_txempty,
+};
+
+/* I/O buffers */
+
+#ifndef CONFIG_UART0_DISABLE
+static char g_uart0rxbuffer[CONFIG_UART0_RXBUFSIZE];
+static char g_uart0txbuffer[CONFIG_UART0_TXBUFSIZE];
+#endif
+#ifndef CONFIG_UART1_DISABLE
+static char g_uart1rxbuffer[CONFIG_UART1_RXBUFSIZE];
+static char g_uart1txbuffer[CONFIG_UART1_TXBUFSIZE];
+#endif
+
+/* This describes the state of the LM3S6918 uart0 port. */
+
+#ifndef CONFIG_UART0_DISABLE
+static struct up_dev_s g_uart0priv =
+{
+  .uartbase       = LM3S_UART0_BASE,
+  .baud           = CONFIG_UART0_BAUD,
+  .irq            = LM3S_IRQ_UART0,
+  .parity         = CONFIG_UART0_PARITY,
+  .bits           = CONFIG_UART0_BITS,
+  .stopbits2      = CONFIG_UART0_2STOP,
+};
+
+static uart_dev_t g_uart0port =
+{
+  .recv     =
+  {
+    .size   = CONFIG_UART0_RXBUFSIZE,
+    .buffer = g_uart0rxbuffer,
+  },
+  .xmit     =
+  {
+    .size   = CONFIG_UART0_TXBUFSIZE,
+    .buffer = g_uart0txbuffer,
+  },
+  .ops      = &g_uart_ops,
+  .priv     = &g_uart0priv,
+};
+#endif
+
+/* This describes the state of the LM3S6918 uart1 port. */
+
+#ifndef CONFIG_UART1_DISABLE
+static struct up_dev_s g_uart1priv =
+{
+  .uartbase       = LM3S_UART1_BASE,
+  .baud           = CONFIG_UART1_BAUD,
+  .irq            = LM3S_IRQ_UART1,
+  .parity         = CONFIG_UART1_PARITY,
+  .bits           = CONFIG_UART1_BITS,
+  .stopbits2      = CONFIG_UART1_2STOP,
+};
+
+static uart_dev_t g_uart1port =
+{
+  .recv     =
+  {
+    .size   = CONFIG_UART1_RXBUFSIZE,
+    .buffer = g_uart1rxbuffer,
+  },
+  .xmit     =
+  {
+    .size   = CONFIG_UART1_TXBUFSIZE,
+    .buffer = g_uart1txbuffer,
+   },
+  .ops      = &g_uart_ops,
+  .priv     = &g_uart1priv,
+};
+#endif
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_serialin
+ ****************************************************************************/
+
+static inline uint32 up_serialin(struct up_dev_s *priv, int offset)
+{
+  return getreg32(priv->uartbase + offset);
+}
+
+/****************************************************************************
+ * Name: up_serialout
+ ****************************************************************************/
+
+static inline void up_serialout(struct up_dev_s *priv, int offset, uint32 value)
+{
+  putreg32(value, priv->uartbase + offset);
+}
+
+/****************************************************************************
+ * Name: up_disableuartint
+ ****************************************************************************/
+
+static inline void up_disableuartint(struct up_dev_s *priv, uint32 *im)
+{
+  /* Return the current interrupt mask value */
+
+  if (im)
+    {
+      *im = priv->im;
+    }
+
+  /* Disable all interrupts */
+
+  priv->im = 0;
+  up_serialout(priv, LM3S_UART_IM_OFFSET, 0);
+}
+
+/****************************************************************************
+ * Name: up_restoreuartint
+ ****************************************************************************/
+
+static inline void up_restoreuartint(struct up_dev_s *priv, uint32 im)
+{
+  priv->im = im;
+  up_serialout(priv, LM3S_UART_IM_OFFSET, im);
+}
+
+/****************************************************************************
+ * Name: up_waittxnotfull
+ ****************************************************************************/
+
+#ifdef HAVE_CONSOLE
+static inline void up_waittxnotfull(struct up_dev_s *priv)
+{
+  int tmp;
+
+  /* Limit how long we will wait for the TX available condition */
+
+  for (tmp = 1000 ; tmp > 0 ; tmp--)
+    {
+      /* Check Tx FIFO is full */
+
+      if ((up_serialin(priv, LM3S_UART_FR_OFFSET) & UART_FR_TXFF) == 0)
+        {
+          /* The Tx FIFO is not full... return */
+
+          break;
+        }
+    }
+
+  /* If we get here, then the wait has timed out and the Tx FIFO remains
+   * full.
+   */
+}
+#endif
+
+/****************************************************************************
+ * Name: up_setup
+ *
+ * Description:
+ *   Configure the UART baud, bits, parity, fifos, etc. This
+ *   method is called the first time that the serial port is
+ *   opened.
+ *
+ ****************************************************************************/
+
+static int up_setup(struct uart_dev_s *dev)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  uint32 lcrh;
+  uint32 ctl;
+#ifndef CONFIG_SUPPRESS_UART_CONFIG
+  uint32 den;
+  uint32 brdi;
+  uint32 remainder;
+  uint32 divfrac;
+
+  /* Note:  The logic here depends on the fact that that the UART module
+   * was enabled and the GPIOs were configured in up_lowsetup().
+   */
+
+  /* Disable the UART by clearing the UARTEN bit in the UART CTL register */
+
+  ctl = getreg32(LM3S_CONSOLE_BASE+LM3S_UART_CTL_OFFSET);
+  ctl &= ~UART_CTL_UARTEN;
+  putreg32(ctl, LM3S_CONSOLE_BASE+LM3S_UART_CTL_OFFSET);
+
+  /* Calculate BAUD rate from the SYS clock:
+   *
+   * "The baud-rate divisor is a 22-bit number consisting of a 16-bit integer
+   *  and a 6-bit fractional part. The number formed by these two values is
+   *  used by the baud-rate generator to determine the bit period. Having a
+   *  fractional baud-rate divider allows the UART to generate all the standard
+   *  baud rates.
+   *
+   * "The 16-bit integer is loaded through the UART Integer Baud-Rate Divisor
+   *  (UARTIBRD) register ... and the 6-bit fractional part is loaded with the
+   *  UART Fractional Baud-Rate Divisor (UARTFBRD) register... The baud-rate
+   *  divisor (BRD) has the following relationship to the system clock (where
+   *  BRDI is the integer part of the BRD and BRDF is the fractional part,
+   *  separated by a decimal place.):
+   *
+   *    "BRD = BRDI + BRDF = UARTSysClk / (16 * Baud Rate)
+   *
+   * "where UARTSysClk is the system clock connected to the UART. The 6-bit
+   *  fractional number (that is to be loaded into the DIVFRAC bit field in the
+   *  UARTFBRD register) can be calculated by taking the fractional part of the
+   *  baud-rate divisor, multiplying it by 64, and adding 0.5 to account for
+   *  rounding errors:
+   *
+   *    "UARTFBRD[DIVFRAC] = integer(BRDF * 64 + 0.5)
+   *
+   * "The UART generates an internal baud-rate reference clock at 16x the baud-
+   *  rate (referred to as Baud16). This reference clock is divided by 16 to
+   *  generate the transmit clock, and is used for error detection during receive
+   *  operations.
+   *
+   * "Along with the UART Line Control, High Byte (UARTLCRH) register ..., the
+   *  UARTIBRD and UARTFBRD registers form an internal 30-bit register. This
+   *  internal register is only updated when a write operation to UARTLCRH is
+   *  performed, so any changes to the baud-rate divisor must be followed by a
+   *  write to the UARTLCRH register for the changes to take effect. ..."
+   */
+
+  den       = priv->baud << 16;
+  brdi      = SYSCLK_FREQUENCY / den;
+  remainder = priv->baud - den * brdi
+  divfrac   = ((remainder << 6) + (den >> 1)) / den;
+
+  up_serialout(priv, LM3S_UART_IBRD_OFFSET, brdi);
+  up_serialout(priv, LM3S_UART_FBRD_OFFSET, divfrac);
+
+  /* Set up the LCRH register */
+
+  lcrh = 0;
+  switch (priv->bits)
+    {
+      case 5:
+        lcrh |= UART_LCRH_WLEN_5BITS;
+        break;
+      case 6:
+        lcrh |= UART_LCRH_WLEN_6BITS;
+        break;
+      case 7:
+        lcrh |= UART_LCRH_WLEN_7BITS;
+        break;
+      case 8:
+      default:
+        lcrh |= UART_LCRH_WLEN_8BITS;
+        break;
+    }
+
+  switch (priv->parity)
+    {
+      case 0:
+      default:
+        break;
+      case 1:
+        lcrh |= UART_LCRH_PEN;
+        break;
+      case 2:
+        lcrh |= UART_LCRH_PEN|UART_LCRH_EPS;
+        break;
+    }
+
+  if (priv->stopbits2)
+    {
+      lcrh |= UART_LCRH_STP2;
+    }
+
+  up_serialout(priv, LM3S_UART_LCRH_OFFSET, lcrh);
+#endif
+
+  /* Set the UART to interrupt whenever the TX FIFO is almost empty or when
+   * any character is received.
+   */
+
+  up_serialout(priv, LM3S_UART_IFLS_OFFSET, UART_IFLS_TXIFLSEL_18th|UART_IFLS_RXIFLSEL_18th);
+
+  /* Flush the Rx and Tx FIFOs -- How do you do that?*/
+
+  /* Enable Rx interrupts from the UART except for Tx interrupts.  We don't want
+   * Tx interrupts until we have something to send.  We will check for serial
+   * errors as part of Rx interrupt processing (no interrupts will be received
+   * yet because the interrupt is still disabled at the interrupt controller.
+   */
+
+  serial_out(priv, LM3S_UART_IM_OFFSET, UART_IM_RXIM|UART_IM_RTIM);
+
+  /* Enable the FIFOs */
+
+#ifndef CONFIG_SUPPRESS_UART_CONFIG
+  lrch = up_serialin(priv, LM3S_UART_LCRH_OFFSET);
+#endif
+  lcrh |= UART_LCRH_FEN;
+  serial_out(priv, LM3S_UART_LCRH_OFFSET, lcrh);
+
+  /* Enable Rx, Tx, and the UART */
+
+#ifndef CONFIG_SUPPRESS_UART_CONFIG
+  ctl = up_serialin(priv, LM3S_UART_CTL_OFFSET);
+#endif
+  ctl |= (UART_CTL_UARTEN|UART_CTL_TXE|UART_CTL_RXE);
+  up_serialout(priv, LM3S_UART_CTL_OFFSET, ctl);
+
+  /* Set up the cache IM value */
+
+  priv->im = up_serialin(priv, LM3S_UART_IM_OFFSET);
+  return OK;
+}
+
+/****************************************************************************
+ * Name: up_shutdown
+ *
+ * Description:
+ *   Disable the UART.  This method is called when the serial
+ *   port is closed
+ *
+ ****************************************************************************/
+
+static void up_shutdown(struct uart_dev_s *dev)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  up_disableuartint(priv, NULL);
+}
+
+/****************************************************************************
+ * Name: up_attach
+ *
+ * Description:
+ *   Configure the UART to operation in interrupt driven mode.  This method is
+ *   called when the serial port is opened.  Normally, this is just after the
+ *   the setup() method is called, however, the serial console may operate in
+ *   a non-interrupt driven mode during the boot phase.
+ *
+ *   RX and TX interrupts are not enabled when by the attach method (unless the
+ *   hardware supports multiple levels of interrupt enabling).  The RX and TX
+ *   interrupts are not enabled until the txint() and rxint() methods are called.
+ *
+ ****************************************************************************/
+
+static int up_attach(struct uart_dev_s *dev)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  int ret;
+
+  /* Attach and enable the IRQ */
+
+  ret = irq_attach(priv->irq, up_interrupt);
+  if (ret == OK)
+    {
+       /* Enable the interrupt (RX and TX interrupts are still disabled
+        * in the UART
+        */
+
+       up_enable_irq(priv->irq);
+    }
+  return ret;
+}
+
+/****************************************************************************
+ * Name: up_detach
+ *
+ * Description:
+ *   Detach UART interrupts.  This method is called when the serial port is
+ *   closed normally just before the shutdown method is called.  The exception is
+ *   the serial console which is never shutdown.
+ *
+ ****************************************************************************/
+
+static void up_detach(struct uart_dev_s *dev)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  up_disable_irq(priv->irq);
+  irq_detach(priv->irq);
+}
+
+/****************************************************************************
+ * Name: up_interrupt
+ *
+ * Description:
+ *   This is the UART interrupt handler.  It will be invoked
+ *   when an interrupt received on the 'irq'  It should call
+ *   uart_transmitchars or uart_receivechar to perform the
+ *   appropriate data transfers.  The interrupt handling logic\
+ *   must be able to map the 'irq' number into the approprite
+ *   uart_dev_s structure in order to call these functions.
+ *
+ ****************************************************************************/
+
+static int up_interrupt(int irq, void *context)
+{
+  struct uart_dev_s *dev = NULL;
+  struct up_dev_s   *priv;
+  uint32             mis;
+  int                passes;
+  boolean            handled;
+
+#ifndef CONFIG_UART0_DISABLE
+  if (g_uart0priv.irq == irq)
+    {
+      dev = &g_uart0port;
+    }
+  else
+#endif
+#ifndef CONFIG_UART1_DISABLE
+  if (g_uart1priv.irq == irq)
+    {
+      dev = &g_uart1port;
+    }
+  else
+#endif
+    {
+      PANIC(OSERR_INTERNAL);
+    }
+  priv = (struct up_dev_s*)dev->priv;
+
+  /* Loop until there are no characters to be transferred or,
+   * until we have been looping for a long time.
+   */
+
+  for (passes = 0; passes < 256 && handled; passes++)
+    {
+      handled = FALSE;
+
+      /* Get the masked UART status and clear the pending interrupts. */
+
+       mis = up_serialin(priv, LM3S_UART_MIS_OFFSET);
+       up_serialout(priv, LM3S_UART_ICR_OFFSET, mis);
+
+      /* Handle incoming, receive bytes (with or without timeout) */
+
+      if ((mis & (UART_MIS_RXMIS|UART_MIS_RTMIS)) != 0)
+        {
+           /* Rx buffer not empty ... process incoming bytes */
+
+           uart_recvchars(dev);
+           handled = TRUE;
+        }
+
+      /* Handle outgoing, transmit bytes */
+
+      if ((mis & UART_MIS_TXMIS) == 0)
+        {
+           /* Tx FIFO not full ... process outgoing bytes */
+
+           uart_xmitchars(dev);
+           handled = TRUE;
+        }
+    }
+    return OK;
+}
+
+/****************************************************************************
+ * Name: up_ioctl
+ *
+ * Description:
+ *   All ioctl calls will be routed through this method
+ *
+ ****************************************************************************/
+
+static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
+{
+  struct inode      *inode = filep->f_inode;
+  struct uart_dev_s *dev   = inode->i_private;
+  struct up_dev_s   *priv  = (struct up_dev_s*)dev->priv;
+  int                ret    = OK;
+
+  switch (cmd)
+    {
+    case TIOCSERGSTRUCT:
+      {
+         struct up_dev_s *user = (struct up_dev_s*)arg;
+         if (!user)
+           {
+             *get_errno_ptr() = EINVAL;
+             ret = ERROR;
+           }
+         else
+           {
+             memcpy(user, dev, sizeof(struct up_dev_s));
+           }
+       }
+       break;
+
+    default:
+      *get_errno_ptr() = ENOTTY;
+      ret = ERROR;
+      break;
+    }
+
+  return ret;
+}
+
+/****************************************************************************
+ * Name: up_receive
+ *
+ * Description:
+ *   Called (usually) from the interrupt level to receive one
+ *   character from the UART.  Error bits associated with the
+ *   receipt are provided in the the return 'status'.
+ *
+ ****************************************************************************/
+
+static int up_receive(struct uart_dev_s *dev, uint32 *status)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  uint32 rxd;
+
+  /* Get the Rx byte + 4 bits of error information.  Return those in status */
+
+  rxd     = up_serialin(priv, LM3S_UART_DR_OFFSET);
+  *status = rxd;
+
+  /* The lower 8bits of the Rx data is the actual recevied byte */
+
+  return rxd & 0xff;
+}
+
+/****************************************************************************
+ * Name: up_rxint
+ *
+ * Description:
+ *   Call to enable or disable RX interrupts
+ *
+ ****************************************************************************/
+
+static void up_rxint(struct uart_dev_s *dev, boolean enable)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  if (enable)
+    {
+      /* Receive an interrupt when their is anything in the Rx FIFO (or an Rx
+       * timeout occurs.
+       */
+
+#ifndef CONFIG_SUPPRESS_SERIAL_INTS
+      priv->im |= (UART_IM_RXIM|UART_IM_RTIM);
+#endif
+    }
+  else
+    {
+      priv->im &= ~(UART_IM_RXIM|UART_IM_RTIM);
+    }
+  up_serialout(priv, LM3S_UART_IM_OFFSET, priv->im);
+}
+
+/****************************************************************************
+ * Name: up_rxavailable
+ *
+ * Description:
+ *   Return TRUE if the receive fifo is not empty
+ *
+ ****************************************************************************/
+
+static boolean up_rxavailable(struct uart_dev_s *dev)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  return ((up_serialin(priv, LM3S_UART_FR_OFFSET) & UART_FR_RXFE) == 0);
+}
+
+/****************************************************************************
+ * Name: up_send
+ *
+ * Description:
+ *   This method will send one byte on the UART
+ *
+ ****************************************************************************/
+
+static void up_send(struct uart_dev_s *dev, int ch)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  up_serialout(priv, LM3S_UART_DR_OFFSET, (uint32)ch);
+}
+
+/****************************************************************************
+ * Name: up_txint
+ *
+ * Description:
+ *   Call to enable or disable TX interrupts
+ *
+ ****************************************************************************/
+
+static void up_txint(struct uart_dev_s *dev, boolean enable)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  if (enable)
+    {
+      /* Set to receive an interrupt when the TX fifo is half emptied */
+#ifndef CONFIG_SUPPRESS_SERIAL_INTS
+      priv->im |= UART_IM_TXIM;
+#endif
+    }
+  else
+    {
+      priv->im &= ~UART_IM_TXIM;
+    }
+  up_serialout(priv, LM3S_UART_IM_OFFSET, priv->im);
+}
+
+/****************************************************************************
+ * Name: up_txready
+ *
+ * Description:
+ *   Return TRUE if the tranmsit fifo is not full
+ *
+ ****************************************************************************/
+
+static boolean up_txready(struct uart_dev_s *dev)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  return ((up_serialin(priv, LM3S_UART_FR_OFFSET) & UART_FR_TXFF) == 0);
+}
+
+/****************************************************************************
+ * Name: up_txempty
+ *
+ * Description:
+ *   Return TRUE if the transmit fifo is empty
+ *
+ ****************************************************************************/
+
+static boolean up_txempty(struct uart_dev_s *dev)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  return ((up_serialin(priv, LM3S_UART_FR_OFFSET) & UART_FR_TXFE) != 0);
+}
+
+/****************************************************************************
+ * Public Funtions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_serialinit
+ *
+ * Description:
+ *   Performs the low level UART initialization early in 
+ *   debug so that the serial console will be available
+ *   during bootup.  This must be called before up_serialinit.
+ *
+ ****************************************************************************/
+
+void up_earlyserialinit(void)
+{
+  /* NOTE:  All GPIO configuration for the UARTs was performed in
+   * up_lowsetup
+   */
+
+  /* Disable all UARTS */
+
+  up_disableuartint(TTYS0_DEV.priv, NULL);
+#ifdef TTYS1_DEV
+  up_disableuartint(TTYS1_DEV.priv, NULL);
+#endif
+
+  /* Configuration whichever one is the console */
+
+#ifdef HAVE_CONSOLE
+  CONSOLE_DEV.isconsole = TRUE;
+  up_setup(&CONSOLE_DEV);
+#endif
+}
+
+/****************************************************************************
+ * Name: up_serialinit
+ *
+ * Description:
+ *   Register serial console and serial ports.  This assumes
+ *   that up_earlyserialinit was called previously.
+ *
+ ****************************************************************************/
+
+void up_serialinit(void)
+{
+  /* Register the console */
+
+#ifdef HAVE_CONSOLE
+  (void)uart_register("/dev/console", &CONSOLE_DEV);
+#endif
+
+  /* Register all UARTs */
+
+  (void)uart_register("/dev/ttyS0", &TTYS0_DEV);
+#ifdef TTYS1_DEV
+  (void)uart_register("/dev/ttyS1", &TTYS1_DEV);
+#endif
+}
+
+/****************************************************************************
+ * Name: up_putc
+ *
+ * Description:
+ *   Provide priority, low-level access to support OS debug  writes
+ *
+ ****************************************************************************/
+
+int up_putc(int ch)
+{
+#ifdef HAVE_CONSOLE
+  struct up_dev_s *priv = (struct up_dev_s*)CONSOLE_DEV.priv;
+  ubyte  im;
+
+  up_disableuartint(priv, &im);
+  up_waittxnotfull(priv);
+  up_serialout(priv, LM3S_UART_DR_OFFSET, (uint32)ch);
+
+  /* Check for LF */
+
+  if (ch == '\n')
+    {
+      /* Add CR */
+
+      up_waittxnotfull(priv);
+      up_serialout(priv, LM3S_UART_DR_OFFSET, (uint32)'\r');
+    }
+
+  up_waittxnotfull(priv);
+  up_restoreuartint(priv, im);
+#endif
+  return ch;
+}
+
+#else /* CONFIG_USE_SERIALDRIVER */
+
+/****************************************************************************
+ * Name: up_putc
+ *
+ * Description:
+ *   Provide priority, low-level access to support OS debug writes
+ *
+ ****************************************************************************/
+
+int up_putc(int ch)
+{
+#ifdef HAVE_CONSOLE
+  /* Check for LF */
+
+  if (ch == '\n')
+    {
+      /* Add CR */
+
+      up_lowputc('\r');
+    }
+
+  up_lowputc(ch);
+#endif
+  return ch;
+}
+
+#endif /* CONFIG_USE_SERIALDRIVER */
diff --git a/nuttx/arch/arm/src/lm3s/lm3s_timerisr.c b/nuttx/arch/arm/src/lm3s/lm3s_timerisr.c
new file mode 100644
index 000000000..e4950d042
--- /dev/null
+++ b/nuttx/arch/arm/src/lm3s/lm3s_timerisr.c
@@ -0,0 +1,140 @@
+/****************************************************************************
+ * arch/arm/src/lm3s/lm3s_timerisr.c
+ *
+ *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include <time.h>
+#include <debug.h>
+#include <nuttx/arch.h>
+#include <arch/board/board.h>
+
+#include "clock_internal.h"
+#include "up_internal.h"
+#include "up_arch.h"
+
+#include "chip.h"
+
+/****************************************************************************
+ * Definitions
+ ****************************************************************************/
+
+/* The desired timer interrupt frequency is provided by the definition
+ * CLK_TCK (see include/time.h).  CLK_TCK defines the desired number of
+ * system clock ticks per second.  That value is a user configurable setting
+ * that defaults to 100 (100 ticks per second = 10 MS interval).
+ *
+ * The timer counts at the rate SYSCLK_FREQUENCY as defined in the board.h
+ * header file.
+ */
+
+#define SYSTICK_RELOAD ((SYSCLK_FREQUENCY / CLK_TCK) - 1)
+
+/* The size of the reload field is 24 bits.  Verify taht the reload value
+ * will fit in the reload register.
+ */
+
+#if SYSTICK_RELOAD > 0x00ffffff
+#  error SYSTICK_RELOAD exceeds the range of the RELOAD register
+#endif
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Global Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Function:  up_timerisr
+ *
+ * Description:
+ *   The timer ISR will perform a variety of services for various portions
+ *   of the systems.
+ *
+ ****************************************************************************/
+
+int up_timerisr(int irq, uint32 *regs)
+{
+   /* Process timer interrupt */
+
+   sched_process_timer();
+   return 0;
+}
+
+/****************************************************************************
+ * Function:  up_timerinit
+ *
+ * Description:
+ *   This function is called during start-up to initialize
+ *   the timer interrupt.
+ *
+ ****************************************************************************/
+
+void up_timerinit(void)
+{
+  uint32 regval;
+
+  /* Set the SysTick interrupt to the default priority */
+
+  regval = getreg32(NVIC_SYSH12_15_PRIORITY);
+  regval &= ~NVIC_SYSH_PRIORITY_PR15_MASK;
+  regval |= (NVIC_SYSH_PRIORITY_DEFAULT << NVIC_SYSH_PRIORITY_PR15_SHIFT);
+  putreg32(regval, NVIC_SYSH12_15_PRIORITY);
+
+  /* Configure SysTick to interrupt at the requested rate */
+
+  putreg32(SYSTICK_RELOAD, NVIC_SYSTICK_RELOAD);
+
+  /* Attach the timer interrupt vector */
+
+  (void)irq_attach(LMSB_IRQ_SYSTICK, (xcpt_t)up_timerisr);
+
+  /* Enable SysTick interrupts */
+
+  putreg32((NVIC_SYSTICK_CTRL_CLKSOURCE|NVIC_SYSTICK_CTRL_TICKINT|NVIC_SYSTICK_CTRL_ENABLE), NVIC_SYSTICK_CTRL);
+
+  /* And enable the timer interrupt */
+
+  up_enable_irq(LMSB_IRQ_SYSTICK);
+}