Clean up addressing

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2491 42af7a65-404d-4744-a932-0658087f49c3

5 files changed, 216 insertions, 115 deletions

diff --git a/nuttx/arch/arm/src/sam3u/sam3u_eefc.h b/nuttx/arch/arm/src/sam3u/sam3u_eefc.h
index b0d1a6c31..ed88a0134 100755
--- a/nuttx/arch/arm/src/sam3u/sam3u_eefc.h
+++ b/nuttx/arch/arm/src/sam3u/sam3u_eefc.h
@@ -58,10 +58,10 @@
 

 /* EEFC register adresses ***************************************************************/

 

-#define SAM3U_EEFC_FMR(n)              (SAM3U_EEFC_BASE(n)+SAM3U_EEFC_FMR_OFFSET)

-#define SAM3U_EEFC_FCR(n)              (SAM3U_EEFC_BASE(n)+SAM3U_EEFC_FCR_OFFSET)

-#define SAM3U_EEFC_FSR(n)              (SAM3U_EEFC_BASE(n)+SAM3U_EEFC_FSR_OFFSET)

-#define SAM3U_EEFC_FRR(n)              (SAM3U_EEFC_BASE(n)+SAM3U_EEFC_FRR_OFFSET)

+#define SAM3U_EEFC_FMR(n)              (SAM3U_EEFCN_BASE(n)+SAM3U_EEFC_FMR_OFFSET)

+#define SAM3U_EEFC_FCR(n)              (SAM3U_EEFCN_BASE(n)+SAM3U_EEFC_FCR_OFFSET)

+#define SAM3U_EEFC_FSR(n)              (SAM3U_EEFCN_BASE(n)+SAM3U_EEFC_FSR_OFFSET)

+#define SAM3U_EEFC_FRR(n)              (SAM3U_EEFCN_BASE(n)+SAM3U_EEFC_FRR_OFFSET)

 

 #define SAM3U_EEFC0_FMR                (SAM3U_EEFC0_BASE+SAM3U_EEFC_FMR_OFFSET)

 #define SAM3U_EEFC0_FCR                (SAM3U_EEFC0_BASE+SAM3U_EEFC_FCR_OFFSET)

diff --git a/nuttx/arch/arm/src/sam3u/sam3u_memorymap.h b/nuttx/arch/arm/src/sam3u/sam3u_memorymap.h
index 91e50f04f..723c78652 100755
--- a/nuttx/arch/arm/src/sam3u/sam3u_memorymap.h
+++ b/nuttx/arch/arm/src/sam3u/sam3u_memorymap.h
@@ -47,82 +47,88 @@
  * Pre-processor Definitions

  ************************************************************************************************/

 

-#define   SAM3U_CODE_BASE       0x00000000 /* 0x00000000-0x1fffffff: Code space */

-#  define SAM3U_BOOTMEMORY_BASE 0x00000000 /* 0x00000000-0x0007ffff:   Boot Memory */

-#  define SAM3U_INTFLASH0_BASE  0x00080000 /* 0x00080000-0x000fffff:   Internal FLASH 0 */

-#  define SAM3U_INTFLASH1_BASE  0x00100000 /* 0x00100000-0x0017ffff:   Internal FLASH 1 */

-#  define SAM3U_INTROM_BASE     0x00180000 /* 0x00180000-0x001fffff:   Internal ROM */

-                                           /* 0x00200000-0x1fffffff:   Reserved */

-#define   SAM3U_INTSRAM_BASE    0x20000000 /* 0x20000000-0x3fffffff: Internal SRAM */

-#  define SAM3U_INTSRAM0_BASE   0x20000000 /* 0x20000000-0x2007ffff:   SRAM0 */

-#  define SAM3U_INTSRAM1_BASE   0x20080000 /* 0x20080000-0x200fffff:   SRAM1 */

-#  define SAM3U_NFCSRAM_BASE    0x20100000 /* 0x20100000-0x207fffff:   NAND FLASH controller (SRAM) */

-#  define SAM3U_UDPHPSDMS_BASE  0x20180000 /* 0x20180000-0x201fffff:   USB Device High Speed (DMA) */

-                                           /* 0x20200000-0x2fffffff:   Undefined */

-#  define SAM3U_BBSRAM_BASE     0x22000000 /* 0x22000000-0x23ffffff:   32Mb bit-band alias */

-                                           /* 0x24000000-0x3fffffff:   Undefined */

-#define SAM3U_PERIPHERALS_BASE  0x40000000 /* 0x40000000-0x5fffffff: Peripherals */

-#  define SAM3U_MCI_BASE        0x40000000 /* 0x40000000-0x400003ff:   High Speed Multimedia Card Interface */

-#  define SAM3U_SSC_BASE        0x40004000 /* 0x40004000-0x40007fff:   Synchronous Serial Controller */

-#  define SAM3U_SPI_BASE        0x40008000 /* 0x40008000-0x4000bfff:   Serial Peripheral Interface */

-                                           /* 0x4000c000-0x4007ffff:   Reserved */

-#  define SAM3U_TC_BASE(n)      (0x40080000+((n)<<6))

-#  define SAM3U_TC0_BASE        0x40080000 /* 0x40080000-0x4008003f:   Timer Counter 0 */

-#  define SAM3U_TC1_BASE        0x40080040 /* 0x40080040-0x4008007f:   Timer Counter 1 */

-#  define SAM3U_TC2_BASE        0x40080080 /* 0x40080080-0x400800bf:   Timer Counter 2 */

-#  define SAM3U_TWI_BASE(n)     (0x40084000+((n)<<14))

-#  define SAM3U_TWI0_BASE       0x40084000 /* 0x40084000-0x40087fff:   Two-Wire Interface 0 */

-#  define SAM3U_TWI1_BASE       0x40088000 /* 0x40088000-0x4008bfff:   Two-Wire Interface 1 */

-#  define SAM3U_PWM_BASE        0x4008c000 /* 0x4008c000-0x4008ffff:   Pulse Width Modulation Controller */

-#  define SAM3U_USART_BASE(n)   (0x40090000+((n)<<14))

-#  define SAM3U_USART0_BASE     0x40090000 /* 0x40090000-0x40093fff:   USART0 */

-#  define SAM3U_USART1_BASE     0x40094000 /* 0x40094000-0x40097fff:   USART1 */

-#  define SAM3U_USART2_BASE     0x40098000 /* 0x40098000-0x4009bfff:   USART2 */

-#  define SAM3U_USART3_BASE     0x4009c000 /* 0x4009c000-0x4009ffff:   USART3 */

-                                           /* 0x400a0000-0x400a3fff:   Reserved */

-#  define SAM3U_UDPHPS_BASE     0x400a4000 /* 0x400a4000-0x400a7fff:   USB Device High Speed */

-#  define SAM3U_ADC12B_BASE     0x400a8000 /* 0x400a8000-0x400abfff:   12-bit ADC Controller */

-#  define SAM3U_ADC_BASE        0x400ac000 /* 0x400ac000-0x400affff:   10-bit ADC Controller */

-#  define SAM3U_DMAC_BASE       0x400b0000 /* 0x400b0000-0x400b3fff:   DMA controller */

-                                           /* 0x400b4000-0x400dffff:   Reserved */

-#  define SAM3U_SYSCTRLR_BASE   0x400e0000 /* 0x400e0000-0x400e25ff:   System controller */

-                                           /* 0x400e2600-0x400fffff:   Reserved */

-                                           /* 0x40100000-0x41ffffff:   Reserved */

-#  define SAM3U_BBPERIPH__BASE  0x42000000 /* 0x42000000-0x43ffffff:   32Mb bit-band alias */

-                                           /* 0x44000000-0x5fffffff:   Reserved */

-#define   SAM3U_EXTSRAM_BASE    0x60000000 /* 0x60000000-0x9fffffff: External SRAM */

-#  define SAM3U_EXTCS_BASE(n)   (0x60000000*((n)<<24))

-#  define SAM3U_EXTCS0_BASE     0x60000000 /* 0x60000000-0x60ffffff:   Chip select 0 */

-#  define SAM3U_EXTCS1_BASE     0x61000000 /* 0x61000000-0x601fffff:   Chip select 1 */

-#  define SAM3U_EXTCS2_BASE     0x62000000 /* 0x62000000-0x62ffffff:   Chip select 2 */

-#  define SAM3U_EXTCS3_BASE     0x63000000 /* 0x63000000-0x63ffffff:   Chip select 3 */

-                                           /* 0x64000000-0x67ffffff:   Reserved */

-#  define SAM3U_NFC_BASE        0x68000000 /* 0x68000000-0x68ffffff:   NAND FLASH controller */

-                                           /* 0x69000000-0x9fffffff:   Reserved */

-                                           /* 0xa0000000-0xdfffffff:   Reserved */

-#define   SAM3U_SYSTEM_BASE     0xe0000000 /* 0xe0000000-0xffffffff: System */

+#define   SAM3U_CODE_BASE        0x00000000 /* 0x00000000-0x1fffffff: Code space */

+#  define SAM3U_BOOTMEMORY_BASE  0x00000000 /* 0x00000000-0x0007ffff:   Boot Memory */

+#  define SAM3U_INTFLASH0_BASE   0x00080000 /* 0x00080000-0x000fffff:   Internal FLASH 0 */

+#  define SAM3U_INTFLASH1_BASE   0x00100000 /* 0x00100000-0x0017ffff:   Internal FLASH 1 */

+#  define SAM3U_INTROM_BASE      0x00180000 /* 0x00180000-0x001fffff:   Internal ROM */

+                                            /* 0x00200000-0x1fffffff:   Reserved */

+#define   SAM3U_INTSRAM_BASE     0x20000000 /* 0x20000000-0x3fffffff: Internal SRAM */

+#  define SAM3U_INTSRAM0_BASE    0x20000000 /* 0x20000000-0x2007ffff:   SRAM0 */

+#  define SAM3U_INTSRAM1_BASE    0x20080000 /* 0x20080000-0x200fffff:   SRAM1 */

+#  define SAM3U_NFCSRAM_BASE     0x20100000 /* 0x20100000-0x207fffff:   NAND FLASH controller (SRAM) */

+#  define SAM3U_UDPHPSDMS_BASE   0x20180000 /* 0x20180000-0x201fffff:   USB Device High Speed (DMA) */

+                                            /* 0x20200000-0x2fffffff:   Undefined */

+#  define SAM3U_BBSRAM_BASE      0x22000000 /* 0x22000000-0x23ffffff:   32Mb bit-band alias */

+                                            /* 0x24000000-0x3fffffff:   Undefined */

+#define SAM3U_PERIPHERALS_BASE   0x40000000 /* 0x40000000-0x5fffffff: Peripherals */

+#  define SAM3U_MCI_BASE         0x40000000 /* 0x40000000-0x400003ff:   High Speed Multimedia Card Interface */

+#  define SAM3U_SSC_BASE         0x40004000 /* 0x40004000-0x40007fff:   Synchronous Serial Controller */

+#  define SAM3U_SPI_BASE         0x40008000 /* 0x40008000-0x4000bfff:   Serial Peripheral Interface */

+                                            /* 0x4000c000-0x4007ffff:   Reserved */

+#  define SAM3U_TC_BASE          0x40080000 /* 0x40080000-0x40083fff:   Timer Counters */

+#    define SAM3U_TCN_BASE(n)    (0x40080000+((n)<<6))

+#    define SAM3U_TC0_BASE       0x40080000 /* 0x40080000-0x4008003f:     Timer Counter 0 */

+#    define SAM3U_TC1_BASE       0x40080040 /* 0x40080040-0x4008007f:     Timer Counter 1 */

+#    define SAM3U_TC2_BASE       0x40080080 /* 0x40080080-0x400800bf:     Timer Counter 2 */

+#  define SAM3U_TWI_BASE         0x40084000 /* 0x40084000-0x4008ffff:   Two-Wire Interface */

+#    define SAM3U_TWIN_BASE(n)   (0x40084000+((n)<<14))

+#    define SAM3U_TWI0_BASE      0x40084000 /* 0x40084000-0x40087fff:     Two-Wire Interface 0 */

+#    define SAM3U_TWI1_BASE      0x40088000 /* 0x40088000-0x4008bfff:     Two-Wire Interface 1 */

+#  define SAM3U_PWM_BASE         0x4008c000 /* 0x4008c000-0x4008ffff:   Pulse Width Modulation Controller */

+#  define SAM3U_USART_BASE       0x40090000 /* 0x40090000-0x4009ffff:   USART */

+#    define SAM3U_USARTN_BASE(n) (0x40090000+((n)<<14))

+#    define SAM3U_USART0_BASE    0x40090000 /* 0x40090000-0x40093fff:     USART0 */

+#    define SAM3U_USART1_BASE    0x40094000 /* 0x40094000-0x40097fff:     USART1 */

+#    define SAM3U_USART2_BASE    0x40098000 /* 0x40098000-0x4009bfff:     USART2 */

+#    define SAM3U_USART3_BASE    0x4009c000 /* 0x4009c000-0x4009ffff:     USART3 */

+                                            /* 0x400a0000-0x400a3fff:   Reserved */

+#  define SAM3U_UDPHPS_BASE      0x400a4000 /* 0x400a4000-0x400a7fff:   USB Device High Speed */

+#  define SAM3U_ADC12B_BASE      0x400a8000 /* 0x400a8000-0x400abfff:   12-bit ADC Controller */

+#  define SAM3U_ADC_BASE         0x400ac000 /* 0x400ac000-0x400affff:   10-bit ADC Controller */

+#  define SAM3U_DMAC_BASE        0x400b0000 /* 0x400b0000-0x400b3fff:   DMA controller */

+                                            /* 0x400b4000-0x400dffff:   Reserved */

+#  define SAM3U_SYSCTRLR_BASE    0x400e0000 /* 0x400e0000-0x400e25ff:   System controller */

+                                            /* 0x400e2600-0x400fffff:   Reserved */

+                                            /* 0x40100000-0x41ffffff:   Reserved */

+#  define SAM3U_BBPERIPH__BASE   0x42000000 /* 0x42000000-0x43ffffff:   32Mb bit-band alias */

+                                            /* 0x44000000-0x5fffffff:   Reserved */

+#define   SAM3U_EXTSRAM_BASE     0x60000000 /* 0x60000000-0x9fffffff: External SRAM */

+#  define SAM3U_EXTCS_BASE       0x60000000 /* 0x60000000-0x63ffffff:   Chip selects */

+#    define SAM3U_EXTCSN_BASE(n) (0x60000000*((n)<<24))

+#    define SAM3U_EXTCS0_BASE    0x60000000 /* 0x60000000-0x60ffffff:     Chip select 0 */

+#    define SAM3U_EXTCS1_BASE    0x61000000 /* 0x61000000-0x601fffff:     Chip select 1 */

+#    define SAM3U_EXTCS2_BASE    0x62000000 /* 0x62000000-0x62ffffff:     Chip select 2 */

+#    define SAM3U_EXTCS3_BASE    0x63000000 /* 0x63000000-0x63ffffff:     Chip select 3 */

+                                            /* 0x64000000-0x67ffffff:   Reserved */

+#  define SAM3U_NFC_BASE         0x68000000 /* 0x68000000-0x68ffffff:   NAND FLASH controller */

+                                            /* 0x69000000-0x9fffffff:   Reserved */

+                                            /* 0xa0000000-0xdfffffff:   Reserved */

+#define   SAM3U_SYSTEM_BASE      0xe0000000 /* 0xe0000000-0xffffffff: System */

 

 /* System Controller Register Blocks:  0x400e0000-0x4007ffff */

 

-#define SAM3U_SMC_BASE          0x400e0000 /* 0x400e0000-0x400e01ff: Static Memory Controller */

-#define SAM3U_MATRIX_BASE       0x400e0200 /* 0x400e0200-0x400e03ff: MATRIX */

-#define SAM3U_PMC_BASE          0x400e0400 /* 0x400e0400-0x400e05ff: Power Management Controller */

-#define SAM3U_UART_BASE         0x400e0600 /* 0x400e0600-0x400e073f: UART */

-#define SAM3U_CHIPID_BASE       0x400e0740 /* 0x400e0740-0x400e07ff: CHIP ID */

-#define SAM3U_EEFC_BASE(n)      (0x400e0800+((n)<<9))

-#define SAM3U_EEFC0_BASE        0x400e0800 /* 0x400e0800-0x400e09ff: Enhanced Embedded Flash Controller 0 */

-#define SAM3U_EEFC1_BASE        0x400e0a00 /* 0x400e0a00-0x400e0bff: Enhanced Embedded Flash Controller 1 */

-#define SAM3U_PIO_BASE(n)       (0x400e0c00+((n)<<9))

-#define SAM3U_PIOA_BASE         0x400e0c00 /* 0x400e0c00-0x400e0dff: Parallel I/O Controller A */

-#define SAM3U_PIOB_BASE         0x400e0e00 /* 0x400e0e00-0x400e0fff: Parallel I/O Controller B */

-#define SAM3U_PIOC_BASE         0x400e1000 /* 0x400e1000-0x400e11ff: Parallel I/O Controller C */

-#define SAM3U_RSTC_BASE         0x400e1200 /* 0x400e1200-0x400e120f: Reset Controller */

-#define SAM3U_SUPC_BASE         0x400e1210 /* 0x400e1210-0x400e122f: Supply Controller */

-#define SAM3U_RTT_BASE          0x400e1230 /* 0x400e1230-0x400e124f: Real Time Timer */

-#define SAM3U_WDT_BASE          0x400e1250 /* 0x400e1250-0x400e125f: Watchdog Timer */

-#define SAM3U_RTC_BASE          0x400e1260 /* 0x400e1260-0x400e128f: Real Time Clock */

-#define SAM3U_GPBR_BASE         0x400e1290 /* 0x400e1290-0x400e13ff: GPBR */

-                                           /* 0x490e1400-0x4007ffff: Reserved */

+#define SAM3U_SMC_BASE           0x400e0000 /* 0x400e0000-0x400e01ff: Static Memory Controller */

+#define SAM3U_MATRIX_BASE        0x400e0200 /* 0x400e0200-0x400e03ff: MATRIX */

+#define SAM3U_PMC_BASE           0x400e0400 /* 0x400e0400-0x400e05ff: Power Management Controller */

+#define SAM3U_UART_BASE          0x400e0600 /* 0x400e0600-0x400e073f: UART */

+#define SAM3U_CHIPID_BASE        0x400e0740 /* 0x400e0740-0x400e07ff: CHIP ID */

+#define SAM3U_EEFC_BASE          0x400e0800 /* 0x400e0800-0x400e0bff: Enhanced Embedded Flash Controllers*/

+#  define SAM3U_EEFCN_BASE(n)    (0x400e0800+((n)<<9))

+#  define SAM3U_EEFC0_BASE       0x400e0800 /* 0x400e0800-0x400e09ff:   Enhanced Embedded Flash Controller 0 */

+#  define SAM3U_EEFC1_BASE       0x400e0a00 /* 0x400e0a00-0x400e0bff:   Enhanced Embedded Flash Controller 1 */

+#define SAM3U_PIO_BASE           0x400e0c00 /* 0x400e0c00-0x400e11ff: Parallel I/O Controllers */

+#  define SAM3U_PION_BASE(n)     (0x400e0c00+((n)<<9))

+#  define SAM3U_PIOA_BASE        0x400e0c00 /* 0x400e0c00-0x400e0dff:   Parallel I/O Controller A */

+#  define SAM3U_PIOB_BASE        0x400e0e00 /* 0x400e0e00-0x400e0fff:   Parallel I/O Controller B */

+#  define SAM3U_PIOC_BASE        0x400e1000 /* 0x400e1000-0x400e11ff:   Parallel I/O Controller C */

+#define SAM3U_RSTC_BASE          0x400e1200 /* 0x400e1200-0x400e120f: Reset Controller */

+#define SAM3U_SUPC_BASE          0x400e1210 /* 0x400e1210-0x400e122f: Supply Controller */

+#define SAM3U_RTT_BASE           0x400e1230 /* 0x400e1230-0x400e124f: Real Time Timer */

+#define SAM3U_WDT_BASE           0x400e1250 /* 0x400e1250-0x400e125f: Watchdog Timer */

+#define SAM3U_RTC_BASE           0x400e1260 /* 0x400e1260-0x400e128f: Real Time Clock */

+#define SAM3U_GPBR_BASE          0x400e1290 /* 0x400e1290-0x400e13ff: GPBR */

+                                            /* 0x490e1400-0x4007ffff: Reserved */

 

 /************************************************************************************************

  * Public Types

diff --git a/nuttx/arch/arm/src/sam3u/sam3u_tc.h b/nuttx/arch/arm/src/sam3u/sam3u_tc.h
index 0b4231039..1c330d38b 100755
--- a/nuttx/arch/arm/src/sam3u/sam3u_tc.h
+++ b/nuttx/arch/arm/src/sam3u/sam3u_tc.h
@@ -53,19 +53,19 @@
 

 /* Timer channel offsets (with respect to timer base offset 0f 0x00, 0x40, or 0x80 */

 

-#define SAM3U_TCN_OFFSET(n)         (0x00 + ((n)<<6)) /* 0x00, 0x40, 0x80 */

-#define SAM3U_TCN_CCR_OFFSET        0x00 /* Channel Control Register */

-#define SAM3U_TCN_CMR_OFFSET        0x04 /* Channel Mode Register */

+#define SAM3U_TCN_OFFSET(n)            (0x00 + ((n)<<6)) /* 0x00, 0x40, 0x80 */

+#define SAM3U_TCN_CCR_OFFSET           0x00 /* Channel Control Register */

+#define SAM3U_TCN_CMR_OFFSET           0x04 /* Channel Mode Register */

                                             /* 0x08 Reserved */

                                             /* 0x0c Reserved */

-#define SAM3U_TCN_CV_OFFSET         0x10 /* Counter Value */

-#define SAM3U_TCN_RA_OFFSET         0x14 /* Register A */

-#define SAM3U_TCN_RB_OFFSET         0x18 /* Register B */

-#define SAM3U_TCN_RC_OFFSET         0x1c /* Register C */

-#define SAM3U_TCN_SR_OFFSET         0x20 /* Status Register */

-#define SAM3U_TCN_IER_OFFSET        0x24 /* Interrupt Enable Register */

-#define SAM3U_TCN_IDR_OFFSET        0x28 /* Interrupt Disable Register */

-#define SAM3U_TCN_IMR_OFFSET        0x2c /* Interrupt Mask Register */

+#define SAM3U_TCN_CV_OFFSET            0x10 /* Counter Value */

+#define SAM3U_TCN_RA_OFFSET            0x14 /* Register A */

+#define SAM3U_TCN_RB_OFFSET            0x18 /* Register B */

+#define SAM3U_TCN_RC_OFFSET            0x1c /* Register C */

+#define SAM3U_TCN_SR_OFFSET            0x20 /* Status Register */

+#define SAM3U_TCN_IER_OFFSET           0x24 /* Interrupt Enable Register */

+#define SAM3U_TCN_IDR_OFFSET           0x28 /* Interrupt Disable Register */

+#define SAM3U_TCN_IMR_OFFSET           0x2c /* Interrupt Mask Register */

 

 /* Timer common registers */

 

@@ -82,16 +82,16 @@
 

 /* Timer channel offsets (with respect to timer base offset 0f 0x00, 0x40, or 0x80 */

 

-#define SAM3U_TC_CCR(n)                (SAM3U_TC_BASE(n)+SAM3U_TCN_CCR_OFFSET)

-#define SAM3U_TC_CMR(n)                (SAM3U_TC_BASE(n)+SAM3U_TCN_CMR_OFFSET)

-#define SAM3U_TC_CV(n)                 (SAM3U_TC_BASE(n)+SAM3U_TCN_CV_OFFSET)

-#define SAM3U_TC_RA(n)                 (SAM3U_TC_BASE(n)+SAM3U_TCN_RA_OFFSET)

-#define SAM3U_TC_RB(n)                 (SAM3U_TC_BASE(n)+SAM3U_TCN_RB_OFFSET)

-#define SAM3U_TC_RC(n)                 (SAM3U_TC_BASE(n)+SAM3U_TCN_RC_OFFSET)

-#define SAM3U_TC_SR(n)                 (SAM3U_TC_BASE(n)+SAM3U_TCN_SR_OFFSET)

-#define SAM3U_TC_IER(n)                (SAM3U_TC_BASE(n)+SAM3U_TCN_IER_OFFSET)

-#define SAM3U_TC_IDR(n)                (SAM3U_TC_BASE(n)+SAM3U_TCN_IDR_OFFSET)

-#define SAM3U_TC_IMR(n)                (SAM3U_TC_BASE(n)+SAM3U_TCN_IMR_OFFSET)

+#define SAM3U_TC_CCR(n)                (SAM3U_TCN_BASE(n)+SAM3U_TCN_CCR_OFFSET)

+#define SAM3U_TC_CMR(n)                (SAM3U_TCN_BASE(n)+SAM3U_TCN_CMR_OFFSET)

+#define SAM3U_TC_CV(n)                 (SAM3U_TCN_BASE(n)+SAM3U_TCN_CV_OFFSET)

+#define SAM3U_TC_RA(n)                 (SAM3U_TCN_BASE(n)+SAM3U_TCN_RA_OFFSET)

+#define SAM3U_TC_RB(n)                 (SAM3U_TCN_BASE(n)+SAM3U_TCN_RB_OFFSET)

+#define SAM3U_TC_RC(n)                 (SAM3U_TCN_BASE(n)+SAM3U_TCN_RC_OFFSET)

+#define SAM3U_TC_SR(n)                 (SAM3U_TCN_BASE(n)+SAM3U_TCN_SR_OFFSET)

+#define SAM3U_TC_IER(n)                (SAM3U_TCN_BASE(n)+SAM3U_TCN_IER_OFFSET)

+#define SAM3U_TC_IDR(n)                (SAM3U_TCN_BASE(n)+SAM3U_TCN_IDR_OFFSET)

+#define SAM3U_TC_IMR(n)                (SAM3U_TCN_BASE(n)+SAM3U_TCN_IMR_OFFSET)

 

 #define SAM3U_TC0_CCR                  (SAM3U_TC0_BASE+SAM3U_TCN_CCR_OFFSET)

 #define SAM3U_TC0_CMR                  (SAM3U_TC0_BASE+SAM3U_TCN_CMR_OFFSET)

@@ -128,12 +128,12 @@
 

 /* Timer common registers */

 

-#define SAM3U_TC_BCR                   (SAM3U_TC0_BASE+SAM3U_TC_BCR_OFFSET)

-#define SAM3U_TC_BMR                   (SAM3U_TC0_BASE+SAM3U_TC_BMR_OFFSET)

-#define SAM3U_TC_QIER                  (SAM3U_TC0_BASE+SAM3U_TC_QIER_OFFSET)

-#define SAM3U_TC_QIDR                  (SAM3U_TC0_BASE+SAM3U_TC_QIDR_OFFSET)

-#define SAM3U_TC_QIMR                  (SAM3U_TC0_BASE+SAM3U_TC_QIMR_OFFSET)

-#define SAM3U_TC_QISR                  (SAM3U_TC0_BASE+SAM3U_TC_QISR_OFFSET)

+#define SAM3U_TC_BCR                   (SAM3U_TC_BASE+SAM3U_TC_BCR_OFFSET)

+#define SAM3U_TC_BMR                   (SAM3U_TC_BASE+SAM3U_TC_BMR_OFFSET)

+#define SAM3U_TC_QIER                  (SAM3U_TC_BASE+SAM3U_TC_QIER_OFFSET)

+#define SAM3U_TC_QIDR                  (SAM3U_TC_BASE+SAM3U_TC_QIDR_OFFSET)

+#define SAM3U_TC_QIMR                  (SAM3U_TC_BASE+SAM3U_TC_QIMR_OFFSET)

+#define SAM3U_TC_QISR                  (SAM3U_TC_BASE+SAM3U_TC_QISR_OFFSET)

 

 /* TC register bit definitions ******************************************************************/

 

diff --git a/nuttx/arch/arm/src/sam3u/sam3u_twi.h b/nuttx/arch/arm/src/sam3u/sam3u_twi.h
index 406f62ca1..4a26ecdc4 100755
--- a/nuttx/arch/arm/src/sam3u/sam3u_twi.h
+++ b/nuttx/arch/arm/src/sam3u/sam3u_twi.h
@@ -67,17 +67,17 @@
 

 /* TWI register adresses ****************************************************************/

 

-#define SAM3U_TWI_CR(n)              (SAM3U_TWI_BASE(n)+SAM3U_TWI_CR_OFFSET)

-#define SAM3U_TWI_MMR(n)             (SAM3U_TWI_BASE(n)+SAM3U_TWI_MMR_OFFSET)

-#define SAM3U_TWI_SMR(n)             (SAM3U_TWI_BASE(n)+SAM3U_TWI_SMR_OFFSET)

-#define SAM3U_TWI_IADR(n)            (SAM3U_TWI_BASE(n)+SAM3U_TWI_IADR_OFFSET)

-#define SAM3U_TWI_CWGR(n)            (SAM3U_TWI_BASE(n)+SAM3U_TWI_CWGR_OFFSET)

-#define SAM3U_TWI_SR(n)              (SAM3U_TWI_BASE(n)+SAM3U_TWI_SR_OFFSET)

-#define SAM3U_TWI_IER(n)             (SAM3U_TWI_BASE(n)+SAM3U_TWI_IER_OFFSET)

-#define SAM3U_TWI_IDR(n)             (SAM3U_TWI_BASE(n)+SAM3U_TWI_IDR_OFFSET)

-#define SAM3U_TWI_IMR(n)             (SAM3U_TWI_BASE(n)+SAM3U_TWI_IMR_OFFSET)

-#define SAM3U_TWI_RHR(n)             (SAM3U_TWI_BASE(n)+SAM3U_TWI_RHR_OFFSET)

-#define SAM3U_TWI_THR(n)             (SAM3U_TWI_BASE(n)+SAM3U_TWI_THR_OFFSET)

+#define SAM3U_TWI_CR(n)              (SAM3U_TWIN_BASE(n)+SAM3U_TWI_CR_OFFSET)

+#define SAM3U_TWI_MMR(n)             (SAM3U_TWIN_BASE(n)+SAM3U_TWI_MMR_OFFSET)

+#define SAM3U_TWI_SMR(n)             (SAM3U_TWIN_BASE(n)+SAM3U_TWI_SMR_OFFSET)

+#define SAM3U_TWI_IADR(n)            (SAM3U_TWIN_BASE(n)+SAM3U_TWI_IADR_OFFSET)

+#define SAM3U_TWI_CWGR(n)            (SAM3U_TWIN_BASE(n)+SAM3U_TWI_CWGR_OFFSET)

+#define SAM3U_TWI_SR(n)              (SAM3U_TWIN_BASE(n)+SAM3U_TWI_SR_OFFSET)

+#define SAM3U_TWI_IER(n)             (SAM3U_TWIN_BASE(n)+SAM3U_TWI_IER_OFFSET)

+#define SAM3U_TWI_IDR(n)             (SAM3U_TWIN_BASE(n)+SAM3U_TWI_IDR_OFFSET)

+#define SAM3U_TWI_IMR(n)             (SAM3U_TWIN_BASE(n)+SAM3U_TWI_IMR_OFFSET)

+#define SAM3U_TWI_RHR(n)             (SAM3U_TWIN_BASE(n)+SAM3U_TWI_RHR_OFFSET)

+#define SAM3U_TWI_THR(n)             (SAM3U_TWIN_BASE(n)+SAM3U_TWI_THR_OFFSET)

 

 #define SAM3U_TWI0_CR                (SAM3U_TWI0_BASE+SAM3U_TWI_CR_OFFSET)

 #define SAM3U_TWI0_MMR               (SAM3U_TWI0_BASE+SAM3U_TWI_MMR_OFFSET)

diff --git a/nuttx/arch/arm/src/sam3u/sam3u_uart.h b/nuttx/arch/arm/src/sam3u/sam3u_uart.h
index 9d17f217d..c30bac8fa 100755
--- a/nuttx/arch/arm/src/sam3u/sam3u_uart.h
+++ b/nuttx/arch/arm/src/sam3u/sam3u_uart.h
@@ -87,6 +87,101 @@
 #define SAM3U_UART_THR                 (SAM3U_UART_BASE+SAM3U_UART_THR_OFFSET)

 #define SAM3U_UART_BRGR                (SAM3U_UART_BASE+SAM3U_UART_BRGR_OFFSET)

 

+#define SAM3U_USART_CR(n)              (SAM3U_USARTN_BASE(n)+SAM3U_UART_CR_OFFSET)

+#define SAM3U_USART_MR(n)              (SAM3U_USARTN_BASE(n)+SAM3U_UART_MR_OFFSET)

+#define SAM3U_USART_IER(n)             (SAM3U_USARTN_BASE(n)+SAM3U_UART_IER_OFFSET)

+#define SAM3U_USART_IDR(n)             (SAM3U_USARTN_BASE(n)+SAM3U_UART_IDR_OFFSET)

+#define SAM3U_USART_IMR(n)             (SAM3U_USARTN_BASE(n)+SAM3U_UART_IMR_OFFSET)

+#define SAM3U_USART_SR(n)              (SAM3U_USARTN_BASE(n)+SAM3U_UART_SR_OFFSET)

+#define SAM3U_USART_RHR(n)             (SAM3U_USARTN_BASE(n)+SAM3U_UART_RHR_OFFSET)

+#define SAM3U_USART_THR(n)             (SAM3U_USARTN_BASE(n)+SAM3U_UART_THR_OFFSET)

+#define SAM3U_USART_BRGR(n)            (SAM3U_USARTN_BASE(n)+SAM3U_UART_BRGR_OFFSET)

+#define SAM3U_USART_RTOR(n)            (SAM3U_USARTN_BASE(n)+SAM3U_USART_RTOR_OFFSET)

+#define SAM3U_USART_TTGR(n)            (SAM3U_USARTN_BASE(n)+SAM3U_USART_TTGR_OFFSET)

+#define SAM3U_USART_FIDI(n)            (SAM3U_USARTN_BASE(n)+SAM3U_USART_FIDI_OFFSET)

+#define SAM3U_USART_NER(n)             (SAM3U_USARTN_BASE(n)+SAM3U_USART_NER_OFFSET)

+#define SAM3U_USART_IF(n)              (SAM3U_USARTN_BASE(n)+SAM3U_USART_IF_OFFSET)

+#define SAM3U_USART_MAN(n)             (SAM3U_USARTN_BASE(n)+SAM3U_USART_MAN_OFFSET)

+#define SAM3U_USART_WPMR(n)            (SAM3U_USARTN_BASE(n)+SAM3U_USART_WPMR_OFFSET)

+#define SAM3U_USART_WPSR(n)            (SAM3U_USARTN_BASE(n)+SAM3U_USART_WPSR_OFFSET)

+#define SAM3U_USART_VERSION(n)         (SAM3U_USARTN_BASE(n)+SAM3U_USART_VERSION_OFFSET)

+

+#define SAM3U_USART0_CR                (SAM3U_USART0_BASE+SAM3U_UART_CR_OFFSET)

+#define SAM3U_USART0_MR_               (SAM3U_USART0_BASE+SAM3U_UART_MR_OFFSET)

+#define SAM3U_USART0_IER               (SAM3U_USART0_BASE+SAM3U_UART_IER_OFFSET)

+#define SAM3U_USART0_IDR               (SAM3U_USART0_BASE+SAM3U_UART_IDR_OFFSET)

+#define SAM3U_USART0_IMR               (SAM3U_USART0_BASE+SAM3U_UART_IMR_OFFSET)

+#define SAM3U_USART0_SR                (SAM3U_USART0_BASE+SAM3U_UART_SR_OFFSET)

+#define SAM3U_USART0_RHR               (SAM3U_USART0_BASE+SAM3U_UART_RHR_OFFSET)

+#define SAM3U_USART0_THR               (SAM3U_USART0_BASE+SAM3U_UART_THR_OFFSET)

+#define SAM3U_USART0_BRGR              (SAM3U_USART0_BASE+SAM3U_UART_BRGR_OFFSET)

+#define SAM3U_USART0_RTOR              (SAM3U_USART0_BASE+SAM3U_USART_RTOR_OFFSET)

+#define SAM3U_USART0_TTGR              (SAM3U_USART0_BASE+SAM3U_USART_TTGR_OFFSET)

+#define SAM3U_USART0_FIDI              (SAM3U_USART0_BASE+SAM3U_USART_FIDI_OFFSET)

+#define SAM3U_USART0_NER               (SAM3U_USART0_BASE+SAM3U_USART_NER_OFFSET)

+#define SAM3U_USART0_IF                (SAM3U_USART0_BASE+SAM3U_USART_IF_OFFSET)

+#define SAM3U_USART0_MAN               (SAM3U_USART0_BASE+SAM3U_USART_MAN_OFFSET)

+#define SAM3U_USART0_WPMR              (SAM3U_USART0_BASE+SAM3U_USART_WPMR_OFFSET)

+#define SAM3U_USART0_WPSR              (SAM3U_USART0_BASE+SAM3U_USART_WPSR_OFFSET)

+#define SAM3U_USART0_VERSION           (SAM3U_USART0_BASE+SAM3U_USART_VERSION_OFFSET)

+

+#define SAM3U_USART1_CR                (SAM3U_USART1_BASE+SAM3U_UART_CR_OFFSET)

+#define SAM3U_USART1_MR_               (SAM3U_USART1_BASE+SAM3U_UART_MR_OFFSET)

+#define SAM3U_USART1_IER               (SAM3U_USART1_BASE+SAM3U_UART_IER_OFFSET)

+#define SAM3U_USART1_IDR               (SAM3U_USART1_BASE+SAM3U_UART_IDR_OFFSET)

+#define SAM3U_USART1_IMR               (SAM3U_USART1_BASE+SAM3U_UART_IMR_OFFSET)

+#define SAM3U_USART1_SR                (SAM3U_USART1_BASE+SAM3U_UART_SR_OFFSET)

+#define SAM3U_USART1_RHR               (SAM3U_USART1_BASE+SAM3U_UART_RHR_OFFSET)

+#define SAM3U_USART1_THR               (SAM3U_USART1_BASE+SAM3U_UART_THR_OFFSET)

+#define SAM3U_USART1_BRGR              (SAM3U_USART1_BASE+SAM3U_UART_BRGR_OFFSET)

+#define SAM3U_USART1_RTOR              (SAM3U_USART1_BASE+SAM3U_USART_RTOR_OFFSET)

+#define SAM3U_USART1_TTGR              (SAM3U_USART1_BASE+SAM3U_USART_TTGR_OFFSET)

+#define SAM3U_USART1_FIDI              (SAM3U_USART1_BASE+SAM3U_USART_FIDI_OFFSET)

+#define SAM3U_USART1_NER               (SAM3U_USART1_BASE+SAM3U_USART_NER_OFFSET)

+#define SAM3U_USART1_IF                (SAM3U_USART1_BASE+SAM3U_USART_IF_OFFSET)

+#define SAM3U_USART1_MAN               (SAM3U_USART1_BASE+SAM3U_USART_MAN_OFFSET)

+#define SAM3U_USART1_WPMR              (SAM3U_USART1_BASE+SAM3U_USART_WPMR_OFFSET)

+#define SAM3U_USART1_WPSR              (SAM3U_USART1_BASE+SAM3U_USART_WPSR_OFFSET)

+#define SAM3U_USART1_VERSION           (SAM3U_USART1_BASE+SAM3U_USART_VERSION_OFFSET)

+

+#define SAM3U_USART2_CR                (SAM3U_USART2_BASE+SAM3U_UART_CR_OFFSET)

+#define SAM3U_USART2_MR_               (SAM3U_USART2_BASE+SAM3U_UART_MR_OFFSET)

+#define SAM3U_USART2_IER               (SAM3U_USART2_BASE+SAM3U_UART_IER_OFFSET)

+#define SAM3U_USART2_IDR               (SAM3U_USART2_BASE+SAM3U_UART_IDR_OFFSET)

+#define SAM3U_USART2_IMR               (SAM3U_USART2_BASE+SAM3U_UART_IMR_OFFSET)

+#define SAM3U_USART2_SR                (SAM3U_USART2_BASE+SAM3U_UART_SR_OFFSET)

+#define SAM3U_USART2_RHR               (SAM3U_USART2_BASE+SAM3U_UART_RHR_OFFSET)

+#define SAM3U_USART2_THR               (SAM3U_USART2_BASE+SAM3U_UART_THR_OFFSET)

+#define SAM3U_USART2_BRGR              (SAM3U_USART2_BASE+SAM3U_UART_BRGR_OFFSET)

+#define SAM3U_USART2_RTOR              (SAM3U_USART2_BASE+SAM3U_USART_RTOR_OFFSET)

+#define SAM3U_USART2_TTGR              (SAM3U_USART2_BASE+SAM3U_USART_TTGR_OFFSET)

+#define SAM3U_USART2_FIDI              (SAM3U_USART2_BASE+SAM3U_USART_FIDI_OFFSET)

+#define SAM3U_USART2_NER               (SAM3U_USART2_BASE+SAM3U_USART_NER_OFFSET)

+#define SAM3U_USART2_IF                (SAM3U_USART2_BASE+SAM3U_USART_IF_OFFSET)

+#define SAM3U_USART2_MAN               (SAM3U_USART2_BASE+SAM3U_USART_MAN_OFFSET)

+#define SAM3U_USART2_WPMR              (SAM3U_USART2_BASE+SAM3U_USART_WPMR_OFFSET)

+#define SAM3U_USART2_WPSR              (SAM3U_USART2_BASE+SAM3U_USART_WPSR_OFFSET)

+#define SAM3U_USART2_VERSION           (SAM3U_USART2_BASE+SAM3U_USART_VERSION_OFFSET)

+

+#define SAM3U_USART3_CR                (SAM3U_USART3_BASE+SAM3U_UART_CR_OFFSET)

+#define SAM3U_USART3_MR_               (SAM3U_USART3_BASE+SAM3U_UART_MR_OFFSET)

+#define SAM3U_USART3_IER               (SAM3U_USART3_BASE+SAM3U_UART_IER_OFFSET)

+#define SAM3U_USART3_IDR               (SAM3U_USART3_BASE+SAM3U_UART_IDR_OFFSET)

+#define SAM3U_USART3_IMR               (SAM3U_USART3_BASE+SAM3U_UART_IMR_OFFSET)

+#define SAM3U_USART3_SR                (SAM3U_USART3_BASE+SAM3U_UART_SR_OFFSET)

+#define SAM3U_USART3_RHR               (SAM3U_USART3_BASE+SAM3U_UART_RHR_OFFSET)

+#define SAM3U_USART3_THR               (SAM3U_USART3_BASE+SAM3U_UART_THR_OFFSET)

+#define SAM3U_USART3_BRGR              (SAM3U_USART3_BASE+SAM3U_UART_BRGR_OFFSET)

+#define SAM3U_USART3_RTOR              (SAM3U_USART3_BASE+SAM3U_USART_RTOR_OFFSET)

+#define SAM3U_USART3_TTGR              (SAM3U_USART3_BASE+SAM3U_USART_TTGR_OFFSET)

+#define SAM3U_USART3_FIDI              (SAM3U_USART3_BASE+SAM3U_USART_FIDI_OFFSET)

+#define SAM3U_USART3_NER               (SAM3U_USART3_BASE+SAM3U_USART_NER_OFFSET)

+#define SAM3U_USART3_IF                (SAM3U_USART3_BASE+SAM3U_USART_IF_OFFSET)

+#define SAM3U_USART3_MAN               (SAM3U_USART3_BASE+SAM3U_USART_MAN_OFFSET)

+#define SAM3U_USART3_WPMR              (SAM3U_USART3_BASE+SAM3U_USART_WPMR_OFFSET)

+#define SAM3U_USART3_WPSR              (SAM3U_USART3_BASE+SAM3U_USART_WPSR_OFFSET)

+#define SAM3U_USART3_VERSION           (SAM3U_USART3_BASE+SAM3U_USART_VERSION_OFFSET)

+

 /* UART register bit definitions ****************************************************************/

 

 /* UART Control Register */