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| author | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2010-03-17 01:22:58 +0000 |
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| committer | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2010-03-17 01:22:58 +0000 |
| commit | 7595be4261d8511950b07dfd91b50b1aaa8e024e (patch) | |
| tree | e1e54f629b3a8711d0b84d62000cb77f98224f91 | |
| parent | 8eb2f77a32b65bf5fb8267553d5ab60078b9eae1 (diff) | |
| download | nuttx-7595be4261d8511950b07dfd91b50b1aaa8e024e.tar.gz nuttx-7595be4261d8511950b07dfd91b50b1aaa8e024e.tar.bz2 nuttx-7595be4261d8511950b07dfd91b50b1aaa8e024e.zip | |
Fix vector configuration
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2547 42af7a65-404d-4744-a932-0658087f49c3
| -rw-r--r-- | nuttx/arch/arm/src/arm/up_head.S | 35 |
1 files changed, 31 insertions, 4 deletions
diff --git a/nuttx/arch/arm/src/arm/up_head.S b/nuttx/arch/arm/src/arm/up_head.S index bfe6afa0b..c3965995b 100644 --- a/nuttx/arch/arm/src/arm/up_head.S +++ b/nuttx/arch/arm/src/arm/up_head.S @@ -209,34 +209,61 @@ __start: mcr p15, 0, r0, c3, c0 /* Load domain access register */ mrc p15, 0, r0, c1, c0 /* Get control register */ - /* Clear bits (see arm.h) */ + /* Clear bits (see arm.h) + * + * CR_R - ROM MMU protection + * CR_F - Implementation defined + * CR_Z - Implementation defined + * + * CR_A - Alignment abort enable + * CR_C - Dcache enable + * CR_W - Write buffer enable + * + * CR_I - Icache enable + */ bic r0, r0, #(CR_R|CR_F|CR_Z) bic r0, r0, #(CR_A|CR_C|CR_W) bic r0, r0, #(CR_I) - /* Set bits (see arm.h) */ + /* Set bits (see arm.h) + * + * CR_M - MMU enable + * CR_P - 32-bit exception handler + * CR_D - 32-bit data address range + */ orr r0, r0, #(CR_M|CR_P|CR_D) /* In most architectures, vectors are relocated to 0xffff0000. * -- but not all + * + * CR_S - System MMU protection + * CR_V - Vectors relocated to 0xffff0000 */ #ifndef CONFIG_ARCH_LOWVECTORS - orr r0, r0, #(CR_S) -#else orr r0, r0, #(CR_S|CR_V) +#else + orr r0, r0, #(CR_S) #endif + /* CR_RR - Round Robin cache replacement */ + #ifdef CPU_CACHE_ROUND_ROBIN orr r0, r0, #(CR_RR) #endif + /* CR_C - Dcache enable */ + #ifndef CPU_DCACHE_DISABLE orr r0, r0, #(CR_C) #endif + /* CR_C - Dcache enable */ + #ifndef CPU_ICACHE_DISABLE orr r0, r0, #(CR_I) #endif + /* CR_A - Alignment abort enable */ + #ifdef ALIGNMENT_TRAP orr r0, r0, #(CR_A) #endif |