Completes implementation of kernel mode build

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3483 42af7a65-404d-4744-a932-0658087f49c3

6 files changed, 576 insertions, 6 deletions

diff --git a/nuttx/arch/arm/src/cortexm3/mpu.h b/nuttx/arch/arm/src/cortexm3/mpu.h
index 63cdabddc..7cb5970d3 100644
--- a/nuttx/arch/arm/src/cortexm3/mpu.h
+++ b/nuttx/arch/arm/src/cortexm3/mpu.h
@@ -40,6 +40,17 @@
  * Included Files
  ************************************************************************************/
 
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+#  include <sys/types.h>
+#  include <stdint.h>
+#  include <stdbool.h>
+#  include <debug.h>
+
+#  include "up_arch.h"
+#endif
+
 /************************************************************************************
  * Pre-processor Definitions
  ************************************************************************************/
@@ -96,8 +107,8 @@
 #define MPU_RASR_ATTR_SHIFT     (21)      /* Bits 19-21: TEX Address Permisson */
 #define MPU_RASR_ATTR__MASK     (7 << MPU_RASR_ATTR_SHIFT)
 #define MPU_RASR_S              (1 << 18) /* Bit 18: Shareable */
-#define MPU_RASR_C              (1 << 17) /* Bit 17: C Address Permission */
-#define MPU_RASR_B              (1 << 16) /* Bit 16: B Address Permission */
+#define MPU_RASR_C              (1 << 17) /* Bit 17: Cacheable */
+#define MPU_RASR_B              (1 << 16) /* Bit 16: Bufferable */
 #define MPU_RASR_AP_SHIFT       (24)      /* Bits 24-26: Access permission */
 #define MPU_RASR_AP_MASK        (7 << MPU_RASR_AP_SHIFT)
 #  define MPU_RASR_AP_NONO      (0 << MPU_RASR_AP_SHIFT) /* P:None U:None */
@@ -105,11 +116,375 @@
 #  define MPU_RASR_AP_RWRO      (2 << MPU_RASR_AP_SHIFT) /* P:RW   U:RO   */
 #  define MPU_RASR_AP_RWRW      (3 << MPU_RASR_AP_SHIFT) /* P:RW   U:RW   */
 #  define MPU_RASR_AP_RONO      (5 << MPU_RASR_AP_SHIFT) /* P:RO   U:None */
-#  define MPU_RASR_AP_RORO      (6 << MPU_RASR_AP_SHIFT) /* P:R0   U:RO   */
+#  define MPU_RASR_AP_RORO      (6 << MPU_RASR_AP_SHIFT) /* P:RO   U:RO   */
 #define MPU_RASR_XN             (1 << 28) /* Bit 28: Instruction access disable */
 
 /************************************************************************************
+ * Global Function Prototypes
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C" {
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Name: mpu_log2regionsize
+ *
+ * Description:
+ *   Determine the smallest value of l2size (log base 2 size) such that the
+ *   following is true:
+ *
+ *   size <= (1 << l2size)
+ *
+ ****************************************************************************/
+
+EXTERN uint8_t mpu_log2regionsize(size_t size);
+
+/****************************************************************************
+ * Name: mpu_subregion
+ *
+ * Description:
+ *   Given the size of the (1) memory to be mapped and (2) the log2 size
+ *   of the mapping to use, determine the minimal sub-region set to span
+ *   that memory region.
+ *
+ * Assumption:
+ *   l2size has the same properties as the return value from
+ *   mpu_log2regionsize()
+ *
+ ****************************************************************************/
+
+EXTERN uint32_t mpu_subregion(size_t size, uint8_t l2size);
+
+/************************************************************************************
  * Inline Functions
  ************************************************************************************/
 
+/****************************************************************************
+ * Name: mpu_showtype
+ *
+ * Description:
+ *   Show the characteristics of the MPU
+ *
+ ****************************************************************************/
+
+static inline void mpu_showtype(void)
+{
+#ifdef CONFIG_DEBUG
+  uint32_t regval = getreg32(MPU_TYPE);
+  dbg("%s MPU Regions: data=%d instr=%d\n",
+      (regval & MPU_TYPE_SEPARATE) != 0 ? "Separate" : "Unified",
+      (regval & MPU_TYPE_DREGION_MASK) >> MPU_TYPE_DREGION_SHIFT,
+      (regval & MPU_TYPE_IREGION_MASK) >> MPU_TYPE_IREGION_SHIFT,
+#endif
+}
+
+/****************************************************************************
+ * Name: mpu_control
+ *
+ * Description:
+ *   Configure and enable (or disable) the MPU
+ *
+ ****************************************************************************/
+
+static inline void mpu_control(bool enable, bool hfnmiena, bool privdefena)
+{
+  uint32_t regval = 0;
+
+  if (enable)
+    {
+      regval |= MPU_CTRL_ENABLE; /* Enable the MPU */
+
+      if (hfnmiena)
+        {
+           regval |= MPU_CTRL_HFNMIENA; /* Enable MPU during hard fault, NMI, and FAULTMAS */
+        }
+
+      if (privdefena)
+        {
+          regval |= MPU_CTRL_PRIVDEFENA; /* Enable privileged access to default memory map */
+        }
+    }
+
+  putreg32(regval, MPU_CTRL);
+}
+
+/****************************************************************************
+ * Name: mpu_userflash
+ *
+ * Description:
+ *   Configure a region for user program flash
+ *
+ ****************************************************************************/
+
+static inline void mpu_userflash(int region, uintptr_t base, size_t size)
+{
+  uint32_t regval;
+  uint8_t  l2size;
+  uint8_t  subregions;
+
+  /* Select the region */
+
+  putreg32(region, MPU_RNR);
+
+  /* Select the region base address */
+
+  putreg32((base & MPU_RBAR_ADDR_MASK) | region, MPU_RBAR);
+
+  /* Select the region size and the sub-region map */
+
+  l2size     = mpu_log2regionsize(size);
+  subregions = mpu_subregion(size, l2size);
+
+  /* The configure the region */
+
+  regval = MPU_RASR_ENABLE                              | /* Enable region */
+           MPU_RASR_SIZE_LOG2((uint32_t)l2size)         | /* Region size   */
+           ((uint32_t)subregions << MPU_RASR_SRD_SHIFT) | /* Sub-regions   */
+           MPU_RASR_C                                   | /* Cacheable     */
+           MPU_RASR_AP_RORO;                              /* P:RO   U:RO   */
+  putreg32(regval, MPU_RASR);
+}
+
+/****************************************************************************
+ * Name: mpu_privflash
+ *
+ * Description:
+ *   Configure a region for privileged program flash
+ *
+ ****************************************************************************/
+
+static inline void mpu_privflash(int region, uintptr_t base, size_t size)
+{
+  uint32_t regval;
+  uint8_t  l2size;
+  uint8_t  subregions;
+
+  /* Select the region */
+
+  putreg32(region, MPU_RNR);
+
+  /* Select the region base address */
+
+  putreg32((base & MPU_RBAR_ADDR_MASK) | region, MPU_RBAR);
+
+  /* Select the region size and the sub-region map */
+
+  l2size     = mpu_log2regionsize(size);
+  subregions = mpu_subregion(size, l2size);
+
+  /* The configure the region */
+
+  regval = MPU_RASR_ENABLE                              | /* Enable region */
+           MPU_RASR_SIZE_LOG2((uint32_t)l2size)         | /* Region size   */
+           ((uint32_t)subregions << MPU_RASR_SRD_SHIFT) | /* Sub-regions   */
+           MPU_RASR_C                                   | /* Cacheable     */
+           MPU_RASR_AP_RONO;                              /* P:RO   U:None */
+  putreg32(regval, MPU_RASR);
+}
+
+/****************************************************************************
+ * Name: mpu_userintsram
+ *
+ * Description:
+ *   Configure a region as user internal SRAM
+ *
+ ****************************************************************************/
+
+static inline void mpu_userintsram(int region, uintptr_t base, size_t size)
+{
+  uint32_t regval;
+  uint8_t  l2size;
+  uint8_t  subregions;
+
+  /* Select the region */
+
+  putreg32(region, MPU_RNR);
+
+  /* Select the region base address */
+
+  putreg32((base & MPU_RBAR_ADDR_MASK) | region, MPU_RBAR);
+
+  /* Select the region size and the sub-region map */
+
+  l2size     = mpu_log2regionsize(size);
+  subregions = mpu_subregion(size, l2size);
+
+  /* The configure the region */
+
+  regval = MPU_RASR_ENABLE                              | /* Enable region */
+           MPU_RASR_SIZE_LOG2((uint32_t)l2size)         | /* Region size   */
+           ((uint32_t)subregions << MPU_RASR_SRD_SHIFT) | /* Sub-regions   */
+           MPU_RASR_S                                   | /* Shareable     */
+           MPU_RASR_C                                   | /* Cacheable     */
+           MPU_RASR_AP_RWRW;                              /* P:RW   U:RW   */
+  putreg32(regval, MPU_RASR);
+}
+
+/****************************************************************************
+ * Name: mpu_privintsram
+ *
+ * Description:
+ *   Configure a region as privileged internal SRAM
+ *
+ ****************************************************************************/
+
+static inline void mpu_privintsram(int region, uintptr_t base, size_t size)
+{
+  uint32_t regval;
+  uint8_t  l2size;
+  uint8_t  subregions;
+
+  /* Select the region */
+
+  putreg32(region, MPU_RNR);
+
+  /* Select the region base address */
+
+  putreg32((base & MPU_RBAR_ADDR_MASK) | region, MPU_RBAR);
+
+  /* Select the region size and the sub-region map */
+
+  l2size     = mpu_log2regionsize(size);
+  subregions = mpu_subregion(size, l2size);
+
+  /* The configure the region */
+
+  regval = MPU_RASR_ENABLE                              | /* Enable region */
+           MPU_RASR_SIZE_LOG2((uint32_t)l2size)         | /* Region size   */
+           ((uint32_t)subregions << MPU_RASR_SRD_SHIFT) | /* Sub-regions   */
+           MPU_RASR_S                                   | /* Shareable     */
+           MPU_RASR_C                                   | /* Cacheable     */
+           MPU_RASR_AP_RWNO;                              /* P:RW   U:None */
+  putreg32(regval, MPU_RASR);
+}
+
+/****************************************************************************
+ * Name: mpu_userextsram
+ *
+ * Description:
+ *   Configure a region as user external SRAM
+ *
+ ****************************************************************************/
+
+static inline void mpu_userextsram(int region, uintptr_t base, size_t size)
+{
+  uint32_t regval;
+  uint8_t  l2size;
+  uint8_t  subregions;
+
+  /* Select the region */
+
+  putreg32(region, MPU_RNR);
+
+  /* Select the region base address */
+
+  putreg32((base & MPU_RBAR_ADDR_MASK) | region, MPU_RBAR);
+
+  /* Select the region size and the sub-region map */
+
+  l2size     = mpu_log2regionsize(size);
+  subregions = mpu_subregion(size, l2size);
+
+  /* The configure the region */
+
+  regval = MPU_RASR_ENABLE                              | /* Enable region */
+           MPU_RASR_SIZE_LOG2((uint32_t)l2size)         | /* Region size   */
+           ((uint32_t)subregions << MPU_RASR_SRD_SHIFT) | /* Sub-regions   */
+           MPU_RASR_S                                   | /* Shareable     */
+           MPU_RASR_C                                   | /* Cacheable     */
+           MPU_RASR_B                                   | /* Bufferable    */
+           MPU_RASR_AP_RWRW;                              /* P:RW   U:RW   */
+  putreg32(regval, MPU_RASR);
+}
+
+/****************************************************************************
+ * Name: mpu_privextsram
+ *
+ * Description:
+ *   Configure a region as privileged external SRAM
+ *
+ ****************************************************************************/
+
+static inline void mpu_privextsram(int region, uintptr_t base, size_t size)
+{
+  uint32_t regval;
+  uint8_t  l2size;
+  uint8_t  subregions;
+
+  /* Select the region */
+
+  putreg32(region, MPU_RNR);
+
+  /* Select the region base address */
+
+  putreg32((base & MPU_RBAR_ADDR_MASK) | region, MPU_RBAR);
+
+  /* Select the region size and the sub-region map */
+
+  l2size     = mpu_log2regionsize(size);
+  subregions = mpu_subregion(size, l2size);
+
+  /* The configure the region */
+
+  regval = MPU_RASR_ENABLE                              | /* Enable region */
+           MPU_RASR_SIZE_LOG2((uint32_t)l2size)         | /* Region size   */
+           ((uint32_t)subregions << MPU_RASR_SRD_SHIFT) | /* Sub-regions   */
+           MPU_RASR_S                                   | /* Shareable     */
+           MPU_RASR_C                                   | /* Cacheable     */
+           MPU_RASR_B                                   | /* Bufferable    */
+           MPU_RASR_AP_RWNO;                              /* P:RW   U:None */
+  putreg32(regval, MPU_RASR);
+}
+
+/****************************************************************************
+ * Name: mpu_peripheral
+ *
+ * Description:
+ *   Configure a region as privileged periperal address space
+ *
+ ****************************************************************************/
+
+static inline void mpu_peripheral(int region, uintptr_t base, size_t size)
+{
+  uint32_t regval;
+  uint8_t  l2size;
+  uint8_t  subregions;
+
+  /* Select the region */
+
+  putreg32(region, MPU_RNR);
+
+  /* Select the region base address */
+
+  putreg32((base & MPU_RBAR_ADDR_MASK) | region, MPU_RBAR);
+
+  /* Select the region size and the sub-region map */
+
+  l2size     = mpu_log2regionsize(size);
+  subregions = mpu_subregion(size, l2size);
+
+  /* The configure the region */
+
+  regval = MPU_RASR_ENABLE                              | /* Enable region */
+           MPU_RASR_SIZE_LOG2((uint32_t)l2size)         | /* Region size   */
+           ((uint32_t)subregions << MPU_RASR_SRD_SHIFT) | /* Sub-regions   */
+           MPU_RASR_S                                   | /* Shareable     */
+           MPU_RASR_B                                   | /* Bufferable    */
+           MPU_RASR_AP_RWNO;                              /* P:RW   U:None */
+  putreg32(regval, MPU_RASR);
+}
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif  /* __ASSEMBLY__ */
 #endif  /* __ARCH_ARM_SRC_COMMON_CORTEXM_MPU_H */
+
diff --git a/nuttx/arch/arm/src/cortexm3/up_copystate.c b/nuttx/arch/arm/src/cortexm3/up_copystate.c
index f5d4ecad2..8704bc106 100644
--- a/nuttx/arch/arm/src/cortexm3/up_copystate.c
+++ b/nuttx/arch/arm/src/cortexm3/up_copystate.c
@@ -1,7 +1,7 @@
 /****************************************************************************
  * arch/arm/src/cortexm3/up_copystate.c
  *
- *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -61,7 +61,7 @@
  ****************************************************************************/
 
 /****************************************************************************
- * Name: up_undefinedinsn
+ * Name: up_copystate
  ****************************************************************************/
 
 /* A little faster than most memcpy's */
diff --git a/nuttx/arch/arm/src/cortexm3/up_mpu.c b/nuttx/arch/arm/src/cortexm3/up_mpu.c
new file mode 100644
index 000000000..12edb9263
--- /dev/null
+++ b/nuttx/arch/arm/src/cortexm3/up_mpu.c
@@ -0,0 +1,154 @@
+/****************************************************************************
+ * arch/arm/src/cortexm3/up_mpu.c
+ *
+ *   Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+
+#include "mpu.h"
+#include "up_internal.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/* This set represents the set of disabled memory sub-regions.  A bit set
+ * corresponds to a disabled sub-region; the LS bit corresponds to the first
+ * region.  The array is indexed by the number of subregions:  0 means no sub-
+ * regions (0xff), and 0 means all subregions but one (0x00).
+ */
+
+static void uint8_t g_regionmap[9] = 
+{
+  0xff, 0x7f, 0x3f, 0x1f, 0x0f, 0x07, 0x03, 0x01, 0x00
+};
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: mpu_log2regionsize
+ *
+ * Description:
+ *   Determine the smallest value of l2size (log base 2 size) such that the
+ *   following is true:
+ *
+ *   size <= (1 << l2size)
+ *
+ ****************************************************************************/
+
+uint8_t mpu_log2regionsize(size_t size)
+{
+  /* The minimum permitted region size is 16 bytes (log2(16) = 4. */
+
+  uint32_t l2size;
+  for (l2size = 4; l2size < 32 && size > (1 << l2size); size++);
+  return l2size;
+}
+
+/****************************************************************************
+ * Name: mpu_subregion
+ *
+ * Description:
+ *   Given the size of the (1) memory to be mapped and (2) the log2 size
+ *   of the mapping to use, determine the minimal sub-region set to span
+ *   that memory region.
+ *
+ * Assumption:
+ *   l2size has the same properties as the return value from
+ *   mpu_log2regionsize()
+ *
+ ****************************************************************************/
+
+uint32_t mpu_subregion(size_t size, uint8_t l2size)
+{
+  unsigned int nsrs
+  uint32_t     asize;
+  uint32_t     mask;
+
+  /* Eight subregions are support.  The representation is as an 8-bit
+   * value with the LS bit corresponding to subregion 0.  A bit is set
+   * to disable the sub-region.
+   *
+   * l2size: Log2 of the actual region size is <= (1 << l2size);
+   */
+
+  DEBUGASSERT(lsize > 3 && size <= (1 << l2size));
+
+  /* Examples with l2size = 12:
+   *
+   *         Shifted Adjusted        Number      Sub-Region
+   * Size    Mask    Size      Shift Sub-Regions Bitset
+   * 0x1000  0x01ff  0x1000    9     8           0x00
+   * 0x0c00  0x01ff  0x0c00    9     6           0x03
+   * 0x0c40  0x01ff  0x0e00    9     7           0x01
+   */
+
+  if (l2size < 32)
+    {
+      mask  = ((1 << lsize)-1) >> 3; /* Shifted mask */
+    }
+
+  /* The 4Gb region size is a special case */
+
+  else
+    {
+      /* NOTE: There is no way to represent a 4Gb region size in the 32-bit
+       * input.
+       */
+
+      mask = 0x1fffffff;             /* Shifted mask */
+    }
+
+  asize = (size + mask) & ~mask; /* Adjusted size */
+  nsrs  = asize >> (lsize-3);    /* Number of subregions */
+  return g_regionmap[nsrs];
+}
+
+
+
diff --git a/nuttx/arch/arm/src/sam3u/Make.defs b/nuttx/arch/arm/src/sam3u/Make.defs
index 51e134d0b..05b27cb22 100755
--- a/nuttx/arch/arm/src/sam3u/Make.defs
+++ b/nuttx/arch/arm/src/sam3u/Make.defs
@@ -48,6 +48,12 @@ CMN_CSRCS	= up_assert.c up_blocktask.c up_copystate.c up_createstack.c \
 		  up_sigdeliver.c up_unblocktask.c up_usestack.c up_doirq.c \
 		  up_hardfault.c up_svcall.c
 
+# Configuration-dependent common files
+
+ifeq ($(CONFIG_NUTTX_KERNEL),y)
+CHIP_CSRCS	+= up_mpu.c
+endif
+
 # Required SAM3U files
 
 CHIP_ASRCS	= 
diff --git a/nuttx/arch/arm/src/sam3u/sam3u_mpuinit.c b/nuttx/arch/arm/src/sam3u/sam3u_mpuinit.c
index 411fba9b1..2dacd36c8 100755
--- a/nuttx/arch/arm/src/sam3u/sam3u_mpuinit.c
+++ b/nuttx/arch/arm/src/sam3u/sam3u_mpuinit.c
@@ -39,6 +39,7 @@
 
 #include <nuttx/config.h>
 #include <arch/board/user_map.h>
+#include "mpu.h"
 
 #ifndef CONFIG_NUTTX_KERNEL
 
@@ -46,6 +47,14 @@
  * Private Definitions
  ****************************************************************************/
 
+#ifndef MAX
+#  define MAX(a,b) a > b ? a : b
+#endif
+
+#ifndef MIN
+#  define MIN(a,b) a < b ? a : b
+#endif
+
 /****************************************************************************
  * Private Data
  ****************************************************************************/
@@ -69,7 +78,31 @@
 
 void sam3u_mpuinitialize(void)
 {
-# warning "Not implemented"
+  uintptr_t datastart = MIN(ONFIG_USER_DATADESTSTART, CONFIG_USER_BSSSTART);
+  uintptr_t dataend   = MAX(ONFIG_USER_DATADESTEND,   CONFIG_USER_BSSEND);
+
+  DEBUGASSERT(CONFIG_USER_TEXTEND >= CONFIG_USER_TEXTSTART && dataend >= datastart);
+
+	@echo "#define C     0x`grep \" _stext\"       $(TOPDIR)/User.map | cut -d' ' -f1`" >> $(BOARD_INCLUDE)/user_map.h
+	@echo "#define        0x`grep \" _etext$\"      $(TOPDIR)/User.map | cut -d' ' -f1`" >> $(BOARD_INCLUDE)/user_map.h
+	@echo "#define CONFIG_USER_DATASOURCE    0x`grep \" _eronly$\"    $(TOPDIR)/User.map | cut -d' ' -f1`" >> $(BOARD_INCLUDE)/user_map.h
+	@echo "#define C 0x`grep \" _sdata$\"     $(TOPDIR)/User.map | cut -d' ' -f1`" >> $(BOARD_INCLUDE)/user_map.h
+	@echo "#define CONFIG_USER_   0x`grep \" _edata$\"     $(TOPDIR)/User.map | cut -d' ' -f1`" >> $(BOARD_INCLUDE)/user_map.h
+	@echo "#define       0x`grep \" _sbss\"       $(TOPDIR)/User.map | cut -d' ' -f1`" >> $(BOARD_INCLUDE)/user_map.h
+	@echo "#define CONFIG_USER_        0x`grep \" _ebss$\"      $(TOPDIR)/User.map | cut -d' ' -f1`" >> $(BOARD_INCLUDE)/user_map.h
+
+  /* Show MPU information */
+
+  mpu_showtype();
+
+  /* Configure user flash and SRAM space */
+
+  mpu_userflash(0, CONFIG_USER_TEXTSTART, CONFIG_USER_TEXTEND - CONFIG_USER_TEXTSTART);
+  mpu_userintsram(1, datastart, dataend - datastart);
+
+  /* Then enable the MPU */
+
+  mpu_control(true, false, true);
 }
 
 #endif /* CONFIG_NUTTX_KERNEL */
diff --git a/nuttx/configs/sam3u-ek/kernel/Makefile b/nuttx/configs/sam3u-ek/kernel/Makefile
index ded4bfac5..c51271cc3 100755
--- a/nuttx/configs/sam3u-ek/kernel/Makefile
+++ b/nuttx/configs/sam3u-ek/kernel/Makefile
@@ -90,6 +90,8 @@ $(BOARD_INCLUDE)/user_map.h: $(TOPDIR)/User.map
 	@echo "/* General memory map */" >> $(BOARD_INCLUDE)/user_map.h
 	@echo "" >> $(BOARD_INCLUDE)/user_map.h
 	@echo "#define CONFIG_USER_ENTRYPOINT    0x`grep \" user_start$\" $(TOPDIR)/User.map | cut -d' ' -f1`" >> $(BOARD_INCLUDE)/user_map.h
+	@echo "#define CONFIG_USER_TEXTSTART     0x`grep \" _stext\"       $(TOPDIR)/User.map | cut -d' ' -f1`" >> $(BOARD_INCLUDE)/user_map.h
+	@echo "#define CONFIG_USER_TEXTEND       0x`grep \" _etext$\"      $(TOPDIR)/User.map | cut -d' ' -f1`" >> $(BOARD_INCLUDE)/user_map.h
 	@echo "#define CONFIG_USER_DATASOURCE    0x`grep \" _eronly$\"    $(TOPDIR)/User.map | cut -d' ' -f1`" >> $(BOARD_INCLUDE)/user_map.h
 	@echo "#define CONFIG_USER_DATADESTSTART 0x`grep \" _sdata$\"     $(TOPDIR)/User.map | cut -d' ' -f1`" >> $(BOARD_INCLUDE)/user_map.h
 	@echo "#define CONFIG_USER_DATADESTEND   0x`grep \" _edata$\"     $(TOPDIR)/User.map | cut -d' ' -f1`" >> $(BOARD_INCLUDE)/user_map.h