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authorpatacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3>2011-11-17 15:15:16 +0000
committerpatacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3>2011-11-17 15:15:16 +0000
commit8a522d4fe24273bf1d8d958c01285cf2b210c6aa (patch)
tree40b1a6fcf8cb02e112fdb5e9f47edb3ba66245c8
parentfe97ed6cb6b1cc99d3347ca6250511a90a989b07 (diff)
downloadnuttx-8a522d4fe24273bf1d8d958c01285cf2b210c6aa.tar.gz
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Add capabilities of the STM3240xx family
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4096 42af7a65-404d-4744-a932-0658087f49c3
-rw-r--r--nuttx/arch/arm/src/stm32/chip.h304
1 files changed, 293 insertions, 11 deletions
diff --git a/nuttx/arch/arm/src/stm32/chip.h b/nuttx/arch/arm/src/stm32/chip.h
index 23670cf10..ed3741b82 100644
--- a/nuttx/arch/arm/src/stm32/chip.h
+++ b/nuttx/arch/arm/src/stm32/chip.h
@@ -57,24 +57,31 @@
*/
#if defined(CONFIG_ARCH_CHIP_STM32F103ZET6)
-# undef CONFIG_STM32_LOWDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
+# undef CONFIG_STM32_LOWDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# define CONFIG_STM32_HIGHDENSITY 1 /* STM32F101x and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
+# undef CONFIG_STM32_STM3240XX /* STM32F405xx and STM32407xx */
+# define STM32_NFSMC 1 /* FSMC */
# define STM32_NATIM 1 /* One advanced timer TIM1 */
-# define STM32_NGTIM 4 /* General timers TIM2,3,4,5 */
+# define STM32_NGTIM 4 /* 16-bit generall timers TIM2,3,4,5 with DMA */
+# define STM32_NGTIM32 0 /* No 32-bit General timers */
# define STM32 NBTIM 0 /* No basic timers */
# define STM32_NDMA 2 /* DMA1-2 */
# define STM32_NSPI 2 /* SPI1-2 */
+# define STM32_NI2S 0 /* No I2S (?) */
# define STM32_NUSART 3 /* USART1-3 */
# define STM32_NI2C 2 /* I2C1-2 */
-# define STM32_NCAN 1 /* bxCAN1 */
+# define STM32_NCAN 1 /* CAN1 */
# define STM32_NSDIO 1 /* SDIO */
+# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */
# define STM32_NGPIO 112 /* GPIOA-G */
# define STM32_NADC 1 /* ADC1 */
# define STM32_NDAC 0 /* No DAC */
# define STM32_NCRC 0 /* No CRC */
# define STM32_NTHERNET 0 /* No ethernet */
+# define STM32_NRNG 0 /* No random number generator (RNG) */
+# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
# include "chip/stm32f103ze_pinmap.h"
#elif defined(CONFIG_ARCH_CHIP_STM32F103RET6)
@@ -82,43 +89,318 @@
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# define CONFIG_STM32_HIGHDENSITY 1 /* STM32F101x and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
+# undef CONFIG_STM32_STM3240XX /* STM32F405xx and STM32407xx */
+# define STM32_NFSMC 1 /* FSMC */
# define STM32_NATIM 2 /* Two advanced timers TIM1 and TIM8 */
-# define STM32_NGTIM 4 /* General timers TIM2,3,4,5 */
+# define STM32_NGTIM 4 /* 16-bit generall timers TIM2,3,4,5 with DMA */
+# define STM32_NGTIM32 0 /* No 32-bit General timers */
# define STM32_NBTIM 2 /* Two basic timers TIM6 and TIM7 */
# define STM32_NDMA 2 /* DMA1-2 */
# define STM32_NSPI 3 /* SPI1-3 */
+# define STM32_NI2S 0 /* No I2S (?) */
# define STM32_NUSART 5 /* USART1-5 */
# define STM32_NI2C 2 /* I2C1-2 */
-# define STM32_NCAN 1 /* bxCAN1 */
+# define STM32_NCAN 1 /* CAN1 */
# define STM32_NSDIO 1 /* SDIO */
+# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */
# define STM32_NGPIO 51 /* GPIOA-D */
# define STM32_NADC 2 /* ADC1-2 */
# define STM32_NDAC 2 /* DAC1-2 */
# define STM32_NCRC 1 /* CRC */
# define STM32_NTHERNET 0 /* No ethernet */
+# define STM32_NRNG 0 /* No random number generator (RNG) */
+# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
# include "chip/stm32f103re_pinmap.h"
#elif defined(CONFIG_ARCH_CHIP_STM32F107VC)
-# undef CONFIG_STM32_LOWDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
+# undef CONFIG_STM32_LOWDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
-# undef CONFIG_STM32_HIGHDENSITY /* STM32F101x and STM32F103x w/ 256/512 Kbytes */
-# define CONFIG_STM32_CONNECTIVITYLINE 1 /* STM32F105x and STM32F107x */
+# undef CONFIG_STM32_HIGHDENSITY /* STM32F101x and STM32F103x w/ 256/512 Kbytes */
+# define CONFIG_STM32_CONNECTIVITYLINE 1 /* STM32F105x and STM32F107x */
+# undef CONFIG_STM32_STM3240XX /* STM32F405xx and STM32407xx */
+# define STM32_NFSMC 1 /* FSMC */
# define STM32_NATIM 1 /* One advanced timers TIM1 */
-# define STM32_NGTIM 4 /* General timers TIM2,3,4,5 */
+# define STM32_NGTIM 4 /* 16-bit generall timers TIM2,3,4,5 with DMA */
+# define STM32_NGTIM32 0 /* No 32-bit General timers */
# define STM32 NBTIM 2 /* Two basic timers, TIM6-7 */
# define STM32_NDMA 2 /* DMA1-2 */
-# define STM32_NSPI 3 /* SPI1-3 I2S1-2 */
+# define STM32_NSPI 3 /* SPI1-3 */
+# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
# define STM32_NUSART 5 /* USART1-3, UART 4-5 */
# define STM32_NI2C 1 /* I2C1 */
-# define STM32_NCAN 2 /* bxCAN1-2 */
+# define STM32_NCAN 2 /* CAN1-2 */
# define STM32_NSDIO 0 /* No SDIO */
+# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */
# define STM32_NGPIO 80 /* GPIOA-E */
# define STM32_NADC 2 /* ADC1-2*/
# define STM32_NDAC 2 /* DAC1-2 */
# define STM32_NCRC 1 /* CRC */
# define STM32_NTHERNET 1 /* 100/100 Ethernet MAC */
+# define STM32_NRNG 0 /* No random number generator (RNG) */
+# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
# include "chip/stm32f107vc_pinmap.h"
+#elif defined(CONFIG_ARCH_CHIP_STM32F405RG) /* LQFP 64 10x10x1.4 1024Kb FLASH 192Kb SRAM */
+# undef CONFIG_STM32_LOWDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
+# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
+# undef CONFIG_STM32_HIGHDENSITY /* STM32F101x and STM32F103x w/ 256/512 Kbytes */
+# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
+# define CONFIG_STM32_STM3240XX 1 /* STM32F405xx and STM32407xx */
+# define STM32_NFSMC 0 /* No FSMC */
+# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
+# define STM32_NGTIM 2 /* 16-bit general timers TIM3 and 4 with DMA */
+# define STM32_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */
+# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
+# define STM32 NBTIM 2 /* Two basic timers, TIM6-7 */
+# define STM32_NDMA 2 /* DMA1-2 */
+# define STM32_NSPI 3 /* SPI1-3 */
+# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
+# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */
+# define STM32_NI2C 3 /* I2C1-3 */
+# define STM32_NCAN 2 /* CAN1-2 */
+# define STM32_NSDIO 1 /* SDIO */
+# define STM32_NUSBOTG 1 /* USB OTG FS/HS */
+# define STM32_NGPIO 144 /* GPIOA-I */
+# define STM32_NADC 3 /* 12-bit ADC1-3, 16 channels */
+# define STM32_NDAC 2 /* 12-bit DAC1-2 */
+# define STM32_NCRC 1 /* CRC */
+# define STM32_NTHERNET 0 /* No Ethernet MAC */
+# define STM32_NRNG 1 /* Random number generator (RNG) */
+# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
+# include "chip/stm32f405rg_pinmap.h"
+
+#elif defined(CONFIG_ARCH_CHIP_STM32F405VG) /* LQFP 100 14x14x1.4 1024Kb FLASH 192Kb SRAM */
+# undef CONFIG_STM32_LOWDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
+# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
+# undef CONFIG_STM32_HIGHDENSITY /* STM32F101x and STM32F103x w/ 256/512 Kbytes */
+# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
+# define CONFIG_STM32_STM3240XX 1 /* STM32F405xx and STM32407xx */
+# define STM32_NFSMC 1 /* FSMC */
+# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
+# define STM32_NGTIM 2 /* 16-bit general timers TIM3 and 4 with DMA */
+# define STM32_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */
+# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
+# define STM32 NBTIM 2 /* Two basic timers, TIM6-7 */
+# define STM32_NDMA 2 /* DMA1-2 */
+# define STM32_NSPI 3 /* SPI1-3 */
+# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
+# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */
+# define STM32_NI2C 3 /* I2C1-3 */
+# define STM32_NCAN 2 /* CAN1-2 */
+# define STM32_NSDIO 1 /* SDIO */
+# define STM32_NUSBOTG 1 /* USB OTG FS/HS */
+# define STM32_NGPIO 144 /* GPIOA-I */
+# define STM32_NADC 3 /* 12-bit ADC1-3, 16 channels */
+# define STM32_NDAC 2 /* 12-bit DAC1-2 */
+# define STM32_NCRC 1 /* CRC */
+# define STM32_NTHERNET 0 /* No Ethernet MAC */
+# define STM32_NRNG 1 /* Random number generator (RNG) */
+# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
+# include "chip/stm32f405vg_pinmap.h"
+
+#elif defined(CONFIG_ARCH_CHIP_STM32F405ZG) /* LQFP 144 20x20x1.4 1024Kb FLASH 192Kb SRAM */
+# undef CONFIG_STM32_LOWDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
+# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
+# undef CONFIG_STM32_HIGHDENSITY /* STM32F101x and STM32F103x w/ 256/512 Kbytes */
+# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
+# define CONFIG_STM32_STM3240XX 1 /* STM32F405xx and STM32407xx */
+# define STM32_NFSMC 1 /* FSMC */
+# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
+# define STM32_NGTIM 2 /* 16-bit general timers TIM3 and 4 with DMA */
+# define STM32_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */
+# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
+# define STM32 NBTIM 2 /* Two basic timers, TIM6-7 */
+# define STM32_NDMA 2 /* DMA1-2 */
+# define STM32_NSPI 3 /* SPI1-3 */
+# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
+# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */
+# define STM32_NI2C 3 /* I2C1-3 */
+# define STM32_NCAN 2 /* CAN1-2 */
+# define STM32_NSDIO 1 /* SDIO */
+# define STM32_NUSBOTG 1 /* USB OTG FS/HS */
+# define STM32_NGPIO 144 /* GPIOA-I */
+# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */
+# define STM32_NDAC 2 /* 12-bit DAC1-2 */
+# define STM32_NCRC 1 /* CRC */
+# define STM32_NTHERNET 0 /* No Ethernet MAC */
+# define STM32_NRNG 1 /* Random number generator (RNG) */
+# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
+# include "chip/stm32f405zg_pinmap.h"
+
+#elif defined(CONFIG_ARCH_CHIP_STM32F407VE) /* LQFP-100 512Kb FLASH 192Kb SRAM */
+# undef CONFIG_STM32_LOWDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
+# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
+# undef CONFIG_STM32_HIGHDENSITY /* STM32F101x and STM32F103x w/ 256/512 Kbytes */
+# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
+# define CONFIG_STM32_STM3240XX 1 /* STM32F405xx and STM32407xx */
+# define STM32_NFSMC 1 /* FSMC */
+# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
+# define STM32_NGTIM 2 /* 16-bit general timers TIM3 and 4 with DMA */
+# define STM32_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */
+# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
+# define STM32 NBTIM 2 /* Two basic timers, TIM6-7 */
+# define STM32_NDMA 2 /* DMA1-2 */
+# define STM32_NSPI 3 /* SPI1-3 */
+# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
+# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */
+# define STM32_NI2C 3 /* I2C1-3 */
+# define STM32_NCAN 2 /* CAN1-2 */
+# define STM32_NSDIO 1 /* SDIO */
+# define STM32_NUSBOTG 1 /* USB OTG FS/HS */
+# define STM32_NGPIO 144 /* GPIOA-I */
+# define STM32_NADC 3 /* 12-bit ADC1-3, 16 channels */
+# define STM32_NDAC 2 /* 12-bit DAC1-2 */
+# define STM32_NCRC 1 /* CRC */
+# define STM32_NTHERNET 1 /* 100/100 Ethernet MAC */
+# define STM32_NRNG 1 /* Random number generator (RNG) */
+# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */
+# include "chip/stm32f407ve_pinmap.h"
+
+#elif defined(CONFIG_ARCH_CHIP_STM32F407VG) /* LQFP-100 14x14x1.4 1024Kb FLASH 192Kb SRAM */
+# undef CONFIG_STM32_LOWDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
+# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
+# undef CONFIG_STM32_HIGHDENSITY /* STM32F101x and STM32F103x w/ 256/512 Kbytes */
+# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
+# define CONFIG_STM32_STM3240XX 1 /* STM32F405xx and STM32407xx */
+# define STM32_NFSMC 1 /* FSMC */
+# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
+# define STM32_NGTIM 2 /* 16-bit general timers TIM3 and 4 with DMA */
+# define STM32_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */
+# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
+# define STM32 NBTIM 2 /* Two basic timers, TIM6-7 */
+# define STM32_NDMA 2 /* DMA1-2 */
+# define STM32_NSPI 3 /* SPI1-3 */
+# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
+# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */
+# define STM32_NI2C 3 /* I2C1-3 */
+# define STM32_NCAN 2 /* CAN1-2 */
+# define STM32_NSDIO 1 /* SDIO */
+# define STM32_NUSBOTG 1 /* USB OTG FS/HS */
+# define STM32_NGPIO 144 /* GPIOA-I */
+# define STM32_NADC 3 /* 12-bit ADC1-3, 16 channels */
+# define STM32_NDAC 2 /* 12-bit DAC1-2 */
+# define STM32_NCRC 1 /* CRC */
+# define STM32_NTHERNET 1 /* 100/100 Ethernet MAC */
+# define STM32_NRNG 1 /* Random number generator (RNG) */
+# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */
+# include "chip/stm32f407vg_pinmap.h"
+
+#elif defined(CONFIG_ARCH_CHIP_STM32F407ZE) /* LQFP-144 512Kb FLASH 192Kb SRAM */
+# undef CONFIG_STM32_LOWDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
+# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
+# undef CONFIG_STM32_HIGHDENSITY /* STM32F101x and STM32F103x w/ 256/512 Kbytes */
+# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
+# define CONFIG_STM32_STM3240XX 1 /* STM32F405xx and STM32407xx */
+# define STM32_NFSMC 1 /* FSMC */
+# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
+# define STM32_NGTIM 2 /* 16-bit general timers TIM3 and 4 with DMA */
+# define STM32_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */
+# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
+# define STM32 NBTIM 2 /* Two basic timers, TIM6-7 */
+# define STM32_NDMA 2 /* DMA1-2 */
+# define STM32_NSPI 3 /* SPI1-3 */
+# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
+# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */
+# define STM32_NI2C 3 /* I2C1-3 */
+# define STM32_NCAN 2 /* CAN1-2 */
+# define STM32_NSDIO 1 /* SDIO */
+# define STM32_NUSBOTG 1 /* USB OTG FS/HS */
+# define STM32_NGPIO 144 /* GPIOA-I */
+# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */
+# define STM32_NDAC 2 /* 12-bit DAC1-2 */
+# define STM32_NCRC 1 /* CRC */
+# define STM32_NTHERNET 1 /* 100/100 Ethernet MAC */
+# define STM32_NRNG 1 /* Random number generator (RNG) */
+# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */
+# include "chip/stm32f407ze_pinmap.h"
+
+#elif defined(CONFIG_ARCH_CHIP_STM32F407ZG) /* LQFP 144 20x20x1.4 1024Kb FLASH 192Kb SRAM */
+# undef CONFIG_STM32_LOWDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
+# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
+# undef CONFIG_STM32_HIGHDENSITY /* STM32F101x and STM32F103x w/ 256/512 Kbytes */
+# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
+# define CONFIG_STM32_STM3240XX 1 /* STM32F405xx and STM32407xx */
+# define STM32_NFSMC 1 /* FSMC */
+# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
+# define STM32_NGTIM 2 /* 16-bit general timers TIM3 and 4 with DMA */
+# define STM32_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */
+# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
+# define STM32 NBTIM 2 /* Two basic timers, TIM6-7 */
+# define STM32_NDMA 2 /* DMA1-2 */
+# define STM32_NSPI 3 /* SPI1-3 */
+# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
+# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */
+# define STM32_NI2C 3 /* I2C1-3 */
+# define STM32_NCAN 2 /* CAN1-2 */
+# define STM32_NSDIO 1 /* SDIO */
+# define STM32_NUSBOTG 1 /* USB OTG FS/HS */
+# define STM32_NGPIO 144 /* GPIOA-I */
+# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */
+# define STM32_NDAC 2 /* 12-bit DAC1-2 */
+# define STM32_NCRC 1 /* CRC */
+# define STM32_NTHERNET 1 /* 100/100 Ethernet MAC */
+# define STM32_NRNG 1 /* Random number generator (RNG) */
+# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */
+# include "chip/stm32f407zg_pinmap.h"
+
+#elif defined(CONFIG_ARCH_CHIP_STM32F407IE) /* LQFP 176 24x24x1.4 512Kb FLASH 192Kb SRAM */
+# undef CONFIG_STM32_LOWDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
+# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
+# undef CONFIG_STM32_HIGHDENSITY /* STM32F101x and STM32F103x w/ 256/512 Kbytes */
+# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
+# define CONFIG_STM32_STM3240XX 1 /* STM32F405xx and STM32407xx */
+# define STM32_NFSMC 1 /* FSMC */
+# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
+# define STM32_NGTIM 2 /* 16-bit general timers TIM3 and 4 with DMA */
+# define STM32_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */
+# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
+# define STM32 NBTIM 2 /* Two basic timers, TIM6-7 */
+# define STM32_NDMA 2 /* DMA1-2 */
+# define STM32_NSPI 3 /* SPI1-3 */
+# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
+# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 (?) */
+# define STM32_NI2C 3 /* I2C1-3 */
+# define STM32_NCAN 2 /* CAN1-2 */
+# define STM32_NSDIO 1 /* SDIO */
+# define STM32_NUSBOTG 1 /* USB OTG FS/HS */
+# define STM32_NGPIO 144 /* GPIOA-I */
+# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */
+# define STM32_NDAC 2 /* 12-bit DAC1-2 */
+# define STM32_NCRC 1 /* CRC */
+# define STM32_NTHERNET 1 /* 100/100 Ethernet MAC */
+# define STM32_NRNG 1 /* Random number generator (RNG) */
+# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */
+# include "chip/stm32f407ie_pinmap.h"
+
+#elif defined(CONFIG_ARCH_CHIP_STM32F407IG) /* BGA 176; LQFP 176 24x24x1.4 1024Kb FLASH 192Kb SRAM */
+# undef CONFIG_STM32_LOWDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
+# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
+# undef CONFIG_STM32_HIGHDENSITY /* STM32F101x and STM32F103x w/ 256/512 Kbytes */
+# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
+# define CONFIG_STM32_STM3240XX 1 /* STM32F405xx and STM32407xx */
+# define STM32_NFSMC 1 /* FSMC */
+# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
+# define STM32_NGTIM 2 /* 16-bit general timers TIM3 and 4 with DMA */
+# define STM32_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */
+# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
+# define STM32 NBTIM 2 /* Two basic timers, TIM6-7 */
+# define STM32_NDMA 2 /* DMA1-2 */
+# define STM32_NSPI 3 /* SPI1-3 */
+# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
+# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */
+# define STM32_NI2C 3 /* I2C1-3 */
+# define STM32_NCAN 2 /* CAN1-2 */
+# define STM32_NSDIO 1 /* SDIO */
+# define STM32_NUSBOTG 1 /* USB OTG FS/HS */
+# define STM32_NGPIO 144 /* GPIOA-I */
+# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */
+# define STM32_NDAC 2 /* 12-bit DAC1-2 */
+# define STM32_NCRC 1 /* CRC */
+# define STM32_NTHERNET 1 /* 100/100 Ethernet MAC */
+# define STM32_NRNG 1 /* Random number generator (RNG) */
+# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */
+# include "chip/stm32f407ig_pinmap.h"
+
#else
# error "Unsupported STM32 chip"
#endif