diff options
| author | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2011-04-15 16:20:25 +0000 |
|---|---|---|
| committer | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2011-04-15 16:20:25 +0000 |
| commit | 3a3fe9efb1e3f0fe6a756b8e4d2fa48d5564137b (patch) | |
| tree | 13d2c82c982b760b250741f7167faf0d509ecbc4 | |
| parent | f1893cbaf513c7f0fbca77240fc59707ad039734 (diff) | |
| download | nuttx-3a3fe9efb1e3f0fe6a756b8e4d2fa48d5564137b.tar.gz nuttx-3a3fe9efb1e3f0fe6a756b8e4d2fa48d5564137b.tar.bz2 nuttx-3a3fe9efb1e3f0fe6a756b8e4d2fa48d5564137b.zip | |
Add code changes from Uros
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3507 42af7a65-404d-4744-a932-0658087f49c3
33 files changed, 2047 insertions, 1115 deletions
diff --git a/apps/vsn/Makefile b/apps/vsn/Makefile index 123df2747..8917ef147 100644 --- a/apps/vsn/Makefile +++ b/apps/vsn/Makefile @@ -37,7 +37,7 @@ # Sub-directories -SUBDIRS = free hello poweroff ramtron sdcard +SUBDIRS = free hello poweroff ramtron sdcard sysinfo all: nothing .PHONY: nothing context depend clean distclean diff --git a/apps/vsn/sysinfo/Makefile b/apps/vsn/sysinfo/Makefile new file mode 100644 index 000000000..f0aac6df2 --- /dev/null +++ b/apps/vsn/sysinfo/Makefile @@ -0,0 +1,114 @@ +############################################################################ +# Makefile +# +# Copyright (C) 2011 Uros Platise. All rights reserved. +# Author: Uros Platise <uros.platise@isotel.eu> +# Gregory Nutt <spudmonkey@racsa.co.cr> +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +# TODO, this makefile should run make under the app dirs, instead of +# sourcing the Make.defs! + +-include $(TOPDIR)/.config +-include $(TOPDIR)/Make.defs +include $(APPDIR)/Make.defs + +ifeq ($(WINTOOL),y) +INCDIROPT = -w +endif + +# Hello Application +# TODO: appname can be automatically extracted from the directory name + +APPNAME = sysinfo +PRIORITY = SCHED_PRIORITY_DEFAULT +STACKSIZE = 768 + +ASRCS = +CSRCS = sysinfo.c + +AOBJS = $(ASRCS:.S=$(OBJEXT)) +COBJS = $(CSRCS:.c=$(OBJEXT)) + +SRCS = $(ASRCS) $(CSRCS) +OBJS = $(AOBJS) $(COBJS) + +ifeq ($(WINTOOL),y) + BIN = "${shell cygpath -w $(APPDIR)/libapps$(LIBEXT)}" +else + BIN = "$(APPDIR)/libapps$(LIBEXT)" +endif + +ROOTDEPPATH = --dep-path . + +# Common build + +VPATH = + +all: .built +.PHONY: context depend clean distclean + +$(AOBJS): %$(OBJEXT): %.S + $(call ASSEMBLE, $<, $@) + +$(COBJS): %$(OBJEXT): %.c + $(call COMPILE, $<, $@) + +.built: $(OBJS) + @( for obj in $(OBJS) ; do \ + $(call ARCHIVE, $(BIN), $${obj}); \ + done ; ) + @touch .built + +# Register application + +.context: + $(call REGISTER,$(APPNAME),$(PRIORITY),$(STACKSIZE),$(APPNAME)_main) + @touch $@ + +context: .context + +# Create dependencies + +.depend: Makefile $(SRCS) + @$(MKDEP) $(ROOTDEPPATH) $(CC) -- $(CFLAGS) -- $(SRCS) >Make.dep + @touch $@ + +depend: .depend + +clean: + @rm -f *.o *~ .*.swp .built + $(call CLEAN) + +distclean: clean + @rm -f .context Make.dep .depend + +-include Make.dep diff --git a/apps/vsn/sysinfo/README.txt b/apps/vsn/sysinfo/README.txt new file mode 100644 index 000000000..3792f4a59 --- /dev/null +++ b/apps/vsn/sysinfo/README.txt @@ -0,0 +1,6 @@ + +This application provides access to System Information + + Source: NuttX + Date: 15. April 2011 + Author: Uros Platise <uros.platise@isotel.eu> diff --git a/apps/vsn/sysinfo/sysinfo.c b/apps/vsn/sysinfo/sysinfo.c new file mode 100644 index 000000000..8625f9db7 --- /dev/null +++ b/apps/vsn/sysinfo/sysinfo.c @@ -0,0 +1,69 @@ +/**************************************************************************** + * sysinfo/sysinfo.c + * + * Copyright (C) 2011 Uros Platise. All rights reserved. + * Author: Uros Platise <uros.platise@isotel.eu> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/** \file + * \brief System Information + * \author Uros Platise + * + * Collects and reports system information. + * + * \todo Gather information also from low-level devices, kernel/sched, clock, + * and further reporting as: sysinfo rtc, or sysinfo sched, ... with + * sysinfo help to report all of the options. + * + **/ + +#include <nuttx/config.h> +#include <nuttx/version.h> +#include <time.h> + +#include <stdio.h> +#include <stdlib.h> + + +int sysinfo_main(int argc, char *argv[]) +{ + printf("System Information:\n"); + + printf("\tNuttX Version:\t" CONFIG_VERSION_STRING " Build: %d\n", CONFIG_VERSION_BUILD); + + printf("\tSystem Time:\t%d [s] UTC " +#ifdef CONFIG_RTC + "Hardware RTC Support" +#endif + "\n", time(NULL) ); + + return 0; +} diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index 376134725..7760d52ea 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -1693,5 +1693,8 @@ character in the string. * tools/version.sh and mkversion.c: Tools to manage a NuttX version number file + * sched/clock_uptime() and lib/time/lib_time.c: Add support for 1 second uptime + interface. + diff --git a/nuttx/arch/arm/src/stm32/Make.defs b/nuttx/arch/arm/src/stm32/Make.defs index 4b6228b0c..6b0114dcb 100755 --- a/nuttx/arch/arm/src/stm32/Make.defs +++ b/nuttx/arch/arm/src/stm32/Make.defs @@ -48,5 +48,5 @@ CHIP_ASRCS = CHIP_CSRCS = stm32_start.c stm32_rcc.c stm32_gpio.c stm32_idle.c \ stm32_irq.c stm32_timerisr.c stm32_dma.c stm32_lowputc.c \ stm32_serial.c stm32_spi.c stm32_usbdev.c stm32_sdio.c \ - stm32_tim.c stm32_i2c.c stm32_waste.c + stm32_tim.c stm32_i2c.c stm32_pwr.c stm32_rtc.c stm32_waste.c diff --git a/nuttx/arch/arm/src/stm32/chip/stm32_bkp.h b/nuttx/arch/arm/src/stm32/chip/stm32_bkp.h new file mode 100644 index 000000000..1788bdee0 --- /dev/null +++ b/nuttx/arch/arm/src/stm32/chip/stm32_bkp.h @@ -0,0 +1,190 @@ +/************************************************************************************ + * arch/arm/src/stm32/chip/stm32_bkp.h + * + * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32_BKP_H +#define __ARCH_ARM_SRC_STM32_CHIP_STM32_BKP_H + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +#if defined(CONFIG_STM32_HIGHDENSITY) || defined(CONFIG_STM32_CONNECTIVITYLINE) +# define CONFIG_STM32_NBKP_BYTES 84 +# define CONFIG_STM32_NBKP_REGS 42 +#else +# define CONFIG_STM32_NBKP_BYTES 20 +# define CONFIG_STM32_NBKP_REGS 10 +#endif + +/* Register Offsets *****************************************************************/ + +#if defined(CONFIG_STM32_HIGHDENSITY) || defined(CONFIG_STM32_CONNECTIVITYLINE) +# define STM32_BKP_DR_OFFSET(n) ((n) > 10 ? 0x0040+4*((n)-10) : 0x0004+4*(n)) +#else +# define STM32_BKP_DR_OFFSET(n) (0x0004+4*(n)) +#endif + +#define STM32_BKP_DR1_OFFSET 0x0004 /* Backup data register 1 */ +#define STM32_BKP_DR2_OFFSET 0x0008 /* Backup data register 2 */ +#define STM32_BKP_DR3_OFFSET 0x000c /* Backup data register 3 */ +#define STM32_BKP_DR4_OFFSET 0x0010 /* Backup data register 4 */ +#define STM32_BKP_DR5_OFFSET 0x0014 /* Backup data register 5 */ +#define STM32_BKP_DR6_OFFSET 0x0018 /* Backup data register 6 */ +#define STM32_BKP_DR7_OFFSET 0x001c /* Backup data register 7 */ +#define STM32_BKP_DR8_OFFSET 0x0020 /* Backup data register 8 */ +#define STM32_BKP_DR9_OFFSET 0x0024 /* Backup data register 9 */ +#define STM32_BKP_DR10_OFFSET 0x0028 /* Backup data register 10 */ + +#define STM32_BKP_RTCCR_OFFSET 0x002c /* RTC clock calibration register */ +#define STM32_BKP_CR_OFFSET 0x0030 /* Backup control register */ +#define STM32_BKP_CSR_OFFSET 0x0034 /* Backup control/status register */ + +#if defined(CONFIG_STM32_HIGHDENSITY) || defined(CONFIG_STM32_CONNECTIVITYLINE) +# define STM32_BKP_DR11_OFFSET 0x0040 /* Backup data register 11 */ +# define STM32_BKP_DR12_OFFSET 0x0044 /* Backup data register 12 */ +# define STM32_BKP_DR13_OFFSET 0x0048 /* Backup data register 13 */ +# define STM32_BKP_DR14_OFFSET 0x004c /* Backup data register 14 */ +# define STM32_BKP_DR15_OFFSET 0x0050 /* Backup data register 15 */ +# define STM32_BKP_DR16_OFFSET 0x0054 /* Backup data register 16 */ +# define STM32_BKP_DR17_OFFSET 0x0058 /* Backup data register 17 */ +# define STM32_BKP_DR18_OFFSET 0x005c /* Backup data register 18 */ +# define STM32_BKP_DR19_OFFSET 0x0060 /* Backup data register 19 */ +# define STM32_BKP_DR20_OFFSET 0x0064 /* Backup data register 20 */ +# define STM32_BKP_DR21_OFFSET 0x0068 /* Backup data register 21 */ +# define STM32_BKP_DR22_OFFSET 0x006c /* Backup data register 22 */ +# define STM32_BKP_DR23_OFFSET 0x0070 /* Backup data register 23 */ +# define STM32_BKP_DR24_OFFSET 0x0074 /* Backup data register 24 */ +# define STM32_BKP_DR25_OFFSET 0x0078 /* Backup data register 25 */ +# define STM32_BKP_DR26_OFFSET 0x007c /* Backup data register 26 */ +# define STM32_BKP_DR27_OFFSET 0x0080 /* Backup data register 27 */ +# define STM32_BKP_DR28_OFFSET 0x0084 /* Backup data register 28 */ +# define STM32_BKP_DR29_OFFSET 0x0088 /* Backup data register 29 */ +# define STM32_BKP_DR30_OFFSET 0x008c /* Backup data register 30 */ +# define STM32_BKP_DR31_OFFSET 0x0090 /* Backup data register 31 */ +# define STM32_BKP_DR32_OFFSET 0x0094 /* Backup data register 32 */ +# define STM32_BKP_DR33_OFFSET 0x0098 /* Backup data register 33 */ +# define STM32_BKP_DR34_OFFSET 0x009c /* Backup data register 34 */ +# define STM32_BKP_DR35_OFFSET 0x00a0 /* Backup data register 35 */ +# define STM32_BKP_DR36_OFFSET 0x00a4 /* Backup data register 36 */ +# define STM32_BKP_DR37_OFFSET 0x00a8 /* Backup data register 37 */ +# define STM32_BKP_DR38_OFFSET 0x00ac /* Backup data register 38 */ +# define STM32_BKP_DR39_OFFSET 0x00b0 /* Backup data register 39 */ +# define STM32_BKP_DR40_OFFSET 0x00b4 /* Backup data register 40 */ +# define STM32_BKP_DR41_OFFSET 0x00b8 /* Backup data register 41 */ +# define STM32_BKP_DR42_OFFSET 0x00bc /* Backup data register 42 */ +#endif + +/* Register Addresses ***************************************************************/ + +#define STM32_BKP_RTCCR (STM32_BKP_BASE+STM32_BKP_RTCCR_OFFSET) +#define STM32_BKP_CR (STM32_BKP_BASE+STM32_BKP_CR_OFFSET) +#define STM32_BKP_CSR (STM32_BKP_BASE+STM32_BKP_CSR_OFFSET) + +#define STM32_BKP_DR(n) (STM32_BKP_BASE+STM32_BKP_DR_OFFSET(n)) +#define STM32_BKP_DR1 (STM32_BKP_BASE+STM32_BKP_DR1_OFFSET) +#define STM32_BKP_DR2 (STM32_BKP_BASE+STM32_BKP_DR2_OFFSET) +#define STM32_BKP_DR3 (STM32_BKP_BASE+STM32_BKP_DR3_OFFSET) +#define STM32_BKP_DR4 (STM32_BKP_BASE+STM32_BKP_DR4_OFFSET) +#define STM32_BKP_DR5 (STM32_BKP_BASE+STM32_BKP_DR5_OFFSET) +#define STM32_BKP_DR6 (STM32_BKP_BASE+STM32_BKP_DR6_OFFSET) +#define STM32_BKP_DR7 (STM32_BKP_BASE+STM32_BKP_DR7_OFFSET) +#define STM32_BKP_DR8 (STM32_BKP_BASE+STM32_BKP_DR8_OFFSET) +#define STM32_BKP_DR9 (STM32_BKP_BASE+STM32_BKP_DR9_OFFSET) +#define STM32_BKP_DR10 (STM32_BKP_BASE+STM32_BKP_DR10_OFFSET) + +#if defined(CONFIG_STM32_HIGHDENSITY) || defined(CONFIG_STM32_CONNECTIVITYLINE) +# define STM32_BKP_DR11 (STM32_BKP_BASE+STM32_BKP_DR11_OFFSET) +# define STM32_BKP_DR12 (STM32_BKP_BASE+STM32_BKP_DR12_OFFSET) +# define STM32_BKP_DR13 (STM32_BKP_BASE+STM32_BKP_DR13_OFFSET) +# define STM32_BKP_DR14 (STM32_BKP_BASE+STM32_BKP_DR14_OFFSET) +# define STM32_BKP_DR15 (STM32_BKP_BASE+STM32_BKP_DR15_OFFSET) +# define STM32_BKP_DR16 (STM32_BKP_BASE+STM32_BKP_DR16_OFFSET) +# define STM32_BKP_DR17 (STM32_BKP_BASE+STM32_BKP_DR17_OFFSET) +# define STM32_BKP_DR18 (STM32_BKP_BASE+STM32_BKP_DR18_OFFSET) +# define STM32_BKP_DR19 (STM32_BKP_BASE+STM32_BKP_DR19_OFFSET) +# define STM32_BKP_DR20 (STM32_BKP_BASE+STM32_BKP_DR20_OFFSET) +# define STM32_BKP_DR21 (STM32_BKP_BASE+STM32_BKP_DR21_OFFSET) +# define STM32_BKP_DR22 (STM32_BKP_BASE+STM32_BKP_DR22_OFFSET) +# define STM32_BKP_DR23 (STM32_BKP_BASE+STM32_BKP_DR23_OFFSET) +# define STM32_BKP_DR24 (STM32_BKP_BASE+STM32_BKP_DR24_OFFSET) +# define STM32_BKP_DR25 (STM32_BKP_BASE+STM32_BKP_DR25_OFFSET) +# define STM32_BKP_DR26 (STM32_BKP_BASE+STM32_BKP_DR26_OFFSET) +# define STM32_BKP_DR27 (STM32_BKP_BASE+STM32_BKP_DR27_OFFSET) +# define STM32_BKP_DR28 (STM32_BKP_BASE+STM32_BKP_DR28_OFFSET) +# define STM32_BKP_DR29 (STM32_BKP_BASE+STM32_BKP_DR29_OFFSET) +# define STM32_BKP_DR30 (STM32_BKP_BASE+STM32_BKP_DR30_OFFSET) +# define STM32_BKP_DR31 (STM32_BKP_BASE+STM32_BKP_DR31_OFFSET) +# define STM32_BKP_DR32 (STM32_BKP_BASE+STM32_BKP_DR32_OFFSET) +# define STM32_BKP_DR33 (STM32_BKP_BASE+STM32_BKP_DR33_OFFSET) +# define STM32_BKP_DR34 (STM32_BKP_BASE+STM32_BKP_DR34_OFFSET) +# define STM32_BKP_DR35 (STM32_BKP_BASE+STM32_BKP_DR35_OFFSET) +# define STM32_BKP_DR36 (STM32_BKP_BASE+STM32_BKP_DR36_OFFSET) +# define STM32_BKP_DR37 (STM32_BKP_BASE+STM32_BKP_DR37_OFFSET) +# define STM32_BKP_DR38 (STM32_BKP_BASE+STM32_BKP_DR38_OFFSET) +# define STM32_BKP_DR39 (STM32_BKP_BASE+STM32_BKP_DR39_OFFSET) +# define STM32_BKP_DR40 (STM32_BKP_BASE+STM32_BKP_DR40_OFFSET) +# define STM32_BKP_DR41 (STM32_BKP_BASE+STM32_BKP_DR41_OFFSET) +# define STM32_BKP_DR42 (STM32_BKP_BASE+STM32_BKP_DR42_OFFSET) +#endif + +/* Register Bitfield Definitions ****************************************************/ + +/* RTC clock calibration register */ + +#define BKP_RTCCR_CAL_SHIFT (0) /* Bits 6-0: Calibration value */ +#define BKP_RTCCR_CAL_MASK (0x7f << BKP_RTCCR_CAL_SHIFT) +#define BKP_RTCCR_CCO (1 << 7) /* Bit 7: Calibration Clock Output */ +#define BKP_RTCCR_ASOE (1 << 8) /* Bit 8: Alarm or Second Output Enable */ +#define BKP_RTCCR_ASOS (1 << 9) /* Bit 9: Alarm or Second Output Selection */ + +/* Backup control register */ + +#define BKP_CR_TPE (1 << 0) /* Bit 0: TAMPER pin enable */ +#define BKP_CR_TPAL (1 << 1) /* Bit 1: TAMPER pin active level */ + +/* Backup control/status register */ + +#define BKP_CSR_CTE (1 << 0) /* Bit 0: Clear Tamper event */ +#define BKP_CSR_CTI (1 << 1) /* Bit 1: Clear Tamper Interrupt */ +#define BKP_CSR_TPIE (1 << 2) /* Bit 2: TAMPER Pin interrupt enable */ +#define BKP_CSR_TEF (1 << 8) /* Bit 8: Tamper Event Flag */ +#define BKP_CSR_TIF (1 << 9) /* Bit 9: Tamper Interrupt Flag */ + +/* Backup data register */ + +#define BKP_DR_SHIFT (0) /* Bits 1510: Backup data */ +#define BKP_DR_MASK (0xffff << BKP_DR_SHIFT) + +#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_BKP_H */ diff --git a/nuttx/arch/arm/src/stm32/chip/stm32_pwr.h b/nuttx/arch/arm/src/stm32/chip/stm32_pwr.h new file mode 100644 index 000000000..8066845af --- /dev/null +++ b/nuttx/arch/arm/src/stm32/chip/stm32_pwr.h @@ -0,0 +1,79 @@ +/************************************************************************************ + * arch/arm/src/stm32/chip/stm32_pwr.h + * + * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32_PWR_H +#define __ARCH_ARM_SRC_STM32_CHIP_STM32_PWR_H + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register Offsets *****************************************************************/ + +#define STM32_PWR_CR_OFFSET 0x0000 /* Power control register */ +#define STM32_PWR_CSR_OFFSET 0x0004 /* Power control/status register */ + +/* Register Addresses ***************************************************************/ + + +/* Register Bitfield Definitions ****************************************************/ + +/* Power control register */ + +#define PWR_CR_LPDS (1 << 0) /* Bit 0: Low-Power Deepsleep */ +#define PWR_CR_PDDS (1 << 1) /* Bit 1: Power Down Deepsleep */ +#define PWR_CR_CWUF (1 << 2) /* Bit 2: Clear Wakeup Flag */ +#define PWR_CR_CSBF (1 << 3) /* Bit 3: Clear Standby Flag */ +#define PWR_CR_PVDE (1 << 4) /* Bit 4: Power Voltage Detector Enable */ +#define PWR_CR_PLS_SHIFT (5) /* Bits 7-5: PVD Level Selection */ +#define PWR_CR_PLS_MASK (7 << PWR_CR_PLS_SHIFT) +# define PWR_CR_2p2V (0 << PWR_CR_PLS_SHIFT) /* 000: 2.2V */ +# define PWR_CR_2p3V (1 << PWR_CR_PLS_SHIFT) /* 001: 2.3V */ +# define PWR_CR_2p4V (2 << PWR_CR_PLS_SHIFT) /* 010: 2.4V */ +# define PWR_CR_2p5V (3 << PWR_CR_PLS_SHIFT) /* 011: 2.5V */ +# define PWR_CR_2p6V (4 << PWR_CR_PLS_SHIFT) /* 100: 2.6V */ +# define PWR_CR_2p7V (5 << PWR_CR_PLS_SHIFT) /* 101: 2.7V */ +# define PWR_CR_2p8V (6 << PWR_CR_PLS_SHIFT) /* 110: 2.8V */ +# define PWR_CR_2p9V (7 << PWR_CR_PLS_SHIFT) /* 111: 2.9V */ +#define PWR_CR_DBP (1 << 8) /* Bit 8: Disable Backup Domain write protection */ + +/* Power control/status register */ + +#define PWR_CSR_WUF (1 << 0) /* Bit 0: Wakeup Flag */ +#define PWR_CSR_SBF (1 << 1) /* Bit 1: Standby Flag */ +#define PWR_CSR_PVDO (1 << 2) /* Bit 2: PVD Output */ +#define PWR_CSR_EWUP (1 << 8) /* Bit 8: Enable WKUP pin */ + +#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_PWR_H */ diff --git a/nuttx/arch/arm/src/stm32/chip/stm32_rtc.h b/nuttx/arch/arm/src/stm32/chip/stm32_rtc.h new file mode 100644 index 000000000..b9fe3d8f3 --- /dev/null +++ b/nuttx/arch/arm/src/stm32/chip/stm32_rtc.h @@ -0,0 +1,96 @@ +/************************************************************************************ + * arch/arm/src/stm32/chip/stm32_rtc.h + * + * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32_RTC_H +#define __ARCH_ARM_SRC_STM32_CHIP_STM32_RTC_H + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register Offsets *****************************************************************/ + +#define STM32_RTC_CRH_OFFSET 0x0000 /* RTC control register High (16-bit) */ +#define STM32_RTC_CRL_OFFSET 0x0004 /* RTC control register low (16-bit) */ +#define STM32_RTC_PRLH_OFFSET 0x0008 /* RTC prescaler load register high (16-bit) */ +#define STM32_RTC_PRLL_OFFSET 0x000c /* RTC prescaler load register low (16-bit) */ +#define STM32_RTC_DIVH_OFFSET 0x0010 /* RTC prescaler divider register high (16-bit) */ +#define STM32_RTC_DIVL_OFFSET 0x0014 /* RTC prescaler divider register low (16-bit) */ +#define STM32_RTC_CNTH_OFFSET 0x0018 /* RTC counter register high (16-bit) */ +#define STM32_RTC_CNTL_OFFSET 0x001c /* RTC counter register low (16-bit) */ +#define STM32_RTC_ALRH_OFFSET 0x0020 /* RTC alarm register high (16-bit) */ +#define STM32_RTC_ALRL_OFFSET 0x0024 /* RTC alarm register low (16-bit) */ + +/* Register Addresses ***************************************************************/ + +#define STM32_RTC_CRH (STM32_RTC_BASE+STM32_RTC_CRH_OFFSET) +#define STM32_RTC_CRL (STM32_RTC_BASE+STM32_RTC_CRL_OFFSET) +#define STM32_RTC_PRLH (STM32_RTC_BASE+STM32_RTC_PRLH_OFFSET) +#define STM32_RTC_PRLL (STM32_RTC_BASE+STM32_RTC_PRLL_OFFSET) +#define STM32_RTC_DIVH (STM32_RTC_BASE+STM32_RTC_DIVH_OFFSET) +#define STM32_RTC_DIVL (STM32_RTC_BASE+STM32_RTC_DIVL_OFFSET) +#define STM32_RTC_CNTH (STM32_RTC_BASE+STM32_RTC_CNTH_OFFSET) +#define STM32_RTC_CNTL (STM32_RTC_BASE+STM32_RTC_CNTL_OFFSET) +#define STM32_RTC_ALRH (STM32_RTC_BASE+STM32_RTC_ALRH_OFFSET) +#define STM32_RTC_ALRL (STM32_RTC_BASE+STM32_RTC_ALRL_OFFSET) + +/* Register Bitfield Definitions ****************************************************/ + +/* RTC control register High (16-bit) */ + +#define RTC_CRH_SECIE (1 << 0) /* Bit 0 : Second Interrupt Enable */ +#define RTC_CRH_ALRIE (1 << 1) /* Bit 1: Alarm Interrupt Enable */ +#define RTC_CRH_OWIE (1 << 2) /* Bit 2: OverfloW Interrupt Enable */ + +/* RTC control register low (16-bit) */ + +#define RTC_CRL_SECF (1 << 0) /* Bit 0: Second Flag */ +#define RTC_CRL_ALRF (1 << 1) /* Bit 1: Alarm Flag */ +#define RTC_CRL_OWF (1 << 2) /* Bit 2: Overflow Flag */ +#define RTC_CRL_RSF (1 << 3) /* Bit 3: Registers Synchronized Flag */ +#define RTC_CRL_CNF (1 << 4) /* Bit 4: Configuration Flag */ +#define RTC_CRL_RTOFF (1 << 5) /* Bit 5: RTC operation OFF */ + +/* RTC prescaler load register high (16-bit) */ + +#define RTC_PRLH_PRL_SHIFT (0) /* Bits 3-0: RTC Prescaler Reload Value High */ +#define RTC_PRLH_PRL_MASK (0x0f << RTC_PRLH_PRL_SHIFT) + +/* RTC prescaler divider register high (16-bit) */ + +#define RTC_DIVH_RTC_DIV_SHIFT (0) /* Bits 3-0: RTC Clock Divider High */ +#define RTC_DIVH_RTC_DIV_MASK (0x0f << RTC_DIVH_RTC_DIV_SHIFT) + +#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_RTC_H */ diff --git a/nuttx/arch/arm/src/stm32/stm32.h b/nuttx/arch/arm/src/stm32/stm32.h index 2845d4e5f..999af048a 100644 --- a/nuttx/arch/arm/src/stm32/stm32.h +++ b/nuttx/arch/arm/src/stm32/stm32.h @@ -67,7 +67,7 @@ #include "chip.h" #include "stm32_adc.h" -#include "stm32_bkp.h" +//#include "stm32_bkp.h" #include "stm32_can.h" #include "stm32_dgbmcu.h" #include "stm32_dma.h" diff --git a/nuttx/arch/arm/src/stm32/stm32_bkp.h b/nuttx/arch/arm/src/stm32/stm32_bkp.h index fd69240e4..8436dbf62 100644 --- a/nuttx/arch/arm/src/stm32/stm32_bkp.h +++ b/nuttx/arch/arm/src/stm32/stm32_bkp.h @@ -43,168 +43,6 @@ #include <nuttx/config.h> #include "chip.h" - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -#if defined(CONFIG_STM32_HIGHDENSITY) || defined(CONFIG_STM32_CONNECTIVITYLINE) -# define CONFIG_STM32_NBKP_BYTES 84 -# define CONFIG_STM32_NBKP_REGS 42 -#else -# define CONFIG_STM32_NBKP_BYTES 20 -# define CONFIG_STM32_NBKP_REGS 10 -#endif - -/* Register Offsets *****************************************************************/ - -#if defined(CONFIG_STM32_HIGHDENSITY) || defined(CONFIG_STM32_CONNECTIVITYLINE) -# define STM32_BKP_DR_OFFSET(n) ((n) > 10 ? 0x0040+4*((n)-10) : 0x0004+4*(n)) -#else -# define STM32_BKP_DR_OFFSET(n) (0x0004+4*(n)) -#endif - -#define STM32_BKP_DR1_OFFSET 0x0004 /* Backup data register 1 */ -#define STM32_BKP_DR2_OFFSET 0x0008 /* Backup data register 2 */ -#define STM32_BKP_DR3_OFFSET 0x000c /* Backup data register 3 */ -#define STM32_BKP_DR4_OFFSET 0x0010 /* Backup data register 4 */ -#define STM32_BKP_DR5_OFFSET 0x0014 /* Backup data register 5 */ -#define STM32_BKP_DR6_OFFSET 0x0018 /* Backup data register 6 */ -#define STM32_BKP_DR7_OFFSET 0x001c /* Backup data register 7 */ -#define STM32_BKP_DR8_OFFSET 0x0020 /* Backup data register 8 */ -#define STM32_BKP_DR9_OFFSET 0x0024 /* Backup data register 9 */ -#define STM32_BKP_DR10_OFFSET 0x0028 /* Backup data register 10 */ - -#define STM32_BKP_RTCCR_OFFSET 0x002c /* RTC clock calibration register */ -#define STM32_BKP_CR_OFFSET 0x0030 /* Backup control register */ -#define STM32_BKP_CSR_OFFSET 0x0034 /* Backup control/status register */ - -#if defined(CONFIG_STM32_HIGHDENSITY) || defined(CONFIG_STM32_CONNECTIVITYLINE) -# define STM32_BKP_DR11_OFFSET 0x0040 /* Backup data register 11 */ -# define STM32_BKP_DR12_OFFSET 0x0044 /* Backup data register 12 */ -# define STM32_BKP_DR13_OFFSET 0x0048 /* Backup data register 13 */ -# define STM32_BKP_DR14_OFFSET 0x004c /* Backup data register 14 */ -# define STM32_BKP_DR15_OFFSET 0x0050 /* Backup data register 15 */ -# define STM32_BKP_DR16_OFFSET 0x0054 /* Backup data register 16 */ -# define STM32_BKP_DR17_OFFSET 0x0058 /* Backup data register 17 */ -# define STM32_BKP_DR18_OFFSET 0x005c /* Backup data register 18 */ -# define STM32_BKP_DR19_OFFSET 0x0060 /* Backup data register 19 */ -# define STM32_BKP_DR20_OFFSET 0x0064 /* Backup data register 20 */ -# define STM32_BKP_DR21_OFFSET 0x0068 /* Backup data register 21 */ -# define STM32_BKP_DR22_OFFSET 0x006c /* Backup data register 22 */ -# define STM32_BKP_DR23_OFFSET 0x0070 /* Backup data register 23 */ -# define STM32_BKP_DR24_OFFSET 0x0074 /* Backup data register 24 */ -# define STM32_BKP_DR25_OFFSET 0x0078 /* Backup data register 25 */ -# define STM32_BKP_DR26_OFFSET 0x007c /* Backup data register 26 */ -# define STM32_BKP_DR27_OFFSET 0x0080 /* Backup data register 27 */ -# define STM32_BKP_DR28_OFFSET 0x0084 /* Backup data register 28 */ -# define STM32_BKP_DR29_OFFSET 0x0088 /* Backup data register 29 */ -# define STM32_BKP_DR30_OFFSET 0x008c /* Backup data register 30 */ -# define STM32_BKP_DR31_OFFSET 0x0090 /* Backup data register 31 */ -# define STM32_BKP_DR32_OFFSET 0x0094 /* Backup data register 32 */ -# define STM32_BKP_DR33_OFFSET 0x0098 /* Backup data register 33 */ -# define STM32_BKP_DR34_OFFSET 0x009c /* Backup data register 34 */ -# define STM32_BKP_DR35_OFFSET 0x00a0 /* Backup data register 35 */ -# define STM32_BKP_DR36_OFFSET 0x00a4 /* Backup data register 36 */ -# define STM32_BKP_DR37_OFFSET 0x00a8 /* Backup data register 37 */ -# define STM32_BKP_DR38_OFFSET 0x00ac /* Backup data register 38 */ -# define STM32_BKP_DR39_OFFSET 0x00b0 /* Backup data register 39 */ -# define STM32_BKP_DR40_OFFSET 0x00b4 /* Backup data register 40 */ -# define STM32_BKP_DR41_OFFSET 0x00b8 /* Backup data register 41 */ -# define STM32_BKP_DR42_OFFSET 0x00bc /* Backup data register 42 */ -#endif - -/* Register Addresses ***************************************************************/ - -#define STM32_BKP_RTCCR (STM32_BKP_BASE+STM32_BKP_RTCCR_OFFSET) -#define STM32_BKP_CR (STM32_BKP_BASE+STM32_BKP_CR_OFFSET) -#define STM32_BKP_CSR (STM32_BKP_BASE+STM32_BKP_CSR_OFFSET) - -#define STM32_BKP_DR(n) (STM32_BKP_BASE+STM32_BKP_DR_OFFSET(n)) -#define STM32_BKP_DR1 (STM32_BKP_BASE+STM32_BKP_DR1_OFFSET) -#define STM32_BKP_DR2 (STM32_BKP_BASE+STM32_BKP_DR2_OFFSET) -#define STM32_BKP_DR3 (STM32_BKP_BASE+STM32_BKP_DR3_OFFSET) -#define STM32_BKP_DR4 (STM32_BKP_BASE+STM32_BKP_DR4_OFFSET) -#define STM32_BKP_DR5 (STM32_BKP_BASE+STM32_BKP_DR5_OFFSET) -#define STM32_BKP_DR6 (STM32_BKP_BASE+STM32_BKP_DR6_OFFSET) -#define STM32_BKP_DR7 (STM32_BKP_BASE+STM32_BKP_DR7_OFFSET) -#define STM32_BKP_DR8 (STM32_BKP_BASE+STM32_BKP_DR8_OFFSET) -#define STM32_BKP_DR9 (STM32_BKP_BASE+STM32_BKP_DR9_OFFSET) -#define STM32_BKP_DR10 (STM32_BKP_BASE+STM32_BKP_DR10_OFFSET) - -#if defined(CONFIG_STM32_HIGHDENSITY) || defined(CONFIG_STM32_CONNECTIVITYLINE) -# define STM32_BKP_DR11 (STM32_BKP_BASE+STM32_BKP_DR11_OFFSET) -# define STM32_BKP_DR12 (STM32_BKP_BASE+STM32_BKP_DR12_OFFSET) -# define STM32_BKP_DR13 (STM32_BKP_BASE+STM32_BKP_DR13_OFFSET) -# define STM32_BKP_DR14 (STM32_BKP_BASE+STM32_BKP_DR14_OFFSET) -# define STM32_BKP_DR15 (STM32_BKP_BASE+STM32_BKP_DR15_OFFSET) -# define STM32_BKP_DR16 (STM32_BKP_BASE+STM32_BKP_DR16_OFFSET) -# define STM32_BKP_DR17 (STM32_BKP_BASE+STM32_BKP_DR17_OFFSET) -# define STM32_BKP_DR18 (STM32_BKP_BASE+STM32_BKP_DR18_OFFSET) -# define STM32_BKP_DR19 (STM32_BKP_BASE+STM32_BKP_DR19_OFFSET) -# define STM32_BKP_DR20 (STM32_BKP_BASE+STM32_BKP_DR20_OFFSET) -# define STM32_BKP_DR21 (STM32_BKP_BASE+STM32_BKP_DR21_OFFSET) -# define STM32_BKP_DR22 (STM32_BKP_BASE+STM32_BKP_DR22_OFFSET) -# define STM32_BKP_DR23 (STM32_BKP_BASE+STM32_BKP_DR23_OFFSET) -# define STM32_BKP_DR24 (STM32_BKP_BASE+STM32_BKP_DR24_OFFSET) -# define STM32_BKP_DR25 (STM32_BKP_BASE+STM32_BKP_DR25_OFFSET) -# define STM32_BKP_DR26 (STM32_BKP_BASE+STM32_BKP_DR26_OFFSET) -# define STM32_BKP_DR27 (STM32_BKP_BASE+STM32_BKP_DR27_OFFSET) -# define STM32_BKP_DR28 (STM32_BKP_BASE+STM32_BKP_DR28_OFFSET) -# define STM32_BKP_DR29 (STM32_BKP_BASE+STM32_BKP_DR29_OFFSET) -# define STM32_BKP_DR30 (STM32_BKP_BASE+STM32_BKP_DR30_OFFSET) -# define STM32_BKP_DR31 (STM32_BKP_BASE+STM32_BKP_DR31_OFFSET) -# define STM32_BKP_DR32 (STM32_BKP_BASE+STM32_BKP_DR32_OFFSET) -# define STM32_BKP_DR33 (STM32_BKP_BASE+STM32_BKP_DR33_OFFSET) -# define STM32_BKP_DR34 (STM32_BKP_BASE+STM32_BKP_DR34_OFFSET) -# define STM32_BKP_DR35 (STM32_BKP_BASE+STM32_BKP_DR35_OFFSET) -# define STM32_BKP_DR36 (STM32_BKP_BASE+STM32_BKP_DR36_OFFSET) -# define STM32_BKP_DR37 (STM32_BKP_BASE+STM32_BKP_DR37_OFFSET) -# define STM32_BKP_DR38 (STM32_BKP_BASE+STM32_BKP_DR38_OFFSET) -# define STM32_BKP_DR39 (STM32_BKP_BASE+STM32_BKP_DR39_OFFSET) -# define STM32_BKP_DR40 (STM32_BKP_BASE+STM32_BKP_DR40_OFFSET) -# define STM32_BKP_DR41 (STM32_BKP_BASE+STM32_BKP_DR41_OFFSET) -# define STM32_BKP_DR42 (STM32_BKP_BASE+STM32_BKP_DR42_OFFSET) -#endif - -/* Register Bitfield Definitions ****************************************************/ - -/* RTC clock calibration register */ - -#define BKP_RTCCR_CAL_SHIFT (0) /* Bits 6-0: Calibration value */ -#define BKP_RTCCR_CAL_MASK (0x7f << BKP_RTCCR_CAL_SHIFT) -#define BKP_RTCCR_CCO (1 << 7) /* Bit 7: Calibration Clock Output */ -#define BKP_RTCCR_ASOE (1 << 8) /* Bit 8: Alarm or Second Output Enable */ -#define BKP_RTCCR_ASOS (1 << 9) /* Bit 9: Alarm or Second Output Selection */ - -/* Backup control register */ - -#define BKP_CR_TPE (1 << 0) /* Bit 0: TAMPER pin enable */ -#define BKP_CR_TPAL (1 << 1) /* Bit 1: TAMPER pin active level */ - -/* Backup control/status register */ - -#define BKP_CSR_CTE (1 << 0) /* Bit 0: Clear Tamper event */ -#define BKP_CSR_CTI (1 << 1) /* Bit 1: Clear Tamper Interrupt */ -#define BKP_CSR_TPIE (1 << 2) /* Bit 2: TAMPER Pin interrupt enable */ -#define BKP_CSR_TEF (1 << 8) /* Bit 8: Tamper Event Flag */ -#define BKP_CSR_TIF (1 << 9) /* Bit 9: Tamper Interrupt Flag */ - -/* Backup data register */ - -#define BKP_DR_SHIFT (0) /* Bits 1510: Backup data */ -#define BKP_DR_MASK (0xffff << BKP_DR_SHIFT) - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ +#include "chip/stm32_bkp.h" #endif /* __ARCH_ARM_SRC_STM32_STM32_BKP_H */ diff --git a/nuttx/arch/arm/src/stm32/stm32_i2c.c b/nuttx/arch/arm/src/stm32/stm32_i2c.c index 90673ef62..f19a1909c 100644 --- a/nuttx/arch/arm/src/stm32/stm32_i2c.c +++ b/nuttx/arch/arm/src/stm32/stm32_i2c.c @@ -66,6 +66,7 @@ #include <nuttx/arch.h> #include <nuttx/irq.h> #include <nuttx/i2c/i2c.h> +#include <nuttx/kmalloc.h> #include <arch/board/board.h> #include <sys/types.h> @@ -81,6 +82,7 @@ #include "stm32_rcc.h" #include "stm32_i2c.h" +#include "stm32_waste.h" #if defined(CONFIG_STM32_I2C1) || defined(CONFIG_STM32_I2C2) @@ -89,8 +91,6 @@ * Private Types ************************************************************************************/ -#define I2C_FLAGS 0x8000 /* RxNE and TxE enabled */ - /** I2C Device Private Data */ struct stm32_i2c_priv_s { @@ -593,8 +593,6 @@ int stm32_i2c_process(FAR struct i2c_dev_s *dev, FAR struct i2c_msg_s *msgs, int uint32_t status = 0; int status_errno = 0; - extern void up_waste(void); - ASSERT(count); /* wait as stop might still be in progress @@ -789,7 +787,7 @@ FAR struct i2c_dev_s * up_i2cinitialize(int port) /* Allocate instance */ - if ( !(inst = malloc( sizeof(struct stm32_i2c_inst_s) )) ) return NULL; + if ( !(inst = kmalloc( sizeof(struct stm32_i2c_inst_s) )) ) return NULL; /* initialize instance */ @@ -831,7 +829,7 @@ int up_i2cuninitialize(FAR struct i2c_dev_s * dev) if ( --((struct stm32_i2c_inst_s *)dev)->priv->refs ) { irqrestore(irqs); - free(dev); + kfree(dev); return OK; } @@ -845,7 +843,7 @@ int up_i2cuninitialize(FAR struct i2c_dev_s * dev) stm32_i2c_sem_destroy( (struct i2c_dev_s *)dev ); - free(dev); + kfree(dev); return OK; } diff --git a/nuttx/arch/arm/src/stm32/stm32_pwr.c b/nuttx/arch/arm/src/stm32/stm32_pwr.c new file mode 100644 index 000000000..861d32b64 --- /dev/null +++ b/nuttx/arch/arm/src/stm32/stm32_pwr.c @@ -0,0 +1,90 @@ +/************************************************************************************ + * arch/arm/src/stm32/stm32_pwr.c + * + * Copyright (C) 2011 Uros Platise. All rights reserved. + * Author: Uros Platise <uros.platise@isotel.eu> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/** \file + * \author Uros Platise + * \brief STM32 Power + * + * \addtogroup STM32_PWR + * \{ + */ + +#include <nuttx/config.h> +#include <nuttx/arch.h> + +#include <stdint.h> +#include <errno.h> + +#include "up_arch.h" +#include "stm32_pwr.h" + + +#if defined(CONFIG_STM32_PWR) + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +static inline uint16_t stm32_pwr_getreg(uint8_t offset) +{ + return getreg32(STM32_PWR_BASE + offset); +} + + +static inline void stm32_pwr_putreg(uint8_t offset, uint16_t value) +{ + putreg32(value, STM32_PWR_BASE + offset); +} + + +static inline void stm32_pwr_modifyreg(uint8_t offset, uint16_t clearbits, uint16_t setbits) +{ + modifyreg32(STM32_PWR_BASE + offset, clearbits, setbits); +} + + + +/************************************************************************************ + * Public Function - Initialization + ************************************************************************************/ + +void stm32_pwr_enablebkp(void) +{ + stm32_pwr_modifyreg(STM32_PWR_CR_OFFSET, 0, PWR_CR_DBP); +} + + +#endif // defined(CONFIG_STM32_PWR) +/** \} */ diff --git a/nuttx/arch/arm/src/stm32/stm32_pwr.h b/nuttx/arch/arm/src/stm32/stm32_pwr.h index bf2b733c3..638d23640 100644 --- a/nuttx/arch/arm/src/stm32/stm32_pwr.h +++ b/nuttx/arch/arm/src/stm32/stm32_pwr.h @@ -43,57 +43,35 @@ #include <nuttx/config.h> #include "chip.h" +#include "chip/stm32_pwr.h" /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ -/* Register Offsets *****************************************************************/ +#ifndef __ASSEMBLY__ -#define STM32_PWR_CR_OFFSET 000x00 /* Power control register */ -#define STM32_PWR_CSR_OFFSET 0x0004 /* Power control/status register */ - -/* Register Addresses ***************************************************************/ - - -/* Register Bitfield Definitions ****************************************************/ - -/* Power control register */ - -#define PWR_CR_LPDS (1 << 0) /* Bit 0: Low-Power Deepsleep */ -#define PWR_CR_PDDS (1 << 1) /* Bit 1: Power Down Deepsleep */ -#define PWR_CR_CWUF (1 << 2) /* Bit 2: Clear Wakeup Flag */ -#define PWR_CR_CSBF (1 << 3) /* Bit 3: Clear Standby Flag */ -#define PWR_CR_PVDE (1 << 4) /* Bit 4: Power Voltage Detector Enable */ -#define PWR_CR_PLS_SHIFT (5) /* Bits 7-5: PVD Level Selection */ -#define PWR_CR_PLS_MASK (7 << PWR_CR_PLS_SHIFT) -# define PWR_CR_2p2V (0 << PWR_CR_PLS_SHIFT) /* 000: 2.2V */ -# define PWR_CR_2p3V (1 << PWR_CR_PLS_SHIFT) /* 001: 2.3V */ -# define PWR_CR_2p4V (2 << PWR_CR_PLS_SHIFT) /* 010: 2.4V */ -# define PWR_CR_2p5V (3 << PWR_CR_PLS_SHIFT) /* 011: 2.5V */ -# define PWR_CR_2p6V (4 << PWR_CR_PLS_SHIFT) /* 100: 2.6V */ -# define PWR_CR_2p7V (5 << PWR_CR_PLS_SHIFT) /* 101: 2.7V */ -# define PWR_CR_2p8V (6 << PWR_CR_PLS_SHIFT) /* 110: 2.8V */ -# define PWR_CR_2p9V (7 << PWR_CR_PLS_SHIFT) /* 111: 2.9V */ -#define PWR_CR_DBP (1 << 8) /* Bit 8: Disable Backup Domain write protection */ - -/* Power control/status register */ - -#define PWR_CSR_WUF (1 << 0) /* Bit 0: Wakeup Flag */ -#define PWR_CSR_SBF (1 << 1) /* Bit 1: Standby Flag */ -#define PWR_CSR_PVDO (1 << 2) /* Bit 2: PVD Output */ -#define PWR_CSR_EWUP (1 << 8) /* Bit 8: Enable WKUP pin */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" { +#else +#define EXTERN extern +#endif /************************************************************************************ * Public Functions ************************************************************************************/ - + +/** Disables Write Protection to the Backup Area + **/ +EXTERN void stm32_pwr_enablebkp(void); + + +/** \} */ +#undef EXTERN +#if defined(__cplusplus) +} +#endif +#endif /* __ASSEMBLY__ */ #endif /* __ARCH_ARM_SRC_STM32_STM32_PWR_H */ diff --git a/nuttx/arch/arm/src/stm32/stm32_rcc.c b/nuttx/arch/arm/src/stm32/stm32_rcc.c index 52e1ac0ae..480345938 100755 --- a/nuttx/arch/arm/src/stm32/stm32_rcc.c +++ b/nuttx/arch/arm/src/stm32/stm32_rcc.c @@ -42,6 +42,7 @@ #include <stdint.h> #include <debug.h> #include <arch/board/board.h> +#include <stdio.h> #include "up_internal.h" #include "up_arch.h" @@ -50,6 +51,7 @@ #include "stm32_rcc.h" #include "stm32_flash.h" #include "stm32_internal.h" +#include "stm32_waste.h" /**************************************************************************** * Definitions @@ -58,11 +60,7 @@ #define HSERDY_TIMEOUT 256 /**************************************************************************** - * Private Types - ****************************************************************************/ - -/**************************************************************************** - * Private Function Prototypes + * Private Functions ****************************************************************************/ /* Put all RCC registers in reset state */ @@ -100,6 +98,7 @@ static inline void rcc_reset(void) putreg32(0, STM32_RCC_CIR); /* Disable all interrupts */ } + static inline void rcc_enableahb(void) { uint32_t regval; @@ -141,6 +140,7 @@ static inline void rcc_enableahb(void) putreg32(regval, STM32_RCC_AHBENR); /* Enable peripherals */ } + static inline void rcc_enableapb1(void) { uint32_t regval; @@ -292,6 +292,7 @@ static inline void rcc_enableapb1(void) putreg32(regval, STM32_RCC_APB1ENR); } + static inline void rcc_enableapb2(void) { uint32_t regval; @@ -373,17 +374,14 @@ static inline void rcc_enableapb2(void) putreg32(regval, STM32_RCC_APB2ENR); } -/**************************************************************************** - * Name: stm32_stdclockconfig - * - * Description: - * Called to set clocking based on standard definitions in board.h. - * NOTE: This logic would need to be extended if you need to select low- - * power clocking modes! - * - ****************************************************************************/ #if !defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) + +/** Called to change to new clock based on settings in board.h + * + * NOTE: This logic would need to be extended if you need to select low- + * power clocking modes! + **/ static inline void stm32_stdclockconfig(void) { uint32_t regval; @@ -471,18 +469,9 @@ static inline void stm32_stdclockconfig(void) } #endif -/**************************************************************************** - * Global Functions - ****************************************************************************/ /**************************************************************************** - * Name: stm32_clockconfig - * - * Description: - * Called to change to new clock based on settings in board.h. - * NOTE: This logic needs to be extended so that we can selected low-power - * clocking modes as well! - * + * Public Functions ****************************************************************************/ void stm32_clockconfig(void) @@ -511,3 +500,23 @@ void stm32_clockconfig(void) rcc_enableapb2(); rcc_enableapb1(); } + + +/** + * \todo Check for LSE good timeout and return with -1, + * possible ISR optimization? or at least ISR should be cough in case of failure + */ +void stm32_rcc_enablelse(void) +{ + /* Enable LSE */ + modifyreg16(STM32_RCC_BDCR, 0, RCC_BDCR_LSEON); + + /* We could wait for ISR here ... */ + while( !(getreg16(STM32_RCC_BDCR) & RCC_BDCR_LSERDY) ) up_waste(); + + /* Select LSE as RTC Clock Source */ + modifyreg16(STM32_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL_LSE); + + /* Enable Clock */ + modifyreg16(STM32_RCC_BDCR, 0, RCC_BDCR_RTCEN); +} diff --git a/nuttx/arch/arm/src/stm32/stm32_rcc.h b/nuttx/arch/arm/src/stm32/stm32_rcc.h index 8a4baacba..1c0020a21 100755 --- a/nuttx/arch/arm/src/stm32/stm32_rcc.h +++ b/nuttx/arch/arm/src/stm32/stm32_rcc.h @@ -46,7 +46,7 @@ #include "chip/stm32_rcc.h" /************************************************************************************ - * Public Data + * Pre-processor Definitions ************************************************************************************/ #ifndef __ASSEMBLY__ @@ -59,6 +59,10 @@ extern "C" { #define EXTERN extern #endif +/************************************************************************************ + * Public Data + ************************************************************************************/ + /* This symbol references the Cortex-M3 vector table (as positioned by the the linker * script, ld.script or ld.script.dfu. The standard location for the vector table is * at the beginning of FLASH at address 0x0800:0000. If we are using the STMicro DFU @@ -68,25 +72,26 @@ extern "C" { extern uint32_t stm32_vectors[]; /* See stm32_vectors.S */ -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ /************************************************************************************ - * Name: stm32_clockconfig - * - * Description: - * Called to change to new clock based on settings in board.h - * + * Public Function Prototypes ************************************************************************************/ +/** Called to change to new clock based on settings in board.h + * + * NOTE: This logic needs to be extended so that we can selected low-power + * clocking modes as well! + **/ EXTERN void stm32_clockconfig(void); +/** Enable LSE Clock + **/ +EXTERN void stm32_rcc_enablelse(void); + + #undef EXTERN #if defined(__cplusplus) } #endif - #endif /* __ASSEMBLY__ */ #endif /* __ARCH_ARM_SRC_STM32_STM32_RRC_H */ - diff --git a/nuttx/arch/arm/src/stm32/stm32_rtc.c b/nuttx/arch/arm/src/stm32/stm32_rtc.c new file mode 100644 index 000000000..ec0afdc35 --- /dev/null +++ b/nuttx/arch/arm/src/stm32/stm32_rtc.c @@ -0,0 +1,314 @@ +/************************************************************************************ + * arch/arm/src/stm32/stm32_rtc.c + * + * Copyright (C) 2011 Uros Platise. All rights reserved. + * Author: Uros Platise <uros.platise@isotel.eu> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/** \file + * \author Uros Platise + * \brief STM32 Real-Time Clock + * + * \addtogroup STM32_RTC + * \{ + * + * The STM32 RTC Driver offers standard precision of 1 Hz or High Resolution + * operating at rate up to 16384 Hz. It provides UTC time and alarm interface + * with external output pin (for wake-up). + * + * RTC is based on hardware RTC module which is located in a separate power + * domain. The 32-bit counter is extended by 16-bit registers in BKP domain + * STM32_BKP_DR1 to provide system equiv. function to the: time_t time(time_t *). + * + * Notation: + * - clock refers to 32-bit hardware counter + * - time is a combination of clock and upper bits stored in backuped domain + * with unit of 1 [s] + * + * \todo Error Handling in case LSE fails during start-up or during operation. + */ + +#include <nuttx/config.h> +#include <nuttx/arch.h> +#include <nuttx/irq.h> +#include <nuttx/ptimer.h> +#include <arch/board/board.h> + +#include <stdlib.h> +#include <stdint.h> +#include <stdbool.h> +#include <stdio.h> + +#include "up_arch.h" + +#include "stm32_pwr.h" +#include "stm32_rcc.h" +#include "stm32_rtc.h" +#include "stm32_waste.h" + + +#if defined(CONFIG_STM32_BKP) + +/************************************************************************************ + * Configuration of the RTC Backup Register (16-bit) + ************************************************************************************/ + +#define RTC_TIMEMSB_REG STM32_BKP_DR1 + + +/************************************************************************************ + * Private Data + ************************************************************************************/ + +/** Variable determines the state of the LSE oscilator. + * Possible errors: + * - on start-up + * - during operation, reported by LSE interrupt + */ +volatile bool g_rtc_enabled = false; + + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +static inline void stm32_rtc_beginwr(void) +{ + /* Previous write is done? */ + while( (getreg16(STM32_RTC_CRL) & RTC_CRL_RTOFF)==0 ) up_waste(); + + /* Enter Config mode, Set Value and Exit */ + modifyreg16(STM32_RTC_CRL, 0, RTC_CRL_CNF); +} + + +static inline void stm32_rtc_endwr(void) +{ + modifyreg16(STM32_RTC_CRL, RTC_CRL_CNF, 0); +} + + +/** Wait for registerred to synchronise with RTC module, call after power-up only */ +static inline void stm32_rtc_wait4rsf(void) +{ + modifyreg16(STM32_RTC_CRL, RTC_CRL_RSF, 0); + while( !(getreg16(STM32_RTC_CRL) & RTC_CRL_RSF) ) up_waste(); +} + + + +/************************************************************************************ + * Interrupt Service Routines + ************************************************************************************/ + +static int stm32_rtc_overflow_isr(int irq, void *context) +{ + uint16_t source = getreg16( STM32_RTC_CRL ); + + if (source & RTC_CRL_OWF) { + putreg16( getreg16(RTC_TIMEMSB_REG) + 1, RTC_TIMEMSB_REG ); + } + + if (source & RTC_CRL_ALRF) { + /* Alarm */ + } + + /* Clear pending flags, leave RSF high */ + + putreg16( RTC_CRL_RSF, STM32_RTC_CRL ); + return 0; +} + + +/************************************************************************************ + * Public Function - Initialization + ************************************************************************************/ + +/** Power-up RTC + * + * \param prescaler A 20-bit value determines the time base, and is defined as: + * f = 32768 / (prescaler + 1) + * + * \return State of the RTC unit + * + * \retval OK If RTC has been successfully configured. + * \retval ERROR On error, if LSE does not start. + **/ +int up_rtcinitialize(void) +{ + /* For this initial version we use predefined value */ + + uint32_t prescaler = STM32_RTC_PRESCALER_MIN; + + /* Set access to the peripheral, enable power and LSE */ + + stm32_pwr_enablebkp(); + stm32_rcc_enablelse(); + + // \todo Get state from this function, if everything is + // okay and whether it is already enabled (if it was disabled + // reset upper time register + g_rtc_enabled = true; + + // \todo Possible stall? should we set the timeout period? and return with -1 + stm32_rtc_wait4rsf(); + + /* Configure prescaler, note that this are write-only registers */ + + stm32_rtc_beginwr(); + putreg16(prescaler >> 16, STM32_RTC_PRLH); + putreg16(prescaler & 0xFFFF, STM32_RTC_PRLL); + stm32_rtc_endwr(); + + /* Configure Overflow Interrupt */ + + irq_attach(STM32_IRQ_RTC, stm32_rtc_overflow_isr); + up_enable_irq(STM32_IRQ_RTC); + + /* Previous write is done? This is required prior writing into CRH */ + + while( (getreg16(STM32_RTC_CRL) & RTC_CRL_RTOFF)==0 ) up_waste(); + + modifyreg16(STM32_RTC_CRH, 0, RTC_CRH_OWIE); + + /* Alarm Int via EXTI Line */ + + // STM32_IRQ_RTCALR /* 41: RTC alarm through EXTI line interrupt */ + + return OK; +} + + +/** Get time (counter) value + * + * \return time, where the unit depends on the prescaler value + **/ +clock_t up_rtc_getclock(void) +{ + return ( (uint32_t)getreg16(STM32_RTC_CNTH) << 16) | + (uint32_t)getreg16(STM32_RTC_CNTL); +} + + +/** Set time (counter) value + * + * \param time The unit depends on the prescaler value + **/ +void up_rtc_setclock(clock_t clock) +{ + stm32_rtc_beginwr(); + putreg16(clock >> 16, STM32_RTC_CNTH); + putreg16(clock & 0xFFFF, STM32_RTC_CNTL); + stm32_rtc_endwr(); +} + + +time_t up_rtc_gettime(void) +{ + /* Fetch time from LSB (hardware counter) and MSB (backup domain) + * Take care on overflow of the LSB: + * - it may overflow just after reading the up_rtc_getclock, transition + * from 0xFF...FF -> 0x000000 + * - ISR would be generated to increment the RTC_TIMEMSB_REG + * - Wrong result would when: DR+1 and LSB is old, resulting in ~DR+2 + * instead of just DR+1 + */ + + irqstate_t irqs = irqsave(); + + uint32_t time_lsb = up_rtc_getclock(); + uint32_t time_msb = getreg16(RTC_TIMEMSB_REG); + + irqrestore( irqs ); + + /* Use the upper bits of the LSB and lower bits of the MSB + * structured as: + * time = time[31:18] from MSB[13:0] | time[17:0] from time_lsb[31:14] + */ + + time_lsb >>= RTC_CLOCKS_SHIFT; + + time_msb <<= (32-RTC_CLOCKS_SHIFT); + time_msb &= ~((1<<(32-RTC_CLOCKS_SHIFT))-1); + + return time_msb | time_lsb; +} + + +void up_rtc_settime(time_t time) +{ + /* Do reverse compared to gettime above */ + + uint32_t time_lsb = time << RTC_CLOCKS_SHIFT | + (up_rtc_getclock() & ((1<<RTC_CLOCKS_SHIFT)-1)); + + uint32_t time_msb = time >> (32-RTC_CLOCKS_SHIFT); + + irqstate_t irqs = irqsave(); + + up_rtc_setclock(time_lsb); + putreg16( time_msb, RTC_TIMEMSB_REG ); + + irqrestore( irqs ); +} + + +/** Set ALARM at which time ALARM callback is going to be generated + * + * The function sets the alarm and return present time at the time + * of setting the alarm. + * + * Note that If actual time has already passed callback will not be + * generated and it is up to the higher level code to compare the + * returned (actual) time and desired time of alarm. + * + * \param attime The unit depends on the prescaler value + * \return presenttime, where the unit depends on the prescaler value + **/ +clock_t up_rtc_setalarm(clock_t atclock) +{ + stm32_rtc_beginwr(); + putreg16(atclock >> 16, STM32_RTC_ALRH); + putreg16(atclock & 0xFFFF, STM32_RTC_ALRL); + stm32_rtc_endwr(); + + return up_rtc_getclock(); +} + + +/** Set alarm output pin */ +void stm32_rtc_settalarmpin(bool activate) +{ +} + + +#endif // defined(CONFIG_STM32_BKP) +/** \} */ diff --git a/nuttx/arch/arm/src/stm32/stm32_rtc.h b/nuttx/arch/arm/src/stm32/stm32_rtc.h index 4ebff07a9..467464664 100644 --- a/nuttx/arch/arm/src/stm32/stm32_rtc.h +++ b/nuttx/arch/arm/src/stm32/stm32_rtc.h @@ -1,8 +1,8 @@ /************************************************************************************ * arch/arm/src/stm32/stm32_rtc.h * - * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Copyright (C) 2011 Uros Platise. All rights reserved. + * Author: Uros Platise <uros.platise@isotel.eu> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -33,84 +33,48 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_RTC_H -#define __ARCH_ARM_SRC_STM32_STM32_RTC_H - /************************************************************************************ * Included Files ************************************************************************************/ +#ifndef __ARCH_ARM_SRC_STM32_STM32_RTC_H +#define __ARCH_ARM_SRC_STM32_STM32_RTC_H + #include <nuttx/config.h> #include "chip.h" +#include "chip/stm32_rtc.h" +#include "chip/stm32_bkp.h" /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ -/* Register Offsets *****************************************************************/ - -#define STM32_RTC_CRH_OFFSET 0x0000 /* RTC control register High (16-bit) */ -#define STM32_RTC_CRL_OFFSET 0x0004 /* RTC control register low (16-bit) */ -#define STM32_RTC_PRLH_OFFSET 0x0008 /* RTC prescaler load register high (16-bit) */ -#define STM32_RTC_PRLL_OFFSET 0x000c /* RTC prescaler load register low (16-bit) */ -#define STM32_RTC_DIVH_OFFSET 0x0010 /* RTC prescaler divider register high (16-bit) */ -#define STM32_RTC_DIVL_OFFSET 0x0014 /* RTC prescaler divider register low (16-bit) */ -#define STM32_RTC_CNTH_OFFSET 0x0018 /* RTC counter register high (16-bit) */ -#define STM32_RTC_CNTL_OFFSET 0x001c /* RTC counter register low (16-bit) */ -#define STM32_RTC_ALRH_OFFSET 0x0020 /* RTC alarm register high (16-bit) */ -#define STM32_RTC_ALRL_OFFSET 0x0024 /* RTC alarm register low (16-bit) */ - -/* Register Addresses ***************************************************************/ - -#define STM32_RTC_CRH (STM32_RTC_BASE+STM32_RTC_CRH_OFFSET) -#define STM32_RTC_CRL (STM32_RTC_BASE+STM32_RTC_CRL_OFFSET) -#define STM32_RTC_PRLH (STM32_RTC_BASE+STM32_RTC_PRLH_OFFSET) -#define STM32_RTC_PRLL (STM32_RTC_BASE+STM32_RTC_PRLL_OFFSET) -#define STM32_RTC_DIVH (STM32_RTC_BASE+STM32_RTC_DIVH_OFFSET) -#define STM32_RTC_DIVL (STM32_RTC_BASE+STM32_RTC_DIVL_OFFSET) -#define STM32_RTC_CNTH (STM32_RTC_BASE+STM32_RTC_CNTH_OFFSET) -#define STM32_RTC_CNTL (STM32_RTC_BASE+STM32_RTC_CNTL_OFFSET) -#define STM32_RTC_ALRH (STM32_RTC_BASE+STM32_RTC_ALRH_OFFSET) -#define STM32_RTC_ALRL (STM32_RTC_BASE+STM32_RTC_ALRL_OFFSET) - -/* Register Bitfield Definitions ****************************************************/ - -/* RTC control register High (16-bit) */ +#define STM32_RTC_PRESCALER_SECOND 32767 /** Default prescaler to get a second base */ +#define STM32_RTC_PRESCALER_MIN 1 /** Maximum speed of 16384 Hz */ -#define RTC_CRH_SECIE (1 << 0) /* Bit 0 : Second Interrupt Enable*/ -#define RTC_CRH_ALRIE (1 << 1) /* Bit 1: Alarm Interrupt Enable*/ -#define RTC_CRH_OWIE (1 << 2) /* Bit 2: OverfloW Interrupt Enable*/ +#ifndef __ASSEMBLY__ -/* RTC control register low (16-bit) */ - -#define RTC_CRL_SECF (1 << 0) /* Bit 0: Second Flag*/ -#define RTC_CRL_ALRF (1 << 1) /* Bit 1: Alarm Flag*/ -#define RTC_CRL_OWF (1 << 2) /* Bit 2: Overflow Flag*/ -#define RTC_CRL_RSF (1 << 3) /* Bit 3: Registers Synchronized Flag*/ -#define RTC_CRL_CNF (1 << 4) /* Bit 4: Configuration Flag*/ -#define RTC_CRL_RTOFF (1 << 5) /* Bit 5: RTC operation OFF*/ - -/* RTC prescaler load register high (16-bit) */ - -#define RTC_PRLH_PRL_SHIFT (0) /* Bits 3-0: RTC Prescaler Reload Value High */ -#define RTC_PRLH_PRL_MASK (0x0f << RTC_PRLH_PRL_SHIFT) - -/* RTC prescaler divider register high (16-bit) */ - -#define RTC_DIVH_RTC_DIV_SHIFT (0) /* Bits 3-0: RTC Clock Divider High */ -#define RTC_DIVH_RTC_DIV_MASK (0x0f << RTC_DIVH_RTC_DIV_SHIFT) +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" { +#else +#define EXTERN extern +#endif /************************************************************************************ - * Public Types + * Public Functions ************************************************************************************/ -/************************************************************************************ - * Public Data - ************************************************************************************/ +/** Set alarm output pin */ +EXTERN void stm32_rtc_settalarmpin(bool activate); -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/** \} */ +#undef EXTERN +#if defined(__cplusplus) +} +#endif +#endif /* __ASSEMBLY__ */ #endif /* __ARCH_ARM_SRC_STM32_STM32_RTC_H */ diff --git a/nuttx/arch/arm/src/stm32/stm32_spi.h b/nuttx/arch/arm/src/stm32/stm32_spi.h index 7a58dd83e..268589bf3 100755 --- a/nuttx/arch/arm/src/stm32/stm32_spi.h +++ b/nuttx/arch/arm/src/stm32/stm32_spi.h @@ -46,7 +46,7 @@ #include "chip/stm32_spi.h" /************************************************************************************ - * Public Data + * Pre-processor Definitions ************************************************************************************/ #ifndef __ASSEMBLY__ @@ -59,6 +59,10 @@ extern "C" { #define EXTERN extern #endif +/************************************************************************************ + * Public Data + ************************************************************************************/ + struct spi_dev_s; enum spi_dev_e; diff --git a/nuttx/arch/arm/src/stm32/stm32_tim.h b/nuttx/arch/arm/src/stm32/stm32_tim.h index a35d0134b..1aa18328e 100644 --- a/nuttx/arch/arm/src/stm32/stm32_tim.h +++ b/nuttx/arch/arm/src/stm32/stm32_tim.h @@ -46,6 +46,19 @@ #include "chip.h" #include "chip/stm32_tim.h" +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" { +#else +#define EXTERN extern +#endif /************************************************************************************ * Public Types @@ -155,9 +168,16 @@ struct stm32_tim_ops_s { ************************************************************************************/ /** Power-up timer and get its structure */ -FAR struct stm32_tim_dev_s * stm32_tim_init(int timer); +EXTERN FAR struct stm32_tim_dev_s * stm32_tim_init(int timer); /** Power-down timer, mark it as unused */ -int stm32_tim_deinit(FAR struct stm32_tim_dev_s * dev); +EXTERN int stm32_tim_deinit(FAR struct stm32_tim_dev_s * dev); + + +#undef EXTERN +#if defined(__cplusplus) +} +#endif +#endif /* __ASSEMBLY__ */ #endif /* __ARCH_ARM_SRC_STM32_STM32_TIM_H */ diff --git a/nuttx/arch/arm/src/stm32/stm32_waste.c b/nuttx/arch/arm/src/stm32/stm32_waste.c index 057e2eb37..a680b8b0f 100755 --- a/nuttx/arch/arm/src/stm32/stm32_waste.c +++ b/nuttx/arch/arm/src/stm32/stm32_waste.c @@ -39,46 +39,19 @@ #include <nuttx/config.h> #include <stdint.h> - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ +#include "stm32_waste.h" /**************************************************************************** * Private Data ****************************************************************************/ -/**************************************************************************** - * Public Data - ****************************************************************************/ - uint32_t idle_wastecounter = 0; /**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** * Public Functions ****************************************************************************/ -/**************************************************************************** - * Name: up_waste - * - * Description: - * up_waste() is the logic that will be executed when portions of kernel - * or user-app is polling some register or similar, waiting for desired - * status. This time is wasted away. This function offers a measure of - * badly written piece of software or some undesired behavior. - * - * At the same time this function adds to some IDLE time which portion - * cannot be used for other purposes (yet). - * - ****************************************************************************/ - void up_waste(void) { idle_wastecounter++; } - - diff --git a/nuttx/arch/arm/src/stm32/stm32_waste.h b/nuttx/arch/arm/src/stm32/stm32_waste.h new file mode 100755 index 000000000..11703d5a6 --- /dev/null +++ b/nuttx/arch/arm/src/stm32/stm32_waste.h @@ -0,0 +1,85 @@ +/**************************************************************************** + * arch/arm/src/stm32/stm32_waste.h + * + * Copyright (C) 2011 Uros Platise. All rights reserved. + * Author: Uros Platise <uros.platise@isotel.eu> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32_STM32_WASTE_H +#define __ARCH_ARM_SRC_STM32_STM32_WASTE_H + +/** \file + * \author Uros Platise + * \brief Waste CPU Time + * + * \addtogroup STM32_WASTE + * \{ + */ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" { +#else +#define EXTERN extern +#endif + + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/** Waste CPU Time + * + * up_waste() is the logic that will be executed when portions of kernel + * or user-app is polling some register or similar, waiting for desired + * status. This time is wasted away. This function offers a measure of + * badly written piece of software or some undesired behavior. + * + * At the same time this function adds to some IDLE time which portion + * cannot be used for other purposes (yet). + **/ + +EXTERN void up_waste(void); + + +#undef EXTERN +#if defined(__cplusplus) +} +#endif +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_STM32_STM32_RRC_H */ diff --git a/nuttx/configs/lpcxpresso-lpc1768/README.txt b/nuttx/configs/lpcxpresso-lpc1768/README.txt index b3f3aa875..51622ac41 100755 --- a/nuttx/configs/lpcxpresso-lpc1768/README.txt +++ b/nuttx/configs/lpcxpresso-lpc1768/README.txt @@ -1,561 +1,569 @@ -README
-^^^^^^
-
-README for NuttX port to the Embedded Artists' LPCXpresso base board with
-the LPCXpresso daughter board.
-
-Contents
-^^^^^^^^
-
- LCPXpresso LPC1768 Board
- Development Environment
- GNU Toolchain Options
- NuttX buildroot Toolchain
- Code Red IDE
- LEDs
- LPCXpresso Configuration Options
- Configurations
-
-LCPXpresso LPC1768 Board
-^^^^^^^^^^^^^^^^^^^^^^^^
-
- Pin Description Connector On Board Base Board
- -------------------------------- --------- -------------- ---------------------
-
- P0[0]/RD1/TXD3/SDA1 J6-9 I2C E2PROM SDA TXD3/SDA1
- P0[1]/TD1/RXD3/SCL J6-10 RXD3/SCL1
- P0[2]/TXD0/AD0[7] J6-21
- P0[3]/RXD0/AD0[6] J6-22
- P0[4]/I2SRX-CLK/RD2/CAP2.0 J6-38 CAN_RX2
- P0[5]/I2SRX-WS/TD2/CAP2.1 J6-39 CAN_TX2
- P0[6]/I2SRX_SDA/SSEL1/MAT2[0] J6-8 SSEL1
- P0[7]/I2STX_CLK/SCK1/MAT2[1] J6-7 SCK1
- P0[8]/I2STX_WS/MISO1/MAT2[2] J6-6 MISO1
- P0[9]/I2STX_SDA/MOSI1/MAT2[3] J6-5 MOSI1
- P0[10] J6-40 TXD2/SDA2
- P0[11] J6-41 RXD2/SCL2
- P0[15]/TXD1/SCK0/SCK J6-13 TXD1/SCK0
- P0[16]/RXD1/SSEL0/SSEL J6-14 RXD1/SSEL0
- P0[17]/CTS1/MISO0/MISO J6-12 MISO0
- P0[18]/DCD1/MOSI0/MOSI J6-11 MOSI0
- P0[19]/DSR1/SDA1 PAD17 N/A
- P0[20]/DTR1/SCL1 PAD18 I2C E2PROM SCL N/A
- P0[21]/RI1/MCIPWR/RD1 J6-23
- P0[22]/RTS1/TD1 J6-24 LED
- P0[23]/AD0[0]/I2SRX_CLK/CAP3[0] J6-15 AD0.0
- P0[24]/AD0[1]/I2SRX_WS/CAP3[1] J6-16 AD0.1
- P0[25]/AD0[2]/I2SRX_SDA/TXD3 J6-17 AD0.2
- P0[26]/AD0[3]/AOUT/RXD3 J6-18 AD0.3/AOUT / RGB LED
- P0[27]/SDA0/USB_SDA J6-25
- P0[28]/SCL0 J6-26
- P0[29]/USB_D+ J6-37 USB_D+
- P0[30]/USB_D- J6-36 USB_D-
-
- P1[0]/ENET-TXD0 J6-34? TXD0 TX-(Ethernet PHY)
- P1[1]/ENET_TXD1 J6-35? TXD1 TX+(Ethernet PHY)
- P1[4]/ENET_TX_EN TXEN N/A
- P1[8]/ENET_CRS CRS_DV/MODE2 N/A
- P1[9]/ENET_RXD0 J6-32? RXD0/MODE0 RD-(Ethernet PHY)
- P1[10]/ENET_RXD1 J6-33? RXD1/MODE1 RD+(Ethernet PHY)
- P1[14]/ENET_RX_ER RXER/PHYAD0 N/A
- P1[15]/ENET_REF_CLK REFCLK N/A
- P1[16]/ENET_MDC MDC N/A
- P1[17]/ENET_MDIO MDIO N/A
- P1[18]/USB_UP_LED/PWM1[1]/CAP1[0] PAD1 N/A
- P1[19]/MC0A/USB_PPWR/N_CAP1.1 PAD2 N/A
- P1[20]/MCFB0/PWM1.2/SCK0 PAD3 N/A
- P1[21]/MCABORT/PWM1.3/SSEL0 PAD4 N/A
- P1[22]/MC0B/USB-PWRD/MAT1.0 PAD5 N/A
- P1[23]/MCFB1/PWM1.4/MISO0 PAD6 N/A
- P1[24]/MCFB2/PWM1.5/MOSI0 PAD7 N/A
- P1[25]/MC1A/MAT1.1 PAD8 N/A
- P1[26]/MC1B/PWM1.6/CAP0.0 PAD9 N/A
- P1[27]/CLKOUT/USB-OVRCR-N/CAP0.1 PAD10 N/A
- P1[28]/MC2A/PCAP1.0/MAT0.0 PAD11 N/A
- P1[29]/MC2B/PCAP1.1/MAT0.1 PAD12 N/A
- P1[30]/VBUS/AD0[4] J6-19 AD0.4
- P1[31]/SCK1/AD0[5] J6-20 AD0.5
-
- P2[0]/PWM1.1/TXD1 J6-42 PWM1.1 / RGB LED / RS422 RX
- P2[1]/PWM1.2/RXD1 J6-43 PWM1.2 / OLED voltage / RGB LED
- P2[2]/PWM1.3/CTS1/TRACEDATA[3] J6-44 PWM1.3
- P2[3]/PWM1.4/DCD1/TRACEDATA[2] J6-45 PWM1.4
- P2[4]/PWM1.5/DSR1/TRACEDATA[1] J6-46 PWM1.5
- P2[5]/PWM1[6]/DTR1/TRACEDATA[0] J6-47 PWM1.6
- P2[6]/PCAP1[0]/RI1/TRACECLK J6-48
- P2[7]/RD2/RTS1 J6-49
- P2[8]/TD2/TXD2 J6-50
- P2[9]/USB_CONNECT/RXD2 PAD19 USB Pullup N/A
- P2[10]/EINT0/NMI J6-51
- P2[11]/EINT1/I2STX_CLK J6-52
- P2[12]/EINT2/I2STX_WS j6-53
- P2[13]/EINT3/I2STX_SDA J6-27
-
- P3[25]/MAT0.0/PWM1.2 PAD13 N/A
- P3[26]/STCLK/MAT0.1/PWM1.3 PAD14 N/A
-
- P4[28]/RX-MCLK/MAT2.0/TXD3 PAD15 N/A
- P4[29]/TX-MCLK/MAT2.1/RXD3 PAD16 N/A
-
-Development Environment
-^^^^^^^^^^^^^^^^^^^^^^^
-
- Either Linux or Cygwin on Windows can be used for the development environment.
- The source has been built only using the GNU toolchain (see below). Other
- toolchains will likely cause problems. Testing was performed using the Cygwin
- environment.
-
-GNU Toolchain Options
-^^^^^^^^^^^^^^^^^^^^^
-
- The NuttX make system has been modified to support the following different
- toolchain options.
-
- 1. The CodeSourcery GNU toolchain,
- 2. The devkitARM GNU toolchain,
- 3. The NuttX buildroot Toolchain (see below).
-
- All testing has been conducted using the NuttX buildroot toolchain. However,
- the make system is setup to default to use the devkitARM toolchain. To use
- the CodeSourcery or devkitARM toolchain, you simply need add one of the
- following configuration options to your .config (or defconfig) file:
-
- CONFIG_LPC17_CODESOURCERYW=y : CodeSourcery under Windows
- CONFIG_LPC17_CODESOURCERYL=y : CodeSourcery under Linux
- CONFIG_LPC17_DEVKITARM=y : devkitARM under Windows
- CONFIG_LPC17_BUILDROOT=y : NuttX buildroot under Linux or Cygwin (default)
-
- If you are not using CONFIG_LPC17_BUILDROOT, then you may also have to modify
- the PATH in the setenv.h file if your make cannot find the tools.
-
- NOTE: the CodeSourcery (for Windows)and devkitARM are Windows native toolchains.
- The CodeSourcey (for Linux) and NuttX buildroot toolchains are Cygwin and/or
- Linux native toolchains. There are several limitations to using a Windows based
- toolchain in a Cygwin environment. The three biggest are:
-
- 1. The Windows toolchain cannot follow Cygwin paths. Path conversions are
- performed automatically in the Cygwin makefiles using the 'cygpath' utility
- but you might easily find some new path problems. If so, check out 'cygpath -w'
-
- 2. Windows toolchains cannot follow Cygwin symbolic links. Many symbolic links
- are used in Nuttx (e.g., include/arch). The make system works around these
- problems for the Windows tools by copying directories instead of linking them.
- But this can also cause some confusion for you: For example, you may edit
- a file in a "linked" directory and find that your changes had not effect.
- That is because you are building the copy of the file in the "fake" symbolic
- directory. If you use a Windows toolchain, you should get in the habit of
- making like this:
-
- make clean_context all
-
- An alias in your .bashrc file might make that less painful.
-
- 3. Dependencies are not made when using Windows versions of the GCC. This is
- because the dependencies are generated using Windows pathes which do not
- work with the Cygwin make.
-
- Support has been added for making dependencies with the windows-native toolchains.
- That support can be enabled by modifying your Make.defs file as follows:
-
- - MKDEP = $(TOPDIR)/tools/mknulldeps.sh
- + MKDEP = $(TOPDIR)/tools/mkdeps.sh --winpaths "$(TOPDIR)"
-
- If you have problems with the dependency build (for example, if you are not
- building on C:), then you may need to modify tools/mkdeps.sh
-
- NOTE 1: The CodeSourcery toolchain (2009q1) does not work with default optimization
- level of -Os (See Make.defs). It will work with -O0, -O1, or -O2, but not with
- -Os.
-
- NOTE 2: The devkitARM toolchain includes a version of MSYS make. Make sure that
- the paths to Cygwin's /bin and /usr/bin directories appear BEFORE the devkitARM
- path or will get the wrong version of make.
-
-Code Red IDE
-^^^^^^^^^^^^
-
- NuttX is built using command-line make. It can be used with an IDE, but some
- effort will be required to create the project (There is a simple RIDE project
- in the RIDE subdirectory).
-
- Makefile Build
- --------------
- Under Eclipse, it is pretty easy to set up an "empty makefile project" and
- simply use the NuttX makefile to build the system. That is almost for free
- under Linux. Under Windows, you will need to set up the "Cygwin GCC" empty
- makefile project in order to work with Windows (Google for "Eclipse Cygwin" -
- there is a lot of help on the internet).
-
- Native Build
- ------------
- Here are a few tips before you start that effort:
-
- 1) Select the toolchain that you will be using in your .config file
- 2) Start the NuttX build at least one time from the Cygwin command line
- before trying to create your project. This is necessary to create
- certain auto-generated files and directories that will be needed.
- 3) Set up include pathes: You will need include/, arch/arm/src/lpc17xx,
- arch/arm/src/common, arch/arm/src/cortexm3, and sched/.
- 4) All assembly files need to have the definition option -D __ASSEMBLY__
- on the command line.
-
- Startup files will probably cause you some headaches. The NuttX startup file
- is arch/arm/src/lpc17x/lpc17_vectors.S.
-
- Using Code Red GNU Tools from Cygwin
- ------------------------------------
-
- Under Cygwin, the Code Red command line tools (e.g., arm-non-eabi-gcc) cannot
- be executed because the they only have execut privileges for Administrators. I
- worked around this by:
-
- Opening a native Cygwin RXVT as Administrator (Right click, "Run as administrator"),
- then executing 'chmod 755 *.exe' in the following directories:
-
- /cygdrive/c/nxp/lpcxpreeso_3.6/bin, and
- /cygdrive/c/nxp/lpcxpreeso_3.6/Tools/bin
-
- Command Line Flash Programming
- ------------------------------
-
- If using LPCLink as your debug connection, first of all boot the LPC-Link using
- the script:
-
- bin\Scripts\bootLPCXpresso type
-
- where type = winusb for Windows XP, or type = hid for Windows Vista / 7.
-
- Now run the flash programming utility with the following options
-
- flash_utility wire -ptarget -flash-load[-exec]=filename [-load-base=base_address]
-
- Where flash_utility is one of:
-
- crt_emu_lpc11_13 (for LPC11xx or LPC13xx parts)
- crt_emu_cm3_nxp (for LPC17xx parts)
- crt_emu_a7_nxp (for LPC21/22/23/24 parts)
- crt_emu_a9_nxp (for LPC31/32 and LPC29xx parts)
- crt_emu_cm3_lmi (for TI Stellaris LM3S parts
-
- wire is one of:
-
- (empty) (for Red Probe+, Red Probe, RDB1768v1, or TI Stellaris evaluation boards)
- -wire=hid (for RDB1768v2 without upgraded firmware)
- -wire=winusb (for RDB1768v2 with upgraded firmware)
- -wire=winusb (for LPC-Link on Windows XP)
- -wire=hid (for LPC-Link on Windows Vista/ Windows 7)
-
- target is the target chip name. For example LPC1343, LPC1114/301, LPC1768 etc.
-
- filename is the file to flash program. It may be an executable (axf) or a binary
- (bin) file. If using a binary file, the base_address must be specified.
-
- base_address is the base load address when flash programming a binary file. It
- should be specified as a hex value with a leading 0x.
-
- Note:
- - flash-load will leave the processor in a stopped state
- - flash-load-exec will start execution of application as soon as download has
- completed.
-
- Examples
- To load the executable file app.axf and start it executing on an LPC1758
- target using Red Probe, use the following command line:
-
- crt_emu_cm3_nxp -pLPC1758 -flash-load-exec=app.axf
-
- To load the binary file binary.bin to address 0x1000 to an LPC1343 target
- using LPC-Link on Windows XP, use the following command line:
-
- crt_emu_lpc11_13_nxp -wire=hid -pLPC1343 -flash-load=binary.bin -load-base=0x1000
-
-NuttX buildroot Toolchain
-^^^^^^^^^^^^^^^^^^^^^^^^^
-
- A GNU GCC-based toolchain is assumed. The files */setenv.sh should
- be modified to point to the correct path to the Cortex-M3 GCC toolchain (if
- different from the default in your PATH variable).
-
- If you have no Cortex-M3 toolchain, one can be downloaded from the NuttX
- SourceForge download site (https://sourceforge.net/project/showfiles.php?group_id=189573).
- This GNU toolchain builds and executes in the Linux or Cygwin environment.
-
- 1. You must have already configured Nuttx in <some-dir>/nuttx.
-
- cd tools
- ./configure.sh lpcxpresso-lpc1768/<sub-dir>
-
- 2. Download the latest buildroot package into <some-dir>
-
- 3. unpack the buildroot tarball. The resulting directory may
- have versioning information on it like buildroot-x.y.z. If so,
- rename <some-dir>/buildroot-x.y.z to <some-dir>/buildroot.
-
- 4. cd <some-dir>/buildroot
-
- 5. cp configs/cortexm3-defconfig-4.3.3 .config
-
- 6. make oldconfig
-
- 7. make
-
- 8. Edit setenv.h, if necessary, so that the PATH variable includes
- the path to the newly built binaries.
-
- See the file configs/README.txt in the buildroot source tree. That has more
- detailed PLUS some special instructions that you will need to follow if you
- are building a Cortex-M3 toolchain for Cygwin under Windows.
-
- NOTE: This is an OABI toolchain.
-
-LEDs
-^^^^
-
- If CONFIG_ARCH_LEDS is defined, then support for the LPCXpresso LEDs will be
- included in the build. See:
-
- - configs/lpcxpresso-lpc1768/include/board.h - Defines LED constants, types and
- prototypes the LED interface functions.
-
- - configs/lpcxpresso-lpc1768/src/lpcxpresso_internal.h - GPIO settings for the LEDs.
-
- - configs/lpcxpresso-lpc1768/src/up_leds.c - LED control logic.
-
- The LPCXpresso LPC1768 has a single LEDs (there are more on the Embedded Artists
- base board, but those are not controlled by NuttX). Usage this single LED by NuttX
- is as follows:
-
- - The LED is not illuminated until the LPCXpresso completes initialization.
-
- If the LED is stuck in the OFF state, this means that the LPCXpresso did not
- complete intialization.
-
- - Each time the OS enters an interrupt (or a signal) it will turn the LED OFF and
- restores its previous stated upon return from the interrupt (or signal).
-
- The normal state, after initialization will be a dull glow. The brightness of
- the glow will be inversely related to the proportion of time spent within interrupt
- handling logic. The glow may decrease in brightness when the system is very
- busy handling device interrupts and increase in brightness as the system becomes
- idle.
-
- Stuck in the OFF state suggests that that the system never completed
- initialization; Stuck in the ON state would indicated that the system
- intialialized, but is not takint interrupts.
-
- - If a fatal assertion or a fatal unhandled exception occurs, the LED will flash
- strongly as a slow, 1Hz rate.
-
-LPCXpresso Configuration Options
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
- CONFIG_ARCH - Identifies the arch/ subdirectory. This should
- be set to:
-
- CONFIG_ARCH=arm
-
- CONFIG_ARCH_family - For use in C code:
-
- CONFIG_ARCH_ARM=y
-
- CONFIG_ARCH_architecture - For use in C code:
-
- CONFIG_ARCH_CORTEXM3=y
-
- CONFIG_ARCH_CHIP - Identifies the arch/*/chip subdirectory
-
- CONFIG_ARCH_CHIP=lpc17xx
-
- CONFIG_ARCH_CHIP_name - For use in C code to identify the exact
- chip:
-
- CONFIG_ARCH_CHIP_LPC1768=y
-
- CONFIG_ARCH_BOARD - Identifies the configs subdirectory and
- hence, the board that supports the particular chip or SoC.
-
- CONFIG_ARCH_BOARD=lpcxpresso-lpc1768
-
- CONFIG_ARCH_BOARD_name - For use in C code
-
- CONFIG_ARCH_BOARD_LPCEXPRESSO=y
-
- CONFIG_ARCH_LOOPSPERMSEC - Must be calibrated for correct operation
- of delay loops
-
- CONFIG_ENDIAN_BIG - define if big endian (default is little
- endian)
-
- CONFIG_DRAM_SIZE - Describes the installed DRAM (CPU SRAM in this case):
-
- CONFIG_DRAM_SIZE=(32*1024) (32Kb)
-
- There is an additional 32Kb of SRAM in AHB SRAM banks 0 and 1.
-
- CONFIG_DRAM_START - The start address of installed DRAM
-
- CONFIG_DRAM_START=0x10000000
-
- CONFIG_DRAM_END - Last address+1 of installed RAM
-
- CONFIG_DRAM_END=(CONFIG_DRAM_START+CONFIG_DRAM_SIZE)
-
- CONFIG_ARCH_IRQPRIO - The LPC17xx supports interrupt prioritization
-
- CONFIG_ARCH_IRQPRIO=y
-
- CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to boards that
- have LEDs
-
- CONFIG_ARCH_INTERRUPTSTACK - This architecture supports an interrupt
- stack. If defined, this symbol is the size of the interrupt
- stack in bytes. If not defined, the user task stacks will be
- used during interrupt handling.
-
- CONFIG_ARCH_STACKDUMP - Do stack dumps after assertions
-
- CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to board architecture.
-
- CONFIG_ARCH_CALIBRATION - Enables some build in instrumentation that
- cause a 100 second delay during boot-up. This 100 second delay
- serves no purpose other than it allows you to calibratre
- CONFIG_ARCH_LOOPSPERMSEC. You simply use a stop watch to measure
- the 100 second delay then adjust CONFIG_ARCH_LOOPSPERMSEC until
- the delay actually is 100 seconds.
-
- Individual subsystems can be enabled:
- CONFIG_LPC17_MAINOSC=y
- CONFIG_LPC17_PLL0=y
- CONFIG_LPC17_PLL1=n
- CONFIG_LPC17_ETHERNET=n
- CONFIG_LPC17_USBHOST=n
- CONFIG_LPC17_USBOTG=n
- CONFIG_LPC17_USBDEV=n
- CONFIG_LPC17_UART0=y
- CONFIG_LPC17_UART1=n
- CONFIG_LPC17_UART2=n
- CONFIG_LPC17_UART3=n
- CONFIG_LPC17_CAN1=n
- CONFIG_LPC17_CAN2=n
- CONFIG_LPC17_SPI=n
- CONFIG_LPC17_SSP0=n
- CONFIG_LPC17_SSP1=n
- CONFIG_LPC17_I2C0=n
- CONFIG_LPC17_I2C1=n
- CONFIG_LPC17_I2S=n
- CONFIG_LPC17_TMR0=n
- CONFIG_LPC17_TMR1=n
- CONFIG_LPC17_TMR2=n
- CONFIG_LPC17_TMR3=n
- CONFIG_LPC17_RIT=n
- CONFIG_LPC17_PWM=n
- CONFIG_LPC17_MCPWM=n
- CONFIG_LPC17_QEI=n
- CONFIG_LPC17_RTC=n
- CONFIG_LPC17_WDT=n
- CONFIG_LPC17_ADC=n
- CONFIG_LPC17_DAC=n
- CONFIG_LPC17_GPDMA=n
- CONFIG_LPC17_FLASH=n
-
- LPC17xx specific device driver settings
-
- CONFIG_UARTn_SERIAL_CONSOLE - selects the UARTn for the
- console and ttys0 (default is the UART0).
- CONFIG_UARTn_RXBUFSIZE - Characters are buffered as received.
- This specific the size of the receive buffer
- CONFIG_UARTn_TXBUFSIZE - Characters are buffered before
- being sent. This specific the size of the transmit buffer
- CONFIG_UARTn_BAUD - The configure BAUD of the UART. Must be
- CONFIG_UARTn_BITS - The number of bits. Must be either 7 or 8.
- CONFIG_UARTn_PARTIY - 0=no parity, 1=odd parity, 2=even parity
- CONFIG_UARTn_2STOP - Two stop bits
-
- LPC17xx specific PHY/Ethernet device driver settings. These setting
- also require CONFIG_NET and CONFIG_LPC17_ETHERNET.
-
- CONFIG_PHY_KS8721 - Selects Micrel KS8721 PHY
- CONFIG_PHY_AUTONEG - Enable auto-negotion
- CONFIG_PHY_SPEED100 - Select 100Mbit vs. 10Mbit speed.
- CONFIG_PHY_FDUPLEX - Select full (vs. half) duplex
-
- CONFIG_NET_EMACRAM_SIZE - Size of EMAC RAM. Default: 16Kb
- CONFIG_NET_NTXDESC - Configured number of Tx descriptors. Default: 18
- CONFIG_NET_NRXDESC - Configured number of Rx descriptors. Default: 18
- CONFIG_NET_PRIORITY - Ethernet interrupt priority. The is default is
- the higest priority.
- CONFIG_NET_WOL - Enable Wake-up on Lan (not fully implemented).
- CONFIG_NET_REGDEBUG - Enabled low level register debug. Also needs
- CONFIG_DEBUG.
- CONFIG_NET_DUMPPACKET - Dump all received and transmitted packets.
- Also needs CONFIG_DEBUG.
- CONFIG_NET_HASH - Enable receipt of near-perfect match frames.
- CONFIG_NET_MULTICAST - Enable receipt of multicast (and unicast) frames.
- Automatically set if CONFIG_NET_IGMP is selected.
-
- LPC17xx USB Device Configuration
-
- CONFIG_LPC17_USBDEV_FRAME_INTERRUPT
- Handle USB Start-Of-Frame events.
- Enable reading SOF from interrupt handler vs. simply reading on demand.
- Probably a bad idea... Unless there is some issue with sampling the SOF
- from hardware asynchronously.
- CONFIG_LPC17_USBDEV_EPFAST_INTERRUPT
- Enable high priority interrupts. I have no idea why you might want to
- do that
- CONFIG_LPC17_USBDEV_NDMADESCRIPTORS
- Number of DMA descriptors to allocate in SRAM.
- CONFIG_LPC17_USBDEV_DMA
- Enable lpc17xx-specific DMA support
-
- LPC17xx USB Host Configuration (the LPCXpresso does not support USB Host)
-
- CONFIG_USBHOST_OHCIRAM_SIZE
- Total size of OHCI RAM (in AHB SRAM Bank 1)
- CONFIG_USBHOST_NEDS
- Number of endpoint descriptors
- CONFIG_USBHOST_NTDS
- Number of transfer descriptors
- CONFIG_USBHOST_TDBUFFERS
- Number of transfer descriptor buffers
- CONFIG_USBHOST_TDBUFSIZE
- Size of one transfer descriptor buffer
- CONFIG_USBHOST_IOBUFSIZE
- Size of one end-user I/O buffer. This can be zero if the
- application can guarantee that all end-user I/O buffers
- reside in AHB SRAM.
-
-Configurations
-^^^^^^^^^^^^^^
-
-Each LPCXpresso configuration is maintained in a sudirectory and can be
-selected as follow:
-
- cd tools
- ./configure.sh lpcxpresso-lpc1768/<subdir>
- cd -
- . ./setenv.sh
-
-Where <subdir> is one of the following:
-
- nsh:
- Configures the NuttShell (nsh) located at examples/nsh. The
- Configuration enables both the serial and telnet NSH interfaces.
- Support for the board's SPI-based MicroSD card is included
- (but not passing tests as of this writing).
-
- ostest:
- This configuration directory, performs a simple OS test using
- examples/ostest.
-
- NOTE: The OSTest runs on the LPCXpresso if it is not installed
- on the base board (using an add-on MAX232 RS232 driver connected
- to:
-
- P0[0]/RD1/TXD3/SDA1 J6-9
- P0[1]/TD1/RXD3/SCL J6-10
-
- I suspect that this test does not run on with the base board
- attached because OSTest blasts out a lot of serial data and
- overruns the FTDI chip before it has a chance to establish the
- connection with the host.
+README +^^^^^^ + +README for NuttX port to the Embedded Artists' LPCXpresso base board with +the LPCXpresso daughter board. + +Contents +^^^^^^^^ + + LCPXpresso LPC1768 Board + Jumpers + Development Environment + GNU Toolchain Options + NuttX buildroot Toolchain + Code Red IDE + LEDs + LPCXpresso Configuration Options + Configurations + +LCPXpresso LPC1768 Board +^^^^^^^^^^^^^^^^^^^^^^^^ + + Pin Description Connector On Board Base Board + -------------------------------- --------- -------------- --------------------- + + P0[0]/RD1/TXD3/SDA1 J6-9 I2C E2PROM SDA TXD3/SDA1 + P0[1]/TD1/RXD3/SCL J6-10 RXD3/SCL1 + P0[2]/TXD0/AD0[7] J6-21 + P0[3]/RXD0/AD0[6] J6-22 + P0[4]/I2SRX-CLK/RD2/CAP2.0 J6-38 CAN_RX2 + P0[5]/I2SRX-WS/TD2/CAP2.1 J6-39 CAN_TX2 + P0[6]/I2SRX_SDA/SSEL1/MAT2[0] J6-8 SSEL1 + P0[7]/I2STX_CLK/SCK1/MAT2[1] J6-7 SCK1 + P0[8]/I2STX_WS/MISO1/MAT2[2] J6-6 MISO1 + P0[9]/I2STX_SDA/MOSI1/MAT2[3] J6-5 MOSI1 + P0[10] J6-40 TXD2/SDA2 + P0[11] J6-41 RXD2/SCL2 + P0[15]/TXD1/SCK0/SCK J6-13 TXD1/SCK0 + P0[16]/RXD1/SSEL0/SSEL J6-14 RXD1/SSEL0 + P0[17]/CTS1/MISO0/MISO J6-12 MISO0 + P0[18]/DCD1/MOSI0/MOSI J6-11 MOSI0 + P0[19]/DSR1/SDA1 PAD17 N/A + P0[20]/DTR1/SCL1 PAD18 I2C E2PROM SCL N/A + P0[21]/RI1/MCIPWR/RD1 J6-23 + P0[22]/RTS1/TD1 J6-24 LED + P0[23]/AD0[0]/I2SRX_CLK/CAP3[0] J6-15 AD0.0 + P0[24]/AD0[1]/I2SRX_WS/CAP3[1] J6-16 AD0.1 + P0[25]/AD0[2]/I2SRX_SDA/TXD3 J6-17 AD0.2 + P0[26]/AD0[3]/AOUT/RXD3 J6-18 AD0.3/AOUT / RGB LED + P0[27]/SDA0/USB_SDA J6-25 + P0[28]/SCL0 J6-26 + P0[29]/USB_D+ J6-37 USB_D+ + P0[30]/USB_D- J6-36 USB_D- + + P1[0]/ENET-TXD0 J6-34? TXD0 TX-(Ethernet PHY) + P1[1]/ENET_TXD1 J6-35? TXD1 TX+(Ethernet PHY) + P1[4]/ENET_TX_EN TXEN N/A + P1[8]/ENET_CRS CRS_DV/MODE2 N/A + P1[9]/ENET_RXD0 J6-32? RXD0/MODE0 RD-(Ethernet PHY) + P1[10]/ENET_RXD1 J6-33? RXD1/MODE1 RD+(Ethernet PHY) + P1[14]/ENET_RX_ER RXER/PHYAD0 N/A + P1[15]/ENET_REF_CLK REFCLK N/A + P1[16]/ENET_MDC MDC N/A + P1[17]/ENET_MDIO MDIO N/A + P1[18]/USB_UP_LED/PWM1[1]/CAP1[0] PAD1 N/A + P1[19]/MC0A/USB_PPWR/N_CAP1.1 PAD2 N/A + P1[20]/MCFB0/PWM1.2/SCK0 PAD3 N/A + P1[21]/MCABORT/PWM1.3/SSEL0 PAD4 N/A + P1[22]/MC0B/USB-PWRD/MAT1.0 PAD5 N/A + P1[23]/MCFB1/PWM1.4/MISO0 PAD6 N/A + P1[24]/MCFB2/PWM1.5/MOSI0 PAD7 N/A + P1[25]/MC1A/MAT1.1 PAD8 N/A + P1[26]/MC1B/PWM1.6/CAP0.0 PAD9 N/A + P1[27]/CLKOUT/USB-OVRCR-N/CAP0.1 PAD10 N/A + P1[28]/MC2A/PCAP1.0/MAT0.0 PAD11 N/A + P1[29]/MC2B/PCAP1.1/MAT0.1 PAD12 N/A + P1[30]/VBUS/AD0[4] J6-19 AD0.4 + P1[31]/SCK1/AD0[5] J6-20 AD0.5 + + P2[0]/PWM1.1/TXD1 J6-42 PWM1.1 / RGB LED / RS422 RX + P2[1]/PWM1.2/RXD1 J6-43 PWM1.2 / OLED voltage / RGB LED + P2[2]/PWM1.3/CTS1/TRACEDATA[3] J6-44 PWM1.3 + P2[3]/PWM1.4/DCD1/TRACEDATA[2] J6-45 PWM1.4 + P2[4]/PWM1.5/DSR1/TRACEDATA[1] J6-46 PWM1.5 + P2[5]/PWM1[6]/DTR1/TRACEDATA[0] J6-47 PWM1.6 + P2[6]/PCAP1[0]/RI1/TRACECLK J6-48 + P2[7]/RD2/RTS1 J6-49 + P2[8]/TD2/TXD2 J6-50 + P2[9]/USB_CONNECT/RXD2 PAD19 USB Pullup N/A + P2[10]/EINT0/NMI J6-51 + P2[11]/EINT1/I2STX_CLK J6-52 + P2[12]/EINT2/I2STX_WS j6-53 + P2[13]/EINT3/I2STX_SDA J6-27 + + P3[25]/MAT0.0/PWM1.2 PAD13 N/A + P3[26]/STCLK/MAT0.1/PWM1.3 PAD14 N/A + + P4[28]/RX-MCLK/MAT2.0/TXD3 PAD15 N/A + P4[29]/TX-MCLK/MAT2.1/RXD3 PAD16 N/A + +Jumpers +^^^^^^^ + + There are many jumpers on the base board. A usable combination is the + default jumper settings WITH the two J54 jumpers both removed. Those + jumpers are for ISP support and will cause the board to reset. + +Development Environment +^^^^^^^^^^^^^^^^^^^^^^^ + + Either Linux or Cygwin on Windows can be used for the development environment. + The source has been built only using the GNU toolchain (see below). Other + toolchains will likely cause problems. Testing was performed using the Cygwin + environment. + +GNU Toolchain Options +^^^^^^^^^^^^^^^^^^^^^ + + The NuttX make system has been modified to support the following different + toolchain options. + + 1. The CodeSourcery GNU toolchain, + 2. The devkitARM GNU toolchain, + 3. The NuttX buildroot Toolchain (see below). + + All testing has been conducted using the NuttX buildroot toolchain. However, + the make system is setup to default to use the devkitARM toolchain. To use + the CodeSourcery or devkitARM toolchain, you simply need add one of the + following configuration options to your .config (or defconfig) file: + + CONFIG_LPC17_CODESOURCERYW=y : CodeSourcery under Windows + CONFIG_LPC17_CODESOURCERYL=y : CodeSourcery under Linux + CONFIG_LPC17_DEVKITARM=y : devkitARM under Windows + CONFIG_LPC17_BUILDROOT=y : NuttX buildroot under Linux or Cygwin (default) + + If you are not using CONFIG_LPC17_BUILDROOT, then you may also have to modify + the PATH in the setenv.h file if your make cannot find the tools. + + NOTE: the CodeSourcery (for Windows)and devkitARM are Windows native toolchains. + The CodeSourcey (for Linux) and NuttX buildroot toolchains are Cygwin and/or + Linux native toolchains. There are several limitations to using a Windows based + toolchain in a Cygwin environment. The three biggest are: + + 1. The Windows toolchain cannot follow Cygwin paths. Path conversions are + performed automatically in the Cygwin makefiles using the 'cygpath' utility + but you might easily find some new path problems. If so, check out 'cygpath -w' + + 2. Windows toolchains cannot follow Cygwin symbolic links. Many symbolic links + are used in Nuttx (e.g., include/arch). The make system works around these + problems for the Windows tools by copying directories instead of linking them. + But this can also cause some confusion for you: For example, you may edit + a file in a "linked" directory and find that your changes had not effect. + That is because you are building the copy of the file in the "fake" symbolic + directory. If you use a Windows toolchain, you should get in the habit of + making like this: + + make clean_context all + + An alias in your .bashrc file might make that less painful. + + 3. Dependencies are not made when using Windows versions of the GCC. This is + because the dependencies are generated using Windows pathes which do not + work with the Cygwin make. + + Support has been added for making dependencies with the windows-native toolchains. + That support can be enabled by modifying your Make.defs file as follows: + + - MKDEP = $(TOPDIR)/tools/mknulldeps.sh + + MKDEP = $(TOPDIR)/tools/mkdeps.sh --winpaths "$(TOPDIR)" + + If you have problems with the dependency build (for example, if you are not + building on C:), then you may need to modify tools/mkdeps.sh + + NOTE 1: The CodeSourcery toolchain (2009q1) does not work with default optimization + level of -Os (See Make.defs). It will work with -O0, -O1, or -O2, but not with + -Os. + + NOTE 2: The devkitARM toolchain includes a version of MSYS make. Make sure that + the paths to Cygwin's /bin and /usr/bin directories appear BEFORE the devkitARM + path or will get the wrong version of make. + +Code Red IDE +^^^^^^^^^^^^ + + NuttX is built using command-line make. It can be used with an IDE, but some + effort will be required to create the project (There is a simple RIDE project + in the RIDE subdirectory). + + Makefile Build + -------------- + Under Eclipse, it is pretty easy to set up an "empty makefile project" and + simply use the NuttX makefile to build the system. That is almost for free + under Linux. Under Windows, you will need to set up the "Cygwin GCC" empty + makefile project in order to work with Windows (Google for "Eclipse Cygwin" - + there is a lot of help on the internet). + + Native Build + ------------ + Here are a few tips before you start that effort: + + 1) Select the toolchain that you will be using in your .config file + 2) Start the NuttX build at least one time from the Cygwin command line + before trying to create your project. This is necessary to create + certain auto-generated files and directories that will be needed. + 3) Set up include pathes: You will need include/, arch/arm/src/lpc17xx, + arch/arm/src/common, arch/arm/src/cortexm3, and sched/. + 4) All assembly files need to have the definition option -D __ASSEMBLY__ + on the command line. + + Startup files will probably cause you some headaches. The NuttX startup file + is arch/arm/src/lpc17x/lpc17_vectors.S. + + Using Code Red GNU Tools from Cygwin + ------------------------------------ + + Under Cygwin, the Code Red command line tools (e.g., arm-non-eabi-gcc) cannot + be executed because the they only have execut privileges for Administrators. I + worked around this by: + + Opening a native Cygwin RXVT as Administrator (Right click, "Run as administrator"), + then executing 'chmod 755 *.exe' in the following directories: + + /cygdrive/c/nxp/lpcxpreeso_3.6/bin, and + /cygdrive/c/nxp/lpcxpreeso_3.6/Tools/bin + + Command Line Flash Programming + ------------------------------ + + If using LPCLink as your debug connection, first of all boot the LPC-Link using + the script: + + bin\Scripts\bootLPCXpresso type + + where type = winusb for Windows XP, or type = hid for Windows Vista / 7. + + Now run the flash programming utility with the following options + + flash_utility wire -ptarget -flash-load[-exec]=filename [-load-base=base_address] + + Where flash_utility is one of: + + crt_emu_lpc11_13 (for LPC11xx or LPC13xx parts) + crt_emu_cm3_nxp (for LPC17xx parts) + crt_emu_a7_nxp (for LPC21/22/23/24 parts) + crt_emu_a9_nxp (for LPC31/32 and LPC29xx parts) + crt_emu_cm3_lmi (for TI Stellaris LM3S parts + + wire is one of: + + (empty) (for Red Probe+, Red Probe, RDB1768v1, or TI Stellaris evaluation boards) + -wire=hid (for RDB1768v2 without upgraded firmware) + -wire=winusb (for RDB1768v2 with upgraded firmware) + -wire=winusb (for LPC-Link on Windows XP) + -wire=hid (for LPC-Link on Windows Vista/ Windows 7) + + target is the target chip name. For example LPC1343, LPC1114/301, LPC1768 etc. + + filename is the file to flash program. It may be an executable (axf) or a binary + (bin) file. If using a binary file, the base_address must be specified. + + base_address is the base load address when flash programming a binary file. It + should be specified as a hex value with a leading 0x. + + Note: + - flash-load will leave the processor in a stopped state + - flash-load-exec will start execution of application as soon as download has + completed. + + Examples + To load the executable file app.axf and start it executing on an LPC1758 + target using Red Probe, use the following command line: + + crt_emu_cm3_nxp -pLPC1758 -flash-load-exec=app.axf + + To load the binary file binary.bin to address 0x1000 to an LPC1343 target + using LPC-Link on Windows XP, use the following command line: + + crt_emu_lpc11_13_nxp -wire=hid -pLPC1343 -flash-load=binary.bin -load-base=0x1000 + +NuttX buildroot Toolchain +^^^^^^^^^^^^^^^^^^^^^^^^^ + + A GNU GCC-based toolchain is assumed. The files */setenv.sh should + be modified to point to the correct path to the Cortex-M3 GCC toolchain (if + different from the default in your PATH variable). + + If you have no Cortex-M3 toolchain, one can be downloaded from the NuttX + SourceForge download site (https://sourceforge.net/project/showfiles.php?group_id=189573). + This GNU toolchain builds and executes in the Linux or Cygwin environment. + + 1. You must have already configured Nuttx in <some-dir>/nuttx. + + cd tools + ./configure.sh lpcxpresso-lpc1768/<sub-dir> + + 2. Download the latest buildroot package into <some-dir> + + 3. unpack the buildroot tarball. The resulting directory may + have versioning information on it like buildroot-x.y.z. If so, + rename <some-dir>/buildroot-x.y.z to <some-dir>/buildroot. + + 4. cd <some-dir>/buildroot + + 5. cp configs/cortexm3-defconfig-4.3.3 .config + + 6. make oldconfig + + 7. make + + 8. Edit setenv.h, if necessary, so that the PATH variable includes + the path to the newly built binaries. + + See the file configs/README.txt in the buildroot source tree. That has more + detailed PLUS some special instructions that you will need to follow if you + are building a Cortex-M3 toolchain for Cygwin under Windows. + + NOTE: This is an OABI toolchain. + +LEDs +^^^^ + + If CONFIG_ARCH_LEDS is defined, then support for the LPCXpresso LEDs will be + included in the build. See: + + - configs/lpcxpresso-lpc1768/include/board.h - Defines LED constants, types and + prototypes the LED interface functions. + + - configs/lpcxpresso-lpc1768/src/lpcxpresso_internal.h - GPIO settings for the LEDs. + + - configs/lpcxpresso-lpc1768/src/up_leds.c - LED control logic. + + The LPCXpresso LPC1768 has a single LEDs (there are more on the Embedded Artists + base board, but those are not controlled by NuttX). Usage this single LED by NuttX + is as follows: + + - The LED is not illuminated until the LPCXpresso completes initialization. + + If the LED is stuck in the OFF state, this means that the LPCXpresso did not + complete intialization. + + - Each time the OS enters an interrupt (or a signal) it will turn the LED OFF and + restores its previous stated upon return from the interrupt (or signal). + + The normal state, after initialization will be a dull glow. The brightness of + the glow will be inversely related to the proportion of time spent within interrupt + handling logic. The glow may decrease in brightness when the system is very + busy handling device interrupts and increase in brightness as the system becomes + idle. + + Stuck in the OFF state suggests that that the system never completed + initialization; Stuck in the ON state would indicated that the system + intialialized, but is not takint interrupts. + + - If a fatal assertion or a fatal unhandled exception occurs, the LED will flash + strongly as a slow, 1Hz rate. + +LPCXpresso Configuration Options +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + + CONFIG_ARCH - Identifies the arch/ subdirectory. This should + be set to: + + CONFIG_ARCH=arm + + CONFIG_ARCH_family - For use in C code: + + CONFIG_ARCH_ARM=y + + CONFIG_ARCH_architecture - For use in C code: + + CONFIG_ARCH_CORTEXM3=y + + CONFIG_ARCH_CHIP - Identifies the arch/*/chip subdirectory + + CONFIG_ARCH_CHIP=lpc17xx + + CONFIG_ARCH_CHIP_name - For use in C code to identify the exact + chip: + + CONFIG_ARCH_CHIP_LPC1768=y + + CONFIG_ARCH_BOARD - Identifies the configs subdirectory and + hence, the board that supports the particular chip or SoC. + + CONFIG_ARCH_BOARD=lpcxpresso-lpc1768 + + CONFIG_ARCH_BOARD_name - For use in C code + + CONFIG_ARCH_BOARD_LPCEXPRESSO=y + + CONFIG_ARCH_LOOPSPERMSEC - Must be calibrated for correct operation + of delay loops + + CONFIG_ENDIAN_BIG - define if big endian (default is little + endian) + + CONFIG_DRAM_SIZE - Describes the installed DRAM (CPU SRAM in this case): + + CONFIG_DRAM_SIZE=(32*1024) (32Kb) + + There is an additional 32Kb of SRAM in AHB SRAM banks 0 and 1. + + CONFIG_DRAM_START - The start address of installed DRAM + + CONFIG_DRAM_START=0x10000000 + + CONFIG_DRAM_END - Last address+1 of installed RAM + + CONFIG_DRAM_END=(CONFIG_DRAM_START+CONFIG_DRAM_SIZE) + + CONFIG_ARCH_IRQPRIO - The LPC17xx supports interrupt prioritization + + CONFIG_ARCH_IRQPRIO=y + + CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to boards that + have LEDs + + CONFIG_ARCH_INTERRUPTSTACK - This architecture supports an interrupt + stack. If defined, this symbol is the size of the interrupt + stack in bytes. If not defined, the user task stacks will be + used during interrupt handling. + + CONFIG_ARCH_STACKDUMP - Do stack dumps after assertions + + CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to board architecture. + + CONFIG_ARCH_CALIBRATION - Enables some build in instrumentation that + cause a 100 second delay during boot-up. This 100 second delay + serves no purpose other than it allows you to calibratre + CONFIG_ARCH_LOOPSPERMSEC. You simply use a stop watch to measure + the 100 second delay then adjust CONFIG_ARCH_LOOPSPERMSEC until + the delay actually is 100 seconds. + + Individual subsystems can be enabled: + CONFIG_LPC17_MAINOSC=y + CONFIG_LPC17_PLL0=y + CONFIG_LPC17_PLL1=n + CONFIG_LPC17_ETHERNET=n + CONFIG_LPC17_USBHOST=n + CONFIG_LPC17_USBOTG=n + CONFIG_LPC17_USBDEV=n + CONFIG_LPC17_UART0=y + CONFIG_LPC17_UART1=n + CONFIG_LPC17_UART2=n + CONFIG_LPC17_UART3=n + CONFIG_LPC17_CAN1=n + CONFIG_LPC17_CAN2=n + CONFIG_LPC17_SPI=n + CONFIG_LPC17_SSP0=n + CONFIG_LPC17_SSP1=n + CONFIG_LPC17_I2C0=n + CONFIG_LPC17_I2C1=n + CONFIG_LPC17_I2S=n + CONFIG_LPC17_TMR0=n + CONFIG_LPC17_TMR1=n + CONFIG_LPC17_TMR2=n + CONFIG_LPC17_TMR3=n + CONFIG_LPC17_RIT=n + CONFIG_LPC17_PWM=n + CONFIG_LPC17_MCPWM=n + CONFIG_LPC17_QEI=n + CONFIG_LPC17_RTC=n + CONFIG_LPC17_WDT=n + CONFIG_LPC17_ADC=n + CONFIG_LPC17_DAC=n + CONFIG_LPC17_GPDMA=n + CONFIG_LPC17_FLASH=n + + LPC17xx specific device driver settings + + CONFIG_UARTn_SERIAL_CONSOLE - selects the UARTn for the + console and ttys0 (default is the UART0). + CONFIG_UARTn_RXBUFSIZE - Characters are buffered as received. + This specific the size of the receive buffer + CONFIG_UARTn_TXBUFSIZE - Characters are buffered before + being sent. This specific the size of the transmit buffer + CONFIG_UARTn_BAUD - The configure BAUD of the UART. Must be + CONFIG_UARTn_BITS - The number of bits. Must be either 7 or 8. + CONFIG_UARTn_PARTIY - 0=no parity, 1=odd parity, 2=even parity + CONFIG_UARTn_2STOP - Two stop bits + + LPC17xx specific PHY/Ethernet device driver settings. These setting + also require CONFIG_NET and CONFIG_LPC17_ETHERNET. + + CONFIG_PHY_KS8721 - Selects Micrel KS8721 PHY + CONFIG_PHY_AUTONEG - Enable auto-negotion + CONFIG_PHY_SPEED100 - Select 100Mbit vs. 10Mbit speed. + CONFIG_PHY_FDUPLEX - Select full (vs. half) duplex + + CONFIG_NET_EMACRAM_SIZE - Size of EMAC RAM. Default: 16Kb + CONFIG_NET_NTXDESC - Configured number of Tx descriptors. Default: 18 + CONFIG_NET_NRXDESC - Configured number of Rx descriptors. Default: 18 + CONFIG_NET_PRIORITY - Ethernet interrupt priority. The is default is + the higest priority. + CONFIG_NET_WOL - Enable Wake-up on Lan (not fully implemented). + CONFIG_NET_REGDEBUG - Enabled low level register debug. Also needs + CONFIG_DEBUG. + CONFIG_NET_DUMPPACKET - Dump all received and transmitted packets. + Also needs CONFIG_DEBUG. + CONFIG_NET_HASH - Enable receipt of near-perfect match frames. + CONFIG_NET_MULTICAST - Enable receipt of multicast (and unicast) frames. + Automatically set if CONFIG_NET_IGMP is selected. + + LPC17xx USB Device Configuration + + CONFIG_LPC17_USBDEV_FRAME_INTERRUPT + Handle USB Start-Of-Frame events. + Enable reading SOF from interrupt handler vs. simply reading on demand. + Probably a bad idea... Unless there is some issue with sampling the SOF + from hardware asynchronously. + CONFIG_LPC17_USBDEV_EPFAST_INTERRUPT + Enable high priority interrupts. I have no idea why you might want to + do that + CONFIG_LPC17_USBDEV_NDMADESCRIPTORS + Number of DMA descriptors to allocate in SRAM. + CONFIG_LPC17_USBDEV_DMA + Enable lpc17xx-specific DMA support + + LPC17xx USB Host Configuration (the LPCXpresso does not support USB Host) + + CONFIG_USBHOST_OHCIRAM_SIZE + Total size of OHCI RAM (in AHB SRAM Bank 1) + CONFIG_USBHOST_NEDS + Number of endpoint descriptors + CONFIG_USBHOST_NTDS + Number of transfer descriptors + CONFIG_USBHOST_TDBUFFERS + Number of transfer descriptor buffers + CONFIG_USBHOST_TDBUFSIZE + Size of one transfer descriptor buffer + CONFIG_USBHOST_IOBUFSIZE + Size of one end-user I/O buffer. This can be zero if the + application can guarantee that all end-user I/O buffers + reside in AHB SRAM. + +Configurations +^^^^^^^^^^^^^^ + +Each LPCXpresso configuration is maintained in a sudirectory and can be +selected as follow: + + cd tools + ./configure.sh lpcxpresso-lpc1768/<subdir> + cd - + . ./setenv.sh + +Where <subdir> is one of the following: + + nsh: + Configures the NuttShell (nsh) located at examples/nsh. The + Configuration enables both the serial and telnet NSH interfaces. + Support for the board's SPI-based MicroSD card is included + (but not passing tests as of this writing). + + ostest: + This configuration directory, performs a simple OS test using + examples/ostest. + + NOTE: The OSTest runs on the LPCXpresso if it is not installed + on the base board (using an add-on MAX232 RS232 driver connected + to: + + P0[0]/RD1/TXD3/SDA1 J6-9 + P0[1]/TD1/RXD3/SCL J6-10 + + I suspect that this test does not run on with the base board + attached because OSTest blasts out a lot of serial data and + overruns the FTDI chip before it has a chance to establish the + connection with the host. diff --git a/nuttx/configs/vsn/include/nsh_romfsimg.h b/nuttx/configs/vsn/include/nsh_romfsimg.h index 7fa7c28ee..b3e894a5b 100755 --- a/nuttx/configs/vsn/include/nsh_romfsimg.h +++ b/nuttx/configs/vsn/include/nsh_romfsimg.h @@ -1,6 +1,6 @@ unsigned char romfs_img[] = { - 0x2d, 0x72, 0x6f, 0x6d, 0x31, 0x66, 0x73, 0x2d, 0x00, 0x00, 0x02, 0x00, - 0x95, 0x7e, 0x5e, 0x1a, 0x4e, 0x53, 0x48, 0x49, 0x6e, 0x69, 0x74, 0x56, + 0x2d, 0x72, 0x6f, 0x6d, 0x31, 0x66, 0x73, 0x2d, 0x00, 0x00, 0x02, 0x10, + 0xad, 0x5b, 0x65, 0xae, 0x4e, 0x53, 0x48, 0x49, 0x6e, 0x69, 0x74, 0x56, 0x6f, 0x6c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x49, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0xd1, 0xff, 0xff, 0x97, 0x2e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -15,34 +15,34 @@ unsigned char romfs_img[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0xd1, 0xff, 0xfe, 0xe0, 0x2e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x1c, - 0x8d, 0x9c, 0xab, 0xda, 0x72, 0x63, 0x53, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x29, + 0x8d, 0x9c, 0xab, 0xcd, 0x72, 0x63, 0x53, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x65, 0x63, 0x68, 0x6f, - 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make the rrload binary format used with @@ -870,3 +876,11 @@ CONFIG_APPS_DIR="../apps" # Provide /dev/ramX and then: mount -t binfs /dev/ram0 /bin CONFIG_APPS_BINDIR=y + +# Application configuration + +CONFIG_APPS_DIR="../apps" + +# Application configuration + +CONFIG_APPS_DIR="../apps" diff --git a/nuttx/configs/vsn/src/sif.c b/nuttx/configs/vsn/src/sif.c index 6f75c4a9e..555c43f63 100644 --- a/nuttx/configs/vsn/src/sif.c +++ b/nuttx/configs/vsn/src/sif.c @@ -70,8 +70,13 @@ #include <nuttx/config.h> #include <nuttx/fs.h> -#include <nuttx/i2c/i2c.h> #include <semaphore.h> +#include <nuttx/clock.h> +#include <nuttx/time.h> +#include <nuttx/rtc.h> + +#include <nuttx/i2c/i2c.h> +#include <nuttx/i2c/st_lis331dl.h> #include <stdio.h> #include <stdlib.h> @@ -80,7 +85,7 @@ #include <errno.h> #include "vsn.h" -#include <nuttx/i2c/st_lis331dl.h> + /**************************************************************************** @@ -297,10 +302,7 @@ int sif_anout_init(void) { vsn_sif.tim3 = stm32_tim_init(3); vsn_sif.tim8 = stm32_tim_init(8); - - vsn_sif.i2c1 = up_i2cinitialize(1); - vsn_sif.i2c2 = up_i2cinitialize(2); - + if (!vsn_sif.tim3 || !vsn_sif.tim8) return ERROR; // Use the TIM3 as PWM modulated analogue output @@ -318,12 +320,15 @@ int sif_anout_init(void) STM32_TIM_ENABLEINT(vsn_sif.tim8, 0); STM32_TIM_SETPERIOD(vsn_sif.tim8, 4096); - STM32_TIM_SETCOMPARE(vsn_sif.tim8, GPIO_OUT_PWRPWM_TIM8_CH, 0); + STM32_TIM_SETCOMPARE(vsn_sif.tim8, GPIO_OUT_PWRPWM_TIM8_CH, 5000); STM32_TIM_SETCLOCK(vsn_sif.tim8, 36e6); STM32_TIM_SETMODE(vsn_sif.tim8, STM32_TIM_MODE_UP); STM32_TIM_SETCHANNEL(vsn_sif.tim8, GPIO_OUT_PWRPWM_TIM8_CH, STM32_TIM_CH_OUTPWM | STM32_TIM_CH_POLARITY_NEG); + vsn_sif.i2c1 = up_i2cinitialize(1); + vsn_sif.i2c2 = up_i2cinitialize(2); + return OK; } @@ -470,7 +475,7 @@ int sif_init(void) sif_gpios_reset(); if ( sif_anout_init() != OK ) return -1; - + /* If everything is okay, register the driver */ (void)register_driver("/dev/sif0", &devsif_fops, 0666, NULL); @@ -502,28 +507,41 @@ int sif_main(int argc, char *argv[]) STM32_TIM_SETCOMPARE(vsn_sif.tim8, GPIO_OUT_PWRPWM_TIM8_CH, val); return 0; } + else if (!strcmp(argv[1], "time") && argc == 3) { + int val = atoi(argv[2]); + up_rtc_settime(val); + } else if (!strcmp(argv[1], "i2c") && argc == 3) { int val = atoi(argv[2]); - struct st_lis331dl_dev_s * lis = st_lis331dl_init(vsn_sif.i2c1, val); + + I2C_SETFREQUENCY(vsn_sif.i2c2, 100000); + + struct st_lis331dl_dev_s * lis = st_lis331dl_init(vsn_sif.i2c2, val); if (lis) { struct st_lis331dl_vector_s * a; int i; + uint32_t time_stamp = clock_systimer(); + + /* Set to 400 Hz : 3 = 133 Hz/axis */ + + st_lis331dl_setconversion(lis, false, true); /* Sample some values */ - for (i=0; i<200000; i++) { + for (i=0; i<1000; ) { if ( (a = st_lis331dl_getreadings(lis)) ) { + i++; printf("%d %d %d\n", a->x, a->y, a->z); } else if (errno != 11) { printf("Readings errno %d\n", errno); break; } - fflush(stdout); - usleep(10000); } + printf("Time diff = %d\n", clock_systimer() - time_stamp); + st_lis331dl_deinit(lis); } else printf("Exit point: errno=%d\n", errno); @@ -533,6 +551,7 @@ int sif_main(int argc, char *argv[]) } fprintf(stderr, "%s:\tinit\n\tgpio\tA B\n\tpwr\tval\n", argv[0]); - fprintf(stderr, "test = %.8x, test irq = %.8x\n", test, test_irq); + fprintf(stderr, "time = %d / %d, time = %d\n", + up_rtc_gettime(), up_rtc_getclock(), time(NULL) ); return -1; } diff --git a/nuttx/include/nuttx/clock.h b/nuttx/include/nuttx/clock.h index e06d2c0dd..4d641696f 100644 --- a/nuttx/include/nuttx/clock.h +++ b/nuttx/include/nuttx/clock.h @@ -49,19 +49,6 @@ * Pro-processor Definitions ****************************************************************************/ /* Configuration ************************************************************/ -/* Access to raw system clock ***********************************************/ -/* The system timer/counter is supported only if (1) the system clock is not - * disabled and (2) we are not configured to use a hardware periodic timer - * for system time. - */ - -#undef __HAVE_SYSTEM_COUNTER -#if !defined(CONFIG_DISABLE_CLOCK) && !defined(CONFIG_PTIMER) -# define __HAVE_SYSTEM_COUNTER 1 -#else -# define __HAVE_SYSTEM_COUNTER 0 -#endif - /* Efficient, direct access to OS global timer variables will be supported * if the execution environment has direct access to kernel global data. * The code in this execution context can access the kernel global data @@ -157,10 +144,6 @@ extern volatile uint32_t g_uptime; * Global Function Prototypes ****************************************************************************/ -/**************************************************************************** - * Global Function Prototypes - ****************************************************************************/ - #ifdef __cplusplus #define EXTERN extern "C" extern "C" { @@ -168,15 +151,46 @@ extern "C" { #define EXTERN extern #endif -/* Indirect access to the system time is required if (1) we are using a - * hardware periodic timer, OR (2) the execution environment does not have - * direct access to kernel global data - */ +/**************************************************************************** + * Function: clock_systimer + * + * Description: + * Return the current value of the system timer counter. Indirect access + * to the system timer counter is required through this function if (1) we + * are using a hardware periodic timer, OR (2) the execution environment + * does not have direct access to kernel global data + * + * Parameters: + * None + * + * Return Value: + * The current value of the system timer counter + * + * Assumptions: + * + ****************************************************************************/ #if defined(CONFIG_PTIMER) || !__HAVE_KERNEL_GLOBALS EXTERN uint32_t clock_systimer(void); #endif +/**************************************************************************** + * Function: clock_uptime + * + * Description: + * Return the current value of the system timer counter, which is only + * enabled when system is in active mode. + * + * Parameters: + * None + * + * Return Value: + * The current value of the system time counter + * + * Assumptions: + * + ****************************************************************************/ + #if defined(CONFIG_UPTIME) && !__HAVE_KERNEL_GLOBALS EXTERN time_t clock_uptime(void); #endif diff --git a/nuttx/include/nuttx/ptimer.h b/nuttx/include/nuttx/ptimer.h index b5b5d65ae..19d493bf7 100755 --- a/nuttx/include/nuttx/ptimer.h +++ b/nuttx/include/nuttx/ptimer.h @@ -1,123 +1,122 @@ -/****************************************************************************
- * include/nuttx/ptimer.h
- *
- * Copyright(C) 2011 Uros Platise. All rights reserved.
- * Author: Uros Platise <uros.platise@isotel.eu>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-#ifndef __INCLUDE_NUTTX_PTIMER_H
-#define __INCLUDE_NUTTX_PTIMER_H
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include <nuttx/config.h>
-
-#include <sys/types.h>
-
-#include <time.h>
-#include <stdint.h>
-#include <stdbool.h>
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/* Configuration ************************************************************/
-
-/* Access macros ************************************************************/
-
-/* Clock manipulation macros ************************************************/
-
-/****************************************************************************
- * Public Types
- ****************************************************************************/
-
-/* The type of the periodic timer callback function */
-
-typedef void (*ptimer_handler_t)(FAR void *arg);
-
-/* The periodic timer vtable */
-
-struct ptimer_dev_s;
-struct ptimer_ops_s
-{
- int (*trigger)(FAR struct ptimer_dev_s *dev, FAR void *arg);
- int (*add)(FAR struct ptimer_dev_s *dev, FAR void *arg, clock_t period);
- int (*set)(FAR struct ptimer_dev_s *dev, FAR void *arg, clock_t period);
- int (*clear)(FAR struct ptimer_dev_s *dev, FAR void *arg);
- clock_t (*remainder)(FAR struct ptimer_dev_s *dev, FAR void *arg);
- clock_t (*overrun)(FAR struct ptimer_dev_s *dev, FAR void *arg);
- int (*exec)(FAR struct ptimer_dev_s *dev, clock_t timeout);
-};
-
-/* PTIMER private data. This structure only defines the initial fields of the
- * structure visible to the SPI client. The specific implementation may
- * add additional, device specific fields
- */
-
-struct ptimer_dev_s
-{
- FAR const struct ptimer_ops_s *ops;
-};
-
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
-
-#undef EXTERN
-#if defined(__cplusplus)
-#define EXTERN extern "C"
-extern "C" {
-#else
-#define EXTERN extern
-#endif
-
-/****************************************************************************
- * Name: up_ptimerinitialize
- *
- * Description:
- * Initialize the periodic timer interface. This function may be called to
- * obtian multiple instances of the interface
- *
- * Returned Value:
- * Valid peridic timer device structre reference on succcess; a NULL on failure
- *
- ****************************************************************************/
-
-EXTERN FAR struct ptimer_dev_s *up_ptimerinitialize(void);
-
-#undef EXTERN
-#if defined(__cplusplus)
-}
-#endif
-#endif /* __INCLUDE_NUTTX_PTIMER_H */
+/**************************************************************************** + * include/nuttx/ptimer.h + * + * Copyright(C) 2011 Uros Platise. All rights reserved. + * Author: Uros Platise <uros.platise@isotel.eu> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __INCLUDE_NUTTX_PTIMER_H +#define __INCLUDE_NUTTX_PTIMER_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include <time.h> +#include <stdint.h> +#include <stdbool.h> + +#include <nuttx/clock.h> + +#ifdef CONFIG_PTIMER + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define RTC_CLOCKS_PER_SEC 16384 +#define RTC_CLOCKS_SHIFT 14 + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Variables + ****************************************************************************/ + +/* Variable determines the state of the RTC module. + * + * After initialization value is set to 'true' if RTC starts successfully. + * The value can be changed to false also during operation if RTC for + * some reason fails. + */ + +extern volatile bool g_rtc_enabled; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" { +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Name: up_rtcinitialize + * + * Description: + * Initialize the periodic timer interface. This function is called once + * from the clock_initialize() function. + * + * Returned Value: + * Returns OK if RTC has successfully started, otherwise ERROR. + * + ****************************************************************************/ + +EXTERN int up_rtcinitialize(void); +EXTERN int up_rtcinitialize(void); + +EXTERN clock_t up_rtc_getclock(void); +EXTERN void up_rtc_setclock(clock_t clock); + +EXTERN time_t up_rtc_gettime(void); +EXTERN void up_rtc_settime(time_t time); + +EXTERN clock_t up_rtc_setalarm(clock_t atclock); + +/* This callback is provided by the clock module and called by the RTC ISR */ + +EXTERN void clock_rtcalarmcb(clock_t clock); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* CONFIG_PTIMER */ +#endif /* __INCLUDE_NUTTX_PTIMER_H */ diff --git a/nuttx/sched/clock_initialize.c b/nuttx/sched/clock_initialize.c index e18b819fa..0079e9f57 100644 --- a/nuttx/sched/clock_initialize.c +++ b/nuttx/sched/clock_initialize.c @@ -1,7 +1,7 @@ /**************************************************************************** * sched/clock_initialize.c * - * Copyright (C) 2007, 2009 Gregory Nutt. All rights reserved. + * Copyright (C) 2007, 2009, 2011 Gregory Nutt. All rights reserved. * Author: Gregory Nutt <spudmonkey@racsa.co.cr> * * Redistribution and use in source and binary forms, with or without @@ -53,15 +53,15 @@ * Definitions ****************************************************************************/ +/* Standard time definitions (in units of seconds) */ + #define SEC_PER_MIN ((time_t)60) #define SEC_PER_HOUR ((time_t)60 * SEC_PER_MIN) #define SEC_PER_DAY ((time_t)24 * SEC_PER_HOUR) -#if __HAVE_SYSTEM_COUNTER -# define incr_systimer() g_system_timer++ -#else -# define incr_systimer() -#endif +/* Defined just so the uptime counter and system timer look similar */ + +#define incr_systimer() g_system_timer++ /**************************************************************************** * Private Type Declarations @@ -79,9 +79,7 @@ * Public Variables ****************************************************************************/ -#if __HAVE_SYSTEM_COUNTER volatile clock_t g_system_timer = 0; -#endif #if CONFIG_UPTIME volatile time_t g_uptime = 0; @@ -155,23 +153,39 @@ static inline void incr_uptime(void) void clock_initialize(void) { time_t jdn; +#ifdef CONFIG_PTIMER + bool rtc_enabled = false; +#endif - /* Initialize the real time close */ + /* Initialize the real time close (this should be un-nesssary except on a + * restart). + */ -#if __HAVE_SYSTEM_COUNTER g_system_timer = 0; +#ifdef CONFIG_UPTIME + g_uptime = 0; +#endif + + /* Do we have hardware periodic timer support? */ + +#ifdef CONFIG_RTC + if (up_rtcinitialize() == OK) + { + rtc_enabled = true; + } #endif /* Get the EPOCH-relative julian date from the calendar year, * month, and date */ -#ifndef CONFIG_PTIMER - jdn = clock_calendar2utc(CONFIG_START_YEAR, CONFIG_START_MONTH, - CONFIG_START_DAY); -#else /* use UTC as starting date */ - jdn = clock_calendar2utc(1970, 1, 1); +#ifdef CONFIG_PTIMER + if (!rtc_enabled) #endif + { + jdn = clock_calendar2utc(CONFIG_START_YEAR, CONFIG_START_MONTH, + CONFIG_START_DAY); + } /* Set the base time as seconds into this julian day. */ diff --git a/nuttx/sched/clock_systimer.c b/nuttx/sched/clock_systimer.c index 5e18f53fd..fde303be6 100644 --- a/nuttx/sched/clock_systimer.c +++ b/nuttx/sched/clock_systimer.c @@ -40,9 +40,12 @@ #include <nuttx/config.h> #include <stdint.h> + #include <nuttx/clock.h> +#include <nuttx/ptimer.h> +#include <nuttx/time.h> -#if __HAVE_SYSTEM_COUNTER && !defined(clock_systimer) /* See nuttx/clock.h */ +#if !defined(clock_systimer) /* See nuttx/clock.h */ /**************************************************************************** * Pre-processor Definitions @@ -74,8 +77,24 @@ uint32_t clock_systimer(void) { + /* Fetch the g_system_timer value from timer hardware, if available */ + +#ifdef CONFIG_PTIMER + + /* Check if the periodic timer is initialized + * + * Note that the unit of the g_system_timer and and up_rtc_getclock() must + * be the same in order. + */ + + if (g_rtc_enabled) + { + up_rtc_getclock(); + } +#endif + return g_system_timer; } -#endif /* __HAVE_SYSTEM_COUNTER */ +#endif /* !clock_systtimer */ diff --git a/nuttx/sched/clock_uptime.c b/nuttx/sched/clock_uptime.c index ae580ed17..cea3262c8 100644 --- a/nuttx/sched/clock_uptime.c +++ b/nuttx/sched/clock_uptime.c @@ -43,14 +43,12 @@ #include <nuttx/clock.h> #include <nuttx/time.h> -#if !defined(CONFIG_DISABLE_CLOCK) && defined(CONFIG_UPTIME) +#if !defined(CONFIG_DISABLE_CLOCK) && defined(CONFIG_UPTIME) && !defined(clock_uptime) /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -#undef clock_uptime - /**************************************************************************** * Private Data ****************************************************************************/ @@ -78,7 +76,16 @@ time_t clock_uptime(void) { - return g_uptime; +#ifdef CONFIG_PTIMER + if (g_rtc_enabled) + { + return up_rtc_gettime(); + } + else +#endif + { + return g_uptime; + } } #endif /* CONFIG_DISABLE_CLOCK && CONFIG_UPTIME */ |