ARMv7-A: Add cp15_disable_dcache(); SAMA5: nor_main.c no disables MMU and caches; Should not remap ISRAM to address 0x0 unless we booted into ISRAM

3 files changed, 70 insertions, 17 deletions

diff --git a/nuttx/arch/arm/src/armv7-a/cache.h b/nuttx/arch/arm/src/armv7-a/cache.h
index 50e9be2c1..19d385944 100644
--- a/nuttx/arch/arm/src/armv7-a/cache.h
+++ b/nuttx/arch/arm/src/armv7-a/cache.h
@@ -194,6 +194,26 @@
 #ifdef __ASSEMBLY__
 
 /************************************************************************************
+ * Name: cp15_disable_dcache
+ *
+ * Description:
+ *   Disable L1 D Cache
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   None
+ *
+ ************************************************************************************/
+
+	.macro	cp15_disable_dcache, tmp
+	mrc		p15, 0, \tmp, c1, c0, 0		/* Read SCTLR */
+	bic		\tmp, \tmp, #(0x1 << 2)		/* Disable D cache */
+	mcr		p15, 0, \tmp, c1, c0, 0		/* Updagte the SCTLR */
+	.endm
+
+/************************************************************************************
  * Name: cp15_disable_caches
  *
  * Description:
@@ -207,7 +227,7 @@
  *
  ************************************************************************************/
 
-	.macro	cp15_invalidate_icache_inner_sharable, tmp
+	.macro	cp15_disable_caches, tmp
 	mrc		p15, 0, \tmp, c1, c0, 0		/* Read SCTLR */
 	bic		\tmp, \tmp, #(0x1 << 12)	/* Disable I cache */
 	bic		\tmp, \tmp, #(0x1 << 2)		/* Disable D cache */
@@ -462,6 +482,33 @@
 #ifndef __ASSEMBLY__
 
 /************************************************************************************
+ * Name: cp15_disable_dcache
+ *
+ * Description:
+ *   Disable L1 Caches
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   None
+ *
+ ************************************************************************************/
+
+static inline void cp15_disable_dcache(void)
+{
+  __asm__ __volatile__
+    (
+      "\tmrc  p15, 0, r0, c1, c0, 0\n"  /* Read SCTLR */
+      "\tbic  r0, r0, #(1 << 2)\n"      /* Disable D cache */
+      "\tmcr  p15, 0, r0, c1, c0, 0\n"  /* Updagte the SCTLR */
+      :
+      :
+      : "r0", "memory"
+    );
+}
+
+/************************************************************************************
  * Name: cp15_disable_caches
  *
  * Description:
@@ -480,8 +527,8 @@ static inline void cp15_disable_caches(void)
   __asm__ __volatile__
     (
       "\tmrc  p15, 0, r0, c1, c0, 0\n"  /* Read SCTLR */
-      "\tbic  r0, r0, #(0x1 << 12)\n"   /* Disable I cache */
-      "\tbic  r0, r0, #(0x1 << 2)\n"    /* Disable D cache */
+      "\tbic  r0, r0, #(1 << 12)\n"     /* Disable I cache */
+      "\tbic  r0, r0, #(1 << 2)\n"      /* Disable D cache */
       "\tmcr  p15, 0, r0, c1, c0, 0\n"  /* Updagte the SCTLR */
       :
       :
diff --git a/nuttx/arch/arm/src/sama5/sam_irq.c b/nuttx/arch/arm/src/sama5/sam_irq.c
index a72eb8c85..d78bee61a 100644
--- a/nuttx/arch/arm/src/sama5/sam_irq.c
+++ b/nuttx/arch/arm/src/sama5/sam_irq.c
@@ -283,11 +283,14 @@ void up_irqinitialize(void)
 
   putreg32(AIC_WPMR_WPKEY | AIC_WPMR_WPEN, SAM_AIC_WPMR);
 
-#ifdef CONFIG_ARCH_LOWVECTORS
-  /* Set remap state 0.  This is done late in the boot sequence.  Any
-   * exceptions taken before this point in time will be handled by the
-   * ROM code, not by the NuttX interrupt since which was, up to this
-   * point, uninitialized.
+#if defined(CONFIG_ARCH_LOWVECTORS) && defined(CONFIG_SAMA5_BOOT_ISRAM)
+  /* Set remap state 0 if we are running from internal SRAM.  If we booted
+   * into NOR FLASH, then the first level bootloader should have already
+   * provided this mapping for us.
+   *
+   * This is done late in the boot sequence.  Any exceptions taken before
+   * this point in time will be handled by the ROM code, not by the NuttX
+   * interrupt since which was, up to this point, uninitialized.
    *
    *   Boot state:    ROM is seen at address 0x00000000
    *   Remap State 0: SRAM is seen at address 0x00000000 (through AHB slave
diff --git a/nuttx/configs/sama5d3x-ek/src/nor_main.c b/nuttx/configs/sama5d3x-ek/src/nor_main.c
index d4062e4ed..af6322511 100644
--- a/nuttx/configs/sama5d3x-ek/src/nor_main.c
+++ b/nuttx/configs/sama5d3x-ek/src/nor_main.c
@@ -92,7 +92,7 @@ int nor_main(int argc, char *argv)
    * are executing from NOR FLASH now).
    */
 
-  printf("Configuring NOR flash on CS0\n");
+  printf("Configuring NOR flash on CS0 and halting\n");
   sam_hsmc_enableclk();
 
   /* The SAMA5D3x-EK has 118MB of 16-bit NOR FLASH at CS0.  The NOR FLASH
@@ -139,14 +139,18 @@ int nor_main(int argc, char *argv)
    */
 
   putreg32(MATRIX_MRCR_RCB0, SAM_MATRIX_MRCR);   /* Enable remap */
-  putreg32(AXIMX_REMAP_REMAP1, SAM_AXIMX_REMAP); /* Remap SRAM */
+  putreg32(AXIMX_REMAP_REMAP1, SAM_AXIMX_REMAP); /* Remap HEBI */
 
   /* Disable the caches and the MMU.  Disabling the MMU should be safe here
    * because there is a 1-to-1 identity mapping between the physical and
    * virtual addressing.
    */
 
-#if 0 /* Causes crashes */
+  /* NOTE:  This generates crashes and lots of error, but does leave the
+   * system in the proper state to run from NOR:  very ugly but usable.
+   * Better than the alternative.
+   */
+
   cp15_disable_mmu();
   cp15_disable_caches();
 
@@ -155,21 +159,20 @@ int nor_main(int argc, char *argv)
   cp15_invalidate_icache();
   cp15_invalidate_dcache_all();
   cp15_invalidate_tlbs();
-#endif
 
 #ifdef SAMA5_NOR_START
   /* Then jump into NOR flash */
 
-  printf("Jumping to NOR flash on CS0\n");
-  fflush(stdout);
-  usleep(500*1000);
+//  printf("Jumping to NOR flash on CS0\n");
+//  fflush(stdout);
+//  usleep(500*1000);
 
   NOR_ENTRY();
 #else
   /* Or just wait patiently for the user to break in with GDB. */
 
-  printf("Waiting for GDB halt\n");
-  fflush(stdout);
+//  printf("Waiting for GDB halt\n");
+//  fflush(stdout);
   for (;;);
 #endif