Fix LPC43xx clocking bugs; LPC43xx now runs at 204MHz

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4946 42af7a65-404d-4744-a932-0658087f49c3

7 files changed, 294 insertions, 43 deletions

diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog
index d920bc7f2..f95f9d81a 100644
--- a/nuttx/ChangeLog
+++ b/nuttx/ChangeLog
@@ -2996,3 +2996,16 @@
 	* fs/: More stylistic file clean-up.
 	* mm/: More stylistic file clean-up.
 	* drivers/ and drivers/serial/: More stylistic file clean-up.
+	* arch/arm/src/lpc43xx/lpc43_clockconfig.c:  Fix PLL1 bit manipulation logic.
+	  Critical bugfix! This would often cause the LPC43xx to fail to boot.
+	* arch/arm/src/lpc43xx/lpc43_rgu.c:  The soft reset logic called from the
+	  beginning of __start seems cause problems.  A magic delay seems to improve
+	  the logic some.  But I suspect that real fix is to get rid of all of the
+	  soft reset logic.  This would also be a critical bugfix if I believed
+	  that it really fixed all of the issues.
+	* arch/arm/src/lpc43xx/chip/lpc43_cgu.h:  Fix a bit mask in the PLL1
+	  control register.  Critical bugfix.
+	* arch/arm/src/lpc43xx/lpc43_clockconfig.c and configs/lpc4330-xplorer/include/board.h:
+	  Implement PLL1 ramp-up logic; Now the LPC43xx is running at 204MHz.
+	* configs/lpc4330-xplorer/*/defconfig:  Re-calibrated delay loops using
+	  the 204MHz clock.  The LPC43xx ripping rips!
diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_cgu.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_cgu.h
index 911bc6764..a71954153 100644
--- a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_cgu.h
+++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_cgu.h
@@ -309,8 +309,8 @@
 #  define PLL1_CTRL_NSEL_DIV3           (2 << PLL1_CTRL_NSEL_SHIFT)
 #  define PLL1_CTRL_NSEL_DIV4           (3 << PLL1_CTRL_NSEL_SHIFT)
                                                   /* Bits 14-15: Reserved */
-#define PLL1_CTRL_MSEL_SHIFT            (16)      /* Bits 16-17: Feedback-divider division ratio M */
-#define PLL1_CTRL_MSEL_MASK             (3 << PLL1_CTRL_MSEL_SHIFT)
+#define PLL1_CTRL_MSEL_SHIFT            (16)      /* Bits 16-23: Feedback-divider division ratio M */
+#define PLL1_CTRL_MSEL_MASK             (0xff << PLL1_CTRL_MSEL_SHIFT)
 #  define PLL1_CTRL_MSEL(n)             (((n)-1) << PLL1_CTRL_MSEL_SHIFT) /* n=1..256 */
 #define PLL1_CTRL_CLKSEL_SHIFT          (24)      /* Bits 24-28: Clock source selection */
 #define PLL1_CTRL_CLKSEL_MASK           (31 << PLL1_CTRL_CLKSEL_SHIFT)
diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_cgu.c b/nuttx/arch/arm/src/lpc43xx/lpc43_cgu.c
index 8e266e039..61c4112ae 100644
--- a/nuttx/arch/arm/src/lpc43xx/lpc43_cgu.c
+++ b/nuttx/arch/arm/src/lpc43xx/lpc43_cgu.c
@@ -54,7 +54,8 @@
 #define LOW_XTAL_FREQUENCY     15000000
 #define MAX_XTAL_FREQUENCY     25000000
 
-#define MAX_FCLKOUT_FREQUENCY 156000000
+#define MAX_FCLKOUT_FREQUENCY 204000000
+#define MAX_FCLKOUT_DIRECT    156000000
 #define MAX_FCCO_FRQUENCY     320000000
 
 /* Configuration ************************************************************/
@@ -74,7 +75,7 @@
 #  error "BOARD_XTAL_FREQUENCY exceeds the maximum value"
 #endif
 
-#if !defined(BOARD_PLL1_DIRECT) && (BOARD_FCLKOUT_FREQUENCY > MAX_FCLKOUT_FREQUENCY)
+#if BOARD_FCLKOUT_FREQUENCY > MAX_FCLKOUT_FREQUENCY
 #  error "BOARD_FCLKOUT_FREQUENCY exceed the maximum"
 #endif
 
@@ -84,16 +85,136 @@
 
 /* Convert the user-friendly definitions in board.h to register bit settings */
 
-#if BOARD_PLL_PSEL == 1
-#  define CTRL_PSEL_VALUE PLL1_CTRL_PSEL_DIV1
-#elif BOARD_PLL_PSEL == 2
-#  define CTRL_PSEL_VALUE PLL1_CTRL_PSEL_DIV2
-#elif BOARD_PLL_PSEL == 4
-#  define CTRL_PSEL_VALUE PLL1_CTRL_PSEL_DIV4
-#elif BOARD_PLL_PSEL == 8
-#  define CTRL_PSEL_VALUE PLL1_CTRL_PSEL_DIV8
+/* Check if we are using a RAMP */
+
+#undef PLL_RAMP
+
+#ifdef BOARD_PLL_RAMP_MSEL
+
+#  define PLL_RAMP 1
+
+   /* Get initial PLL values */
+
+#  define INIT_MSEL_VALUE PLL1_CTRL_MSEL(1)
+#  define INIT_NSEL_VALUE PLL1_CTRL_NSEL_DIV1
+
+   /* Pick the initial PSEL value (integer mode) */
+
+#  ifndef BOARD_XTAL_FREQUENCY
+#    error "BOARD_XTAL_FREQUENCY is not defined in board.h"
+#  endif
+
+#  if BOARD_XTAL_FREQUENCY >= MAX_FCLKOUT_DIRECT
+#    error "BOARD_XTAL_FREQUENCY value is not supported"
+#  endif
+
+#  if (2 * BOARD_XTAL_FREQUENCY) > MAX_FCCO_FRQUENCY
+#    error "Impossible value for BOARD_XTAL_FREQUENCY"
+#  elif (2 * 2 * BOARD_XTAL_FREQUENCY) > MAX_FCCO_FRQUENCY
+#    define INIT_PSEL_VALUE PLL1_CTRL_PSEL_DIV1
+#  elif (2 * 4 * BOARD_XTAL_FREQUENCY) > MAX_FCCO_FRQUENCY
+#    define INIT_PSEL_VALUE PLL1_CTRL_PSEL_DIV2
+#  elif (2 * 8 * BOARD_XTAL_FREQUENCY) > MAX_FCCO_FRQUENCY
+#    define INIT_PSEL_VALUE PLL1_CTRL_PSEL_DIV4
+#  else
+#    define INIT_PSEL_VALUE PLL1_CTRL_PSEL_DIV8
+#  endif
+
+   /* Select initial integer mode controls */
+
+#  define INIT_PLL_CONTROLS \
+   (PLL1_CTRL_FBSEL | INIT_PSEL_VALUE  | INIT_NSEL_VALUE | INIT_MSEL_VALUE)
+
+   /* Select a value close to a 10 millisecond delay */
+
+#  define XTAL_DELAY \
+   (10 * BOARD_XTAL_FREQUENCY + (LPC43_CCLK - 1)) / LPC43_CCLK
+
+   /* Check the ramp-up MSEL value */
+
+#  if (BOARD_PLL_RAMP_MSEL > 0) && (BOARD_PLL_RAMP_MSEL < 256)
+#    define RAMP_MSEL_VALUE PLL1_CTRL_MSEL(BOARD_PLL_RAMP_MSEL)
+#  else
+#    error "Unsupported value of BOARD_PLL_RAMP_NSEL"
+#  endif
+
+   /* Check the ramp-up NSEL value */
+
+#  ifndef BOARD_PLL_RAMP_NSEL
+#    error "BOARD_PLL_RAMP_NSEL is not defined in board.h"
+#  endif
+
+#  if BOARD_PLL_RAMP_NSEL == 1
+#   define RAMP_NSEL_VALUE PLL1_CTRL_NSEL_DIV1
+#  elif BOARD_PLL_RAMP_NSEL == 2
+#    define RAMP_NSEL_VALUE PLL1_CTRL_NSEL_DIV2
+#  elif BOARD_PLL_RAMP_NSEL == 3
+#    define RAMP_NSEL_VALUE PLL1_CTRL_NSEL_DIV3
+#  elif BOARD_PLL_RAMP_NSEL == 4
+#    define RAMP_NSEL_VALUE PLL1_CTRL_NSEL_DIV4
+#  else
+#    error "Unsupported value of BOARD_PLL_RAMP_NSEL"
+#  endif
+
+   /* Check for direct mode */
+
+#  ifndef BOARD_RAMP_FCLKOUT
+#    error "BOARD_RAMP_FCLKOUT is not defined in board.h"
+#  endif
+
+#  if BOARD_RAMP_FCLKOUT >= MAX_FCLKOUT_DIRECT
+
+     /* Select direct mode controls */
+
+#    define RAMP_PLL_CONTROLS \
+    (PLL1_CTRL_FBSEL | PLL1_CTRL_DIRECT  | RAMP_NSEL_VALUE | RAMP_MSEL_VALUE)
+
+#  else
+
+   /* Check the ramp-up PSEL value */
+
+#    ifndef BOARD_PLL_RAMP_PSEL
+#     error "BOARD_PLL_RAMP_PSEL is not defined in board.h"
+#    endif
+
+#    if BOARD_PLL_RAMP_PSEL == 1
+#      define RAMP_PSEL_VALUE PLL1_CTRL_PSEL_DIV1
+#    elif BOARD_PLL_RAMP_PSEL == 2
+#      define RAMP_PSEL_VALUE PLL1_CTRL_PSEL_DIV2
+#    elif BOARD_PLL_RAMP_PSEL == 4
+#      define RAMP_PSEL_VALUE PLL1_CTRL_PSEL_DIV4
+#    elif BOARD_PLL_RAMP_PSEL == 8
+#      define RAMP_PSEL_VALUE PLL1_CTRL_PSEL_DIV8
+#    else
+#      error "Unsupported value of BOARD_PLL_RAMP_PSEL"
+#    endif
+#  endif
+
+     /* Select integer mode controls */
+
+#    define RAMP_PLL_CONTROLS \
+     (PLL1_CTRL_FBSEL | RAMP_PSEL_VALUE  | RAMP_NSEL_VALUE | RAMP_MSEL_VALUE)
+
+   /* Select a value close to a 10 millisecond delay */
+
+#endif
+
+   /* Check the Final MSEL value */
+
+#ifndef BOARD_PLL_MSEL
+#  error "BOARD_PLL_MSEL is not defined in board.h"
+#endif
+
+#if (BOARD_PLL_MSEL > 0) && (BOARD_PLL_MSEL < 256)
+#  define CTRL_MSEL_VALUE PLL1_CTRL_MSEL(BOARD_PLL_MSEL)
 #else
-#  error "Unsupported value of BOARD_PLL_PSEL"
+#  error "Unsupported value of BOARD_PLL_MSEL"
+#endif
+
+   /* Check the Final NSEL value */
+
+#ifndef BOARD_PLL_NSEL
+#  error "BOARD_PLL_NSEL is not defined in board.h"
 #endif
 
 #if BOARD_PLL_NSEL == 1
@@ -108,10 +229,44 @@
 #  error "Unsupported value of BOARD_PLL_NSEL"
 #endif
 
-#if (BOARD_PLL_MSEL > 0) && (BOARD_PLL_MSEL < 256)
-#  define CTRL_MSEL_VALUE PLL1_CTRL_MSEL(BOARD_PLL_MSEL)
-#else
-#  error "Unsupported value of BOARD_PLL_NSEL"
+   /* Check for direct mode */
+
+#ifndef BOARD_FCLKOUT_FREQUENCY
+#  error "BOARD_FCLKOUT_FREQUENCY is not defined in board.h"
+#endif
+
+#if BOARD_FCLKOUT_FREQUENCY >= MAX_FCLKOUT_DIRECT
+
+     /* Select direct mode controls */
+
+#    define PLL_CONTROLS \
+     (PLL1_CTRL_FBSEL | PLL1_CTRL_DIRECT | CTRL_NSEL_VALUE | CTRL_MSEL_VALUE)
+
+#  else
+
+   /* Check the Final PSEL value */
+
+#  ifndef BOARD_PLL_PSEL
+#    error "BOARD_PLL_PSEL is not defined in board.h"
+#  endif
+
+#  if BOARD_PLL_PSEL == 1
+#    define CTRL_PSEL_VALUE PLL1_CTRL_PSEL_DIV1
+#  elif BOARD_PLL_PSEL == 2
+#    define CTRL_PSEL_VALUE PLL1_CTRL_PSEL_DIV2
+#  elif BOARD_PLL_PSEL == 4
+#    define CTRL_PSEL_VALUE PLL1_CTRL_PSEL_DIV4
+#  elif BOARD_PLL_PSEL == 8
+#    define CTRL_PSEL_VALUE PLL1_CTRL_PSEL_DIV8
+#  else
+#    error "Unsupported value of BOARD_PLL_PSEL"
+#  endif
+
+     /* Select integer mode controls */
+
+#    define PLL_CONTROLS \
+     (PLL1_CTRL_FBSEL | CTRL_PSEL_VALUE  | CTRL_NSEL_VALUE | CTRL_MSEL_VALUE)
+
 #endif
 
 /****************************************************************************
@@ -162,7 +317,7 @@ static inline void lpc43_xtalconfig(void)
 
   /* Select the crystal oscillator as the input to PLL1 */
 
-  regval = getreg32(LPC43_PLL1_CTRL);
+  regval  = getreg32(LPC43_PLL1_CTRL);
   regval &= ~PLL1_CTRL_CLKSEL_MASK;
   regval |= PLL1_CLKSEL_XTAL | PLL1_CTRL_AUTOBLOCK;
   putreg32(regval, LPC43_PLL1_CTRL);
@@ -177,7 +332,7 @@ static inline void lpc43_xtalconfig(void)
  *
  ****************************************************************************/
 
-static inline void lpc43_pll1config(void)
+static inline void lpc43_pll1config(uint32_t ctrlvalue)
 {
   uint32_t regval;
 
@@ -195,7 +350,6 @@ static inline void lpc43_pll1config(void)
   regval &= ~(PLL1_CTRL_BYPASS    | PLL1_CTRL_FBSEL     | PLL1_CTRL_DIRECT |
               PLL1_CTRL_PSEL_MASK | PLL1_CTRL_NSEL_MASK |
               PLL1_CTRL_MSEL_MASK);
-  putreg32(regval, LPC43_PLL1_CTRL);
   
   /* Set selected PLL1 controls:
    *
@@ -206,13 +360,7 @@ static inline void lpc43_pll1config(void)
    *   - PLL1_CTRL_MSEL:      Set to the value from board.h
    */
 
-#ifdef BOARD_PLL1_DIRECT
-  regval |= (PLL1_CTRL_FBSEL | PLL1_CTRL_DIRECT | CTRL_PSEL_VALUE |
-             CTRL_NSEL_VALUE | CTRL_MSEL_VALUE);
-#else
-  regval |= (PLL1_CTRL_FBSEL | CTRL_PSEL_VALUE  | CTRL_NSEL_VALUE |
-             CTRL_MSEL_VALUE);
-#endif
+  regval    |= ctrlvalue;
   putreg32(regval, LPC43_PLL1_CTRL);
 }
 
@@ -255,13 +403,13 @@ static inline void lpc43_pll1enable(void)
  *
  ****************************************************************************/
 
-static inline void lpc43_m4clkselect(void)
+static inline void lpc43_m4clkselect(uint32_t clksel)
 {
   uint32_t regval;
 
   regval = getreg32(LPC43_BASE_M4_CLK);
   regval &= ~BASE_M4_CLK_CLKSEL_MASK;
-  regval |= BASE_M4_CLKSEL_PLL1;
+  regval |= clksel;
   putreg32(regval, LPC43_BASE_M4_CLK);
 }
 
@@ -285,15 +433,50 @@ void lpc43_clockconfig(void)
 
   lpc43_xtalconfig();
 
+#ifndef PLL_RAMP
   /* Configure PLL1 */
 
-  lpc43_pll1config();
+  lpc43_pll1config(PLL_CONTROLS);
 
   /* Enable PLL1 */
 
   lpc43_pll1enable();
+ 
+  /* Set up PLL1 output as the M4 clock */
+
+  lpc43_m4clkselect(BASE_M4_CLKSEL_PLL1);
+#else
+
+  /* Drive the M4 clock from the XTAL until the PLL is configured */
+
+  lpc43_m4clkselect(BASE_M4_CLKSEL_XTAL);
+
+  /* Select the initial PLL1 configured (BOARD_XTAL_FREQUENCY x 1) */
+
+  lpc43_pll1config(INIT_PLL_CONTROLS);
+
+  /* Enable PLL1 */
+
+  lpc43_pll1enable();
+
+  /* Delay around 10 milliseconds */
+
+  up_mdelay(XTAL_DELAY);
+
+  /* Configure the intermediate, ramp-up configuration for PLL1 */
+
+  lpc43_pll1config(RAMP_PLL_CONTROLS);
 
   /* Set up PLL1 output as the M4 clock */
 
-  lpc43_m4clkselect();
+  lpc43_m4clkselect(BASE_M4_CLKSEL_PLL1);
+
+  /* Delay around 10 milliseconds */
+
+  up_mdelay(XTAL_DELAY);
+
+  /* Go to the final, full-speed PLL1 configuration */
+
+  lpc43_pll1config(PLL_CONTROLS);  
+#endif
 }
diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_rgu.c b/nuttx/arch/arm/src/lpc43xx/lpc43_rgu.c
index 544afe187..d5ab819dc 100644
--- a/nuttx/arch/arm/src/lpc43xx/lpc43_rgu.c
+++ b/nuttx/arch/arm/src/lpc43xx/lpc43_rgu.c
@@ -41,6 +41,7 @@
 #include <nuttx/config.h>
 
 #include <arch/irq.h>
+#include <nuttx/arch.h>
 
 #include "nvic.h"
 #include "up_arch.h"
@@ -112,6 +113,10 @@ void lpc43_softreset(void)
             RGU_CTRL1_CAN0_RST    | RGU_CTRL1_M0APP_RST),
             LPC43_RGU_CTRL1);
 
+  /* A delay seems to be necessary somewhere around here */
+
+  up_mdelay(20);
+
   /* Clear all pending interupts */
 
   putreg32(0xffffffff, NVIC_IRQ0_31_CLRPEND);
diff --git a/nuttx/configs/lpc4330-xplorer/include/board.h b/nuttx/configs/lpc4330-xplorer/include/board.h
index 94de34832..6901b8d16 100644
--- a/nuttx/configs/lpc4330-xplorer/include/board.h
+++ b/nuttx/configs/lpc4330-xplorer/include/board.h
@@ -69,10 +69,6 @@
 #define BOARD_RTCCLK_FREQUENCY      (32768)     /* RTC oscillator frequency (Y1) */
 #define BOARD_INTRCOSC_FREQUENCY    (4000000)   /* Internal RC oscillator frequency */
 
-/* TODO:  The LPC43xx is capable of running at much higher frequencies, but requires
- * a ramp-up in several stages.
- */
-
 /* Integer and direct modes are supported:
  *
  * In integer mode (Fclkout < 156000000):
@@ -85,12 +81,66 @@
  *    Fcco    = Fclkout
  */
 
-#undef  BOARD_PLL1_DIRECT                       /* Integer mode */
-#define BOARD_PLL_MSEL              (6)         /* Msel = 6 */
-#define BOARD_PLL_NSEL              (1)         /* Nsel = 1 */
-#define BOARD_PLL_PSEL              (2)         /* Psel = 2 */
-#define BOARD_FCLKOUT_FREQUENCY     (72000000)  /* 6 * 12,000,000 / 1 */
-#define BOARD_FCCO_FREQUENCY        (244000000) /* 2 * 2 * 72,000,000 */
+#ifdef CONFIG_LPC43_72MHz
+
+/* NOTE:  At 72MHz, the calibrated value of CONFIG_BOARD_LOOPSPERMSEC was
+ * determined to be:
+ *
+ *    CONFIG_BOARD_LOOPSPERMSEC=7191
+ *
+ * executing from SRAM.
+ */
+
+/* Final clocking (Integer mode with no ramp-up)
+ *
+ *    Fclkout = 6 * 12MHz / 1  = 72MHz
+ *    Fcco    = 2 * 2 * 72MHz = 216MHz
+ */
+
+#  define BOARD_PLL_MSEL            (6)         /* Msel = 6 */
+#  define BOARD_PLL_NSEL            (1)         /* Nsel = 1 */
+#  define BOARD_PLL_PSEL            (2)         /* Psel = 2 */
+
+#  define BOARD_FCLKOUT_FREQUENCY   (72000000)  /* 6 * 12,000,000 / 1 */
+#  define BOARD_FCCO_FREQUENCY      (244000000) /* 2 * 2 * Fclkout */
+ 
+#else
+
+/* NOTE:  At 72MHz, the calibrated value of CONFIG_BOARD_LOOPSPERMSEC was
+ * determined to be:
+ *
+ *    CONFIG_BOARD_LOOPSPERMSEC=18535
+ *
+ * executing from SRAM.
+ */
+
+/* Intermediate ramp-up clocking (Integer mode). If BOARD_PLL_RAMP_MSEL
+ * is not defined, there will be no ramp-up.  
+ *
+ *    Fclkout = 9 * 12MHz / 1  = 108MHz
+ *    Fcco    = 2 * 1 * 108MHz = 216MHz
+ */
+
+#  define BOARD_PLL_RAMP_MSEL       (9)         /* Msel = 9 */
+#  define BOARD_PLL_RAMP_NSEL       (1)         /* Nsel = 1 */
+#  define BOARD_PLL_RAMP_PSEL       (1)         /* Psel = 1 */
+
+#  define BOARD_RAMP_FCLKOUT        (108000000) /* 9 * 12,000,000 / 1 */
+#  define BOARD_RAMP_FCCO           (216000000) /* 2 * 1 * Fclkout */
+
+/* Final clocking (Direct mode). 
+ *
+ *    Fclkout = 17 * 12MHz / 1 = 204MHz
+ *    Fcco    = Fclockout      = 204MHz
+ */
+
+#  define BOARD_PLL_MSEL            (17)        /* Msel = 17 */
+#  define BOARD_PLL_NSEL            (1)         /* Nsel = 1 */
+
+#  define BOARD_FCLKOUT_FREQUENCY   (204000000) /* 17 * 12,000,000 / 1 */
+#  define BOARD_FCCO_FREQUENCY      (204000000) /* Fclockout */
+
+#endif
 
 /* This is the clock setup we configure for:
  *
diff --git a/nuttx/configs/lpc4330-xplorer/nsh/defconfig b/nuttx/configs/lpc4330-xplorer/nsh/defconfig
index edd7406c5..8ab5e33ac 100644
--- a/nuttx/configs/lpc4330-xplorer/nsh/defconfig
+++ b/nuttx/configs/lpc4330-xplorer/nsh/defconfig
@@ -81,7 +81,7 @@ CONFIG_ARCH_CHIP=lpc43xx
 CONFIG_ARCH_CHIP_LPC4330FET100=y
 CONFIG_ARCH_BOARD=lpc4330-xplorer
 CONFIG_ARCH_BOARD_LPC4330_XPLORER=y
-CONFIG_BOARD_LOOPSPERMSEC=7191
+CONFIG_BOARD_LOOPSPERMSEC=18535
 CONFIG_DRAM_SIZE=(72*1024)
 CONFIG_DRAM_START=0x10080000
 CONFIG_DRAM_END=(CONFIG_DRAM_START+CONFIG_DRAM_SIZE)
diff --git a/nuttx/configs/lpc4330-xplorer/ostest/defconfig b/nuttx/configs/lpc4330-xplorer/ostest/defconfig
index 1dca0cc37..c20897b76 100644
--- a/nuttx/configs/lpc4330-xplorer/ostest/defconfig
+++ b/nuttx/configs/lpc4330-xplorer/ostest/defconfig
@@ -81,7 +81,7 @@ CONFIG_ARCH_CHIP=lpc43xx
 CONFIG_ARCH_CHIP_LPC4330FET100=y
 CONFIG_ARCH_BOARD=lpc4330-xplorer
 CONFIG_ARCH_BOARD_LPC4330_XPLORER=y
-CONFIG_BOARD_LOOPSPERMSEC=7191
+CONFIG_BOARD_LOOPSPERMSEC=18535
 CONFIG_DRAM_SIZE=(72*1024)
 CONFIG_DRAM_START=0x10080000
 CONFIG_DRAM_END=(CONFIG_DRAM_START+CONFIG_DRAM_SIZE)