Back port some A10 changes into the SAMA5 memory map definitions

3 files changed, 106 insertions, 65 deletions

diff --git a/nuttx/arch/arm/src/a1x/chip/a10_memorymap.h b/nuttx/arch/arm/src/a1x/chip/a10_memorymap.h
index 4676bc10f..e411b11d7 100644
--- a/nuttx/arch/arm/src/a1x/chip/a10_memorymap.h
+++ b/nuttx/arch/arm/src/a1x/chip/a10_memorymap.h
@@ -540,7 +540,8 @@
 
 #  define VECTOR_L2_END_PADDR     (VECTOR_L2_PBASE+VECTOR_L2_SIZE)
 #  define VECTOR_L2_END_VADDR     (VECTOR_L2_VBASE+VECTOR_L2_SIZE)
-#endif
+
+#endif /* !CONFIG_ARCH_LOWVECTORS */
 
 /* Paging L2 page table offset/size */
 
@@ -572,11 +573,15 @@
  */
 
 #define VECTOR_TABLE_SIZE         0x00010000
+
 #ifdef CONFIG_ARCH_LOWVECTORS  /* Vectors located at 0x0000:0000  */
+
 #  define A1X_VECTOR_PADDR        A1X_SRAMA1_PADDR
 #  define A1X_VECTOR_VSRAM        A1X_SRAMA1_VADDR
 #  define A1X_VECTOR_VADDR        0x00000000
+
 #else  /* Vectors located at 0xffff:0000 -- this probably does not work */
+
 #  ifdef A1X_ISRAM1_SIZE >= VECTOR_TABLE_SIZE
 #    define A1X_VECTOR_PADDR      (A1X_SRAMA1_PADDR+A1X_ISRAM1_SIZE-VECTOR_TABLE_SIZE)
 #    define A1X_VECTOR_VSRAM      (A1X_SRAMA1_VADDR+A1X_ISRAM1_SIZE-VECTOR_TABLE_SIZE)
@@ -585,6 +590,7 @@
 #    define A1X_VECTOR_VSRAM      (A1X_SRAMA1_VADDR+A1X_ISRAM0_SIZE-VECTOR_TABLE_SIZE)
 #  endif
 #  define A1X_VECTOR_VADDR        0xffff0000
+
 #endif
 
 /************************************************************************************
diff --git a/nuttx/arch/arm/src/sama5/chip/sama5d3x_memorymap.h b/nuttx/arch/arm/src/sama5/chip/sama5d3x_memorymap.h
index a7c05d282..6b7f57254 100644
--- a/nuttx/arch/arm/src/sama5/chip/sama5d3x_memorymap.h
+++ b/nuttx/arch/arm/src/sama5/chip/sama5d3x_memorymap.h
@@ -460,86 +460,88 @@
  * And, if so, then its size must agree with the configured size.
  */
 
-#if defined(CONFIG_SAMA5_EBICS0) && defined(CONFIG_SAMA5_EBICS0_NOR) && \
-    defined (CONFIG_SAMA5_BOOT_CS0FLASH)
+#  if defined(CONFIG_SAMA5_EBICS0) && defined(CONFIG_SAMA5_EBICS0_NOR) && \
+      defined (CONFIG_SAMA5_BOOT_CS0FLASH)
 
-#  if CONFIG_SAMA5_EBICS0_SIZE != CONFIG_FLASH_SIZE
-#    error CS0 FLASH size disagreement
-#  endif
+#    if CONFIG_SAMA5_EBICS0_SIZE != CONFIG_FLASH_SIZE
+#      error CS0 FLASH size disagreement
+#    endif
 
-#  undef CONFIG_SAMA5_BOOT_CS1FLASH
-#  undef CONFIG_SAMA5_BOOT_CS2FLASH
-#  undef CONFIG_SAMA5_BOOT_CS3FLASH
+#    undef CONFIG_SAMA5_BOOT_CS1FLASH
+#    undef CONFIG_SAMA5_BOOT_CS2FLASH
+#    undef CONFIG_SAMA5_BOOT_CS3FLASH
 
-#elif defined(CONFIG_SAMA5_EBICS1) && defined(CONFIG_SAMA5_EBICS1_NOR) && \
-      defined (CONFIG_SAMA5_BOOT_CS1FLASH)
+#  elif defined(CONFIG_SAMA5_EBICS1) && defined(CONFIG_SAMA5_EBICS1_NOR) && \
+        defined (CONFIG_SAMA5_BOOT_CS1FLASH)
 
-#  if CONFIG_SAMA5_EBICS1_SIZE != CONFIG_FLASH_SIZE
-#    error CS1 FLASH size disagreement
-#  endif
+#    if CONFIG_SAMA5_EBICS1_SIZE != CONFIG_FLASH_SIZE
+#      error CS1 FLASH size disagreement
+#    endif
 
-#  undef CONFIG_SAMA5_BOOT_CS0FLASH
-#  undef CONFIG_SAMA5_BOOT_CS2FLASH
-#  undef CONFIG_SAMA5_BOOT_CS3FLASH
+#    undef CONFIG_SAMA5_BOOT_CS0FLASH
+#    undef CONFIG_SAMA5_BOOT_CS2FLASH
+#    undef CONFIG_SAMA5_BOOT_CS3FLASH
 
-#elif defined(CONFIG_SAMA5_EBICS2) && defined(CONFIG_SAMA5_EBICS2_NOR) && \
-      defined (CONFIG_SAMA5_BOOT_CS2FLASH)
+#  elif defined(CONFIG_SAMA5_EBICS2) && defined(CONFIG_SAMA5_EBICS2_NOR) && \
+        defined (CONFIG_SAMA5_BOOT_CS2FLASH)
 
-#  if CONFIG_SAMA2_EBICS0_SIZE != CONFIG_FLASH_SIZE
-#    error CS2 FLASH size disagreement
-#  endif
+#    if CONFIG_SAMA2_EBICS0_SIZE != CONFIG_FLASH_SIZE
+#      error CS2 FLASH size disagreement
+#    endif
 
-#  undef CONFIG_SAMA5_BOOT_CS0FLASH
-#  undef CONFIG_SAMA5_BOOT_CS1FLASH
-#  undef CONFIG_SAMA5_BOOT_CS3FLASH
+#    undef CONFIG_SAMA5_BOOT_CS0FLASH
+#    undef CONFIG_SAMA5_BOOT_CS1FLASH
+#    undef CONFIG_SAMA5_BOOT_CS3FLASH
 
-#elif defined(CONFIG_SAMA5_EBICS3) && defined(CONFIG_SAMA5_EBICS3_NOR) && \
-      defined (CONFIG_SAMA5_BOOT_CS3FLASH)
+#  elif defined(CONFIG_SAMA5_EBICS3) && defined(CONFIG_SAMA5_EBICS3_NOR) && \
+        defined (CONFIG_SAMA5_BOOT_CS3FLASH)
 
-#  if CONFIG_SAMA5_EBICS3_SIZE != CONFIG_FLASH_SIZE
-#    error CS3 FLASH size disagreement
-#  endif
+#    if CONFIG_SAMA5_EBICS3_SIZE != CONFIG_FLASH_SIZE
+#      error CS3 FLASH size disagreement
+#    endif
 
-#  undef CONFIG_SAMA5_BOOT_CS0FLASH
-#  undef CONFIG_SAMA5_BOOT_CS1FLASH
-#  undef CONFIG_SAMA5_BOOT_CS2FLASH
+#    undef CONFIG_SAMA5_BOOT_CS0FLASH
+#    undef CONFIG_SAMA5_BOOT_CS1FLASH
+#    undef CONFIG_SAMA5_BOOT_CS2FLASH
 
-#else
-#  error CONFIG_BOOT_RUNFROMFLASH=y, but no bootable NOR flash defined
+#  else
+#    error CONFIG_BOOT_RUNFROMFLASH=y, but no bootable NOR flash defined
 
-#  undef CONFIG_SAMA5_BOOT_CS0FLASH
-#  undef CONFIG_SAMA5_BOOT_CS1FLASH
-#  undef CONFIG_SAMA5_BOOT_CS2FLASH
-#  undef CONFIG_SAMA5_BOOT_CS3FLASH
+#    undef CONFIG_SAMA5_BOOT_CS0FLASH
+#    undef CONFIG_SAMA5_BOOT_CS1FLASH
+#    undef CONFIG_SAMA5_BOOT_CS2FLASH
+#    undef CONFIG_SAMA5_BOOT_CS3FLASH
 
-#endif
+#  endif
 
-/* Set up the NOR FLASH region as the NUTTX .text region */
+  /* Set up the NOR FLASH region as the NUTTX .text region */
 
 #  define NUTTX_TEXT_VADDR       (CONFIG_FLASH_VSTART & 0xfff00000)
 #  define NUTTX_TEXT_PADDR       (CONFIG_FLASH_START & 0xfff00000)
 #  define NUTTX_TEXT_PEND        ((CONFIG_FLASH_END + 0x000fffff) & 0xfff00000)
 #  define NUTTX_TEXT_SIZE        (NUTTX_TEXT_PEND - NUTTX_TEXT_PADDR)
 
-/* In the default configuration, the primary RAM use for .bss and .data
- * is the internal SRAM.
- */
+  /* In the default configuration, the primary RAM use for .bss and .data
+   * is the internal SRAM.
+   */
 
 #  define NUTTX_RAM_VADDR        (CONFIG_RAM_VSTART & 0xfff00000)
 #  define NUTTX_RAM_PADDR        (CONFIG_RAM_START & 0xfff00000)
 #  define NUTTX_RAM_PEND         ((CONFIG_RAM_END + 0x000fffff) & 0xfff00000)
 #  define NUTTX_RAM_SIZE         (NUTTX_RAM_PEND - NUTTX_RAM_PADDR)
 
-#else
-/* Otherwise we are running from some kind of RAM (ISRAM or SDRAM).
- * Setup the RAM region as the NUTTX .txt, .bss, and .data region.
- */
+#else /* CONFIG_BOOT_RUNFROMFLASH */
+
+  /* Otherwise we are running from some kind of RAM (ISRAM or SDRAM).
+   * Setup the RAM region as the NUTTX .txt, .bss, and .data region.
+   */
 
 #  define NUTTX_TEXT_VADDR       (CONFIG_RAM_VSTART & 0xfff00000)
 #  define NUTTX_TEXT_PADDR       (CONFIG_RAM_START & 0xfff00000)
 #  define NUTTX_TEXT_PEND        ((CONFIG_RAM_END + 0x000fffff) & 0xfff00000)
 #  define NUTTX_TEXT_SIZE        (NUTTX_TEXT_PEND - NUTTX_TEXT_PADDR)
-#endif
+
+#endif /* CONFIG_BOOT_RUNFROMFLASH */
 
 /* MMU Page Table Location
  *
@@ -561,6 +563,7 @@
 
 #undef PGTABLE_IN_HIGHSRAM
 #undef PGTABLE_IN_LOWSRAM
+#undef ARMV7A_PGTABLE_MAPPING
 
 #if !defined(PGTABLE_BASE_PADDR) || !defined(PGTABLE_BASE_VADDR)
 
@@ -591,7 +594,7 @@
    * in the way at that position.
    */
 
-#if defined(CONFIG_BOOT_RUNFROMISRAM) && defined(CONFIG_ARCH_LOWVECTORS)
+#  if defined(CONFIG_BOOT_RUNFROMISRAM) && defined(CONFIG_ARCH_LOWVECTORS)
 
   /* In this case, table must lie at the top 16Kb of ISRAM1 (or ISRAM0 if ISRAM1
    * is not available in this architecture)
@@ -601,18 +604,19 @@
    */
 
 #    if SAM_ISRAM1_SIZE > 0
-#        define PGTABLE_BASE_PADDR (SAM_ISRAM1_PADDR+SAM_ISRAM1_SIZE-PGTABLE_SIZE)
-#        ifndef CONFIG_PAGING
-#          define PGTABLE_BASE_VADDR (SAM_ISRAM1_VADDR+SAM_ISRAM1_SIZE-PGTABLE_SIZE)
-#        endif
+#      define PGTABLE_BASE_PADDR (SAM_ISRAM1_PADDR+SAM_ISRAM1_SIZE-PGTABLE_SIZE)
+#      ifndef CONFIG_PAGING
+#        define PGTABLE_BASE_VADDR (SAM_ISRAM1_VADDR+SAM_ISRAM1_SIZE-PGTABLE_SIZE)
+#      endif
 #    else
-#        define PGTABLE_BASE_PADDR (SAM_ISRAM0_PADDR+SAM_ISRAM0_SIZE-PGTABLE_SIZE)
-#        ifndef CONFIG_PAGING
-#          define PGTABLE_BASE_VADDR (SAM_ISRAM0_VADDR+SAM_ISRAM0_SIZE-PGTABLE_SIZE)
-#        endif
+#      define PGTABLE_BASE_PADDR (SAM_ISRAM0_PADDR+SAM_ISRAM0_SIZE-PGTABLE_SIZE)
+#      ifndef CONFIG_PAGING
+#        define PGTABLE_BASE_VADDR (SAM_ISRAM0_VADDR+SAM_ISRAM0_SIZE-PGTABLE_SIZE)
+#      endif
 #    endif
 #    define PGTABLE_IN_HIGHSRAM   1
-#  else
+
+#  else /* CONFIG_BOOT_RUNFROMISRAM && CONFIG_ARCH_LOWVECTORS */
 
   /* Otherwise, the vectors lie at another location (perhaps in NOR FLASH, perhaps
    * elsewhere in internal SRAM).  The page table will then be positioned at
@@ -624,8 +628,19 @@
 #      define PGTABLE_BASE_VADDR  SAM_ISRAM0_VADDR
 #    endif
 #    define PGTABLE_IN_LOWSRAM    1
+
+#  endif /* CONFIG_BOOT_RUNFROMISRAM && CONFIG_ARCH_LOWVECTORS */
+
+  /* In either case, the page table lies in ISRAM.  If ISRAM is not the
+   * primary RAM region, then we will need to set-up a special mapping for
+   * the page table at boot time.
+   */
+
+#  if NUTTX_RAM_PADDR != SAM_ISRAM_PSECTION
+#    define ARMV7A_PGTABLE_MAPPING 1
 #  endif
-#endif
+
+#endif /* !PGTABLE_BASE_PADDR || !PGTABLE_BASE_VADDR */
 
 /* Level 2 Page table start addresses.
  *
@@ -658,28 +673,28 @@
  */
 
 #ifndef CONFIG_ARCH_LOWVECTORS
-/* Vector L2 page table offset/size */
+  /* Vector L2 page table offset/size */
 
 #  define VECTOR_L2_OFFSET        0x000002000
 #  define VECTOR_L2_SIZE          0x000000400
 
-/* Vector L2 page table base addresses */
+  /* Vector L2 page table base addresses */
 
 #  define VECTOR_L2_PBASE         (PGTABLE_BASE_PADDR+VECTOR_L2_OFFSET)
 #  define VECTOR_L2_VBASE         (PGTABLE_BASE_VADDR+VECTOR_L2_OFFSET)
 
-/* Vector L2 page table end addresses */
+  /* Vector L2 page table end addresses */
 
 #  define VECTOR_L2_END_PADDR     (VECTOR_L2_PBASE+VECTOR_L2_SIZE)
 #  define VECTOR_L2_END_VADDR     (VECTOR_L2_VBASE+VECTOR_L2_SIZE)
 
-/* Paging L2 page table offset/size */
+  /* Paging L2 page table offset/size */
 
 #  define PGTABLE_L2_OFFSET       0x000002400
 #  define PGTABLE_L2_SIZE         0x000001800
 
 #else
-/* Paging L2 page table offset/size */
+  /* Paging L2 page table offset/size */
 
 #  define PGTABLE_L2_OFFSET       0x000002000
 #  define PGTABLE_L2_SIZE         0x000001c00
@@ -707,11 +722,15 @@
  */
 
 #define VECTOR_TABLE_SIZE         0x00010000
+
 #ifdef CONFIG_ARCH_LOWVECTORS  /* Vectors located at 0x0000:0000  */
+
 #  define SAM_VECTOR_PADDR        SAM_ISRAM0_PADDR
 #  define SAM_VECTOR_VSRAM        SAM_ISRAM0_VADDR
 #  define SAM_VECTOR_VADDR        0x00000000
+
 #else  /* Vectors located at 0xffff:0000 -- this probably does not work */
+
 #  ifdef SAM_ISRAM1_SIZE >= VECTOR_TABLE_SIZE
 #    define SAM_VECTOR_PADDR      (SAM_ISRAM1_PADDR+SAM_ISRAM1_SIZE-VECTOR_TABLE_SIZE)
 #    define SAM_VECTOR_VSRAM      (SAM_ISRAM1_VADDR+SAM_ISRAM1_SIZE-VECTOR_TABLE_SIZE)
@@ -720,6 +739,7 @@
 #    define SAM_VECTOR_VSRAM      (SAM_ISRAM0_VADDR+SAM_ISRAM0_SIZE-VECTOR_TABLE_SIZE)
 #  endif
 #  define SAM_VECTOR_VADDR        0xffff0000
+
 #endif
 
 /************************************************************************************
diff --git a/nuttx/configs/pcduino-a10/README.txt b/nuttx/configs/pcduino-a10/README.txt
index 59a0f64c8..5c074fc27 100644
--- a/nuttx/configs/pcduino-a10/README.txt
+++ b/nuttx/configs/pcduino-a10/README.txt
@@ -101,6 +101,7 @@ Contents
   - Serial Console
   - LEDs
   - Buttons
+  - Booting NuttX from an SD card
 
 pcDuino v1 Connectors
 =====================
@@ -249,3 +250,17 @@ Buttons
     SW4 Key_Home  LCD1_D18/ATAD14/KP_OUT0/SMC_SLK/EINT18/CSI1_D18/PH18
     SW5 Key_Menu  LCD1_D19/ATAD15/KP_OUT1/SMC_SDA/EINT19/CSI1_D19/PH19
 
+Booting NuttX from an SD card
+=============================
+
+  These are the steps to get U-Boot booting from SD Card:
+
+  $ git clone https://github.com/yuq/u-boot-sunxi.git
+  $ cd u-boot-sunxi
+  $ make pcduino CROSS_COMPILE=arm-linux-gnueabi-
+  $ sudo dd if=./spl/sunxi-spl.bin of=/dev/sdb bs=1024 seek=8
+  $ sudo dd if=u-boot.bin of=/dev/sdb bs=1024 seek=32
+
+  We need to replace u-boot.bin by nuttx.bin.
+
+  Reference: https://www.olimex.com/wiki/Bare_Metal_programming_A13#Stand_alone_program_running_with_uboot