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author | Gregory Nutt <gnutt@nuttx.org> | 2013-10-25 08:46:57 -0600 |
---|---|---|
committer | Gregory Nutt <gnutt@nuttx.org> | 2013-10-25 08:46:57 -0600 |
commit | be634bfa13e412258e8cce03ae5a6526f434439d (patch) | |
tree | 2cc5c3eaf8f8ef6c2a38b9155d5327d7b296dfe8 | |
parent | 3f772ef5b5ab5a26802355ecd024cb824d10bfab (diff) | |
download | nuttx-be634bfa13e412258e8cce03ae5a6526f434439d.tar.gz nuttx-be634bfa13e412258e8cce03ae5a6526f434439d.tar.bz2 nuttx-be634bfa13e412258e8cce03ae5a6526f434439d.zip |
SAMA5 ADC+TC: Several updates/fixes from ongoing debug
-rw-r--r-- | nuttx/arch/arm/src/sama5/Kconfig | 8 | ||||
-rw-r--r-- | nuttx/arch/arm/src/sama5/chip/sam_adc.h | 4 | ||||
-rw-r--r-- | nuttx/arch/arm/src/sama5/sam_adc.c | 20 | ||||
-rw-r--r-- | nuttx/arch/arm/src/sama5/sam_dmac.c | 4 | ||||
-rw-r--r-- | nuttx/arch/arm/src/sama5/sam_tc.c | 43 |
5 files changed, 44 insertions, 35 deletions
diff --git a/nuttx/arch/arm/src/sama5/Kconfig b/nuttx/arch/arm/src/sama5/Kconfig index fb7d0378d..a3d9d316b 100644 --- a/nuttx/arch/arm/src/sama5/Kconfig +++ b/nuttx/arch/arm/src/sama5/Kconfig @@ -2257,6 +2257,14 @@ config SAMA5_TC1_TIOB5 endif # SAMA5_TC1 +config SAMA5_TC_REGDEBUG + bool "TC Register level debug" + depends on DEBUG + default n + ---help--- + Output detailed register-level Timer/Counter device debug information. + Very invasive! Requires also DEBUG. + endmenu # Timer/counter Configuration endif # SAMA5_TC0 || SAMA5_TC1 diff --git a/nuttx/arch/arm/src/sama5/chip/sam_adc.h b/nuttx/arch/arm/src/sama5/chip/sam_adc.h index 93720a698..a14cda5c6 100644 --- a/nuttx/arch/arm/src/sama5/chip/sam_adc.h +++ b/nuttx/arch/arm/src/sama5/chip/sam_adc.h @@ -203,7 +203,7 @@ /* Channel Sequence Register 1 */ -#define ADC_SEQR1_USCH_SHIFT(n) (((n)-1) << 4) /* n=1..8 */ +#define ADC_SEQR1_USCH_SHIFT(n) (((n)-1) << 2) /* n=1..8 */ #define ADC_SEQR1_USCH_MASK(n) (15 << ADC_SEQR1_USCH_SHIFT(n)) # define ADC_SEQR1_USCH(n,v) ((uint32_t)(v) << ADC_SEQR1_USCH_SHIFT(n)) #define ADC_SEQR1_USCH1_SHIFT (0) /* Bits 0-3: User sequence number 1 */ @@ -233,7 +233,7 @@ /* Channel Sequence Register 2 */ -#define ADC_SEQR2_USCH_SHIFT(n) (((n)-9) << 4) /* n=9..11 */ +#define ADC_SEQR2_USCH_SHIFT(n) (((n)-9) << 2) /* n=9..11 */ #define ADC_SEQR2_USCH_MASK(n) (15 << ADC_SEQR2_USCH_SHIFT(n)) # define ADC_SEQR2_USCH(n,v) ((uint32_t)(v) << ADC_SEQR2_USCH_SHIFT(n)) #define ADC_SEQR2_USCH9_SHIFT (0) /* Bits 0-3: User sequence number 9 */ diff --git a/nuttx/arch/arm/src/sama5/sam_adc.c b/nuttx/arch/arm/src/sama5/sam_adc.c index dc458362b..cd7ca45fe 100644 --- a/nuttx/arch/arm/src/sama5/sam_adc.c +++ b/nuttx/arch/arm/src/sama5/sam_adc.c @@ -671,7 +671,7 @@ static void sam_adc_dmacallback(DMA_HANDLE handle, void *arg, int result) sam_adc_dmasetup(priv->dma, priv->odd ? (void *)priv->oddbuf : (void *)priv->evenbuf, - SAMA5_NCHANNELS); + SAMA5_NCHANNELS * sizeof(uint32_t)); } #endif @@ -995,7 +995,7 @@ static int sam_adc_setup(struct adc_dev_s *dev) priv->ready = true; priv->enabled = false; - sam_adc_dmasetup(priv->dma, (void *)priv->evenbuf, SAMA5_NCHANNELS); + sam_adc_dmasetup(priv, (void *)priv->evenbuf, SAMA5_NCHANNELS); #else /* Enable end-of-conversion interrupts for all enabled channels. */ @@ -1566,8 +1566,6 @@ static void sam_adc_analogchange(struct sam_adc_s *priv) #ifdef CONFIG_SAMA5_ADC_SEQUENCER static void sam_adc_setseqr(int chan, uint32_t *seqr1, uint32_t *seqr2, int seq) { - avdbg("seqr1=%p seqr2=%p seg=%d\n"); - if (seq > 8) { *seqr2 |= ADC_SEQR2_USCH(seq, chan); @@ -1576,6 +1574,8 @@ static void sam_adc_setseqr(int chan, uint32_t *seqr1, uint32_t *seqr2, int seq) { *seqr1 |= ADC_SEQR1_USCH(seq, chan); } + + avdbg("chan=%d seqr1=%08x seqr2=%08x seq=%d\n", chan, *seqr1, *seqr2, seq); } #endif @@ -1591,9 +1591,9 @@ static void sam_adc_sequencer(struct sam_adc_s *priv) /* Set user configured channel sequence */ - seqr1 = 0; - seqr2 = 0; - seq = 0; + seqr1 = 0; + seqr2 = 0; + seq = 1; #ifdef CONFIG_SAMA5_ADC_CHAN0 sam_adc_setseqr(0, &seqr1, &seqr2, seq++); @@ -1701,12 +1701,6 @@ static void sam_adc_channels(struct sam_adc_s *priv) avdbg("Entry\n"); - /* Disable the sequencer */ - - regval = sam_adc_getreg(priv, SAM_ADC_MR); - regval &= ~ADC_MR_USEQ; - sam_adc_putreg(priv, SAM_ADC_MR, regval); - /* Enable channels. */ regval = 0; diff --git a/nuttx/arch/arm/src/sama5/sam_dmac.c b/nuttx/arch/arm/src/sama5/sam_dmac.c index 1bbdc2ee0..ff8a13735 100644 --- a/nuttx/arch/arm/src/sama5/sam_dmac.c +++ b/nuttx/arch/arm/src/sama5/sam_dmac.c @@ -2154,7 +2154,7 @@ int sam_dmatxsetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, remaining -= maxtransfer; /* Increment the memory & peripheral address (if it is appropriate to - * do do). + * do so). */ if ((dmach->flags & DMACH_FLAG_PERIPHINCREMENT) != 0) @@ -2233,7 +2233,7 @@ int sam_dmarxsetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, remaining -= maxtransfer; /* Increment the memory & peripheral address (if it is appropriate to - * do do). + * do so). */ if ((dmach->flags & DMACH_FLAG_PERIPHINCREMENT) != 0) diff --git a/nuttx/arch/arm/src/sama5/sam_tc.c b/nuttx/arch/arm/src/sama5/sam_tc.c index 46b728c72..8844a0358 100644 --- a/nuttx/arch/arm/src/sama5/sam_tc.c +++ b/nuttx/arch/arm/src/sama5/sam_tc.c @@ -93,8 +93,13 @@ /* Timer debug is enabled if any timer client is enabled */ +#ifndef CONFIG_DEBUG +# undef CONFIG_DEBUG_ANALOG +# undef CONFIG_SAMA5_TC_REGDEBUG +#endif + #undef DEBUG_TC -#if defined(CONFIG_SAMA5_ADC) +#if defined(CONFIG_SAMA5_ADC) && defined(CONFIG_DEBUG_ANALOG) # define DEBUG_TC 1 #endif @@ -159,7 +164,7 @@ struct sam_tc_s /* Debug stuff */ -#ifdef CONFIG_SAMA5_HSMCI_REGDEBUG +#ifdef CONFIG_SAMA5_TC_REGDEBUG bool wrlast; /* Last was a write */ uint32_t addrlast; /* Last address */ uint32_t vallast; /* Last value */ @@ -176,22 +181,22 @@ struct sam_tc_s static void sam_takesem(struct sam_tc_s *tc); #define sam_givesem(tc) (sem_post(&tc->exclsem)) -#ifdef CONFIG_SAMA5_HSMCI_REGDEBUG -static bool sam_checkreg(struct sam_tc_s *tc, bool wr, - uint32_t value, uint32_t regaddr, uint32_t regval); +#ifdef CONFIG_SAMA5_TC_REGDEBUG +static bool sam_checkreg(struct sam_tc_s *tc, bool wr, uint32_t regaddr, + uint32_t regval); #else -# define sam_checkreg(tc,wr,value,regaddr) (false) +# define sam_checkreg(tc,wr,regaddr,regval) (false) #endif static inline uint32_t sam_tc_getreg(struct sam_chan_s *chan, unsigned int offset); static inline void sam_tc_putreg(struct sam_chan_s *chan, - unsigned int offset, uint32_t value); + unsigned int offset, uint32_t regval); static inline uint32_t sam_chan_getreg(struct sam_chan_s *chan, unsigned int offset); static inline void sam_chan_putreg(struct sam_chan_s *chan, - unsigned int offset, uint32_t value); + unsigned int offset, uint32_t regval); /* Initialization ***********************************************************/ @@ -425,8 +430,10 @@ static void sam_takesem(struct sam_tc_s *tc) * Check if the current register access is a duplicate of the preceding. * * Input Parameters: - * value - The value to be written - * regaddr - The address of the register to write to + * tc - The timer/counter peripheral state + * wr - True:write access false:read access + * regval - The regiser value associated with the access + * regaddr - The address of the register being accessed * * Returned Value: * true: This is the first register access of this type. @@ -434,12 +441,12 @@ static void sam_takesem(struct sam_tc_s *tc) * ****************************************************************************/ -#ifdef CONFIG_SAMA5_HSMCI_REGDEBUG +#ifdef CONFIG_SAMA5_TC_REGDEBUG static bool sam_checkreg(struct sam_tc_s *tc, bool wr, uint32_t regaddr, - uint32_t value) + uint32_t regval) { if (wr == tc->wrlast && /* Same kind of access? */ - value == tc->vallast && /* Same value? */ + regval == tc->vallast && /* Same value? */ regaddr == tc->addrlast) /* Same regaddr? */ { /* Yes, then just keep a count of the number of times we did this. */ @@ -461,7 +468,7 @@ static bool sam_checkreg(struct sam_tc_s *tc, bool wr, uint32_t regaddr, /* Save information about the new access */ tc->wrlast = wr; - tc->vallast = value; + tc->vallast = regval; tc->addrlast = regaddr; tc->ntimes = 0; } @@ -487,7 +494,7 @@ static inline uint32_t sam_tc_getreg(struct sam_chan_s *chan, uint32_t regaddr = tc->base + offset; uint32_t regval = getreg32(regaddr); -#ifdef CONFIG_SAMA5_HSMCI_REGDEBUG +#ifdef CONFIG_SAMA5_TC_REGDEBUG if (sam_checkreg(tc, false, regval, regaddr)) { lldbg("%08x->%08x\n", regaddr, regval); @@ -511,7 +518,7 @@ static inline void sam_tc_putreg(struct sam_chan_s *chan, uint32_t regval, struct sam_tc_s *tc = chan->tc; uint32_t regaddr = tc->base + offset; -#ifdef CONFIG_SAMA5_HSMCI_REGDEBUG +#ifdef CONFIG_SAMA5_TC_REGDEBUG if (sam_checkreg(tc, true, regval, regaddr)) { lldbg("%08x<-%08x\n", regaddr, regval); @@ -535,7 +542,7 @@ static inline uint32_t sam_chan_getreg(struct sam_chan_s *chan, uint32_t regaddr = chan->base + offset; uint32_t regval = getreg32(regaddr); -#ifdef CONFIG_SAMA5_HSMCI_REGDEBUG +#ifdef CONFIG_SAMA5_TC_REGDEBUG if (sam_checkreg(chan->tc, false, regval, regaddr)) { lldbg("%08x->%08x\n", regaddr, regval); @@ -558,7 +565,7 @@ static inline void sam_chan_putreg(struct sam_chan_s *chan, unsigned int offset, { uint32_t regaddr = chan->base + offset; -#ifdef CONFIG_SAMA5_HSMCI_REGDEBUG +#ifdef CONFIG_SAMA5_TC_REGDEBUG if (sam_checkreg(chan->tc, true, regval, regaddr)) { lldbg("%08x<-%08x\n", regaddr, regval); |