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| author | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2013-02-13 15:59:10 +0000 |
|---|---|---|
| committer | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2013-02-13 15:59:10 +0000 |
| commit | cc16ba43ea26fdd50fdf14e15e45c1c17833c7b6 (patch) | |
| tree | e81b1efff038d004b0864a336db2a11342a2eeaf | |
| parent | d32f956730f3e4ffa9e244163f9646d9f6049305 (diff) | |
| download | nuttx-cc16ba43ea26fdd50fdf14e15e45c1c17833c7b6.tar.gz nuttx-cc16ba43ea26fdd50fdf14e15e45c1c17833c7b6.tar.bz2 nuttx-cc16ba43ea26fdd50fdf14e15e45c1c17833c7b6.zip | |
A few more fixes for LPC1788 compilation (still more needed)
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5650 42af7a65-404d-4744-a932-0658087f49c3
| -rw-r--r-- | nuttx/arch/arm/src/lpc17xx/chip/lpc178x_syscon.h | 15 | ||||
| -rw-r--r-- | nuttx/configs/open1788/include/board.h | 8 |
2 files changed, 15 insertions, 8 deletions
diff --git a/nuttx/arch/arm/src/lpc17xx/chip/lpc178x_syscon.h b/nuttx/arch/arm/src/lpc17xx/chip/lpc178x_syscon.h index d930896ac..8c1b26f6d 100644 --- a/nuttx/arch/arm/src/lpc17xx/chip/lpc178x_syscon.h +++ b/nuttx/arch/arm/src/lpc17xx/chip/lpc178x_syscon.h @@ -249,9 +249,9 @@ /* PLL0/1 Configuration register */ #define SYSCON_PLLCFG_MSEL_SHIFT (0) /* Bit 0-4: PLL Multiplier value */ -#define SYSCON_PLLCFG_MSEL_MASK (0x1f << SYSCON_PLL0CFG_MSEL_SHIFT) +#define SYSCON_PLLCFG_MSEL_MASK (0x1f << SYSCON_PLLCFG_MSEL_SHIFT) #define SYSCON_PLLCFG_PSEL_SHIFT (5) /* Bit 5-6: PLL Pre-Divider value */ -#define SYSCON_PLLCFG_PSEL_MASK (3 << SYSCON_PLL0CFG_PSEL_SHIFT) +#define SYSCON_PLLCFG_PSEL_MASK (3 << SYSCON_PLLCFG_PSEL_SHIFT) /* PLL0/1 Status register */ @@ -573,7 +573,6 @@ #define SYSCON_EMCCAL_CALVALUE_SHIFT (0) /* Bits 0-7: Ring oscillator count during 32 clocks of Internal RC */ #define SYSCON_EMCCAL_CALVALUE_MASK (0xff << SYSCON_EMCCAL_CALVALUE_SHIFT) -//~ #define SYSCON_EMCCAL_CALVALUE /* Bits 8-13: Reserved */ #define SYSCON_EMCCAL_START_SHIFT (14) /* Bit 14: Start control bit for EMC calibration counter */ #define SYSCON_EMCCAL_START_MASK (1 << SYSCON_EMCCAL_START_SHIFT) @@ -581,8 +580,16 @@ #define SYSCON_EMCCAL_DONE_SHIFT (15) /* Bit 15: Measurement completetion flag bit */ #define SYSCON_EMCCAL_DONE_MASK (1 << SYSCON_EMCCAL_DONE_SHIFT) /* Automatically cleared when START bit is set */ -//~ # define SYSCON_EMCCAL_DONE /* Bits 16-31: Reserved */ + +/* Compatibility Definitions ************************************************************************/ +/* Need in lpc17_clockconfig.h for compatibility with the LPC176x family: */ + +#define SYSCON_PLLCON_PLLC (0) /* Bit does not exist in LPC178x family */ +#define SYSCON_PLL0STAT_PLLE SYSCON_PLLSTAT_PLLE /* PLL enable readback */ +#define SYSCON_PLL0STAT_PLLC SYSCON_PLLSTAT_PLLC /* PLL connect readback */ +#define SYSCON_PLL0STAT_PLOCK SYSCON_PLLSTAT_PLOCK /* PLL lock status */ + /**************************************************************************************************** * Public Types ****************************************************************************************************/ diff --git a/nuttx/configs/open1788/include/board.h b/nuttx/configs/open1788/include/board.h index 13d75870a..258735e34 100644 --- a/nuttx/configs/open1788/include/board.h +++ b/nuttx/configs/open1788/include/board.h @@ -84,7 +84,7 @@ */ #define BOARD_CCLKCFG_DIVIDER 6 -#define BOARD_CCLKCFG_VALUE ((BOARD_CCLKCFG_DIVIDER-1) << SYSCON_CCLKCFG_SHIFT) +#define BOARD_CCLKCFG_VALUE ((BOARD_CCLKCFG_DIVIDER-1) << SYSCON_CCLKCFG_CCLKDIV_SHIFT) /* PLL0. PLL0 is used to generate the CPU clock divider input (PLLCLK). * @@ -100,10 +100,10 @@ #define BOARD_CLKSRCSEL_VALUE SYSCON_CLKSRCSEL_MAIN #define BOARD_PLL0CFG_MSEL 20 -#define BOARD_PLL0CFG_NSEL 1 +#define BOARD_PLL0CFG_PSEL 1 #define BOARD_PLL0CFG_VALUE \ - (((BOARD_PLL0CFG_MSEL-1) << SYSCON_PLL0CFG_MSEL_SHIFT) | \ - ((BOARD_PLL0CFG_NSEL-1) << SYSCON_PLL0CFG_NSEL_SHIFT)) + (((BOARD_PLL0CFG_MSEL-1) << SYSCON_PLLCFG_MSEL_SHIFT) | \ + ((BOARD_PLL0CFG_PSEL-1) << SYSCON_PLLCFG_PSEL_SHIFT)) /* PLL1 -- Not used. */ |