Add Kinetis GPIO definitions

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3852 42af7a65-404d-4744-a932-0658087f49c3

5 files changed, 680 insertions, 78 deletions

diff --git a/nuttx/arch/arm/include/kinetis/irq.h b/nuttx/arch/arm/include/kinetis/irq.h
index a8b5c2221..ae4ca682f 100644
--- a/nuttx/arch/arm/include/kinetis/irq.h
+++ b/nuttx/arch/arm/include/kinetis/irq.h
@@ -286,7 +286,7 @@
 #  define KINETIS_IRQ_PORTB       (104) /* Vector 104: Pin detect port B */
 #  define KINETIS_IRQ_PORTC       (105) /* Vector 105: Pin detect port C */
 #  define KINETIS_IRQ_PORTD       (106) /* Vector 106: Pin detect port D */
-#  define KINETIS_IRQ_PORTD       (107) /* Vector 107: Pin detect port E */
+#  define KINETIS_IRQ_PORTE       (107) /* Vector 107: Pin detect port E */
                                         /* Vectors 108-119: Reserved */
 
 /* Note that the total number of IRQ numbers supported is equal to the number of
diff --git a/nuttx/arch/arm/src/kinetis/kinetis_internal.h b/nuttx/arch/arm/src/kinetis/kinetis_internal.h
index a23a3c89a..3691dccde 100755
--- a/nuttx/arch/arm/src/kinetis/kinetis_internal.h
+++ b/nuttx/arch/arm/src/kinetis/kinetis_internal.h
@@ -49,6 +49,7 @@
 
 #include "up_internal.h"
 #include "chip.h"
+#include "kinetis_port.h"
 
 /************************************************************************************
  * Definitions
@@ -56,8 +57,178 @@
 
 /* Configuration ********************************************************************/
 
-/* Bit-encoded input to kinetis_configgpio() ******************************************/
-#warning "Missing logic"
+/* Bit-encoded input to kinetis_configgpio() ****************************************/
+/* General form (32-bits, only 20 bits are unused in the encoding):
+ *
+ * oooo mmmf iiii ---- ---- -ppp ---b bbbb
+ */
+
+/* Bits 25-31: 7 bits are used to encode the basic pin configuration:
+ *
+ * oooo mmm- ---- ---- ---- ---- ---- ----
+ * oooommm:
+ * |   `--- mmm: mode
+ * `------- oooo: options (may be combined)
+ */
+
+#define _GPIO_MODE_SHIFT        (25) /* Bits 25-27: Pin mode */
+#define _GPIO_MODE_MASK         (7 << _GPIO_MODE_SHIFT)
+#define _GPIO_OPTIONS_SHIFT     (28) /* Bits 28-31: Pin mode options */
+#define _GPIO_OPTIONS_MASK      (15 << _GPIO_OPTIONS_SHIFT)
+
+#define _GPIO_MODE_ANALOG       (0)  /* 000 Pin Disabled (Analog) */
+#define _GPIO_MODE_GPIO         (1)  /* 001 Alternative 1 (GPIO) */
+#define _GPIO_MODE_ALT2         (2)  /* 010 Alternative 2 */
+#define _GPIO_MODE_ALT3         (3)  /* 011 Alternative 3 */
+#define _GPIO_MODE_ALT4         (4)  /* 100 Alternative 4 */
+#define _GPIO_MODE_ALT5         (5)  /* 101 Alternative 5 */
+#define _GPIO_MODE_ALT6         (6)  /* 110 Alternative 6 */
+#define _GPIO_MODE_ALT7         (7)  /* 111 Alternative 7 */
+
+#define _GPIO_IO_MASK           (1)  /* xxx1 GPIO input/output mask */
+#define _GPIO_INPUT             (0)  /* xxx0 GPIO input */
+#define _GPIO_INPUT_PULLMASK    (6)  /* x11x Mask for pull-up or -down bits */
+#define _GPIO_INPUT_PULLENABLE  (2)  /* x010 Enables pull-up or -down */
+#define _GPIO_INPUT_PULLDOWN    (2)  /* x010 Input with internal pull-down resistor */
+#define _GPIO_INPUT_PULLUP      (6)  /* x110 Input with internal pull-up resistor */
+#define _GPIO_INPUT_FILTER_MASK (8)  /* 1xxx Mask to test if passive filter enabled */
+#define _GPIO_INPUT_FILTER      (8)  /* 1xx0 Input with passive filter enabled */
+
+#define _GPIO_OUTPUT            (1)  /* xxx1 GPIO output */
+#define _GPIO_OUTPUT_SLEW_MASK  (2)  /* xx1x Mask to test for slow slew rate */
+#define _GPIO_OUTPUT_FAST       (1)  /* xx01 Output with fast slew rate */
+#define _GPIO_OUTPUT_SLOW       (3)  /* xx11 Output with slow slew rate */
+#define _GPIO_OUTPUT_OD_MASK    (4)  /* x1xx Mask to test for open drain */
+#define _GPIO_OUTPUT_OPENDRAIN  (5)  /* x1x1 Output with open drain enabled */
+#define _GPIO_OUTPUT_DRIVE_MASK (4)  /* 1xxx Mask to test for high drive strengh */
+#define _GPIO_OUTPUT_LOWDRIVE   (1)  /* 0xx1 Output with low drive strength */
+#define _GPIO_OUTPUT_HIGHDRIVE  (9)  /* 1xx1 Output with high drive strength */
+
+#define GPIO_ANALOG             (_GPIO_MODE_ANALOG       << _GPIO_MODE_SHIFT)
+
+#define GPIO_INPUT              ((_GPIO_MODE_GPIO        << _GPIO_MODE_SHIFT) | \
+                                 (_GPIO_INPUT            << _GPIO_OPTIONS_SHIFT))
+#define GPIO_PULLDOWN           ((_GPIO_MODE_GPIO        << _GPIO_MODE_SHIFT) | \
+                                 (_GPIO_INPUT_PULLDOWN   << _GPIO_OPTIONS_SHIFT))
+#define GPIO_PULLDOWN           ((_GPIO_MODE_GPIO        << _GPIO_MODE_SHIFT) | \
+                                 (_GPIO_INPUT_PULLUP     << _GPIO_OPTIONS_SHIFT))
+#define GPIO_FILTER             ((_GPIO_MODE_GPIO        << _GPIO_MODE_SHIFT) | \
+                                 (_GPIO_INPUT_FILTER     << _GPIO_OPTIONS_SHIFT))
+
+#define GPIO_OUTPUT             ((_GPIO_MODE_GPIO        << _GPIO_MODE_SHIFT) | \
+                                 (_GPIO_OUTPUT           << _GPIO_OPTIONS_SHIFT))
+#define GPIO_FAST               ((_GPIO_MODE_GPIO        << _GPIO_MODE_SHIFT) | \
+                                 (_GPIO_OUTPUT_FAST      << _GPIO_OPTIONS_SHIFT))
+#define GPIO_SLOW               ((_GPIO_MODE_GPIO        << _GPIO_MODE_SHIFT) | \
+                                 (_GPIO_OUTPUT_SLOW      << _GPIO_OPTIONS_SHIFT))
+#define GPIO_OPENDRAIN          ((_GPIO_MODE_GPIO        << _GPIO_MODE_SHIFT) | \
+                                 (_GPIO_OUTPUT_LOWDRIVE  << _GPIO_OPTIONS_SHIFT))
+#define GPIO_LOWDRIVE           ((_GPIO_MODE_GPIO        << _GPIO_MODE_SHIFT) | \
+                                 (_GPIO_OUTPUT_OPENDRAIN << _GPIO_OPTIONS_SHIFT))
+#define GPIO_HIGHDRIVE          ((_GPIO_MODE_GPIO        << _GPIO_MODE_SHIFT) | \
+                                 (_GPIO_OUTPUT_HIGHDRIVE << _GPIO_OPTIONS_SHIFT))
+
+#define GPIO_ALT2               (_GPIO_MODE_ALT2         << _GPIO_MODE_SHIFT)
+#define GPIO_ALT3               (_GPIO_MODE_ALT3         << _GPIO_MODE_SHIFT)
+#define GPIO_ALT4               (_GPIO_MODE_ALT4         << _GPIO_MODE_SHIFT)
+#define GPIO_ALT5               (_GPIO_MODE_ALT5         << _GPIO_MODE_SHIFT)
+#define GPIO_ALT6               (_GPIO_MODE_ALT6         << _GPIO_MODE_SHIFT)
+#define GPIO_ALT7               (_GPIO_MODE_ALT7         << _GPIO_MODE_SHIFT)
+
+/* One bit is used to enable the digital filter:
+ *
+ * ---- ---f ---- ---- ---- ---- ---- ----
+ */
+
+#define GPIO_DIGFILTER          (1 << 24)  /* Bit 24: Enable digital filter */
+
+/* Four bits are used to incode DMA/interupt options:
+ *
+ * ---- ---- iiii ---- ---- ---- ---- ----
+ */
+
+#define _GPIO_INT_SHIFT         (20)
+#define _GPIO_INT_MASK          (15 << _GPIO_MODE_SHIFT)
+
+#define _GPIO_INTDMA_MASK       (1)  /* xxx1 DMA/interrupt mask */
+#define _GPIO_DMA               (0)  /* xxx0 DMA (vs interrupt) */
+#define _GPIO_DMA_EDGE_MASK     (6)  /* x11x Mask to test edge */
+#define _GPIO_DMA_RISING        (2)  /* x010 DMA Request on rising edge */
+#define _GPIO_DMA_FALLING       (4)  /* x100 DMA Request on falling edge */
+#define _GPIO_DMA_BOTH          (6)  /* x110 DMA Request on either edge */
+
+#define _GPIO_INTERRUPT         (1)  /* xxx1 Interrupt (vs DMA) */
+#define _GPIO_INT_ZERO          (1)  /* 0001 Interrupt when logic zero */
+#define _GPIO_INT_RISING        (3)  /* 0011 Interrupt on rising edge */
+#define _GPIO_INT_FALLING       (5)  /* 0101 Interrupt on falling edge */
+#define _GPIO_INT_BOTH          (7)  /* 0111 Interrupt on either edge */
+#define _GPIO_INT_BOTH          (9)  /* 1001 Interrupt when logic one */
+
+#define GPIO_DMA_RISING         (_GPIO_DMA_RISING  << _GPIO_MODE_SHIFT)
+#define GPIO_DMA_FALLING        (_GPIO_DMA_FALLING << _GPIO_MODE_SHIFT)
+#define GPIO_DMA_BOTH           (_GPIO_DMA_BOTH    << _GPIO_MODE_SHIFT)
+#define GPIO_INT_ZERO           (_GPIO_INT_ZERO    << _GPIO_MODE_SHIFT)
+#define GPIO_INT_RISING         (_GPIO_INT_RISING  << _GPIO_MODE_SHIFT)
+#define GPIO_INT_FALLING        (_GPIO_INT_FALLING << _GPIO_MODE_SHIFT)
+#define GPIO_INT_BOTH           (_GPIO_INT_BOTH    << _GPIO_MODE_SHIFT)
+#define GPIO_INT_ONE            (_GPIO_INT_BOTH    << _GPIO_MODE_SHIFT)
+
+/* Three bits are used to define the port number:
+ *
+ * oooo mmmf iiii ---- ---- -ppp ---b bbbb
+ */
+
+#define _GPIO_PORT_SHIFT        (8)  /* Bits 8-10: port number */
+#define _GPIO_PORT_MASK         (7 << _GPIO_PORT_SHIFT)
+
+#define GPIO_PORTA              (KINETIS_PORTA << _GPIO_PORT_SHIFT)
+#define GPIO_PORTB              (KINETIS_PORTB << _GPIO_PORT_SHIFT)
+#define GPIO_PORTC              (KINETIS_PORTC << _GPIO_PORT_SHIFT)
+#define GPIO_PORTD              (KINETIS_PORTD << _GPIO_PORT_SHIFT)
+#define GPIO_PORTE              (KINETIS_PORTE << _GPIO_PORT_SHIFT)
+
+
+/* Five bits are used to define the pin number:
+ *
+ * oooo mmmf iiii ---- ---- -ppp ---b bbbb
+ */
+
+#define _GPIO_PIN_SHIFT         (0)  /* Bits 0-4: port number */
+#define _GPIO_PIN_MASK          (31 << _GPIO_PIN_SHIFT)
+
+#define GPIO_PIN(n)             ((n) << _GPIO_PIN_SHIFT)
+#define GPIO_PIN0               (0 << _GPIO_PIN_SHIFT)
+#define GPIO_PIN1               (1 << _GPIO_PIN_SHIFT)
+#define GPIO_PIN2               (2 << _GPIO_PIN_SHIFT)
+#define GPIO_PIN3               (3 << _GPIO_PIN_SHIFT)
+#define GPIO_PIN4               (4 << _GPIO_PIN_SHIFT)
+#define GPIO_PIN5               (5 << _GPIO_PIN_SHIFT)
+#define GPIO_PIN6               (6 << _GPIO_PIN_SHIFT)
+#define GPIO_PIN7               (7 << _GPIO_PIN_SHIFT)
+#define GPIO_PIN8               (8 << _GPIO_PIN_SHIFT)
+#define GPIO_PIN9               (9 << _GPIO_PIN_SHIFT)
+#define GPIO_PIN10              (10 << _GPIO_PIN_SHIFT)
+#define GPIO_PIN11              (11 << _GPIO_PIN_SHIFT)
+#define GPIO_PIN12              (12 << _GPIO_PIN_SHIFT)
+#define GPIO_PIN13              (13 << _GPIO_PIN_SHIFT)
+#define GPIO_PIN14              (14 << _GPIO_PIN_SHIFT)
+#define GPIO_PIN15              (15 << _GPIO_PIN_SHIFT)
+#define GPIO_PIN16              (16 << _GPIO_PIN_SHIFT)
+#define GPIO_PIN17              (17 << _GPIO_PIN_SHIFT)
+#define GPIO_PIN18              (18 << _GPIO_PIN_SHIFT)
+#define GPIO_PIN19              (19 << _GPIO_PIN_SHIFT)
+#define GPIO_PIN20              (20 << _GPIO_PIN_SHIFT)
+#define GPIO_PIN21              (21 << _GPIO_PIN_SHIFT)
+#define GPIO_PIN22              (22 << _GPIO_PIN_SHIFT)
+#define GPIO_PIN23              (23 << _GPIO_PIN_SHIFT)
+#define GPIO_PIN24              (24 << _GPIO_PIN_SHIFT)
+#define GPIO_PIN25              (25 << _GPIO_PIN_SHIFT)
+#define GPIO_PIN26              (26 << _GPIO_PIN_SHIFT)
+#define GPIO_PIN27              (27 << _GPIO_PIN_SHIFT)
+#define GPIO_PIN28              (28 << _GPIO_PIN_SHIFT)
+#define GPIO_PIN29              (29 << _GPIO_PIN_SHIFT)
+#define GPIO_PIN30              (30 << _GPIO_PIN_SHIFT)
+#define GPIO_PIN31              (31 << _GPIO_PIN_SHIFT)
 
 /************************************************************************************
  * Public Types
@@ -161,7 +332,7 @@ EXTERN void kinetis_gpioirqinitialize(void);
  *
  ************************************************************************************/
 
-EXTERN int kinetis_configgpio(uint16_t cfgset);
+EXTERN int kinetis_configgpio(uint32_t cfgset);
 
 /************************************************************************************
  * Name: kinetis_gpiowrite
@@ -171,7 +342,7 @@ EXTERN int kinetis_configgpio(uint16_t cfgset);
  *
  ************************************************************************************/
 
-EXTERN void kinetis_gpiowrite(uint16_t pinset, bool value);
+EXTERN void kinetis_gpiowrite(uint32_t pinset, bool value);
 
 /************************************************************************************
  * Name: kinetis_gpioread
@@ -181,7 +352,7 @@ EXTERN void kinetis_gpiowrite(uint16_t pinset, bool value);
  *
  ************************************************************************************/
 
-EXTERN bool kinetis_gpioread(uint16_t pinset);
+EXTERN bool kinetis_gpioread(uint32_t pinset);
 
 /************************************************************************************
  * Name: kinetis_gpioirqenable
@@ -220,7 +391,7 @@ EXTERN void kinetis_gpioirqdisable(int irq);
  ************************************************************************************/
 
 #ifdef CONFIG_DEBUG_GPIO
-EXTERN int kinetis_dumpgpio(uint16_t pinset, const char *msg);
+EXTERN int kinetis_dumpgpio(uint32_t pinset, const char *msg);
 #else
 #  define kinetis_dumpgpio(p,m)
 #endif
diff --git a/nuttx/arch/arm/src/kinetis/kinetis_memorymap.h b/nuttx/arch/arm/src/kinetis/kinetis_memorymap.h
index 2691b61ec..e0dba8e85 100755
--- a/nuttx/arch/arm/src/kinetis/kinetis_memorymap.h
+++ b/nuttx/arch/arm/src/kinetis/kinetis_memorymap.h
@@ -124,11 +124,12 @@
 # define KINETIS_TSI_BASE       0x40045000 /* Touch sense interface */
 # define KINETIS_SIMLP_BASE     0x40047000 /* SIM low-power logic */
 # define KINETIS_SIM_BASE       0x40048000 /* System integration module (SIM) */
-# define KINETIS_PAMUX_BASE     0x40049000 /* Port A multiplexing control */
-# define KINETIS_PBMUX_BASE     0x4004a000 /* Port B multiplexing control */
-# define KINETIS_PCMUX_BASE     0x4004b000 /* Port C multiplexing control */
-# define KINETIS_PDMUX_BASE     0x4004c000 /* Port D multiplexing control */
-# define KINETIS_PEMUX_BASE     0x4004d000 /* Port E multiplexing control */
+# define KINETIS_PORT_BASE(n)   (0x40049000 + ((n) << 12))
+# define KINETIS_PORTA_BASE     0x40049000 /* Port A multiplexing control */
+# define KINETIS_PORTB_BASE     0x4004a000 /* Port B multiplexing control */
+# define KINETIS_PORTC_BASE     0x4004b000 /* Port C multiplexing control */
+# define KINETIS_PORTD_BASE     0x4004c000 /* Port D multiplexing control */
+# define KINETIS_PORTE_BASE     0x4004d000 /* Port E multiplexing control */
 # define KINETIS_SWWDOG_BASE    0x40052000 /* Software watchdog */
 # define KINETIS_EXTWDOG_BASE   0x40061000 /* External watchdog */
 # define KINETIS_CMT_BASE       0x40062000 /* Carrier modulator timer (CMT) */
@@ -248,11 +249,12 @@
 # define KINETIS_TSI_BASE       0x40045000 /* Touch sense interface */
 # define KINETIS_SIMLP_BASE     0x40047000 /* SIM low-power logic */
 # define KINETIS_SIM_BASE       0x40048000 /* System integration module (SIM) */
-# define KINETIS_PAMUX_BASE     0x40049000 /* Port A multiplexing control */
-# define KINETIS_PBMUX_BASE     0x4004a000 /* Port B multiplexing control */
-# define KINETIS_PCMUX_BASE     0x4004b000 /* Port C multiplexing control */
-# define KINETIS_PDMUX_BASE     0x4004c000 /* Port D multiplexing control */
-# define KINETIS_PEMUX_BASE     0x4004d000 /* Port E multiplexing control */
+# define KINETIS_PORT_BASE(n)   (0x40049000 + ((n) << 12))
+# define KINETIS_PORTA_BASE     0x40049000 /* Port A multiplexing control */
+# define KINETIS_PORTB_BASE     0x4004a000 /* Port B multiplexing control */
+# define KINETIS_PORTC_BASE     0x4004b000 /* Port C multiplexing control */
+# define KINETIS_PORTD_BASE     0x4004c000 /* Port D multiplexing control */
+# define KINETIS_PORTE_BASE     0x4004d000 /* Port E multiplexing control */
 # define KINETIS_SWWDOG_BASE    0x40052000 /* Software watchdog */
 # define KINETIS_EXTWDOG_BASE   0x40061000 /* External watchdog */
 # define KINETIS_CMT_BASE       0x40062000 /* Carrier modulator timer (CMT) */
diff --git a/nuttx/arch/arm/src/kinetis/kinetis_port.h b/nuttx/arch/arm/src/kinetis/kinetis_port.h
new file mode 100755
index 000000000..7472af8bc
--- /dev/null
+++ b/nuttx/arch/arm/src/kinetis/kinetis_port.h
@@ -0,0 +1,430 @@
+/************************************************************************************
+ * arch/arm/src/kinetis/kinetis_port.h
+ *
+ *   Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_PORT_H
+#define __ARCH_ARM_SRC_KINETIS_KINETIS_PORT_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "chip.h"
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+/* General Definitions **************************************************************/
+
+#define KINETIS_PORTA              (0)
+#define KINETIS_PORTB              (1)
+#define KINETIS_PORTC              (2)
+#define KINETIS_PORTD              (3)
+#define KINETIS_PORTE              (4)
+
+/* Register Offsets *****************************************************************/
+
+#define KINETIS_PORT_PCR_OFFSET(n) ((n) << 2) /* Pin Control Register n, n=0..31 */
+#define KINETIS_PORT_PCR0_OFFSET   0x0000 /* Pin Control Register 0 */
+#define KINETIS_PORT_PCR1_OFFSET   0x0004 /* Pin Control Register 1 */
+#define KINETIS_PORT_PCR2_OFFSET   0x0008 /* Pin Control Register 2 */
+#define KINETIS_PORT_PCR3_OFFSET   0x000C /* Pin Control Register 3 */
+#define KINETIS_PORT_PCR4_OFFSET   0x0010 /* Pin Control Register 4 */
+#define KINETIS_PORT_PCR5_OFFSET   0x0014 /* Pin Control Register 5 */
+#define KINETIS_PORT_PCR6_OFFSET   0x0018 /* Pin Control Register 6 */
+#define KINETIS_PORT_PCR7_OFFSET   0x001c /* Pin Control Register 7 */
+#define KINETIS_PORT_PCR8_OFFSET   0x0020 /* Pin Control Register 8 */
+#define KINETIS_PORT_PCR9_OFFSET   0x0024 /* Pin Control Register 9 */
+#define KINETIS_PORT_PCR10_OFFSET  0x0028 /* Pin Control Register 10 */
+#define KINETIS_PORT_PCR11_OFFSET  0x002c /* Pin Control Register 11 */
+#define KINETIS_PORT_PCR12_OFFSET  0x0030 /* Pin Control Register 12 */
+#define KINETIS_PORT_PCR13_OFFSET  0x0034 /* Pin Control Register 13 */
+#define KINETIS_PORT_PCR14_OFFSET  0x0038 /* Pin Control Register 14 */
+#define KINETIS_PORT_PCR15_OFFSET  0x003c /* Pin Control Register 15 */
+#define KINETIS_PORT_PCR16_OFFSET  0x0040 /* Pin Control Register 16 */
+#define KINETIS_PORT_PCR17_OFFSET  0x0044 /* Pin Control Register 17 */
+#define KINETIS_PORT_PCR18_OFFSET  0x0048 /* Pin Control Register 18 */
+#define KINETIS_PORT_PCR19_OFFSET  0x004c /* Pin Control Register 19 */
+#define KINETIS_PORT_PCR20_OFFSET  0x0050 /* Pin Control Register 20 */
+#define KINETIS_PORT_PCR21_OFFSET  0x0054 /* Pin Control Register 21 */
+#define KINETIS_PORT_PCR22_OFFSET  0x0058 /* Pin Control Register 22 */
+#define KINETIS_PORT_PCR23_OFFSET  0x005c /* Pin Control Register 23 */
+#define KINETIS_PORT_PCR24_OFFSET  0x0060 /* Pin Control Register 24 */
+#define KINETIS_PORT_PCR25_OFFSET  0x0064 /* Pin Control Register 25 */
+#define KINETIS_PORT_PCR26_OFFSET  0x0068 /* Pin Control Register 26 */
+#define KINETIS_PORT_PCR27_OFFSET  0x006c /* Pin Control Register 27 */
+#define KINETIS_PORT_PCR28_OFFSET  0x0070 /* Pin Control Register 28 */
+#define KINETIS_PORT_PCR29_OFFSET  0x0074 /* Pin Control Register 29 */
+#define KINETIS_PORT_PCR30_OFFSET  0x0078 /* Pin Control Register 30 */
+#define KINETIS_PORT_PCR31_OFFSET  0x007c /* Pin Control Register 31 */
+#define KINETIS_PORT_GPCLR_OFFSET  0x0080 /* Global Pin Control Low Register */
+#define KINETIS_PORT_GPCHR_OFFSET  0x0084 /* Global Pin Control High Register */
+#define KINETIS_PORT_ISFR_OFFSET   0x00a0 /* Interrupt Status Flag Register */
+#define KINETIS_PORT_DFER_OFFSET   0x00c0 /* Digital Filter Enable Register */
+#define KINETIS_PORT_DFCR_OFFSET   0x00c4 /* Digital Filter Clock Register */
+#define KINETIS_PORT_DFWR_OFFSET   0x00c8 /* Digital Filter Width Register */
+
+/* Register Addresses ***************************************************************/
+
+#define KINETIS_PORT_PCR(p,n)      (KINETIS_PORT_BASE(p)+KINETIS_PORT_PCR_OFFSET(n)
+#define KINETIS_PORT_PCR0(p)       (KINETIS_PORT_BASE(p)+KINETIS_PORT_PCR0_OFFSET)
+#define KINETIS_PORT_PCR1(p)       (KINETIS_PORT_BASE(p)+KINETIS_PORT_PCR1_OFFSET)
+#define KINETIS_PORT_PCR2(p)       (KINETIS_PORT_BASE(p)+KINETIS_PORT_PCR2_OFFSET)
+#define KINETIS_PORT_PCR3(p)       (KINETIS_PORT_BASE(p)+KINETIS_PORT_PCR3_OFFSET)
+#define KINETIS_PORT_PCR4(p)       (KINETIS_PORT_BASE(p)+KINETIS_PORT_PCR4_OFFSET)
+#define KINETIS_PORT_PCR5(p)       (KINETIS_PORT_BASE(p)+KINETIS_PORT_PCR5_OFFSET)
+#define KINETIS_PORT_PCR6(p)       (KINETIS_PORT_BASE(p)+KINETIS_PORT_PCR6_OFFSET)
+#define KINETIS_PORT_PCR7(p)       (KINETIS_PORT_BASE(p)+KINETIS_PORT_PCR7_OFFSET)
+#define KINETIS_PORT_PCR8(p)       (KINETIS_PORT_BASE(p)+KINETIS_PORT_PCR8_OFFSET)
+#define KINETIS_PORT_PCR9(p)       (KINETIS_PORT_BASE(p)+KINETIS_PORT_PCR9_OFFSET)
+#define KINETIS_PORT_PCR10(p)      (KINETIS_PORT_BASE(p)+KINETIS_PORT_PCR10_OFFSET)
+#define KINETIS_PORT_PCR11(p)      (KINETIS_PORT_BASE(p)+KINETIS_PORT_PCR11_OFFSET)
+#define KINETIS_PORT_PCR12(p)      (KINETIS_PORT_BASE(p)+KINETIS_PORT_PCR12_OFFSET)
+#define KINETIS_PORT_PCR13(p)      (KINETIS_PORT_BASE(p)+KINETIS_PORT_PCR13_OFFSET)
+#define KINETIS_PORT_PCR14(p)      (KINETIS_PORT_BASE(p)+KINETIS_PORT_PCR14_OFFSET)
+#define KINETIS_PORT_PCR15(p)      (KINETIS_PORT_BASE(p)+KINETIS_PORT_PCR15_OFFSET)
+#define KINETIS_PORT_PCR16(p)      (KINETIS_PORT_BASE(p)+KINETIS_PORT_PCR16_OFFSET)
+#define KINETIS_PORT_PCR17(p)      (KINETIS_PORT_BASE(p)+KINETIS_PORT_PCR17_OFFSET)
+#define KINETIS_PORT_PCR18(p)      (KINETIS_PORT_BASE(p)+KINETIS_PORT_PCR18_OFFSET)
+#define KINETIS_PORT_PCR19(p)      (KINETIS_PORT_BASE(p)+KINETIS_PORT_PCR19_OFFSET)
+#define KINETIS_PORT_PCR20(p)      (KINETIS_PORT_BASE(p)+KINETIS_PORT_PCR20_OFFSET)
+#define KINETIS_PORT_PCR21(p)      (KINETIS_PORT_BASE(p)+KINETIS_PORT_PCR21_OFFSET)
+#define KINETIS_PORT_PCR22(p)      (KINETIS_PORT_BASE(p)+KINETIS_PORT_PCR22_OFFSET)
+#define KINETIS_PORT_PCR23(p)      (KINETIS_PORT_BASE(p)+KINETIS_PORT_PCR23_OFFSET)
+#define KINETIS_PORT_PCR24(p)      (KINETIS_PORT_BASE(p)+KINETIS_PORT_PCR24_OFFSET)
+#define KINETIS_PORT_PCR25(p)      (KINETIS_PORT_BASE(p)+KINETIS_PORT_PCR25_OFFSET)
+#define KINETIS_PORT_PCR26(p)      (KINETIS_PORT_BASE(p)+KINETIS_PORT_PCR26_OFFSET)
+#define KINETIS_PORT_PCR27(p)      (KINETIS_PORT_BASE(p)+KINETIS_PORT_PCR27_OFFSET)
+#define KINETIS_PORT_PCR28(p)      (KINETIS_PORT_BASE(p)+KINETIS_PORT_PCR28_OFFSET)
+#define KINETIS_PORT_PCR29(p)      (KINETIS_PORT_BASE(p)+KINETIS_PORT_PCR29_OFFSET)
+#define KINETIS_PORT_PCR30(p)      (KINETIS_PORT_BASE(p)+KINETIS_PORT_PCR30_OFFSET)
+#define KINETIS_PORT_PCR31(p)      (KINETIS_PORT_BASE(p)+KINETIS_PORT_PCR31_OFFSET)
+#define KINETIS_PORT_GPCLR(p)      (KINETIS_PORT_BASE(p)+KINETIS_PORT_GPCLR_OFFSET)
+#define KINETIS_PORT_GPCHR(p)      (KINETIS_PORT_BASE(p)+KINETIS_PORT_GPCHR_OFFSET)
+#define KINETIS_PORT_ISFR(p)       (KINETIS_PORT_BASE(p)+KINETIS_PORT_ISFR_OFFSET)
+#define KINETIS_PORT_DFER(p)       (KINETIS_PORT_BASE(p)+KINETIS_PORT_DFER_OFFSET)
+#define KINETIS_PORT_DFCR(p)       (KINETIS_PORT_BASE(p)+KINETIS_PORT_DFCR_OFFSET)
+#define KINETIS_PORT_DFWR(p)       (KINETIS_PORT_BASE(p)+KINETIS_PORT_DFWR_OFFSET)
+
+#define KINETIS_PORTA_PCR(n)       (KINETIS_PORTA_BASE+KINETIS_PORT_PCR_OFFSET(n)
+#define KINETIS_PORTA_PCR0         (KINETIS_PORTA_BASE+KINETIS_PORT_PCR0_OFFSET)
+#define KINETIS_PORTA_PCR1         (KINETIS_PORTA_BASE+KINETIS_PORT_PCR1_OFFSET)
+#define KINETIS_PORTA_PCR2         (KINETIS_PORTA_BASE+KINETIS_PORT_PCR2_OFFSET)
+#define KINETIS_PORTA_PCR3         (KINETIS_PORTA_BASE+KINETIS_PORT_PCR3_OFFSET)
+#define KINETIS_PORTA_PCR4         (KINETIS_PORTA_BASE+KINETIS_PORT_PCR4_OFFSET)
+#define KINETIS_PORTA_PCR5         (KINETIS_PORTA_BASE+KINETIS_PORT_PCR5_OFFSET)
+#define KINETIS_PORTA_PCR6         (KINETIS_PORTA_BASE+KINETIS_PORT_PCR6_OFFSET)
+#define KINETIS_PORTA_PCR7         (KINETIS_PORTA_BASE+KINETIS_PORT_PCR7_OFFSET)
+#define KINETIS_PORTA_PCR8         (KINETIS_PORTA_BASE+KINETIS_PORT_PCR8_OFFSET)
+#define KINETIS_PORTA_PCR9         (KINETIS_PORTA_BASE+KINETIS_PORT_PCR9_OFFSET)
+#define KINETIS_PORTA_PCR10        (KINETIS_PORTA_BASE+KINETIS_PORT_PCR10_OFFSET)
+#define KINETIS_PORTA_PCR11        (KINETIS_PORTA_BASE+KINETIS_PORT_PCR11_OFFSET)
+#define KINETIS_PORTA_PCR12        (KINETIS_PORTA_BASE+KINETIS_PORT_PCR12_OFFSET)
+#define KINETIS_PORTA_PCR13        (KINETIS_PORTA_BASE+KINETIS_PORT_PCR13_OFFSET)
+#define KINETIS_PORTA_PCR14        (KINETIS_PORTA_BASE+KINETIS_PORT_PCR14_OFFSET)
+#define KINETIS_PORTA_PCR15        (KINETIS_PORTA_BASE+KINETIS_PORT_PCR15_OFFSET)
+#define KINETIS_PORTA_PCR16        (KINETIS_PORTA_BASE+KINETIS_PORT_PCR16_OFFSET)
+#define KINETIS_PORTA_PCR17        (KINETIS_PORTA_BASE+KINETIS_PORT_PCR17_OFFSET)
+#define KINETIS_PORTA_PCR18        (KINETIS_PORTA_BASE+KINETIS_PORT_PCR18_OFFSET)
+#define KINETIS_PORTA_PCR19        (KINETIS_PORTA_BASE+KINETIS_PORT_PCR19_OFFSET)
+#define KINETIS_PORTA_PCR20        (KINETIS_PORTA_BASE+KINETIS_PORT_PCR20_OFFSET)
+#define KINETIS_PORTA_PCR21        (KINETIS_PORTA_BASE+KINETIS_PORT_PCR21_OFFSET)
+#define KINETIS_PORTA_PCR22        (KINETIS_PORTA_BASE+KINETIS_PORT_PCR22_OFFSET)
+#define KINETIS_PORTA_PCR23        (KINETIS_PORTA_BASE+KINETIS_PORT_PCR23_OFFSET)
+#define KINETIS_PORTA_PCR24        (KINETIS_PORTA_BASE+KINETIS_PORT_PCR24_OFFSET)
+#define KINETIS_PORTA_PCR25        (KINETIS_PORTA_BASE+KINETIS_PORT_PCR25_OFFSET)
+#define KINETIS_PORTA_PCR26        (KINETIS_PORTA_BASE+KINETIS_PORT_PCR26_OFFSET)
+#define KINETIS_PORTA_PCR27        (KINETIS_PORTA_BASE+KINETIS_PORT_PCR27_OFFSET)
+#define KINETIS_PORTA_PCR28        (KINETIS_PORTA_BASE+KINETIS_PORT_PCR28_OFFSET)
+#define KINETIS_PORTA_PCR29        (KINETIS_PORTA_BASE+KINETIS_PORT_PCR29_OFFSET)
+#define KINETIS_PORTA_PCR30        (KINETIS_PORTA_BASE+KINETIS_PORT_PCR30_OFFSET)
+#define KINETIS_PORTA_PCR31        (KINETIS_PORTA_BASE+KINETIS_PORT_PCR31_OFFSET)
+#define KINETIS_PORTA_GPCLR        (KINETIS_PORTA_BASE+KINETIS_PORT_GPCLR_OFFSET)
+#define KINETIS_PORTA_GPCHR        (KINETIS_PORTA_BASE+KINETIS_PORT_GPCHR_OFFSET)
+#define KINETIS_PORTA_ISFR         (KINETIS_PORTA_BASE+KINETIS_PORT_ISFR_OFFSET)
+#define KINETIS_PORTA_DFER         (KINETIS_PORTA_BASE+KINETIS_PORT_DFER_OFFSET)
+#define KINETIS_PORTA_DFCR         (KINETIS_PORTA_BASE+KINETIS_PORT_DFCR_OFFSET)
+#define KINETIS_PORTA_DFWR         (KINETIS_PORTA_BASE+KINETIS_PORT_DFWR_OFFSET)
+
+#define KINETIS_PORTB_PCR(n)       (KINETIS_PORTB_BASE+KINETIS_PORT_PCR_OFFSET(n)
+#define KINETIS_PORTB_PCR0         (KINETIS_PORTB_BASE+KINETIS_PORT_PCR0_OFFSET)
+#define KINETIS_PORTB_PCR1         (KINETIS_PORTB_BASE+KINETIS_PORT_PCR1_OFFSET)
+#define KINETIS_PORTB_PCR2         (KINETIS_PORTB_BASE+KINETIS_PORT_PCR2_OFFSET)
+#define KINETIS_PORTB_PCR3         (KINETIS_PORTB_BASE+KINETIS_PORT_PCR3_OFFSET)
+#define KINETIS_PORTB_PCR4         (KINETIS_PORTB_BASE+KINETIS_PORT_PCR4_OFFSET)
+#define KINETIS_PORTB_PCR5         (KINETIS_PORTB_BASE+KINETIS_PORT_PCR5_OFFSET)
+#define KINETIS_PORTB_PCR6         (KINETIS_PORTB_BASE+KINETIS_PORT_PCR6_OFFSET)
+#define KINETIS_PORTB_PCR7         (KINETIS_PORTB_BASE+KINETIS_PORT_PCR7_OFFSET)
+#define KINETIS_PORTB_PCR8         (KINETIS_PORTB_BASE+KINETIS_PORT_PCR8_OFFSET)
+#define KINETIS_PORTB_PCR9         (KINETIS_PORTB_BASE+KINETIS_PORT_PCR9_OFFSET)
+#define KINETIS_PORTB_PCR10        (KINETIS_PORTB_BASE+KINETIS_PORT_PCR10_OFFSET)
+#define KINETIS_PORTB_PCR11        (KINETIS_PORTB_BASE+KINETIS_PORT_PCR11_OFFSET)
+#define KINETIS_PORTB_PCR12        (KINETIS_PORTB_BASE+KINETIS_PORT_PCR12_OFFSET)
+#define KINETIS_PORTB_PCR13        (KINETIS_PORTB_BASE+KINETIS_PORT_PCR13_OFFSET)
+#define KINETIS_PORTB_PCR14        (KINETIS_PORTB_BASE+KINETIS_PORT_PCR14_OFFSET)
+#define KINETIS_PORTB_PCR15        (KINETIS_PORTB_BASE+KINETIS_PORT_PCR15_OFFSET)
+#define KINETIS_PORTB_PCR16        (KINETIS_PORTB_BASE+KINETIS_PORT_PCR16_OFFSET)
+#define KINETIS_PORTB_PCR17        (KINETIS_PORTB_BASE+KINETIS_PORT_PCR17_OFFSET)
+#define KINETIS_PORTB_PCR18        (KINETIS_PORTB_BASE+KINETIS_PORT_PCR18_OFFSET)
+#define KINETIS_PORTB_PCR19        (KINETIS_PORTB_BASE+KINETIS_PORT_PCR19_OFFSET)
+#define KINETIS_PORTB_PCR20        (KINETIS_PORTB_BASE+KINETIS_PORT_PCR20_OFFSET)
+#define KINETIS_PORTB_PCR21        (KINETIS_PORTB_BASE+KINETIS_PORT_PCR21_OFFSET)
+#define KINETIS_PORTB_PCR22        (KINETIS_PORTB_BASE+KINETIS_PORT_PCR22_OFFSET)
+#define KINETIS_PORTB_PCR23        (KINETIS_PORTB_BASE+KINETIS_PORT_PCR23_OFFSET)
+#define KINETIS_PORTB_PCR24        (KINETIS_PORTB_BASE+KINETIS_PORT_PCR24_OFFSET)
+#define KINETIS_PORTB_PCR25        (KINETIS_PORTB_BASE+KINETIS_PORT_PCR25_OFFSET)
+#define KINETIS_PORTB_PCR26        (KINETIS_PORTB_BASE+KINETIS_PORT_PCR26_OFFSET)
+#define KINETIS_PORTB_PCR27        (KINETIS_PORTB_BASE+KINETIS_PORT_PCR27_OFFSET)
+#define KINETIS_PORTB_PCR28        (KINETIS_PORTB_BASE+KINETIS_PORT_PCR28_OFFSET)
+#define KINETIS_PORTB_PCR29        (KINETIS_PORTB_BASE+KINETIS_PORT_PCR29_OFFSET)
+#define KINETIS_PORTB_PCR30        (KINETIS_PORTB_BASE+KINETIS_PORT_PCR30_OFFSET)
+#define KINETIS_PORTB_PCR31        (KINETIS_PORTB_BASE+KINETIS_PORT_PCR31_OFFSET)
+#define KINETIS_PORTB_GPCLR        (KINETIS_PORTB_BASE+KINETIS_PORT_GPCLR_OFFSET)
+#define KINETIS_PORTB_GPCHR        (KINETIS_PORTB_BASE+KINETIS_PORT_GPCHR_OFFSET)
+#define KINETIS_PORTB_ISFR         (KINETIS_PORTB_BASE+KINETIS_PORT_ISFR_OFFSET)
+#define KINETIS_PORTB_DFER         (KINETIS_PORTB_BASE+KINETIS_PORT_DFER_OFFSET)
+#define KINETIS_PORTB_DFCR         (KINETIS_PORTB_BASE+KINETIS_PORT_DFCR_OFFSET)
+#define KINETIS_PORTB_DFWR         (KINETIS_PORTB_BASE+KINETIS_PORT_DFWR_OFFSET)
+
+#define KINETIS_PORTC_PCR(n)       (KINETIS_PORTC_BASE+KINETIS_PORT_PCR_OFFSET(n)
+#define KINETIS_PORTC_PCR0         (KINETIS_PORTC_BASE+KINETIS_PORT_PCR0_OFFSET)
+#define KINETIS_PORTC_PCR1         (KINETIS_PORTC_BASE+KINETIS_PORT_PCR1_OFFSET)
+#define KINETIS_PORTC_PCR2         (KINETIS_PORTC_BASE+KINETIS_PORT_PCR2_OFFSET)
+#define KINETIS_PORTC_PCR3         (KINETIS_PORTC_BASE+KINETIS_PORT_PCR3_OFFSET)
+#define KINETIS_PORTC_PCR4         (KINETIS_PORTC_BASE+KINETIS_PORT_PCR4_OFFSET)
+#define KINETIS_PORTC_PCR5         (KINETIS_PORTC_BASE+KINETIS_PORT_PCR5_OFFSET)
+#define KINETIS_PORTC_PCR6         (KINETIS_PORTC_BASE+KINETIS_PORT_PCR6_OFFSET)
+#define KINETIS_PORTC_PCR7         (KINETIS_PORTC_BASE+KINETIS_PORT_PCR7_OFFSET)
+#define KINETIS_PORTC_PCR8         (KINETIS_PORTC_BASE+KINETIS_PORT_PCR8_OFFSET)
+#define KINETIS_PORTC_PCR9         (KINETIS_PORTC_BASE+KINETIS_PORT_PCR9_OFFSET)
+#define KINETIS_PORTC_PCR10        (KINETIS_PORTC_BASE+KINETIS_PORT_PCR10_OFFSET)
+#define KINETIS_PORTC_PCR11        (KINETIS_PORTC_BASE+KINETIS_PORT_PCR11_OFFSET)
+#define KINETIS_PORTC_PCR12        (KINETIS_PORTC_BASE+KINETIS_PORT_PCR12_OFFSET)
+#define KINETIS_PORTC_PCR13        (KINETIS_PORTC_BASE+KINETIS_PORT_PCR13_OFFSET)
+#define KINETIS_PORTC_PCR14        (KINETIS_PORTC_BASE+KINETIS_PORT_PCR14_OFFSET)
+#define KINETIS_PORTC_PCR15        (KINETIS_PORTC_BASE+KINETIS_PORT_PCR15_OFFSET)
+#define KINETIS_PORTC_PCR16        (KINETIS_PORTC_BASE+KINETIS_PORT_PCR16_OFFSET)
+#define KINETIS_PORTC_PCR17        (KINETIS_PORTC_BASE+KINETIS_PORT_PCR17_OFFSET)
+#define KINETIS_PORTC_PCR18        (KINETIS_PORTC_BASE+KINETIS_PORT_PCR18_OFFSET)
+#define KINETIS_PORTC_PCR19        (KINETIS_PORTC_BASE+KINETIS_PORT_PCR19_OFFSET)
+#define KINETIS_PORTC_PCR20        (KINETIS_PORTC_BASE+KINETIS_PORT_PCR20_OFFSET)
+#define KINETIS_PORTC_PCR21        (KINETIS_PORTC_BASE+KINETIS_PORT_PCR21_OFFSET)
+#define KINETIS_PORTC_PCR22        (KINETIS_PORTC_BASE+KINETIS_PORT_PCR22_OFFSET)
+#define KINETIS_PORTC_PCR23        (KINETIS_PORTC_BASE+KINETIS_PORT_PCR23_OFFSET)
+#define KINETIS_PORTC_PCR24        (KINETIS_PORTC_BASE+KINETIS_PORT_PCR24_OFFSET)
+#define KINETIS_PORTC_PCR25        (KINETIS_PORTC_BASE+KINETIS_PORT_PCR25_OFFSET)
+#define KINETIS_PORTC_PCR26        (KINETIS_PORTC_BASE+KINETIS_PORT_PCR26_OFFSET)
+#define KINETIS_PORTC_PCR27        (KINETIS_PORTC_BASE+KINETIS_PORT_PCR27_OFFSET)
+#define KINETIS_PORTC_PCR28        (KINETIS_PORTC_BASE+KINETIS_PORT_PCR28_OFFSET)
+#define KINETIS_PORTC_PCR29        (KINETIS_PORTC_BASE+KINETIS_PORT_PCR29_OFFSET)
+#define KINETIS_PORTC_PCR30        (KINETIS_PORTC_BASE+KINETIS_PORT_PCR30_OFFSET)
+#define KINETIS_PORTC_PCR31        (KINETIS_PORTC_BASE+KINETIS_PORT_PCR31_OFFSET)
+#define KINETIS_PORTC_GPCLR        (KINETIS_PORTC_BASE+KINETIS_PORT_GPCLR_OFFSET)
+#define KINETIS_PORTC_GPCHR        (KINETIS_PORTC_BASE+KINETIS_PORT_GPCHR_OFFSET)
+#define KINETIS_PORTC_ISFR         (KINETIS_PORTC_BASE+KINETIS_PORT_ISFR_OFFSET)
+#define KINETIS_PORTC_DFER         (KINETIS_PORTC_BASE+KINETIS_PORT_DFER_OFFSET)
+#define KINETIS_PORTC_DFCR         (KINETIS_PORTC_BASE+KINETIS_PORT_DFCR_OFFSET)
+#define KINETIS_PORTC_DFWR         (KINETIS_PORTC_BASE+KINETIS_PORT_DFWR_OFFSET)
+
+#define KINETIS_PORTD_PCR(n)       (KINETIS_PORTD_BASE+KINETIS_PORT_PCR_OFFSET(n)
+#define KINETIS_PORTD_PCR0         (KINETIS_PORTD_BASE+KINETIS_PORT_PCR0_OFFSET)
+#define KINETIS_PORTD_PCR1         (KINETIS_PORTD_BASE+KINETIS_PORT_PCR1_OFFSET)
+#define KINETIS_PORTD_PCR2         (KINETIS_PORTD_BASE+KINETIS_PORT_PCR2_OFFSET)
+#define KINETIS_PORTD_PCR3         (KINETIS_PORTD_BASE+KINETIS_PORT_PCR3_OFFSET)
+#define KINETIS_PORTD_PCR4         (KINETIS_PORTD_BASE+KINETIS_PORT_PCR4_OFFSET)
+#define KINETIS_PORTD_PCR5         (KINETIS_PORTD_BASE+KINETIS_PORT_PCR5_OFFSET)
+#define KINETIS_PORTD_PCR6         (KINETIS_PORTD_BASE+KINETIS_PORT_PCR6_OFFSET)
+#define KINETIS_PORTD_PCR7         (KINETIS_PORTD_BASE+KINETIS_PORT_PCR7_OFFSET)
+#define KINETIS_PORTD_PCR8         (KINETIS_PORTD_BASE+KINETIS_PORT_PCR8_OFFSET)
+#define KINETIS_PORTD_PCR9         (KINETIS_PORTD_BASE+KINETIS_PORT_PCR9_OFFSET)
+#define KINETIS_PORTD_PCR10        (KINETIS_PORTD_BASE+KINETIS_PORT_PCR10_OFFSET)
+#define KINETIS_PORTD_PCR11        (KINETIS_PORTD_BASE+KINETIS_PORT_PCR11_OFFSET)
+#define KINETIS_PORTD_PCR12        (KINETIS_PORTD_BASE+KINETIS_PORT_PCR12_OFFSET)
+#define KINETIS_PORTD_PCR13        (KINETIS_PORTD_BASE+KINETIS_PORT_PCR13_OFFSET)
+#define KINETIS_PORTD_PCR14        (KINETIS_PORTD_BASE+KINETIS_PORT_PCR14_OFFSET)
+#define KINETIS_PORTD_PCR15        (KINETIS_PORTD_BASE+KINETIS_PORT_PCR15_OFFSET)
+#define KINETIS_PORTD_PCR16        (KINETIS_PORTD_BASE+KINETIS_PORT_PCR16_OFFSET)
+#define KINETIS_PORTD_PCR17        (KINETIS_PORTD_BASE+KINETIS_PORT_PCR17_OFFSET)
+#define KINETIS_PORTD_PCR18        (KINETIS_PORTD_BASE+KINETIS_PORT_PCR18_OFFSET)
+#define KINETIS_PORTD_PCR19        (KINETIS_PORTD_BASE+KINETIS_PORT_PCR19_OFFSET)
+#define KINETIS_PORTD_PCR20        (KINETIS_PORTD_BASE+KINETIS_PORT_PCR20_OFFSET)
+#define KINETIS_PORTD_PCR21        (KINETIS_PORTD_BASE+KINETIS_PORT_PCR21_OFFSET)
+#define KINETIS_PORTD_PCR22        (KINETIS_PORTD_BASE+KINETIS_PORT_PCR22_OFFSET)
+#define KINETIS_PORTD_PCR23        (KINETIS_PORTD_BASE+KINETIS_PORT_PCR23_OFFSET)
+#define KINETIS_PORTD_PCR24        (KINETIS_PORTD_BASE+KINETIS_PORT_PCR24_OFFSET)
+#define KINETIS_PORTD_PCR25        (KINETIS_PORTD_BASE+KINETIS_PORT_PCR25_OFFSET)
+#define KINETIS_PORTD_PCR26        (KINETIS_PORTD_BASE+KINETIS_PORT_PCR26_OFFSET)
+#define KINETIS_PORTD_PCR27        (KINETIS_PORTD_BASE+KINETIS_PORT_PCR27_OFFSET)
+#define KINETIS_PORTD_PCR28        (KINETIS_PORTD_BASE+KINETIS_PORT_PCR28_OFFSET)
+#define KINETIS_PORTD_PCR29        (KINETIS_PORTD_BASE+KINETIS_PORT_PCR29_OFFSET)
+#define KINETIS_PORTD_PCR30        (KINETIS_PORTD_BASE+KINETIS_PORT_PCR30_OFFSET)
+#define KINETIS_PORTD_PCR31        (KINETIS_PORTD_BASE+KINETIS_PORT_PCR31_OFFSET)
+#define KINETIS_PORTD_GPCLR        (KINETIS_PORTD_BASE+KINETIS_PORT_GPCLR_OFFSET)
+#define KINETIS_PORTD_GPCHR        (KINETIS_PORTD_BASE+KINETIS_PORT_GPCHR_OFFSET)
+#define KINETIS_PORTD_ISFR         (KINETIS_PORTD_BASE+KINETIS_PORT_ISFR_OFFSET)
+#define KINETIS_PORTD_DFER         (KINETIS_PORTD_BASE+KINETIS_PORT_DFER_OFFSET)
+#define KINETIS_PORTD_DFCR         (KINETIS_PORTD_BASE+KINETIS_PORT_DFCR_OFFSET)
+#define KINETIS_PORTD_DFWR         (KINETIS_PORTD_BASE+KINETIS_PORT_DFWR_OFFSET)
+
+#define KINETIS_PORTE_PCR(n)       (KINETIS_PORTE_BASE+KINETIS_PORT_PCR_OFFSET(n)
+#define KINETIS_PORTE_PCR0         (KINETIS_PORTE_BASE+KINETIS_PORT_PCR0_OFFSET)
+#define KINETIS_PORTE_PCR1         (KINETIS_PORTE_BASE+KINETIS_PORT_PCR1_OFFSET)
+#define KINETIS_PORTE_PCR2         (KINETIS_PORTE_BASE+KINETIS_PORT_PCR2_OFFSET)
+#define KINETIS_PORTE_PCR3         (KINETIS_PORTE_BASE+KINETIS_PORT_PCR3_OFFSET)
+#define KINETIS_PORTE_PCR4         (KINETIS_PORTE_BASE+KINETIS_PORT_PCR4_OFFSET)
+#define KINETIS_PORTE_PCR5         (KINETIS_PORTE_BASE+KINETIS_PORT_PCR5_OFFSET)
+#define KINETIS_PORTE_PCR6         (KINETIS_PORTE_BASE+KINETIS_PORT_PCR6_OFFSET)
+#define KINETIS_PORTE_PCR7         (KINETIS_PORTE_BASE+KINETIS_PORT_PCR7_OFFSET)
+#define KINETIS_PORTE_PCR8         (KINETIS_PORTE_BASE+KINETIS_PORT_PCR8_OFFSET)
+#define KINETIS_PORTE_PCR9         (KINETIS_PORTE_BASE+KINETIS_PORT_PCR9_OFFSET)
+#define KINETIS_PORTE_PCR10        (KINETIS_PORTE_BASE+KINETIS_PORT_PCR10_OFFSET)
+#define KINETIS_PORTE_PCR11        (KINETIS_PORTE_BASE+KINETIS_PORT_PCR11_OFFSET)
+#define KINETIS_PORTE_PCR12        (KINETIS_PORTE_BASE+KINETIS_PORT_PCR12_OFFSET)
+#define KINETIS_PORTE_PCR13        (KINETIS_PORTE_BASE+KINETIS_PORT_PCR13_OFFSET)
+#define KINETIS_PORTE_PCR14        (KINETIS_PORTE_BASE+KINETIS_PORT_PCR14_OFFSET)
+#define KINETIS_PORTE_PCR15        (KINETIS_PORTE_BASE+KINETIS_PORT_PCR15_OFFSET)
+#define KINETIS_PORTE_PCR16        (KINETIS_PORTE_BASE+KINETIS_PORT_PCR16_OFFSET)
+#define KINETIS_PORTE_PCR17        (KINETIS_PORTE_BASE+KINETIS_PORT_PCR17_OFFSET)
+#define KINETIS_PORTE_PCR18        (KINETIS_PORTE_BASE+KINETIS_PORT_PCR18_OFFSET)
+#define KINETIS_PORTE_PCR19        (KINETIS_PORTE_BASE+KINETIS_PORT_PCR19_OFFSET)
+#define KINETIS_PORTE_PCR20        (KINETIS_PORTE_BASE+KINETIS_PORT_PCR20_OFFSET)
+#define KINETIS_PORTE_PCR21        (KINETIS_PORTE_BASE+KINETIS_PORT_PCR21_OFFSET)
+#define KINETIS_PORTE_PCR22        (KINETIS_PORTE_BASE+KINETIS_PORT_PCR22_OFFSET)
+#define KINETIS_PORTE_PCR23        (KINETIS_PORTE_BASE+KINETIS_PORT_PCR23_OFFSET)
+#define KINETIS_PORTE_PCR24        (KINETIS_PORTE_BASE+KINETIS_PORT_PCR24_OFFSET)
+#define KINETIS_PORTE_PCR25        (KINETIS_PORTE_BASE+KINETIS_PORT_PCR25_OFFSET)
+#define KINETIS_PORTE_PCR26        (KINETIS_PORTE_BASE+KINETIS_PORT_PCR26_OFFSET)
+#define KINETIS_PORTE_PCR27        (KINETIS_PORTE_BASE+KINETIS_PORT_PCR27_OFFSET)
+#define KINETIS_PORTE_PCR28        (KINETIS_PORTE_BASE+KINETIS_PORT_PCR28_OFFSET)
+#define KINETIS_PORTE_PCR29        (KINETIS_PORTE_BASE+KINETIS_PORT_PCR29_OFFSET)
+#define KINETIS_PORTE_PCR30        (KINETIS_PORTE_BASE+KINETIS_PORT_PCR30_OFFSET)
+#define KINETIS_PORTE_PCR31        (KINETIS_PORTE_BASE+KINETIS_PORT_PCR31_OFFSET)
+#define KINETIS_PORTE_GPCLR        (KINETIS_PORTE_BASE+KINETIS_PORT_GPCLR_OFFSET)
+#define KINETIS_PORTE_GPCHR        (KINETIS_PORTE_BASE+KINETIS_PORT_GPCHR_OFFSET)
+#define KINETIS_PORTE_ISFR         (KINETIS_PORTE_BASE+KINETIS_PORT_ISFR_OFFSET)
+#define KINETIS_PORTE_DFER         (KINETIS_PORTE_BASE+KINETIS_PORT_DFER_OFFSET)
+#define KINETIS_PORTE_DFCR         (KINETIS_PORTE_BASE+KINETIS_PORT_DFCR_OFFSET)
+#define KINETIS_PORTE_DFWR         (KINETIS_PORTE_BASE+KINETIS_PORT_DFWR_OFFSET)
+
+/* Register Bit Definitions *********************************************************/
+/* Pin Control Register n, n=0..31 */
+
+#define PORT_PCR_PS                 (1 << 0)  /* Bit 0: Pull Select */
+#define PORT_PCR_PE                 (1 << 1)  /* Bit 1: Pull Enable */
+#define PORT_PCR_SRE                (1 << 2)  /* Bit 2: Slew Rate Enable */
+                                              /* Bit 3: Reserved */
+#define PORT_PCR_PFE                (1 << 4)  /* Bit 4: Passive Filter Enable */
+#define PORT_PCR_ODE                (1 << 5)  /* Bit 5: Open Drain Enable */
+#define PORT_PCR_DSE                (1 << 6)  /* Bit 6: Drive Strength Enable */
+                                              /* Bit 7: Reserved */
+#define PORT_PCR_MUX_SHIFT          (8)       /* Bits 8-10: Pin Mux Control */
+#define PORT_PCR_MUX_MASK           (7 << PORT_PCR_MUX_SHIFT)
+#  define PORT_PCR_MUX_ANALOG       (0 << PORT_PCR_MUX_SHIFT)  /* Pin Disabled (Analog) */
+#  define PORT_PCR_MUX_GPIO         (1 << PORT_PCR_MUX_SHIFT)  /* Alternative 1 (GPIO) */
+#  define PORT_PCR_MUX_ALT1         (1 << PORT_PCR_MUX_SHIFT)  /* Alternative 1 (GPIO) */
+#  define PORT_PCR_MUX_ALT2         (2 << PORT_PCR_MUX_SHIFT)  /* Alternative 2 (chip specific) */
+#  define PORT_PCR_MUX_ALT3         (3 << PORT_PCR_MUX_SHIFT)  /* Alternative 3 (chip specific) */
+#  define PORT_PCR_MUX_ALT4         (4 << PORT_PCR_MUX_SHIFT)  /* Alternative 4 (chip specific) */
+#  define PORT_PCR_MUX_ALT5         (5 << PORT_PCR_MUX_SHIFT)  /* Alternative 5 (chip specific) */
+#  define PORT_PCR_MUX_ALT6         (6 << PORT_PCR_MUX_SHIFT)  /* Alternative 6 (chip specific) */
+#  define PORT_PCR_MUX_ALT7         (7 << PORT_PCR_MUX_SHIFT)  /* Alternative 7 (chip specific / JTAG / NMI) */
+                                              /* Bits 11-14: Reserved */
+#define PORT_PCR_LK                 (1 << 15) /* Bit 15: Lock Register */
+#define PORT_PCR_IRQC_SHIFT         (16)      /* Bits 16-19: Interrupt Configuration */
+#define PORT_PCR_IRQC_MASK          (15 << PORT_PCR_IRQC_SHIFT)
+#  define PORT_PCR_IRQC_DISABLED    (0 << PORT_PCR_IRQC_SHIFT)  /* Interrupt/DMA Request disabled */
+#  define PORT_PCR_IRQC_DMARISING   (1 << PORT_PCR_IRQC_SHIFT)  /* DMA Request on rising edge */
+#  define PORT_PCR_IRQC_DMAFALLING  (2 << PORT_PCR_IRQC_SHIFT)  /* DMA Request on falling edge */
+#  define PORT_PCR_IRQC_DMABOTH     (3 << PORT_PCR_IRQC_SHIFT)  /* DMA Request on either edge */
+#  define PORT_PCR_IRQC_ZERO        (8 << PORT_PCR_IRQC_SHIFT)  /* Interrupt when logic zero */
+#  define PORT_PCR_IRQC_RISING      (9 << PORT_PCR_IRQC_SHIFT)  /* Interrupt on rising edge */
+#  define PORT_PCR_IRQC_FALLING     (10 << PORT_PCR_IRQC_SHIFT) /* Interrupt on falling edge */
+#  define PORT_PCR_IRQC_BOTH        (11 << PORT_PCR_IRQC_SHIFT) /* Interrupt on either edge */
+#  define PORT_PCR_IRQC_ONE         (12 << PORT_PCR_IRQC_SHIFT) /* Interrupt when logic one */
+                                              /* Bits 20-23: Reserved */
+#define PORT_PCR_ISF                (1 << 24) /* Bit 24: Interrupt Status Flag */
+                                              /* Bits 25-31: Reserved */
+
+/* Global Pin Control Low Register */
+
+#define PORT_GPCLR_GPWD_SHIFT       (0)       /* Bits 0-15: Global Pin Write Data */
+#define PORT_GPCLR_GPWD_MASK        (0xffff << PORT_GPCLR_GPWD_SHIFT)
+#  define PORT_GPCLR_GPWD(n)        ((1 << (n)) << PORT_GPCLR_GPWD_SHIFT)
+#define PORT_GPCLR_GPWE_SHIFT       (16)      /* Bits 16-31: Global Pin Write Enable */
+#define PORT_GPCLR_GPWE_MASK        (0xffff << PORT_GPCLR_GPWE_SHIFT)
+#  define PORT_GPCLR_GPWE(n)        ((1 << (n)) << PORT_GPCLR_GPWE_SHIFT)
+
+/* Global Pin Control High Register */
+
+#define PORT_GPCHR_
+
+#define PORT_GPCHR_GPWD_SHIFT       (0)       /* Bits 0-15: Global Pin Write Data */
+#define PORT_GPCHR_GPWD_MASK        (0xffff << PORT_GPCHR_GPWD_SHIFT)
+#  define PORT_GPCHR_GPWD(n)        ((1 << (n)) << PORT_GPCHR_GPWD_SHIFT)
+#define PORT_GPCHR_GPWE_SHIFT       (16)      /* Bits 16-31: Global Pin Write Enable */
+#define PORT_GPCHR_GPWE_MASK        (0xffff << PORT_GPCHR_GPWE_SHIFT)
+#  define PORT_GPCHR_GPWE(n)        ((1 << (n)) << PORT_GPCHR_GPWE_SHIFT)
+
+/* Interrupt Status Flag Register */
+
+#define PORT_ISFR(n)                (1 << (n))
+
+/* Digital Filter Enable Register */
+
+#define PORT_DFER(n)                (1 << (n))
+
+/* Digital Filter Clock Register */
+
+#define PORT_DFCR_CS                (1 << 0)  /* Bit 0: Clock Source */
+
+/* Digital Filter Width Register */
+
+#define PORT_DFWR_FILT_SHIFT        (0)       /* Bits 0-4: Filter Length */
+#define PORT_DFWR_FILT_MASK         (31 << PORT_DFWR_FILT_SHIFT)
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_PORT_H */
diff --git a/nuttx/arch/arm/src/kinetis/kinetis_uart.h b/nuttx/arch/arm/src/kinetis/kinetis_uart.h
index 39fd28b3f..af28dcbfc 100755
--- a/nuttx/arch/arm/src/kinetis/kinetis_uart.h
+++ b/nuttx/arch/arm/src/kinetis/kinetis_uart.h
@@ -289,7 +289,6 @@
 #endif
 
 /* Register Bit Definitions *********************************************************/
-
 /* UART Baud Rate Register High */
 
 #define UART_BDH_SBR_SHIFT           (0)       /* Bits 0-4: MS Bits 8-13 of the UART Baud Rate Bits */
@@ -402,42 +401,42 @@
 
 /* UART FIFO Parameters */
 
-#define UART_PFIFO_RXFIFOSIZE_SHIFT     (0)       /* Bits 0-2: Receive FIFO. Buffer Depth */
-#define UART_PFIFO_RXFIFOSIZE_MASK      (7 << UART_PFIFO_RXFIFOSIZE_SHIFT)
-#  define UART_PFIFO_RXFIFOSIZE_1       (0 << UART_PFIFO_RXFIFOSIZE_SHIFT) /* 1 */
-#  define UART_PFIFO_RXFIFOSIZE_4       (1 << UART_PFIFO_RXFIFOSIZE_SHIFT) /* 4 */
-#  define UART_PFIFO_RXFIFOSIZE_8       (2 << UART_PFIFO_RXFIFOSIZE_SHIFT) /* 8 */
-#  define UART_PFIFO_RXFIFOSIZE_16      (3 << UART_PFIFO_RXFIFOSIZE_SHIFT) /* 16 */
-#  define UART_PFIFO_RXFIFOSIZE_32      (4 << UART_PFIFO_RXFIFOSIZE_SHIFT) /* 32 */
-#  define UART_PFIFO_RXFIFOSIZE_16      (5 << UART_PFIFO_RXFIFOSIZE_SHIFT) /* 64 */
-#  define UART_PFIFO_RXFIFOSIZE_128     (6 << UART_PFIFO_RXFIFOSIZE_SHIFT) /* 128 */
-#define UART_PFIFO_RXFE                 (1 << 3)  /* Bit 3: Receive FIFO Enable */
-#define UART_PFIFO_TXFIFOSIZE_SHIFT     (4)       /* Bits 4-6: Transmit FIFO. Buffer Depth */
-#define UART_PFIFO_TXFIFOSIZE_MASK      (7 << UART_PFIFO_TXFIFOSIZE_SHIFT)
-#  define UART_PFIFO_TXFIFOSIZE_1       (0 << UART_PFIFO_TXFIFOSIZE_SHIFT) /* 1 */
-#  define UART_PFIFO_TXFIFOSIZE_4       (1 << UART_PFIFO_TXFIFOSIZE_SHIFT) /* 4 */
-#  define UART_PFIFO_TXFIFOSIZE_8       (2 << UART_PFIFO_TXFIFOSIZE_SHIFT) /* 8 */
-#  define UART_PFIFO_TXFIFOSIZE_16      (3 << UART_PFIFO_TXFIFOSIZE_SHIFT) /* 16 */
-#  define UART_PFIFO_TXFIFOSIZE_32      (4 << UART_PFIFO_TXFIFOSIZE_SHIFT) /* 32 */
-#  define UART_PFIFO_TXFIFOSIZE_16      (5 << UART_PFIFO_TXFIFOSIZE_SHIFT) /* 64 */
-#  define UART_PFIFO_TXFIFOSIZE_128     (6 << UART_PFIFO_TXFIFOSIZE_SHIFT) /* 128 */
-#define UART_PFIFO_TXFE                 (1 << 7)  /* Bit 7: Transmit FIFO Enable */
+#define UART_PFIFO_RXFIFOSIZE_SHIFT  (0)       /* Bits 0-2: Receive FIFO. Buffer Depth */
+#define UART_PFIFO_RXFIFOSIZE_MASK   (7 << UART_PFIFO_RXFIFOSIZE_SHIFT)
+#  define UART_PFIFO_RXFIFOSIZE_1    (0 << UART_PFIFO_RXFIFOSIZE_SHIFT) /* 1 */
+#  define UART_PFIFO_RXFIFOSIZE_4    (1 << UART_PFIFO_RXFIFOSIZE_SHIFT) /* 4 */
+#  define UART_PFIFO_RXFIFOSIZE_8    (2 << UART_PFIFO_RXFIFOSIZE_SHIFT) /* 8 */
+#  define UART_PFIFO_RXFIFOSIZE_16   (3 << UART_PFIFO_RXFIFOSIZE_SHIFT) /* 16 */
+#  define UART_PFIFO_RXFIFOSIZE_32   (4 << UART_PFIFO_RXFIFOSIZE_SHIFT) /* 32 */
+#  define UART_PFIFO_RXFIFOSIZE_16   (5 << UART_PFIFO_RXFIFOSIZE_SHIFT) /* 64 */
+#  define UART_PFIFO_RXFIFOSIZE_128  (6 << UART_PFIFO_RXFIFOSIZE_SHIFT) /* 128 */
+#define UART_PFIFO_RXFE              (1 << 3)  /* Bit 3: Receive FIFO Enable */
+#define UART_PFIFO_TXFIFOSIZE_SHIFT  (4)       /* Bits 4-6: Transmit FIFO. Buffer Depth */
+#define UART_PFIFO_TXFIFOSIZE_MASK   (7 << UART_PFIFO_TXFIFOSIZE_SHIFT)
+#  define UART_PFIFO_TXFIFOSIZE_1    (0 << UART_PFIFO_TXFIFOSIZE_SHIFT) /* 1 */
+#  define UART_PFIFO_TXFIFOSIZE_4    (1 << UART_PFIFO_TXFIFOSIZE_SHIFT) /* 4 */
+#  define UART_PFIFO_TXFIFOSIZE_8    (2 << UART_PFIFO_TXFIFOSIZE_SHIFT) /* 8 */
+#  define UART_PFIFO_TXFIFOSIZE_16   (3 << UART_PFIFO_TXFIFOSIZE_SHIFT) /* 16 */
+#  define UART_PFIFO_TXFIFOSIZE_32   (4 << UART_PFIFO_TXFIFOSIZE_SHIFT) /* 32 */
+#  define UART_PFIFO_TXFIFOSIZE_16   (5 << UART_PFIFO_TXFIFOSIZE_SHIFT) /* 64 */
+#  define UART_PFIFO_TXFIFOSIZE_128  (6 << UART_PFIFO_TXFIFOSIZE_SHIFT) /* 128 */
+#define UART_PFIFO_TXFE              (1 << 7)  /* Bit 7: Transmit FIFO Enable */
 
 /* UART FIFO Control Register */
 
-#define UART_CFIFO_RXUFE                (1 << 0)  /* Bit 0: Receive FIFO Underflow Interrupt Enable */
-#define UART_CFIFO_TXOFE                (1 << 1)  /* Bit 1: Transmit FIFO Overflow Interrupt Enable */
-                                                  /* Bits 2-5: Reserved */
-#define UART_CFIFO_RXFLUSH              (1 << 6)  /* Bit 6: Receive FIFO/Buffer Flush */
-#define UART_CFIFO_TXFLUSH              (1 << 7)  /* Bit 7: Transmit FIFO/Buffer Flush */
+#define UART_CFIFO_RXUFE             (1 << 0)  /* Bit 0: Receive FIFO Underflow Interrupt Enable */
+#define UART_CFIFO_TXOFE             (1 << 1)  /* Bit 1: Transmit FIFO Overflow Interrupt Enable */
+                                               /* Bits 2-5: Reserved */
+#define UART_CFIFO_RXFLUSH           (1 << 6)  /* Bit 6: Receive FIFO/Buffer Flush */
+#define UART_CFIFO_TXFLUSH           (1 << 7)  /* Bit 7: Transmit FIFO/Buffer Flush */
 
 /* UART FIFO Status Register */
 
-#define UART_SFIFO_RXUF                 (1 << 0)  /* Bit 0: Receiver Buffer Underflow Flag */
-#define UART_SFIFO_TXOF                 (1 << 1)  /* Bit 1: Transmitter Buffer Overflow Flag */
-                                                  /* Bits 2-5: Reserved */
-#define UART_SFIFO_RXEMPT               (1 << 6)  /* Bit 6: Receive Buffer/FIFO Empty */
-#define UART_SFIFO_TXEMPT               (1 << 7)  /* Bit 7: Transmit Buffer/FIFO Empty */
+#define UART_SFIFO_RXUF              (1 << 0)  /* Bit 0: Receiver Buffer Underflow Flag */
+#define UART_SFIFO_TXOF              (1 << 1)  /* Bit 1: Transmitter Buffer Overflow Flag */
+                                               /* Bits 2-5: Reserved */
+#define UART_SFIFO_RXEMPT            (1 << 6)  /* Bit 6: Receive Buffer/FIFO Empty */
+#define UART_SFIFO_TXEMPT            (1 << 7)  /* Bit 7: Transmit Buffer/FIFO Empty */
 
 /* UART FIFO Transmit Watermark.  8-bit watermark value. */
 /* UART FIFO Transmit Count. 8-bit count value */
@@ -446,53 +445,53 @@
 
 /* UART 7816 Control Register */
 
-#define UART_C7816_ISO7816E             (1 << 0)  /* Bit 0: ISO-7816 Functionality Enabled */
-#define UART_C7816_TTYPE                (1 << 1)  /* Bit 1: Transfer Type */
-#define UART_C7816_INIT                 (1 << 2)  /* Bit 2: Detect Initial Character */
-#define UART_C7816_ANACK                (1 << 3)  /* Bit 3: Generate NACK on Error */
-#define UART_C7816_ONACK                (1 << 4)  /* Bit 4: Generate NACK on Overflow */
-                                                  /* Bits 5-7: Reserved */
+#define UART_C7816_ISO7816E          (1 << 0)  /* Bit 0: ISO-7816 Functionality Enabled */
+#define UART_C7816_TTYPE             (1 << 1)  /* Bit 1: Transfer Type */
+#define UART_C7816_INIT              (1 << 2)  /* Bit 2: Detect Initial Character */
+#define UART_C7816_ANACK             (1 << 3)  /* Bit 3: Generate NACK on Error */
+#define UART_C7816_ONACK             (1 << 4)  /* Bit 4: Generate NACK on Overflow */
+                                               /* Bits 5-7: Reserved */
 
 /* UART 7816 Interrupt Enable Register */
 
-#define UART_IE7816_RXTE                (1 << 0)  /* Bit 0: Receive Threshold Exceeded Interrupt Enable */
-#define UART_IE7816_TXTE                (1 << 1)  /* Bit 1: Transmit Threshold Exceeded Interrupt Enable */
-#define UART_IE7816_GTVE                (1 << 2)  /* Bit 2: Guard Timer Violated Interrupt Enable */
-                                                  /* Bit 3: Reserved */
-#define UART_IE7816_INITDE              (1 << 4)  /* Bit 4: Initial Character Detected Interrupt Enable */
-#define UART_IE7816_BWTE                (1 << 5)  /* Bit 5: Block Wait Timer Interrupt Enable */
-#define UART_IE7816_CWTE                (1 << 6)  /* Bit 6: Character Wait Timer Interrupt Enable */
-#define UART_IE7816_WTE                 (1 << 7)  /* Bit 7: Wait Timer Interrupt Enable */
+#define UART_IE7816_RXTE             (1 << 0)  /* Bit 0: Receive Threshold Exceeded Interrupt Enable */
+#define UART_IE7816_TXTE             (1 << 1)  /* Bit 1: Transmit Threshold Exceeded Interrupt Enable */
+#define UART_IE7816_GTVE             (1 << 2)  /* Bit 2: Guard Timer Violated Interrupt Enable */
+                                               /* Bit 3: Reserved */
+#define UART_IE7816_INITDE           (1 << 4)  /* Bit 4: Initial Character Detected Interrupt Enable */
+#define UART_IE7816_BWTE             (1 << 5)  /* Bit 5: Block Wait Timer Interrupt Enable */
+#define UART_IE7816_CWTE             (1 << 6)  /* Bit 6: Character Wait Timer Interrupt Enable */
+#define UART_IE7816_WTE              (1 << 7)  /* Bit 7: Wait Timer Interrupt Enable */
 
 /* UART 7816 Interrupt Status Register */
 
-#define UART_IS7816_RXT                 (1 << 0)  /* Bit 0: Receive Threshold Exceeded Interrupt */
-#define UART_IS7816_TXT                 (1 << 1)  /* Bit 1: Transmit Threshold Exceeded Interrupt */
-#define UART_IS7816_GTV                 (1 << 2)  /* Bit 2: Guard Timer Violated Interrupt */
-                                                  /* Bit 3: Reserved */
-#define UART_IS7816_INITD               (1 << 4)  /* Bit 4: Initial Character Detected Interrupt */
-#define UART_IS7816_BWT                 (1 << 5)  /* Bit 5: Block Wait Timer Interrupt */
-#define UART_IS7816_CWT                 (1 << 6)  /* Bit 6: Character Wait Timer Interrupt */
-#define UART_IS7816_WT                  (1 << 7)  /* Bit 7: Wait Timer Interrupt */
+#define UART_IS7816_RXT              (1 << 0)  /* Bit 0: Receive Threshold Exceeded Interrupt */
+#define UART_IS7816_TXT              (1 << 1)  /* Bit 1: Transmit Threshold Exceeded Interrupt */
+#define UART_IS7816_GTV              (1 << 2)  /* Bit 2: Guard Timer Violated Interrupt */
+                                               /* Bit 3: Reserved */
+#define UART_IS7816_INITD            (1 << 4)  /* Bit 4: Initial Character Detected Interrupt */
+#define UART_IS7816_BWT              (1 << 5)  /* Bit 5: Block Wait Timer Interrupt */
+#define UART_IS7816_CWT              (1 << 6)  /* Bit 6: Character Wait Timer Interrupt */
+#define UART_IS7816_WT               (1 << 7)  /* Bit 7: Wait Timer Interrupt */
 
 /* UART 7816 Wait Parameter Register.  8-bit Wait Timer Interrupt value. */
 
 /* UART 7816 Wait Parameter Register */
 
-#define UART_WP7816T1_BWI_SHIFT         (0) /* Bit 0-3: Block Wait Time Integer(C7816[TTYPE] = 1) */
-#define UART_WP7816T1_BWI_MASK          (15 << UART_WP7816T1_BWI_SHIFT)
-#define UART_WP7816T1_CWI_SHIFT         (4) /* Bits 4-7: Character Wait Time Integer (C7816[TTYPE] = 1) */
-#define UART_WP7816T1_CWI_MASK          (15 << UART_WP7816T1_CWI_SHIFT)
+#define UART_WP7816T1_BWI_SHIFT      (0)       /* Bit 0-3: Block Wait Time Integer(C7816[TTYPE] = 1) */
+#define UART_WP7816T1_BWI_MASK       (15 << UART_WP7816T1_BWI_SHIFT)
+#define UART_WP7816T1_CWI_SHIFT      (4)       /* Bits 4-7: Character Wait Time Integer (C7816[TTYPE] = 1) */
+#define UART_WP7816T1_CWI_MASK       (15 << UART_WP7816T1_CWI_SHIFT)
 
 /* UART 7816 Wait N Register.  8-bit Guard Band value. */
 /* UART 7816 Wait FD Register. 8-bit FD Multiplier value. */
 
 /* UART 7816 Error Threshold Register */
 
-#define UART_ET7816_RXTHRESHOLD_SHIFT   (0) /* Bit 0-3: Receive NACK Threshold */
-#define UART_ET7816_RXTHRESHOLD_MASK    (15 << UART_ET7816_RXTHRESHOLD_SHIFT)
-#define UART_ET7816_TXTHRESHOLD_SHIFT   (4) /* Bits 4-7: Transmit NACK Threshold */
-#define UART_ET7816_TXTHRESHOLD_MASK    (15 << UART_ET7816_TXTHRESHOLD_MASK)
+#define UART_ET7816_RXTHRESH_SHIFT   (0)       /* Bit 0-3: Receive NACK Threshold */
+#define UART_ET7816_RXTHRESH_MASK    (15 << UART_ET7816_RXTHRESHOLD_SHIFT)
+#define UART_ET7816_TXTHRESH_SHIFT   (4)       /* Bits 4-7: Transmit NACK Threshold */
+#define UART_ET7816_TXTHRESH_MASK    (15 << UART_ET7816_TXTHRESHOLD_MASK)
 
 /* UART 7816 Transmit Length Register. 8-bit Transmit Length value */