SAM4E: Add support for the Cortex-M Cache Control block

7 files changed, 570 insertions, 199 deletions

diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog
index 1f567ba9d..a6748f2f0 100644
--- a/nuttx/ChangeLog
+++ b/nuttx/ChangeLog
@@ -6978,5 +6978,6 @@
 	* configs/spark: Refresh all spark configurations (2014-3-11).
 	* arch/arm/src/tiva/chip/tm4c_memorymap.h:  Fix typos reported by
 	  Daniel Pereira de Carvalho (2014-2-12).
-
+	* arch/arm/src/sam34/sam_cmcc.c:  Add logic to manage the Cortex-M
+	  Cache Control block.  Untested on initial check-in (2014-3-12).
 
diff --git a/nuttx/arch/arm/src/sam34/Kconfig b/nuttx/arch/arm/src/sam34/Kconfig
index 1c31f5427..e04e609ba 100644
--- a/nuttx/arch/arm/src/sam34/Kconfig
+++ b/nuttx/arch/arm/src/sam34/Kconfig
@@ -249,131 +249,174 @@ config ARCH_CHIP_SAM4S
 
 menu "AT91SAM3/4 Peripheral Support"
 
-config SAM_PICOCACHE
-	bool "PICOCACHE"
-	default y
+config SAM34_ABDACB
+	bool "Audio Bitstream DAC (ABDAC)"
+	default n
 	depends on ARCH_CHIP_SAM4L
 
-config SAM34_OCD
-	bool "On-chip DEBUG"
-	depends on ARCH_CHIP_SAM4L
-	default y if DEBUG_SYMBOLS
-	default n if !DEBUG_SYMBOLS
+config SAM34_ACC
+	bool "Analog Comparator (ACC/ACMP)"
+	default n
+	depends on ARCH_CHIP_SAM4L || ARCH_CHIP_SAM4S || ARCH_CHIP_SAM4E
 
-config SAM34_APBA
-	bool "APBA bridge"
+config SAM34_ADC
+	bool "10-bit ADC Controller (ADC)"
 	default n
-	depends on ARCH_CHIP_SAM4L
+	depends on ARCH_CHIP_SAM3U
+
+config SAM34_ADC12B
+	bool "12-bit ADC Controller (ADC12)"
+	default n
+	depends on !ARCH_CHIP_SAM4E
+
+config SAM34_AES
+	bool "AES"
+	default n
+	depends on ARCH_CHIP_SAM4E
 
 config SAM34_AESA
 	bool "Advanced Encryption Standard (AESA)"
 	default n
 	depends on ARCH_CHIP_SAM4L
 
-config SAM34_IISC
-	bool "Inter-IC Sound (I2S) Controller"
+config SAM34_AFEC0
+	bool "Analog Front End 0 (AFEC0)"
+	default n
+	depends on ARCH_CHIP_SAM4E
+
+config SAM34_AFEC1
+	bool "Analog Front End 1 (AFEC1)"
+	default n
+	depends on ARCH_CHIP_SAM4E
+
+config SAM34_APBA
+	bool "APBA bridge (APBA)"
 	default n
 	depends on ARCH_CHIP_SAM4L
 
-config SAM34_SPI0
-	bool "Serial Peripheral Interface 0 (SPI0)"
+config SAM34_AST
+	bool "Asynchronous Timer (AST)"
 	default n
+	depends on ARCH_CHIP_SAM4L
 
-config SAM34_SPI1
-	bool "Serial Peripheral Interface 1 (SPI1)"
+config SAM34_CAN0
+	bool "CAN0"
 	default n
-	depends on ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A
+	depends on ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4E
 
-config SAM34_SSC
-	bool "Synchronous Serial Controller (SSC)"
+config SAM34_CAN1
+	bool "CAN1"
 	default n
-	depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4S
+	depends on ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4E
 
-config SAM34_TC0
-	bool "Timer/Counter 0 (TC0)"
+config SAM34_CATB
+	bool "Capacitive Touch Module B (CATB)"
 	default n
+	depends on ARCH_CHIP_SAM4L
 
-config SAM34_TC1
-	bool "Timer/Counter 1 (TC1)"
+config SAM34_CHIPID
+	bool "Chip ID"
 	default n
+	depends on ARCH_CHIP_SAM4L || ARCH_CHIP_SAM4E
 
-config SAM34_TC2
-	bool "Timer/Counter 2 (TC2)"
+config SAM34_CMCC
+	bool "Cortex M Cache Controller (CMCC)"
 	default n
-	depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4S || ARCH_CHIP_SAM4E
+	depends on ARCH_CHIP_SAM4E
 
-config SAM34_TC3
-	bool "Timer/Counter 3 (TC3)"
+config SAM34_CRCCU
+	bool "CRC Calculation Unit (CRCCU)"
 	default n
-	depends on ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4S || ARCH_CHIP_SAM4E
+	depends on ARCH_CHIP_SAM4L || ARCH_CHIP_SAM4S
 
-config SAM34_TC4
-	bool "Timer/Counter 4 (TC4)"
+config SAM34_DACC
+	bool "Digital To Analog Converter (DACC)"
 	default n
-	depends on ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4S || ARCH_CHIP_SAM4E
+	depends on ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4L || ARCH_CHIP_SAM4S || ARCH_CHIP_SAM4E
 
-config SAM34_TC5
-	bool "Timer/Counter 5 (TC5)"
+config SAM34_EIC
+	bool "External Interrupt Controller (EIC)"
 	default n
-	depends on ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4S || ARCH_CHIP_SAM4E
+	depends on ARCH_CHIP_SAM4L || ARCH_CHIP_SAM4E
 
-config SAM34_TC6
-	bool "Timer/Counter 6 (TC6)"
+config SAM34_DMAC
+	bool "DMA controller"
 	default n
-	depends on ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4E
+	depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4E
+	select ARCH_DMA
 
-config SAM34_TC7
-	bool "Timer/Counter 7 (TC7)"
+config SAM34_EMAC
+	bool "Ethernet MAC (EMAC)"
 	default n
 	depends on ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4E
 
-config SAM34_TC8
-	bool "Timer/Counter 6 (TC8)"
+config SAM34_FREQM
+	bool "Frequency Meter (FREQM)"
 	default n
-	depends on ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4E
+	depends on ARCH_CHIP_SAM4L
 
-config SAM34_PWM
-	bool "Pulse Width Modulation (PWM) Controller"
+config SAM34_GLOC
+	bool "GLOC"
 	default n
-	depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4S || ARCH_CHIP_SAM4E
+	depends on ARCH_CHIP_SAM4L
 
-config SAM34_TWIM0
-	bool "Two-wire Master Interface 0 (TWIM0)"
+config SAM34_HMATRIX
+	bool "HMATRIX"
 	default n
+	depends on ARCH_CHIP_SAM4L
 
-config SAM34_TWIS0
-	bool "Two-wire Slave Interface 0 (TWIS0)"
+config SAM34_HRAMC1
+	bool "HRAMC1 (picoCache RAM)"
 	default n
+	depends on ARCH_CHIP_SAM4L
 
-config SAM34_TWIM1
-	bool "Two-wire Master Interface 1 (TWIM1)"
+config SAM34_HSMCI
+	bool "High Speed Multimedia Card Interface (HSMCI)"
 	default n
+	depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4S || ARCH_CHIP_SAM4E
+	select ARCH_HAVE_SDIO
 
-config SAM34_TWIS1
-	bool "Two-wire Slave Interface 1 (TWIS1)"
+config SAM34_IISC
+	bool "Inter-IC Sound (I2S) Controller"
 	default n
+	depends on ARCH_CHIP_SAM4L
 
-config SAM34_TWIM2
-	bool "Two-wire Master Interface 2 (TWIM2)"
+config SAM34_LCDCA
+	bool "LCD Controller A (LCDCA)"
 	default n
 	depends on ARCH_CHIP_SAM4L
 
-config SAM34_TWIM3
-	bool "Two-wire Master Interface 3 (TWIM3)"
+config SAM34_NAND
+	bool "NAND support"
+	default n
+	depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM4E
+
+config SAM34_OCD
+	bool "On-chip DEBUG (OCD)"
+	depends on ARCH_CHIP_SAM4L
+	default y if DEBUG_SYMBOLS
+	default n if !DEBUG_SYMBOLS
+
+config SAM34_PARC
+	bool "Parallel Capture (PARC)"
 	default n
 	depends on ARCH_CHIP_SAM4L
 
-config SAM34_UART0
-	bool "UART 0"
-	default y
-	depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4S || ARCH_CHIP_SAM4E
-	select ARCH_HAVE_UART0
+config SAM34_PDCA
+	bool "Peripheral DMA controller (PDC)"
+	default n
+	depends on ARCH_CHIP_SAM4L || ARCH_CHIP_SAM4S || ARCH_CHIP_SAM4E
+	select ARCH_DMA
 
-config SAM34_UART1
-	bool "UART 1"
+config SAM34_PEVC
+	bool "Peripheral Event Controller"
 	default n
-	depends on ARCH_CHIP_SAM4S || ARCH_CHIP_SAM4E
-	select ARCH_HAVE_UART1
+	depends on ARCH_CHIP_SAM4L
+
+config SAM_PICOCACHE
+	bool "PicoCACHE"
+	default y
+	depends on ARCH_CHIP_SAM4L
 
 config SAM34_PICOUART
 	bool "PicoUART"
@@ -381,215 +424,177 @@ config SAM34_PICOUART
 	depends on ARCH_CHIP_SAM4L
 	select ARCH_HAVE_UART
 
-config SAM34_USART0
-	bool "USART 0"
+config SAM34_PWM
+	bool "Pulse Width Modulation (PWM) Controller"
 	default n
-	select ARCH_HAVE_USART0
+	depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4S || ARCH_CHIP_SAM4E
 
-config SAM34_USART1
-	bool "USART 1"
+config SAM34_RTC
+	bool "Real Time Clock (RTC)"
 	default n
-	select ARCH_HAVE_USART1
+	depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4S || ARCH_CHIP_SAM4E
 
-config SAM34_USART2
-	bool "USART 2"
+config SAM34_RTT
+	bool "Real Time Timer (RTT)"
 	default n
-	select ARCH_HAVE_USART2
-	depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4L
+	depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4S || ARCH_CHIP_SAM4E
 
-config SAM34_USART3
-	bool "USART 3"
+config SAM34_SDRAMC
+	bool "SDRAM Controller (SDRAMC)"
 	default n
-	select ARCH_HAVE_USART3
-	depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4L
+	depends on ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A
 
-config SAM34_ADC12B
-	bool "12-bit ADC Controller"
+config SAM34_SMC
+	bool "Static Memory Controller (SMC)"
 	default n
-	depends on !ARCH_CHIP_SAM4E
+	depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4S || ARCH_CHIP_SAM4E
 
-config SAM34_ADC
-	bool "10-bit ADC Controller"
+config SAM34_SPI0
+	bool "Serial Peripheral Interface 0 (SPI0)"
 	default n
-	depends on ARCH_CHIP_SAM3U
 
-config SAM34_AFEC0
-	bool "Analog Front End 0"
+config SAM34_SPI1
+	bool "Serial Peripheral Interface 1 (SPI1)"
 	default n
-	depends on ARCH_CHIP_SAM4E
+	depends on ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A
 
-config SAM34_AFEC1
-	bool "Analog Front End 1"
+config SAM34_SSC
+	bool "Synchronous Serial Controller (SSC)"
 	default n
-	depends on ARCH_CHIP_SAM4E
+	depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4S
 
-config SAM34_DACC
-	bool "Digital To Analog Converter (DAC)"
+config SAM34_TC0
+	bool "Timer/Counter 0 (TC0)"
 	default n
-	depends on ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4L || ARCH_CHIP_SAM4S || ARCH_CHIP_SAM4E
 
-config SAM34_ACC
-	bool "Analog Comparator (AC)"
+config SAM34_TC1
+	bool "Timer/Counter 1 (TC1)"
 	default n
-	depends on ARCH_CHIP_SAM4L || ARCH_CHIP_SAM4S || ARCH_CHIP_SAM4E
 
-config SAM34_GLOC
-	bool "GLOC"
+config SAM34_TC2
+	bool "Timer/Counter 2 (TC2)"
 	default n
-	depends on ARCH_CHIP_SAM4L
+	depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4S || ARCH_CHIP_SAM4E
 
-config SAM34_ABDACB
-	bool "Audio Bitstream DAC (ABDAC)"
+config SAM34_TC3
+	bool "Timer/Counter 3 (TC3)"
 	default n
-	depends on ARCH_CHIP_SAM4L
+	depends on ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4S || ARCH_CHIP_SAM4E
 
-config SAM34_TRNG
-	bool "True Random Number Generator (TRNG)"
+config SAM34_TC4
+	bool "Timer/Counter 4 (TC4)"
 	default n
-	depends on ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4L
+	depends on ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4S || ARCH_CHIP_SAM4E
 
-config SAM34_AES
-	bool "AES"
+config SAM34_TC5
+	bool "Timer/Counter 5 (TC5)"
 	default n
-	depends on ARCH_CHIP_SAM4E
+	depends on ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4S || ARCH_CHIP_SAM4E
 
-config SAM34_EMAC
-	bool "Ethernet MAC (EMAC)"
+config SAM34_TC6
+	bool "Timer/Counter 6 (TC6)"
 	default n
 	depends on ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4E
 
-config SAM34_CAN0
-	bool "CAN0"
+config SAM34_TC7
+	bool "Timer/Counter 7 (TC7)"
 	default n
 	depends on ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4E
 
-config SAM34_CAN1
-	bool "CAN1"
+config SAM34_TC8
+	bool "Timer/Counter 6 (TC8)"
 	default n
 	depends on ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4E
 
-config SAM34_PARC
-	bool "Parallel Capture (PARC)"
-	default n
-	depends on ARCH_CHIP_SAM4L
-
-config SAM34_CATB
-	bool "Capacitive Touch Module B (CATB)"
+config SAM34_TRNG
+	bool "True Random Number Generator (TRNG)"
 	default n
-	depends on ARCH_CHIP_SAM4L
+	depends on ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4L
 
-config SAM34_LCDCA
-	bool "LCD Controller A (LCDCA)"
+config SAM34_TWIM0
+	bool "Two-wire Master Interface 0 (TWIM0)"
 	default n
-	depends on ARCH_CHIP_SAM4L
 
-config SAM34_HRAMC1
-	bool "HRAMC1 (picoCache RAM)"
+config SAM34_TWIS0
+	bool "Two-wire Slave Interface 0 (TWIS0)"
 	default n
-	depends on ARCH_CHIP_SAM4L
 
-config SAM34_SMC
-	bool "Static Memory Controller (SMC)"
+config SAM34_TWIM1
+	bool "Two-wire Master Interface 1 (TWIM1)"
 	default n
-	depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4S || ARCH_CHIP_SAM4E
 
-config SAM34_SDRAMC
-	bool "SDRAM Controller (SDRAMC)"
+config SAM34_TWIS1
+	bool "Two-wire Slave Interface 1 (TWIS1)"
 	default n
-	depends on ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A
 
-config SAM34_NAND
-	bool "NAND support"
+config SAM34_TWIM2
+	bool "Two-wire Master Interface 2 (TWIM2)"
 	default n
-	depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM4E
+	depends on ARCH_CHIP_SAM4L
 
-config SAM34_HMATRIX
-	bool "HMATRIX"
+config SAM34_TWIM3
+	bool "Two-wire Master Interface 3 (TWIM3)"
 	default n
 	depends on ARCH_CHIP_SAM4L
 
-config SAM34_PDCA
-	bool "Peripheral DMA controller (PDC)"
-	default n
-	depends on ARCH_CHIP_SAM4L || ARCH_CHIP_SAM4S || ARCH_CHIP_SAM4E
-	select ARCH_DMA
+config SAM34_UART0
+	bool "UART 0"
+	default y
+	depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4S || ARCH_CHIP_SAM4E
+	select ARCH_HAVE_UART0
 
-config SAM34_DMAC
-	bool "DMA controller"
+config SAM34_UART1
+	bool "UART 1"
 	default n
-	depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4E
-	select ARCH_DMA
+	depends on ARCH_CHIP_SAM4S || ARCH_CHIP_SAM4E
+	select ARCH_HAVE_UART1
 
-config SAM34_CRCCU
-	bool "CRC Calculation Unit"
+config SAM34_UDP
+	bool "USB Device Full Speed (UDP)"
 	default n
-	depends on ARCH_CHIP_SAM4L || ARCH_CHIP_SAM4S
+	depends on ARCH_CHIP_SAM4S || ARCH_CHIP_SAM4E
 
 config SAM34_UDPHS
-	bool "USB Device High Speed"
+	bool "USB Device High Speed (UDPHS)"
 	default n
 	depends on ARCH_CHIP_SAM3U
 
 config SAM34_UOTGHS
-	bool "USB OTG High Speed"
+	bool "USB OTG High Speed (UOTGHS)"
 	default n
 	depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM3X
 
-config SAM34_UDP
-	bool "USB Device Full Speed"
-	default n
-	depends on ARCH_CHIP_SAM4S || ARCH_CHIP_SAM4E
-
 config SAM34_USBC
-	bool "USB 2.0 Interface"
-	default n
-	depends on ARCH_CHIP_SAM4L
-
-config SAM34_PEVC
-	bool "Peripheral Event Controller"
+	bool "USB 2.0 Interface (USBC)"
 	default n
 	depends on ARCH_CHIP_SAM4L
 
-config SAM34_CHIPID
-	bool "Chip ID"
-	default n
-	depends on ARCH_CHIP_SAM4L || ARCH_CHIP_SAM4E
-
-config SAM34_FREQM
-	bool "Frequency Meter (FREQM)"
+config SAM34_USART0
+	bool "USART 0"
 	default n
-	depends on ARCH_CHIP_SAM4L
+	select ARCH_HAVE_USART0
 
-config SAM34_AST
-	bool "Asynchronous Timer (AST)"
+config SAM34_USART1
+	bool "USART 1"
 	default n
-	depends on ARCH_CHIP_SAM4L
+	select ARCH_HAVE_USART1
 
-config SAM34_RTC
-	bool "Real Time Clock (RTC)"
+config SAM34_USART2
+	bool "USART 2"
 	default n
-	depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4S || ARCH_CHIP_SAM4E
+	select ARCH_HAVE_USART2
+	depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4L
 
-config SAM34_RTT
-	bool "Real Time Timer (RTT)"
+config SAM34_USART3
+	bool "USART 3"
 	default n
-	depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4S || ARCH_CHIP_SAM4E
+	select ARCH_HAVE_USART3
+	depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4L
 
 config SAM34_WDT
 	bool "Watchdog Timer (WDT)"
 	default n
 
-config SAM34_EIC
-	bool "External Interrupt Controller (EIC)"
-	default n
-	depends on ARCH_CHIP_SAM4L || ARCH_CHIP_SAM4E
-
-config SAM34_HSMCI
-	bool "High Speed Multimedia Card Interface (HSMCI)"
-	default n
-	depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4S || ARCH_CHIP_SAM4E
-	select ARCH_HAVE_SDIO
-
 endmenu # AT91SAM3/4 Peripheral Support
 
 if ARCH_CHIP_SAM4L
diff --git a/nuttx/arch/arm/src/sam34/Make.defs b/nuttx/arch/arm/src/sam34/Make.defs
index 3e8fe88fe..0fe0d5b56 100644
--- a/nuttx/arch/arm/src/sam34/Make.defs
+++ b/nuttx/arch/arm/src/sam34/Make.defs
@@ -92,6 +92,10 @@ ifeq ($(CONFIG_NUTTX_KERNEL),y)
 CHIP_CSRCS += sam_userspace.c sam_mpuinit.c
 endif
 
+ifeq ($(CONFIG_SAM34_CMCC),y)
+CHIP_CSRCS += sam_cmcc.c
+endif
+
 ifeq ($(CONFIG_SAM34_DMAC),y)
 CHIP_CSRCS += sam_dmac.c
 endif
diff --git a/nuttx/arch/arm/src/sam34/chip/sam_cmcc.h b/nuttx/arch/arm/src/sam34/chip/sam_cmcc.h
index 1f7e14dba..440ea72c1 100644
--- a/nuttx/arch/arm/src/sam34/chip/sam_cmcc.h
+++ b/nuttx/arch/arm/src/sam34/chip/sam_cmcc.h
@@ -49,6 +49,15 @@
 /****************************************************************************************
  * Pre-processor Definitions
  ****************************************************************************************/
+/* This information is available in the Cache Type Register.  How every, it is more
+ * efficient if we do not to do the decoding on each cache access.
+ */
+
+#ifdef CONFIG_ARCH_CHIP_SAM4E
+#  define CMCC_CACHE_SIZE            2048
+#  define CMCC_CACHE_LINE_SIZE       16
+#  define CMCC_NWAYS                 4
+#endif
 
 /* CMCC register offsets ****************************************************************/
 
@@ -100,7 +109,7 @@
 #  define CMCC_TYPE_CSIZE_2KB        (1 << CMCC_TYPE_CSIZE_SHIFT) /* Cache Size 2 Kbytes */
 #  define CMCC_TYPE_CSIZE_4KB        (2 << CMCC_TYPE_CSIZE_SHIFT) /* Cache Size 4 Kbytes */
 #  define CMCC_TYPE_CSIZE_8KB        (3 << CMCC_TYPE_CSIZE_SHIFT) /* Cache Size 8 Kbytes */
-#define CMCC_TYPE_CLSIZE_SHIFT       (11)      /* Bits 11-13: Cache Size */
+#define CMCC_TYPE_CLSIZE_SHIFT       (11)      /* Bits 11-13: Cache Line Size */
 #define CMCC_TYPE_CLSIZE_MASK        (7 << CMCC_TYPE_CLSIZE_SHIFT)
 #  define CMCC_TYPE_CLSIZE_4B        (0 << CMCC_TYPE_CLSIZE_SHIFT) /* 4 Bytes */
 #  define CMCC_TYPE_CLSIZE_8B        (1 << CMCC_TYPE_CLSIZE_SHIFT) /* 8 Bytes */
@@ -130,6 +139,7 @@
 #  define CMCC_MAINT1_INDEX(n)       ((uint32_t)(n) << CMCC_MAINT1_INDEX_SHIFT)
 #define CMCC_MAINT1_WAY_SHIFT        (30)      /* Bits 30-31: Invalidate Way */
 #define CMCC_MAINT1_WAY_MASK         (3 << CMCC_MAINT1_WAY_SHIFT)
+#  define CMCC_MAINT1_WAY(n)         ((uint32_t)(n) << CMCC_MAINT1_WAY_SHIFT)
 #  define CMCC_MAINT1_WAY0           (0 << CMCC_MAINT1_WAY_SHIFT) /* Way 0 selected */
 #  define CMCC_MAINT1_WAY1           (1 << CMCC_MAINT1_WAY_SHIFT) /* Way 1 selected */
 #  define CMCC_MAINT1_WAY2           (2 << CMCC_MAINT1_WAY_SHIFT) /* Way 2 selected */
diff --git a/nuttx/arch/arm/src/sam34/sam_cmcc.c b/nuttx/arch/arm/src/sam34/sam_cmcc.c
new file mode 100644
index 000000000..9b7ef0725
--- /dev/null
+++ b/nuttx/arch/arm/src/sam34/sam_cmcc.c
@@ -0,0 +1,211 @@
+/****************************************************************************
+ * arch/arm/src/sam34/sam_cmcc.c
+ *
+ *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <assert.h>
+
+#include "up_arch.h"
+#include "chip/sam_cmcc.h"
+#include "sam_cmcc.h"
+
+#ifdef CONFIG_SAM34_CMCC
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define CMCC_MASK     (CMCC_CACHE_LINE_SIZE-1)
+
+#if CMCC_CACHE_LINE_SIZE == 4
+#  define CMCC_SHIFT   2
+#elif CMCC_CACHE_LINE_SIZE == 8
+#  define CMCC_SHIFT   3
+#elif CMCC_CACHE_LINE_SIZE == 16
+#  define CMCC_SHIFT   4
+#elif CMCC_CACHE_LINE_SIZE == 32
+#  define CMCC_SHIFT   5
+#else
+#  error Unknown cache line size
+#endif
+
+#define ALIGN_UP(a)   (((a)+CMCC_MASK) & ~CMCC_MASK)
+#define ALIGN_DOWN(a) ((a) & ~CMCC_MASK)
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: sam_cmcc_enable
+ *
+ * Description:
+ *   Enable the Cortex-M Cache Controller
+ *
+ ****************************************************************************/
+
+void sam_cmcc_enable(void)
+{
+  /* "On reset, the cache controller data entries are all invalidated and the
+   *  cache is disabled. The cache is transparent to processor operations. The
+   *  cache controller is activated with its configuration registers. The
+   *  configuration interface is memory mapped in the private peripheral bus.
+   *
+   * "Use the following sequence to enable the cache controller.
+   *
+   * "1. Verify that the cache controller is disabled, reading the value of the
+   *     CSTS (cache status) field of the CMCC_SR register.
+   * "2. Enable the cache controller, writing 1 to the CEN (cache enable) field
+   *    of the CMCC_CTRL register."
+   */
+
+  if ((getreg32(SAM_CMCC_SR) & CMCC_SR_CSTS) == 0)
+    {
+      putreg32(CMCC_CTRL_CEN, SAM_CMCC_CTRL);
+    }
+}
+
+/****************************************************************************
+ * Name: sam_cmcc_disable
+ *
+ * Description:
+ *   Disable the Cortex-M Cache Controller
+ *
+ ****************************************************************************/
+
+void sam_cmcc_disable(void)
+{
+  /* "1. Disable the cache controller, writing 0 to the CEN field of the
+   *     CMCC_CTRL register.
+   * "2. Check CSTS field of the CMCC_SR to verify that the cache is
+   *     successfully disabled.
+   */
+
+  putreg32(0, SAM_CMCC_CTRL);
+  while ((getreg32(SAM_CMCC_SR) & CMCC_SR_CSTS) != 0);
+}
+
+/****************************************************************************
+ * Name: sam_cmcc_invalidate
+ *
+ * Description:
+ *   Invalidate a range of addresses.  Note:  These addresses should be
+ *   aligned with the beginning and end of cache lines.  Otherwise, values
+ *   at the edges of the region will also be invalidated!
+ *
+ ****************************************************************************/
+
+void sam_cmcc_invalidate(uintptr_t start, uintptr_t end)
+{
+  uintptr_t addr;
+  uint32_t regval;
+  uint32_t way
+  uint32_t index;
+  int nlines;
+
+  /* "When an invalidate by line command is issued the cache controller resets
+   *  the valid bit information of the decoded cache line. As the line is no
+   *  longer valid the replacement counter points to that line.
+   *
+   * "Use the following sequence to invalidate one line of cache.
+   *
+   * "1. Disable the cache controller, writing 0 to the CEN field of the
+   *     CMCC_CTRL register.
+   * "2. Check CSTS field of the CMCC_SR to verify that the cache is
+   *     successfully disabled.
+   * "3. Perform an invalidate by line writing the bit set {index, way} in
+   *     the CMCC_MAINT1 register.
+   * "4. Enable the cache controller, writing 1 to the CEN field of the
+   *     CMCC_CTRL register."
+   */
+
+  /* Disable the cache controller */
+
+  sam_cmcc_disable();
+
+  /* Invalidate the address region */
+
+  start  = ALIGN_DOWN(start);
+  end    = ALIGN_up(end);
+
+  index  = (start >> CMCC_SHIFT)
+  nlines = ((end - start) >> CMCC_SHIFT);
+
+  for (addr = start; addr < end; addr += CMCC_CACHE_LINE_SIZE, index++)
+    {
+      regval = CMCC_MAINT1_INDEX(index);
+      for (way = 0; way < CMCC_NWAYS; way++)
+        {
+          putreg32(regval | CMCC_MAINT1_WAY(way), SAM_CMCC_MAINT1);
+        }
+    }
+
+  /* Re-enable the cache controller */
+
+  sam_cmcc_enable();
+}
+
+/****************************************************************************
+ * Name: sam_cmcc_invalidateall
+ *
+ * Description:
+ *   Invalidate the entire cache
+ *
+ ****************************************************************************/
+
+void sam_cmcc_invalidateall(void)
+{
+  /* "To invalidate all cache entries:
+   *
+   * " Write 1 to the INVALL field of the CMCC_MAINT0 register."
+   */
+
+  putreg32(CMCC_MAINT0_INVALL, SAM_CMCC_MAINT0);
+}
+
+#endif /* CONFIG_SAM34_CMCC */
diff --git a/nuttx/arch/arm/src/sam34/sam_cmcc.h b/nuttx/arch/arm/src/sam34/sam_cmcc.h
new file mode 100644
index 000000000..6b7f17ca5
--- /dev/null
+++ b/nuttx/arch/arm/src/sam34/sam_cmcc.h
@@ -0,0 +1,129 @@
+/************************************************************************************
+ * arch/arm/src/sam34/sam_cmcc.h
+ *
+ *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_SAM34_SAM_CMCC_H
+#define __ARCH_ARM_SRC_SAM34_SAM_CMCC_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+
+#ifdef CONFIG_SAM34_CMCC
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Inline Functions
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/************************************************************************************
+ * Public Function Prototypes
+ ************************************************************************************/
+
+/****************************************************************************
+ * Name: sam_cmcc_enable
+ *
+ * Description:
+ *   Enable the Cortex-M Cache Controller
+ *
+ ****************************************************************************/
+
+void sam_cmcc_enable(void);
+
+/****************************************************************************
+ * Name: sam_cmcc_disable
+ *
+ * Description:
+ *   Disable the Cortex-M Cache Controller
+ *
+ ****************************************************************************/
+
+void sam_cmcc_disable(void);
+
+/****************************************************************************
+ * Name: sam_cmcc_invalidate
+ *
+ * Description:
+ *   Invalidate a range of addresses.  Note:  These addresses should be
+ *   aligned with the beginning and end of cache lines.  Otherwise, values
+ *   at the edges of the region will also be invalidated!
+ *
+ ****************************************************************************/
+
+void sam_cmcc_invalidate(uintptr_t start, uintptr_t end);
+
+/****************************************************************************
+ * Name: sam_cmcc_invalidateall
+ *
+ * Description:
+ *   Invalidate the entire cache
+ *
+ ****************************************************************************/
+
+void sam_cmcc_invalidateall(void);
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* CONFIG_SAM34_CMCC */
+#endif /* __ARCH_ARM_SRC_SAM34_SAM_CMCC_H */
diff --git a/nuttx/arch/arm/src/sam34/sam_start.c b/nuttx/arch/arm/src/sam34/sam_start.c
index 0e1ead766..501c386dd 100644
--- a/nuttx/arch/arm/src/sam34/sam_start.c
+++ b/nuttx/arch/arm/src/sam34/sam_start.c
@@ -171,6 +171,17 @@ void __start(void)
   sam_boardinitialize();
   showprogress('D');
 
+#ifdef CONFIG_SAM34_CMCC
+  /* Enable the Cortex-M Cache
+   *
+   * REVISIT:  This logic is complete but I have not yet tried to enable it.
+   * I have some questions about how the cache will effect memory mapped
+   * register accesses.
+   */
+
+  sam_cmcc_enable();
+#endif
+
   /* Then start NuttX */
 
   showprogress('\r');