LPC2378: SPI driver from Lizhuoyi

7 files changed, 838 insertions, 48 deletions

diff --git a/nuttx/arch/arm/src/lpc2378/Kconfig b/nuttx/arch/arm/src/lpc2378/Kconfig
index c3d5a0036..8425d2db5 100644
--- a/nuttx/arch/arm/src/lpc2378/Kconfig
+++ b/nuttx/arch/arm/src/lpc2378/Kconfig
@@ -150,6 +150,11 @@ config LPC2378_IC2
 	default n
 	select I2C
 
+config LPC2378_SPI
+	bool "SPI"
+	default n
+	select SPI
+
 endmenu
 
 if LPC2378_USBDEV
diff --git a/nuttx/arch/arm/src/lpc2378/Make.defs b/nuttx/arch/arm/src/lpc2378/Make.defs
index a245bc98a..5c4d282ee 100644
--- a/nuttx/arch/arm/src/lpc2378/Make.defs
+++ b/nuttx/arch/arm/src/lpc2378/Make.defs
@@ -38,31 +38,38 @@
 #
 ##############################################################################
 
-HEAD_ASRC	= lpc23xx_head.S
+HEAD_ASRC = lpc23xx_head.S
 
-CMN_ASRCS	= up_saveusercontext.S up_fullcontextrestore.S up_vectors.S \
-			  vfork.S
-CMN_CSRCS	= up_allocateheap.c up_assert.c up_blocktask.c up_copyfullstate.c \
-			  up_createstack.c up_dataabort.c up_mdelay.c up_udelay.c \
-			  up_exit.c up_idle.c up_initialize.c up_initialstate.c \
-			  up_interruptcontext.c up_prefetchabort.c up_releasepending.c \
-			  up_releasestack.c up_reprioritizertr.c up_syscall.c up_unblocktask.c \
-			  up_undefinedinsn.c up_usestack.c up_lowputs.c up_vfork.c
+CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_vectors.S \
+   vfork.S
+CMN_CSRCS = up_allocateheap.c up_assert.c up_blocktask.c up_copyfullstate.c \
+   up_createstack.c up_dataabort.c up_mdelay.c up_udelay.c \
+   up_exit.c up_idle.c up_initialize.c up_initialstate.c \
+   up_interruptcontext.c up_prefetchabort.c up_releasepending.c \
+   up_releasestack.c up_reprioritizertr.c up_syscall.c up_unblocktask.c \
+   up_undefinedinsn.c up_usestack.c up_lowputs.c up_vfork.c
 
 ifneq ($(CONFIG_DISABLE_SIGNALS),y)
-CMN_CSRCS	+= up_schedulesigaction.c up_sigdeliver.c
+CMN_CSRCS += up_schedulesigaction.c up_sigdeliver.c
 endif
 
 ifeq ($(CONFIG_ELF),y)
 CMN_CSRCS += up_elf.c
 endif
 
-CHIP_ASRCS	= lpc23xx_lowputc.S
-CHIP_CSRCS	= lpc23xx_pllsetup.c  lpc23xx_decodeirq.c lpc23xx_irq.c lpc23xx_timerisr.c \
-			  lpc23xx_serial.c lpc23xx_io.c
-		  
+CHIP_ASRCS = lpc23xx_lowputc.S
+CHIP_CSRCS = lpc23xx_pllsetup.c  lpc23xx_decodeirq.c lpc23xx_irq.c lpc23xx_timerisr.c \
+   lpc23xx_serial.c lpc23xx_io.c
+
+ifeq ($(CONFIG_LPC2378_SPI),y)
+CHIP_CSRCS += lpc23xx_spi.c
+endif
+
+ifeq ($(CONFIG_I2C),y)
+CHIP_CSRCS += lpc23xx_i2c.c
+endif
 
 ifeq ($(CONFIG_USBDEV),y)
-#CHIP_CSRCS	+= lpc23xx_usbdev.c
+#CHIP_CSRCS += lpc23xx_usbdev.c
 endif
 
diff --git a/nuttx/arch/arm/src/lpc2378/lpc23xx_i2c.c b/nuttx/arch/arm/src/lpc2378/lpc23xx_i2c.c
index a94deb03a..7d401a9fd 100644
--- a/nuttx/arch/arm/src/lpc2378/lpc23xx_i2c.c
+++ b/nuttx/arch/arm/src/lpc2378/lpc23xx_i2c.c
@@ -14,7 +14,7 @@
  *
  *   Author: David Hewson
  *
- *   Copyright (C) 2010-2011 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2010-2011, 2014 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
  *
  * Redistribution and use in source and binary forms, with or without
diff --git a/nuttx/arch/arm/src/lpc2378/lpc23xx_i2c.h b/nuttx/arch/arm/src/lpc2378/lpc23xx_i2c.h
index 62b928b90..c0f33660f 100644
--- a/nuttx/arch/arm/src/lpc2378/lpc23xx_i2c.h
+++ b/nuttx/arch/arm/src/lpc2378/lpc23xx_i2c.h
@@ -6,7 +6,7 @@
  *
  * Derived arch/arm/src/lpc17xx/lpc17_i2c.h
  *
- *   Copyright (C) 2010 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2010, 2014 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
  *
  * Redistribution and use in source and binary forms, with or without
diff --git a/nuttx/arch/arm/src/lpc2378/lpc23xx_spi.c b/nuttx/arch/arm/src/lpc2378/lpc23xx_spi.c
new file mode 100644
index 000000000..f0e48d3d2
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc2378/lpc23xx_spi.c
@@ -0,0 +1,620 @@
+/****************************************************************************
+ * arch/arm/src/lpc2378/lpc23xx_spi.c
+ *
+ *   Copyright (C) 2013 Li Zhuoyi. All rights reserved.
+ *   Author: Li Zhuoyi <lzyy.cn@gmail.com>
+ *
+ * Derived from  arch/arm/src/lpc17xx/lpc17_spi.c
+ *
+ *   Copyright (C) 2010, 2012, 2014 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <semaphore.h>
+#include <errno.h>
+#include <debug.h>
+
+#include <arch/board/board.h>
+#include <nuttx/arch.h>
+#include <nuttx/spi/spi.h>
+
+#include "up_internal.h"
+#include "up_arch.h"
+
+#include "chip.h"
+#include "lpc23xx_pinsel.h"
+#include "lpc23xx_scb.h"
+#include "lpc23xx_spi.h"
+
+#ifdef CONFIG_LPC2378_SPI
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+/* Configuration ************************************************************/
+
+#ifdef CONFIG_SPI_EXCHANGE
+#  error CONFIG_SPI_EXCHANGE is not supported by this driver
+#endif
+
+/* Debug ********************************************************************/
+/* CONFIG_DEBUG_SPI enables debug output from this file */
+
+#ifdef CONFIG_DEBUG_SPI
+#  define spidbg  lldbg
+#  ifdef CONFIG_DEBUG_VERBOSE
+#    define spivdbg lldbg
+#  else
+#    define spivdbg(x...)
+#  endif
+#else
+#  define spidbg(x...)
+#  define spivdbg(x...)
+#endif
+
+/* SPI Clocking.
+ *
+ * The CPU clock is divided by by 1, 2, 4, or 8 to get the SPI peripheral
+ * clock (SPI_CLOCK).  SPI_CLOCK may be further divided by 8-254 to get the
+ * SPI clock.  If we want a usable range of 4KHz to 25MHz for the SPI, then:
+ *
+ * 1. SPICLK must be greater than (8*25MHz) = 200MHz (so we can't reach 25MHz),
+ *    and
+ * 2. SPICLK must be less than (254*40Khz) = 101.6MHz.
+ *
+ * If we assume that CCLK less than or equal to 100MHz, we can just
+ * use the CCLK undivided to get the SPI_CLOCK.
+ *
+ * NOTE: CCLK must be defined in the board.h header file.
+ */
+
+#define SPI_PCLKSET_DIV    SYSCON_PCLKSEL_CCLK
+#define SPI_CLOCK          CCLK
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/* This structure describes the state of the SSP driver */
+
+struct lpc23xx_spidev_s
+{
+  struct spi_dev_s spidev;     /* Externally visible part of the SPI interface */
+#ifndef CONFIG_SPI_OWNBUS
+  sem_t            exclsem;    /* Held while chip is selected for mutual exclusion */
+  uint32_t         frequency;  /* Requested clock frequency */
+  uint32_t         actual;     /* Actual clock frequency */
+  uint8_t          nbits;      /* Width of word in bits (8 to 16) */
+  uint8_t          mode;       /* Mode 0,1,2,3 */
+#endif
+};
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/* SPI methods */
+
+#ifndef CONFIG_SPI_OWNBUS
+static int      spi_lock(FAR struct spi_dev_s *dev, bool lock);
+#endif
+static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency);
+static void     spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode);
+static void     spi_setbits(FAR struct spi_dev_s *dev, int nbits);
+static uint16_t spi_send(FAR struct spi_dev_s *dev, uint16_t ch);
+static void     spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size_t nwords);
+static void     spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nwords);
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static const struct spi_ops_s g_spiops =
+{
+#ifndef CONFIG_SPI_OWNBUS
+  .lock              = spi_lock,
+#endif
+  .select            = lpc23xx_spiselect,   /* Provided externally */
+  .setfrequency      = spi_setfrequency,
+  .setmode           = spi_setmode,
+  .setbits           = spi_setbits,
+  .status            = lpc23xx_spistatus,
+#ifdef CONFIG_SPI_CMDDATA
+  .cmddata           = lpc23xx_spicmddata,
+#endif
+  .send              = spi_send,
+  .sndblock          = spi_sndblock,
+  .recvblock         = spi_recvblock,
+#ifdef CONFIG_SPI_CALLBACK
+  .registercallback  = lpc23xx_spiregister, /* Provided externally */
+#else
+  .registercallback  = 0,                   /* Not implemented */
+#endif
+};
+
+static struct lpc23xx_spidev_s g_spidev =
+{
+  .spidev            = { &g_spiops },
+};
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: spi_lock
+ *
+ * Description:
+ *   On SPI buses where there are multiple devices, it will be necessary to
+ *   lock SPI to have exclusive access to the buses for a sequence of
+ *   transfers.  The bus should be locked before the chip is selected. After
+ *   locking the SPI bus, the caller should then also call the setfrequency,
+ *   setbits, and setmode methods to make sure that the SPI is properly
+ *   configured for the device.  If the SPI bus is being shared, then it
+ *   may have been left in an incompatible state.
+ *
+ * Input Parameters:
+ *   dev  - Device-specific state data
+ *   lock - true: Lock spi bus, false: unlock SPI bus
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+#ifndef CONFIG_SPI_OWNBUS
+static int spi_lock(FAR struct spi_dev_s *dev, bool lock)
+{
+  FAR struct lpc23xx_spidev_s *priv = (FAR struct lpc23xx_spidev_s *)dev;
+
+  if (lock)
+    {
+      /* Take the semaphore (perhaps waiting) */
+
+      while (sem_wait(&priv->exclsem) != 0)
+        {
+          /* The only case that an error should occur here is if the wait was awakened
+           * by a signal.
+           */
+
+          ASSERT(errno == EINTR);
+        }
+    }
+  else
+    {
+      (void)sem_post(&priv->exclsem);
+    }
+
+  return OK;
+}
+#endif
+
+/****************************************************************************
+ * Name: spi_setfrequency
+ *
+ * Description:
+ *   Set the SPI frequency.
+ *
+ * Input Parameters:
+ *   dev -       Device-specific state data
+ *   frequency - The SPI frequency requested
+ *
+ * Returned Value:
+ *   Returns the actual frequency selected
+ *
+ ****************************************************************************/
+
+static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency)
+{
+  FAR struct lpc23xx_spidev_s *priv = (FAR struct lpc23xx_spidev_s *)dev;
+  uint32_t divisor;
+  uint32_t actual;
+
+  /* Check if the requested frequence is the same as the frequency selection */
+
+  DEBUGASSERT(priv && frequency <= SPI_CLOCK / 2);
+#ifndef CONFIG_SPI_OWNBUS
+  if (priv->frequency == frequency)
+    {
+      /* We are already at this frequency.  Return the actual. */
+
+      return priv->actual;
+    }
+#endif
+
+  /* frequency = SPI_CLOCK / divisor, or divisor = SPI_CLOCK / frequency */
+
+  divisor = SPI_CLOCK / frequency;
+
+  /* The SPI CCR register must contain an even number greater than or equal to 8. */
+
+  if (divisor < 8)
+    {
+      divisor = 8;
+    }
+  else if (divisor > 254)
+    {
+      divisor = 254;
+    }
+
+  divisor = (divisor + 1) & ~1;
+
+  /* Save the new divisor value */
+
+  putreg32(divisor, SPI_CCR);
+
+  /* Calculate the new actual */
+
+  actual = SPI_CLOCK / divisor;
+
+  /* Save the frequency setting */
+
+#ifndef CONFIG_SPI_OWNBUS
+  priv->frequency = frequency;
+  priv->actual    = actual;
+#endif
+
+  spidbg("Frequency %d->%d\n", frequency, actual);
+  return actual;
+}
+
+/****************************************************************************
+ * Name: spi_setmode
+ *
+ * Description:
+ *   Set the SPI mode. Optional.  See enum spi_mode_e for mode definitions
+ *
+ * Input Parameters:
+ *   dev -  Device-specific state data
+ *   mode - The SPI mode requested
+ *
+ * Returned Value:
+ *   none
+ *
+ ****************************************************************************/
+
+static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)
+{
+  FAR struct lpc23xx_spidev_s *priv = (FAR struct lpc23xx_spidev_s *)dev;
+  uint32_t regval;
+
+  /* Has the mode changed? */
+
+#ifndef CONFIG_SPI_OWNBUS
+  if (mode != priv->mode)
+    {
+#endif
+      /* Yes... Set CR appropriately */
+
+      regval = getreg32(SPI_CR);
+      regval &= ~(SPI_CR_CPOL|SPI_CR_CPHA);
+
+      switch (mode)
+        {
+          case SPIDEV_MODE0: /* CPOL=0; CPHA=0 */
+            break;
+
+          case SPIDEV_MODE1: /* CPOL=0; CPHA=1 */
+            regval |= SPI_CR_CPHA;
+            break;
+
+          case SPIDEV_MODE2: /* CPOL=1; CPHA=0 */
+            regval |= SPI_CR_CPOL;
+            break;
+
+          case SPIDEV_MODE3: /* CPOL=1; CPHA=1 */
+            regval |= (SPI_CR_CPOL|SPI_CR_CPHA);
+            break;
+
+          default:
+            DEBUGASSERT(FALSE);
+            return;
+        }
+
+      putreg32(regval, SPI_CR);
+
+      /* Save the mode so that subsequent re-configuratins will be faster */
+
+#ifndef CONFIG_SPI_OWNBUS
+      priv->mode = mode;
+    }
+#endif
+}
+
+/****************************************************************************
+ * Name: spi_setbits
+ *
+ * Description:
+ *   Set the number if bits per word.
+ *
+ * Input Parameters:
+ *   dev -  Device-specific state data
+ *   nbits - The number of bits requests
+ *
+ * Returned Value:
+ *   none
+ *
+ ****************************************************************************/
+
+static void spi_setbits(FAR struct spi_dev_s *dev, int nbits)
+{
+  FAR struct lpc23xx_spidev_s *priv = (FAR struct lpc23xx_spidev_s *)dev;
+  uint32_t regval;
+
+  /* Has the number of bits changed? */
+
+  DEBUGASSERT(priv && nbits > 7 && nbits < 17);
+
+#ifndef CONFIG_SPI_OWNBUS
+  if (nbits != priv->nbits)
+    {
+#endif
+      /* Yes... Set CR appropriately */
+
+      regval = getreg32(SPI_CR);
+      regval &= ~SPI_CR_BITS_MASK;
+      regval |= (nbits << SPI_CR_BITS_SHIFT) & SPI_CR_BITS_MASK;
+      regval |= SPI_CR_BITENABLE;
+      regval = getreg32(SPI_CR);
+
+      /* Save the selection so the subsequence re-configurations will be faster */
+
+#ifndef CONFIG_SPI_OWNBUS
+      priv->nbits = nbits;
+    }
+#endif
+}
+
+/****************************************************************************
+ * Name: spi_send
+ *
+ * Description:
+ *   Exchange one word on SPI
+ *
+ * Input Parameters:
+ *   dev - Device-specific state data
+ *   wd  - The word to send.  the size of the data is determined by the
+ *         number of bits selected for the SPI interface.
+ *
+ * Returned Value:
+ *   response
+ *
+ ****************************************************************************/
+
+static uint16_t spi_send(FAR struct spi_dev_s *dev, uint16_t wd)
+{
+  /* Write the data to transmitted to the SPI Data Register */
+
+  putreg32((uint32_t)wd, SPI_DR);
+
+  /* Wait for the SPIF bit in the SPI Status Register to be set to 1. The
+   * SPIF bit will be set after the last sampling clock edge of the SPI
+   * data transfer.
+   */
+
+  while ((getreg32(SPI_SR) & SPI_SR_SPIF) == 0);
+
+  /* Read the SPI Status Register again to clear the status bit */
+
+  (void)getreg32(SPI_SR);
+  return (uint16_t)getreg32(SPI_DR);
+}
+
+/*************************************************************************
+ * Name: spi_sndblock
+ *
+ * Description:
+ *   Send a block of data on SPI
+ *
+ * Input Parameters:
+ *   dev -    Device-specific state data
+ *   buffer - A pointer to the buffer of data to be sent
+ *   nwords - the length of data to send from the buffer in number of words.
+ *            The wordsize is determined by the number of bits-per-word
+ *            selected for the SPI interface.  If nbits <= 8, the data is
+ *            packed into uint8_t's; if nbits >8, the data is packed into uint16_t's
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size_t nwords)
+{
+  FAR uint8_t *ptr = (FAR uint8_t*)buffer;
+  uint8_t data;
+
+  spidbg("nwords: %d\n", nwords);
+  while (nwords)
+    {
+      /* Write the data to transmitted to the SPI Data Register */
+
+      data = *ptr++;
+      putreg32((uint32_t)data, SPI_DR);
+
+      /* Wait for the SPIF bit in the SPI Status Register to be set to 1. The
+       * SPIF bit will be set after the last sampling clock edge of the SPI
+       * data transfer.
+       */
+
+      while ((getreg32(SPI_SR) & SPI_SR_SPIF) == 0);
+
+      /* Read the SPI Status Register again to clear the status bit */
+
+      (void)getreg32(SPI_SR);
+      nwords--;
+    }
+}
+
+/****************************************************************************
+ * Name: spi_recvblock
+ *
+ * Description:
+ *   Revice a block of data from SPI
+ *
+ * Input Parameters:
+ *   dev -    Device-specific state data
+ *   buffer - A pointer to the buffer in which to receive data
+ *   nwords - the length of data that can be received in the buffer in number
+ *            of words.  The wordsize is determined by the number of bits-per-word
+ *            selected for the SPI interface.  If nbits <= 8, the data is
+ *            packed into uint8_t's; if nbits >8, the data is packed into uint16_t's
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nwords)
+{
+  FAR uint8_t *ptr = (FAR uint8_t*)buffer;
+
+  spidbg("nwords: %d\n", nwords);
+  while (nwords)
+    {
+      /* Write some dummy data to the SPI Data Register in order to clock the
+       * read data.
+       */
+
+      putreg32(0xff, SPI_DR);
+
+      /* Wait for the SPIF bit in the SPI Status Register to be set to 1. The
+       * SPIF bit will be set after the last sampling clock edge of the SPI
+       * data transfer.
+       */
+
+      while ((getreg32(SPI_SR) & SPI_SR_SPIF) == 0);
+
+      /* Read the SPI Status Register again to clear the status bit */
+
+      (void)getreg32(SPI_SR);
+
+      /* Read the received data from the SPI Data Register */
+
+      *ptr++ = (uint8_t)getreg32(SPI_DR);
+      nwords--;
+    }
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_spiinitialize
+ *
+ * Description:
+ *   Initialize the selected SPI port
+ *
+ * Input Parameter:
+ *   Port number (for hardware that has multiple SPI interfaces)
+ *
+ * Returned Value:
+ *   Valid SPI device structure reference on success; a NULL on failure
+ *
+ ****************************************************************************/
+
+FAR struct spi_dev_s *up_spiinitialize(int port)
+{
+  FAR struct lpc23xx_spidev_s *priv = &g_spidev;
+  irqstate_t flags;
+  uint32_t regval;
+
+  /* Configure multiplexed pins as connected on the board.  Chip select
+   * pins must be configured by board-specific logic.  All SPI pins and
+   * one SPI1 pin (SCK) have multiple, alternative pin selection.
+   * Definitions in the board.h file must be provided to resolve the
+   * board-specific pin configuration like:
+   *
+   * #define GPIO_SPI_SCK GPIO_SPI_SCK_1
+   */
+
+  flags = irqsave();
+
+  regval  = getreg32(LPC23XX_SCB_BASE+SCB_PCONP_OFFSET);
+  regval |= PCSPI;
+  putreg32(regval, LPC23XX_SCB_BASE+SCB_PCONP_OFFSET);
+
+  regval  = getreg32(LPC23XX_SCB_BASE+SCB_PCLKSEL0_OFFSET);
+  regval &= ~SPI_PCLKSEL_MASK;
+  regval |= SPI_PCLKSEL;
+  putreg32(regval, LPC23XX_SCB_BASE+SCB_PCLKSEL0_OFFSET);
+
+  regval  = getreg32(LPC23XX_PINSEL0);
+  regval &= ~SPI_PINSEL0_MASK ;
+  regval |= SPI_PINSEL0;
+  putreg32(regval, LPC23XX_PINSEL0);
+
+  regval  = getreg32(LPC23XX_PINSEL1);
+  regval &= ~SPI_PINSEL1_MASK ;
+  regval |= SPI_PINSEL1;
+  putreg32(regval, LPC23XX_PINSEL1);
+
+  irqrestore(flags);
+
+  /* Configure 8-bit SPI mode and master mode */
+
+  putreg32(SPI_CR_BITS_8BITS|SPI_CR_BITENABLE|SPI_CR_MSTR, SPI_CR);
+
+  /* Set the initial SPI configuration */
+
+#ifndef CONFIG_SPI_OWNBUS
+  priv->frequency = 0;
+  priv->nbits     = 8;
+  priv->mode      = SPIDEV_MODE0;
+#endif
+
+  /* Select a default frequency of approx. 400KHz */
+
+  spi_setfrequency((FAR struct spi_dev_s *)priv, 400000);
+
+  /* Initialize the SPI semaphore that enforces mutually exclusive access */
+
+#ifndef CONFIG_SPI_OWNBUS
+  sem_init(&priv->exclsem, 0, 1);
+#endif
+  return &priv->spidev;
+}
+
+#endif /* CONFIG_LPC2378_SPI */
diff --git a/nuttx/arch/arm/src/lpc2378/lpc23xx_spi.h b/nuttx/arch/arm/src/lpc2378/lpc23xx_spi.h
new file mode 100644
index 000000000..d6a80b692
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc2378/lpc23xx_spi.h
@@ -0,0 +1,163 @@
+/************************************************************************************
+ * arch/arm/src/lpc2378/lpc23xx_spi.h
+ *
+ *   Copyright (C) 2013 Li Zhuoyi. All rights reserved.
+ *   Author: Li Zhuoyi <lzyy.cn@gmail.com>
+ *
+ * Derived arch/arm/src/lpc17xx/lpc17_spi.h
+ *
+ *   Copyright (C) 2010, 2014 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LPC2378_LPC23XX_SPI_H
+#define __ARCH_ARM_SRC_LPC2378_LPC23XX_SPI_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "chip.h"
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+/* SPI Pin Configuration ************************************************************/
+
+#define SPI_BASE             SPI0_BASE_ADDR
+
+#define SPI_PCLKSEL_MASK     (0x03 << 16)
+#define SPI_PCLKSEL          (0x01 << 16)
+
+#define SPI_PINSEL0_MASK     (0x03 << 30)   /* P0.15 SCK    PINSEL0 */
+#define SPI_PINSEL1_MASK     (0x0f << 2)    /* P0.17 P0.18  PINSEL1 */
+#define SPI_PINSEL0          (0x03 << 30)
+#define SPI_PINSEL1          (0x0f << 2)
+
+/* SPI PRegister offsets ************************************************************/
+
+#define SPI_CR_OFFSET        0x0000  /* Control Register */
+#define SPI_SR_OFFSET        0x0004  /* SPI Status Register */
+#define SPI_DR_OFFSET        0x0008  /* SPI Data Register */
+#define SPI_CCR_OFFSET       0x000c  /* SPI Clock Counter Register */
+#define SPI_TCR_OFFSET       0x0010  /* SPI Test Control Register */
+#define SPI_TSR_OFFSET       0x0014  /* SPI Test Status Register */
+#define SPI_INT_OFFSET       0x001c  /* SPI Interrupt Register */
+
+/* SPI Register addresses ***********************************************************/
+
+#define SPI_CR               (SPI_BASE+SPI_CR_OFFSET)
+#define SPI_SR               (SPI_BASE+SPI_SR_OFFSET)
+#define SPI_DR               (SPI_BASE+SPI_DR_OFFSET)
+#define SPI_CCR              (SPI_BASE+SPI_CCR_OFFSET)
+#define TCR_CCR              (SPI_BASE+SPI_TCR_OFFSET)
+#define TSR_CCR              (SPI_BASE+SPI_TSR_OFFSET)
+#define SPI_INT              (SPI_BASE+SPI_INT_OFFSET)
+
+/* SPI Register bit definitions *****************************************************/
+
+/* Control Register */
+                                       /* Bits 0-1: Reserved */
+#define SPI_CR_BITENABLE     (1 << 2)  /* Bit 2:  Enable word size selected by BITS */
+#define SPI_CR_CPHA          (1 << 3)  /* Bit 3:  Clock phase control */
+#define SPI_CR_CPOL          (1 << 4)  /* Bit 4:  Clock polarity control */
+#define SPI_CR_MSTR          (1 << 5)  /* Bit 5:  Master mode select */
+#define SPI_CR_LSBF          (1 << 6)  /* Bit 6:  SPI data is transferred LSB first */
+#define SPI_CR_SPIE          (1 << 7)  /* Bit 7:  Serial peripheral interrupt enable */
+#define SPI_CR_BITS_SHIFT    (8)       /* Bits 8-11: Number of bits per word (BITENABLE==1) */
+#define SPI_CR_BITS_MASK     (15 << SPI_CR_BITS_SHIFT)
+#  define SPI_CR_BITS_8BITS  (8 <<  SPI_CR_BITS_SHIFT) /* 8 bits per transfer */
+#  define SPI_CR_BITS_9BITS  (9 <<  SPI_CR_BITS_SHIFT) /* 9 bits per transfer */
+#  define SPI_CR_BITS_10BITS (10 << SPI_CR_BITS_SHIFT) /* 10 bits per transfer */
+#  define SPI_CR_BITS_11BITS (11 << SPI_CR_BITS_SHIFT) /* 11 bits per transfer */
+#  define SPI_CR_BITS_12BITS (12 << SPI_CR_BITS_SHIFT) /* 12 bits per transfer */
+#  define SPI_CR_BITS_13BITS (13 << SPI_CR_BITS_SHIFT) /* 13 bits per transfer */
+#  define SPI_CR_BITS_14BITS (14 << SPI_CR_BITS_SHIFT) /* 14 bits per transfer */
+#  define SPI_CR_BITS_15BITS (15 << SPI_CR_BITS_SHIFT) /* 15 bits per transfer */
+#  define SPI_CR_BITS_16BITS (0 <<  SPI_CR_BITS_SHIFT) /* 16 bits per transfer */
+                                       /* Bits 12-31: Reserved */
+/* SPI Status Register */
+                                       /* Bits 0-2: Reserved */
+#define SPI_SR_ABRT          (1 << 3)  /* Bit 3:  Slave abort */
+#define SPI_SR_MODF          (1 << 4)  /* Bit 4:  Mode fault */
+#define SPI_SR_ROVR          (1 << 5)  /* Bit 5:  Read overrun */
+#define SPI_SR_WCOL          (1 << 6)  /* Bit 6:  Write collision */
+#define SPI_SR_SPIF          (1 << 7)  /* Bit 7:  SPI transfer complete */
+                                       /* Bits 8-31: Reserved */
+/* SPI Data Register */
+
+#define SPI_DR_MASK          (0xff)    /* Bits 0-15: SPI Bi-directional data port */
+#define SPI_DR_MASKWIDE      (0xffff)  /* Bits 0-15: If SPI_CR_BITENABLE != 0 */
+                                       /* Bits 8-31: Reserved */
+/* SPI Clock Counter Register */
+
+#define SPI_CCR_MASK         (0xff)    /* Bits 0-7: SPI Clock counter setting */
+                                       /* Bits 8-31: Reserved */
+/* SPI Test Control Register */
+                                       /* Bit 0: Reserved */
+#define SPI_TCR_TEST_SHIFT   (1)       /* Bits 1-7: SPI test mode */
+#define SPI_TCR_TEST_MASK    (0x7f << SPI_TCR_TEST_SHIFT)
+                                       /* Bits 8-31: Reserved */
+/* SPI Test Status Register */
+                                       /* Bits 0-2: Reserved */
+#define SPI_TSR_ABRT         (1 << 3)  /* Bit 3:  Slave abort */
+#define SPI_TSR_MODF         (1 << 4)  /* Bit 4:  Mode fault */
+#define SPI_TSR_ROVR         (1 << 5)  /* Bit 5:  Read overrun */
+#define SPI_TSR_WCOL         (1 << 6)  /* Bit 6:  Write collision */
+#define SPI_TSR_SPIF         (1 << 7)  /* Bit 7:  SPI transfer complete */
+                                       /* Bits 8-31: Reserved */
+/* SPI Interrupt Register */
+
+#define SPI_INT_SPIF         (1 << 0)  /* SPI interrupt */
+                                       /* Bits 1-31: Reserved */
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+/* These functions must be provided by the board specific logic that has knowledge
+ * the chip select and card detect GPIO configuration of the board.
+ */
+
+void  lpc23xx_spiselect(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected);
+uint8_t lpc23xx_spistatus(FAR struct spi_dev_s *dev, enum spi_dev_e devid);
+
+#endif /* __ARCH_ARM_SRC_LPC2378_LPC23XX_SPI_H */
diff --git a/nuttx/configs/olimex-lpc2378/include/board.h b/nuttx/configs/olimex-lpc2378/include/board.h
index 44919c46c..dc6770a8c 100644
--- a/nuttx/configs/olimex-lpc2378/include/board.h
+++ b/nuttx/configs/olimex-lpc2378/include/board.h
@@ -6,7 +6,7 @@
  *
  * This is part of the NuttX RTOS and based on the LPC2148 port:
  *
- *   Copyright (C) 2010 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2010, 2014 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -38,35 +38,34 @@
  *
  ****************************************************************************/
 
-#ifndef __ARCH_BOARD_BOARD_H
-#define __ARCH_BOARD_BOARD_H
+#ifndef __CONFIGS_OLIMEX_LPC2378_INCLUDE_BOARD_H
+#define __CONFIGS_OLIMEX_LPC2378_INCLUDE_BOARD_H
 
-#ifdef __cplusplus
-   extern "C" {
-#endif
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
 
-/* If  USB is enabled, PLL must be configured for 48MHz to provide USB clocking */
-//--  F_pll = (2 * M * F_in)/N
-//--  F_out = ((2 * (PLL_M + 1 ) * FOSC)/(0+1))/(CCLK_DIV+1)  = 288/5 = 57 600 000 Hz
-//~ #ifdef CONFIG_USBDEV
- //~ #	define FOSC		(12000000)	/* Oscillator frequency */
- //~ #	define CCLK		(57600000)	/* CPU running clock */
- //~ #	define FCCO		(288000000)	/* CPU CCO clock */
-//~ #else
- #	define FOSC		(12000000)	/* Oscillator frequency */
- #	define CCLK		(57600000)	/* CPU running clock */
- #	define FCCO		(288000000)	/* CPU CCO clock */
- //~ #	define CCLK		(72000000)	/* CPU running clock */
- //~ #	define FCCO		(360000000)	/* CPU CCO clock */
-//~ #endif 
+/* If  USB is enabled, PLL must be configured for 48MHz to provide USB
+ * clocking.
+ *
+ *   F_pll = (2 * M * F_in) / N
+ *   F_out = ((2 * (PLL_M + 1) * FOSC)/(PLL_N + 1))/(CCLK_DIV + 1)
+ *
+ * With PLL_M=11, PLL_N=0, CCLK_DIV=4:
+ *
+ *   F_out = ((2 * (11 + 1) * 12000000)/(0 + 1))/(4 + 1)
+ *         = 288,000,000 / 5 = 57,600,000 Hz
+ */
 
-//~#define PLL_M	( (FCCO / (2 * FOSC))-1 ) 
-//~ #define PLL_N	( ((2 * PLL_M * FOSC) / FCCO)-1 )
-#define PLL_M	11
-#define PLL_N	0
+#define FOSC             (12000000)   /* Oscillator frequency */
+#define FCCO             (288000000)  /* CPU CCO clock */
+#define CCLK             (57600000)   /* CPU running clock */
 
-#define CCLK_DIV	4
-#define USBCLK_DIV	6
+#define PLL_M             11
+#define PLL_N             0
+
+#define CCLK_DIV          4
+#define USBCLK_DIV        6
 
  /* LED definitions **********************************************************/
 
@@ -79,12 +78,8 @@
 #define LED_ASSERTION     6
 #define LED_PANIC         7
  
-#ifdef __cplusplus
-   }
-#endif
- 
 /****************************************************************************
  * Inline Functions
  ****************************************************************************/
 
-#endif  /* __ARCH_BOARD_BOARD_H */
+#endif  /* __CONFIGS_OLIMEX_LPC2378_INCLUDE_BOARD_H */