Add SAMD20 pin configuration definitions

6 files changed, 565 insertions, 274 deletions

diff --git a/nuttx/arch/arm/src/sam34/chip/sam4s_pinmap.h b/nuttx/arch/arm/src/sam34/chip/sam4s_pinmap.h
index 55c1be272..4b2654b4e 100644
--- a/nuttx/arch/arm/src/sam34/chip/sam4s_pinmap.h
+++ b/nuttx/arch/arm/src/sam34/chip/sam4s_pinmap.h
@@ -60,7 +60,7 @@
  *
  * #define GPIO_PCK0 GPIO_PCK0_1
  *
- * The driver will then automatically configre PA6 as the PCK0 pin.
+ * The driver will then automatically configure PA6 as the PCK0 pin.
  */
 
 /* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
@@ -69,7 +69,7 @@
  * pins in this file.
  */
 
-/* 12-bit Analog-to-Digital Conververt (ADC) */
+/* 12-bit Analog-to-Digital Converter (ADC) */
 
 #define GPIO_ADC0_AD0     (GPIO_INPUT | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN17)
 #define GPIO_ADC0_AD1     (GPIO_INPUT | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN18)
diff --git a/nuttx/arch/arm/src/samd/chip/sam_port.h b/nuttx/arch/arm/src/samd/chip/sam_port.h
index 0186018c8..84778cdea 100644
--- a/nuttx/arch/arm/src/samd/chip/sam_port.h
+++ b/nuttx/arch/arm/src/samd/chip/sam_port.h
@@ -49,15 +49,260 @@
  ********************************************************************************************/
 /* PORT register offsets ********************************************************************/
 
-#warning Missing logic
+#define SAM_PORTA_OFFSET          0x0000 /* Port A register offset */
+#define SAM_PORTB_OFFSET          0x0080 /* Port B register offset */
+
+#define SAM_PORT_DIR_OFFSET       0x0000 /* Data direction register */
+#define SAM_PORT_DIRCLR_OFFSET    0x0004 /* Data direction clear register */
+#define SAM_PORT_DIRSET_OFFSET    0x0008 /* Data direction set register */
+#define SAM_PORT_DIRTGL_OFFSET    0x000c /* Data direction toggle register */
+#define SAM_PORT_OUT_OFFSET       0x0010 /* Data output value register */
+#define SAM_PORT_OUTCLR_OFFSET    0x0014 /* Data output value clear register */
+#define SAM_PORT_OUTSET_OFFSET    0x0018 /* Data output value set register */
+#define SAM_PORT_OUTTGL_OFFSET    0x001c /* Data output value toggle register */
+#define SAM_PORT_IN_OFFSET        0x0020 /* Data input value register */
+#define SAM_PORT_CTRL_OFFSET      0x0024 /* Control register */
+#define SAM_PORT_WRCONFIG_OFFSET  0x0028 /* Write configuration registers */
+
+#define SAM_PORT_PMUX_OFFSET(n)   (0x0030+((n)>>1))
+#define SAM_PORT_PMUX0_OFFSET     0x0030 /* Peripheral multiplexing register 0 */
+#define SAM_PORT_PMUX1_OFFSET     0x0031 /* Peripheral multiplexing register 1 */
+#define SAM_PORT_PMUX2_OFFSET     0x0032 /* Peripheral multiplexing register 2 */
+#define SAM_PORT_PMUX3_OFFSET     0x0033 /* Peripheral multiplexing register 3 */
+#define SAM_PORT_PMUX4_OFFSET     0x0034 /* Peripheral multiplexing register 4 */
+#define SAM_PORT_PMUX5_OFFSET     0x0035 /* Peripheral multiplexing register 5 */
+#define SAM_PORT_PMUX6_OFFSET     0x0036 /* Peripheral multiplexing register 6 */
+#define SAM_PORT_PMUX7_OFFSET     0x0037 /* Peripheral multiplexing register 7 */
+#define SAM_PORT_PMUX8_OFFSET     0x0038 /* Peripheral multiplexing register 8 */
+#define SAM_PORT_PMUX9_OFFSET     0x0039 /* Peripheral multiplexing register 9 */
+#define SAM_PORT_PMUX10_OFFSET    0x003a /* Peripheral multiplexing register 10 */
+#define SAM_PORT_PMUX11_OFFSET    0x003b /* Peripheral multiplexing register 11 */
+#define SAM_PORT_PMUX12_OFFSET    0x003c /* Peripheral multiplexing register 12 */
+#define SAM_PORT_PMUX13_OFFSET    0x003d /* Peripheral multiplexing register 13 */
+#define SAM_PORT_PMUX14_OFFSET    0x003e /* Peripheral multiplexing register 14 */
+#define SAM_PORT_PMUX15_OFFSET    0x003f /* Peripheral multiplexing register 15 */
+
+#define SAM_PORT_PINCFG_OFFSET(n) (0x0040+(n))
+#define SAM_PORT_PINCFG0_OFFSET   0x0040 /* Pin configuration register 0 */
+#define SAM_PORT_PINCFG1_OFFSET   0x0041 /* Pin configuration register 1 */
+#define SAM_PORT_PINCFG2_OFFSET   0x0042 /* Pin configuration register 2 */
+#define SAM_PORT_PINCFG3_OFFSET   0x0043 /* Pin configuration register 3 */
+#define SAM_PORT_PINCFG4_OFFSET   0x0044 /* Pin configuration register 4 */
+#define SAM_PORT_PINCFG5_OFFSET   0x0045 /* Pin configuration register 5 */
+#define SAM_PORT_PINCFG6_OFFSET   0x0046 /* Pin configuration register 6 */
+#define SAM_PORT_PINCFG7_OFFSET   0x0047 /* Pin configuration register 7 */
+#define SAM_PORT_PINCFG8_OFFSET   0x0048 /* Pin configuration register 8 */
+#define SAM_PORT_PINCFG9_OFFSET   0x0049 /* Pin configuration register 9 */
+#define SAM_PORT_PINCFG10_OFFSET  0x004a /* Pin configuration register 10 */
+#define SAM_PORT_PINCFG11_OFFSET  0x004b /* Pin configuration register 11 */
+#define SAM_PORT_PINCFG12_OFFSET  0x004c /* Pin configuration register 12 */
+#define SAM_PORT_PINCFG13_OFFSET  0x004d /* Pin configuration register 13 */
+#define SAM_PORT_PINCFG14_OFFSET  0x004e /* Pin configuration register 14 */
+#define SAM_PORT_PINCFG15_OFFSET  0x004f /* Pin configuration register 15 */
+#define SAM_PORT_PINCFG16_OFFSET  0x0050 /* Pin configuration register 16 */
+#define SAM_PORT_PINCFG17_OFFSET  0x0051 /* Pin configuration register 17 */
+#define SAM_PORT_PINCFG18_OFFSET  0x0052 /* Pin configuration register 18 */
+#define SAM_PORT_PINCFG19_OFFSET  0x0053 /* Pin configuration register 19 */
+#define SAM_PORT_PINCFG20_OFFSET  0x0054 /* Pin configuration register 20 */
+#define SAM_PORT_PINCFG21_OFFSET  0x0055 /* Pin configuration register 21 */
+#define SAM_PORT_PINCFG22_OFFSET  0x0056 /* Pin configuration register 22 */
+#define SAM_PORT_PINCFG23_OFFSET  0x0057 /* Pin configuration register 23 */
+#define SAM_PORT_PINCFG24_OFFSET  0x0058 /* Pin configuration register 24 */
+#define SAM_PORT_PINCFG25_OFFSET  0x0059 /* Pin configuration register 25 */
+#define SAM_PORT_PINCFG26_OFFSET  0x005a /* Pin configuration register 26 */
+#define SAM_PORT_PINCFG27_OFFSET  0x005b /* Pin configuration register 27 */
+#define SAM_PORT_PINCFG28_OFFSET  0x005c /* Pin configuration register 28 */
+#define SAM_PORT_PINCFG29_OFFSET  0x005d /* Pin configuration register 29 */
+#define SAM_PORT_PINCFG30_OFFSET  0x005e /* Pin configuration register 30 */
+#define SAM_PORT_PINCFG31_OFFSET  0x005f /* Pin configuration register 31 */
 
 /* PORT register addresses ******************************************************************/
 
-#warning Missing logic
+#define SAM_PORTA_BASE            (SAM_PORT_BASE+SAM_PORTA_OFFSET)
+#define SAM_PORTB_BASE            (SAM_PORT_BASE+SAM_PORTB_OFFSET)
+
+#define SAM_PORTA_DIR             (SAM_PORTA_BASE+SAM_PORT_DIR_OFFSET)
+#define SAM_PORTA_DIRCLR          (SAM_PORTA_BASE+SAM_PORT_DIRCLR_OFFSET)
+#define SAM_PORTA_DIRSET          (SAM_PORTA_BASE+SAM_PORT_DIRSET_OFFSET)
+#define SAM_PORTA_DIRTGL          (SAM_PORTA_BASE+SAM_PORT_DIRTGL_OFFSET)
+#define SAM_PORTA_OUT             (SAM_PORTA_BASE+SAM_PORT_OUT_OFFSET)
+#define SAM_PORTA_OUTCLR          (SAM_PORTA_BASE+SAM_PORT_OUTCLR_OFFSET)
+#define SAM_PORTA_OUTSET          (SAM_PORTA_BASE+SAM_PORT_OUTSET_OFFSET)
+#define SAM_PORTA_OUTTGL          (SAM_PORTA_BASE+SAM_PORT_OUTTGL_OFFSET)
+#define SAM_PORTA_IN              (SAM_PORTA_BASE+SAM_PORT_IN_OFFSET)
+#define SAM_PORTA_CTRL            (SAM_PORTA_BASE+SAM_PORT_CTRL_OFFSET)
+#define SAM_PORTA_WRCONFIG        (SAM_PORTA_BASE+SAM_PORT_WRCONFIG_OFFSET)
+
+#define SAM_PORTA_PMUX(n)         (SAM_PORTA_BASE+SAM_PORT_PMUX_OFFSET(n))
+#define SAM_PORTA_PMUX0           (SAM_PORTA_BASE+SAM_PORT_PMUX0_OFFSET)
+#define SAM_PORTA_PMUX1           (SAM_PORTA_BASE+SAM_PORT_PMUX1_OFFSET)
+#define SAM_PORTA_PMUX2           (SAM_PORTA_BASE+SAM_PORT_PMUX2_OFFSET)
+#define SAM_PORTA_PMUX3           (SAM_PORTA_BASE+SAM_PORT_PMUX3_OFFSET)
+#define SAM_PORTA_PMUX4           (SAM_PORTA_BASE+SAM_PORT_PMUX4_OFFSET)
+#define SAM_PORTA_PMUX5           (SAM_PORTA_BASE+SAM_PORT_PMUX5_OFFSET)
+#define SAM_PORTA_PMUX6           (SAM_PORTA_BASE+SAM_PORT_PMUX6_OFFSET)
+#define SAM_PORTA_PMUX7           (SAM_PORTA_BASE+SAM_PORT_PMUX7_OFFSET)
+#define SAM_PORTA_PMUX8           (SAM_PORTA_BASE+SAM_PORT_PMUX8_OFFSET)
+#define SAM_PORTA_PMUX9           (SAM_PORTA_BASE+SAM_PORT_PMUX9_OFFSET)
+#define SAM_PORTA_PMUX10          (SAM_PORTA_BASE+SAM_PORT_PMUX10_OFFSET)
+#define SAM_PORTA_PMUX11          (SAM_PORTA_BASE+SAM_PORT_PMUX11_OFFSET)
+#define SAM_PORTA_PMUX12          (SAM_PORTA_BASE+SAM_PORT_PMUX12_OFFSET)
+#define SAM_PORTA_PMUX13          (SAM_PORTA_BASE+SAM_PORT_PMUX13_OFFSET)
+#define SAM_PORTA_PMUX14          (SAM_PORTA_BASE+SAM_PORT_PMUX14_OFFSET)
+#define SAM_PORTA_PMUX15          (SAM_PORTA_BASE+SAM_PORT_PMUX15_OFFSET)
+
+#define SAM_PORTA_PINCFG(n)       (SAM_PORTA_BASE+SAM_PORT_PINCFG_OFFSET(n))
+#define SAM_PORTA_PINCFG0         (SAM_PORTA_BASE+SAM_PORT_PINCFG0_OFFSET)
+#define SAM_PORTA_PINCFG1         (SAM_PORTA_BASE+SAM_PORT_PINCFG1_OFFSET)
+#define SAM_PORTA_PINCFG2         (SAM_PORTA_BASE+SAM_PORT_PINCFG2_OFFSET)
+#define SAM_PORTA_PINCFG3         (SAM_PORTA_BASE+SAM_PORT_PINCFG3_OFFSET)
+#define SAM_PORTA_PINCFG4         (SAM_PORTA_BASE+SAM_PORT_PINCFG4_OFFSET)
+#define SAM_PORTA_PINCFG5         (SAM_PORTA_BASE+SAM_PORT_PINCFG5_OFFSET)
+#define SAM_PORTA_PINCFG6         (SAM_PORTA_BASE+SAM_PORT_PINCFG6_OFFSET)
+#define SAM_PORTA_PINCFG7         (SAM_PORTA_BASE+SAM_PORT_PINCFG7_OFFSET)
+#define SAM_PORTA_PINCFG8         (SAM_PORTA_BASE+SAM_PORT_PINCFG8_OFFSET)
+#define SAM_PORTA_PINCFG9         (SAM_PORTA_BASE+SAM_PORT_PINCFG9_OFFSET)
+#define SAM_PORTA_PINCFG10        (SAM_PORTA_BASE+SAM_PORT_PINCFG10_OFFSET)
+#define SAM_PORTA_PINCFG11        (SAM_PORTA_BASE+SAM_PORT_PINCFG11_OFFSET)
+#define SAM_PORTA_PINCFG12        (SAM_PORTA_BASE+SAM_PORT_PINCFG12_OFFSET)
+#define SAM_PORTA_PINCFG13        (SAM_PORTA_BASE+SAM_PORT_PINCFG13_OFFSET)
+#define SAM_PORTA_PINCFG14        (SAM_PORTA_BASE+SAM_PORT_PINCFG14_OFFSET)
+#define SAM_PORTA_PINCFG15        (SAM_PORTA_BASE+SAM_PORT_PINCFG15_OFFSET)
+#define SAM_PORTA_PINCFG16        (SAM_PORTA_BASE+SAM_PORT_PINCFG16_OFFSET)
+#define SAM_PORTA_PINCFG17        (SAM_PORTA_BASE+SAM_PORT_PINCFG17_OFFSET)
+#define SAM_PORTA_PINCFG18        (SAM_PORTA_BASE+SAM_PORT_PINCFG18_OFFSET)
+#define SAM_PORTA_PINCFG19        (SAM_PORTA_BASE+SAM_PORT_PINCFG19_OFFSET)
+#define SAM_PORTA_PINCFG20        (SAM_PORTA_BASE+SAM_PORT_PINCFG20_OFFSET)
+#define SAM_PORTA_PINCFG21        (SAM_PORTA_BASE+SAM_PORT_PINCFG21_OFFSET)
+#define SAM_PORTA_PINCFG22        (SAM_PORTA_BASE+SAM_PORT_PINCFG22_OFFSET)
+#define SAM_PORTA_PINCFG23        (SAM_PORTA_BASE+SAM_PORT_PINCFG23_OFFSET)
+#define SAM_PORTA_PINCFG24        (SAM_PORTA_BASE+SAM_PORT_PINCFG24_OFFSET)
+#define SAM_PORTA_PINCFG25        (SAM_PORTA_BASE+SAM_PORT_PINCFG25_OFFSET)
+#define SAM_PORTA_PINCFG26        (SAM_PORTA_BASE+SAM_PORT_PINCFG26_OFFSET)
+#define SAM_PORTA_PINCFG27        (SAM_PORTA_BASE+SAM_PORT_PINCFG27_OFFSET)
+#define SAM_PORTA_PINCFG28        (SAM_PORTA_BASE+SAM_PORT_PINCFG28_OFFSET)
+#define SAM_PORTA_PINCFG29        (SAM_PORTA_BASE+SAM_PORT_PINCFG29_OFFSET)
+#define SAM_PORTA_PINCFG30        (SAM_PORTA_BASE+SAM_PORT_PINCFG30_OFFSET)
+#define SAM_PORTA_PINCFG31        (SAM_PORTA_BASE+SAM_PORT_PINCFG31_OFFSET)
+
+#define SAM_PORTB_DIR             (SAM_PORTB_BASE+SAM_PORT_DIR_OFFSET)
+#define SAM_PORTB_DIRCLR          (SAM_PORTB_BASE+SAM_PORT_DIRCLR_OFFSET)
+#define SAM_PORTB_DIRSET          (SAM_PORTB_BASE+SAM_PORT_DIRSET_OFFSET)
+#define SAM_PORTB_DIRTGL          (SAM_PORTB_BASE+SAM_PORT_DIRTGL_OFFSET)
+#define SAM_PORTB_OUT             (SAM_PORTB_BASE+SAM_PORT_OUT_OFFSET)
+#define SAM_PORTB_OUTCLR          (SAM_PORTB_BASE+SAM_PORT_OUTCLR_OFFSET)
+#define SAM_PORTB_OUTSET          (SAM_PORTB_BASE+SAM_PORT_OUTSET_OFFSET)
+#define SAM_PORTB_OUTTGL          (SAM_PORTB_BASE+SAM_PORT_OUTTGL_OFFSET)
+#define SAM_PORTB_IN              (SAM_PORTB_BASE+SAM_PORT_IN_OFFSET)
+#define SAM_PORTB_CTRL            (SAM_PORTB_BASE+SAM_PORT_CTRL_OFFSET)
+#define SAM_PORTB_WRCONFIG        (SAM_PORTB_BASE+SAM_PORT_WRCONFIG_OFFSET)
+
+#define SAM_PORTB_PMUX(n)         (SAM_PORTB_BASE+SAM_PORT_PMUX_OFFSET(n))
+#define SAM_PORTB_PMUX0           (SAM_PORTB_BASE+SAM_PORT_PMUX0_OFFSET)
+#define SAM_PORTB_PMUX1           (SAM_PORTB_BASE+SAM_PORT_PMUX1_OFFSET)
+#define SAM_PORTB_PMUX2           (SAM_PORTB_BASE+SAM_PORT_PMUX2_OFFSET)
+#define SAM_PORTB_PMUX3           (SAM_PORTB_BASE+SAM_PORT_PMUX3_OFFSET)
+#define SAM_PORTB_PMUX4           (SAM_PORTB_BASE+SAM_PORT_PMUX4_OFFSET)
+#define SAM_PORTB_PMUX5           (SAM_PORTB_BASE+SAM_PORT_PMUX5_OFFSET)
+#define SAM_PORTB_PMUX6           (SAM_PORTB_BASE+SAM_PORT_PMUX6_OFFSET)
+#define SAM_PORTB_PMUX7           (SAM_PORTB_BASE+SAM_PORT_PMUX7_OFFSET)
+#define SAM_PORTB_PMUX8           (SAM_PORTB_BASE+SAM_PORT_PMUX8_OFFSET)
+#define SAM_PORTB_PMUX9           (SAM_PORTB_BASE+SAM_PORT_PMUX9_OFFSET)
+#define SAM_PORTB_PMUX10          (SAM_PORTB_BASE+SAM_PORT_PMUX10_OFFSET)
+#define SAM_PORTB_PMUX11          (SAM_PORTB_BASE+SAM_PORT_PMUX11_OFFSET)
+#define SAM_PORTB_PMUX12          (SAM_PORTB_BASE+SAM_PORT_PMUX12_OFFSET)
+#define SAM_PORTB_PMUX13          (SAM_PORTB_BASE+SAM_PORT_PMUX13_OFFSET)
+#define SAM_PORTB_PMUX14          (SAM_PORTB_BASE+SAM_PORT_PMUX14_OFFSET)
+#define SAM_PORTB_PMUX15          (SAM_PORTB_BASE+SAM_PORT_PMUX15_OFFSET)
+
+#define SAM_PORTB_PINCFG(n)       (SAM_PORTB_BASE+SAM_PORT_PINCFG_OFFSET(n))
+#define SAM_PORTB_PINCFG0         (SAM_PORTB_BASE+SAM_PORT_PINCFG0_OFFSET)
+#define SAM_PORTB_PINCFG1         (SAM_PORTB_BASE+SAM_PORT_PINCFG1_OFFSET)
+#define SAM_PORTB_PINCFG2         (SAM_PORTB_BASE+SAM_PORT_PINCFG2_OFFSET)
+#define SAM_PORTB_PINCFG3         (SAM_PORTB_BASE+SAM_PORT_PINCFG3_OFFSET)
+#define SAM_PORTB_PINCFG4         (SAM_PORTB_BASE+SAM_PORT_PINCFG4_OFFSET)
+#define SAM_PORTB_PINCFG5         (SAM_PORTB_BASE+SAM_PORT_PINCFG5_OFFSET)
+#define SAM_PORTB_PINCFG6         (SAM_PORTB_BASE+SAM_PORT_PINCFG6_OFFSET)
+#define SAM_PORTB_PINCFG7         (SAM_PORTB_BASE+SAM_PORT_PINCFG7_OFFSET)
+#define SAM_PORTB_PINCFG8         (SAM_PORTB_BASE+SAM_PORT_PINCFG8_OFFSET)
+#define SAM_PORTB_PINCFG9         (SAM_PORTB_BASE+SAM_PORT_PINCFG9_OFFSET)
+#define SAM_PORTB_PINCFG10        (SAM_PORTB_BASE+SAM_PORT_PINCFG10_OFFSET)
+#define SAM_PORTB_PINCFG11        (SAM_PORTB_BASE+SAM_PORT_PINCFG11_OFFSET)
+#define SAM_PORTB_PINCFG12        (SAM_PORTB_BASE+SAM_PORT_PINCFG12_OFFSET)
+#define SAM_PORTB_PINCFG13        (SAM_PORTB_BASE+SAM_PORT_PINCFG13_OFFSET)
+#define SAM_PORTB_PINCFG14        (SAM_PORTB_BASE+SAM_PORT_PINCFG14_OFFSET)
+#define SAM_PORTB_PINCFG15        (SAM_PORTB_BASE+SAM_PORT_PINCFG15_OFFSET)
+#define SAM_PORTB_PINCFG16        (SAM_PORTB_BASE+SAM_PORT_PINCFG16_OFFSET)
+#define SAM_PORTB_PINCFG17        (SAM_PORTB_BASE+SAM_PORT_PINCFG17_OFFSET)
+#define SAM_PORTB_PINCFG18        (SAM_PORTB_BASE+SAM_PORT_PINCFG18_OFFSET)
+#define SAM_PORTB_PINCFG19        (SAM_PORTB_BASE+SAM_PORT_PINCFG19_OFFSET)
+#define SAM_PORTB_PINCFG20        (SAM_PORTB_BASE+SAM_PORT_PINCFG20_OFFSET)
+#define SAM_PORTB_PINCFG21        (SAM_PORTB_BASE+SAM_PORT_PINCFG21_OFFSET)
+#define SAM_PORTB_PINCFG22        (SAM_PORTB_BASE+SAM_PORT_PINCFG22_OFFSET)
+#define SAM_PORTB_PINCFG23        (SAM_PORTB_BASE+SAM_PORT_PINCFG23_OFFSET)
+#define SAM_PORTB_PINCFG24        (SAM_PORTB_BASE+SAM_PORT_PINCFG24_OFFSET)
+#define SAM_PORTB_PINCFG25        (SAM_PORTB_BASE+SAM_PORT_PINCFG25_OFFSET)
+#define SAM_PORTB_PINCFG26        (SAM_PORTB_BASE+SAM_PORT_PINCFG26_OFFSET)
+#define SAM_PORTB_PINCFG27        (SAM_PORTB_BASE+SAM_PORT_PINCFG27_OFFSET)
+#define SAM_PORTB_PINCFG28        (SAM_PORTB_BASE+SAM_PORT_PINCFG28_OFFSET)
+#define SAM_PORTB_PINCFG29        (SAM_PORTB_BASE+SAM_PORT_PINCFG29_OFFSET)
+#define SAM_PORTB_PINCFG30        (SAM_PORTB_BASE+SAM_PORT_PINCFG30_OFFSET)
+#define SAM_PORTB_PINCFG31        (SAM_PORTB_BASE+SAM_PORT_PINCFG31_OFFSET)
 
 /* PORT register bit definitions ************************************************************/
 
-#warning Missing logic
+/* Data direction, data direction clear,  data direction set, and data direction toggle
+ * registers
+ */
+
+#define PORT_DIR(n)               (1 << n) /* Port data n, direction, n=0-31 */
+
+/* Data output value, data output value clear, data output value set, and data output
+ * value toggle registers
+ */
+
+#define PORT_OUT(n)               (1 << n) /* Port data n output value, n=0-31 */
+
+/* Data input value register */
+
+#define PORT_IN(n)                (1 << n) /* Port n data input value, n=0-31 */
+
+/* Control register */
+
+#define PORT_CTRL(n)              (1 << n) /* Port n input sampling mode, n=0-31 */
+
+/* Write configuration registers */
+
+#define PORT_WRCONFIG_PINMASK_SHIFT (0) /* Bits 0-15:  Pin Mask for Multiple Pin Configuration */
+#define PORT_WRCONFIG_PINMASK_MASK  (0xffff << PORT_WRCONFIG_PINMASK_SHIFT)
+#  define PORT_WRCONFIG_PINMASK(n)  (1 << (PORT_WRCONFIG_PINMASK_SHIFT+(n)))
+#define PORT_WRCONFIG_PMUXEN      (1 << 16) /* Bit 16: Peripheral Multiplexer Enable */
+#define PORT_WRCONFIG_INEN        (1 << 17) /* Bit 17: Input Enable */
+#define PORT_WRCONFIG_PULLEN      (1 << 18) /* Bit 18: Pull Enable */
+#define PORT_WRCONFIG_DRVSTR      (1 << 22) /* Bit 22: Output Driver Strength Selection */
+#define PORT_WRCONFIG_PMUX_SHIFT  (24)      /* Bits 24-27: Peripheral Multiplexing */
+#define PORT_WRCONFIG_PMUX_MASK   (15 << PORT_WRCONFIG_PMUX_SHIFT)
+#define PORT_WRCONFIG_WRPMUX      (1 << 28) /* Bit 28: Write PMUX */
+#define PORT_WRCONFIG_WRPINCFG    (1 << 30) /* Bit 30: Write PINCFG */
+#define PORT_WRCONFIG_HWSEL       (1 << 31) /* Bit 31: Half-Word Select */
+
+/* Peripheral multiplexing registers */
+
+#define PORT_PMUX_PERIPHA         0x00      /* Peripheral function A */
+#define PORT_PMUX_PERIPHB         0x01      /* Peripheral function B */
+#define PORT_PMUX_PERIPHC         0x02      /* Peripheral function C */
+#define PORT_PMUX_PERIPHD         0x03      /* Peripheral function D */
+#define PORT_PMUX_PERIPHE         0x04      /* Peripheral function E */
+#define PORT_PMUX_PERIPHF         0x05      /* Peripheral function F */
+#define PORT_PMUX_PERIPHG         0x06      /* Peripheral function G */
+#define PORT_PMUX_PERIPHH         0x07      /* Peripheral function H */
+
+/* Pin configuration registers */
+
+#define PORT_PINCFG_PMUXEN        (1 << 0)  /* Bit 0: Peripheral Multiplexer Enable */
+#define PORT_PINCFG_INEN          (1 << 1)  /* Bit 1: Input Enable */
+#define PORT_PINCFG_PULLEN        (1 << 2)  /* Bit 2: Pull Enable */
+#define PORT_PINCFG_DRVSTR        (1 << 6)  /* Bit 6: Output Driver Strength Selection */
 
 /********************************************************************************************
  * Public Types
diff --git a/nuttx/arch/arm/src/samd/chip/samd20_pinmap.h b/nuttx/arch/arm/src/samd/chip/samd20_pinmap.h
index 04b225edd..0ed9be383 100644
--- a/nuttx/arch/arm/src/samd/chip/samd20_pinmap.h
+++ b/nuttx/arch/arm/src/samd/chip/samd20_pinmap.h
@@ -47,8 +47,304 @@
 /********************************************************************************************
  * Pre-processor Definitions
  ********************************************************************************************/
+/* GPIO pin definitions *********************************************************************/
+/* Alternate Pin Functions.
+ *
+ * Alternative pin selections are provided with a numeric suffix like _1, _2, etc.
+ * Drivers, however, will use the pin selection without the numeric suffix.
+ * Additional definitions are required in the board.h file.  For example, if we
+ * wanted the SERCOM0 PAD0 on PA8, then the following definition should appear in
+ * the board.h header file for that board:
+ *
+ * #define PORT_SERCOM0_PAD0 PORT_SERCOM0_PAD0_1
+ *
+ * The driver will then automatically configure PA8 as the SERCOM0 PAD0 pin.
+ */
+
+/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
+ * Additional effort is required to select specific GPIO options such as frequency,
+ * open-drain/push-pull, and pull-up/down!  Just the basics are defined for most
+ * pins in this file.
+ */
+
+/* Analog comparator */
+
+#define PORT_AC_CMP0_1       (PORT_FUNCH | PORTA | PORT_PIN12)
+#define PORT_AC_CMP0_2       (PORT_FUNCH | PORTA | PORT_PIN18)
+#define PORT_AC_CMP1_1       (PORT_FUNCH | PORTA | PORT_PIN13)
+#define PORT_AC_CMP1_2       (PORT_FUNCH | PORTA | PORT_PIN19)
+
+/* ADC voltage references */
+
+#define PORT_ADC_VREFA       (PORT_FUNCB | PORTA | PORT_PIN3)
+#define PORT_ADC_VREFB       (PORT_FUNCB | PORTA | PORT_PIN4)
+
+#define PORT_AIN0_1          (PORT_FUNCB | PORTA | PORT_PIN2)
+#define PORT_AIN0_2          (PORT_FUNCB | PORTA | PORT_PIN4)
+#define PORT_AIN1_1          (PORT_FUNCB | PORTA | PORT_PIN3)
+#define PORT_AIN1_2          (PORT_FUNCB | PORTA | PORT_PIN5)
+#define PORT_AIN2_1          (PORT_FUNCB | PORTA | PORT_PIN6)
+#define PORT_AIN2_2          (PORT_FUNCB | PORTB | PORT_PIN8)
+#define PORT_AIN3_1          (PORT_FUNCB | PORTA | PORT_PIN7)
+#define PORT_AIN3_2          (PORT_FUNCB | PORTB | PORT_PIN9)
+#define PORT_AIN4            (PORT_FUNCB | PORTA | PORT_PIN4)
+#define PORT_AIN5            (PORT_FUNCB | PORTA | PORT_PIN5)
+#define PORT_AIN6            (PORT_FUNCB | PORTA | PORT_PIN6)
+#define PORT_AIN7            (PORT_FUNCB | PORTA | PORT_PIN7)
+#define PORT_AIN8            (PORT_FUNCB | PORTB | PORT_PIN0)
+#define PORT_AIN9            (PORT_FUNCB | PORTB | PORT_PIN1)
+#define PORT_AIN10           (PORT_FUNCB | PORTB | PORT_PIN2)
+#define PORT_AIN11           (PORT_FUNCB | PORTB | PORT_PIN3)
+#define PORT_AIN12           (PORT_FUNCB | PORTB | PORT_PIN4)
+#define PORT_AIN13           (PORT_FUNCB | PORTB | PORT_PIN5)
+#define PORT_AIN14           (PORT_FUNCB | PORTB | PORT_PIN6)
+#define PORT_AIN15           (PORT_FUNCB | PORTB | PORT_PIN7)
+#define PORT_AIN16           (PORT_FUNCB | PORTA | PORT_PIN8)
+#define PORT_AIN17           (PORT_FUNCB | PORTA | PORT_PIN9)
+#define PORT_AIN18           (PORT_FUNCB | PORTA | PORT_PIN10)
+#define PORT_AIN19           (PORT_FUNCB | PORTA | PORT_PIN11)
+
+/* DAC */
+
+#define PORT_DAC_VREFA       (PORT_FUNCB | PORTA | PORT_PIN3)
+#define PORT_DAC_VOUT        (PORT_FUNCB | PORTA | PORT_PIN2)
+
+/* External interrupts */
+
+#define PORT_EXTINT0_1       (PORT_FUNCA | PORTA | PORT_PIN0)
+#define PORT_EXTINT0_2       (PORT_FUNCA | PORTA | PORT_PIN16)
+#define PORT_EXTINT0_3       (PORT_FUNCA | PORTB | PORT_PIN0)
+#define PORT_EXTINT0_4       (PORT_FUNCA | PORTB | PORT_PIN16)
+#define PORT_EXTINT1_1       (PORT_FUNCA | PORTA | PORT_PIN1)
+#define PORT_EXTINT1_2       (PORT_FUNCA | PORTA | PORT_PIN17)
+#define PORT_EXTINT1_3       (PORT_FUNCA | PORTB | PORT_PIN1)
+#define PORT_EXTINT1_4       (PORT_FUNCA | PORTB | PORT_PIN17)
+#define PORT_EXTINT2_1       (PORT_FUNCA | PORTA | PORT_PIN18)
+#define PORT_EXTINT2_2       (PORT_FUNCA | PORTA | PORT_PIN2)
+#define PORT_EXTINT2_3       (PORT_FUNCA | PORTB | PORT_PIN2)
+#define PORT_EXTINT3_1       (PORT_FUNCA | PORTA | PORT_PIN19)
+#define PORT_EXTINT3_2       (PORT_FUNCA | PORTA | PORT_PIN3)
+#define PORT_EXTINT3_3       (PORT_FUNCA | PORTB | PORT_PIN3)
+#define PORT_EXTINT4_1       (PORT_FUNCA | PORTA | PORT_PIN20)
+#define PORT_EXTINT4_2       (PORT_FUNCA | PORTA | PORT_PIN4)
+#define PORT_EXTINT4_3       (PORT_FUNCA | PORTB | PORT_PIN4)
+#define PORT_EXTINT5_1       (PORT_FUNCA | PORTA | PORT_PIN21)
+#define PORT_EXTINT5_2       (PORT_FUNCA | PORTA | PORT_PIN5)
+#define PORT_EXTINT5_3       (PORT_FUNCA | PORTB | PORT_PIN5)
+#define PORT_EXTINT6_1       (PORT_FUNCA | PORTA | PORT_PIN22)
+#define PORT_EXTINT6_2       (PORT_FUNCA | PORTA | PORT_PIN6)
+#define PORT_EXTINT6_3       (PORT_FUNCA | PORTB | PORT_PIN22)
+#define PORT_EXTINT6_4       (PORT_FUNCA | PORTB | PORT_PIN6)
+#define PORT_EXTINT7_1       (PORT_FUNCA | PORTA | PORT_PIN23)
+#define PORT_EXTINT7_2       (PORT_FUNCA | PORTA | PORT_PIN7)
+#define PORT_EXTINT7_3       (PORT_FUNCA | PORTB | PORT_PIN23)
+#define PORT_EXTINT7_4       (PORT_FUNCA | PORTB | PORT_PIN7)
+#define PORT_EXTINT8_1       (PORT_FUNCA | PORTA | PORT_PIN28)
+#define PORT_EXTINT8_2       (PORT_FUNCA | PORTB | PORT_PIN8)
+#define PORT_EXTINT9_1       (PORT_FUNCA | PORTA | PORT_PIN9)
+#define PORT_EXTINT9_2       (PORT_FUNCA | PORTB | PORT_PIN9)
+#define PORT_EXTINT10_1      (PORT_FUNCA | PORTA | PORT_PIN10)
+#define PORT_EXTINT10_2      (PORT_FUNCA | PORTA | PORT_PIN30)
+#define PORT_EXTINT10_3      (PORT_FUNCA | PORTB | PORT_PIN10)
+#define PORT_EXTINT11_1      (PORT_FUNCA | PORTA | PORT_PIN11)
+#define PORT_EXTINT11_2      (PORT_FUNCA | PORTA | PORT_PIN31)
+#define PORT_EXTINT11_3      (PORT_FUNCA | PORTB | PORT_PIN11)
+#define PORT_EXTINT12_1      (PORT_FUNCA | PORTA | PORT_PIN12)
+#define PORT_EXTINT12_2      (PORT_FUNCA | PORTA | PORT_PIN24)
+#define PORT_EXTINT12_3      (PORT_FUNCA | PORTB | PORT_PIN12)
+#define PORT_EXTINT13_1      (PORT_FUNCA | PORTA | PORT_PIN13)
+#define PORT_EXTINT13_2      (PORT_FUNCA | PORTA | PORT_PIN25)
+#define PORT_EXTINT13_3      (PORT_FUNCA | PORTB | PORT_PIN13)
+#define PORT_EXTINT14_1      (PORT_FUNCA | PORTA | PORT_PIN14)
+#define PORT_EXTINT14_2      (PORT_FUNCA | PORTB | PORT_PIN14)
+#define PORT_EXTINT14_3      (PORT_FUNCA | PORTB | PORT_PIN30)
+#define PORT_EXTINT15_1      (PORT_FUNCA | PORTA | PORT_PIN15)
+#define PORT_EXTINT15_2      (PORT_FUNCA | PORTA | PORT_PIN27)
+#define PORT_EXTINT15_3      (PORT_FUNCA | PORTB | PORT_PIN15)
+#define PORT_EXTINT15_4      (PORT_FUNCA | PORTB | PORT_PIN31)
+
+/* Generic clock controller I/O */
+
+#define PORT_GCLK_IO0_1      (PORT_FUNCH | PORTA | PORT_PIN14)
+#define PORT_GCLK_IO0_2      (PORT_FUNCH | PORTA | PORT_PIN27)
+#define PORT_GCLK_IO0_3      (PORT_FUNCH | PORTA | PORT_PIN28)
+#define PORT_GCLK_IO0_4      (PORT_FUNCH | PORTA | PORT_PIN30)
+#define PORT_GCLK_IO0_5      (PORT_FUNCH | PORTB | PORT_PIN14)
+#define PORT_GCLK_IO0_6      (PORT_FUNCH | PORTB | PORT_PIN22)
+#define PORT_GCLK_IO1_1      (PORT_FUNCH | PORTA | PORT_PIN15)
+#define PORT_GCLK_IO1_2      (PORT_FUNCH | PORTB | PORT_PIN15)
+#define PORT_GCLK_IO1_3      (PORT_FUNCH | PORTB | PORT_PIN23)
+#define PORT_GCLK_IO2_1      (PORT_FUNCH | PORTA | PORT_PIN16)
+#define PORT_GCLK_IO2_2      (PORT_FUNCH | PORTB | PORT_PIN16)
+#define PORT_GCLK_IO3_1      (PORT_FUNCH | PORTA | PORT_PIN17)
+#define PORT_GCLK_IO3_2      (PORT_FUNCH | PORTB | PORT_PIN17)
+#define PORT_GCLK_IO4_1      (PORT_FUNCH | PORTA | PORT_PIN10)
+#define PORT_GCLK_IO4_2      (PORT_FUNCH | PORTA | PORT_PIN20)
+#define PORT_GCLK_IO4_3      (PORT_FUNCH | PORTB | PORT_PIN10)
+#define PORT_GCLK_IO5_1      (PORT_FUNCH | PORTA | PORT_PIN11)
+#define PORT_GCLK_IO5_2      (PORT_FUNCH | PORTA | PORT_PIN21)
+#define PORT_GCLK_IO5_3      (PORT_FUNCH | PORTB | PORT_PIN11)
+#define PORT_GCLK_IO6_1      (PORT_FUNCH | PORTA | PORT_PIN22)
+#define PORT_GCLK_IO6_2      (PORT_FUNCH | PORTB | PORT_PIN12)
+#define PORT_GCLK_IO7_1      (PORT_FUNCH | PORTA | PORT_PIN23)
+#define PORT_GCLK_IO7_2      (PORT_FUNCH | PORTB | PORT_PIN13)
+
+/* No maskable interrupt */
+
+#define PORT_NMI             (PORT_FUNCA | PORTA | PORT_PIN8)
+
+/* Serial communication interface (SERCOM) */
+
+#define PORT_SERCOM0_PAD0_1  (PORT_FUNCC | PORTA | PORT_PIN8)
+#define PORT_SERCOM0_PAD0_2  (PORT_FUNCD | PORTA | PORT_PIN4)
+#define PORT_SERCOM0_PAD1_1  (PORT_FUNCC | PORTA | PORT_PIN9)
+#define PORT_SERCOM0_PAD1_2  (PORT_FUNCD | PORTA | PORT_PIN5)
+#define PORT_SERCOM0_PAD2_1  (PORT_FUNCC | PORTA | PORT_PIN10)
+#define PORT_SERCOM0_PAD2_2  (PORT_FUNCD | PORTA | PORT_PIN6)
+#define PORT_SERCOM0_PAD3_1  (PORT_FUNCC | PORTA | PORT_PIN11)
+#define PORT_SERCOM0_PAD3_2  (PORT_FUNCD | PORTA | PORT_PIN7)
+#define PORT_SERCOM1_PAD0_1  (PORT_FUNCC | PORTA | PORT_PIN16)
+#define PORT_SERCOM1_PAD0_2  (PORT_FUNCD | PORTA | PORT_PIN0)
+#define PORT_SERCOM1_PAD1_1  (PORT_FUNCC | PORTA | PORT_PIN17)
+#define PORT_SERCOM1_PAD1_2  (PORT_FUNCD | PORTA | PORT_PIN1)
+#define PORT_SERCOM1_PAD2_1  (PORT_FUNCC | PORTA | PORT_PIN18)
+#define PORT_SERCOM1_PAD2_2  (PORT_FUNCD | PORTA | PORT_PIN30)
+#define PORT_SERCOM1_PAD3_1  (PORT_FUNCC | PORTA | PORT_PIN19)
+#define PORT_SERCOM1_PAD3_2  (PORT_FUNCD | PORTA | PORT_PIN31)
+#define PORT_SERCOM2_PAD0_1  (PORT_FUNCC | PORTA | PORT_PIN12)
+#define PORT_SERCOM2_PAD0_2  (PORT_FUNCD | PORTA | PORT_PIN8)
+#define PORT_SERCOM2_PAD1_1  (PORT_FUNCC | PORTA | PORT_PIN13)
+#define PORT_SERCOM2_PAD1_2  (PORT_FUNCD | PORTA | PORT_PIN9)
+#define PORT_SERCOM2_PAD2_1  (PORT_FUNCC | PORTA | PORT_PIN14)
+#define PORT_SERCOM2_PAD2_2  (PORT_FUNCD | PORTA | PORT_PIN10)
+#define PORT_SERCOM2_PAD3_1  (PORT_FUNCC | PORTA | PORT_PIN15)
+#define PORT_SERCOM2_PAD3_2  (PORT_FUNCD | PORTA | PORT_PIN11)
+#define PORT_SERCOM3_PAD0_1  (PORT_FUNCC | PORTA | PORT_PIN22)
+#define PORT_SERCOM3_PAD0_2  (PORT_FUNCD | PORTA | PORT_PIN16)
+#define PORT_SERCOM3_PAD1_1  (PORT_FUNCC | PORTA | PORT_PIN23)
+#define PORT_SERCOM3_PAD1_2  (PORT_FUNCD | PORTA | PORT_PIN17)
+#define PORT_SERCOM3_PAD2_1  (PORT_FUNCC | PORTA | PORT_PIN24)
+#define PORT_SERCOM3_PAD2_2  (PORT_FUNCD | PORTA | PORT_PIN18)
+#define PORT_SERCOM3_PAD2_3  (PORT_FUNCD | PORTA | PORT_PIN20)
+#define PORT_SERCOM3_PAD3_1  (PORT_FUNCC | PORTA | PORT_PIN25)
+#define PORT_SERCOM3_PAD3_2  (PORT_FUNCD | PORTA | PORT_PIN19)
+#define PORT_SERCOM3_PAD3_3  (PORT_FUNCD | PORTA | PORT_PIN21)
+#define PORT_SERCOM4_PAD0_1  (PORT_FUNCC | PORTB | PORT_PIN12)
+#define PORT_SERCOM4_PAD0_2  (PORT_FUNCD | PORTA | PORT_PIN12)
+#define PORT_SERCOM4_PAD0_3  (PORT_FUNCD | PORTB | PORT_PIN8)
+#define PORT_SERCOM4_PAD1_1  (PORT_FUNCC | PORTB | PORT_PIN13)
+#define PORT_SERCOM4_PAD1_2  (PORT_FUNCD | PORTA | PORT_PIN13)
+#define PORT_SERCOM4_PAD1_3  (PORT_FUNCD | PORTB | PORT_PIN9)
+#define PORT_SERCOM4_PAD2_1  (PORT_FUNCC | PORTB | PORT_PIN14)
+#define PORT_SERCOM4_PAD2_2  (PORT_FUNCD | PORTA | PORT_PIN14)
+#define PORT_SERCOM4_PAD2_3  (PORT_FUNCD | PORTB | PORT_PIN10)
+#define PORT_SERCOM4_PAD3_1  (PORT_FUNCC | PORTB | PORT_PIN15)
+#define PORT_SERCOM4_PAD3_2  (PORT_FUNCD | PORTA | PORT_PIN15)
+#define PORT_SERCOM4_PAD3_3  (PORT_FUNCD | PORTB | PORT_PIN11)
+#define PORT_SERCOM5_PAD0_1  (PORT_FUNCC | PORTB | PORT_PIN16)
+#define PORT_SERCOM5_PAD0_2  (PORT_FUNCD | PORTA | PORT_PIN22)
+#define PORT_SERCOM5_PAD0_3  (PORT_FUNCD | PORTB | PORT_PIN2)
+#define PORT_SERCOM5_PAD0_4  (PORT_FUNCD | PORTB | PORT_PIN30)
+#define PORT_SERCOM5_PAD1_1  (PORT_FUNCC | PORTB | PORT_PIN17)
+#define PORT_SERCOM5_PAD1_2  (PORT_FUNCD | PORTA | PORT_PIN23)
+#define PORT_SERCOM5_PAD1_3  (PORT_FUNCD | PORTB | PORT_PIN3)
+#define PORT_SERCOM5_PAD1_4  (PORT_FUNCD | PORTB | PORT_PIN31)
+#define PORT_SERCOM5_PAD2_1  (PORT_FUNCC | PORTA | PORT_PIN20)
+#define PORT_SERCOM5_PAD2_2  (PORT_FUNCD | PORTA | PORT_PIN24)
+#define PORT_SERCOM5_PAD2_3  (PORT_FUNCD | PORTB | PORT_PIN0)
+#define PORT_SERCOM5_PAD2_4  (PORT_FUNCD | PORTB | PORT_PIN22)
+#define PORT_SERCOM5_PAD3_1  (PORT_FUNCC | PORTA | PORT_PIN21)
+#define PORT_SERCOM5_PAD3_2  (PORT_FUNCD | PORTA | PORT_PIN25)
+#define PORT_SERCOM5_PAD3_3  (PORT_FUNCD | PORTB | PORT_PIN1)
+#define PORT_SERCOM5_PAD3_4  (PORT_FUNCD | PORTB | PORT_PIN23)
+
+/* JTAG/SWI */
+
+#define PORT_SWCLK           (PORT_FUNCG | PORTA | PORT_PIN30)
+#define PORT_SWDIO           (PORT_FUNCG | PORTA | PORT_PIN31)
+
+/* Timer/Counters */
+
+#define PORT_TC0_WO0_1       (PORT_FUNCE | PORTA | PORT_PIN8)
+#define PORT_TC0_WO0_2       (PORT_FUNCF | PORTA | PORT_PIN4)
+#define PORT_TC0_WO0_3       (PORT_FUNCF | PORTB | PORT_PIN30)
+#define PORT_TC0_WO1_1       (PORT_FUNCE | PORTA | PORT_PIN9)
+#define PORT_TC0_WO1_2       (PORT_FUNCF | PORTA | PORT_PIN5)
+#define PORT_TC0_WO1_3       (PORT_FUNCF | PORTB | PORT_PIN31)
+#define PORT_TC1_WO0_1       (PORT_FUNCE | PORTA | PORT_PIN10)
+#define PORT_TC1_WO0_2       (PORT_FUNCF | PORTA | PORT_PIN30)
+#define PORT_TC1_WO0_3       (PORT_FUNCF | PORTA | PORT_PIN6)
+#define PORT_TC1_WO1_1       (PORT_FUNCE | PORTA | PORT_PIN11)
+#define PORT_TC1_WO1_2       (PORT_FUNCF | PORTA | PORT_PIN31)
+#define PORT_TC1_WO1_3       (PORT_FUNCF | PORTA | PORT_PIN7)
+#define PORT_TC2_WO0_1       (PORT_FUNCE | PORTA | PORT_PIN12)
+#define PORT_TC2_WO0_2       (PORT_FUNCF | PORTA | PORT_PIN0)
+#define PORT_TC2_WO0_3       (PORT_FUNCF | PORTA | PORT_PIN16)
+#define PORT_TC2_WO1_1       (PORT_FUNCE | PORTA | PORT_PIN13)
+#define PORT_TC2_WO1_2       (PORT_FUNCF | PORTA | PORT_PIN1)
+#define PORT_TC2_WO1_3       (PORT_FUNCF | PORTA | PORT_PIN17)
+#define PORT_TC3_WO0_1       (PORT_FUNCE | PORTA | PORT_PIN14)
+#define PORT_TC3_WO0_2       (PORT_FUNCF | PORTA | PORT_PIN18)
+#define PORT_TC3_WO1_1       (PORT_FUNCE | PORTA | PORT_PIN15)
+#define PORT_TC3_WO1_2       (PORT_FUNCF | PORTA | PORT_PIN19)
+#define PORT_TC4_WO0_1       (PORT_FUNCE | PORTB | PORT_PIN12)
+#define PORT_TC4_WO0_2       (PORT_FUNCF | PORTA | PORT_PIN22)
+#define PORT_TC4_WO0_3       (PORT_FUNCF | PORTB | PORT_PIN8)
+#define PORT_TC4_WO1_1       (PORT_FUNCE | PORTB | PORT_PIN13)
+#define PORT_TC4_WO1_2       (PORT_FUNCF | PORTA | PORT_PIN23)
+#define PORT_TC4_WO1_3       (PORT_FUNCF | PORTB | PORT_PIN9)
+#define PORT_TC5_WO0_1       (PORT_FUNCE | PORTB | PORT_PIN14)
+#define PORT_TC5_WO0_2       (PORT_FUNCF | PORTA | PORT_PIN24)
+#define PORT_TC5_WO0_3       (PORT_FUNCF | PORTB | PORT_PIN10)
+#define PORT_TC5_WO1_1       (PORT_FUNCE | PORTB | PORT_PIN15)
+#define PORT_TC5_WO1_2       (PORT_FUNCF | PORTA | PORT_PIN25)
+#define PORT_TC5_WO1_3       (PORT_FUNCF | PORTB | PORT_PIN11)
+#define PORT_TC6_WO0_1       (PORT_FUNCE | PORTB | PORT_PIN16)
+#define PORT_TC6_WO0_2       (PORT_FUNCF | PORTB | PORT_PIN2)
+#define PORT_TC6_WO1_1       (PORT_FUNCE | PORTB | PORT_PIN17)
+#define PORT_TC6_WO1_2       (PORT_FUNCF | PORTB | PORT_PIN3)
+#define PORT_TC7_WO0_1       (PORT_FUNCE | PORTA | PORT_PIN20)
+#define PORT_TC7_WO0_2       (PORT_FUNCF | PORTB | PORT_PIN0)
+#define PORT_TC7_WO0_3       (PORT_FUNCF | PORTB | PORT_PIN22)
+#define PORT_TC7_WO1_1       (PORT_FUNCE | PORTA | PORT_PIN21)
+#define PORT_TC7_WO1_2       (PORT_FUNCF | PORTB | PORT_PIN1)
+#define PORT_TC7_WO1_3       (PORT_FUNCF | PORTB | PORT_PIN23)
+
+/* Peripheral touch controller */
+
+#define PORT_PTC_X0          (PORT_FUNCB | PORTA | PORT_PIN8)
+#define PORT_PTC_X1          (PORT_FUNCB | PORTA | PORT_PIN9)
+#define PORT_PTC_X2          (PORT_FUNCB | PORTA | PORT_PIN10)
+#define PORT_PTC_X3          (PORT_FUNCB | PORTA | PORT_PIN11)
+#define PORT_PTC_X4          (PORT_FUNCB | PORTA | PORT_PIN16)
+#define PORT_PTC_X5          (PORT_FUNCB | PORTA | PORT_PIN17)
+#define PORT_PTC_X6          (PORT_FUNCB | PORTA | PORT_PIN18)
+#define PORT_PTC_X7          (PORT_FUNCB | PORTA | PORT_PIN19)
+#define PORT_PTC_X8          (PORT_FUNCB | PORTA | PORT_PIN20)
+#define PORT_PTC_X9          (PORT_FUNCB | PORTA | PORT_PIN21)
+#define PORT_PTC_X10         (PORT_FUNCB | PORTA | PORT_PIN22)
+#define PORT_PTC_X11         (PORT_FUNCB | PORTA | PORT_PIN23)
+#define PORT_PTC_X12         (PORT_FUNCB | PORTB | PORT_PIN12)
+#define PORT_PTC_X13         (PORT_FUNCB | PORTB | PORT_PIN13)
+#define PORT_PTC_X14         (PORT_FUNCB | PORTB | PORT_PIN14)
+#define PORT_PTC_X15         (PORT_FUNCB | PORTB | PORT_PIN15)
 
-#warning Missing logic
+#define PORT_PTC_Y0          (PORT_FUNCB | PORTA | PORT_PIN2)
+#define PORT_PTC_Y1          (PORT_FUNCB | PORTA | PORT_PIN3)
+#define PORT_PTC_Y2          (PORT_FUNCB | PORTA | PORT_PIN4)
+#define PORT_PTC_Y3          (PORT_FUNCB | PORTA | PORT_PIN5)
+#define PORT_PTC_Y4          (PORT_FUNCB | PORTA | PORT_PIN6)
+#define PORT_PTC_Y5          (PORT_FUNCB | PORTA | PORT_PIN7)
+#define PORT_PTC_Y6          (PORT_FUNCB | PORTB | PORT_PIN0)
+#define PORT_PTC_Y7          (PORT_FUNCB | PORTB | PORT_PIN1)
+#define PORT_PTC_Y8          (PORT_FUNCB | PORTB | PORT_PIN2)
+#define PORT_PTC_Y9          (PORT_FUNCB | PORTB | PORT_PIN3)
+#define PORT_PTC_Y10         (PORT_FUNCB | PORTB | PORT_PIN4)
+#define PORT_PTC_Y11         (PORT_FUNCB | PORTB | PORT_PIN5)
+#define PORT_PTC_Y12         (PORT_FUNCB | PORTB | PORT_PIN6)
+#define PORT_PTC_Y13         (PORT_FUNCB | PORTB | PORT_PIN7)
+#define PORT_PTC_Y14         (PORT_FUNCB | PORTB | PORT_PIN8)
+#define PORT_PTC_Y15         (PORT_FUNCB | PORTB | PORT_PIN9)
 
 /********************************************************************************************
  * Public Types
diff --git a/nuttx/arch/arm/src/samd/chip/samd_port.h b/nuttx/arch/arm/src/samd/chip/samd_port.h
deleted file mode 100755
index 662099817..000000000
--- a/nuttx/arch/arm/src/samd/chip/samd_port.h
+++ /dev/null
@@ -1,249 +0,0 @@
-/********************************************************************************************
- * arch/arm/src/samd/chip/sam_port.h
- *
- *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ********************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_SAMD_CHIP_SAM_PORT_H
-#define __ARCH_ARM_SRC_SAMD_CHIP_SAM_PORT_H
-
-/********************************************************************************************
- * Included Files
- ********************************************************************************************/
-
-#include <nuttx/config.h>
-
-#include "chip.h"
-
-/********************************************************************************************
- * Pre-processor Definitions
- ********************************************************************************************/
-/* PORT register offsets ********************************************************************/
-
-#define SAM_PORT_DIR_OFFSET       0x0000 /* Data direction register */
-#define SAM_PORT_DIRCLR_OFFSET    0x0004 /* Data direction clear register */
-#define SAM_PORT_DIRSET_OFFSET    0x0008 /* Data direction set register */
-#define SAM_PORT_DIRTGL_OFFSET    0x000c /* Data direction toggle register */
-#define SAM_PORT_OUT_OFFSET       0x0010 /* Data output value register */
-#define SAM_PORT_OUTCLR_OFFSET    0x0014 /* Data output value clear register */
-#define SAM_PORT_OUTSET_OFFSET    0x0018 /* Data output value set register */
-#define SAM_PORT_OUTTGL_OFFSET    0x001c /* Data output value toggle register */
-#define SAM_PORT_IN_OFFSET        0x0020 /* Data input value register */
-#define SAM_PORT_CTRL_OFFSET      0x0024 /* Control register */
-#define SAM_PORT_WRCONFIG_OFFSET  0x0028 /* Write configuration registers */
-
-#define SAM_PORT_PMUX_OFFSET(n)   (0x0030+((n)>>1))
-#define SAM_PORT_PMUX0_OFFSET     0x0030 /* Peripheral multiplexing register 0 */
-#define SAM_PORT_PMUX1_OFFSET     0x0031 /* Peripheral multiplexing register 1 */
-#define SAM_PORT_PMUX2_OFFSET     0x0032 /* Peripheral multiplexing register 2 */
-#define SAM_PORT_PMUX3_OFFSET     0x0033 /* Peripheral multiplexing register 3 */
-#define SAM_PORT_PMUX4_OFFSET     0x0034 /* Peripheral multiplexing register 4 */
-#define SAM_PORT_PMUX5_OFFSET     0x0035 /* Peripheral multiplexing register 5 */
-#define SAM_PORT_PMUX6_OFFSET     0x0036 /* Peripheral multiplexing register 6 */
-#define SAM_PORT_PMUX7_OFFSET     0x0037 /* Peripheral multiplexing register 7 */
-#define SAM_PORT_PMUX8_OFFSET     0x0038 /* Peripheral multiplexing register 8 */
-#define SAM_PORT_PMUX9_OFFSET     0x0039 /* Peripheral multiplexing register 9 */
-#define SAM_PORT_PMUX10_OFFSET    0x003a /* Peripheral multiplexing register 10 */
-#define SAM_PORT_PMUX11_OFFSET    0x003b /* Peripheral multiplexing register 11 */
-#define SAM_PORT_PMUX12_OFFSET    0x003c /* Peripheral multiplexing register 12 */
-#define SAM_PORT_PMUX13_OFFSET    0x003d /* Peripheral multiplexing register 13 */
-#define SAM_PORT_PMUX14_OFFSET    0x003e /* Peripheral multiplexing register 14 */
-#define SAM_PORT_PMUX15_OFFSET    0x003f /* Peripheral multiplexing register 15 */
-
-#define SAM_PORT_PINCFG_OFFSET(n) (0x0040+(n))
-#define SAM_PORT_PINCFG0_OFFSET   0x0040 /* Pin configuration register 0 */
-#define SAM_PORT_PINCFG1_OFFSET   0x0041 /* Pin configuration register 1 */
-#define SAM_PORT_PINCFG2_OFFSET   0x0042 /* Pin configuration register 2 */
-#define SAM_PORT_PINCFG3_OFFSET   0x0043 /* Pin configuration register 3 */
-#define SAM_PORT_PINCFG4_OFFSET   0x0044 /* Pin configuration register 4 */
-#define SAM_PORT_PINCFG5_OFFSET   0x0045 /* Pin configuration register 5 */
-#define SAM_PORT_PINCFG6_OFFSET   0x0046 /* Pin configuration register 6 */
-#define SAM_PORT_PINCFG7_OFFSET   0x0047 /* Pin configuration register 7 */
-#define SAM_PORT_PINCFG8_OFFSET   0x0048 /* Pin configuration register 8 */
-#define SAM_PORT_PINCFG9_OFFSET   0x0049 /* Pin configuration register 9 */
-#define SAM_PORT_PINCFG10_OFFSET  0x004a /* Pin configuration register 10 */
-#define SAM_PORT_PINCFG11_OFFSET  0x004b /* Pin configuration register 11 */
-#define SAM_PORT_PINCFG12_OFFSET  0x004c /* Pin configuration register 12 */
-#define SAM_PORT_PINCFG13_OFFSET  0x004d /* Pin configuration register 13 */
-#define SAM_PORT_PINCFG14_OFFSET  0x004e /* Pin configuration register 14 */
-#define SAM_PORT_PINCFG15_OFFSET  0x004f /* Pin configuration register 15 */
-#define SAM_PORT_PINCFG16_OFFSET  0x0050 /* Pin configuration register 16 */
-#define SAM_PORT_PINCFG17_OFFSET  0x0051 /* Pin configuration register 17 */
-#define SAM_PORT_PINCFG18_OFFSET  0x0052 /* Pin configuration register 18 */
-#define SAM_PORT_PINCFG19_OFFSET  0x0053 /* Pin configuration register 19 */
-#define SAM_PORT_PINCFG20_OFFSET  0x0054 /* Pin configuration register 20 */
-#define SAM_PORT_PINCFG21_OFFSET  0x0055 /* Pin configuration register 21 */
-#define SAM_PORT_PINCFG22_OFFSET  0x0056 /* Pin configuration register 22 */
-#define SAM_PORT_PINCFG23_OFFSET  0x0057 /* Pin configuration register 23 */
-#define SAM_PORT_PINCFG24_OFFSET  0x0058 /* Pin configuration register 24 */
-#define SAM_PORT_PINCFG25_OFFSET  0x0059 /* Pin configuration register 25 */
-#define SAM_PORT_PINCFG26_OFFSET  0x005a /* Pin configuration register 26 */
-#define SAM_PORT_PINCFG27_OFFSET  0x005b /* Pin configuration register 27 */
-#define SAM_PORT_PINCFG28_OFFSET  0x005c /* Pin configuration register 28 */
-#define SAM_PORT_PINCFG29_OFFSET  0x005d /* Pin configuration register 29 */
-#define SAM_PORT_PINCFG30_OFFSET  0x005e /* Pin configuration register 30 */
-#define SAM_PORT_PINCFG31_OFFSET  0x005f /* Pin configuration register 31 */
-
-/* PORT register addresses ******************************************************************/
-
-#define SAM_PORT_DIR              (SAM_PORT_BASE+SAM_PORT_DIR_OFFSET)
-#define SAM_PORT_DIRCLR           (SAM_PORT_BASE+SAM_PORT_DIRCLR_OFFSET)
-#define SAM_PORT_DIRSET           (SAM_PORT_BASE+SAM_PORT_DIRSET_OFFSET)
-#define SAM_PORT_DIRTGL           (SAM_PORT_BASE+SAM_PORT_DIRTGL_OFFSET)
-#define SAM_PORT_OUT              (SAM_PORT_BASE+SAM_PORT_OUT_OFFSET)
-#define SAM_PORT_OUTCLR           (SAM_PORT_BASE+SAM_PORT_OUTCLR_OFFSET)
-#define SAM_PORT_OUTSET           (SAM_PORT_BASE+SAM_PORT_OUTSET_OFFSET)
-#define SAM_PORT_OUTTGL           (SAM_PORT_BASE+SAM_PORT_OUTTGL_OFFSET)
-#define SAM_PORT_IN               (SAM_PORT_BASE+SAM_PORT_IN_OFFSET)
-#define SAM_PORT_CTRL             (SAM_PORT_BASE+SAM_PORT_CTRL_OFFSET)
-#define SAM_PORT_WRCONFIG         (SAM_PORT_BASE+SAM_PORT_WRCONFIG_OFFSET)
-
-#define SAM_PORT_PMUX(n)          (SAM_PORT_BASE+SAM_PORT_PMUX_OFFSET(n))
-#define SAM_PORT_PMUX0            (SAM_PORT_BASE+SAM_PORT_PMUX0_OFFSET)
-#define SAM_PORT_PMUX1            (SAM_PORT_BASE+SAM_PORT_PMUX1_OFFSET)
-#define SAM_PORT_PMUX2            (SAM_PORT_BASE+SAM_PORT_PMUX2_OFFSET)
-#define SAM_PORT_PMUX3            (SAM_PORT_BASE+SAM_PORT_PMUX3_OFFSET)
-#define SAM_PORT_PMUX4            (SAM_PORT_BASE+SAM_PORT_PMUX4_OFFSET)
-#define SAM_PORT_PMUX5            (SAM_PORT_BASE+SAM_PORT_PMUX5_OFFSET)
-#define SAM_PORT_PMUX6            (SAM_PORT_BASE+SAM_PORT_PMUX6_OFFSET)
-#define SAM_PORT_PMUX7            (SAM_PORT_BASE+SAM_PORT_PMUX7_OFFSET)
-#define SAM_PORT_PMUX8            (SAM_PORT_BASE+SAM_PORT_PMUX8_OFFSET)
-#define SAM_PORT_PMUX9            (SAM_PORT_BASE+SAM_PORT_PMUX9_OFFSET)
-#define SAM_PORT_PMUX10           (SAM_PORT_BASE+SAM_PORT_PMUX10_OFFSET)
-#define SAM_PORT_PMUX11           (SAM_PORT_BASE+SAM_PORT_PMUX11_OFFSET)
-#define SAM_PORT_PMUX12           (SAM_PORT_BASE+SAM_PORT_PMUX12_OFFSET)
-#define SAM_PORT_PMUX13           (SAM_PORT_BASE+SAM_PORT_PMUX13_OFFSET)
-#define SAM_PORT_PMUX14           (SAM_PORT_BASE+SAM_PORT_PMUX14_OFFSET)
-#define SAM_PORT_PMUX15           (SAM_PORT_BASE+SAM_PORT_PMUX15_OFFSET)
-
-#define SAM_PORT_PINCFG(n)        (SAM_PORT_BASE+SAM_PORT_PINCFG_OFFSET(n))
-#define SAM_PORT_PINCFG0          (SAM_PORT_BASE+SAM_PORT_PINCFG0_OFFSET)
-#define SAM_PORT_PINCFG1          (SAM_PORT_BASE+SAM_PORT_PINCFG1_OFFSET)
-#define SAM_PORT_PINCFG2          (SAM_PORT_BASE+SAM_PORT_PINCFG2_OFFSET)
-#define SAM_PORT_PINCFG3          (SAM_PORT_BASE+SAM_PORT_PINCFG3_OFFSET)
-#define SAM_PORT_PINCFG4          (SAM_PORT_BASE+SAM_PORT_PINCFG4_OFFSET)
-#define SAM_PORT_PINCFG5          (SAM_PORT_BASE+SAM_PORT_PINCFG5_OFFSET)
-#define SAM_PORT_PINCFG6          (SAM_PORT_BASE+SAM_PORT_PINCFG6_OFFSET)
-#define SAM_PORT_PINCFG7          (SAM_PORT_BASE+SAM_PORT_PINCFG7_OFFSET)
-#define SAM_PORT_PINCFG8          (SAM_PORT_BASE+SAM_PORT_PINCFG8_OFFSET)
-#define SAM_PORT_PINCFG9          (SAM_PORT_BASE+SAM_PORT_PINCFG9_OFFSET)
-#define SAM_PORT_PINCFG10         (SAM_PORT_BASE+SAM_PORT_PINCFG10_OFFSET)
-#define SAM_PORT_PINCFG11         (SAM_PORT_BASE+SAM_PORT_PINCFG11_OFFSET)
-#define SAM_PORT_PINCFG12         (SAM_PORT_BASE+SAM_PORT_PINCFG12_OFFSET)
-#define SAM_PORT_PINCFG13         (SAM_PORT_BASE+SAM_PORT_PINCFG13_OFFSET)
-#define SAM_PORT_PINCFG14         (SAM_PORT_BASE+SAM_PORT_PINCFG14_OFFSET)
-#define SAM_PORT_PINCFG15         (SAM_PORT_BASE+SAM_PORT_PINCFG15_OFFSET)
-#define SAM_PORT_PINCFG16         (SAM_PORT_BASE+SAM_PORT_PINCFG16_OFFSET)
-#define SAM_PORT_PINCFG17         (SAM_PORT_BASE+SAM_PORT_PINCFG17_OFFSET)
-#define SAM_PORT_PINCFG18         (SAM_PORT_BASE+SAM_PORT_PINCFG18_OFFSET)
-#define SAM_PORT_PINCFG19         (SAM_PORT_BASE+SAM_PORT_PINCFG19_OFFSET)
-#define SAM_PORT_PINCFG20         (SAM_PORT_BASE+SAM_PORT_PINCFG20_OFFSET)
-#define SAM_PORT_PINCFG21         (SAM_PORT_BASE+SAM_PORT_PINCFG21_OFFSET)
-#define SAM_PORT_PINCFG22         (SAM_PORT_BASE+SAM_PORT_PINCFG22_OFFSET)
-#define SAM_PORT_PINCFG23         (SAM_PORT_BASE+SAM_PORT_PINCFG23_OFFSET)
-#define SAM_PORT_PINCFG24         (SAM_PORT_BASE+SAM_PORT_PINCFG24_OFFSET)
-#define SAM_PORT_PINCFG25         (SAM_PORT_BASE+SAM_PORT_PINCFG25_OFFSET)
-#define SAM_PORT_PINCFG26         (SAM_PORT_BASE+SAM_PORT_PINCFG26_OFFSET)
-#define SAM_PORT_PINCFG27         (SAM_PORT_BASE+SAM_PORT_PINCFG27_OFFSET)
-#define SAM_PORT_PINCFG28         (SAM_PORT_BASE+SAM_PORT_PINCFG28_OFFSET)
-#define SAM_PORT_PINCFG29         (SAM_PORT_BASE+SAM_PORT_PINCFG29_OFFSET)
-#define SAM_PORT_PINCFG30         (SAM_PORT_BASE+SAM_PORT_PINCFG30_OFFSET)
-#define SAM_PORT_PINCFG31         (SAM_PORT_BASE+SAM_PORT_PINCFG31_OFFSET)
-
-/* PORT register bit definitions ************************************************************/
-
-/* Data direction, data direction clear,  data direction set, and data direction toggle
- * registers
- */
-
-#define PORT_DIR(n)               (1 << n) /* Port data n, direction, n=0-31 */
-
-/* Data output value, data output value clear, data output value set, and data output
- * value toggle registers
- */
-
-#define PORT_OUT(n)               (1 << n) /* Port data n output value, n=0-31 */
-
-/* Data input value register */
-
-#define PORT_IN(n)                (1 << n) /* Port n data input value, n=0-31 */
-
-/* Control register */
-
-#define PORT_CTRL(n)              (1 << n) /* Port n input sampling mode, n=0-31 */
-
-/* Write configuration registers */
-
-#define PORT_WRCONFIG_PINMASK_SHIFT (0) /* Bits 0-15:  Pin Mask for Multiple Pin Configuration */
-#define PORT_WRCONFIG_PINMASK_MASK  (0xffff << PORT_WRCONFIG_PINMASK_SHIFT)
-#  define PORT_WRCONFIG_PINMASK(n)  (1 << (PORT_WRCONFIG_PINMASK_SHIFT+(n)))
-#define PORT_WRCONFIG_PMUXEN      (1 << 16) /* Bit 16: Peripheral Multiplexer Enable */
-#define PORT_WRCONFIG_INEN        (1 << 17) /* Bit 17: Input Enable */
-#define PORT_WRCONFIG_PULLEN      (1 << 18) /* Bit 18: Pull Enable */
-#define PORT_WRCONFIG_DRVSTR      (1 << 22) /* Bit 22: Output Driver Strength Selection */
-#define PORT_WRCONFIG_PMUX_SHIFT  (24)      /* Bits 24-27: Peripheral Multiplexing */
-#define PORT_WRCONFIG_PMUX_MASK   (15 << PORT_WRCONFIG_PMUX_SHIFT)
-#define PORT_WRCONFIG_WRPMUX      (1 << 28) /* Bit 28: Write PMUX */
-#define PORT_WRCONFIG_WRPINCFG    (1 << 30) /* Bit 30: Write PINCFG */
-#define PORT_WRCONFIG_HWSEL       (1 << 31) /* Bit 31: Half-Word Select */
-
-/* Peripheral multiplexing registers */
-
-#define PORT_PMUX_PERIPHA         0x00      /* Peripheral function A */
-#define PORT_PMUX_PERIPHB         0x01      /* Peripheral function B */
-#define PORT_PMUX_PERIPHC         0x02      /* Peripheral function C */
-#define PORT_PMUX_PERIPHD         0x03      /* Peripheral function D */
-#define PORT_PMUX_PERIPHE         0x04      /* Peripheral function E */
-#define PORT_PMUX_PERIPHF         0x05      /* Peripheral function F */
-#define PORT_PMUX_PERIPHG         0x06      /* Peripheral function G */
-#define PORT_PMUX_PERIPHH         0x07      /* Peripheral function H */
-
-/* Pin configuration registers */
-
-#define PORT_PINCFG_PMUXEN        (1 << 0)  /* Bit 0: Peripheral Multiplexer Enable */
-#define PORT_PINCFG_INEN          (1 << 1)  /* Bit 1: Input Enable */
-#define PORT_PINCFG_PULLEN        (1 << 2)  /* Bit 2: Pull Enable */
-#define PORT_PINCFG_DRVSTR        (1 << 6)  /* Bit 6: Output Driver Strength Selection */
-
-/********************************************************************************************
- * Public Types
- ********************************************************************************************/
-
-/********************************************************************************************
- * Public Data
- ********************************************************************************************/
-
-/********************************************************************************************
- * Public Functions
- ********************************************************************************************/
-
-#endif /* __ARCH_ARM_SRC_SAMD_CHIP_SAM_PORT_H */
diff --git a/nuttx/arch/arm/src/samd/sam_port.h b/nuttx/arch/arm/src/samd/sam_port.h
index a2e8032ed..a9223b05a 100644
--- a/nuttx/arch/arm/src/samd/sam_port.h
+++ b/nuttx/arch/arm/src/samd/sam_port.h
@@ -253,10 +253,10 @@
  *   Peripheral:  .... .... .... .... ..P. ....
  */
 
-#define PORT_PORT_SHIFT            (5)         /* Bit 5:  Port number */
-#define PORT_PORT_MASK             (1 << PORT_PORT_SHIFT)
-#  define PORT_PORTA               (0 << PORT_PORT_SHIFT)
-#  define PORT_PORTB               (1 << PORT_PORT_SHIFT)
+#define PORT_SHIFT                 (5)         /* Bit 5:  Port number */
+#define PORT_MASK                  (1 << PORT_SHIFT)
+#  define PORTA                    (0 << PORT_SHIFT)
+#  define PORTB                    (1 << PORT_SHIFT)
 
 /* This identifies the bit in the port:
  *
@@ -309,8 +309,7 @@
  * Public Types
  ****************************************************************************/
 
-typedef uint16_t port_cfgset_t;
-#warning REVISIT
+typedef uint32_t port_cfgset_t;
 
 /****************************************************************************
  * Public Data
diff --git a/nuttx/configs/samd20-xplained/src/samd20-xplained.h b/nuttx/configs/samd20-xplained/src/samd20-xplained.h
index 3f4aaff54..4bf014ddc 100644
--- a/nuttx/configs/samd20-xplained/src/samd20-xplained.h
+++ b/nuttx/configs/samd20-xplained/src/samd20-xplained.h
@@ -82,7 +82,7 @@
  */
 
 #define PORT_STATUS_LED (PORT_OUTPUT | PORT_PULL_NONE | PORT_OUTPUT_SET | \
-                         PORT_PORTA | PORT_PIN14)
+                         PORTA | PORT_PIN14)
 
 /* Mechanical buttons:
  *
@@ -93,7 +93,7 @@
  *   PA15 SW0
  */
 
-#define PORT_SW0      (PORT_INTERRUPT | PORT_PULL_UP | PORT_PORTA | PORT_PIN15)
+#define PORT_SW0      (PORT_INTERRUPT | PORT_PULL_UP | PORTA | PORT_PIN15)
 #define IRQ_SW0       SAM_IRQ_PA15
 
 /* I/O1
@@ -127,11 +127,11 @@
 #    endif
 
 #    define PORT_SD_CD (PORT_INTERRUPT | PORT_INT_CHANGE | PORT_PULL_UP | \
-                        PORT_PORTF | PORT_PIN5)
+                        PORTF | PORT_PIN5)
 #    define IRQ_SD_CD   SAM_IRQ_PB5
 
 #    define PORT_SD_CS (PORT_OUTPUT | PORT_PULL_NONE | PORT_OUTPUT_SET | \
-                        PORT_PORTA | PORT_PIN5)
+                        PORTA | PORT_PIN5)
 #    define SD_CSNO    0
 
 #  elif defined(CONFIG_SAMD20_XPLAINED_IOMODULE_EXT2)
@@ -142,11 +142,11 @@
 #    endif
 
 #    define PORT_CD   (PORT_INTERRUPT | PORT_INT_CHANGE | PORT_PULL_UP | \
-                       PORT_PORTB | PORT_PIN15)
+                       PORTB | PORT_PIN15)
 #    define IRQ_CD     SAM_IRQ_PB15
 
 #    define PORT_SD_CS (PORT_OUTPUT | PORT_PULL_NONE | PORT_OUTPUT_SET | \
-                        PORT_PORTA | PORT_PIN17)
+                        PORTA | PORT_PIN17)
 #    define SD_CSNO    2
 
 #  else
@@ -195,11 +195,11 @@
 #    endif
 
 #    define PORT_OLED_DATA (PORT_OUTPUT | PORT_PULL_NONE | PORT_OUTPUT_CLEAR | \
-                            PORT_PORTB | PORT_PIN6)
+                            PORTB | PORT_PIN6)
 #    define PORT_OLED_RST  (PORT_OUTPUT | PORT_PULL_NONE | PORT_OUTPUT_CLEAR | \
-                            PORT_PORTB | PORT_PIN5)
+                            PORTB | PORT_PIN5)
 #    define PORT_OLED_CS   (PORT_OUTPUT | PORT_PULL_NONE | PORT_OUTPUT_SET | \
-                            PORT_PORTA | PORT_PIN5)
+                            PORTA | PORT_PIN5)
 #    define OLED_CSNO       0
 
 #  elif defined(CONFIG_SAMD20_XPLAINED_OLED1MODULE_EXT2)
@@ -210,11 +210,11 @@
 #    endif
 
 #    define PORT_OLED_DATA (PORT_OUTPUT | PORT_PULL_NONE | PORT_OUTPUT_CLEAR | \
-                            PORT_PORTA | PORT_PIN20)
+                            PORTA | PORT_PIN20)
 #    define PORT_OLED_RST  (PORT_OUTPUT | PORT_PULL_NONE | PORT_OUTPUT_CLEAR | \
-                            PORT_PORTB | PORT_PIN15)
+                            PORTB | PORT_PIN15)
 #    define PORT_OLED_CS   (PORT_OUTPUT | PORT_PULL_NONE | PORT_OUTPUT_SET | \
-                            PORT_PORTA | PORT_PIN17)
+                            PORTA | PORT_PIN17)
 #    define OLED_CSNO      2
 
 #  else
@@ -224,7 +224,7 @@
 
 #if defined(CONFIG_LCD_UG2864AMBAG01) || defined(CONFIG_LCD_UG2864HSWEG01)
 #    define PORT_SD_CS (PORT_OUTPUT | PORT_PULL_NONE | PORT_OUTPUT_SET | \
-                        PORT_PORTB | PORT_PIN11) /* REVISIT */
+                        PORTB | PORT_PIN11) /* REVISIT */
 #endif
 
 /************************************************************************************