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authorGregory Nutt <gnutt@nuttx.org>2013-10-29 16:57:06 -0600
committerGregory Nutt <gnutt@nuttx.org>2013-10-29 16:57:06 -0600
commit356deb76216e0226ec205833975e6097cdf458ae (patch)
tree1b8f3b8cf752aa019c6cb2ee363112f3907fb07e
parent3e5f4e594f86b5617dcbea5eeefa73ec314c2a3a (diff)
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Minor changes while pondering a camera interface
-rw-r--r--nuttx/arch/Kconfig4
-rw-r--r--nuttx/arch/arm/src/sama5/chip/sam_isi.h21
-rw-r--r--nuttx/arch/arm/src/sama5/chip/sama5d3x_pinmap.h4
-rw-r--r--nuttx/configs/sama5d3x-ek/README.txt38
-rw-r--r--nuttx/include/nuttx/spi/spi.h1
5 files changed, 64 insertions, 4 deletions
diff --git a/nuttx/arch/Kconfig b/nuttx/arch/Kconfig
index 2c81f17ca..37b3e4d1a 100644
--- a/nuttx/arch/Kconfig
+++ b/nuttx/arch/Kconfig
@@ -296,5 +296,5 @@ config FLASH_SIZE
The size in bytes of the installed boot FLASH. "Boot" FLASH
refers to the FLASH that you link program code into.
-endif
-endmenu
+endif # BOOT_RUNFROMFLASH && ARCH_HAVE_MMU
+endmenu # Boot Memory Configuration
diff --git a/nuttx/arch/arm/src/sama5/chip/sam_isi.h b/nuttx/arch/arm/src/sama5/chip/sam_isi.h
index dc2fb1db3..fe8ebddb9 100644
--- a/nuttx/arch/arm/src/sama5/chip/sam_isi.h
+++ b/nuttx/arch/arm/src/sama5/chip/sam_isi.h
@@ -325,4 +325,25 @@
# define ISI_WPSR_WPVSRC_R2Y_SET1 (8 << ISI_WPSR_WPVSRC_SHIFT) /* Write access in ISI_R2Y_SET1 */
# define ISI_WPSR_WPVSRC_R2Y_SET2 (9 << ISI_WPSR_WPVSRC_SHIFT) /* Write access in ISI_R2Y_SET2 */
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+/* "The destination frame buffers are defined by a series of Frame Buffer Descriptors
+ * (FBD). Each FBD controls the transfer of one entire frame and then optionally
+ * loads a further FBD to switch the DMA operation at another frame buffer address.
+ *
+ * "The FBD is defined by a series of three words. The first one defines the current
+ * frame buffer address (named DMA_X_ADDR register), the second defines control
+ * information (named DMA_X_CTRL register) and the third defines the next descriptor
+ * address (named DMA_X_DSCR). DMA transfer mode with linked list support is
+ * available for both codec and preview datapath."
+ */
+
+struct isi_dscr_s
+{
+ uint32_t addr; /* Current framebuffer address */
+ uint32_t ctrl; /* Control information */
+ uint32_t dscr; /* Next descriptor address */
+};
+
#endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_ISI_H */
diff --git a/nuttx/arch/arm/src/sama5/chip/sama5d3x_pinmap.h b/nuttx/arch/arm/src/sama5/chip/sama5d3x_pinmap.h
index e94d35b4c..b9544671c 100644
--- a/nuttx/arch/arm/src/sama5/chip/sama5d3x_pinmap.h
+++ b/nuttx/arch/arm/src/sama5/chip/sama5d3x_pinmap.h
@@ -190,8 +190,6 @@
#define PIO_ISI_D0 (PIO_PERIPHC | PIO_CFG_DEFAULT | PIO_PORT_PIOA | PIO_PIN16) /* Type: GPIO */
#define PIO_ISI_D1 (PIO_PERIPHC | PIO_CFG_DEFAULT | PIO_PORT_PIOA | PIO_PIN17) /* Type: GPIO */
-#define PIO_ISI_D10 (PIO_PERIPHC | PIO_CFG_DEFAULT | PIO_PORT_PIOC | PIO_PIN27) /* Type: GPIO */
-#define PIO_ISI_D11 (PIO_PERIPHC | PIO_CFG_DEFAULT | PIO_PORT_PIOC | PIO_PIN26) /* Type: GPIO */
#define PIO_ISI_D2 (PIO_PERIPHC | PIO_CFG_DEFAULT | PIO_PORT_PIOA | PIO_PIN18) /* Type: GPIO */
#define PIO_ISI_D3 (PIO_PERIPHC | PIO_CFG_DEFAULT | PIO_PORT_PIOA | PIO_PIN19) /* Type: GPIO */
#define PIO_ISI_D4 (PIO_PERIPHC | PIO_CFG_DEFAULT | PIO_PORT_PIOA | PIO_PIN20) /* Type: GPIO */
@@ -200,6 +198,8 @@
#define PIO_ISI_D7 (PIO_PERIPHC | PIO_CFG_DEFAULT | PIO_PORT_PIOA | PIO_PIN23) /* Type: GPIO */
#define PIO_ISI_D8 (PIO_PERIPHC | PIO_CFG_DEFAULT | PIO_PORT_PIOC | PIO_PIN29) /* Type: GPIO */
#define PIO_ISI_D9 (PIO_PERIPHC | PIO_CFG_DEFAULT | PIO_PORT_PIOC | PIO_PIN28) /* Type: GPIO */
+#define PIO_ISI_D10 (PIO_PERIPHC | PIO_CFG_DEFAULT | PIO_PORT_PIOC | PIO_PIN27) /* Type: GPIO */
+#define PIO_ISI_D11 (PIO_PERIPHC | PIO_CFG_DEFAULT | PIO_PORT_PIOC | PIO_PIN26) /* Type: GPIO */
#define PIO_ISI_HSYNC (PIO_PERIPHC | PIO_CFG_DEFAULT | PIO_PORT_PIOA | PIO_PIN31) /* Type: GPIO */
#define PIO_ISI_PCK (PIO_PERIPHC | PIO_CFG_DEFAULT | PIO_PORT_PIOC | PIO_PIN30) /* Type: GPIO */
#define PIO_ISI_VSYNC (PIO_PERIPHC | PIO_CFG_DEFAULT | PIO_PORT_PIOA | PIO_PIN30) /* Type: GPIO */
diff --git a/nuttx/configs/sama5d3x-ek/README.txt b/nuttx/configs/sama5d3x-ek/README.txt
index daa430f82..c62673ea3 100644
--- a/nuttx/configs/sama5d3x-ek/README.txt
+++ b/nuttx/configs/sama5d3x-ek/README.txt
@@ -79,6 +79,7 @@ Contents
- AT24 Serial EEPROM
- CAN Usage
- SAMA5 ADC Support
+ - OV2640 Camera interface
- SAMA5D3x-EK Configuration Options
- Configurations
@@ -802,6 +803,43 @@ SAMA5 ADC Support
Application Configuration -> Examples -> ADC eample
CONFIG_EXAMPLES_ADC_GROUPSIZE=16 : Larger buffers in the test
+OV2640 Camera interface
+=======================
+
+SAMA5D3x PIN SAMA5D3x-EK OV2640
+PIO PER SIGNAL ISI Socket J11
+---- --- ------------- --- ------------ ------------
+ 1 VDDISI
+ 2 GND
+ 3 VDDISI
+ 4 GND
+PE28 ? ? 5 ZB_SLPTR
+PE29 ? ? 6 ZB_RST
+PC27 B TWI1_CK 7 TWCK1
+PC26 B TWI1_D 8 TWD1
+ 9 GND
+PD31 B PCK1 (ISI_MCK) 10 ISI_MCK
+ 11 GND
+PA30 C ISI_VSYNC 12 ISI_VSYNC
+ 13 GND
+PA31 C ISI_HSYNC 14 ISI_HSYNC
+ 15 GND
+PC30 C ISI_PCK 16 ISI_PCK
+ 17 GND
+PA16 C ISI_D0 18 ISI_D0
+PA17 C ISI_D1 19 ISI_D1
+PA18 C ISI_D2 20 ISI_D2
+PA19 C ISI_D3 21 ISI_D3
+PA20 C ISI_D4 22 ISI_D4
+PA21 C ISI_D5 23 ISI_D5
+PA22 C ISI_D6 24 ISI_D6
+PA23 C ISI_D7 25 ISI_D7
+PC29 C ISI_D8 26 ISI_D8
+PC28 C ISI_D9 27 ISI_D9
+PC27 C ISI_D10 28 ISI_D10
+PC26 C ISI_D11 29 ISI_D11
+ 30 GND
+
SAMA5D3x-EK Configuration Options
=================================
diff --git a/nuttx/include/nuttx/spi/spi.h b/nuttx/include/nuttx/spi/spi.h
index 2cfe7644c..5f127287d 100644
--- a/nuttx/include/nuttx/spi/spi.h
+++ b/nuttx/include/nuttx/spi/spi.h
@@ -354,6 +354,7 @@ enum spi_dev_e
SPIDEV_FLASH, /* Select SPI FLASH device */
SPIDEV_ETHERNET, /* Select SPI ethernet device */
SPIDEV_DISPLAY, /* Select SPI LCD/OLED display device */
+ SPIDEV_CAMERA, /* Select SPI imaging device */
SPIDEV_WIRELESS, /* Select SPI Wireless device */
SPIDEV_TOUCHSCREEN, /* Select SPI touchscreen device */
SPIDEV_EXPANDER, /* Select SPI I/O expander device */