SAMA5D3x-EK: At support for the AT25 serial FLASH

9 files changed, 357 insertions, 11 deletions

diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog
index 1769f774b..e1b9ab99b 100644
--- a/nuttx/ChangeLog
+++ b/nuttx/ChangeLog
@@ -5284,4 +5284,6 @@
 	  and have several limitations:  No DMA, no SPI1 support (2013-8-4).
 	* arch/arm/src/sama5/sam_spi.c and sam_spi.h:  Now supports SPI1
 	  and a register access debug option (2013-8-4).
+	* configs/sama5d3x-ek/src/sam_spi.c:  At board support for the
+	  AT25 serial flash (2013-8-4).
 
diff --git a/nuttx/arch/arm/src/sama5/chip/sama5d3x_pinmap.h b/nuttx/arch/arm/src/sama5/chip/sama5d3x_pinmap.h
index a13b7744d..decda4ac4 100644
--- a/nuttx/arch/arm/src/sama5/chip/sama5d3x_pinmap.h
+++ b/nuttx/arch/arm/src/sama5/chip/sama5d3x_pinmap.h
@@ -92,6 +92,7 @@
 
 #define GPIO_CAN0_RX       (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOD | GPIO_PIN14) /* Type: GPIO */
 #define GPIO_CAN0_TX       (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOD | GPIO_PIN15) /* Type: GPIO */
+
 #define GPIO_CAN1_RX       (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN14) /* Type: GMAC */
 #define GPIO_CAN1_TX       (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN15) /* Type: GMAC */
 
@@ -256,12 +257,14 @@
 #define GPIO_MCI0_DA5      (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOD | GPIO_PIN6)  /* Type: GPIO */
 #define GPIO_MCI0_DA6      (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOD | GPIO_PIN7)  /* Type: GPIO */
 #define GPIO_MCI0_DA7      (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOD | GPIO_PIN8)  /* Type: GPIO */
+
 #define GPIO_MCI1_CDA      (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN19) /* Type: GMAC */
 #define GPIO_MCI1_CK       (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN24) /* Type: GMAC */
 #define GPIO_MCI1_DA0      (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN20) /* Type: GMAC */
 #define GPIO_MCI1_DA1      (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN21) /* Type: GMAC */
 #define GPIO_MCI1_DA2      (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN22) /* Type: GMAC */
 #define GPIO_MCI1_DA3      (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN23) /* Type: GMAC */
+
 #define GPIO_MCI2_CDA      (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN10) /* Type: GPIO */
 #define GPIO_MCI2_CK       (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN15) /* Type: MCI_CLK */
 #define GPIO_MCI2_DA0      (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN11) /* Type: GPIO */
@@ -282,17 +285,20 @@
 #define GPIO_PWM0_H_2      (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN20) /* Type: GPIO */
 #define GPIO_PWM0_L_1      (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN1)  /* Type: GMAC */
 #define GPIO_PWM0_L_2      (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN21) /* Type: GPIO */
+
 #define GPIO_PWM1_FI       (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN31) /* Type: GPIO */
 #define GPIO_PWM1_H_1      (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN4)  /* Type: GMAC */
 #define GPIO_PWM1_H_2      (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN22) /* Type: GPIO */
 #define GPIO_PWM1_L_1      (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN5)  /* Type: GMAC */
 #define GPIO_PWM1_L_2      (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOE | GPIO_PIN31) /* Type: EBI */
 #define GPIO_PWM1_L_3      (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN23) /* Type: GPIO */
+
 #define GPIO_PWM2_FI       (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN29) /* Type: GPIO */
 #define GPIO_PWM2_H_1      (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOD | GPIO_PIN5)  /* Type: GPIO */
 #define GPIO_PWM2_H_2      (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN8)  /* Type: GMAC */
 #define GPIO_PWM2_L_1      (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOD | GPIO_PIN6)  /* Type: GPIO */
 #define GPIO_PWM2_L_2      (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN9)  /* Type: GMAC */
+
 #define GPIO_PWM3_FI       (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOD | GPIO_PIN16) /* Type: GPIO */
 #define GPIO_PWM3_H_1      (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOD | GPIO_PIN7)  /* Type: GPIO */
 #define GPIO_PWM3_H_2      (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN12) /* Type: GMAC */
@@ -308,6 +314,7 @@
 #define GPIO_SPI0_NPCS2    (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOD | GPIO_PIN15) /* Type: GPIO */
 #define GPIO_SPI0_NPCS3    (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOD | GPIO_PIN16) /* Type: GPIO */
 #define GPIO_SPI0_SPCK     (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOD | GPIO_PIN12) /* Type: GPIO_CLK */
+
 #define GPIO_SPI1_MISO     (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN22) /* Type: GPIO */
 #define GPIO_SPI1_MOSI     (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN23) /* Type: GPIO */
 #define GPIO_SPI1_NPCS0    (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN25) /* Type: GPIO */
@@ -324,6 +331,7 @@
 #define GPIO_SSC0_TD       (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN18) /* Type: GPIO */
 #define GPIO_SSC0_TF       (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN17) /* Type: GPIO */
 #define GPIO_SSC0_TK       (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN16) /* Type: GPIO */
+
 #define GPIO_SSC1_RD       (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN11) /* Type: GMAC */
 #define GPIO_SSC1_RF       (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN10) /* Type: GMAC */
 #define GPIO_SSC1_RK       (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN7)  /* Type: GMAC */
@@ -336,18 +344,23 @@
 #define GPIO_TC0_CLK       (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOD | GPIO_PIN7)  /* Type: GPIO */
 #define GPIO_TC0_IOA       (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOD | GPIO_PIN5)  /* Type: GPIO */
 #define GPIO_TC0_IOB       (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOD | GPIO_PIN6)  /* Type: GPIO */
+
 #define GPIO_TC1_CLK       (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN14) /* Type: GPIO */
 #define GPIO_TC1_IOA       (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN12) /* Type: GPIO */
 #define GPIO_TC1_IOB       (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN13) /* Type: GPIO */
+
 #define GPIO_TC2_CLK       (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOE | GPIO_PIN29) /* Type: EBI */
 #define GPIO_TC2_IOA       (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOE | GPIO_PIN27) /* Type: EBI */
 #define GPIO_TC2_IOB       (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOE | GPIO_PIN28) /* Type: EBI */
+
 #define GPIO_TC3_CLK       (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN2)  /* Type: GPIO */
 #define GPIO_TC3_IOA       (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN0)  /* Type: GPIO */
 #define GPIO_TC3_IOB       (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN1)  /* Type: GPIO */
+
 #define GPIO_TC4_CLK       (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN5)  /* Type: GPIO */
 #define GPIO_TC4_IOA       (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN3)  /* Type: GPIO */
 #define GPIO_TC4_IOB       (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN4)  /* Type: GPIO */
+
 #define GPIO_TC5_CLK       (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN8)  /* Type: GPIO */
 #define GPIO_TC5_IOA       (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN6)  /* Type: GPIO */
 #define GPIO_TC5_IOB       (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN7)  /* Type: GPIO */
@@ -356,6 +369,7 @@
 
 #define GPIO_TWI0_CK       (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN31) /* Type: GPIO */
 #define GPIO_TWI0_D        (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN30) /* Type: GPIO */
+
 #define GPIO_TWI1_CK       (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN27) /* Type: GPIO */
 #define GPIO_TWI1_D        (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN26) /* Type: GPIO */
 #define GPIO_TWI2_CK       (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN19) /* Type: GPIO */
@@ -365,6 +379,7 @@
 
 #define GPIO_UART0_RXD     (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN29) /* Type: GPIO */
 #define GPIO_UART0_TXD     (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN30) /* Type: GPIO */
+
 #define GPIO_UART1_RXD     (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN30) /* Type: GPIO */
 #define GPIO_UART1_TXD     (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN31) /* Type: GPIO */
 
@@ -375,16 +390,19 @@
 #define GPIO_USART0_RXD    (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOD | GPIO_PIN17) /* Type: GPIO */
 #define GPIO_USART0_SCK    (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOD | GPIO_PIN14) /* Type: GPIO */
 #define GPIO_USART0_TXD    (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOD | GPIO_PIN18) /* Type: GPIO */
+
 #define GPIO_USART1_CTS    (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN26) /* Type: GMAC */
 #define GPIO_USART1_RTS    (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN27) /* Type: GPIO */
 #define GPIO_USART1_RXD    (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN28) /* Type: GPIO */
 #define GPIO_USART1_SCK    (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN25) /* Type: GMAC */
 #define GPIO_USART1_TXD    (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN29) /* Type: GPIO */
+
 #define GPIO_USART2_CTS    (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOE | GPIO_PIN23) /* Type: EBI */
 #define GPIO_USART2_RTS    (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOE | GPIO_PIN24) /* Type: EBI */
 #define GPIO_USART2_RXD    (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOE | GPIO_PIN25) /* Type: EBI */
 #define GPIO_USART2_SCK    (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOE | GPIO_PIN20) /* Type: EBI */
 #define GPIO_USART2_TXD    (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOE | GPIO_PIN26) /* Type: EBI */
+
 #define GPIO_USART3_CTS    (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOE | GPIO_PIN16) /* Type: EBI */
 #define GPIO_USART3_RTS    (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOE | GPIO_PIN17) /* Type: EBI */
 #define GPIO_USART3_RXD    (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOE | GPIO_PIN18) /* Type: EBI */
diff --git a/nuttx/configs/sam3u-ek/src/up_spi.c b/nuttx/configs/sam3u-ek/src/up_spi.c
index f06c37747..20423200d 100644
--- a/nuttx/configs/sam3u-ek/src/up_spi.c
+++ b/nuttx/configs/sam3u-ek/src/up_spi.c
@@ -89,7 +89,7 @@
  * Name: sam_spiinitialize
  *
  * Description:
- *   Called to configure SPI chip select GPIO pins for the SAM3U10E-EVAL board.
+ *   Called to configure SPI chip select GPIO pins for the SAM3U-EK board.
  *
  ************************************************************************************/
 
diff --git a/nuttx/configs/sama5d3x-ek/README.txt b/nuttx/configs/sama5d3x-ek/README.txt
index 727925d92..6009de3e1 100644
--- a/nuttx/configs/sama5d3x-ek/README.txt
+++ b/nuttx/configs/sama5d3x-ek/README.txt
@@ -62,7 +62,6 @@ README
 Contents
 ========
 
-  - PIO Muliplexing
   - Development Environment
   - GNU Toolchain Options
   - IDEs
@@ -74,14 +73,10 @@ Contents
   - Creating and Using NORBOOT
   - Buttons and LEDs
   - Serial Consoles
+  - Serial FLASH
   - SAMA5D3x-EK Configuration Options
   - Configurations
 
-PIO Muliplexing
-===============
-
-  To be provided
-
 Development Environment
 =======================
 
@@ -513,6 +508,25 @@ Serial Consoles
     - Jumper JP16 not fitted: CDC is enabled
     - Jumper JP16 fitted : CDC is disabled"
 
+Serial FLASH
+============
+
+  Both the Ronetix and Embest versions of the SAMAD3x CPU modules include an
+  Atmel AT25DF321A, 32-megabit, 2.7-volt SPI serial flash.  The SPI
+  connection is as follows:
+
+    AT25DF321A      SAMA5
+    --------------- -----------------------------------------------
+    SI              PD11 SPI0_MOSI
+    SO              PD10 SPI0_MIS0
+    SCK             PD12 SPI0_SPCK
+    /CS             PD13 via NL17SZ126 if JP1 is closed (See below)
+
+  JP1 and JP2 seem to related to /CS on the Ronetix board, but the usage is
+  less clear.  For the Embest module, JP1 must be closed to connect /CS to
+  PD13; on the Ronetix schematic, JP11 seems only to bypass a resistor (may
+  not be populated?).  I think closing JP1 is correct in either case.
+
 SAMA5D3x-EK Configuration Options
 =================================
 
@@ -915,6 +929,24 @@ Configurations
         If the CPU speed changes, then so must the NOR and SDRAM
         initialization!
 
+    7. The Embest or Ronetix CPU module includes an Atmel AT25DF321A,
+       32-megabit, 2.7-volt SPI serial flash.  Support for that serial
+       FLASH can be enabled by modifying the NuttX configuration as
+       follows:
+
+       System Type -> SAMA5 Peripheral Support
+         CONFIG_SAMA5_SPI0=y                   : Enable SPI0
+
+       Device Drivers -> Memory Technology Device (MTD) Support
+         CONFIG_SPI=y                          : Enable SPI support
+         CONFIG_SPI_EXCHANGE=y                 : Support the exchange method
+
+       Device Drivers -> SPI Driver Support
+         CONFIG_MTD=y                          : Enable MTD support
+         CONFIG_MTD_AT25=y                     : Enable the AT25 driver
+         CONFIG_AT25_SPIMODE=0                 : Use SPI mode 0
+         CONFIG_AT25_SPIFREQUENCY=20000000     : Use SPI frequency 20MHz
+
       2013-7-31:  I have been unable to execute this configuration from NOR
         FLASH by closing the BMS jumper (J9).  As far as I can tell, this
         jumper does nothing on my board???  I have been using the norboot
diff --git a/nuttx/configs/sama5d3x-ek/src/Makefile b/nuttx/configs/sama5d3x-ek/src/Makefile
index 7e94a01ee..1236b2cfc 100644
--- a/nuttx/configs/sama5d3x-ek/src/Makefile
+++ b/nuttx/configs/sama5d3x-ek/src/Makefile
@@ -46,6 +46,14 @@ ifeq ($(CONFIG_HAVE_CXX),y)
 CSRCS += sam_cxxinitialize.c
 endif
 
+ifeq ($(CONFIG_SAMA5_SPI0),y)
+CSRCS += sam_spi.c
+else
+ifeq ($(CONFIG_SAMA5_SPI1),y)
+CSRCS += sam_spi.c
+endif
+endif
+
 ifeq ($(CONFIG_SAMA5_DDRCS),y)
 CSRCS += sam_sdram.c
 endif
diff --git a/nuttx/configs/sama5d3x-ek/src/sam_boot.c b/nuttx/configs/sama5d3x-ek/src/sam_boot.c
index f68cae4b4..4d4cb27e6 100644
--- a/nuttx/configs/sama5d3x-ek/src/sam_boot.c
+++ b/nuttx/configs/sama5d3x-ek/src/sam_boot.c
@@ -67,6 +67,17 @@
 
 void sam_boardinitialize(void)
 {
+  /* Configure SPI chip selects if 1) SPI is enable, and 2) the weak function
+   * sam_spiinitialize() has been brought into the link.
+   */
+
+#if defined(CONFIG_SAMA5_SPI0) || defined(CONFIG_SAMA5_SPI1)
+  if (sam_spiinitialize)
+    {
+      sam_spiinitialize();
+    }
+#endif
+
 #if defined(CONFIG_SAMA5_DDRCS) && !defined(CONFIG_SAMA5_BOOT_SDRAM)
 
   /* Configure SDRAM if (1) SDRAM has been enalbled in the NuttX configuration and
diff --git a/nuttx/configs/sama5d3x-ek/src/sam_spi.c b/nuttx/configs/sama5d3x-ek/src/sam_spi.c
new file mode 100644
index 000000000..ee27f1f64
--- /dev/null
+++ b/nuttx/configs/sama5d3x-ek/src/sam_spi.c
@@ -0,0 +1,216 @@
+/************************************************************************************
+ * configs/sama5d3x-ek/src/up_spi.c
+ *
+ *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <debug.h>
+#include <errno.h>
+
+#include <nuttx/spi/spi.h>
+#include <arch/board/board.h>
+
+#include "up_arch.h"
+#include "chip.h"
+#include "sam_gpio.h"
+#include "sam_spi.h"
+#include "sama5d3x-ek.h"
+
+#if defined(CONFIG_SAMA5_SPI0) || defined(CONFIG_SAMA5_SPI1)
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+
+/* Enables debug output from this file (needs CONFIG_DEBUG too) */
+
+#undef SPI_DEBUG   /* Define to enable debug */
+#undef SPI_VERBOSE /* Define to enable verbose debug */
+
+#ifdef SPI_DEBUG
+#  define spidbg  lldbg
+#  ifdef SPI_VERBOSE
+#    define spivdbg lldbg
+#  else
+#    define spivdbg(x...)
+#  endif
+#else
+#  undef SPI_VERBOSE
+#  define spidbg(x...)
+#  define spivdbg(x...)
+#endif
+
+/************************************************************************************
+ * Private Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Name: sam_spiinitialize
+ *
+ * Description:
+ *   Called to configure SPI chip select GPIO pins for the SAMA5D3x-EK board.
+ *
+ ************************************************************************************/
+
+void weak_function sam_spiinitialize(void)
+{
+#ifdef CONFIG_SAMA5_SPI0
+#ifdef CONFIG_MTD_AT25
+  /* The AT25 serial FLASH connects using NPCS0 */
+
+   sam_configgpio(GPIO_AT25_NPCS0);
+#endif
+#endif
+
+#ifdef CONFIG_SAMA5_SPI1
+#endif
+}
+
+/****************************************************************************
+ * Name:  sam_spi[0|1]select, sam_spi[0|1]status, and sam_spi[0|1]cmddata
+ *
+ * Description:
+ *   These external functions must be provided by board-specific logic.  They
+ *   include:
+ *
+ *   o sam_spi[0|1]select is a functions tomanage the board-specific chip selects
+ *   o sam_spi[0|1]status and sam_spi[0|1]cmddata:  Implementations of the status
+ *     and cmddata methods of the SPI interface defined by struct spi_ops_
+ *     (see include/nuttx/spi/spi.h). All other methods including
+ *     up_spiinitialize()) are provided by common SAM3/4 logic.
+ *
+ *  To use this common SPI logic on your board:
+ *
+ *   1. Provide logic in sam_boardinitialize() to configure SPI chip select
+ *      pins.
+ *   2. Provide sam_spi[0|1]select() and sam_spi[0|1]status() functions in your board-
+ *      specific logic.  These functions will perform chip selection and
+ *      status operations using GPIOs in the way your board is configured.
+ *   2. If CONFIG_SPI_CMDDATA is defined in the NuttX configuration, provide
+ *      sam_spi[0|1]cmddata() functions in your board-specific logic.  This
+ *      function will perform cmd/data selection operations using GPIOs in
+ *      the way your board is configured.
+ *   3. Add a call to up_spiinitialize() in your low level application
+ *      initialization logic
+ *   4. The handle returned by up_spiinitialize() may then be used to bind the
+ *      SPI driver to higher level logic (e.g., calling
+ *      mmcsd_spislotinitialize(), for example, will bind the SPI driver to
+ *      the SPI MMC/SD driver).
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: sam_spi[0|1]select
+ *
+ * Description:
+ *   PIO chip select pins may be programmed by the board specific logic in
+ *   one of two different ways.  First, the pins may be programmed as SPI
+ *   peripherals.  In that case, the pins are completely controlled by the
+ *   SPI driver.  This method still needs to be provided, but it may be only
+ *   a stub.
+ *
+ *   An alternative way to program the PIO chip select pins is as a normal
+ *   GPIO output.  In that case, the automatic control of the CS pins is
+ *   bypassed and this function must provide control of the chip select.
+ *   NOTE:  In this case, the GPIO output pin does *not* have to be the
+ *   same as the NPCS pin normal associated with the chip select number.
+ *
+ * Input Parameters:
+ *   devid - Identifies the (logical) device
+ *   selected - TRUE:Select the device, FALSE:De-select the device
+ *
+ * Returned Values:
+ *   None
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SAMA5_SPI0
+void sam_spi0select(enum spi_dev_e devid, bool selected)
+{
+#ifdef CONFIG_MTD_AT25
+  /* The AT25 serial FLASH connects using NPCS0 */
+
+  if (devid == SPIDEV_FLASH)
+    {
+      sam_gpiowrite(GPIO_AT25_NPCS0, !selected);
+    }
+#endif
+}
+#endif
+
+#ifdef CONFIG_SAMA5_SPI1
+void sam_spi1select(enum spi_dev_e devid, bool selected)
+{
+}
+#endif
+
+/****************************************************************************
+ * Name: sam_spi[0|1]status
+ *
+ * Description:
+ *   Return status information associated with the SPI device.
+ *
+ * Input Parameters:
+ *   devid - Identifies the (logical) device
+ *
+ * Returned Values:
+ *   Bit-encoded SPI status (see include/nuttx/spi/spi.h.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SAMA5_SPI0
+uint8_t sam_spi0status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
+{
+  return 0;
+}
+#endif
+
+#ifdef CONFIG_SAMA5_SPI0
+uint8_t sam_spi1status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
+{
+  return 0;
+}
+#endif
+
+#endif /* CONFIG_SAMA5_SPI0 || CONFIG_SAMA5_SPI1 */
diff --git a/nuttx/configs/sama5d3x-ek/src/sama5d3x-ek.h b/nuttx/configs/sama5d3x-ek/src/sama5d3x-ek.h
index 4dfd1c203..4a9b91c7e 100644
--- a/nuttx/configs/sama5d3x-ek/src/sama5d3x-ek.h
+++ b/nuttx/configs/sama5d3x-ek/src/sama5d3x-ek.h
@@ -94,6 +94,28 @@
                       GPIO_INT_BOTHEDGES | GPIO_PORT_PIOE | GPIO_PIN27)
 #define IRQ_USER1    SAM_IRQ_PE27
 
+/* SPI Chip Selects *****************************************************************/
+/* Both the Ronetix and Embest versions of the SAMAD3x CPU modules include an
+ * Atmel AT25DF321A, 32-megabit, 2.7-volt SPI serial flash.  The SPI
+ * connection is as follows:
+ *
+ *   AT25DF321A      SAMA5
+ *   --------------- -----------------------------------------------
+ *   SI              PD11 SPI0_MOSI
+ *   SO              PD10 SPI0_MIS0
+ *   SCK             PD12 SPI0_SPCK
+ *   /CS             PD13 via NL17SZ126 if JP1 is closed (See below)
+ *
+ * JP1 and JP2 seem to related to /CS on the Ronetix board, but the usage is
+ * less clear.  For the Embest module, JP1 must be closed to connect /CS to
+ * PD13; on the Ronetix schematic, JP11 seems only to bypass a resistor (may
+ * not be populated?).  I think closing JP1 is correct in either case.
+ */
+
+#define GPIO_AT25_NPCS0 (GPIO_OUTPUT | GPIO_CFG_PULLUP | GPIO_OUTPUT_SET | \
+                         GPIO_PORT_PIOD | GPIO_PIN13)
+#define AT25_CSNUM      0
+
 /************************************************************************************
  * Public Types
  ************************************************************************************/
@@ -109,6 +131,18 @@
  ************************************************************************************/
 
 /************************************************************************************
+ * Name: sam_spiinitialize
+ *
+ * Description:
+ *   Called to configure SPI chip select PIO pins for the SAMA4D3x-EK board.
+ *
+ ************************************************************************************/
+
+#if defined(CONFIG_SAMA5_SPI0) || defined(CONFIG_SAMA5_SPI1)
+void weak_function sam_spiinitialize(void);
+#endif
+
+/************************************************************************************
  * Name: board_sdram_config
  *
  * Description:
diff --git a/nuttx/drivers/mtd/Kconfig b/nuttx/drivers/mtd/Kconfig
index e4107949b..a68fcaaeb 100644
--- a/nuttx/drivers/mtd/Kconfig
+++ b/nuttx/drivers/mtd/Kconfig
@@ -86,6 +86,31 @@ config AT24XX_ADDR
 
 endif
 
+config MTD_AT25
+	bool "SPI-based AT25 FLASH"
+	default n
+	select SPI
+
+if MTD_AT25
+
+config AT25_SPIMODE
+	int "AT25 SPI Mode"
+	default 0
+
+config AT25_SPIFREQUENCY
+	int "AT25 SPI Frequency"
+	default 20000000
+
+config AT25_READONLY
+	bool "AT25 Read-Only FLASH"
+	default n
+
+config AT25_SECTOR512
+	bool "Simulate 512 byte Erase Blocks"
+	default n
+
+endif
+
 config MTD_AT45DB
 	bool "SPI-based AT45DB flash"
 	default n
@@ -94,15 +119,15 @@ config MTD_AT45DB
 if MTD_AT45DB
 
 config AT45DB_FREQUENCY
-	int "at45db frequency"
+	int "AT45DB frequency"
 	default 1000000
 
 config AT45DB_PREWAIT
-	bool "enables higher performance write logic"
+	bool "Enable higher performance write logic"
 	default y
 
 config AT45DB_PWRSAVE
-	bool "enables power save"
+	bool "Enable power save"
 	default n
 
 endif
@@ -147,7 +172,7 @@ endif
 
 config MTD_SMART
 	bool "Sector Mapped Allocation for Really Tiny (SMART) Flash support"
-	default y
+	default n
 	---help---
 		The MP25x series of Flash devices are typically very small and have a very large
 		erase block size.  This causes issues with the standard Flash Translation Layer