Removed unused ARMv7-A cache function

3 files changed, 42 insertions, 51 deletions

diff --git a/nuttx/arch/arm/src/armv7-a/arm_cache.S b/nuttx/arch/arm/src/armv7-a/arm_cache.S
index 79b3703e7..36349b362 100755
--- a/nuttx/arch/arm/src/armv7-a/arm_cache.S
+++ b/nuttx/arch/arm/src/armv7-a/arm_cache.S
@@ -98,7 +98,6 @@
 	.globl	cp15_invalidate_dcache_for_dma
 	.globl	cp15_clean_dcache_for_dma
 	.globl	cp15_flush_dcache_for_dma
-	.globl	cp15_flush_kern_dcache_for_dma
 
 /****************************************************************************
  * Public Functions
@@ -302,44 +301,4 @@ cp15_flush_dcache_for_dma:
 	dsb
 	bx		lr
 	.size cp15_flush_dcache_for_dma, . - cp15_flush_dcache_for_dma
-
-/****************************************************************************
- * Name: cp15_flush_kern_dcache_for_dma
- *
- * Description:
- *   Ensure that the data held in the page kaddr is written back to the page
- *   in question.
- *
- * Input Parameters:
- *   start - virtual start address of region
- *   end   - virtual end address of region
- *
- * Returned Value:
- *   None
- *
- ****************************************************************************/
-
-	.globl	cp15_flush_kern_dcache_for_dma
-	.type	cp15_flush_kern_dcache_for_dma, function
-
-cp15_flush_kern_dcache_for_dma:
-
-	mrc		CP15_TR(r3)				/* Read the Cache Type Register */
-	lsr		r3, r3, #16				/* Isolate the DMinLine field */
-	and		r3, r3, #0xf
-	mov		r2, #4
-	mov		r2, r2, lsl r3			/* Get the cache line size in bytes */
-
-	add		r1, r0, r1
-	sub		r3, r2, #1				/* R3=Cache line size mask */
-	bic		r0, r0, r3				/* R0=aligned start address */
-
-	mcrne	CP15_DCCIMVAC(r0)		/* Clean and invalidate data cache line by VA to PoC */
-	add		r0, r0, r2				/* R12=Next cache line */
-	cmp		r0, r1					/* Loop until all cache lines have been cleaned */
-	blo		1b						/* Merge with loop flushing each D cache line to memory */
-
-	dsb
-	bx		lr
-	.size cp15_flush_kern_dcache_for_dma, . - cp15_flush_kern_dcache_for_dma
 	.end
diff --git a/nuttx/configs/sama5d3x-ek/README.txt b/nuttx/configs/sama5d3x-ek/README.txt
index 30aa7baca..c7747b733 100644
--- a/nuttx/configs/sama5d3x-ek/README.txt
+++ b/nuttx/configs/sama5d3x-ek/README.txt
@@ -64,11 +64,6 @@ README
 Contents
 ========
 
-  - Configurations
-
-Contents
-========
-
   - PIO Muliplexing
   - Development Environment
   - GNU Toolchain Options
@@ -76,7 +71,8 @@ Contents
   - NuttX EABI "buildroot" Toolchain
   - NuttX OABI "buildroot" Toolchain
   - NXFLAT Toolchain
-  - Loading Code
+  - Loading Code into SRAM with J-Link
+  - Writing to FLASH using SAM-BA
   - Buttons and LEDs
   - Serial Consoles
   - SAMA5D3x-EK Configuration Options
@@ -282,8 +278,8 @@ NXFLAT Toolchain
   8. Edit setenv.h, if necessary, so that the PATH variable includes
      the path to the newly built NXFLAT binaries.
 
-Loading Code
-============
+Loading Code into SRAM with J-Link
+==================================
 
   Loading code with the Segger tools and GDB
   ------------------------------------------
@@ -307,6 +303,42 @@ Loading Code
     J-Link> setpc <address of __start>
     J-Link> ... start debugging ...
 
+Writing to FLASH using SAM-BA
+=============================
+
+  Assumed starting configuration:
+
+    1. You have installed the J-Lnk CDC USB driver (Windows only, there is
+        no need to install a driver on any regular Linux distribution),
+    2. You have the USB connected to DBGU poort (J14)
+    3. Terminal configuration:  115200 8N1
+
+  Using SAM-BA to write to FLASH:
+
+    1. Exit the terminal emulation program and remove the USB cable from
+       the DBGU port (J14)
+    2. Connect the USB cable to the device USB port (J20)
+    3. JP9 must open so that (BMS == 1) to boot from on-chip Boot ROM
+    4. Press and maintain PB4 CS_BOOT button and power up the board.  PB4
+       CS_BOOT button prevents booting from Nand or serial Flash by
+       disabling Flash Chip Selects after having powered the board, you can
+       release the PB4 BS_BOOT button.
+    5. On Windows you may need to wait for a device driver to be installed.
+    6. Start the SAM-BA application, selecting (1) the correct USB serial
+       port, and (2) board = at91sama5d3x-ek.
+    7. The SAM-BA menu should appear.
+    8. Select the FLASH bank that you want to use and the address to write
+       to and "Execute"
+    9. When you are finished writing to FLASH, remove the USB cable from J20
+       and re-connect the serial link on USB CDC / DBGU connector (J14) and
+       re-open the terminal emulator program.
+    10. Power cycle the board.
+
+  NOTES:  By closing JP9 (BMS == 0), you can force the board to boot
+  directly to NOR FLASH.  Executing from other memories will require that
+  you provide a special code header so that you code can be recognized as a
+  boot-able image by the ROM bootloader.
+
 Buttons and LEDs
 ================
 
diff --git a/nuttx/configs/sama5d3x-ek/include/board.h b/nuttx/configs/sama5d3x-ek/include/board.h
index 82a6025ae..657039970 100644
--- a/nuttx/configs/sama5d3x-ek/include/board.h
+++ b/nuttx/configs/sama5d3x-ek/include/board.h
@@ -52,7 +52,7 @@
  *
  *   MAINOSC:  Frequency = 12MHz (crysta)
  *   PLLA: PLL Divider = 1, Multiplier = 66 to generate PLLACK = 792MHz
- *   Master Clock (MCK): Source = PLLACK/2, Prescalar = 1, MDIV =  to generate
+ *   Master Clock (MCK): Source = PLLACK/2, Prescalar = 1, MDIV = 3 to generate
 *      MCK      =  132MHz
  *     CPU clock = 396MHz
  */
@@ -88,7 +88,7 @@
  *  Prescaler input                         = 792MHz / 2 = 396MHz
  *  Prescaler output                        = 792MHz / 1 = 396MHz
  *  Processor Clock (PCK)                   = 396MHz
- *  Master clock (MCK)                       = 396MHz / 3 = 132MHz
+ *  Master clock (MCK)                      = 396MHz / 3 = 132MHz
  */
 
 #define BOARD_PMC_MCKR_CSS         PMC_MCKR_CSS_PLLA