SAMA5: Add logic to initialize SAMA5D3x-EK on-board SDRAM

8 files changed, 657 insertions, 51 deletions

diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog
index 3966b6390..9d40b4253 100644
--- a/nuttx/ChangeLog
+++ b/nuttx/ChangeLog
@@ -5254,4 +5254,7 @@
 	  caching issues (and much less redundant) (2013-8-1)
 	* arch/arm/src/sama5/chip/sam_mpddrc.h:  Add DDR controller
 	  registers definitions for the SAMA5 (2013-8-1).
+	* nuttx/configs/sama5d3x-ek/src/sam_sdram.c:  Add logic which
+	  will (eventually) support the SDRAM on the SAMA5D3x-EK
+	  board.  Initial commit is untested and incomplete (2013-8-1).
 
diff --git a/nuttx/arch/arm/src/sama5/chip/sam_mpddrc.h b/nuttx/arch/arm/src/sama5/chip/sam_mpddrc.h
index 636fb971a..d72d9d731 100644
--- a/nuttx/arch/arm/src/sama5/chip/sam_mpddrc.h
+++ b/nuttx/arch/arm/src/sama5/chip/sam_mpddrc.h
@@ -66,8 +66,8 @@
 #define SAM_MPDDRC_OCMS_KEY1_OFFSET     0x003c /* MPDDRC OCMS KEY1 Register */
 #define SAM_MPDDRC_OCMS_KEY2_OFFSET     0x0040 /* MPDDRC OCMS KEY2 Register */
                                                /* 0x0044-0x0070 Reserved */
-#define SAM_MPDDRC_DLL_MO_OFFSET        0x0074 /* MPDDRC DLL Master Offset Register */
-#define SAM_MPDDRC_DLL_SOF_OFFSET       0x0078 /* MPDDRC DLL Slave Offset Register */
+#define SAM_MPDDRC_DLL_MOR_OFFSET       0x0074 /* MPDDRC DLL Master Offset Register */
+#define SAM_MPDDRC_DLL_SOR_OFFSET       0x0078 /* MPDDRC DLL Slave Offset Register */
 #define SAM_MPDDRC_DLL_MS_OFFSET        0x007c /* MPDDRC DLL Status Master Register */
 #define SAM_MPDDRC_DLL_SS0_OFFSET       0x0080 /* MPDDRC DLL Status Slave 0 Register */
 #define SAM_MPDDRC_DLL_SS1_OFFSET       0x0084 /* MPDDRC DLL Status Slave 1 Register */
@@ -97,8 +97,8 @@
 #define SAM_MPDDRC_OCMS                 (SAM_MPDDRC_OFFSET+SAM_MPDDRC_OCMS_OFFSET)
 #define SAM_MPDDRC_OCMS_KEY1            (SAM_MPDDRC_OFFSET+SAM_MPDDRC_OCMS_KEY1_OFFSET)
 #define SAM_MPDDRC_OCMS_KEY2            (SAM_MPDDRC_OFFSET+SAM_MPDDRC_OCMS_KEY2_OFFSET)
-#define SAM_MPDDRC_DLL_MO               (SAM_MPDDRC_OFFSET+SAM_MPDDRC_DLL_MO_OFFSET)
-#define SAM_MPDDRC_DLL_SOF              (SAM_MPDDRC_OFFSET+SAM_MPDDRC_DLL_SOF_OFFSET)
+#define SAM_MPDDRC_DLL_MOR              (SAM_MPDDRC_OFFSET+SAM_MPDDRC_DLL_MOR_OFFSET)
+#define SAM_MPDDRC_DLL_SOR              (SAM_MPDDRC_OFFSET+SAM_MPDDRC_DLL_SOR_OFFSET)
 #define SAM_MPDDRC_DLL_MS               (SAM_MPDDRC_OFFSET+SAM_MPDDRC_DLL_MS_OFFSET)
 #define SAM_MPDDRC_DLL_SS0              (SAM_MPDDRC_OFFSET+SAM_MPDDRC_DLL_SS0_OFFSET)
 #define SAM_MPDDRC_DLL_SS1              (SAM_MPDDRC_OFFSET+SAM_MPDDRC_DLL_SS1_OFFSET)
@@ -140,16 +140,16 @@
 
 #define MPDDRC_CR_NC_SHIFT              (0)       /* Bits 0-1: Number of Column Bits */
 #define MPDDRC_CR_NC_MASK               (3 << MPDDRC_CR_NC_SHIFT)
-#  define MPDDRC_CR_NC_COL9             (0 << MPDDRC_CR_NC_SHIFT) /* 9 DDR column bits */
-#  define MPDDRC_CR_NC_COL10            (1 << MPDDRC_CR_NC_SHIFT) /* 10 DDR column bits */
-#  define MPDDRC_CR_NC_COL11            (2 << MPDDRC_CR_NC_SHIFT) /* 11 DDR column bits */
-#  define MPDDRC_CR_NC_COL12            (3 << MPDDRC_CR_NC_SHIFT) /* 12 DDR column bits */
+#  define MPDDRC_CR_NC_9                (0 << MPDDRC_CR_NC_SHIFT) /* 9 DDR column bits */
+#  define MPDDRC_CR_NC_10               (1 << MPDDRC_CR_NC_SHIFT) /* 10 DDR column bits */
+#  define MPDDRC_CR_NC_11               (2 << MPDDRC_CR_NC_SHIFT) /* 11 DDR column bits */
+#  define MPDDRC_CR_NC_12               (3 << MPDDRC_CR_NC_SHIFT) /* 12 DDR column bits */
 #define MPDDRC_CR_NR_SHIFT              (2)       /* Bits 2-3: Number of Row Bits */
 #define MPDDRC_CR_NR_MASK               (3 << MPDDRC_CR_NR_SHIFT)
-#  define MPDDRC_CR_NR_ROW11            (0 << MPDDRC_CR_NR_SHIFT) /* 00 ROW_11 11 row bits */
-#  define MPDDRC_CR_NR_ROW12            (1 << MPDDRC_CR_NR_SHIFT) /* 01 ROW_12 12 row bits */
-#  define MPDDRC_CR_NR_ROW13            (2 << MPDDRC_CR_NR_SHIFT) /* 10 ROW_13 13 row bits */
-#  define MPDDRC_CR_NR_ROW14            (3 << MPDDRC_CR_NR_SHIFT) /* 11 ROW_14 14 row bits */
+#  define MPDDRC_CR_NR_11               (0 << MPDDRC_CR_NR_SHIFT) /* 00 ROW_11 11 row bits */
+#  define MPDDRC_CR_NR_12               (1 << MPDDRC_CR_NR_SHIFT) /* 01 ROW_12 12 row bits */
+#  define MPDDRC_CR_NR_13               (2 << MPDDRC_CR_NR_SHIFT) /* 10 ROW_13 13 row bits */
+#  define MPDDRC_CR_NR_14               (3 << MPDDRC_CR_NR_SHIFT) /* 11 ROW_14 14 row bits */
 #define MPDDRC_CR_CAS_SHIFT             (4)       /* Bits 4-6: CAS Latency */
 #define MPDDRC_CR_CAS_MASK              (7 << MPDDRC_CR_CAS_SHIFT)
 #  define MPDDRC_CR_CAS_2               (2 << MPDDRC_CR_CAS_SHIFT) /* 010 DDR_CAS2 LPDDR1 CAS Latency 2 */
@@ -159,7 +159,7 @@
 #  define MPDDRC_CR_CAS_6               (6 << MPDDRC_CR_CAS_SHIFT) /* 110 DDR_CAS6 DDR2 CAS Latency 6 */
 #define MPDDRC_CR_DLL                   (1 << 7)  /* Bit 7:  Reset DLL */
 #define MPDDRC_CR_DIC_DS                (1 << 8)  /* Bit 8:  Output Driver Impedance Control (Drive Strength) */
-#define MPDDRC_CR_DIS_DLL               (1 << 9)  /* Bit 9:  DISABLE DLL */
+#define MPDDRC_CR_DIS_DLL               (1 << 9)  /* Bit 9:  Disable DLL */
 #define MPDDRC_CR_ZQ_SHIFT              (10)      /* Bits 10-11: ZQ Calibration */
 #define MPDDRC_CR_ZQ_MASK               (3 << MPDDRC_CR_ZQ_SHIFT)
 #  define MPDDRC_CR_ZQ_INIT             (0 << MPDDRC_CR_ZQ_SHIFT) /* Calibration command after initialization */
@@ -248,8 +248,8 @@
 #  define MPDDRC_LPR_LPCB_SELFREFRESH   (1 << MPDDRC_LPR_LPCB_SHIFT) /* Issues a 'Self Refresh' to device, clocks deactivated */
 #  define MPDDRC_LPR_LPCB_POWERDOWN     (2 << MPDDRC_LPR_LPCB_SHIFT) /* Issues a 'Power-down' to device after each access */
 #  define MPDDRC_LPR_LPCB_DEEPPWD       (3 << MPDDRC_LPR_LPCB_SHIFT) /* TIssues a 'Deep Power-down' to Low-power device */
-#define MPDDRC_LPR_CLK_FR               (1 << 2)  /* Bit 2:  Clock Frozen Command*/
-#define MPDDRC_LPR_LPDDR2_PWOFF         (1 << 3)  /* Bit 3:  LPDDR2 Power Off*/
+#define MPDDRC_LPR_CLK_FR               (1 << 2)  /* Bit 2:  Clock Frozen Command */
+#define MPDDRC_LPR_LPDDR2_PWOFF         (1 << 3)  /* Bit 3:  LPDDR2 Power Off */
 #define MPDDRC_LPR_PASR_SHIFT           (4)       /* Bits 4-6: Partial Array Self Refresh */
 #define MPDDRC_LPR_PASR_MASK            (7 << MPDDRC_LPR_PASR_SHIFT)
 #  define MPDDRC_LPR_PASR(n)            ((n) << MPDDRC_LPR_PASR_SHIFT)
@@ -258,10 +258,12 @@
 #  define MPDDRC_LPR_DS(n)              ((n) << MPDDRC_LPR_DS_SHIFT)
 #define MPDDRC_LPR_TIMEOUT_SHIFT        (12)      /* Bits 12-13: Enter Low-power Mode */
 #define MPDDRC_LPR_TIMEOUT_MASK         (3 << MPDDRC_LPR_TIMEOUT_SHIFT)
-#  define MPDDRC_LPR_TIMEOUT_END        (0 << MPDDRC_LPR_TIMEOUT_SHIFT) /* Activates low-power mode after the end of transfer */
+#  define MPDDRC_LPR_TIMEOUT_0CLKS      (0 << MPDDRC_LPR_TIMEOUT_SHIFT) /* Activates low-power mode after the end of transfer */
 #  define MPDDRC_LPR_TIMEOUT_64CLKS     (1 << MPDDRC_LPR_TIMEOUT_SHIFT) /* Activates low-power mode 64 clocks after the end of transfer */
 #  define MPDDRC_LPR_TIMEOUT_128CLKS    (2 << MPDDRC_LPR_TIMEOUT_SHIFT) /* 28 Activates low-power mode 128 clocks after the end of transfer */
 #define MPDDRC_LPR_APDE                 (1 << 16) /* Bit 16:  ctive Power Down Exit Time */
+#  define MPDDRC_LPR_APDE_FAST          (0)
+#  define MPDDRC_LPR_APDE_SLOW          MPDDRC_LPR_APDE
 #define MPDDRC_LPR_UPD_MR_SHIFT         (20)      /* Bits 20-21: Update Load Mode Register and Extended Mode Register */
 #define MPDDRC_LPR_UPD_MR_MASK          (3 << MPDDRC_LPR_UPD_MR_SHIFT)
 #  define MPDDRC_LPR_UPD_MR_DISABLED    (0 << MPDDRC_LPR_UPD_MR_SHIFT) /* DISABLED Update is disabled */
@@ -282,6 +284,7 @@
 /* MPDDRC High Speed Register */
 
 #define MPDDRC_HS_DIS_ANTICIP_READ      (1 << 2) /* Bit 2:  Disable Anticip Read Access */
+#define MPDDRC_HS_AUTOREFRESH_CAL       (1 << 5) /* Bit 5:  calibration during autorefresh (REVISIT) */
 
 /* MPDDRC LPDDR2 Low-power Register */
 
@@ -317,7 +320,7 @@
 
 #define MPDDRC_IO_CALIBR_RDIV_SHIFT     (0)       /* Bits 0-2: Resistor Divider, Output Driver Impedance */
 #define MPDDRC_IO_CALIBR_RDIV_MASK      (7 << MPDDRC_IO_CALIBR_RDIV_SHIFT)
-#  define MPDDRC_IO_CALIBR_RZQ34        (1 << MPDDRC_IO_CALIBR_RDIV_SHIFT) /* LPDDR2 RZQ = 34.3 Ohm DDR2/LPDDR1: Not applicable */
+#  define MPDDRC_IO_CALIBR_RZQ34_NA     (1 << MPDDRC_IO_CALIBR_RDIV_SHIFT) /* LPDDR2 RZQ = 34.3 Ohm DDR2/LPDDR1: Not applicable */
 #  define MPDDRC_IO_CALIBR_RZQ40_33     (2 << MPDDRC_IO_CALIBR_RDIV_SHIFT) /* LPDDR2:RZQ = 40 Ohm   DDR2/LPDDR1: RZQ = 33.3 Ohm */
 #  define MPDDRC_IO_CALIBR_RZQ48_40     (3 << MPDDRC_IO_CALIBR_RDIV_SHIFT) /* LPDDR2:RZQ = 48 Ohm   DDR2/LPDDR1: RZQ = 40 Ohm */
 #  define MPDDRC_IO_CALIBR_RZQ60_50     (4 << MPDDRC_IO_CALIBR_RDIV_SHIFT) /* LPDDR2:RZQ = 60 Ohm   DDR2/LPDDR1: RZQ = 50 Ohm */
@@ -342,28 +345,31 @@
 
 /* MPDDRC DLL Master Offset Register */
 
-#define MPDDRC_DLL_MO_MOFF_SHIFT        (0)       /* Bits 0-3: DLL Master Delay Line Offset */
-#define MPDDRC_DLL_MO_MOFF_MASK         (15 << MPDDRC_DLL_MO_MOFF_SHIFT)
-#  define MPDDRC_DLL_MO_MOFF(n)         ((n) << MPDDRC_DLL_MO_MOFF_SHIFT)
-#define MPDDRC_DLL_MO_CLK90OFF_SHIFT    (8)       /* Bits 8-12: DLL CLK90 Delay Line Offset */
-#define MPDDRC_DLL_MO_CLK90OFF_MASK     (31 << MPDDRC_DLL_MO_CLK90OFF_SHIFT)
-#  define MPDDRC_DLL_MO_CLK90OFF(n)     ((n) << MPDDRC_DLL_MO_CLK90OFF_SHIFT)
-#define MPDDRC_DLL_MO_SELOFF            (1 << 16) /* Bit 16: DLL Offset Selection */
+#define MPDDRC_DLL_MOR_MOFF_SHIFT       (0)       /* Bits 0-3: DLL Master Delay Line Offset */
+#define MPDDRC_DLL_MOR_MOFF_MASK        (15 << MPDDRC_DLL_MOR_MOFF_SHIFT)
+#  define MPDDRC_DLL_MOR_MOFF(n)        ((n) << MPDDRC_DLL_MOR_MOFF_SHIFT)
+#define MPDDRC_DLL_MOR_CLK90OFF_SHIFT   (8)       /* Bits 8-12: DLL CLK90 Delay Line Offset */
+#define MPDDRC_DLL_MOR_CLK90OFF_MASK    (31 << MPDDRC_DLL_MOR_CLK90OFF_SHIFT)
+#  define MPDDRC_DLL_MOR_CLK90OFF(n)    ((n) << MPDDRC_DLL_MOR_CLK90OFF_SHIFT)
+#define MPDDRC_DLL_MOR_SELOFF           (1 << 16) /* Bit 16: DLL Offset Selection */
+#define MPDDRC_DLL_MOR_KEY_SHIFT        (24)      /* Bits 24-31: DLL CLK90 Delay Line Offset (REVISIT) */
+#define MPDDRC_DLL_MOR_KEY_MASK         (0xff << MPDDRC_DLL_MOR_CLK90OFF_SHIFT)
+#  define MPDDRC_DLL_MOR_KEY            (0xc5 << MPDDRC_DLL_MOR_CLK90OFF_SHIFT)
 
 /* MPDDRC DLL Slave Offset Register */
 
-#define MPDDRC_DLL_SOF_S0OFF_SHIFT      (0)     /* Bits 0-4: DLL Slave 0 Delay Line Offset */
-#define MPDDRC_DLL_SOF_S0OFF_MASK       (31 << MPDDRC_DLL_SOF_S0OFF_SHIFT)
-#  define MPDDRC_DLL_SOF_S0OFF(n)       ((n) << MPDDRC_DLL_SOF_S0OFF_SHIFT)
-#define MPDDRC_DLL_SOF_S1OFF_SHIFT      (8)     /* Bits 8-12: DLL Slave 1 Delay Line Offset */
-#define MPDDRC_DLL_SOF_S1OFF_MASK       (31 << MPDDRC_DLL_SOF_S1OFF_SHIFT)
-#  define MPDDRC_DLL_SOF_S1OFF(n)       ((n) << MPDDRC_DLL_SOF_S1OFF_SHIFT)
-#define MPDDRC_DLL_SOF_S2OFF_SHIFT      (16)     /* Bits 16-20: DLL Slave 2 Delay Line Offset */
-#define MPDDRC_DLL_SOF_S2OFF_MASK       (31 << MPDDRC_DLL_SOF_S2OFF_SHIFT)
-#  define MPDDRC_DLL_SOF_S2OFF(n)       ((n) << MPDDRC_DLL_SOF_S2OFF_SHIFT)
-#define MPDDRC_DLL_SOF_S3OFF_SHIFT      (24)     /* Bits 24-28: DLL Slave 3 Delay Line Offset */
-#define MPDDRC_DLL_SOF_S3OFF_MASK       (31 << MPDDRC_DLL_SOF_S3OFF_SHIFT)
-#  define MPDDRC_DLL_SOF_S3OFF(n)       ((n) << MPDDRC_DLL_SOF_S3OFF_SHIFT)
+#define MPDDRC_DLL_SOR_S0OFF_SHIFT      (0)     /* Bits 0-4: DLL Slave 0 Delay Line Offset */
+#define MPDDRC_DLL_SOR_S0OFF_MASK       (31 << MPDDRC_DLL_SOR_S0OFF_SHIFT)
+#  define MPDDRC_DLL_SOR_S0OFF(n)       ((n) << MPDDRC_DLL_SOR_S0OFF_SHIFT)
+#define MPDDRC_DLL_SOR_S1OFF_SHIFT      (8)     /* Bits 8-12: DLL Slave 1 Delay Line Offset */
+#define MPDDRC_DLL_SOR_S1OFF_MASK       (31 << MPDDRC_DLL_SOR_S1OFF_SHIFT)
+#  define MPDDRC_DLL_SOR_S1OFF(n)       ((n) << MPDDRC_DLL_SOR_S1OFF_SHIFT)
+#define MPDDRC_DLL_SOR_S2OFF_SHIFT      (16)     /* Bits 16-20: DLL Slave 2 Delay Line Offset */
+#define MPDDRC_DLL_SOR_S2OFF_MASK       (31 << MPDDRC_DLL_SOR_S2OFF_SHIFT)
+#  define MPDDRC_DLL_SOR_S2OFF(n)       ((n) << MPDDRC_DLL_SOR_S2OFF_SHIFT)
+#define MPDDRC_DLL_SOR_S3OFF_SHIFT      (24)     /* Bits 24-28: DLL Slave 3 Delay Line Offset */
+#define MPDDRC_DLL_SOR_S3OFF_MASK       (31 << MPDDRC_DLL_SOR_S3OFF_SHIFT)
+#  define MPDDRC_DLL_SOR_S3OFF(n)       ((n) << MPDDRC_DLL_SOR_S3OFF_SHIFT)
 
 /* MPDDRC DLL Status Master Register */
 
diff --git a/nuttx/arch/arm/src/sama5/chip/sam_pmc.h b/nuttx/arch/arm/src/sama5/chip/sam_pmc.h
index ac3946b6f..c1e801d84 100644
--- a/nuttx/arch/arm/src/sama5/chip/sam_pmc.h
+++ b/nuttx/arch/arm/src/sama5/chip/sam_pmc.h
@@ -133,7 +133,7 @@
 #define PMC_LCDCK                      (1 << 3)  /* Bit 3:  LCD2x Clock */
 #define PMC_SMDCK                      (1 << 4)  /* Bit 4:  SMD Clock */
 #define PMC_UHP                        (1 << 6)  /* Bit 6:  USB Host OHCI Clocks */
-#define PMC_UDP                        (1 << 7)  /* Bit 7: USB Device Clock */
+#define PMC_UDP                        (1 << 7)  /* Bit 7:  USB Device Clock */
 #define PMC_PCK0                       (1 << 8)  /* Bit 8:  Programmable Clock 0 Output */
 #define PMC_PCK1                       (1 << 9)  /* Bit 9:  Programmable Clock 1 Output */
 #define PMC_PCK2                       (1 << 10) /* Bit 10: Programmable Clock 2 Output */
diff --git a/nuttx/arch/arm/src/sama5/chip/sam_sfr.h b/nuttx/arch/arm/src/sama5/chip/sam_sfr.h
index 154af5a43..9ea3600a5 100644
--- a/nuttx/arch/arm/src/sama5/chip/sam_sfr.h
+++ b/nuttx/arch/arm/src/sama5/chip/sam_sfr.h
@@ -49,7 +49,9 @@
 /* SFR Register Offsets *************************************************************/
 
                                            /* 0x0000-0x000c: Reserved */
-#define SAM_SFR_OHCIICR_OFFSET      0x1000 /* OHCI Interrupt Configuration Register */
+#define SAM_SFR_DDRCFG_OFFSET       0x0004 /* DDR Configuration register (undocumented) */
+                                           /* 0x0000-0x000c: Reserved */
+#define SAM_SFR_OHCIICR_OFFSET      0x0010 /* OHCI Interrupt Configuration Register */
 #define SAM_SFR_OHCIISR_OFFSET      0x0014 /* OHCI Interrupt Status Register */
                                            /* 0x0018-0x001c: Reserved */
 #define SAM_SFR_SECURE_OFFSET       0x0028 /* Security Configuration Register */
@@ -60,6 +62,7 @@
 
 /* SFR Register Addresses ***********************************************************/
 
+#define SAM_SFR_DDRCFG              (SAM_SFR_VBASE+SAM_SFR_DDRCFG_OFFSET) /* REVISIT */
 #define SAM_SFR_OHCIICR             (SAM_SFR_VBASE+SAM_SFR_OHCIICR_OFFSET)
 #define SAM_SFR_OHCIISR             (SAM_SFR_VBASE+SAM_SFR_OHCIISR_OFFSET)
 #define SAM_SFR_SECURE              (SAM_SFR_VBASE+SAM_SFR_SECURE_OFFSET)
@@ -68,6 +71,10 @@
 
 /* SFR Register Bit Definitions *****************************************************/
 
+/* DDR Configuration register (undocumented, REVISIT) */
+
+#define SFR_DDRCFG_DRQON            (3 << 16) /* Force DDR_DQ and DDR_DQS input buffer always on */
+
 /* OHCI Interrupt Configuration Register */
 
 #define SFR_OHCIICR_RES0            (1 << 0)  /* Bit 0:  USB port 0 reset */
diff --git a/nuttx/configs/sama5d3x-ek/src/Makefile b/nuttx/configs/sama5d3x-ek/src/Makefile
index 1ae5ae4cf..7e94a01ee 100644
--- a/nuttx/configs/sama5d3x-ek/src/Makefile
+++ b/nuttx/configs/sama5d3x-ek/src/Makefile
@@ -46,6 +46,10 @@ ifeq ($(CONFIG_HAVE_CXX),y)
 CSRCS += sam_cxxinitialize.c
 endif
 
+ifeq ($(CONFIG_SAMA5_DDRCS),y)
+CSRCS += sam_sdram.c
+endif
+
 ifeq ($(CONFIG_SAMA5_BOOT_CS0FLASH),y)
 CSRCS += sam_norflash.c
 endif
diff --git a/nuttx/configs/sama5d3x-ek/src/sam_norflash.c b/nuttx/configs/sama5d3x-ek/src/sam_norflash.c
index 3604dcfc2..1b4ff0c3f 100644
--- a/nuttx/configs/sama5d3x-ek/src/sam_norflash.c
+++ b/nuttx/configs/sama5d3x-ek/src/sam_norflash.c
@@ -1,9 +1,16 @@
-/************************************************************************************
+/****************************************************************************
  * configs/sama5d3x-ek/src/sam_norflash.c
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
  *
+ * Most of this file derives from Atmel sample code for the SAMA5D3x-EK
+ * board.  That sample code has licensing that is compatible with the NuttX
+ * modified BSD license:
+ *
+ *   Copyright (c) 2012, Atmel Corporation
+ *   All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
@@ -14,8 +21,8 @@
  *    notice, this list of conditions and the following disclaimer in
  *    the documentation and/or other materials provided with the
  *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
+ * 3. Neither the name NuttX nor Atmel nor the names of its contributors may
+ *    be used to endorse or promote products derived from this software
  *    without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
@@ -31,11 +38,11 @@
  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  *
- ************************************************************************************/
+ ****************************************************************************/
 
-/************************************************************************************
+/****************************************************************************
  * Included Files
- ************************************************************************************/
+ ****************************************************************************/
 
 #include <nuttx/config.h>
 
@@ -49,17 +56,17 @@
 
 #ifdef CONFIG_SAMA5_BOOT_CS0FLASH
 
-/************************************************************************************
- * Definitions
- ************************************************************************************/
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
 
-/************************************************************************************
+/****************************************************************************
  * Private Functions
- ************************************************************************************/
+ ****************************************************************************/
 
-/************************************************************************************
+/****************************************************************************
  * Public Functions
- ************************************************************************************/
+ ****************************************************************************/
 
 /****************************************************************************
  * Name: board_norflash_config
diff --git a/nuttx/configs/sama5d3x-ek/src/sam_sdram.c b/nuttx/configs/sama5d3x-ek/src/sam_sdram.c
new file mode 100644
index 000000000..71b9748dd
--- /dev/null
+++ b/nuttx/configs/sama5d3x-ek/src/sam_sdram.c
@@ -0,0 +1,548 @@
+/****************************************************************************
+ * configs/sama5d3x-ek/src/sam_sdram.c
+ *
+ *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Most of this file derives from Atmel sample code for the SAMA5D3x-E
+ * board.  That sample code has licensing that is compatible with the NuttX
+ * modified BSD license:
+ *
+ *   Copyright (c) 2012, Atmel Corporation
+ *   All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor Atmel nor the names of its contributors may
+ *    be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <debug.h>
+
+#include "up_arch.h"
+
+#include "sam_periphclks.h"
+#incldue "chip/sam_memorymap.h"
+#include "chip/sam_pmc.h"
+#include "chip/sam_sfr.h"
+
+#include "sama5d3x-ek.h"
+
+/* This file requires:
+ *
+ * CONFIG_SAMA5_DDRCS -- DRAM support is enabled, and
+ * !CONFIG_SAMA5_BOOT_SDRAM - We did not boot into SRAM, and
+ * !CONFIG_BOOT_RUNFROMSDRAM - We are not running from SDRAM.
+ */
+
+#if defined(CONFIG_SAMA5_DDRCS) && !defined(CONFIG_SAMA5_BOOT_SDRAM) && \
+   !defined(CONFIG_BOOT_RUNFROMSDRAM)
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+/* Used for SDRAM command handshaking */
+
+#define DDR2_BA0(r) (1 << (25 + r))
+#define DDR2_BA1(r) (1 << (26 + r))
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: board_sdram_delay
+ *
+ * Description:
+ *   Precision delay function for SDRAM configuration.
+ *
+ *   This delay loop requires 6 core cycles per iteration.  At 396MHz, that
+ *   is equivalent to 15.1515 nanoseconds per iteration.
+ *
+ ****************************************************************************/
+
+static inline board_sdram_delay(unsigned int loops)
+{
+  volatile unsigned int i;
+
+  for (i = 0; i < loops; i++)
+    {
+      asm("nop");
+    }
+}
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Name: board_sdram_config
+ *
+ * Description:
+ *   Configures DDR2 (MT47H128M16RT 128MB/ MT47H64M16HR)
+ *
+ *     MT47H64M16HR : 8 Meg x 16 x 8 banks
+ *     Refresh count: 8K
+ *     Row address: A[12:0] (8K)
+ *     Column address A[9:0] (1K)
+ *     Bank address BA[2:0] a(24,25) (8)
+ *
+ *  This logic was taken from Atmel sample code for the SAMA5D3x-EK.
+ *
+ *  Input Parameters:
+ *     devtype - Either DDRAM_MT47H128M16RT or DDRAM_MT47H64M16HR
+ *
+ *  Assumptions:
+ *    The DDR memory regions is configured as strongly ordered memory.  When
+ *    we complete initialization of SDRAM and it is ready for use, we will
+ *    make DRAM into normal memory.
+ *
+ ************************************************************************************/
+
+void board_sdram_config(uint8_t sdramtype)
+{
+  volatile uint8_t *ddr = (uint8_t *)SAM_DDRCS_VSECTION;
+  uint32_t regval;
+
+  /* Enable x2 clocking to the MPDDRC */
+
+  sam_mpddrc_enableclk();
+
+  /* Enable DDR clocking */
+
+  regval  = getreg32(SAM_PMC_SCER);
+  regval |= SAM_PMC_SCER;
+  putreg32(regval, SAM_PMC_SCER);
+
+  /* Clear the low power register */
+
+  putreg32(0, SAM_MPDDRC_LPR);
+
+  /* Enabled autofresh during calibration (undocumented) */
+
+  regval  = getreg32(SAM_MPDDRC_HS);
+  regval |= MPDDRC_HS_AUTOREFRESH_CAL;
+  putreg32(regval, SAM_MPDDRC_HS);
+
+  /* Force DDR_DQ and DDR_DQS input buffer always on (undocumented) */
+
+  regval  = getreg32(SAM_SFR_DDRCFG);
+  regval |= SFR_DDRCFG_DRQON;
+  putreg32(regval, SAM_SFR_DDRCFG);
+
+  /* Configure the slave offset register */
+
+  regval = MPDDRC_DLL_SOR_S0OFF(1) |      /* DLL Slave 0 Delay Line Offset */
+           MPDDRC_DLL_SOR_S1OFF(0) |      /* DLL Slave 1 Delay Line Offset */
+           MPDDRC_DLL_SOR_S2OFF(1) |      /* DLL Slave 2 Delay Line Offset */
+           MPDDRC_DLL_SOR_S3OFF(1);       /* DLL Slave 3 Delay Line Offset */
+  putreg32(regval, SAM_MPDDRC_DLL_SOR);
+
+  /* Configure the master offset register (including upper mystery bits) */
+
+  regval = MPDDRC_DLL_MOR_MOFF(7) |       /* DLL Master Delay Line Offset */
+           MPDDRC_DLL_MOR_CLK90OFF(31) |  /* DLL CLK90 Delay Line Offset */
+           MPDDRC_DLL_MOR_SELOFF |        /* DLL Offset Selection */
+           MPDDRC_DLL_MOR_KEY |           /* Undocumented key */
+  putreg32(regval, SAM_MPDDRC_DLL_MOR);
+
+  /* Configure the I/O calibration register */
+
+  regval  =  getreg32(SAM_MPDDRC_IO_CALIBR);
+  regval &= ~(MPDDRC_IO_CALIBR_RDIV_MASK | MPDDRC_IO_CALIBR_TZQIO_MASK);
+  regval |= (MPDDRC_IO_CALIBR_RZQ48_40 |  MPDDRC_IO_CALIBR_TZQIO(3));
+  putreg(regval, SAM_MPDDRC_IO_CALIBR);
+
+  /* Force DDR_DQ and DDR_DQS input buffer always on, clearing other bits
+   * (undocumented)
+   */
+
+  putreg32(SFR_DDRCFG_DRQON, SAM_SFR_DDRCFG);
+
+  /* Step 1: Program the memory device type
+   *
+   *   DBW = 0 (32-bit bus wide)
+   *   Memory Device = DDR2-SDRAM
+   */
+
+  putreg32(MPDDRC_MD_DDR2_SDRAM, SAM_MPDDRC_MD);
+
+  /* Step 2: Program the features of DDR2-SDRAM device into the Timing
+   * Register
+   *
+   * For DDRAM_MT47H128M16RT
+   *
+   *   NC      = 10 DDR column bits
+   *   NR      = 14 DDR row bits
+   *   CAS     = DDR2/LPDDR2 CAS Latency 4
+   *   DLL     = Disable reset (0)
+   *   DIC_DS  = 0
+   *   DIS_DLL = Enable PLL (0)
+   *   ZQ      = Calibration command after initialization (0)
+   *   OCD     = OCD calibration mode exit, maintain setting (0)
+   *   DQMS    = Not shared (0)
+   *   ENDRM   = Disable read measure (0)
+   *   NB      = 8 banks
+   *   NDQS    = Not DQS disabled
+   *   DECODE  = Sequential decoding (0)
+   *   UNAL    = Unaliged access supported
+   */
+
+  if (sdramtype == DDRAM_MT47H128M16RT)
+    {
+      regval = MPDDRC_CR_NC_10 |    /* Number of Column Bits */
+               MPDDRC_CR_NR_14 |    /* Number of Row Bits */
+               MPDDRC_CR_CAS_4 |    /* CAS Latency */
+               MPDDRC_CR_OCD_EXIT | /* Off-chip Driver */
+               MPDDRC_CR_8BANKS |   /* Number of Banks */
+               MPDDRC_CR_NDQS |     /* Not DQS */
+               MPDDRC_CR_UNAL;      /* upport Unaligned Access */
+      putreg32(regval, SAM_MPDDRC_CR);
+    }
+
+  /* For DDRAM_MT47H128M16RT
+   *
+   *   NC      = 10 DDR column bits
+   *   NR      = 13 DDR row bits
+   *   CAS     = DDR2/LPDDR2 CAS Latency 3
+   *   DLL     = Disable reset (0)
+   *   DIC_DS  = 0
+   *   DIS_DLL = Enable PLL (0)
+   *   ZQ      = Calibration command after initialization (0)
+   *   OCD     = OCD calibration mode exit, maintain setting (0)
+   *   DQMS    = Not shared (0)
+   *   ENDRM   = Disable read measure (0)
+   *   NB      = 8 banks
+   *   NDQS    = Not DQS disabled
+   *   DECODE  = Sequential decoding (0)
+   *   UNAL    = Unaliged access supported
+   */
+
+  else if (sdramtype == DDRAM_MT47H64M16HR)
+    {
+      regval = MPDDRC_CR_NC_10 |    /* Number of Column Bits */
+               MPDDRC_CR_NR_13 |    /* Number of Row Bits */
+               MPDDRC_CR_CAS_3 |    /* CAS Latency */
+               MPDDRC_CR_OCD_EXIT | /* Off-chip Driver */
+               MPDDRC_CR_8BANKS |   /* Number of Banks */
+               MPDDRC_CR_NDQS |     /* Not DQS */
+               MPDDRC_CR_UNAL;      /* upport Unaligned Access */
+      putreg32(regval, SAM_MPDDRC_CR);
+    }
+
+  /* Configure the Timing Parameter 0 Register */
+
+  regval = MPDDRC_TPR0_TRAS(6) |    /*  Active to Precharge Delay:    6 * 7.5 = 45 ns */
+           MPDDRC_TPR0_TRCD(2) |    /*  Row to Column Delay:          2 * 7.5 = 15 ns */
+           MPDDRC_TPR0_TWR(2) |     /*  Write Recovery Delay:         3 * 7.5 = 22.5 ns */
+           MPDDRC_TPR0_TRC(8) |     /*  Row Cycle Delay:              8 * 7.5 = 60 ns */
+           MPDDRC_TPR0_TRP(2) |     /*  Row Precharge Delay:          2 * 7.5 = 15 ns */
+           MPDDRC_TPR0_TRRD(1) |    /*  Active BankA to Active BankB: 2 * 7.5 = 15 ns */
+           MPDDRC_TPR0_TWTR(2) |    /*  Internal Write to Read Delay: 2 clock cycle */
+           MPDDRC_TPR0_TMRD(2);     /*  Load Mode Register Command to
+                                     *  Activate or Refresh Command:  2 clock cycles */
+  putreg32(regval, SAM_MPDDRC_TPR0);
+
+  /* Configure the Timing Parameter 1 Register */
+
+  regval = MPDDRC_TPR1_TRFC(14) |   /* Row Cycle Delay:
+                                     *   18 * 7.5 = 135 ns (min 127.5 ns for 1Gb DDR) */
+           MPDDRC_TPR1_TXSNR(16) |  /* Exit Self Refresh Delay to Non Read Command:
+                                     *   20 * 7.5 > 142.5ns TXSNR: Exit self refresh
+                                     *   delay to non read command */
+           MPDDRC_TPR1_TXSRD(208) | /* Exit Self Refresh Delay to Read Command:
+                                     *   min 200 clock cycles, TXSRD: Exit self refresh
+                                     *   delay to Read command */
+           MPDDRC_TPR1_TXP(2);      /* Exit Power-down Delay to First Command:
+                                     *   2 * 7.5 = 15 ns */
+  putreg32(regval, SAM_MPDDRC_TPR1);
+
+  /* Configure the Timing Parameter 2 Register */
+
+  regval = MPDDRC_TPR2_TXARD(7) |   /* Exit Active Power Down Delay to Read Command in Mode 'Fast Exit':
+                                     *   min 2 clock cycles */
+           MPDDRC_TPR2_TXARDS(7) |  /* Exit Active Power Down Delay to Read Command in Mode 'Slow Exit':
+                                     *   min 7 clock cycles */
+           MPDDRC_TPR2_TRPA(2) |    /* Row Precharge All Delay:
+                                     *   min 18ns */
+           MPDDRC_TPR2_TRTP(2) |    /* Four Active Windows:
+                                     *   2 * 7.5 = 15 ns (min 7.5ns) */
+           MPDDRC_TPR2_TFAW(10) ;
+  putreg32(regval, SAM_MPDDRC_TPR2);
+
+  /* DDRSDRC Low-power Register */
+
+  board_sdram_delay(13200);
+
+  regval = MPDDRC_LPR_LPCB_DISABLED |  /* Low-power Feature is inhibited */
+           MPDDRC_LPR_TIMEOUT_0CLKS |  /* Activates low-power mode after the end of transfer */
+           MPDDRC_LPR_APDE_FAST;       /* Active Power Down Exit Time */
+  putreg32(regval, SAM_MPDDRC_LPR);
+
+  /* Step 3: An NOP command is issued to the DDR2-SDRAM. Program the NOP
+   * command into the Mode Register, the application must set MODE to 1 in
+   * the Mode Register.
+   */
+
+  putreg32(MPDDRC_MR_MODE_NOP, SAM_MPDDRC_MR);
+
+  /* Perform a write access to any DDR2-SDRAM address to acknowledge this
+   * command.
+   */
+
+  *ddr = 0;
+
+  /* Now clocks which drive DDR2-SDRAM device are enabled.*/
+  /* Step 4:  An NOP command is issued to the DDR2-SDRAM */
+
+  putreg32(MPDDRC_MR_MODE_NOP, SAM_MPDDRC_MR);
+
+  /* Perform a write access to any DDR2-SDRAM address to acknowledge this command.*/
+
+  *ddr = 0;
+
+  /* Now CKE is driven high.*/
+  /* Wait 400 ns min */
+
+  board_sdram_delay(100);
+
+  /* Step 5: An all banks precharge command is issued to the DDR2-SDRAM. */
+
+  putreg32(MPDDRC_MR_MODE_PRCGALL, SAM_MPDDRC_MR);
+
+  /* Perform a write access to any DDR2-SDRAM address to acknowledge this command.*/
+
+  *ddr = 0;
+
+  /* Wait 400 ns min */
+
+  board_sdram_delay(100);
+
+  /* Step 6: An Extended Mode Register set (EMRS2) cycle is  issued to chose
+   * between commercialor high  temperature operations.
+   *
+   * The write address must be chosen so that BA[1] is set to 1 and BA[0] is
+   * set to 0.
+   */
+
+  putreg32(MPDDRC_MR_MODE_EXTLMR, SAM_MPDDRC_MR);
+  *((uint8_t *)(ddr + DDR2_BA1(sdramtype))) = 0;
+
+  /* Wait 2 cycles min */
+
+  board_sdram_delay(100);
+
+  /* Step 7: An Extended Mode Register set (EMRS3) cycle is issued to set
+   * all registers to 0.
+   *
+   * The write address must be chosen so that BA[1] is set to 1 and BA[0] is
+   * set to 1.
+   */
+
+  putreg32(MPDDRC_MR_MODE_EXTLMR, SAM_MPDDRC_MR);
+  *((uint8_t *)(ddr + DDR2_BA1(sdramtype) + DDR2_BA0(sdramtype))) = 0;
+
+  /* Wait 2 cycles min */
+
+  board_sdram_delay(100);
+
+   /* Step 8:  An Extended Mode Register set (EMRS1) cycle is issued to enable DLL.
+    *
+    * The write address must be chosen so that BA[1] is set to 0 and BA[0] is set to 1.
+    */
+
+  putreg32(MPDDRC_MR_MODE_EXTLMR, SAM_MPDDRC_MR);
+  *((uint8_t *)(ddr + DDR2_BA0(sdramtype))) = 0;
+
+  /* An additional 200 cycles of clock are required for locking DLL */
+
+  board_sdram_delay(10000);
+
+  /* Step 9:  Program DLL field into the Configuration Register.*/
+
+  regval  = getreg32(SAM_MPDDRC_CR);
+  regval |= MPDDRC_CR_DLL;
+  putreg32(regval, SAM_MPDDRC_CR);
+
+  /* Step 10: A Mode Register set (MRS) cycle is issued to reset DLL.
+   *
+   * The write address must be chosen so that BA[1:0] bits are set to 0.
+   */
+
+  putreg32(MPDDRC_MR_MODE_LMR, SAM_MPDDRC_MR);
+  *ddr = 0;
+
+  /* Wait 2 cycles min */
+
+  board_sdram_delay(100);
+
+  /* Step 11: An all banks precharge command is issued to the DDR2-SDRAM.
+   *
+   * Perform a write access to any DDR2-SDRAM address to acknowledge this command */
+   */
+
+  putreg32(MPDDRC_MR_MODE_PRCGALL, SAM_MPDDRC_MR);
+  *ddr = 0;
+
+  /* Wait 2 cycles min */
+
+  board_sdram_delay(100);
+
+  /* Step 12: Two auto-refresh (CBR) cycles are provided. Program the auto
+   * refresh command (CBR) into the Mode Register.
+   *
+   * Perform a write access to any DDR2-SDRAM address to acknowledge this
+   * command.
+   */
+
+  putreg32(MPDDRC_MR_MODE_RFSH, SAM_MPDDRC_MR);
+  *ddr = 0;
+
+  /* Wait 2 cycles min */
+
+  board_sdram_delay(100);
+
+  /* Configure 2nd CBR.
+   *
+   * Perform a write access to any DDR2-SDRAM address to acknowledge this command.
+   */
+
+  putreg32(MPDDRC_MR_MODE_RFSH, SAM_MPDDRC_MR);
+  *ddr = 0;
+
+  /* Wait 2 cycles min */
+
+  board_sdram_delay(100);
+
+  /* Step 13: Program DLL field into the Configuration Register to low
+   * (Disable DLL reset).
+   */
+
+  regval  = getreg32(SAM_MPDDRC_CR);
+  regval &= ~MPDDRC_CR_DLL;
+  putreg32(regval, SAM_MPDDRC_CR);
+
+  /* Step 14: A Mode Register set (MRS) cycle is issued to program the
+   * parameters of the DDR2-SDRAM devices.
+   *
+   * The write address must be chosen so that BA[1:0] are set to 0.
+   */
+
+  putreg32(MPDDRC_MR_MODE_LMR, SAM_MPDDRC_MR);
+  *ddr = 0;
+
+  /* Wait 2 cycles min */
+
+  board_sdram_delay(100);
+
+  /* Step 15: Program OCD field into the Configuration Register to high (OCD
+   * calibration default).
+   */
+
+  regval  = getreg32(SAM_MPDDRC_CR);
+  retval |= MPDDRC_CR_OCD_DEFAULT;
+  putreg32(regval, SAM_MPDDRC_CR);
+
+  /* Step 16: An Extended Mode Register set (EMRS1) cycle is issued to OCD
+   * default value.
+   *
+   * The write address must be chosen so that BA[1] is set to 0 and BA[0] is
+   * set to 1.
+   */
+
+  putreg32(MPDDRC_MR_MODE_EXTLMR, SAM_MPDDRC_MR);
+  *((uint8_t *)(ddr + DDR2_BA0(sdramtype))) = 0;
+
+  /* Wait 2 cycles min */
+
+  board_sdram_delay(100);
+
+  /* Step 17: Program OCD field into the Configuration Register to low (OCD
+   * calibration mode exit).
+   */
+
+#if 0
+  regval  = getreg32(SAM_MPDDRC_CR);
+  regval &= ~MPDDRC_CR_OCD_MASK;
+  putreg32(regval, SAM_MPDDRC_CR);
+#endif
+
+  /* Step 18: An Extended Mode Register set (EMRS1) cycle is issued to
+   * enable OCD exit.
+   *
+   * The write address must be chosen so that BA[1] is set to 0 and BA[0] is
+   * set to 1.
+   */
+
+  putreg32(MPDDRC_MR_MODE_EXTLMR, SAM_MPDDRC_MR);
+  *((uint8_t *)(ddr + DDR2_BA0(sdramtype))) = 0;
+
+  /* Wait 2 cycles min */
+
+  board_sdram_delay(100);
+
+  /* Step 19,20: A mode Normal command is provided. Program the Normal mode
+   * into Mode Register.
+   */
+
+  putreg32(MPDDRC_MR_MODE_NORMAL, SAM_MPDDRC_MR);
+  *ddr = 0;
+
+  /* Step 21: Write the refresh rate into the count field in the Refresh
+   * Timer register. The DDR2-SDRAM device requires a refresh every 15.625
+   * usec or 7.81 usec.
+   *
+   * With a 100MHz frequency, the refresh timer count register must to be
+   * set with (15.625 /100 MHz) = 1562 i.e. 0x061A or (7.81 /100MHz) = 781
+   * i.e. 0x030d.
+   */
+
+  /* For MT47H64M16HR, The refresh period is 64ms (commercial), This equates
+   * to an average refresh rate of 7.8125usec (commercial), To ensure all
+   * rows of all banks are properly refreshed, 8192 REFRESH commands must be
+   * issued every 64ms (commercial)
+   */
+
+  /* ((64 x 10(^-3))/8192) x133 x (10^6) */
+  /* Set Refresh timer 7.8125 us */
+
+  putreg32( MPDDRC_RTR_COUNT(300), SAM_MPDDRC_RTR);
+
+  /* OK now we are ready to work on the DDRSDR */
+  /* Wait for end of calibration */
+
+  board_sdram_delay(500);
+#warning Make SDRAM cacheable
+}
+
+#endif /* CONFIG_SAMA5_DDRCS && !CONFIG_SAMA5_BOOT_SDRAM && !CONFIG_BOOT_RUNFROMSDRAM */
+#endif /* CONFIG_SAMA5_BOOT_CS0FLASH */
diff --git a/nuttx/configs/sama5d3x-ek/src/sama5d3x-ek.h b/nuttx/configs/sama5d3x-ek/src/sama5d3x-ek.h
index 7c9c45f06..2b2a0d7fb 100644
--- a/nuttx/configs/sama5d3x-ek/src/sama5d3x-ek.h
+++ b/nuttx/configs/sama5d3x-ek/src/sama5d3x-ek.h
@@ -109,6 +109,37 @@
  ************************************************************************************/
 
 /************************************************************************************
+ * Name: board_sdram_config
+ *
+ * Description:
+ *   Configures DDR2 (MT47H128M16RT 128MB/ MT47H64M16HR)
+ *
+ *     MT47H64M16HR : 8 Meg x 16 x 8 banks
+ *     Refresh count: 8K
+ *     Row address: A[12:0] (8K)
+ *     Column address A[9:0] (1K)
+ *     Bank address BA[2:0] a(24,25) (8)
+ *
+ *  This logic was taken from Atmel sample code for the SAMA5D3x-EK.
+ *
+ *  Input Parameters:
+ *     devtype - Either DDRAM_MT47H128M16RT or DDRAM_MT47H64M16HR
+ *
+ *  Assumptions:
+ *    The DDR memory regions is configured as strongly ordered memory.  When we
+ *    complete initialization of SDRAM and it is ready for use, we will make DRAM
+ *    into normal memory.
+ *
+ ************************************************************************************/
+
+#if defined(CONFIG_SAMA5_DDRCS) && !defined(CONFIG_SAMA5_BOOT_SDRAM) && \
+   !defined(CONFIG_BOOT_RUNFROMSDRAM)
+void board_sdram_config(uint8_t sdramtype);
+#else
+#  define board_sdram_config(t)
+#endif
+
+/************************************************************************************
  * Name: up_ledinit
  ************************************************************************************/