diff options
author | Gregory Nutt <gnutt@nuttx.org> | 2013-06-04 15:12:56 -0600 |
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committer | Gregory Nutt <gnutt@nuttx.org> | 2013-06-04 15:12:56 -0600 |
commit | 9172affc0d3603a09cf55ea169715acb87dc1f8e (patch) | |
tree | dac4fea7834bafd154a9d7e5ec2aa5f77f134e05 | |
parent | 1344f8cc1c7e76dd50752b3e34ccf19dea9619cb (diff) | |
download | nuttx-9172affc0d3603a09cf55ea169715acb87dc1f8e.tar.gz nuttx-9172affc0d3603a09cf55ea169715acb87dc1f8e.tar.bz2 nuttx-9172affc0d3603a09cf55ea169715acb87dc1f8e.zip |
Add SAM4L GPIO driver
-rw-r--r-- | nuttx/ChangeLog | 3 | ||||
-rw-r--r-- | nuttx/arch/arm/src/sam34/Make.defs | 10 | ||||
-rw-r--r-- | nuttx/arch/arm/src/sam34/chip/sam4l_gpio.h | 42 | ||||
-rw-r--r-- | nuttx/arch/arm/src/sam34/sam3u_gpio.c (renamed from nuttx/arch/arm/src/sam34/sam_gpio.c) | 2 | ||||
-rw-r--r-- | nuttx/arch/arm/src/sam34/sam4l_gpio.c | 569 | ||||
-rw-r--r-- | nuttx/arch/arm/src/sam34/sam4l_gpio.h | 24 |
6 files changed, 609 insertions, 41 deletions
diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index 08ef5784f..fcde5f0c2 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -4894,3 +4894,6 @@ * nuttx/arch/arm/src/sam34/sam4l_gpio.h: Created GPIO driver header file for the SAM4L. Also renamed the SAM3U header file to sam3u_gpio.h (2013-6-4). + * nuttx/arch/arm/src/sam34/sam4l_gpio.c: Created GPIO driver for + the SAM4L (2013-6-4). + diff --git a/nuttx/arch/arm/src/sam34/Make.defs b/nuttx/arch/arm/src/sam34/Make.defs index 813bcbe4c..683751bb5 100644 --- a/nuttx/arch/arm/src/sam34/Make.defs +++ b/nuttx/arch/arm/src/sam34/Make.defs @@ -78,11 +78,17 @@ endif CHIP_ASRCS = CHIP_CSRCS = sam_allocateheap.c sam_clockconfig.c sam_gpioirq.c -CHIP_CSRCS += sam_irq.c sam_lowputc.c sam_gpio.c sam_serial.c -CHIP_CSRCS += sam_start.c sam_timerisr.c +CHIP_CSRCS += sam_irq.c sam_lowputc.c sam_serial.c sam_start.c +CHIP_CSRCS += sam_timerisr.c # Configuration-dependent SAM3/4 files +ifeq ($(CONFIG_ARCH_CHIP_SAM4L),y) +CHIP_CSRCS += sam4l_gpio.c +else +CHIP_CSRCS += sam3u_gpio.c +endif + ifeq ($(CONFIG_NUTTX_KERNEL),y) CHIP_CSRCS += sam_userspace.c sam_mpuinit.c endif diff --git a/nuttx/arch/arm/src/sam34/chip/sam4l_gpio.h b/nuttx/arch/arm/src/sam34/chip/sam4l_gpio.h index d180b2b92..4927ab706 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam4l_gpio.h +++ b/nuttx/arch/arm/src/sam34/chip/sam4l_gpio.h @@ -58,10 +58,10 @@ /* {PMR2, PMR1, PMR0} Selected Peripheral Function * - * 000 GPIO 100 D - * 001 A 101 E - * 010 B 110 F - * 011 C 111 G + * 000 A 100 E + * 001 B 101 F + * 010 C 110 G + * 011 D 111 H * * NOTE: Labeling in the data sheet is inconsistent. In the pin multiplexing table, * It shows GPIO functions A-G with 000 apparently corresponding to the GPIO. In the @@ -96,11 +96,7 @@ /* Pin Value Register Read (4 registers)*/ -#define SAM_GPIO_PVR_OFFSET(n) (0x0060 + (((n) & ~31) >> 3)) -#define SAM_GPIO_PVR0_OFFSET 0x0060 /* Pin Value Register 0 Read*/ -#define SAM_GPIO_PVR1_OFFSET 0x0064 /* Pin Value Register 1 Read*/ -#define SAM_GPIO_PVR2_OFFSET 0x0068 /* Pin Value Register 2 Read*/ -#define SAM_GPIO_PVR3_OFFSET 0x006c /* Pin Value Register 3 Read*/ +#define SAM_GPIO_PVR_OFFSET 0x0060 /* Pin Value Register Read */ /* {PUER, PDER} Selected Function * @@ -150,17 +146,13 @@ /* Interrupt Flag Register Read (2 registers)*/ -#define SAM_GPIO_IFR_OFFSET(n) (0x00d0 + (((n) & ~31) >> 3)) -#define SAM_GPIO_IFR0_OFFSET 0x00d0 /* Interrupt Flag Register 0 Read */ -#define SAM_GPIO_IFR1_OFFSET 0x00d4 /* Interrupt Flag Register 0 Read */ +#define SAM_GPIO_IFR_OFFSET 0x00d0 /* Interrupt Flag Register 0 Read */ /* Interrupt Flag Register Clear (2 registers)*/ -#define SAM_GPIO_IFRC_OFFSET(n) (0x00d8 + (((n) & ~31) >> 3)) -#define SAM_GPIO_IFRC0_OFFSET 0x00d8 /* Interrupt Flag Register 0 Clear */ -#define SAM_GPIO_IFRC1_OFFSET 0x00dc /* Interrupt Flag Register 1 Clear */ +#define SAM_GPIO_IFRC _OFFSET 0x00d8 /* Interrupt Flag Register 0 Clear */ -/* {ODCR1, ODCR0} Interrupt Mode +/* {ODCR1, ODCR0} Output drive strength * * 00 Lowest drive strength * 01 ... @@ -230,11 +222,7 @@ /* Pin Value Register Read (4 registers)*/ -#define SAM_GPIO_PVR(n) (SAM_GPIO_BASE+SAM_GPIO_PVR_OFFSET(n)) -#define SAM_GPIO_PVR0 (SAM_GPIO_BASE+SAM_GPIO_PVR0_OFFSET) -#define SAM_GPIO_PVR1 (SAM_GPIO_BASE+SAM_GPIO_PVR1_OFFSET) -#define SAM_GPIO_PVR2 (SAM_GPIO_BASE+SAM_GPIO_PVR2_OFFSET) -#define SAM_GPIO_PVR3 (SAM_GPIO_BASE+SAM_GPIO_PVR3_OFFSET) +#define SAM_GPIO_PVR (SAM_GPIO_BASE+SAM_GPIO_PVR_OFFSET) #define SAM_GPIO_PUER (SAM_GPIO_BASE+SAM_GPIO_PUER_OFFSET) #define SAM_GPIO_PUERS (SAM_GPIO_BASE+SAM_GPIO_PUERS_OFFSET) @@ -266,17 +254,13 @@ #define SAM_GPIO_GFERC (SAM_GPIO_BASE+SAM_GPIO_GFERC_OFFSET) #define SAM_GPIO_GFERT (SAM_GPIO_BASE+SAM_GPIO_GFERT_OFFSET) -/* Interrupt Flag Register Read (2 registers)*/ +/* Interrupt Flag Register Read */ -#define SAM_GPIO_IFR(n) (SAM_GPIO_BASE+SAM_GPIO_IFR_OFFSET(n)) -#define SAM_GPIO_IFR0 (SAM_GPIO_BASE+SAM_GPIO_IFR0_OFFSET) -#define SAM_GPIO_IFR1 (SAM_GPIO_BASE+SAM_GPIO_IFR1_OFFSET) +#define SAM_GPIO_IFR (SAM_GPIO_BASE+SAM_GPIO_IFR_OFFSET) -/* Interrupt Flag Register Clear (2 registers)*/ +/* Interrupt Flag Register Clear */ -#define SAM_GPIO_IFRC(n) (SAM_GPIO_BASE+SAM_GPIO_IFRC_OFFSET(n)) -#define SAM_GPIO_IFRC0 (SAM_GPIO_BASE+SAM_GPIO_IFRC0_OFFSET) -#define SAM_GPIO_IFRC1 (SAM_GPIO_BASE+SAM_GPIO_IFRC1_OFFSET) +#define SAM_GPIO_IFRC (SAM_GPIO_BASE+SAM_GPIO_IFRC_OFFSET) #define SAM_GPIO_ODCR0 (SAM_GPIO_BASE+SAM_GPIO_ODCR0_OFFSET) #define SAM_GPIO_ODCR0S (SAM_GPIO_BASE+SAM_GPIO_ODCR0S_OFFSET) diff --git a/nuttx/arch/arm/src/sam34/sam_gpio.c b/nuttx/arch/arm/src/sam34/sam3u_gpio.c index 0924857b9..271bb2f9b 100644 --- a/nuttx/arch/arm/src/sam34/sam_gpio.c +++ b/nuttx/arch/arm/src/sam34/sam3u_gpio.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/sam34/sam_gpio.c + * arch/arm/src/sam34/sam3u_gpio.c * * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt <gnutt@nuttx.org> diff --git a/nuttx/arch/arm/src/sam34/sam4l_gpio.c b/nuttx/arch/arm/src/sam34/sam4l_gpio.c new file mode 100644 index 000000000..64f1d6000 --- /dev/null +++ b/nuttx/arch/arm/src/sam34/sam4l_gpio.c @@ -0,0 +1,569 @@ +/**************************************************************************** + * arch/arm/src/sam34/sam4l_gpio.c + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include <stdint.h> +#include <time.h> +#include <errno.h> +#include <debug.h> + +#include <nuttx/arch.h> +#include <arch/board/board.h> + +#include "up_internal.h" +#include "up_arch.h" + +#include "chip.h" +#include "sam_gpio.h" +#include "chip/sam4l_gpio.h" + +/**************************************************************************** + * Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_GPIO +static const char g_portchar[4] = { 'A', 'B', 'C', 'D' }; +#endif + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ +/**************************************************************************** + * Name: sam_gpiobase + * + * Description: + * Return the base address of the GPIO register set + * + ****************************************************************************/ + +static inline uintptr_t sam_gpiobase(gpio_pinset_t cfgset) +{ + int port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + return SAM_GPION_BASE(port); +} + +/**************************************************************************** + * Name: sam_gpiopin + * + * Description: + * Returun the base address of the GPIO register set + * + ****************************************************************************/ + +static inline int sam_gpiopin(gpio_pinset_t cfgset) +{ + return 1 << ((cfgset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT); +} + +/**************************************************************************** + * Name: sam_configinput + * + * Description: + * Configure a GPIO input pin based on bit-encoded description of the pin. + * + ****************************************************************************/ + +static int sam_configinput(uintptr_t base, uint32_t pin, gpio_pinset_t cfgset) +{ + /* Disable interrupts on the pin */ + + putreg32(pin, base + SAM_GPIO_IERC_OFFSET); + + /* Disable the output driver and select the GPIO function */ + + putreg32(pin, base + SAM_GPIO_ODERC_OFFSET); + putreg32(pin, base + SAM_GPIO_GPERS_OFFSET); + + /* Clear peripheral-only settings (just to make debug easier) */ + + putreg32(pin, base + SAM_GPIO_PMR0C_OFFSET); + putreg32(pin, base + SAM_GPIO_PMR1C_OFFSET); + putreg32(pin, base + SAM_GPIO_PMR2C_OFFSET); + putreg32(pin, base + SAM_GPIO_EVERC_OFFSET); + + /* Clear output-only settings (just to make debug easier) */ + + putreg32(pin, base + SAM_GPIO_ODCR0C_OFFSET); + putreg32(pin, base + SAM_GPIO_ODCR1C_OFFSET); + putreg32(pin, base + SAM_GPIO_OSRR0C_OFFSET); + + /* Clear the interrupt configuration (just to make debug easier) */ + + putreg32(pin, base + SAM_GPIO_IMR0C_OFFSET); + putreg32(pin, base + SAM_GPIO_IMR1C_OFFSET); + + /* Enable/disable the pull-up as requested */ + + if ((cfgset & GPIO_PULL_UP) != 0) + { + putreg32(pin, base + SAM_GPIO_PUERS_OFFSET); + } + else + { + putreg32(pin, base + SAM_GPIO_PUERC_OFFSET); + } + + if ((cfgset & GPIO_PULL_DOWN) != 0) + { + putreg32(pin, base + SAM_GPIO_PDERS_OFFSET); + } + else + { + putreg32(pin, base + SAM_GPIO_PDERC_OFFSET); + } + + /* Check if glitch filtering should be enabled */ + + if ((cfgset & GPIO_GLITCH_FILTER) != 0) + { + putreg32(pin, base + SAM_GPIO_GFERS_OFFSET); + } + else + { + putreg32(pin, base + SAM_GPIO_GFERC_OFFSET); + } + + /* Check if the input Schmitt trigger should be enabled */ + + if ((cfgset & GPIO_SCHMITT_TRIGGER) != 0) + { + putreg32(pin, base + SAM_GPIO_STERS_OFFSET); + } + else + { + putreg32(pin, base + SAM_GPIO_STERC_OFFSET); + } + + return OK; +} + +/**************************************************************************** + * Name: sam_configinterrupt + * + * Description: + * Configure a GPIO input pin based on bit-encoded description of the pin. + * + ****************************************************************************/ + +static inline int sam_configinterrupt(uintptr_t base, uint32_t pin, + gpio_pinset_t cfgset) +{ + int ret; + + /* Just configure the pin as an input, then set the interrupt configuration. + * Here we exploit the fact that sam_configinput() enabled both rising and + * falling edges. + */ + + ret = sam_configinput(base, pin, cfgset) + if (ret = OK) + { + /* Disable rising and falling edge interrupts as requested + * {IMR1, IMR0} Interrupt Mode + * + * 00 Pin Change <-- We already have this + * 01 Rising Edge <-- GPIO_INT_RISING + * 10 Falling Edge <-- GPIO_INT_FALLING + * 11 Reserved + */ + + gpio_pinset_t edges = cfgset & GPIO_INT_MASK; + + if (eges = GPIO_INT_RISING) + { + /* Rising only.. disable interrrupts on the falling edge */ + + putreg32(pin, base + SAM_GPIO_IMR0S_OFFSET); + } + else if (edges = GPIO_INT_FALLING) + { + /* Falling only.. disable interrrupts on the rising edge */ + + putreg32(pin, base + SAM_GPIO_IMR1S_OFFSET); + } + } + + return ret; +} + +/**************************************************************************** + * Name: sam_configoutput + * + * Description: + * Configure a GPIO output pin based on bit-encoded description of the pin. + * + * Assumption: + * sam_configinput has been called to put the pin into the default input + * state: + * + * GPER -> GPIO + * PMD0-2 -> zeroed + * ODER -> disabled + * PUER+PDER -> No pull up- or down. + * IER -> Interrupt disabled + * IMR0-1 -> zeroed + * Glitch filter -> disabled + * Output drive -> lowest + * Slew control -> disabled + * Schmitt trigger -> disabled + * Peripheral events -> disabled + * + ****************************************************************************/ + +static inline int sam_configoutput(uintptr_t base, uint32_t pin, + gpio_pinset_t cfgset) +{ + /* Set the output drive strength + * + * {ODCR1, ODCR0} Output drive strength + * + * 00 Lowest drive strength + * 01 ... + * 10 ... + * 11 Highest drive strength + */ + + switch (cfgset & GPIO_DRIVE_MASK) + { + default: + case GPIO_DRIVE_LOW: /* OCDR1=0 OCDR0=0 */ + break; /* This is the current setting */ + + case GPIO_DRIVE_MEDLOW: /* OCDR1=0 OCDR0=1 */ + putreg32(pin, base + SAM_GPIO_ODCR0S_OFFSET); + break; + + case GPIO_DRIVE_MEDHIGH: /* OCDR1=1 OCDR0=0 */ + putreg32(pin, base + SAM_GPIO_ODCR1S_OFFSET); + break; + + case GPIO_DRIVE_HIGH: /* OCDR1=1 OCDR0=1 */ + putreg32(pin, base + SAM_GPIO_ODCR0S_OFFSET); + putreg32(pin, base + SAM_GPIO_ODCR1S_OFFSET); + break; + } + + /* Set the output slew control is requested */ + + if ((cfgset & GPIO_SLEW) != 0) + { + putreg32(pin, base + SAM_GPIO_OSRR0S_OFFSET); + } + + /* Enable the output driver */ + + putreg32(pin, base + SAM_GPIO_ODERS_OFFSET); + + /* And set the initial value of the output */ + + sam_gpiowrite(cfgset, ((cfgset & GPIO_OUTPUT_SET) != 0)); + return OK; +} + +/**************************************************************************** + * Name: sam_configperiph + * + * Description: + * Configure a GPIO pin driven by a peripheral based on bit-encoded + * description of the pin. + * + * Assumption: + * sam_configinput has been called to put the pin into the default input + * state: + * + * GPER -> GPIO + * PMD0-2 -> zeroed + * ODER -> disabled + * PUER+PDER -> No pull up- or down. + * IER -> Interrupt disabled + * IMR0-1 -> zeroed + * Glitch filter -> disabled + * Output drive -> lowest + * Slew control -> disabled + * Schmitt trigger -> disabled + * Peripheral events -> disabled + * + ****************************************************************************/ + +static inline int sam_configperiph(uintptr_t base, uint32_t pin, + gpio_pinset_t cfgset) +{ + * Peripheral: MM.. FFFE .... IIG. .PPB BBBB + + gpio_pinset_t edges; + + /* Select the peripheral function. + * + * {PMR2, PMR1, PMR0} selects peripheral function: + * + * 000 A 100 E + * 001 B 101 F + * 010 C 110 G + * 011 D 111 H + */ + + switch (cfgset & GPIO_FUNC_MASK) + { + default: + case _GPIO_FUNCA: /* Function A 000 */ + break; /* We already have this configuration */ + + case _GPIO_FUNCD: /* Function D 011 */ + putreg32(pin, base + SAM_GPIO_PMR1S_OFFSET); + break; + case _GPIO_FUNCB: /* Function B 001 */ + putreg32(pin, base + SAM_GPIO_PMR0S_OFFSET); + break; + + case _GPIO_FUNCG: /* Function G 110 */ + putreg32(pin, base + SAM_GPIO_PMR2S_OFFSET); + case _GPIO_FUNCC: /* Function C 010 */ + putreg32(pin, base + SAM_GPIO_PMR1S_OFFSET); + break; + + case _GPIO_FUNCE: /* Function E 100 */ + putreg32(pin, base + SAM_GPIO_PMR2S_OFFSET); + break; + case _GPIO_FUNCF: /* Function F 101 */ + putreg32(pin, base + SAM_GPIO_PMR0S_OFFSET); + break; + + case _GPIO_FUNCH: /* Function H 111 */ + putreg32(pin, base + SAM_GPIO_PMR0S_OFFSET); + putreg32(pin, base + SAM_GPIO_PMR1S_OFFSET); + putreg32(pin, base + SAM_GPIO_PMR2S_OFFSET); + break; + } + + /* Check if glitch filtering should be enabled */ + + if ((cfgset & GPIO_GLITCH_FILTER) != 0) + { + putreg32(pin, base + SAM_GPIO_GFERS_OFFSET); + } + + /* Disable rising and falling edge events as requested (of course, + * these do nothing unless events are also enabled. + * + * {IMR1, IMR0} Interrupt Mode + * + * 00 Pin Change <-- We already have this + * 01 Rising Edge <-- GPIO_INT_RISING + * 10 Falling Edge <-- GPIO_INT_FALLING + * 11 Reserved + */ + + edges = cfgset & GPIO_INT_MASK; + if (eges = GPIO_INT_RISING) + { + /* Rising only.. disable interrrupts on the falling edge */ + + putreg32(pin, base + SAM_GPIO_IMR0S_OFFSET); + } + else if (edges = GPIO_INT_FALLING) + { + /* Falling only.. disable interrrupts on the rising edge */ + + putreg32(pin, base + SAM_GPIO_IMR1S_OFFSET); + } + + /* REVISIT: Should event generation be enabled now? I am assuming so */ + + if (eges = GPIO_PERIPH_EVENTS) + { + /* Rising only.. disable interrrupts on the falling edge */ + + putreg32(pin, base + SAM_GPIO_EVERS_OFFSET); + } + + /* Finally, drive the pen from the peripheral */ + + putreg32(pin, base + SAM_GPIO_GPERC_OFFSET); + return OK; +} + +/**************************************************************************** + * Global Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: sam_configgpio + * + * Description: + * Configure a GPIO pin based on bit-encoded description of the pin. + * + ****************************************************************************/ + +int sam_configgpio(gpio_pinset_t cfgset) +{ + gpio_pinset_t inputset; + uintptr_t base = sam_gpiobase(cfgset); + uint32_t pin = sam_gpiopin(cfgset); + int ret; + + /* Put the GPIO in a known state. A generic GPIO input pin. */ + + inputset = GPIO_INPUT | (cfgset & (GPIO_PORT_MASK | GPIO_PIN_MASK)); + ret = sam_configinput(base, pin, inputset); + if (ret == OK) + { + /* Then put the GPIO into the requested state */ + + switch (cfgset & GPIO_MODE_MASK) + { + case GPIO_INPUT: + ret = sam_configinput(base, pin, cfgset); + break; + + case GPIO_OUTPUT: + ret = sam_configoutput(base, pin, cfgset); + break; + + case GPIO_PERIPHERAL: + ret = sam_configperiph(base, pin, cfgset); + break; + + case GPIO_INTERRUPT: + ret = sam_configinterrupt(base, pin, cfgset); + break; + + default: + ret = -EINVAL; + break; + } + } + + return ret; +} + +/**************************************************************************** + * Name: sam_gpiowrite + * + * Description: + * Write one or zero to the selected GPIO pin + * + ****************************************************************************/ + +void sam_gpiowrite(gpio_pinset_t pinset, bool value) +{ + uintptr_t base = sam_gpiobase(pinset); + uint32_t pin = sam_gpiopin(pinset); + + if (value) + { + putreg32(pin, base + SAM_GPIO_OVRS_OFFSET); + } + else + { + putreg32(pin, base + SAM_GPIO_OVRC_OFFSET); + } +} + +/**************************************************************************** + * Name: sam_gpioread + * + * Description: + * Read one or zero from the selected GPIO pin + * + ****************************************************************************/ + +bool sam_gpioread(gpio_pinset_t pinset) +{ + uintptr_t base = sam_gpiobase(pinset); + uint32_t pin = sam_gpiopin(pinset); + + return (getreg32(base + SAM_GPIO_PVR_OFFSET) & pin) != 0; +} + +/************************************************************************************ + * Function: sam_dumpgpio + * + * Description: + * Dump all GPIO registers associated with the base address of the provided pinset. + * + ************************************************************************************/ + +#ifdef CONFIG_DEBUG_GPIO +int sam_dumpgpio(uint32_t pinset, const char *msg) +{ + irqstate_t flags; + uintptr_t base; + unsigned int pin; + unsigned int port; + + /* Get the base address associated with the PIO port */ + + pin = sam_gpiopin(pinset); + port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + base = SAM_GPION_BASE(port); + + /* The following requires exclusive access to the GPIO registers */ + + flags = irqsave(); + lldbg("GPIO%c pinset: %08x base: %08x -- %s\n", + g_portchar[port], pinset, base, msg); + lldbg(" GPER: %08x PMR0: %08x PMR1: %08x PMR2: %08x\n", + getreg32(base + SAM_GPIO_GPER_OFFSET), getreg32(base + SAM_GPIO_PMR0_OFFSET), + getreg32(base + SAM_GPIO_PMR1_OFFSET), getreg32(base + SAM_GPIO_PMR2_OFFSET)); + lldbg(" ODER: %08x OVR: %08x PVR: %08x PUER: %08x\n", + getreg32(base + SAM_GPIO_ODER_OFFSET), getreg32(base + SAM_GPIO_OVR_OFFSET), + getreg32(base + SAM_GPIO_PVR_OFFSET), getreg32(base + SAM_GPIO_PUER_OFFSET)); + lldbg(" PDER: %08x IER: %08x IMR0: %08x IMR1: %08x\n", + getreg32(base + SAM_GPIO_PDER_OFFSET), getreg32(base + SAM_GPIO_IER_OFFSET), + getreg32(base + SAM_GPIO_IMR0_OFFSET), getreg32(base + SAM_GPIO_IMR1_OFFSET)); + lldbg(" GFER: %08x IFR: %08x ODCR0: %08x ODCR1: %08x\n", + getreg32(base + SAM_GPIO_GFER_OFFSET), getreg32(base + SAM_GPIO_IFR_OFFSET), + getreg32(base + SAM_GPIO_ODCR0_OFFSET), getreg32(base + SAM_GPIO_ODCR1_OFFSET)); + lldbg(" OSRR0: %08x EVER: %08x PARAM: %08x VERS: %08x\n", + getreg32(base + SAM_GPIO_OSRR0_OFFSET), getreg32(base + SAM_GPIO_EVER_OFFSET), + getreg32(base + SAM_GPIO_PARAMETER_OFFSET), getreg32(base + SAM_GPIO_VERSION_OFFSET)); + irqrestore(flags); + return OK; +} +#endif + diff --git a/nuttx/arch/arm/src/sam34/sam4l_gpio.h b/nuttx/arch/arm/src/sam34/sam4l_gpio.h index 2a65ac134..314d28ab1 100644 --- a/nuttx/arch/arm/src/sam34/sam4l_gpio.h +++ b/nuttx/arch/arm/src/sam34/sam4l_gpio.h @@ -137,14 +137,14 @@ * Peripheral: MM.. FFF. .... .... .... .... */ -# define GPIO_FUNCA (GPIO_PERIPHERAL | _GPIO_FUNCA) /* Function A */ -# define GPIO_FUNCB (GPIO_PERIPHERAL | _GPIO_FUNCB) /* Function B */ -# define GPIO_FUNCC (GPIO_PERIPHERAL | _GPIO_FUNCC) /* Function C */ -# define GPIO_FUNCD (GPIO_PERIPHERAL | _GPIO_FUNCD) /* Function D */ -# define GPIO_FUNCE (GPIO_PERIPHERAL | _GPIO_FUNCE) /* Function E */ -# define GPIO_FUNCF (GPIO_PERIPHERAL | _GPIO_FUNCF) /* Function F */ -# define GPIO_FUNCG (GPIO_PERIPHERAL | _GPIO_FUNCG) /* Function G */ -# define GPIO_FUNCH (GPIO_PERIPHERAL | _GPIO_FUNCH) /* Function H */ +#define GPIO_FUNCA (GPIO_PERIPHERAL | _GPIO_FUNCA) /* Function A */ +#define GPIO_FUNCB (GPIO_PERIPHERAL | _GPIO_FUNCB) /* Function B */ +#define GPIO_FUNCC (GPIO_PERIPHERAL | _GPIO_FUNCC) /* Function C */ +#define GPIO_FUNCD (GPIO_PERIPHERAL | _GPIO_FUNCD) /* Function D */ +#define GPIO_FUNCE (GPIO_PERIPHERAL | _GPIO_FUNCE) /* Function E */ +#define GPIO_FUNCF (GPIO_PERIPHERAL | _GPIO_FUNCF) /* Function F */ +#define GPIO_FUNCG (GPIO_PERIPHERAL | _GPIO_FUNCG) /* Function G */ +#define GPIO_FUNCH (GPIO_PERIPHERAL | _GPIO_FUNCH) /* Function H */ /* Peripheral event control * @@ -158,7 +158,7 @@ * Peripheral: .... ...E .... .... .... .... */ -#define GPIO_SCHMITT_TRIGGER (1 << 16) /* Bit 16: Enable peripheral events */ +#define GPIO_PERIPH_EVENTS (1 << 16) /* Bit 16: Enable peripheral events */ /* Output drive control * @@ -226,6 +226,12 @@ # define GPIO_INT_RISING (1 << GPIO_INT_SHIFT) /* Rising edge */ # define GPIO_INT_FALLING (2 << GPIO_INT_SHIFT) /* Falling edge */ +/* These combinations control events. These help to clean up pin definitions. */ + +#define GPIO_EVENT_CHANGE (GPIO_PERIPH_EVENTS | GPIO_INT_CHANGE) /* Pin change */ +#define GPIO_EVENT_RISING (GPIO_PERIPH_EVENTS | GPIO_INT_RISING) /* Rising edge */ +#define GPIO_EVENT_FALLING (GPIO_PERIPH_EVENTS | GPIO_INT_FALLING) /* Falling edge */ + /* Enable input/periphal glitch filter * * MODE BITFIELDS |