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authorGregory Nutt <gnutt@nuttx.org>2014-06-21 14:25:47 -0600
committerGregory Nutt <gnutt@nuttx.org>2014-06-21 14:25:47 -0600
commitae9cd96e4302ce45e0169ff6ee48f7c149412478 (patch)
tree45c12b742907068ab3f81606ce657981aa2b3ef6
parentf9b51c52593bff81f96595bbef477ac6032578d3 (diff)
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SAMA5D4: Add missing mappings for the VDEC and L2CC memory regions
-rw-r--r--nuttx/arch/arm/src/sama5/chip/sam_matrix.h1
-rw-r--r--nuttx/arch/arm/src/sama5/chip/sama5d4x_memorymap.h4
-rw-r--r--nuttx/arch/arm/src/sama5/sam_boot.c18
-rw-r--r--nuttx/arch/arm/src/sama5/sam_irq.c2
4 files changed, 23 insertions, 2 deletions
diff --git a/nuttx/arch/arm/src/sama5/chip/sam_matrix.h b/nuttx/arch/arm/src/sama5/chip/sam_matrix.h
index dd4c8b6e8..b84285580 100644
--- a/nuttx/arch/arm/src/sama5/chip/sam_matrix.h
+++ b/nuttx/arch/arm/src/sama5/chip/sam_matrix.h
@@ -56,6 +56,7 @@
/* These are bits maps of PIDs in the H64MX SPSELR registers. These are used by
* application code to quickly determine if a given PID is served by H32MX or H64MX
* which, in turn, is needed to know if the peripheral secured in SPSELR).
+ * Reference: "In Matrix" column of "Table 9-1. Peripheral identifiers."
*
* NOTE that these hard-code bit values must match the PID assignments in
* arch/arm/include/sama5/sama5*_irq.h.
diff --git a/nuttx/arch/arm/src/sama5/chip/sama5d4x_memorymap.h b/nuttx/arch/arm/src/sama5/chip/sama5d4x_memorymap.h
index 927c86aea..2643567f8 100644
--- a/nuttx/arch/arm/src/sama5/chip/sama5d4x_memorymap.h
+++ b/nuttx/arch/arm/src/sama5/chip/sama5d4x_memorymap.h
@@ -254,12 +254,14 @@
#define SAM_BOOTMEM_MMUFLAGS MMU_ROMFLAGS
#define SAM_ROM_MMUFLAGS MMU_ROMFLAGS
#define SAM_ISRAM_MMUFLAGS MMU_MEMFLAGS
-#define SAM_SMD_MMUFLAGS MMU_MEMFLAGS
+#define SAM_VDEC_MMUFLAGS MMU_IOFLAGS
#define SAM_UDPHSRAM_MMUFLAGS MMU_IOFLAGS
#define SAM_UHPOHCI_MMUFLAGS MMU_IOFLAGS
#define SAM_UHPEHCI_MMUFLAGS MMU_IOFLAGS
#define SAM_AXIMX_MMUFLAGS MMU_IOFLAGS
#define SAM_DAP_MMUFLAGS MMU_IOFLAGS
+#define SAM_SMD_MMUFLAGS MMU_MEMFLAGS
+#define SAM_L2CC_MMUFLAGS MMU_IOFLAGS
/* If the NFC is not being used, the NFC SRAM can be used as general purpose
* SRAM (cached). If the NFC is used, then the NFC SRAM should be treated
diff --git a/nuttx/arch/arm/src/sama5/sam_boot.c b/nuttx/arch/arm/src/sama5/sam_boot.c
index 5dfa4c861..1b86f2dcf 100644
--- a/nuttx/arch/arm/src/sama5/sam_boot.c
+++ b/nuttx/arch/arm/src/sama5/sam_boot.c
@@ -188,11 +188,21 @@ static const struct section_mapping_s section_mapping[] =
{ SAM_NFCSRAM_PSECTION, SAM_NFCSRAM_VSECTION,
SAM_NFCSRAM_MMUFLAGS, SAM_NFCSRAM_NSECTIONS
},
+
#ifndef CONFIG_PAGING /* Internal SRAM is already fully mapped */
{ SAM_ISRAM_PSECTION, SAM_ISRAM_VSECTION,
SAM_ISRAM_MMUFLAGS, SAM_ISRAM_NSECTIONS
},
#endif
+
+#ifdef SAM_VDEC_PSECTION
+ /* If the memory map supports a video decoder (VDEC), then map it */
+
+ { SAM_VDEC_PSECTION, SAM_VDEC_VSECTION,
+ SAM_VDEC_MMUFLAGS, SAM_VDEC_NSECTIONS
+ },
+#endif
+
{ SAM_SMD_PSECTION, SAM_SMD_VSECTION,
SAM_SMD_MMUFLAGS, SAM_SMD_NSECTIONS
},
@@ -212,6 +222,14 @@ static const struct section_mapping_s section_mapping[] =
SAM_DAP_MMUFLAGS, SAM_DAP_NSECTIONS
},
+#ifdef SAM_L2CC_PSECTION
+ /* If the memory map supports an L2 cache controller (L2CC), then map it */
+
+ { SAM_L2CC_PSECTION, SAM_L2CC_VSECTION,
+ SAM_L2CC_MMUFLAGS, SAM_L2CC_NSECTIONS
+ },
+#endif
+
/* SAMA5 CS0 External Memories */
#ifdef CONFIG_SAMA5_EBICS0
diff --git a/nuttx/arch/arm/src/sama5/sam_irq.c b/nuttx/arch/arm/src/sama5/sam_irq.c
index d36220096..5a852fd89 100644
--- a/nuttx/arch/arm/src/sama5/sam_irq.c
+++ b/nuttx/arch/arm/src/sama5/sam_irq.c
@@ -350,7 +350,7 @@ static void sam_aic_initialize(uintptr_t base)
* EOICR register.
*/
- for (i = 0; i < 8 ; i++)
+ for (i = 0; i < 8; i++)
{
putreg32(AIC_EOICR_ENDIT, base + SAM_AIC_EOICR_OFFSET);
}