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| author | Gregory Nutt <gnutt@nuttx.org> | 2013-11-28 08:13:59 -0600 |
|---|---|---|
| committer | Gregory Nutt <gnutt@nuttx.org> | 2013-11-28 08:13:59 -0600 |
| commit | f198c423c88a3fec85e8244daa1b43c03cb2cc13 (patch) | |
| tree | 972c2a63f37d85886416bb46bd52f6b6bbbb7020 | |
| parent | 382a7012f3613df64b49a018dd8b4644745d6b01 (diff) | |
| download | nuttx-f198c423c88a3fec85e8244daa1b43c03cb2cc13.tar.gz nuttx-f198c423c88a3fec85e8244daa1b43c03cb2cc13.tar.bz2 nuttx-f198c423c88a3fec85e8244daa1b43c03cb2cc13.zip | |
STM32 F4: Add support for GPIOK and GPIOJ. From Ken Pettit
| -rw-r--r-- | nuttx/ChangeLog | 2 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/stm32/chip/stm32f40xxx_gpio.h | 26 |
2 files changed, 28 insertions, 0 deletions
diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index 09e62188d..e89e0dd56 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -6117,3 +6117,5 @@ reporting (that would only be seen if both partition support and multi-root directory support are enabled at the same time). From Ken Pettit (2013-11-28). + * arch/arm/src/stm32/chip/stm32f40xxx_gpio.h: Add support for GPIOK and + GPIOJ. From Ken Pettit (2013-11-28). diff --git a/nuttx/arch/arm/src/stm32/chip/stm32f40xxx_gpio.h b/nuttx/arch/arm/src/stm32/chip/stm32f40xxx_gpio.h index 3d06fc53a..7d4b33b66 100644 --- a/nuttx/arch/arm/src/stm32/chip/stm32f40xxx_gpio.h +++ b/nuttx/arch/arm/src/stm32/chip/stm32f40xxx_gpio.h @@ -174,6 +174,32 @@ # define STM32_GPIOI_AFRH (STM32_GPIOI_BASE+STM32_GPIO_AFRH_OFFSET) #endif +#if STM32_NGPIO_PORTS > 9 +# define STM32_GPIOJ_MODER (STM32_GPIOJ_BASE+STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOJ_OTYPER (STM32_GPIOJ_BASE+STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOJ_OSPEED (STM32_GPIOJ_BASE+STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOJ_PUPDR (STM32_GPIOJ_BASE+STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOJ_IDR (STM32_GPIOJ_BASE+STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOJ_ODR (STM32_GPIOJ_BASE+STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOJ_BSRR (STM32_GPIOJ_BASE+STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOJ_LCKR (STM32_GPIOJ_BASE+STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOJ_AFRL (STM32_GPIOJ_BASE+STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOJ_AFRH (STM32_GPIOJ_BASE+STM32_GPIO_AFRH_OFFSET) +#endif + +#if STM32_NGPIO_PORTS > 10 +# define STM32_GPIOK_MODER (STM32_GPIOK_BASE+STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOK_OTYPER (STM32_GPIOK_BASE+STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOK_OSPEED (STM32_GPIOK_BASE+STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOK_PUPDR (STM32_GPIOK_BASE+STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOK_IDR (STM32_GPIOK_BASE+STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOK_ODR (STM32_GPIOK_BASE+STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOK_BSRR (STM32_GPIOK_BASE+STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOK_LCKR (STM32_GPIOK_BASE+STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOK_AFRL (STM32_GPIOK_BASE+STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOK_AFRH (STM32_GPIOK_BASE+STM32_GPIO_AFRH_OFFSET) +#endif + /* Register Bitfield Definitions ****************************************************/ /* GPIO port mode register */ |