More SAMA5 DMAC driver fixes. Still does not work.

5 files changed, 67 insertions, 27 deletions

diff --git a/nuttx/arch/arm/src/sam34/sam3u_dmac.c b/nuttx/arch/arm/src/sam34/sam3u_dmac.c
index 69a0d256e..01585e91b 100644
--- a/nuttx/arch/arm/src/sam34/sam3u_dmac.c
+++ b/nuttx/arch/arm/src/sam34/sam3u_dmac.c
@@ -412,7 +412,7 @@ sam_txctrlabits(struct sam_dma_s *dmach)
  ****************************************************************************/
 
 static inline uint32_t sam_txctrla(struct sam_dma_s *dmach,
-                                   uint32_t dmasize, uint32_t txctrlabits)
+                                   uint32_t dmasize, uint32_t ctrla)
 {
   /* Set the buffer transfer size field.  This is the number of transfers to
    * be performed, that is, the number of source width transfers to perform.
@@ -428,7 +428,8 @@ static inline uint32_t sam_txctrla(struct sam_dma_s *dmach,
     }
 
   DEBUGASSERT(dmasize <= DMACHAN_CTRLA_BTSIZE_MAX);
-  return (txctrlabits & ~DMACHAN_CTRLA_BTSIZE_MASK) | (dmasize << DMACHAN_CTRLA_BTSIZE_SHIFT);
+  return (ctrla & ~DMACHAN_CTRLA_BTSIZE_MASK) |
+         (dmasize << DMACHAN_CTRLA_BTSIZE_SHIFT);
 }
 
 /****************************************************************************
@@ -503,7 +504,7 @@ static inline uint32_t sam_rxctrlabits(struct sam_dma_s *dmach)
  ****************************************************************************/
 
 static inline uint32_t sam_rxctrla(struct sam_dma_s *dmach,
-                                   uint32_t dmasize, uint32_t txctrlabits)
+                                   uint32_t dmasize, uint32_t ctrla)
 {
   /* Set the buffer transfer size field.  This is the number of transfers to
    * be performed, that is, the number of source width transfers to perform.
@@ -519,7 +520,8 @@ static inline uint32_t sam_rxctrla(struct sam_dma_s *dmach,
     }
 
   DEBUGASSERT(dmasize <= DMACHAN_CTRLA_BTSIZE_MAX);
-  return (txctrlabits & ~DMACHAN_CTRLA_BTSIZE_MASK) | (dmasize << DMACHAN_CTRLA_BTSIZE_SHIFT);
+  return (ctrla & ~DMACHAN_CTRLA_BTSIZE_MASK) |
+         (dmasize << DMACHAN_CTRLA_BTSIZE_SHIFT);
 }
 
 /****************************************************************************
@@ -1130,7 +1132,7 @@ static int sam_dmainterrupt(int irq, void *context)
                * interrupt as part of a multiple buffer transfer.
                */
 
-              else /* f ((regval & DMAC_EBC_BTC(chndx)) != 0) */
+              else /* if ((regval & DMAC_EBC_BTC(chndx)) != 0) */
                 {
                   /* Write the KEEPON field to clear the STALL states */
 
diff --git a/nuttx/arch/arm/src/sama5/chip/sam_dmac.h b/nuttx/arch/arm/src/sama5/chip/sam_dmac.h
index 68b3b592d..fbcd6b651 100755
--- a/nuttx/arch/arm/src/sama5/chip/sam_dmac.h
+++ b/nuttx/arch/arm/src/sama5/chip/sam_dmac.h
@@ -780,7 +780,7 @@
 #define DMAC0_CH_SMD_RX               (16)       /* SMD Receive */
 
 
-/* DMA Controller 0 Channel Definitions */
+/* DMA Controller 1 Channel Definitions */
 
 #define DMAC1_CH_HSMCI1               (0)        /* HSMCI1 Receive/transmit */
 #define DMAC1_CH_HSMCI2               (1)        /* HSMCI2 Receive/transmit */
diff --git a/nuttx/arch/arm/src/sama5/sam_dmac.c b/nuttx/arch/arm/src/sama5/sam_dmac.c
index 42d91ea9f..f26bab5de 100644
--- a/nuttx/arch/arm/src/sama5/sam_dmac.c
+++ b/nuttx/arch/arm/src/sama5/sam_dmac.c
@@ -652,7 +652,7 @@ static inline uint32_t sam_txctrlabits(struct sam_dmach_s *dmach)
  ****************************************************************************/
 
 static inline uint32_t sam_txctrla(struct sam_dmach_s *dmach,
-                                   uint32_t dmasize, uint32_t txctrlabits)
+                                   uint32_t dmasize, uint32_t ctrla)
 {
   unsigned int chunksize;
 
@@ -686,7 +686,7 @@ static inline uint32_t sam_txctrla(struct sam_dmach_s *dmach,
     }
 
   DEBUGASSERT(dmasize <= DMAC_CH_CTRLA_BTSIZE_MAX);
-  return (txctrlabits & ~DMAC_CH_CTRLA_BTSIZE_MASK) |
+  return (ctrla & ~DMAC_CH_CTRLA_BTSIZE_MASK) |
          (dmasize << DMAC_CH_CTRLA_BTSIZE_SHIFT);
 }
 
@@ -753,7 +753,7 @@ static inline uint32_t sam_rxctrlabits(struct sam_dmach_s *dmach)
  ****************************************************************************/
 
 static inline uint32_t sam_rxctrla(struct sam_dmach_s *dmach,
-                                   uint32_t dmasize, uint32_t txctrlabits)
+                                   uint32_t dmasize, uint32_t ctrla)
 {
   unsigned int chunksize;
 
@@ -787,7 +787,7 @@ static inline uint32_t sam_rxctrla(struct sam_dmach_s *dmach,
     }
 
   DEBUGASSERT(dmasize <= DMAC_CH_CTRLA_BTSIZE_MAX);
-  return (txctrlabits & ~DMAC_CH_CTRLA_BTSIZE_MASK) |
+  return (ctrla & ~DMAC_CH_CTRLA_BTSIZE_MASK) |
          (dmasize << DMAC_CH_CTRLA_BTSIZE_SHIFT);
 }
 
@@ -803,6 +803,7 @@ static inline uint32_t sam_rxctrla(struct sam_dmach_s *dmach,
 static inline uint32_t sam_txctrlb(struct sam_dmach_s *dmach)
 {
   uint32_t regval;
+  unsigned int ahbif;
 
   /* Assume that we will not be using the link list and disable the source
    * and destination descriptors.  The default will be single transfer mode.
@@ -854,6 +855,11 @@ static inline uint32_t sam_txctrlb(struct sam_dmach_s *dmach)
         }
     }
 
+  /* Source ABH layer */
+
+  ahbif = (dmach->flags & DMACH_FLAG_MEMAHB_MASK) >> DMACH_FLAG_MEMAHB_SHIFT;
+  regval |= (ahbif << DMAC_CH_CTRLB_SIF_SHIFT);
+
   /* Select source address incrementing */
 
   if ((dmach->flags & DMACH_FLAG_MEMINCREMENT) == 0)
@@ -861,6 +867,11 @@ static inline uint32_t sam_txctrlb(struct sam_dmach_s *dmach)
       regval |= DMAC_CH_CTRLB_SRCINCR_FIXED;
     }
 
+  /* Destination ABH layer */
+
+  ahbif = (dmach->flags & DMACH_FLAG_PERIPHAHB_MASK) >> DMACH_FLAG_PERIPHAHB_SHIFT;
+  regval |= (ahbif << DMAC_CH_CTRLB_DIF_SHIFT);
+
   /* Select destination address incrementing */
 
   if ((dmach->flags & DMACH_FLAG_PERIPHINCREMENT) == 0)
@@ -883,6 +894,7 @@ static inline uint32_t sam_txctrlb(struct sam_dmach_s *dmach)
 static inline uint32_t sam_rxctrlb(struct sam_dmach_s *dmach)
 {
   uint32_t regval;
+  unsigned int ahbif;
 
   /* Assume that we will not be using the link list and disable the source
    * and destination descriptors.  The default will be single transfer mode.
@@ -934,6 +946,11 @@ static inline uint32_t sam_rxctrlb(struct sam_dmach_s *dmach)
         }
     }
 
+  /* Source ABH layer */
+
+  ahbif = (dmach->flags & DMACH_FLAG_PERIPHAHB_MASK) >> DMACH_FLAG_PERIPHAHB_SHIFT;
+  regval |= (ahbif << DMAC_CH_CTRLB_SIF_SHIFT);
+
   /* Select source address incrementing */
 
   if ((dmach->flags & DMACH_FLAG_PERIPHINCREMENT) == 0)
@@ -941,6 +958,11 @@ static inline uint32_t sam_rxctrlb(struct sam_dmach_s *dmach)
       regval |= DMAC_CH_CTRLB_SRCINCR_FIXED;
     }
 
+  /* Destination ABH layer */
+
+  ahbif = (dmach->flags & DMACH_FLAG_MEMAHB_MASK) >> DMACH_FLAG_MEMAHB_SHIFT;
+  regval |= (ahbif << DMAC_CH_CTRLB_DIF_SHIFT);
+
   /* Select address incrementing */
 
   if ((dmach->flags & DMACH_FLAG_MEMINCREMENT) == 0)
@@ -1033,7 +1055,10 @@ sam_allocdesc(struct sam_dmach_s *dmach, struct dma_linklist_s *prev,
 
                   prev->ctrlb &= ~DMAC_CH_CTRLB_BOTHDSCR;
 
-                  /* Link the previous tail to the new tail */
+                  /* Link the previous tail to the new tail.
+                   * REVISIT:  This assumes that the next description is fetched
+                   * via AHB IF0.
+                   */
 
                   prev->dscr = (uint32_t)desc;
                 }
@@ -1413,7 +1438,7 @@ static int sam_dmac_interrupt(struct sam_dmac_s *dmac)
                * interrupt as part of a multiple buffer transfer.
                */
 
-              else /* f ((regval & DMAC_EBC_BTC(chndx)) != 0) */
+              else /* if ((regval & DMAC_EBC_BTC(chndx)) != 0) */
                 {
                   /* Write the KEEPON field to clear the STALL states */
 
diff --git a/nuttx/arch/arm/src/sama5/sam_dmac.h b/nuttx/arch/arm/src/sama5/sam_dmac.h
index db63f56bd..138f41f64 100644
--- a/nuttx/arch/arm/src/sama5/sam_dmac.h
+++ b/nuttx/arch/arm/src/sama5/sam_dmac.h
@@ -82,34 +82,44 @@
 #define DMACH_FLAG_PERIPHPID_MASK             (63 << DMACH_FLAG_PERIPHPID_SHIFT)
 #define DMACH_FLAG_PERIPHH2SEL                (1 << 8)  /* Bits 8: HW handshaking */
 #define DMACH_FLAG_PERIPHISPERIPH             (1 << 9)  /* Bits 9: 0=memory; 1=peripheral */
-#define DMACH_FLAG_PERIPHWIDTH_SHIFT          (10)      /* Bits 10-11: Peripheral width */
+#define DMACH_FLAG_PERIPHAHB_SHIFT            (10)      /* Bits 10-11: Peripheral ABH layer number */
+#define DMACH_FLAG_PERIPHAHB_MASK             (3 << DMACH_FLAG_PERIPHAHB_SHIFT)
+#  define DMACH_FLAG_PERIPHAHB_AHB_IF0        (0 << DMACH_FLAG_PERIPHAHB_SHIFT) /* AHB-Lite Interface 0 */
+#  define DMACH_FLAG_PERIPHAHB_AHB_IF1        (1 << DMACH_FLAG_PERIPHAHB_SHIFT) /* AHB-Lite Interface 1 */
+#  define DMACH_FLAG_PERIPHAHB_AHB_IF2        (2 << DMACH_FLAG_PERIPHAHB_SHIFT) /* AHB-Lite Interface 2 */
+#define DMACH_FLAG_PERIPHWIDTH_SHIFT          (12)      /* Bits 12-13: Peripheral width */
 #define DMACH_FLAG_PERIPHWIDTH_MASK           (3 << DMACH_FLAG_PERIPHWIDTH_SHIFT)
 #  define DMACH_FLAG_PERIPHWIDTH_8BITS        (0 << DMACH_FLAG_PERIPHWIDTH_SHIFT) /* 8 bits */
 #  define DMACH_FLAG_PERIPHWIDTH_16BITS       (1 << DMACH_FLAG_PERIPHWIDTH_SHIFT) /* 16 bits */
 #  define DMACH_FLAG_PERIPHWIDTH_32BITS       (2 << DMACH_FLAG_PERIPHWIDTH_SHIFT) /* 32 bits */
 #  define DMACH_FLAG_PERIPHWIDTH_64BITS       (3 << DMACH_FLAG_PERIPHWIDTH_SHIFT) /* 64 bits */
-#define DMACH_FLAG_PERIPHINCREMENT            (1 << 12) /* Bit 12: Autoincrement peripheral address */
-#define DMACH_FLAG_PERIPHCHUNKSIZE_SHIFT      (13)      /* Bits 13-14: Peripheral chunk size */
+#define DMACH_FLAG_PERIPHINCREMENT            (1 << 14) /* Bit 14: Autoincrement peripheral address */
+#define DMACH_FLAG_PERIPHCHUNKSIZE_SHIFT      (15)      /* Bits 15-16: Peripheral chunk size */
 #define DMACH_FLAG_PERIPHCHUNKSIZE_MASK       (3 << DMACH_FLAG_PERIPHCHUNKSIZE_SHIFT)
-#  define DMACH_FLAG_PERIPHCHUNKSIZE_1        (0 << DMACH_FLAG_PERIPHCHUNKSIZE_SHIFT) /* Peripheral chunksize = 1 */
-#  define DMACH_FLAG_PERIPHCHUNKSIZE_4        (1 << DMACH_FLAG_PERIPHCHUNKSIZE_SHIFT) /* Peripheral chunksize = 4 */
-#  define DMACH_FLAG_PERIPHCHUNKSIZE_8        (3 << DMACH_FLAG_PERIPHCHUNKSIZE_SHIFT) /* Peripheral chunksize = 8 */
-#  define DMACH_FLAG_PERIPHCHUNKSIZE_16       (4 << DMACH_FLAG_PERIPHCHUNKSIZE_SHIFT) /* Peripheral chunksize = 16 */
+#  define DMACH_FLAG_PERIPHCHUNKSIZE_1        (0 << DMACH_FLAG_PERIPHCHUNKSIZE_SHIFT) /* Peripheral chunksize=1 */
+#  define DMACH_FLAG_PERIPHCHUNKSIZE_4        (1 << DMACH_FLAG_PERIPHCHUNKSIZE_SHIFT) /* Peripheral chunksize=4 */
+#  define DMACH_FLAG_PERIPHCHUNKSIZE_8        (3 << DMACH_FLAG_PERIPHCHUNKSIZE_SHIFT) /* Peripheral chunksize=8 */
+#  define DMACH_FLAG_PERIPHCHUNKSIZE_16       (4 << DMACH_FLAG_PERIPHCHUNKSIZE_SHIFT) /* Peripheral chunksize=16 */
 
 /* Memory endpoint characteristics */
 
-#define DMACH_FLAG_MEMPID_SHIFT               (15)      /* Bits 15-20: Memory PID */
+#define DMACH_FLAG_MEMPID_SHIFT               (17)      /* Bits 17-22: Memory PID */
 #define DMACH_FLAG_MEMPID_MASK                (63 << DMACH_FLAG_PERIPHPID_SHIFT)
-#define DMACH_FLAG_MEMH2SEL                   (1 << 21) /* Bits 21: HW handshaking */
-#define DMACH_FLAG_MEMISPERIPH                (1 << 22) /* Bits 22: 0=memory; 1=peripheral */
-#define DMACH_FLAG_MEMWIDTH_SHIFT             (23)      /* Bits 23-24: Memory width */
+#define DMACH_FLAG_MEMH2SEL                   (1 << 23) /* Bits 23: HW handshaking */
+#define DMACH_FLAG_MEMISPERIPH                (1 << 24) /* Bits 24: 0=memory; 1=peripheral */
+#define DMACH_FLAG_MEMAHB_SHIFT               (25)      /* Bits 25-26: Peripheral ABH layer number */
+#define DMACH_FLAG_MEMAHB_MASK                (3 << DMACH_FLAG_MEMAHB_SHIFT)
+#  define DMACH_FLAG_MEMAHB_AHB_IF0           (0 << DMACH_FLAG_MEMAHB_SHIFT) /* AHB-Lite Interface 0 */
+#  define DMACH_FLAG_MEMAHB_AHB_IF1           (1 << DMACH_FLAG_MEMAHB_SHIFT) /* AHB-Lite Interface 1 */
+#  define DMACH_FLAG_MEMAHB_AHB_IF2           (2 << DMACH_FLAG_MEMAHB_SHIFT) /* AHB-Lite Interface 2 */
+#define DMACH_FLAG_MEMWIDTH_SHIFT             (27)      /* Bits 27-28: Memory width */
 #define DMACH_FLAG_MEMWIDTH_MASK              (3 << DMACH_FLAG_MEMWIDTH_SHIFT)
 #  define DMACH_FLAG_MEMWIDTH_8BITS           (0 << DMACH_FLAG_MEMWIDTH_SHIFT) /* 8 bits */
 #  define DMACH_FLAG_MEMWIDTH_16BITS          (1 << DMACH_FLAG_MEMWIDTH_SHIFT) /* 16 bits */
 #  define DMACH_FLAG_MEMWIDTH_32BITS          (2 << DMACH_FLAG_MEMWIDTH_SHIFT) /* 32 bits */
 #  define DMACH_FLAG_MEMWIDTH_64BITS          (3 << DMACH_FLAG_MEMWIDTH_SHIFT) /* 64 bits */
-#define DMACH_FLAG_MEMINCREMENT               (1 << 25) /* Bit 25: Autoincrement memory address */
-#define DMACH_FLAG_MEMCHUNKSIZE_SHIFT         (26)      /* Bit 26-27: Memory chunk size */
+#define DMACH_FLAG_MEMINCREMENT               (1 << 29) /* Bit 29: Autoincrement memory address */
+#define DMACH_FLAG_MEMCHUNKSIZE_SHIFT         (30)      /* Bit 30-31: Memory chunk size */
 #define DMACH_FLAG_MEMCHUNKSIZE_MASK          (3 << DMACH_FLAG_MEMCHUNKSIZE_SHIFT)
 #  define DMACH_FLAG_MEMCHUNKSIZE_1           (0 << DMACH_FLAG_MEMCHUNKSIZE_SHIFT) /* Peripheral chunksize = 1 */
 #  define DMACH_FLAG_MEMCHUNKSIZE_4           (1 << DMACH_FLAG_MEMCHUNKSIZE_SHIFT) /* Peripheral chunksize = 4 */
diff --git a/nuttx/arch/arm/src/sama5/sam_hsmci.c b/nuttx/arch/arm/src/sama5/sam_hsmci.c
index 8cd783ca0..8ad9a1b2a 100644
--- a/nuttx/arch/arm/src/sama5/sam_hsmci.c
+++ b/nuttx/arch/arm/src/sama5/sam_hsmci.c
@@ -126,12 +126,15 @@
 
 #define HSMCI_DTIMER_DATATIMEOUT (0x000fffff)
 
-/* DMA configuration flags */
+/* DMA configuration flags
+ * REVISIT:  Is memory always on IF0?
+ */
 
 #define DMA_FLAGS(pid) \
-  (((pid) << DMACH_FLAG_PERIPHPID_SHIFT) | \
+  (((pid) << DMACH_FLAG_PERIPHPID_SHIFT) | DMACH_FLAG_PERIPHAHB_AHB_IF2 | \
    DMACH_FLAG_PERIPHH2SEL | DMACH_FLAG_PERIPHISPERIPH |  \
    DMACH_FLAG_PERIPHWIDTH_32BITS | DMACH_FLAG_PERIPHCHUNKSIZE_1 | \
+   ((0x3f) << DMACH_FLAG_MEMPID_SHIFT) | DMACH_FLAG_MEMAHB_AHB_IF0 | \
    DMACH_FLAG_MEMWIDTH_32BITS | DMACH_FLAG_MEMINCREMENT | \
    DMACH_FLAG_MEMCHUNKSIZE_4)