First cut at support for Cortex-M0

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5655 42af7a65-404d-4744-a932-0658087f49c3

2 files changed, 585 insertions, 0 deletions

diff --git a/nuttx/arch/arm/include/armv6-m/irq.h b/nuttx/arch/arm/include/armv6-m/irq.h
new file mode 100644
index 000000000..bad7883fa
--- /dev/null
+++ b/nuttx/arch/arm/include/armv6-m/irq.h
@@ -0,0 +1,342 @@
+/****************************************************************************
+ * arch/arm/include/armv6-m/irq.h
+ *
+ *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directed but, rather, only indirectly
+ * through nuttx/irq.h
+ */
+
+#ifndef __ARCH_ARM_INCLUDE_ARMV6_M_IRQ_H
+#define __ARCH_ARM_INCLUDE_ARMV6_M_IRQ_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <nuttx/irq.h>
+#ifndef __ASSEMBLY__
+#  include <nuttx/compiler.h>
+#  include <stdint.h>
+#endif
+
+#include <arch/chip/chip.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* IRQ Stack Frame Format:
+ *
+ * The following additional registers are stored by the interrupt handling
+ * logic.
+ */
+
+#define REG_R13             (0)  /* R13 = SP at time of interrupt */
+#define REG_BASEPRI         (1)  /* BASEPRI */
+#define REG_R4              (2)  /* R4 */
+#define REG_R5              (3)  /* R5 */
+#define REG_R6              (4)  /* R6 */
+#define REG_R7              (5)  /* R7 */
+#define REG_R8              (6)  /* R8 */
+#define REG_R9              (7)  /* R9 */
+#define REG_R10             (8)  /* R10 */
+#define REG_R11             (9)  /* R11 */
+#define REG_EXC_RETURN      (10) /* EXC_RETURN */
+
+/* The total number of registers saved by software */
+
+#define SW_XCPT_REGS        (11)
+#define SW_XCPT_SIZE        (4 * SW_XCPT_REGS)
+
+/* On entry into an IRQ, the hardware automatically saves the following
+ * registers on the stack in this (address) order:
+ */
+
+#define REG_R0              (SW_XCPT_REGS+0) /* R0 */
+#define REG_R1              (SW_XCPT_REGS+1) /* R1 */
+#define REG_R2              (SW_XCPT_REGS+2) /* R2 */
+#define REG_R3              (SW_XCPT_REGS+3) /* R3 */
+#define REG_R12             (SW_XCPT_REGS+4) /* R12 */
+#define REG_R14             (SW_XCPT_REGS+5) /* R14 = LR */
+#define REG_R15             (SW_XCPT_REGS+6) /* R15 = PC */
+#define REG_XPSR            (SW_XCPT_REGS+7) /* xPSR */
+
+#define HW_XCPT_REGS        (8)
+#define HW_XCPT_SIZE        (4 * HW_XCPT_REGS)
+
+#define XCPTCONTEXT_REGS    (HW_XCPT_REGS + SW_XCPT_REGS)
+#define XCPTCONTEXT_SIZE    (4 * XCPTCONTEXT_REGS)
+
+/* Alternate register names */
+
+#define REG_A1              REG_R0
+#define REG_A2              REG_R1
+#define REG_A3              REG_R2
+#define REG_A4              REG_R3
+#define REG_V1              REG_R4
+#define REG_V2              REG_R5
+#define REG_V3              REG_R6
+#define REG_V4              REG_R7
+#define REG_V5              REG_R8
+#define REG_V6              REG_R9
+#define REG_V7              REG_R10
+#define REG_SB              REG_R9
+#define REG_SL              REG_R10
+#define REG_FP              REG_R11
+#define REG_IP              REG_R12
+#define REG_SP              REG_R13
+#define REG_LR              REG_R14
+#define REG_PC              REG_R15
+
+/* The PIC register is usually R10. It can be R9 is stack checking is enabled
+ * or if the user changes it with -mpic-register on the GCC command line.
+ */
+
+#define REG_PIC             REG_R10
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/* The following structure is included in the TCB and defines the complete
+ * state of the thread.
+ */
+
+#ifndef __ASSEMBLY__
+struct xcptcontext
+{
+  /* The following function pointer is non-zero if there
+   * are pending signals to be processed.
+   */
+
+#ifndef CONFIG_DISABLE_SIGNALS
+  void *sigdeliver; /* Actual type is sig_deliver_t */
+
+  /* These are saved copies of LR, PRIMASK, and xPSR used during
+   * signal processing.
+   */
+
+  uint32_t saved_pc;
+  uint32_t saved_basepri;
+  uint32_t saved_xpsr;
+#endif
+
+  /* Register save area */
+
+  uint32_t regs[XCPTCONTEXT_REGS];
+};
+#endif
+
+/****************************************************************************
+ * Inline functions
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/* Get/set the PRIMASK register */
+
+static inline uint8_t getprimask(void) inline_function;
+static inline uint8_t getprimask(void)
+{
+  uint32_t primask;
+  __asm__ __volatile__
+    (
+     "\tmrs  %0, primask\n"
+     : "=r" (primask)
+     :
+     : "memory");
+
+  return (uint8_t)primask;
+}
+
+static inline void setprimask(uint32_t primask) inline_function;
+static inline void setprimask(uint32_t primask)
+{
+  __asm__ __volatile__
+    (
+      "\tmsr primask, %0\n"
+      :
+      : "r" (primask)
+      : "memory");
+}
+
+/* Get/set the BASEPRI register.  The BASEPRI register defines the minimum
+ * priority for exception processing. When BASEPRI is set to a nonzero
+ * value, it prevents the activation of all exceptions with the same or
+ * lower priority level as the BASEPRI value.
+ */
+
+static inline uint8_t getbasepri(void) inline_function;
+static inline uint8_t getbasepri(void)
+{
+  uint32_t basepri;
+
+  __asm__ __volatile__
+    (
+     "\tmrs  %0, basepri\n"
+     : "=r" (basepri)
+     :
+     : "memory");
+
+  return (uint8_t)basepri;
+}
+
+static inline void setbasepri(uint32_t basepri) inline_function;
+static inline void setbasepri(uint32_t basepri)
+{
+  __asm__ __volatile__
+    (
+      "\tmsr basepri, %0\n"
+      :
+      : "r" (basepri)
+      : "memory");
+}
+
+/* Disable IRQs */
+
+static inline void irqdisable(void) inline_function;
+static inline void irqdisable(void)
+{
+  setbasepri(NVIC_SYSH_DISABLE_PRIORITY);
+}
+
+/* Save the current primask state & disable IRQs */
+
+static inline irqstate_t irqsave(void) inline_function;
+static inline irqstate_t irqsave(void)
+{
+  uint8_t basepri = getbasepri();
+  setbasepri(NVIC_SYSH_DISABLE_PRIORITY);
+  return (irqstate_t)basepri;
+}
+
+/* Enable IRQs */
+
+static inline void irqenable(void) inline_function;
+static inline void irqenable(void)
+{
+  setbasepri(0);
+  __asm__ __volatile__ ("\tcpsie  i\n");
+}
+
+/* Restore saved primask state */
+
+static inline void irqrestore(irqstate_t flags) inline_function;
+static inline void irqrestore(irqstate_t flags)
+{
+  setbasepri((uint32_t)flags);
+}
+
+/* Get/set IPSR */
+
+static inline uint32_t getipsr(void) inline_function;
+static inline uint32_t getipsr(void)
+{
+  uint32_t ipsr;
+  __asm__ __volatile__
+    (
+     "\tmrs  %0, ipsr\n"
+     : "=r" (ipsr)
+     :
+     : "memory");
+
+  return ipsr;
+}
+
+static inline void setipsr(uint32_t ipsr) inline_function;
+static inline void setipsr(uint32_t ipsr)
+{
+  __asm__ __volatile__
+    (
+      "\tmsr ipsr, %0\n"
+      :
+      : "r" (ipsr)
+      : "memory");
+}
+
+/* Get/set CONTROL */
+
+static inline uint32_t getcontrol(void) inline_function;
+static inline uint32_t getcontrol(void)
+{
+  uint32_t control;
+  __asm__ __volatile__
+    (
+     "\tmrs  %0, control\n"
+     : "=r" (control)
+     :
+     : "memory");
+
+  return control;
+}
+
+static inline void setcontrol(uint32_t control) inline_function;
+static inline void setcontrol(uint32_t control)
+{
+  __asm__ __volatile__
+    (
+      "\tmsr control, %0\n"
+      :
+      : "r" (control)
+      : "memory");
+}
+
+#endif /* __ASSEMBLY__ */
+
+/****************************************************************************
+ * Public Variables
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C" {
+#else
+#define EXTERN extern
+#endif
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+#endif
+
+#endif /* __ARCH_ARM_INCLUDE_ARMV6_M_IRQ_H */
+
diff --git a/nuttx/arch/arm/include/armv6-m/syscall.h b/nuttx/arch/arm/include/armv6-m/syscall.h
new file mode 100644
index 000000000..f92dea7e8
--- /dev/null
+++ b/nuttx/arch/arm/include/armv6-m/syscall.h
@@ -0,0 +1,243 @@
+/****************************************************************************
+ * arch/arm/include/armv6-m/syscall.h
+ *
+ *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directed but, rather, only indirectly
+ * through include/syscall.h or include/sys/sycall.h
+ */
+
+#ifndef __ARCH_ARM_INCLUDE_ARMV6_M_SYSCALL_H
+#define __ARCH_ARM_INCLUDE_ARMV6_M_SYSCALL_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+#  include <stdint.h>
+#endif
+
+/****************************************************************************
+ * Pro-processor Definitions
+ ****************************************************************************/
+
+#define SYS_syscall 0x00
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Inline functions
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/* SVC call with SYS_ call number and no parameters */
+
+static inline uintptr_t sys_call0(unsigned int nbr)
+{
+  register long reg0 __asm__("r0") = (long)(nbr);
+
+  __asm__ __volatile__
+  (
+    "svc %1"
+    : "=r"(reg0)
+    : "i"(SYS_syscall), "r"(reg0)
+    : "memory"
+  );
+
+  return reg0;
+}
+
+/* SVC call with SYS_ call number and one parameter */
+
+static inline uintptr_t sys_call1(unsigned int nbr, uintptr_t parm1)
+{
+  register long reg0 __asm__("r0") = (long)(nbr);
+  register long reg1 __asm__("r1") = (long)(parm1);
+
+  __asm__ __volatile__
+  (
+    "svc %1"
+    : "=r"(reg0)
+    : "i"(SYS_syscall), "r"(reg0), "r"(reg1)
+    : "memory"
+  );
+
+  return reg0;
+}
+
+/* SVC call with SYS_ call number and two parameters */
+
+static inline uintptr_t sys_call2(unsigned int nbr, uintptr_t parm1,
+                                  uintptr_t parm2)
+{
+  register long reg0 __asm__("r0") = (long)(nbr);
+  register long reg2 __asm__("r2") = (long)(parm2);
+  register long reg1 __asm__("r1") = (long)(parm1);
+
+  __asm__ __volatile__
+  (
+    "svc %1"
+    : "=r"(reg0)
+    : "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2)
+    : "memory"
+  );
+
+  return reg0;
+}
+
+/* SVC call with SYS_ call number and three parameters */
+
+static inline uintptr_t sys_call3(unsigned int nbr, uintptr_t parm1,
+                                  uintptr_t parm2, uintptr_t parm3)
+{
+  register long reg0 __asm__("r0") = (long)(nbr);
+  register long reg3 __asm__("r3") = (long)(parm3);
+  register long reg2 __asm__("r2") = (long)(parm2);
+  register long reg1 __asm__("r1") = (long)(parm1);
+
+  __asm__ __volatile__
+  (
+    "svc %1"
+    : "=r"(reg0)
+    : "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2), "r"(reg3)
+    : "memory"
+  );
+
+  return reg0;
+}
+
+/* SVC call with SYS_ call number and four parameters */
+
+static inline uintptr_t sys_call4(unsigned int nbr, uintptr_t parm1,
+                                  uintptr_t parm2, uintptr_t parm3,
+                                  uintptr_t parm4)
+{
+  register long reg0 __asm__("r0") = (long)(nbr);
+  register long reg4 __asm__("r4") = (long)(parm4);
+  register long reg3 __asm__("r3") = (long)(parm3);
+  register long reg2 __asm__("r2") = (long)(parm2);
+  register long reg1 __asm__("r1") = (long)(parm1);
+
+  __asm__ __volatile__
+  (
+    "svc %1"
+    : "=r"(reg0)
+    : "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2),
+      "r"(reg3), "r"(reg4)
+    : "memory"
+  );
+
+  return reg0;
+}
+
+/* SVC call with SYS_ call number and five parameters */
+
+static inline uintptr_t sys_call5(unsigned int nbr, uintptr_t parm1,
+                                  uintptr_t parm2, uintptr_t parm3,
+                                  uintptr_t parm4, uintptr_t parm5)
+{
+  register long reg0 __asm__("r0") = (long)(nbr);
+  register long reg5 __asm__("r5") = (long)(parm5);
+  register long reg4 __asm__("r4") = (long)(parm4);
+  register long reg3 __asm__("r3") = (long)(parm3);
+  register long reg2 __asm__("r2") = (long)(parm2);
+  register long reg1 __asm__("r1") = (long)(parm1);
+
+  __asm__ __volatile__
+  (
+    "svc %1"
+    : "=r"(reg0)
+    : "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2),
+      "r"(reg3), "r"(reg4), "r"(reg5)
+    : "memory"
+  );
+
+  return reg0;
+}
+
+/* SVC call with SYS_ call number and six parameters */
+
+static inline uintptr_t sys_call6(unsigned int nbr, uintptr_t parm1,
+                                  uintptr_t parm2, uintptr_t parm3,
+                                  uintptr_t parm4, uintptr_t parm5,
+                                  uintptr_t parm6)
+{
+  register long reg0 __asm__("r0") = (long)(nbr);
+  register long reg6 __asm__("r6") = (long)(parm6);
+  register long reg5 __asm__("r5") = (long)(parm5);
+  register long reg4 __asm__("r4") = (long)(parm4);
+  register long reg3 __asm__("r3") = (long)(parm3);
+  register long reg2 __asm__("r2") = (long)(parm2);
+  register long reg1 __asm__("r1") = (long)(parm1);
+
+  __asm__ __volatile__
+  (
+    "svc %1"
+    : "=r"(reg0)
+    : "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2),
+      "r"(reg3), "r"(reg4), "r"(reg5), "r"(reg6)
+    : "memory"
+  );
+
+  return reg0;
+}
+
+/****************************************************************************
+ * Public Variables
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C" {
+#else
+#define EXTERN extern
+#endif
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_ARM_INCLUDE_ARMV6_M_SYSCALL_H */
+