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authorpatacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3>2013-01-22 01:25:40 +0000
committerpatacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3>2013-01-22 01:25:40 +0000
commitfefa8ee3353d5ac7ef0e925ba8dcbbb89f2c96ae (patch)
treea1914fb5c45a61232078c98064198ac8818f07b4 /nuttx/arch/arm/include/lpc43xx
parentc86261aac88dcc280ca37e532ba96435c1c54699 (diff)
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Add option to use BASEPRI instead of PRIMASK to disable interrupts in all ARMv7-M architectures
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5546 42af7a65-404d-4744-a932-0658087f49c3
Diffstat (limited to 'nuttx/arch/arm/include/lpc43xx')
-rw-r--r--nuttx/arch/arm/include/lpc43xx/chip.h31
1 files changed, 30 insertions, 1 deletions
diff --git a/nuttx/arch/arm/include/lpc43xx/chip.h b/nuttx/arch/arm/include/lpc43xx/chip.h
index 220ce38d0..7ff787e48 100644
--- a/nuttx/arch/arm/include/lpc43xx/chip.h
+++ b/nuttx/arch/arm/include/lpc43xx/chip.h
@@ -1,7 +1,7 @@
/************************************************************************************
* arch/arm/include/lpc43xx/chip.h
*
- * Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2012-2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@@ -542,6 +542,35 @@
# error "Unsupported LPC43xx chip"
#endif
+/* NVIC priority levels *************************************************************/
+/* Each priority field holds a priority value, 0-31. The lower the value, the greater
+ * the priority of the corresponding interrupt.
+ *
+ * The Cortex-M4 core supports up to 53 interrupts an 8 prgrammable interrupt
+ * priority levels; The Cortex-M0 core supports up to 32 interrupts with 4
+ * programmable interrupt priorities.
+ */
+
+#define LPC43M4_SYSH_PRIORITY_MIN 0xe0 /* All bits[7:5] set is minimum priority */
+#define LPC43M4_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
+#define LPC43M4_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
+#define LPC43M4_SYSH_PRIORITY_STEP 0x10 /* Steps between priorities */
+
+#define LPC43M0_SYSH_PRIORITY_MIN 0xc0 /* All bits[7:6] set is minimum priority */
+#define LPC43M0_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
+#define LPC43M0_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
+#define LPC43M0_SYSH_PRIORITY_STEP 0x20 /* Steps between priorities */
+
+/* Only the Cortex-M4 is supported by Nuttx */
+
+#define NVIC_SYSH_PRIORITY_MIN LPC43M4_SYSH_PRIORITY_MIN
+#define NVIC_SYSH_PRIORITY_DEFAULT LPC43M4_SYSH_PRIORITY_DEFAULT
+#define NVIC_SYSH_PRIORITY_MAX LPC43M4_SYSH_PRIORITY_MAX
+#define NVIC_SYSH_PRIORITY_STEP LPC43M4_SYSH_PRIORITY_INCR
+
+#define NVIC_SYSH_DISABLE_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP)
+#define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX
+
/************************************************************************************
* Public Types
************************************************************************************/