Tiva: Updated files to allow for ADC triggering by the timer. I’ve cleaned up some parts of the ADC code, too, and fleshed out the PWM triggering ioctl. From Calvin Maguranis

5 files changed, 832 insertions, 952 deletions

diff --git a/nuttx/arch/arm/src/tiva/Kconfig b/nuttx/arch/arm/src/tiva/Kconfig
index 94083af81..2691373c4 100644
--- a/nuttx/arch/arm/src/tiva/Kconfig
+++ b/nuttx/arch/arm/src/tiva/Kconfig
@@ -802,6 +802,14 @@ config TIVA_TIMER32_PERIODIC
 	bool "32-bit one-shot/periodic timer support"
 	default n
 
+config TIVA_TIMER32_ADCEVENT
+	bool "32-bit one-shot/periodic timer ADC event support"
+	default n
+	depends on TIVA_TIMER32_PERIODIC
+	depends on TIVA_TIMER_32BIT
+	---help---
+		Enable timer support for triggering an ADC sample on timeout.
+
 config TIVA_TIMER32_RTC
 	bool "32-bit RTC (needs 32.768-KHz input)"
 	default n
@@ -818,17 +826,25 @@ config TIVA_TIMER16_PERIODIC
 	bool "16-bit one-shot/periodic timer support"
 	default n
 
-config TIVA_TIMER32_EDGECOUNT
+config TIVA_TIMER16_ADCEVENT
+	bool "16-bit one-shot/periodic timer ADC event support"
+	default n
+	depends on TIVA_TIMER16_PERIODIC
+	depends on TIVA_TIMER_16BIT
+	---help---
+		Enable timer support for triggering an ADC sample on timeout.
+
+config TIVA_TIMER16_EDGECOUNT
 	bool "16-bit input edge-count capture support"
 	default n
 	depends on EXPERIMENTAL
 
-config TIVA_TIMER32_TIMECAP
+config TIVA_TIMER16_TIMECAP
 	bool "16-bit input time capture support"
 	default n
 	depends on EXPERIMENTAL
 
-config TIVA_TIMER32_PWM
+config TIVA_TIMER16_PWM
 	bool "16-bit PWM output support"
 	default n
 	depends on EXPERIMENTAL
@@ -858,7 +874,6 @@ config TIVA_ADC_CLOCK
 		16 MHz to 32 MHz. The TM4C123 clock is limited to 16 MHz.
 
 if TIVA_ADC0
-menu "Tiva ADC0 configuration"
 
 menuconfig TIVA_ADC0_SSE0
 	bool "Enable and configure ADC0 SSE0"
@@ -1290,11 +1305,9 @@ config TIVA_ADC0_SSE3_STEP0_AIN
 	default 0
 	depends on TIVA_ADC0_SSE3_STEP0
 
-endmenu # Tiva ADC0 configuration
 endif # TIVA_ADC0
 
 if TIVA_ADC1
-menu "Tiva ADC1 configuration"
 
 menuconfig TIVA_ADC1_SSE0
 	bool "Enable and configure ADC1 SSE0"
@@ -1725,7 +1738,6 @@ config TIVA_ADC1_SSE3_TRIGGER
 		default 0
 		depends on TIVA_ADC1_SSE3_STEP0
 
-endmenu # Tiva ADC1 configuration
 endif # TIVA_ADC1
 
 config TIVA_ADC_REGDEBUG
diff --git a/nuttx/arch/arm/src/tiva/tiva_adc.c b/nuttx/arch/arm/src/tiva/tiva_adc.c
index ecf915904..6586ec332 100644
--- a/nuttx/arch/arm/src/tiva/tiva_adc.c
+++ b/nuttx/arch/arm/src/tiva/tiva_adc.c
@@ -92,54 +92,76 @@
  * Pre-processor Definitions
  ****************************************************************************/
 
-/* Misc utility defines *****************************************************/
-
-#  define TIVA_ADC_ENABLE  true
-#  define TIVA_ADC_DISABLE false
+/* Configuration ************************************************************/
 
-#  define TIVA_ADC_RESOLUTION 4095
+#ifndef CONFIG_TIVA_ADC_CLOCK
+#  define CONFIG_TIVA_ADC_CLOCK TIVA_ADC_CLOCK_MIN
+#endif
 
-#  ifdef CONFIG_ARCH_CHIP_TM4C123
-#    define TIVA_ADC_CLOCK_MAX (16000000)
-#    define TIVA_ADC_CLOCK_MIN (16000000)
-#  elif CONFIG_ARCH_CHIP_TM4C129
-#    define TIVA_ADC_CLOCK_MAX (32000000)
-#    define TIVA_ADC_CLOCK_MIN (16000000)
-#  else
-#    error TIVA_ADC_CLOCK: unsupported architecture
-#  endif                               /* CONFIG_ARCH_CHIP_TM4C129 */
+#ifdef CONFIG_TIVA_ADC_VREF
+#  ifndef CONFIG_ARCH_CHIP_TM4C129
+#    error Voltage reference selection only supported in TM4C129 parts
+#  endif
+#endif
 
-/* Allow the same function call to be used for sample rate */
+#ifdef CONFIG_TIVA_ADC_ALT_CLK
+#  warning CONFIG_TIVA_ADC_ALT_CLK unsupported.
+#endif
 
-#  ifdef CONFIG_ARCH_CHIP_TM4C123
-#    define TIVA_ADC_SAMPLE_RATE_SLOWEST  (ADC_PC_SR_125K)
-#    define TIVA_ADC_SAMPLE_RATE_SLOW     (ADC_PC_SR_250K)
-#    define TIVA_ADC_SAMPLE_RATE_FAST     (ADC_PC_SR_500K)
-#    define TIVA_ADC_SAMPLE_RATE_FASTEST  (ADC_PC_SR_1M)
-#  elif CONFIG_ARCH_CHIP_TM4C129
-#    define TIVA_ADC_SAMPLE_RATE_SLOWEST  (ADC_PC_MCR_1_8)
-#    define TIVA_ADC_SAMPLE_RATE_SLOW     (ADC_PC_MCR_1_4)
-#    define TIVA_ADC_SAMPLE_RATE_FAST     (ADC_PC_MCR_1_2)
-#    define TIVA_ADC_SAMPLE_RATE_FASTEST  (ADC_PC_MCR_FULL)
-#  else
-#    error TIVA_ADC_SAMPLE_RATE: unsupported architecture
-#  endif                               /* CONFIG_ARCH_CHIP_TM4C12* */
+/* Are we using interrupt-based triggering (opposed to SW triggering)? Then work
+ * queues are required.
+ */
 
-/* Configuration ************************************************************/
+#if (CONFIG_TIVA_ADC0_SSE0_TRIGGER > 0) || (CONFIG_TIVA_ADC0_SSE1_TRIGGER > 0) || \
+    (CONFIG_TIVA_ADC0_SSE2_TRIGGER > 0) || (CONFIG_TIVA_ADC0_SSE3_TRIGGER > 0) || \
+    (CONFIG_TIVA_ADC0_SSE0_TRIGGER > 0) || (CONFIG_TIVA_ADC0_SSE1_TRIGGER > 0) || \
+    (CONFIG_TIVA_ADC0_SSE2_TRIGGER > 0) || (CONFIG_TIVA_ADC0_SSE3_TRIGGER > 0)
+#  define TIVA_ADC_HAVE_INTERRUPTS 1
+#endif
 
-#  ifndef CONFIG_TIVA_ADC_CLOCK
-#    define CONFIG_TIVA_ADC_CLOCK TIVA_ADC_CLOCK_MIN
+#ifdef TIVA_ADC_HAVE_INTERRUPTS
+#  ifndef CONFIG_SCHED_WORKQUEUE
+#    error Work queue support is required (CONFIG_SCHED_WORKQUEUE) for ADC interrupts
 #  endif
+#endif
+
+#ifndef CONFIG_DEBUG
+#  undef CONFIG_TIVA_ADC_REGDEBUG
+#endif
 
-#  ifdef CONFIG_TIVA_ADC_VREF
-#    ifndef CONFIG_ARCH_CHIP_TM4C129
-#      error Voltage reference selection only supported in TM4C129 parts
-#    endif                             /* CONFIG_ARCH_CHIP_TM4C129 */
-#  endif                               /* CONFIG_TIVA_ADC_VREF */
 
-#  ifdef CONFIG_TIVA_ADC_ALT_CLK
-#    warning CONFIG_TIVA_ADC_ALT_CLK unsupported.
-#  endif                               /* CONFIG_TIVA_ADC_ALT_CLK */
+/* Misc utility defines *****************************************************/
+
+#define TIVA_ADC_ENABLE  true
+#define TIVA_ADC_DISABLE false
+
+#define TIVA_ADC_RESOLUTION 4095
+
+#ifdef CONFIG_ARCH_CHIP_TM4C123
+#  define TIVA_ADC_CLOCK_MAX (16000000)
+#  define TIVA_ADC_CLOCK_MIN (16000000)
+#elif CONFIG_ARCH_CHIP_TM4C129
+#  define TIVA_ADC_CLOCK_MAX (32000000)
+#  define TIVA_ADC_CLOCK_MIN (16000000)
+#else
+#  error TIVA_ADC_CLOCK: unsupported architecture
+#endif
+
+/* Allow the same function call to be used for sample rate */
+
+#ifdef CONFIG_ARCH_CHIP_TM4C123
+#  define TIVA_ADC_SAMPLE_RATE_SLOWEST  (ADC_PC_SR_125K)
+#  define TIVA_ADC_SAMPLE_RATE_SLOW     (ADC_PC_SR_250K)
+#  define TIVA_ADC_SAMPLE_RATE_FAST     (ADC_PC_SR_500K)
+#  define TIVA_ADC_SAMPLE_RATE_FASTEST  (ADC_PC_SR_1M)
+#elif CONFIG_ARCH_CHIP_TM4C129
+#  define TIVA_ADC_SAMPLE_RATE_SLOWEST  (ADC_PC_MCR_1_8)
+#  define TIVA_ADC_SAMPLE_RATE_SLOW     (ADC_PC_MCR_1_4)
+#  define TIVA_ADC_SAMPLE_RATE_FAST     (ADC_PC_MCR_1_2)
+#  define TIVA_ADC_SAMPLE_RATE_FASTEST  (ADC_PC_MCR_FULL)
+#else
+#  error TIVA_ADC_SAMPLE_RATE: unsupported architecture
+#endif
 
 /* Utility macros ***********************************************************/
 
@@ -149,68 +171,72 @@
  * to the TSSEL_PS register
  */
 
-#  define ADC_TRIG_PWM_CFG(t) \
-    (1<<(ADC_TSSEL_PS_SHIFT(ADC_TRIG_PWM_GEN(t))))
+#define ADC_TRIG_PWM_CFG(t) \
+    (1<<(ADC_TSSEL_PS_SHIFT(ADC_TRIG_gen(t))))
 
 /* ADC support definitions **************************************************/
 
-#  define ADC_CHN_AIN(n)   GPIO_ADC_AIN##n
-#  define TIVA_ADC_PIN(n)  ADC_CHN_AIN(n)
+#define ADC_CHN_AIN(n)   GPIO_ADC_AIN##n
+#define TIVA_ADC_PIN(n)  ADC_CHN_AIN(n)
 
-#  define SSE_PROC_TRIG(n)  (1 << (n))
-#  define SSE_PROC_TRIG_ALL (0xF)
+#define SSE_PROC_TRIG(n)  (1 << (n))
+#define SSE_PROC_TRIG_ALL (0xF)
 
-#  define SSE_IDX(a,s)      (((a)*SSE_PER_BASE) + (s))
+#define SSE_IDX(a,s)      (((a)*SSE_PER_BASE) + (s))
 
-#  define MAX_NORMAL_CHN 15
-#  define BASE_PER_ADC   2
-#  define SSE_PER_BASE   4
-#  define SSE_MAX_STEP   8
-#  define NUM_SSE(n)     (sizeof(n)/sizeof(n[0]))
+#define MAX_NORMAL_CHN 15
+#define BASE_PER_ADC   2
+#define SSE_PER_BASE   4
+#define SSE_MAX_STEP   8
+#define NUM_SSE(n)     (sizeof(n)/sizeof(n[0]))
 
-#  define GET_AIN(a,s,c) (uint8_t)((getreg32( \
+#define GET_AIN(a,s,c) (uint8_t)((getreg32( \
     TIVA_ADC_BASE(a)+TIVA_ADC_SSMUX(s)) & ADC_SSMUX_MUX_MASK(c)) >> ADC_SSMUX_MUX_SHIFT(c))
 
-#  define ADC_SSE_STEP_NULL 0xFF
+#define ADC_SSE_STEP_NULL 0xFF
 
-#  define CLOCK_CONFIG(div, src) \
+#define CLOCK_CONFIG(div, src) \
     ( ((((div) << ADC_CC_CLKDIV_SHIFT) & ADC_CC_CLKDIV_MASK) | \
     ((src) & ADC_CC_CS_MASK)) & (ADC_CC_CLKDIV_MASK + ADC_CC_CS_MASK) )
 
-#  define SEM_PROCESS_PRIVATE 0
-#  define SEM_PROCESS_SHARED  1
+#define SEM_PROCESS_PRIVATE 0
+#define SEM_PROCESS_SHARED  1
 
 /* Debug ********************************************************************/
 
 /* CONFIG_DEBUG_ADC + CONFIG_DEBUG enables general ADC debug output. */
 
-#  ifdef CONFIG_DEBUG_ADC
-#    define adcdbg dbg
-#    define adcvdbg vdbg
-#  else
-#    define adcdbg(x...)
-#    define adcvdbg(x...)
-#  endif
-
-#  ifndef CONFIG_DEBUG
-#    undef CONFIG_TIVA_ADC_REGDEBUG
-#  endif
+#ifdef CONFIG_DEBUG_ADC
+#  define adcdbg    dbg
+#  define adcvdbg   vdbg
+#  define adclldbg  lldbg
+#  define adcllvdbg lldbg
+#else
+#  define adcdbg(x...)
+#  define adcvdbg(x...)
+#  define adclldbg(x...)
+#  define adcllvdbg(x...)
+#endif
+
+#ifndef CONFIG_DEBUG
+#  undef CONFIG_TIVA_ADC_REGDEBUG
+#endif
 
 /* ADC event trace logic.  NOTE:  trace uses the internal, non-standard, low-level
  * debug interface syslog() but does not require that any other debug
  * is enabled.
  */
 
-#  ifndef CONFIG_ADC_TRACE
-#    define tiva_adc_tracereset(p)
-#    define tiva_adc_tracenew(p,s)
-#    define tiva_adc_traceevent(p,e,a)
-#    define tiva_adc_tracedump(p)
-#  endif
+#ifndef CONFIG_ADC_TRACE
+#  define tiva_adc_tracereset(p)
+#  define tiva_adc_tracenew(p,s)
+#  define tiva_adc_traceevent(p,e,a)
+#  define tiva_adc_tracedump(p)
+#endif
 
-#  ifndef CONFIG_ADC_NTRACE
-#    define CONFIG_ADC_NTRACE 32
-#  endif
+#ifndef CONFIG_ADC_NTRACE
+#  define CONFIG_ADC_NTRACE 32
+#endif
 
 /****************************************************************************
  * Public Functions
@@ -257,18 +283,21 @@ struct tiva_adc_s
   uint8_t devno;              /* ADC device number */
   struct tiva_adc_sse_s *sse[SSE_PER_BASE];   /* Sample sequencer operation
                                                * state */
+#ifdef CONFIG_TIVA_ADC_REGDEBUG
   /* Debug stuff */
-#  ifdef CONFIG_TIVA_ADC_REGDEBUG
+
   bool wrlast;                /* Last was a write */
   uintptr_t addrlast;         /* Last address */
   uint32_t vallast;           /* Last value */
   int ntimes;                 /* Number of times */
-#  endif                        /* CONFIG_TIVA_ADC_REGDEBUG */
+#endif                        /* CONFIG_TIVA_ADC_REGDEBUG */
 };
 
 struct tiva_adc_sse_s
 {
+  struct tiva_adc_s *adc;     /* Parent peripheral */
   sem_t exclsem;              /* Mutual exclusion semaphore */
+  struct work_s work;         /* Supports the interrupt handling "bottom half" */
   bool ena;                   /* Sample sequencer operation state */
   uint32_t irq;               /* SSE interrupt vectors */
   uint8_t num;                /* SSE number */
@@ -279,17 +308,18 @@ struct tiva_adc_sse_s
  ****************************************************************************/
 
 /* Debug ADC functions **********************************************/
-#  if defined(CONFIG_TIVA_ADC_REGDEBUG) && defined(CONFIG_DEBUG)
+
+#if defined(CONFIG_TIVA_ADC_REGDEBUG) && defined(CONFIG_DEBUG)
 static bool tiva_adc_checkreg(struct tiva_adc_s *priv, bool wr,
                               uint32_t regval, uintptr_t address);
-#  endif
+#endif
 
-#  ifdef CONFIG_TIVA_ADC_REGDEBUG
+#ifdef CONFIG_TIVA_ADC_REGDEBUG
 static void tiva_adc_modifyreg(struct tiva_adc_s *priv, unsigned int addr,
                                uint32_t clearbits, uint32_t setbits);
-#  else
-#    define tiva_adc_modifyreg(priv,addr,clearbits,setbits) modifyreg32(addr,clearbits,setbits)
-#  endif
+#else
+#  define tiva_adc_modifyreg(priv,addr,clearbits,setbits) modifyreg32(addr,clearbits,setbits)
+#endif
 
 /* TM4C-specific ADC functions **********************************************/
 
@@ -297,9 +327,12 @@ static void tiva_adc_modifyreg(struct tiva_adc_s *priv, unsigned int addr,
 
 static int adc_state(struct tiva_adc_s *adc, bool state);
 static void adc_clock(uint32_t freq);
-#  ifdef CONFIG_ARCH_CHIP_TM4C129
+#ifdef CONFIG_ARCH_CHIP_TM4C129
 static void adc_vref(uint8_t vref);
-#  endif                               /* CONFIG_ARCH_CHIP_TM4C129 */
+#endif
+#ifdef CONFIG_TIVA_ADC_INTERRUPTS
+static void tiva_adc_read(void *arg);
+#endif
 
 /* Peripheral (base) level */
 
@@ -311,10 +344,9 @@ static uint32_t adc_int_status(struct tiva_adc_s *adc);
 
 static void sse_state(struct tiva_adc_s *adc, uint8_t sse, bool state);
 static void sse_trigger(struct tiva_adc_s *adc, uint8_t sse, uint32_t trigger);
-#  ifdef CONFIG_EXPERIMENTAL
-static void sse_pwm_trig_ioctl(struct tiva_adc_s *adc, uint8_t sse,
-                               uint32_t cfg);
-#  endif
+#ifdef CONFIG_EXPERIMENTAL
+static void sse_pwm_trig_ioctl(struct tiva_adc_s *adc, uint8_t sse, uint32_t cfg);
+#endif
 static int sse_data(struct tiva_adc_s *adc, uint8_t sse);
 static void sse_priority(struct tiva_adc_s *adc, uint8_t sse, uint8_t priority);
 
@@ -326,58 +358,58 @@ static void sse_register_chn(struct tiva_adc_s *adc, uint8_t sse, uint8_t chn,
                              uint32_t ain);
 static void sse_differential(struct tiva_adc_s *adc, uint8_t sse, uint8_t chn,
                              uint32_t diff);
-#  ifdef CONFIG_EXPERIMENTAL
+#ifdef CONFIG_EXPERIMENTAL
 static void sse_sample_hold_time(struct tiva_adc_s *adc, uint8_t sse,
                                  uint8_t chn, uint32_t shold);
-#  endif
+#endif
 static void sse_step_cfg(struct tiva_adc_s *adc, uint8_t sse, uint8_t chn,
                          uint8_t cfg);
 
 /* Helper functions *********************************************************/
 
-#  ifdef CONFIG_TIVA_ADC0
+#ifdef CONFIG_TIVA_ADC0
 static void tiva_adc0_sse_init(void);
 static void tiva_adc0_assign_channels(void);
 static void tiva_adc0_assign_interrupts(void);
-#    ifdef CONFIG_TIVA_ADC0_SSE0
+#  ifdef CONFIG_TIVA_ADC0_SSE0
 static void adc0_sse0_chn_cfg(void);
 static void adc0_sse0_interrupt(int irq, void *context);
-#    endif
-#    ifdef CONFIG_TIVA_ADC0_SSE1
+#  endif
+#  ifdef CONFIG_TIVA_ADC0_SSE1
 static void adc0_sse1_chn_cfg(void);
 static void adc0_sse1_interrupt(int irq, void *context);
-#    endif
-#    ifdef CONFIG_TIVA_ADC0_SSE2
+#  endif
+#  ifdef CONFIG_TIVA_ADC0_SSE2
 static void adc0_sse2_chn_cfg(void);
 static void adc0_sse2_interrupt(int irq, void *context);
-#    endif
-#    ifdef CONFIG_TIVA_ADC0_SSE3
+#  endif
+#  ifdef CONFIG_TIVA_ADC0_SSE3
 static void adc0_sse3_chn_cfg(void);
 static void adc0_sse3_interrupt(int irq, void *context);
-#    endif
 #  endif
+#endif
 
-#  ifdef CONFIG_TIVA_ADC1
+#ifdef CONFIG_TIVA_ADC1
 static void tiva_adc1_sse_init(void);
 static void tiva_adc1_assign_channels(void);
 static void tiva_adc1_assign_interrupts(void);
-#    ifdef CONFIG_TIVA_ADC1_SSE0
+#  ifdef CONFIG_TIVA_ADC1_SSE0
 static void adc1_sse0_chn_cfg(void);
 static void adc1_sse0_interrupt(int irq, void *context);
-#    endif
-#    ifdef CONFIG_TIVA_ADC1_SSE1
+#  endif
+#  ifdef CONFIG_TIVA_ADC1_SSE1
 static void adc1_sse1_chn_cfg(void);
 static void adc1_sse1_interrupt(int irq, void *context);
-#    endif
-#    ifdef CONFIG_TIVA_ADC1_SSE2
+#  endif
+#  ifdef CONFIG_TIVA_ADC1_SSE2
 static void adc1_sse2_chn_cfg(void);
 static void adc1_sse2_interrupt(int irq, void *context);
-#    endif
-#    ifdef CONFIG_TIVA_ADC1_SSE3
+#  endif
+#  ifdef CONFIG_TIVA_ADC1_SSE3
 static void adc1_sse3_chn_cfg(void);
 static void adc1_sse3_interrupt(int irq, void *context);
-#    endif
 #  endif
+#endif
 
 /****************************************************************************
  * Private Data
@@ -387,10 +419,13 @@ static void adc1_sse3_interrupt(int irq, void *context);
 
 static struct tiva_adc_state_s adc_common =
 {
-  .init = {
+  .init =
+  {
     false,
-    false},
-  .sse = {
+    false
+  },
+  .sse =
+  {
     false,
     false,
     false,
@@ -398,48 +433,49 @@ static struct tiva_adc_state_s adc_common =
     false,
     false,
     false,
-    false},
+    false
+  },
 };
 
-#  ifdef CONFIG_TIVA_ADC0
+#ifdef CONFIG_TIVA_ADC0
 
 /* ADC device instance 0 */
 
 static struct adc_dev_s g_adcdev0;
 static struct tiva_adc_s adc0;
-#    ifdef CONFIG_TIVA_ADC0_SSE0
+#  ifdef CONFIG_TIVA_ADC0_SSE0
 static struct tiva_adc_sse_s sse00;
-#    endif
-#    ifdef CONFIG_TIVA_ADC0_SSE1
+#  endif
+#  ifdef CONFIG_TIVA_ADC0_SSE1
 static struct tiva_adc_sse_s sse01;
-#    endif
-#    ifdef CONFIG_TIVA_ADC0_SSE2
+#  endif
+#  ifdef CONFIG_TIVA_ADC0_SSE2
 static struct tiva_adc_sse_s sse02;
-#    endif
-#    ifdef CONFIG_TIVA_ADC0_SSE3
+#  endif
+#  ifdef CONFIG_TIVA_ADC0_SSE3
 static struct tiva_adc_sse_s sse03;
-#    endif
 #  endif
+#endif
 
-#  ifdef CONFIG_TIVA_ADC1
+#ifdef CONFIG_TIVA_ADC1
 
 /* ADC device instance 1 */
 
 static struct adc_dev_s g_adcdev1;
 static struct tiva_adc_s adc1;
-#    ifdef CONFIG_TIVA_ADC1_SSE0
+#  ifdef CONFIG_TIVA_ADC1_SSE0
 static struct tiva_adc_sse_s sse10;
-#    endif
-#    ifdef CONFIG_TIVA_ADC1_SSE1
+#  endif
+#  ifdef CONFIG_TIVA_ADC1_SSE1
 static struct tiva_adc_sse_s sse11;
-#    endif
-#    ifdef CONFIG_TIVA_ADC1_SSE2
+#  endif
+#  ifdef CONFIG_TIVA_ADC1_SSE2
 static struct tiva_adc_sse_s sse12;
-#    endif
-#    ifdef CONFIG_TIVA_ADC1_SSE3
+#  endif
+#  ifdef CONFIG_TIVA_ADC1_SSE3
 static struct tiva_adc_sse_s sse13;
-#    endif
 #  endif
+#endif
 
 /****************************************************************************
  * Private Functions
@@ -457,7 +493,9 @@ static struct tiva_adc_sse_s sse13;
 static void tiva_adc_reset(struct adc_dev_s *dev)
 {
   struct tiva_adc_s *priv = (struct tiva_adc_s *)dev->ad_priv;
+
   adcvdbg("Resetting...\n");
+
   /* Only if ADCs are active do we run the reset routine: - disable ADC
    * interrupts - clear interrupt bits - disable all active sequences
    * Otherwise, if the peripheral is inactive, perform no operations since
@@ -496,6 +534,7 @@ static void tiva_adc_reset(struct adc_dev_s *dev)
 static int tiva_adc_setup(struct adc_dev_s *dev)
 {
   adcvdbg("Setup\n");
+
   /* Only if ADCs are active do we run the reset routine: - enable ADC
    * interrupts - clear interrupt bits - enable all active sequences - register
    * triggers and respective interrupt handlers Otherwise, if the peripheral is
@@ -529,9 +568,11 @@ static int tiva_adc_setup(struct adc_dev_s *dev)
 static void tiva_adc_shutdown(struct adc_dev_s *dev)
 {
   struct tiva_adc_s *priv = (struct tiva_adc_s *)dev->ad_priv;
+
   adcvdbg("Shutdown\n");
 
   /* Reset the ADC peripheral */
+
   tiva_adc_reset(dev);
 
   uint8_t s = 0;
@@ -564,6 +605,7 @@ static void tiva_adc_shutdown(struct adc_dev_s *dev)
 static void tiva_adc_rxint(struct adc_dev_s *dev, bool enable)
 {
   struct tiva_adc_s *priv = (struct tiva_adc_s *)dev->ad_priv;
+
   adcvdbg("rx enable=%d\n", enable);
 
   uint8_t s = 0;
@@ -573,7 +615,7 @@ static void tiva_adc_rxint(struct adc_dev_s *dev, bool enable)
         (tiva_adc_getreg(priv, TIVA_ADC_EMUX(priv->devno)) >> s) & 0xF;
       if (adc_common.sse[SSE_IDX(priv->devno, s)] && (trigger > 0))
         {
-          sse_state(priv, s, enable);
+          sse_int_state(priv, s, enable);
         }
     }
 }
@@ -597,50 +639,61 @@ static int tiva_adc_ioctl(struct adc_dev_s *dev, int cmd, unsigned long arg)
 {
   struct tiva_adc_s *priv = (struct tiva_adc_s *)dev->ad_priv;
   int ret = OK;
-  uint32_t stat = 0;
-  uint8_t sse = (uint8_t) arg;
+  uint32_t regval = 0;
+  uint8_t sse = 0;
 
   adcvdbg("cmd=%d arg=%ld\n", cmd, arg);
+
   switch (cmd)
     {
       /* Software trigger */
 
       case ANIOC_TRIGGER:
 
+        sse = (uint8_t) arg;
+
         /* start conversion and read to buffer */
 
         adc_proc_trig(priv, (uint8_t) SSE_PROC_TRIG(sse));
-        stat = adc_int_status(priv) & (1 << sse);
-        while (!stat)
+        regval = adc_int_status(priv) & (1 << sse);
+        while (!regval)
           {
-            stat = adc_int_status(priv) & (1 << sse);
+            regval = adc_int_status(priv) & (1 << sse);
           }
 
         sse_clear_int(priv, sse);
         sse_data(priv, sse);
         break;
 
-        /* TODO: Needs to be tested, needs to encode which SSE since trigger type
-         * isn't tracked and, needs a PWM driver to use.
-         */
-
-#  if 0
       /* PWM triggering */
 
+#warning Missing Logic
+
+      /* TODO: Needs to be tested */
+
+#ifdef CONFIG_EXPERIMENTAL
+
       case TIVA_ADC_PWM_TRIG_IOCTL:
-        for (s = 0; s < SSE_PER_BASE; ++s)
+
+        /* Verify input SSE trigger is a PWM trigger */
+
+        sse = (uint8_t)(arg & 0x2);
+        regval = (tiva_adc_getreg(priv, (TIVA_ADC_EMUX(adc->devno))) >>
+            ADC_EMUX_SHIFT(sse)) & ADC_EMUX_MASK(sse);
+
+        if ((regval == ADC_EMUX_PWM0) ||
+            (regval == ADC_EMUX_PWM1) ||
+            (regval == ADC_EMUX_PWM2) ||
+            (regval == ADC_EMUX_PWM3))
           {
-            if (adc_common.sse[SSE_IDX(priv->devno, s)])
-              {
-                /* TODO: fixme */
-                if (priv, s->trigger & ADC_TRIG_PWM_MASK)
-                  {
-                    sse_pwm_trig_ioctl(priv, s, (uint32_t) arg);
-                  }
-              }
+            sse_pwm_trig_ioctl(priv, sse, (uint32_t)(arg&0xFFFFFFFC));
           }
+
         break;
-#  endif
+
+#endif
+
+#warning Missing Logic
 
       /* Unsupported or invalid command */
 
@@ -653,10 +706,56 @@ static int tiva_adc_ioctl(struct adc_dev_s *dev, int cmd, unsigned long arg)
 }
 
 /****************************************************************************
+ * Name: tiva_adc_read
+ *
+ * Description:
+ *   This function executes on the worker thread.  It is scheduled by
+ *   sam_adc_interrupt whenever any enabled event occurs. All interrupts
+ *   are disabled when this function runs. tiva_adc_read will
+ *   re-enable interrupts when it completes processing all pending events.
+ *
+ * Input Parameters
+ *   arg - The ADC SSE data structure cast to (void *)
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+static void tiva_adc_read(void *arg)
+{
+  struct tiva_adc_sse_s *sse = (struct tiva_adc_sse_s *)arg;
+  uint32_t data = 0;
+  uint8_t fifo_count = 0;
+
+  /* Get exclusive access to the driver data structure */
+
+  tiva_adc_lock(sse->adc, sse->num);
+
+  /* Get sampled data */
+
+  while (!(tiva_adc_getreg(&adc0, TIVA_ADC_BASE(0) + TIVA_ADC_SSFSTAT(0)) &
+          ADC_SSFSTAT_EMPTY) && fifo_count < SSE_MAX_STEP)
+    {
+      data = tiva_adc_getreg(&adc0, TIVA_ADC_BASE(0) + TIVA_ADC_SSFIFO(0));
+      (void)adc_receive(adc0.dev, GET_AIN(0, 0, fifo_count), data);
+      ++fifo_count;
+    }
+
+  /* Exit, re-enabling ADC interrupts */
+
+  sse_int_state(&adc0, 0, TIVA_ADC_ENABLE);
+
+  /* Release our lock on the ADC structure */
+
+  tiva_adc_unlock(sse->adc, sse->num);
+}
+
+/****************************************************************************
  * Register Operations
  ****************************************************************************/
 
-#  ifdef CONFIG_TIVA_ADC_REGDEBUG
+#ifdef CONFIG_TIVA_ADC_REGDEBUG
 
 /****************************************************************************
  * Name: tiva_adc_checkreg
@@ -709,7 +808,7 @@ static bool tiva_adc_checkreg(struct tiva_adc_s *priv, bool wr,
 
   return true;
 }
-#  endif /* CONFIG_TIVA_ADC_REGDEBUG */
+#endif /* CONFIG_TIVA_ADC_REGDEBUG */
 
 /****************************************************************************
  * Name: tiva_adc_modifyreg
@@ -722,7 +821,7 @@ static bool tiva_adc_checkreg(struct tiva_adc_s *priv, bool wr,
  *
  ****************************************************************************/
 
-#  ifdef CONFIG_TIVA_ADC_REGDEBUG
+#ifdef CONFIG_TIVA_ADC_REGDEBUG
 static void tiva_adc_modifyreg(struct tiva_adc_s *priv, unsigned int addr,
                                uint32_t clearbits, uint32_t setbits)
 {
@@ -734,7 +833,7 @@ static void tiva_adc_modifyreg(struct tiva_adc_s *priv, unsigned int addr,
   tiva_adc_putreg(priv, addr, regval);
   irqrestore(flags);
 }
-#  endif /* CONFIG_TIVA_ADC_REGDEBUG */
+#endif /* CONFIG_TIVA_ADC_REGDEBUG */
 
 /* TM4C-specific ADC functions **********************************************/
 
@@ -755,25 +854,24 @@ static int adc_state(struct tiva_adc_s *adc, bool state)
 {
   if (state == TIVA_ADC_ENABLE)
     {
-
       /* Enable clocking to the ADC peripheral */
 
-#  ifdef TIVA_SYSCON_RCGCADC
+#ifdef TIVA_SYSCON_RCGCADC
       modifyreg32(TIVA_SYSCON_RCGCADC, 0, 1 << adc->devno);
-#  else
+#else
       modifyreg32(TIVA_SYSCON_RCGC0, 0, SYSCON_RCGC0_ADC0);
-#  endif
+#endif
       return OK;
     }
   else if (state == TIVA_ADC_DISABLE)
     {
       /* Disable clocking to the ADC peripheral */
 
-#  ifdef TIVA_SYSCON_RCGCADC
+#ifdef TIVA_SYSCON_RCGCADC
       modifyreg32(TIVA_SYSCON_RCGCADC, 1 << adc->devno, 0);
-#  else
+#else
       modifyreg32(TIVA_SYSCON_RCGC0, SYSCON_RCGC0_ADC0, 0);
-#  endif
+#endif
       return OK;
     }
 
@@ -802,7 +900,7 @@ static int adc_state(struct tiva_adc_s *adc, bool state)
 
 static void adc_clock(uint32_t freq)
 {
-#  if defined(CONFIG_ARCH_CHIP_TM4C123)
+#if defined(CONFIG_ARCH_CHIP_TM4C123)
   /* For the TM4C123, the ADC clock source does not affect the frequency, it
    * runs at 16 MHz regardless. You end up selecting between the MOSC (default)
    * or the PIOSC. The PIOSC allows the ADC to operate even in deep sleep mode.
@@ -811,8 +909,8 @@ static void adc_clock(uint32_t freq)
 
   uintptr_t ccreg = (TIVA_ADC0_BASE + TIVA_ADC_CC_OFFSET);
   modifyreg32(ccreg, 0, (freq & ADC_CC_CS_MASK));
-#  elif defined (CONFIG_ARCH_CHIP_TM4C129)
 
+#elif defined (CONFIG_ARCH_CHIP_TM4C129)
   /* check clock bounds and specific match cases */
 
   uint32_t clk_src = 0;
@@ -840,13 +938,11 @@ static void adc_clock(uint32_t freq)
 
   uintptr_t ccreg = (TIVA_ADC0_BASE + TIVA_ADC_CC_OFFSET);
   modifyreg32(ccreg, 0, CLOCK_CONFIG(div, clk_src));
-#  else
-#    error Unsupported architecture reported
-#  endif
+#else
+#  error Unsupported architecture reported
+#endif
 }
 
-#  ifdef CONFIG_ARCH_CHIP_TM4C129
-
 /****************************************************************************
  * Name: adc_vref
  *
@@ -858,6 +954,7 @@ static void adc_clock(uint32_t freq)
  *
  ****************************************************************************/
 
+#ifdef CONFIG_ARCH_CHIP_TM4C129
 static void adc_vref(uint8_t vref)
 {
   uintptr_t ctlreg = (TIVA_ADC0_BASE + TIVA_ADC_CTL_OFFSET);
@@ -870,7 +967,7 @@ static void adc_vref(uint8_t vref)
       modifyreg32(ctlreg, 0, vref);
     }
 }
-#  endif
+#endif
 
 /****************************************************************************
  * Name: adc_sample_rate
@@ -890,8 +987,7 @@ static void adc_sample_rate(uint8_t rate)
 {
   uintptr_t pcreg = (TIVA_ADC0_BASE + TIVA_ADC_PC_OFFSET);
 
-  /*
-   * NOTE: ADC_PC_SR_MASK is intended for use with the TM4C123, the
+  /* NOTE: ADC_PC_SR_MASK is intended for use with the TM4C123, the
    * alternative is ADC_PC_MCR_MASK for the TM4C129. However both masks
    * mask off the first 4 bits (0xF) so there is no need to distinguish
    * between the two.
@@ -923,9 +1019,9 @@ static void adc_proc_trig(struct tiva_adc_s *adc, uint8_t sse_mask)
 {
   uintptr_t pssireg = TIVA_ADC_PSSI(adc->devno);
   tiva_adc_modifyreg(adc, pssireg, 0, sse_mask);
-#  ifdef CONFIG_TIVA_ADC_SYNC
-#    warning CONFIG_TIVA_ADC_SYNC unsupported at this time.
-#  endif
+#ifdef CONFIG_TIVA_ADC_SYNC
+#  warning CONFIG_TIVA_ADC_SYNC unsupported at this time.
+#endif
 }
 
 /****************************************************************************
@@ -1029,32 +1125,28 @@ static void sse_trigger(struct tiva_adc_s *adc, uint8_t sse, uint32_t trigger)
  * Input parameters:
  *   adc - peripheral state
  *   sse - sample sequencer
- *   cfg - PWM and generator encoding
+ *   cfg - which PWM modulator and generator to use, use TIVA_ADC_PWM_TRIG
+ *         to encode the value correctly
  *
  ****************************************************************************/
 
-#  ifdef CONFIG_EXPERIMENTAL
-static void sse_pwm_trig_ioctl(struct tiva_adc_s *adc, uint8_t sse,
-                               uint32_t cfg)
+#ifdef CONFIG_EXPERIMENTAL
+static void sse_pwm_trig_ioctl(struct tiva_adc_s *adc, uint8_t sse, uint32_t cfg)
 {
-  if ((ADC_TRIG_PWM_MASK & cfg) > 0)
-    {
+  /* PWM triggering needs an additional register to be set (ADC_TSSEL) */
 
-      /* PWM triggering needs an additional register to be set (ADC_TSSEL) */
+  uintptr_t tsselreg = TIVA_ADC_TSSEL(adc->devno);
 
-      uintptr_t tsselreg = TIVA_ADC_TSSEL(adc->devno);
-      uint32_t pwmcfg = ADC_TRIG_PWM_CFG(cfg);
-      if ((cfg & ADC_EMUX_MASK(0)) == 1)
-        {
-          tiva_adc_modifyreg(adc, tsselreg, 0, pwmcfg);
-        }
-      else
-        {
-          tiva_adc_modifyreg(adc, tsselreg, pwmcfg, 0);
-        }
+  if ((cfg & ADC_EMUX_MASK(0)) == 1)
+    {
+      tiva_adc_modifyreg(adc, tsselreg, 0, cfg);
+    }
+  else
+    {
+      tiva_adc_modifyreg(adc, tsselreg, cfg, 0);
     }
 }
-#  endif
+#endif
 
 /****************************************************************************
  * Name: sse_int
@@ -1186,6 +1278,7 @@ static void sse_priority(struct tiva_adc_s *adc, uint8_t sse, uint8_t priority)
 {
   uintptr_t ssprireg = TIVA_ADC_SSPRI(adc->devno);
   uint32_t sspri = 0;
+
   if (priority == 0)
     {
       /* The 0 value is a special case since using modifyregn() results in an
@@ -1227,6 +1320,7 @@ static void sse_register_chn(struct tiva_adc_s *adc, uint8_t sse, uint8_t chn,
 
   uintptr_t ssmuxreg = (TIVA_ADC_BASE(adc->devno) + TIVA_ADC_SSMUX(sse));
   uint32_t step = 0;
+
   if (ain > 0)
     {
       step = ((ain << ADC_SSMUX_MUX_SHIFT(chn)) & ADC_SSMUX_MUX_MASK(chn));
@@ -1238,7 +1332,7 @@ static void sse_register_chn(struct tiva_adc_s *adc, uint8_t sse, uint8_t chn,
       tiva_adc_modifyreg(adc, ssmuxreg, step, 0);
     }
 
-#  ifdef CONFIG_ARCH_CHIP_TM4C129
+#ifdef CONFIG_ARCH_CHIP_TM4C129
   /* Configure SSE extended mux (SSEMUX) with step number and configuration */
 
   ssmuxreg = (TIVA_ADC_BASE(adc->devno) + TIVA_ADC_SSMUX(sse));
@@ -1251,7 +1345,7 @@ static void sse_register_chn(struct tiva_adc_s *adc, uint8_t sse, uint8_t chn,
     {
       tiva_adc_modifyreg(adc, ssmuxreg, step, 0);
     }
-#  endif
+#endif
 }
 
 /****************************************************************************
@@ -1271,16 +1365,16 @@ static void sse_register_chn(struct tiva_adc_s *adc, uint8_t sse, uint8_t chn,
 static void sse_differential(struct tiva_adc_s *adc, uint8_t sse, uint8_t chn,
                              uint32_t diff)
 {
-#  ifdef CONFIG_TIVA_ADC_DIFFERENTIAL
-#    error CONFIG_TIVA_ADC_DIFFERENTIAL unsupported!!
-#  else
+#ifdef CONFIG_TIVA_ADC_DIFFERENTIAL
+#  error CONFIG_TIVA_ADC_DIFFERENTIAL unsupported!!
+#else
 
   /* for now, ensure the FIFO is used and differential sampling is disabled */
 
   uintptr_t ssopreg = (TIVA_ADC_BASE(adc->devno) + TIVA_ADC_SSOP(sse));
   uint32_t sdcopcfg = (1 << chn);
   tiva_adc_modifyreg(adc, ssopreg, sdcopcfg, 0);
-#  endif
+#endif
 }
 
 /****************************************************************************
@@ -1300,7 +1394,7 @@ static void sse_differential(struct tiva_adc_s *adc, uint8_t sse, uint8_t chn,
  *
  ****************************************************************************/
 
-#  ifdef CONFIG_EXPERIMENTAL
+#ifdef CONFIG_EXPERIMENTAL
 static void sse_sample_hold_time(struct tiva_adc_s *adc, uint8_t sse,
                                  uint8_t chn, uint32_t shold)
 {
@@ -1314,7 +1408,7 @@ static void sse_sample_hold_time(struct tiva_adc_s *adc, uint8_t sse,
       tiva_adc_modifyreg(adc, sstshreg, ADC_SSTSH_MASK(sse), 0);
     }
 }
-#  endif
+#endif
 
 /****************************************************************************
  * Name: sse_step_cfg
@@ -1334,7 +1428,7 @@ static void sse_sample_hold_time(struct tiva_adc_s *adc, uint8_t sse,
  *       temperature sensor does not have a differential option, this bit must
  *       not be set when the TS3 bit is set.
  *
- *  *Comparator/Differental functionality is unsupported and ignored.
+ *  *Comparator/Differential functionality is unsupported and ignored.
  *
  * Input parameters:
  *   adc - peripheral state
@@ -1363,7 +1457,7 @@ static void sse_step_cfg(struct tiva_adc_s *adc, uint8_t sse, uint8_t chn,
  *   Initialize the ADC
  *
  * Returned Value:
- *   Valid can device structure reference on succcess; a NULL on failure
+ *   Valid can device structure reference on success; a NULL on failure
  *
  ****************************************************************************/
 
@@ -1375,7 +1469,7 @@ struct adc_dev_s *tiva_adc_initialize(int adc_num)
 
   struct tiva_adc_s *adc;
   uint8_t s;
-#  ifdef CONFIG_TIVA_ADC0
+#ifdef CONFIG_TIVA_ADC0
   if (adc_num == 0)
     {
       adc0.ena = false;
@@ -1383,46 +1477,46 @@ struct adc_dev_s *tiva_adc_initialize(int adc_num)
 
       /* Debug stuff */
 
-#    ifdef CONFIG_TIVA_ADC_REGDEBUG
+#  ifdef CONFIG_TIVA_ADC_REGDEBUG
       adc0.wrlast = false;
       adc0.addrlast = 0x0;
       adc0.vallast = 0x0;
       adc0.ntimes = 0;
-#    endif                             /* CONFIG_TIVA_ADC_REGDEBUG */
+#  endif                             /* CONFIG_TIVA_ADC_REGDEBUG */
 
       /* Initialize SSEs */
 
-#    ifdef CONFIG_TIVA_ADC0_SSE0
+#  ifdef CONFIG_TIVA_ADC0_SSE0
       sse00.ena = false;
       sse00.irq = TIVA_IRQ_ADC0;
       sse00.num = 0;
       sem_init(&sse00.exclsem, SEM_PROCESS_PRIVATE, 1);
       adc0.sse[0] = &sse00;
-#    endif                             /* CONFIG_TIVA_ADC0_SSE0 */
+#  endif                             /* CONFIG_TIVA_ADC0_SSE0 */
 
-#    ifdef CONFIG_TIVA_ADC0_SSE1
+#  ifdef CONFIG_TIVA_ADC0_SSE1
       sse01.ena = false;
-      sse01.irq = TIVA_IRQ_ADC0;
+      sse01.irq = TIVA_IRQ_ADC1;
       sse01.num = 1;
       sem_init(&sse01.exclsem, SEM_PROCESS_PRIVATE, 1);
       adc0.sse[1] = &sse01;
-#    endif                             /* CONFIG_TIVA_ADC0_SSE1 */
+#  endif                             /* CONFIG_TIVA_ADC0_SSE1 */
 
-#    ifdef CONFIG_TIVA_ADC0_SSE2
+#  ifdef CONFIG_TIVA_ADC0_SSE2
       sse02.ena = false;
-      sse02.irq = TIVA_IRQ_ADC0;
+      sse02.irq = TIVA_IRQ_ADC2;
       sse02.num = 2;
       sem_init(&sse02.exclsem, SEM_PROCESS_PRIVATE, 1);
       adc0.sse[2] = &sse02;
-#    endif                             /* CONFIG_TIVA_ADC0_SSE2 */
+#  endif                             /* CONFIG_TIVA_ADC0_SSE2 */
 
-#    ifdef CONFIG_TIVA_ADC0_SSE3
+#  ifdef CONFIG_TIVA_ADC0_SSE3
       sse03.ena = false;
-      sse03.irq = TIVA_IRQ_ADC0;
+      sse03.irq = TIVA_IRQ_ADC3;
       sse03.num = 3;
       sem_init(&sse03.exclsem, SEM_PROCESS_PRIVATE, 1);
       adc0.sse[3] = &sse03;
-#    endif                             /* CONFIG_TIVA_ADC0_SSE3 */
+#  endif                             /* CONFIG_TIVA_ADC0_SSE3 */
 
       adc0.dev = &g_adcdev0;
       adc = &adc0;
@@ -1432,9 +1526,9 @@ struct adc_dev_s *tiva_adc_initialize(int adc_num)
       g_adcdev0.ad_ops = &g_adcops;
       g_adcdev0.ad_priv = &adc0;
     }
-#  endif                               /* CONFIG_TIVA_ADC0 */
+#endif                               /* CONFIG_TIVA_ADC0 */
 
-#  ifdef CONFIG_TIVA_ADC1
+#ifdef CONFIG_TIVA_ADC1
   if (adc_num == 1)
     {
       adc1.ena = false;
@@ -1442,46 +1536,46 @@ struct adc_dev_s *tiva_adc_initialize(int adc_num)
 
       /* Debug stuff */
 
-#    ifdef CONFIG_TIVA_ADC_REGDEBUG
+#  ifdef CONFIG_TIVA_ADC_REGDEBUG
       adc1.wrlast = false;
       adc1.addrlast = 0x0;
       adc1.vallast = 0x0;
       adc1.ntimes = 0;
-#    endif                             /* CONFIG_TIVA_ADC_REGDEBUG */
+#  endif                             /* CONFIG_TIVA_ADC_REGDEBUG */
 
       /* Initialize SSEs */
 
-#    ifdef CONFIG_TIVA_ADC1_SSE0
+#  ifdef CONFIG_TIVA_ADC1_SSE0
       sse10.ena = false;
-      sse10.irq = TIVA_IRQ_ADC0;
+      sse10.irq = TIVA_IRQ_ADC1_0;
       sse10.num = 0;
       sem_init(&sse10.exclsem, SEM_PROCESS_PRIVATE, 1);
       adc1.sse[0] = &sse10;
-#    endif                             /* CONFIG_TIVA_ADC1_SSE0 */
+#  endif                             /* CONFIG_TIVA_ADC1_SSE0 */
 
-#    ifdef CONFIG_TIVA_ADC1_SSE1
+#  ifdef CONFIG_TIVA_ADC1_SSE1
       sse11.ena = false;
-      sse11.irq = TIVA_IRQ_ADC0;
+      sse11.irq = TIVA_IRQ_ADC1_1;
       sse11.num = 1;
       sem_init(&sse11.exclsem, SEM_PROCESS_PRIVATE, 1);
       adc1.sse[1] = &sse11;
-#    endif                             /* CONFIG_TIVA_ADC1_SSE1 */
+#  endif                             /* CONFIG_TIVA_ADC1_SSE1 */
 
-#    ifdef CONFIG_TIVA_ADC1_SSE2
+#  ifdef CONFIG_TIVA_ADC1_SSE2
       sse12.ena = false;
-      sse12.irq = TIVA_IRQ_ADC0;
+      sse12.irq = TIVA_IRQ_ADC1_2;
       sse12.num = 2;
       sem_init(&sse12.exclsem, SEM_PROCESS_PRIVATE, 1);
       adc1.sse[2] = &sse12;
-#    endif                             /* CONFIG_TIVA_ADC1_SSE2 */
+#  endif                             /* CONFIG_TIVA_ADC1_SSE2 */
 
-#    ifdef CONFIG_TIVA_ADC1_SSE3
+#  ifdef CONFIG_TIVA_ADC1_SSE3
       sse13.ena = false;
-      sse13.irq = TIVA_IRQ_ADC0;
+      sse13.irq = TIVA_IRQ_ADC1_3;
       sse13.num = 3;
       sem_init(&sse13.exclsem, SEM_PROCESS_PRIVATE, 1);
       adc1.sse[3] = &sse13;
-#    endif                             /* CONFIG_TIVA_ADC1_SSE3 */
+#  endif                             /* CONFIG_TIVA_ADC1_SSE3 */
 
       adc1.dev = &g_adcdev1;
       adc = &adc1;
@@ -1491,12 +1585,12 @@ struct adc_dev_s *tiva_adc_initialize(int adc_num)
       g_adcdev1.ad_ops = &g_adcops;
       g_adcdev1.ad_priv = &adc1;
     }
-#  endif                               /* CONFIG_TIVA_ADC1 */
+#endif                               /* CONFIG_TIVA_ADC1 */
 
   if (adc_num > 1)
     {
-      adcvdbg("ERROR: Invalid ADV devno given, must be 0 or 1! ADC Devno: %d\n",
-              adc_num);
+      adcdbg("ERROR: Invalid ADV devno given, must be 0 or 1! ADC Devno: %d\n",
+             adc_num);
       return NULL;
     }
 
@@ -1510,8 +1604,8 @@ struct adc_dev_s *tiva_adc_initialize(int adc_num)
 
       if (adc_state(adc, TIVA_ADC_ENABLE) < 0)
         {
-          adcvdbg("ERROR: failure to power ADC peripheral (devno=%d)\n",
-                  adc_num);
+          adcdbg("ERROR: failure to power ADC peripheral (devno=%d)\n",
+                 adc_num);
           return NULL;
         }
 
@@ -1523,11 +1617,11 @@ struct adc_dev_s *tiva_adc_initialize(int adc_num)
 
       adc_sample_rate(TIVA_ADC_SAMPLE_RATE_FASTEST);
 
-#  ifdef CONFIG_ARCH_CHIP_TM4C129
+#ifdef CONFIG_ARCH_CHIP_TM4C129
       /* voltage reference */
 
       adc_vref();
-#  endif                               /* CONFIG_ARCH_CHIP_TM4C129 */
+#endif                               /* CONFIG_ARCH_CHIP_TM4C129 */
       adc_common.init[adc->devno] = true;
     }
 
@@ -1539,7 +1633,7 @@ struct adc_dev_s *tiva_adc_initialize(int adc_num)
 
   if (adc->ena == false)
     {
-#  if CONFIG_TIVA_ADC0
+#if CONFIG_TIVA_ADC0
       if (adc_num == 0)
         {
           /* Configure sample sequencers */
@@ -1551,9 +1645,9 @@ struct adc_dev_s *tiva_adc_initialize(int adc_num)
           tiva_adc0_assign_interrupts();
           tiva_adc0_assign_channels();
         }
-#  endif
+#endif
 
-#  if CONFIG_TIVA_ADC1
+#if CONFIG_TIVA_ADC1
       if (adc_num == 1)
         {
           /* Configure sample sequencers */
@@ -1565,7 +1659,7 @@ struct adc_dev_s *tiva_adc_initialize(int adc_num)
           tiva_adc1_assign_interrupts();
           tiva_adc1_assign_channels();
         }
-#  endif
+#endif
 
       /* Enable SSEs */
 
@@ -1600,7 +1694,9 @@ struct adc_dev_s *tiva_adc_initialize(int adc_num)
 void tiva_adc_lock(FAR struct tiva_adc_s *priv, int sse)
 {
   int ret;
+
   adcvdbg("Locking\n");
+
   do
     {
       ret = sem_wait(&priv->sse[sse]->exclsem);
@@ -1636,7 +1732,7 @@ void tiva_adc_unlock(FAR struct tiva_adc_s *priv, int sse)
  *
  ****************************************************************************/
 
-#  ifdef CONFIG_TIVA_ADC_REGDEBUG
+#ifdef CONFIG_TIVA_ADC_REGDEBUG
 uint32_t tiva_adc_getreg(struct tiva_adc_s *priv, uintptr_t address)
 {
   uint32_t regval = getreg32(address);
@@ -1667,7 +1763,7 @@ void tiva_adc_putreg(struct tiva_adc_s *priv, uintptr_t address,
 
   putreg32(regval, address);
 }
-#  endif                               /* CONFIG_TIVA_ADC_REGDEBUG */
+#endif                               /* CONFIG_TIVA_ADC_REGDEBUG */
 
 /****************************************************************************
  * Name: Verbose, generated code
@@ -1680,1215 +1776,1008 @@ void tiva_adc_putreg(struct tiva_adc_s *priv, uintptr_t address,
 
 /* Sample sequencer initialization ******************************************/
 
-#  ifdef CONFIG_TIVA_ADC0
+#ifdef CONFIG_TIVA_ADC0
 static void tiva_adc0_sse_init(void)
 {
-#    ifdef CONFIG_TIVA_ADC0_SSE0
+#  ifdef CONFIG_TIVA_ADC0_SSE0
   sse_state(&adc0, 0, TIVA_ADC_DISABLE);
   sse_priority(&adc0, 0, CONFIG_TIVA_ADC0_SSE0_PRIORITY);
   sse_trigger(&adc0, 0, CONFIG_TIVA_ADC0_SSE0_TRIGGER);
   adc_common.sse[SSE_IDX(0, 0)] = true;
-#    endif
-
-#    ifdef CONFIG_TIVA_ADC0_SSE1
+#  endif
+#  ifdef CONFIG_TIVA_ADC0_SSE1
   sse_state(&adc0, 1, TIVA_ADC_DISABLE);
   sse_priority(&adc0, 1, CONFIG_TIVA_ADC0_SSE1_PRIORITY);
   sse_trigger(&adc0, 1, CONFIG_TIVA_ADC0_SSE1_TRIGGER);
   adc_common.sse[SSE_IDX(0, 1)] = true;
-#    endif
-
-#    ifdef CONFIG_TIVA_ADC0_SSE2
+#  endif
+#  ifdef CONFIG_TIVA_ADC0_SSE2
   sse_state(&adc0, 2, TIVA_ADC_DISABLE);
   sse_priority(&adc0, 2, CONFIG_TIVA_ADC0_SSE2_PRIORITY);
   sse_trigger(&adc0, 2, CONFIG_TIVA_ADC0_SSE2_TRIGGER);
   adc_common.sse[SSE_IDX(0, 2)] = true;
-#    endif
-
-#    ifdef CONFIG_TIVA_ADC0_SSE3
+#  endif
+#  ifdef CONFIG_TIVA_ADC0_SSE3
   sse_state(&adc0, 3, TIVA_ADC_DISABLE);
   sse_priority(&adc0, 3, CONFIG_TIVA_ADC0_SSE3_PRIORITY);
   sse_trigger(&adc0, 3, CONFIG_TIVA_ADC0_SSE3_TRIGGER);
   adc_common.sse[SSE_IDX(0, 3)] = true;
-#    endif
+#  endif
 }
-#  endif                               /* CONFIG_TIVA_ADC0 */
+#endif                               /* CONFIG_TIVA_ADC0 */
 
-#  ifdef CONFIG_TIVA_ADC1
+#ifdef CONFIG_TIVA_ADC1
 static void tiva_adc1_sse_init(void)
 {
-#    ifdef CONFIG_TIVA_ADC1_SSE0
+#  ifdef CONFIG_TIVA_ADC1_SSE0
   sse_state(&adc1, 0, TIVA_ADC_DISABLE);
   sse_priority(&adc1, 0, CONFIG_TIVA_ADC1_SSE0_PRIORITY);
   sse_trigger(&adc1, 0, CONFIG_TIVA_ADC1_SSE0_TRIGGER);
   adc_common.sse[SSE_IDX(1, 0)] = true;
-#    endif
-
-#    ifdef CONFIG_TIVA_ADC1_SSE1
+#  endif
+#  ifdef CONFIG_TIVA_ADC1_SSE1
   sse_state(&adc1, 1, TIVA_ADC_DISABLE);
   sse_priority(&adc1, 1, CONFIG_TIVA_ADC1_SSE1_PRIORITY);
   sse_trigger(&adc1, 1, CONFIG_TIVA_ADC1_SSE1_TRIGGER);
   adc_common.sse[SSE_IDX(1, 1)] = true;
-#    endif
-
-#    ifdef CONFIG_TIVA_ADC1_SSE2
+#  endif
+#  ifdef CONFIG_TIVA_ADC1_SSE2
   sse_state(&adc1, 2, TIVA_ADC_DISABLE);
   sse_priority(&adc1, 2, CONFIG_TIVA_ADC1_SSE2_PRIORITY);
   sse_trigger(&adc1, 2, CONFIG_TIVA_ADC1_SSE2_TRIGGER);
   adc_common.sse[SSE_IDX(1, 2)] = true;
-#    endif
-
-#    ifdef CONFIG_TIVA_ADC1_SSE3
+#  endif
+#  ifdef CONFIG_TIVA_ADC1_SSE3
   sse_state(&adc1, 3, TIVA_ADC_DISABLE);
   sse_priority(&adc1, 3, CONFIG_TIVA_ADC1_SSE3_PRIORITY);
   sse_trigger(&adc1, 3, CONFIG_TIVA_ADC1_SSE3_TRIGGER);
   adc_common.sse[SSE_IDX(1, 3)] = true;
-#    endif
+#  endif
 }
-#  endif                               /* CONFIG_TIVA_ADC1 */
+#endif                               /* CONFIG_TIVA_ADC1 */
 
 /* Sample sequencer interrupt initialization ********************************/
 
-#  ifdef CONFIG_TIVA_ADC0
+#ifdef TIVA_ADC_HAVE_INTERRUPTS
 static void tiva_adc0_assign_interrupts(void)
 {
+#  ifdef CONFIG_TIVA_ADC0
   uint32_t ret = 0;
 #    ifdef CONFIG_TIVA_ADC0_SSE0
-  ret = irq_attach(sse00.irq, (xcpt_t) adc0_sse0_interrupt);
+  ret = irq_attach(sse00.irq, (xcpt_t)adc0_sse0_interrupt);
   if (ret < 0)
     {
-      adbg("ERROR: Failed to attach IRQ %d: %d\n", sse00.irq, ret);
+      adcdbg("ERROR: Failed to attach IRQ %d: %d\n", sse00.irq, ret);
       return;
     }
-
   up_enable_irq(sse00.irq);
-#    endif                             /* CONFIG_TIVA_ADC0_SSE0 */
-
+#    endif
 #    ifdef CONFIG_TIVA_ADC0_SSE1
-  ret = irq_attach(sse01.irq, (xcpt_t) adc0_sse1_interrupt);
+  ret = irq_attach(sse01.irq, (xcpt_t)adc0_sse1_interrupt);
   if (ret < 0)
     {
-      adbg("ERROR: Failed to attach IRQ %d: %d\n", sse01.irq, ret);
+      adcdbg("ERROR: Failed to attach IRQ %d: %d\n", sse01.irq, ret);
       return;
     }
-
   up_enable_irq(sse01.irq);
-#    endif                             /* CONFIG_TIVA_ADC0_SSE1 */
-
+#    endif
 #    ifdef CONFIG_TIVA_ADC0_SSE2
-  ret = irq_attach(sse02.irq, (xcpt_t) adc0_sse2_interrupt);
+  ret = irq_attach(sse02.irq, (xcpt_t)adc0_sse2_interrupt);
   if (ret < 0)
     {
-      adbg("ERROR: Failed to attach IRQ %d: %d\n", sse02.irq, ret);
+      adcdbg("ERROR: Failed to attach IRQ %d: %d\n", sse02.irq, ret);
       return;
     }
-
   up_enable_irq(sse02.irq);
-#    endif                             /* CONFIG_TIVA_ADC0_SSE2 */
-
+#    endif
 #    ifdef CONFIG_TIVA_ADC0_SSE3
-  ret = irq_attach(sse03.irq, (xcpt_t) adc0_sse3_interrupt);
+  ret = irq_attach(sse03.irq, (xcpt_t)adc0_sse3_interrupt);
   if (ret < 0)
     {
-      adbg("ERROR: Failed to attach IRQ %d: %d\n", sse03.irq, ret);
+      adcdbg("ERROR: Failed to attach IRQ %d: %d\n", sse03.irq, ret);
       return;
     }
-
   up_enable_irq(sse03.irq);
-#    endif                             /* CONFIG_TIVA_ADC0_SSE3 */
+#    endif
+#  endif
 };
-#  endif                               /* CONFIG_TIVA_ADC0 */
 
-#  ifdef CONFIG_TIVA_ADC1
 static void tiva_adc1_assign_interrupts(void)
 {
+#  ifdef CONFIG_TIVA_ADC1
   uint32_t ret = 0;
 #    ifdef CONFIG_TIVA_ADC1_SSE0
-  ret = irq_attach(sse10.irq, (xcpt_t) adc1_sse0_interrupt);
+  ret = irq_attach(sse10.irq, (xcpt_t)adc1_sse0_interrupt);
   if (ret < 0)
     {
-      adbg("ERROR: Failed to attach IRQ %d: %d\n", sse10.irq, ret);
+      adcdbg("ERROR: Failed to attach IRQ %d: %d\n", sse10.irq, ret);
       return;
     }
-
   up_enable_irq(sse10.irq);
-#    endif                             /* CONFIG_TIVA_ADC1_SSE0 */
-
+#    endif
 #    ifdef CONFIG_TIVA_ADC1_SSE1
-  ret = irq_attach(sse11.irq, (xcpt_t) adc1_sse1_interrupt);
+  ret = irq_attach(sse11.irq, (xcpt_t)adc1_sse1_interrupt);
   if (ret < 0)
     {
-      adbg("ERROR: Failed to attach IRQ %d: %d\n", sse11.irq, ret);
+      adcdbg("ERROR: Failed to attach IRQ %d: %d\n", sse11.irq, ret);
       return;
     }
-
   up_enable_irq(sse11.irq);
-#    endif                             /* CONFIG_TIVA_ADC1_SSE1 */
-
+#    endif
 #    ifdef CONFIG_TIVA_ADC1_SSE2
-  ret = irq_attach(sse12.irq, (xcpt_t) adc1_sse2_interrupt);
+  ret = irq_attach(sse12.irq, (xcpt_t)adc1_sse2_interrupt);
   if (ret < 0)
     {
-      adbg("ERROR: Failed to attach IRQ %d: %d\n", sse12.irq, ret);
+      adcdbg("ERROR: Failed to attach IRQ %d: %d\n", sse12.irq, ret);
       return;
     }
-
   up_enable_irq(sse12.irq);
-#    endif                             /* CONFIG_TIVA_ADC1_SSE2 */
-
+#    endif
 #    ifdef CONFIG_TIVA_ADC1_SSE3
-  ret = irq_attach(sse13.irq, (xcpt_t) adc1_sse3_interrupt);
+  ret = irq_attach(sse13.irq, (xcpt_t)adc1_sse3_interrupt);
   if (ret < 0)
     {
-      adbg("ERROR: Failed to attach IRQ %d: %d\n", sse13.irq, ret);
+      adcdbg("ERROR: Failed to attach IRQ %d: %d\n", sse13.irq, ret);
       return;
     }
-
   up_enable_irq(sse13.irq);
-#    endif                             /* CONFIG_TIVA_ADC1_SSE3 */
+#    endif
+#  endif
 };
-#  endif                               /* CONFIG_TIVA_ADC1 */
+#endif /* TIVA_ADC_HAVE_INTERRUPTS */
 
 /* Sample sequencer interrupt declaration ********************************/
 
+#ifdef TIVA_ADC_HAVE_INTERRUPTS
 #  ifdef CONFIG_TIVA_ADC0
 #    ifdef CONFIG_TIVA_ADC0_SSE0
 static void adc0_sse0_interrupt(int irq, void *context)
 {
-  uint8_t fifo_count = 0;
+  int ret;
+
+  DEBUGASSERT((sse00.ena == true) &&
+              (adc_common.sse[SSE_IDX(0, 0)] == true));
+
+  /* disable further  interrupts. Interrupts will be re-enabled
+   * after the worker thread executes.
+   */
+
   sse_int_state(&adc0, 0, TIVA_ADC_DISABLE);
+
+  /* Clear interrupt status */
+
   sse_clear_int(&adc0, 0);
-  tiva_adc_lock(&adc0, 0);
-  while (!(tiva_adc_getreg(&adc0, TIVA_ADC_BASE(0) + TIVA_ADC_SSFSTAT(0)) &
-          ADC_SSFSTAT_EMPTY) && fifo_count++ < SSE_MAX_STEP)
+
+  /* Transfer processing to the worker thread.  Since interrupts are
+   * disabled while the work is pending, no special action should be
+   * required to protected the work queue.
+   */
+
+  DEBUGASSERT(sse00.work.worker == NULL);
+  ret = work_queue(HPWORK, &sse00.work, tiva_adc_read, &sse00, 0);
+  if (ret != 0)
     {
-      uint32_t data =
-        tiva_adc_getreg(&adc0, TIVA_ADC_BASE(0) + TIVA_ADC_SSFIFO(0));
-      (void)adc_receive(adc0.dev, GET_AIN(0, 0, fifo_count), data);
+      adcdbg("ERROR: Failed to queue work: %d\n", ret);
     }
-
-  sse_int_state(&adc0, 0, TIVA_ADC_ENABLE);
-  tiva_adc_unlock(&adc0, 0);
 }
-#    endif                             /* CONFIG_TIVA_ADC0_SSE0 */
-
+#    endif
 #    ifdef CONFIG_TIVA_ADC0_SSE1
 static void adc0_sse1_interrupt(int irq, void *context)
 {
-  uint8_t fifo_count = 0;
+  int ret;
+
+  DEBUGASSERT((sse01.ena == true) &&
+              (adc_common.sse[SSE_IDX(0, 1)] == true));
+
   sse_int_state(&adc0, 1, TIVA_ADC_DISABLE);
   sse_clear_int(&adc0, 1);
-  tiva_adc_lock(&adc0, 1);
-  while (!(tiva_adc_getreg(&adc0, TIVA_ADC_BASE(0) + TIVA_ADC_SSFSTAT(1)) &
-          ADC_SSFSTAT_EMPTY) && fifo_count++ < SSE_MAX_STEP)
+  DEBUGASSERT(sse01.work.worker == NULL);
+  ret = work_queue(HPWORK, &sse01.work, tiva_adc_read, &sse01, 0);
+  if (ret != 0)
     {
-      uint32_t data =
-        tiva_adc_getreg(&adc0, TIVA_ADC_BASE(0) + TIVA_ADC_SSFIFO(1));
-      (void)adc_receive(adc0.dev, GET_AIN(0, 1, fifo_count), data);
+      adcdbg("ERROR: Failed to queue work: %d ADC.SSE: %d.%d\n",
+             ret, adc0.devno, sse01.num);
     }
-
-  sse_int_state(&adc0, 1, TIVA_ADC_ENABLE);
-  tiva_adc_unlock(&adc0, 1);
 }
-#    endif                             /* CONFIG_TIVA_ADC0_SSE1 */
-
+#    endif
 #    ifdef CONFIG_TIVA_ADC0_SSE2
 static void adc0_sse2_interrupt(int irq, void *context)
 {
-  uint8_t fifo_count = 0;
+  int ret;
+
+  DEBUGASSERT((sse02.ena == true) &&
+              (adc_common.sse[SSE_IDX(0, 2)] == true));
+
   sse_int_state(&adc0, 2, TIVA_ADC_DISABLE);
   sse_clear_int(&adc0, 2);
-  tiva_adc_lock(&adc0, 2);
-  while (!(tiva_adc_getreg(&adc0, TIVA_ADC_BASE(0) + TIVA_ADC_SSFSTAT(2)) &
-          ADC_SSFSTAT_EMPTY) && fifo_count++ < SSE_MAX_STEP)
+  DEBUGASSERT(sse02.work.worker == NULL);
+  ret = work_queue(HPWORK, &sse02.work, tiva_adc_read, &sse02, 0);
+  if (ret != 0)
     {
-      uint32_t data =
-        tiva_adc_getreg(&adc0, TIVA_ADC_BASE(0) + TIVA_ADC_SSFIFO(2));
-      (void)adc_receive(adc0.dev, GET_AIN(0, 2, fifo_count), data);
+      adcdbg("ERROR: Failed to queue work: %d ADC.SSE: %d.%d\n",
+             ret, adc0.devno, sse02.num);
     }
-
-  sse_int_state(&adc0, 2, TIVA_ADC_ENABLE);
-  tiva_adc_unlock(&adc0, 2);
 }
-#    endif                             /* CONFIG_TIVA_ADC0_SSE2 */
-
+#    endif
 #    ifdef CONFIG_TIVA_ADC0_SSE3
 static void adc0_sse3_interrupt(int irq, void *context)
 {
-  uint8_t fifo_count = 0;
+  int ret;
+
+  DEBUGASSERT((sse03.ena == true) &&
+              (adc_common.sse[SSE_IDX(0, 3)] == true));
+
   sse_int_state(&adc0, 3, TIVA_ADC_DISABLE);
   sse_clear_int(&adc0, 3);
-  tiva_adc_lock(&adc0, 3);
-  while (!(tiva_adc_getreg(&adc0, TIVA_ADC_BASE(0) + TIVA_ADC_SSFSTAT(3)) &
-          ADC_SSFSTAT_EMPTY) && fifo_count++ < SSE_MAX_STEP)
+  DEBUGASSERT(sse03.work.worker == NULL);
+  ret = work_queue(HPWORK, &sse03.work, tiva_adc_read, &sse03, 0);
+  if (ret != 0)
     {
-      uint32_t data =
-        tiva_adc_getreg(&adc0, TIVA_ADC_BASE(0) + TIVA_ADC_SSFIFO(3));
-      (void)adc_receive(adc0.dev, GET_AIN(0, 3, fifo_count), data);
+      adcdbg("ERROR: Failed to queue work: %d ADC.SSE: %d.%d\n",
+             ret, adc0.devno, sse03.num);
     }
-
-  sse_int_state(&adc0, 3, TIVA_ADC_ENABLE);
-  tiva_adc_unlock(&adc0, 3);
 }
-#    endif                             /* CONFIG_TIVA_ADC0_SSE3 */
-#  endif                               /* CONFIG_TIVA_ADC0 */
+#    endif
+#  endif /* CONFIG_TIVA_ADC0 */
 
 #  ifdef CONFIG_TIVA_ADC1
 #    ifdef CONFIG_TIVA_ADC1_SSE0
 static void adc1_sse0_interrupt(int irq, void *context)
 {
-  uint8_t fifo_count = 0;
+  int ret;
+
+  DEBUGASSERT((sse10.ena == true) &&
+              (adc_common.sse[SSE_IDX(1, 0)] == true));
+
   sse_int_state(&adc1, 0, TIVA_ADC_DISABLE);
   sse_clear_int(&adc1, 0);
-  tiva_adc_lock(&adc1, 0);
-  while (!(tiva_adc_getreg(&adc1, TIVA_ADC_BASE(1) + TIVA_ADC_SSFSTAT(0)) &
-          ADC_SSFSTAT_EMPTY) && fifo_count++ < SSE_MAX_STEP)
+  DEBUGASSERT(sse10.work.worker == NULL);
+  ret = work_queue(HPWORK, &sse10.work, tiva_adc_read, &sse10, 0);
+  if (ret != 0)
     {
-      uint32_t data =
-        tiva_adc_getreg(&adc1, TIVA_ADC_BASE(1) + TIVA_ADC_SSFIFO(0));
-      (void)adc_receive(adc1.dev, GET_AIN(1, 0, fifo_count), data);
+      adcdbg("ERROR: Failed to queue work: %d ADC.SSE: %d.%d\n",
+             ret, adc1.devno, sse10.num);
     }
-
-  sse_int_state(&adc1, 0, TIVA_ADC_ENABLE);
-  tiva_adc_unlock(&adc1, 0);
 }
-#    endif                             /* CONFIG_TIVA_ADC1_SSE0 */
-
+#    endif
 #    ifdef CONFIG_TIVA_ADC1_SSE1
 static void adc1_sse1_interrupt(int irq, void *context)
 {
-  uint8_t fifo_count = 0;
+  int ret;
+
+  DEBUGASSERT((sse11.ena == true) &&
+              (adc_common.sse[SSE_IDX(1, 1)] == true));
+
   sse_int_state(&adc1, 1, TIVA_ADC_DISABLE);
   sse_clear_int(&adc1, 1);
-  tiva_adc_lock(&adc1, 1);
-  while (!(tiva_adc_getreg(&adc1, TIVA_ADC_BASE(1) + TIVA_ADC_SSFSTAT(1)) &
-          ADC_SSFSTAT_EMPTY) && fifo_count++ < SSE_MAX_STEP)
+  DEBUGASSERT(sse11.work.worker == NULL);
+  ret = work_queue(HPWORK, &sse11.work, tiva_adc_read, &sse11, 0);
+  if (ret != 0)
     {
-      uint32_t data =
-        tiva_adc_getreg(&adc1, TIVA_ADC_BASE(1) + TIVA_ADC_SSFIFO(1));
-      (void)adc_receive(adc1.dev, GET_AIN(1, 1, fifo_count), data);
+      adcdbg("ERROR: Failed to queue work: %d ADC.SSE: %d.%d\n",
+             ret, adc1.devno, sse11.num);
     }
-
-  sse_int_state(&adc1, 1, TIVA_ADC_ENABLE);
-  tiva_adc_unlock(&adc1, 1);
 }
-#    endif                             /* CONFIG_TIVA_ADC1_SSE1 */
-
+#    endif
 #    ifdef CONFIG_TIVA_ADC1_SSE2
 static void adc1_sse2_interrupt(int irq, void *context)
 {
-  uint8_t fifo_count = 0;
+  int ret;
+
+  DEBUGASSERT((sse12.ena == true) &&
+              (adc_common.sse[SSE_IDX(1, 2)] == true));
+
   sse_int_state(&adc1, 2, TIVA_ADC_DISABLE);
   sse_clear_int(&adc1, 2);
-  tiva_adc_lock(&adc1, 2);
-  while (!(tiva_adc_getreg(&adc1, TIVA_ADC_BASE(1) + TIVA_ADC_SSFSTAT(2)) &
-          ADC_SSFSTAT_EMPTY) && fifo_count++ < SSE_MAX_STEP)
+  DEBUGASSERT(sse12.work.worker == NULL);
+  ret = work_queue(HPWORK, &sse12.work, tiva_adc_read, &sse12, 0);
+  if (ret != 0)
     {
-      uint32_t data =
-        tiva_adc_getreg(&adc1, TIVA_ADC_BASE(1) + TIVA_ADC_SSFIFO(2));
-      (void)adc_receive(adc1.dev, GET_AIN(1, 2, fifo_count), data);
+      adcdbg("ERROR: Failed to queue work: %d ADC.SSE: %d.%d\n",
+             ret, adc1.devno, sse12.num);
     }
-
-  sse_int_state(&adc1, 2, TIVA_ADC_ENABLE);
-  tiva_adc_unlock(&adc1, 2);
 }
-#    endif                             /* CONFIG_TIVA_ADC1_SSE2 */
-
+#    endif
 #    ifdef CONFIG_TIVA_ADC1_SSE3
 static void adc1_sse3_interrupt(int irq, void *context)
 {
-  uint8_t fifo_count = 0;
+  int ret;
+
+  DEBUGASSERT((sse13.ena == true) &&
+              (adc_common.sse[SSE_IDX(1, 3)] == true));
+
   sse_int_state(&adc1, 3, TIVA_ADC_DISABLE);
   sse_clear_int(&adc1, 3);
-  tiva_adc_lock(&adc1, 3);
-  while (!(tiva_adc_getreg(&adc1, TIVA_ADC_BASE(1) + TIVA_ADC_SSFSTAT(3)) &
-          ADC_SSFSTAT_EMPTY) && fifo_count++ < SSE_MAX_STEP)
+  DEBUGASSERT(sse13.work.worker == NULL);
+  ret = work_queue(HPWORK, &sse13.work, tiva_adc_read, &sse13, 0);
+  if (ret != 0)
     {
-      uint32_t data =
-        tiva_adc_getreg(&adc1, TIVA_ADC_BASE(1) + TIVA_ADC_SSFIFO(3));
-      (void)adc_receive(adc1.dev, GET_AIN(1, 3, fifo_count), data);
+      adcdbg("ERROR: Failed to queue work: %d ADC.SSE: %d.%d\n",
+             ret, adc1.devno, sse13.num);
     }
-
-  sse_int_state(&adc1, 3, TIVA_ADC_ENABLE);
-  tiva_adc_unlock(&adc1, 3);
 }
-#    endif                             /* CONFIG_TIVA_ADC1_SSE3 */
-#  endif                               /* CONFIG_TIVA_ADC1 */
+#    endif
+#  endif /* CONFIG_TIVA_ADC1 */
+#endif /* TIVA_ADC_HAVE_INTERRUPTS */
 
 /* Channel assignment *******************************************************/
 
-#  ifdef CONFIG_TIVA_ADC0
+#ifdef CONFIG_TIVA_ADC0
 static void tiva_adc0_assign_channels(void)
 {
-#    ifdef CONFIG_TIVA_ADC0_SSE0
+#  ifdef CONFIG_TIVA_ADC0_SSE0
   adc0_sse0_chn_cfg();
-#    endif
-
-#    ifdef CONFIG_TIVA_ADC0_SSE1
+#  endif
+#  ifdef CONFIG_TIVA_ADC0_SSE1
   adc0_sse1_chn_cfg();
-#    endif
-
-#    ifdef CONFIG_TIVA_ADC0_SSE2
+#  endif
+#  ifdef CONFIG_TIVA_ADC0_SSE2
   adc0_sse2_chn_cfg();
-#    endif
-
-#    ifdef CONFIG_TIVA_ADC0_SSE3
+#  endif
+#  ifdef CONFIG_TIVA_ADC0_SSE3
   adc0_sse3_chn_cfg();
-#    endif
+#  endif
 }
-#  endif                               /* CONFIG_TIVA_ADC0 */
+#endif
 
-#  ifdef CONFIG_TIVA_ADC1
+#ifdef CONFIG_TIVA_ADC1
 static void tiva_adc1_assign_channels(void)
 {
-#    ifdef CONFIG_TIVA_ADC1_SSE0
+#  ifdef CONFIG_TIVA_ADC1_SSE0
   adc1_sse0_chn_cfg();
-#    endif
-
-#    ifdef CONFIG_TIVA_ADC1_SSE1
+#  endif
+#  ifdef CONFIG_TIVA_ADC1_SSE1
   adc1_sse1_chn_cfg();
-#    endif
-
-#    ifdef CONFIG_TIVA_ADC1_SSE2
+#  endif
+#  ifdef CONFIG_TIVA_ADC1_SSE2
   adc1_sse2_chn_cfg();
-#    endif
-
-#    ifdef CONFIG_TIVA_ADC1_SSE3
+#  endif
+#  ifdef CONFIG_TIVA_ADC1_SSE3
   adc1_sse3_chn_cfg();
-#    endif
+#  endif
 }
-#  endif                               /* CONFIG_TIVA_ADC1 */
+#endif
 
 /* Channel config ***********************************************************/
 
-#  ifdef CONFIG_TIVA_ADC0
-#    ifdef CONFIG_TIVA_ADC0_SSE0
+#ifdef CONFIG_TIVA_ADC0
+#  ifdef CONFIG_TIVA_ADC0_SSE0
 static void adc0_sse0_chn_cfg(void)
 {
   uint32_t chncfg = 0;
-#      ifdef CONFIG_TIVA_ADC0_SSE0_STEP0
-#        ifdef CONFIG_TIVA_ADC0_SSE0_STEP0_TS
+#    ifdef CONFIG_TIVA_ADC0_SSE0_STEP0
+#      ifdef CONFIG_TIVA_ADC0_SSE0_STEP0_TS
   chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
-#        else                          /* ADC_SSCTL_IE */
+#      else
   chncfg = ADC_SSCTL_IE;
-#        endif                         /* CONFIG_TIVA_ADC0_SSE0_STEP0_TS */
-
+#      endif
   tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC0_SSE0_STEP0_AIN));
   sse_register_chn(&adc0, 0, 0, CONFIG_TIVA_ADC0_SSE0_STEP0_AIN);
   sse_differential(&adc0, 0, 0, 0);
 #        if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC0_SSE0_TRIGGER == ADC_EMUX_PROC)
   sse_sample_hold_time(&adc0, 0, 0, ADC_SSTH_SHOLD_16);
-#        endif                         /* (CONFIG_TIVA_ADC0_SSE0_TRIGGER ==
-                                        * ADC_EMUX_PROC) && defined
-                                        * (CONFIG_ARCH_CHIP_TM4C129) */
-
+#        endif
 #        ifndef CONFIG_TIVA_ADC0_SSE0_STEP1
   sse_step_cfg(&adc0, 0, 0, chncfg | ADC_SSCTL_END);
-
-#        else                          /* CONFIG_TIVA_ADC0_SSE0_STEP1 */
+#        else
   sse_step_cfg(&adc0, 0, 0, chncfg);
-#        endif                         /* !CONFIG_TIVA_ADC0_SSE0_STEP1 */
-
-#        ifdef CONFIG_TIVA_ADC0_SSE0_STEP1
-#          ifdef CONFIG_TIVA_ADC0_SSE0_STEP1_TS
+#        endif
+#      ifdef CONFIG_TIVA_ADC0_SSE0_STEP1
+#        ifdef CONFIG_TIVA_ADC0_SSE0_STEP1_TS
   chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
-#          else                        /* ADC_SSCTL_IE */
+#        else
   chncfg = ADC_SSCTL_IE;
-#          endif                       /* CONFIG_TIVA_ADC0_SSE0_STEP1_TS */
-
+#        endif
   tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC0_SSE0_STEP1_AIN));
   sse_register_chn(&adc0, 0, 1, CONFIG_TIVA_ADC0_SSE0_STEP1_AIN);
   sse_differential(&adc0, 0, 1, 0);
 #          if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC0_SSE0_TRIGGER == ADC_EMUX_PROC)
   sse_sample_hold_time(&adc0, 0, 1, ADC_SSTH_SHOLD_16);
-#          endif                       /* (CONFIG_TIVA_ADC0_SSE0_TRIGGER ==
-                                        * ADC_EMUX_PROC) && defined
-                                        * (CONFIG_ARCH_CHIP_TM4C129) */
-
+#          endif
 #          ifndef CONFIG_TIVA_ADC0_SSE0_STEP2
   sse_step_cfg(&adc0, 0, 1, chncfg | ADC_SSCTL_END);
-
-#          else                        /* CONFIG_TIVA_ADC0_SSE0_STEP2 */
+#          else
   sse_step_cfg(&adc0, 0, 1, chncfg);
-#          endif                       /* !CONFIG_TIVA_ADC0_SSE0_STEP2 */
-
-#          ifdef CONFIG_TIVA_ADC0_SSE0_STEP2
-#            ifdef CONFIG_TIVA_ADC0_SSE0_STEP2_TS
+#          endif
+#        ifdef CONFIG_TIVA_ADC0_SSE0_STEP2
+#          ifdef CONFIG_TIVA_ADC0_SSE0_STEP2_TS
   chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
-#            else                      /* ADC_SSCTL_IE */
+#          else
   chncfg = ADC_SSCTL_IE;
-#            endif                     /* CONFIG_TIVA_ADC0_SSE0_STEP2_TS */
-
+#          endif
   tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC0_SSE0_STEP2_AIN));
   sse_register_chn(&adc0, 0, 2, CONFIG_TIVA_ADC0_SSE0_STEP2_AIN);
   sse_differential(&adc0, 0, 2, 0);
 #            if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC0_SSE0_TRIGGER == ADC_EMUX_PROC)
   sse_sample_hold_time(&adc0, 0, 2, ADC_SSTH_SHOLD_16);
-#            endif                     /* (CONFIG_TIVA_ADC0_SSE0_TRIGGER ==
-                                        * ADC_EMUX_PROC) && defined
-                                        * (CONFIG_ARCH_CHIP_TM4C129) */
-
+#            endif
 #            ifndef CONFIG_TIVA_ADC0_SSE0_STEP3
   sse_step_cfg(&adc0, 0, 2, chncfg | ADC_SSCTL_END);
-
-#            else                      /* CONFIG_TIVA_ADC0_SSE0_STEP3 */
+#            else
   sse_step_cfg(&adc0, 0, 2, chncfg);
-#            endif                     /* !CONFIG_TIVA_ADC0_SSE0_STEP3 */
-
-#            ifdef CONFIG_TIVA_ADC0_SSE0_STEP3
-#              ifdef CONFIG_TIVA_ADC0_SSE0_STEP3_TS
+#            endif
+#          ifdef CONFIG_TIVA_ADC0_SSE0_STEP3
+#            ifdef CONFIG_TIVA_ADC0_SSE0_STEP3_TS
   chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
-#              else                    /* ADC_SSCTL_IE */
+#            else
   chncfg = ADC_SSCTL_IE;
-#              endif                   /* CONFIG_TIVA_ADC0_SSE0_STEP3_TS */
+#            endif
   tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC0_SSE0_STEP3_AIN));
   sse_register_chn(&adc0, 0, 3, CONFIG_TIVA_ADC0_SSE0_STEP3_AIN);
   sse_differential(&adc0, 0, 3, 0);
 #              if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC0_SSE0_TRIGGER == ADC_EMUX_PROC)
   sse_sample_hold_time(&adc0, 0, 3, ADC_SSTH_SHOLD_16);
-#              endif                   /* (CONFIG_TIVA_ADC0_SSE0_TRIGGER ==
-                                        * ADC_EMUX_PROC) && defined
-                                        * (CONFIG_ARCH_CHIP_TM4C129) */
-
+#              endif
 #              ifndef CONFIG_TIVA_ADC0_SSE0_STEP4
   sse_step_cfg(&adc0, 0, 3, chncfg | ADC_SSCTL_END);
-#              else                    /* CONFIG_TIVA_ADC0_SSE0_STEP4 */
+#              else
   sse_step_cfg(&adc0, 0, 3, chncfg);
-#              endif                   /* !CONFIG_TIVA_ADC0_SSE0_STEP4 */
-
-#              ifdef CONFIG_TIVA_ADC0_SSE0_STEP4
-#                ifdef CONFIG_TIVA_ADC0_SSE0_STEP4_TS
+#              endif
+#            ifdef CONFIG_TIVA_ADC0_SSE0_STEP4
+#              ifdef CONFIG_TIVA_ADC0_SSE0_STEP4_TS
   chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
-#                else                  /* ADC_SSCTL_IE */
+#              else
   chncfg = ADC_SSCTL_IE;
-#                endif                 /* CONFIG_TIVA_ADC0_SSE0_STEP4_TS */
-
+#              endif
   tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC0_SSE0_STEP4_AIN));
   sse_register_chn(&adc0, 0, 4, CONFIG_TIVA_ADC0_SSE0_STEP4_AIN);
   sse_differential(&adc0, 0, 4, 0);
 #                if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC0_SSE0_TRIGGER == ADC_EMUX_PROC)
   sse_sample_hold_time(&adc0, 0, 4, ADC_SSTH_SHOLD_16);
-#                endif                 /* (CONFIG_TIVA_ADC0_SSE0_TRIGGER ==
-                                        * ADC_EMUX_PROC) && defined
-                                        * (CONFIG_ARCH_CHIP_TM4C129) */
-
+#                endif
 #                ifndef CONFIG_TIVA_ADC0_SSE0_STEP5
   sse_step_cfg(&adc0, 0, 4, chncfg | ADC_SSCTL_END);
-
-#                else                  /* CONFIG_TIVA_ADC0_SSE0_STEP5 */
+#                else
   sse_step_cfg(&adc0, 0, 4, chncfg);
-#                endif                 /* !CONFIG_TIVA_ADC0_SSE0_STEP5 */
-
-#                ifdef CONFIG_TIVA_ADC0_SSE0_STEP5
-#                  ifdef CONFIG_TIVA_ADC0_SSE0_STEP5_TS
+#                endif
+#              ifdef CONFIG_TIVA_ADC0_SSE0_STEP5
+#                ifdef CONFIG_TIVA_ADC0_SSE0_STEP5_TS
   chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
-#                  else                /* ADC_SSCTL_IE */
+#                else
   chncfg = ADC_SSCTL_IE;
-#                  endif               /* CONFIG_TIVA_ADC0_SSE0_STEP5_TS */
+#                endif
   tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC0_SSE0_STEP5_AIN));
   sse_register_chn(&adc0, 0, 5, CONFIG_TIVA_ADC0_SSE0_STEP5_AIN);
   sse_differential(&adc0, 0, 5, 0);
 #                  if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC0_SSE0_TRIGGER == ADC_EMUX_PROC)
   sse_sample_hold_time(&adc0, 0, 5, ADC_SSTH_SHOLD_16);
-#                  endif               /* (CONFIG_TIVA_ADC0_SSE0_TRIGGER ==
-                                        * ADC_EMUX_PROC) && defined
-                                        * (CONFIG_ARCH_CHIP_TM4C129) */
-
+#                  endif
 #                  ifndef CONFIG_TIVA_ADC0_SSE0_STEP6
   sse_step_cfg(&adc0, 0, 5, chncfg | ADC_SSCTL_END);
-
-#                  else                /* CONFIG_TIVA_ADC0_SSE0_STEP6 */
+#                  else
   sse_step_cfg(&adc0, 0, 5, chncfg);
-#                  endif               /* !CONFIG_TIVA_ADC0_SSE0_STEP6 */
-
-#                  ifdef CONFIG_TIVA_ADC0_SSE0_STEP6
-#                    ifdef CONFIG_TIVA_ADC0_SSE0_STEP6_TS
+#                  endif
+#                ifdef CONFIG_TIVA_ADC0_SSE0_STEP6
+#                  ifdef CONFIG_TIVA_ADC0_SSE0_STEP6_TS
   chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
-#                    else              /* ADC_SSCTL_IE */
+#                  else
   chncfg = ADC_SSCTL_IE;
-#                    endif             /* CONFIG_TIVA_ADC0_SSE0_STEP6_TS */
-
+#                  endif
   tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC0_SSE0_STEP6_AIN));
   sse_register_chn(&adc0, 0, 6, CONFIG_TIVA_ADC0_SSE0_STEP6_AIN);
   sse_differential(&adc0, 0, 6, 0);
 #                    if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC0_SSE0_TRIGGER == ADC_EMUX_PROC)
   sse_sample_hold_time(&adc0, 0, 6, ADC_SSTH_SHOLD_16);
-#                    endif             /* (CONFIG_TIVA_ADC0_SSE0_TRIGGER ==
-                                        * ADC_EMUX_PROC) && defined
-                                        * (CONFIG_ARCH_CHIP_TM4C129) */
-
+#                    endif
 #                    ifndef CONFIG_TIVA_ADC0_SSE0_STEP7
   sse_step_cfg(&adc0, 0, 6, chncfg | ADC_SSCTL_END);
-
-#                    else              /* CONFIG_TIVA_ADC0_SSE0_STEP7 */
+#                    else
   sse_step_cfg(&adc0, 0, 6, chncfg);
-#                    endif             /* !CONFIG_TIVA_ADC0_SSE0_STEP7 */
-
-#                    ifdef CONFIG_TIVA_ADC0_SSE0_STEP7
-#                      ifdef CONFIG_TIVA_ADC0_SSE0_STEP7_TS
+#                    endif
+#                  ifdef CONFIG_TIVA_ADC0_SSE0_STEP7
+#                    ifdef CONFIG_TIVA_ADC0_SSE0_STEP7_TS
   chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
-#                      else            /* ADC_SSCTL_IE */
+#                    else
   chncfg = ADC_SSCTL_IE;
-#                      endif           /* CONFIG_TIVA_ADC0_SSE0_STEP7_TS */
-
+#                    endif
   tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC0_SSE0_STEP7_AIN));
   sse_register_chn(&adc0, 0, 7, CONFIG_TIVA_ADC0_SSE0_STEP7_AIN);
   sse_differential(&adc0, 0, 7, 0);
 #                      if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC0_SSE0_TRIGGER == ADC_EMUX_PROC)
   sse_sample_hold_time(&adc0, 0, 7, ADC_SSTH_SHOLD_16);
-#                      endif           /* (CONFIG_TIVA_ADC0_SSE0_TRIGGER ==
-                                        * ADC_EMUX_PROC) && defined
-                                        * (CONFIG_ARCH_CHIP_TM4C129) */
-
+#                      endif
   sse_step_cfg(&adc0, 0, 7, chncfg | ADC_SSCTL_END);
-
-#                    endif             /* CONFIG_TIVA_ADC0_SSE0_STEP7 */
-#                  endif               /* CONFIG_TIVA_ADC0_SSE0_STEP6 */
-#                endif                 /* CONFIG_TIVA_ADC0_SSE0_STEP5 */
-#              endif                   /* CONFIG_TIVA_ADC0_SSE0_STEP4 */
-#            endif                     /* CONFIG_TIVA_ADC0_SSE0_STEP3 */
-#          endif                       /* CONFIG_TIVA_ADC0_SSE0_STEP2 */
-#        endif                         /* CONFIG_TIVA_ADC0_SSE0_STEP1 */
-#      endif                           /* CONFIG_TIVA_ADC0_SSE0_STEP0 */
+#                  endif /* CONFIG_TIVA_ADC0_SSE0_STEP7 */
+#                endif /* CONFIG_TIVA_ADC0_SSE0_STEP6 */
+#              endif /* CONFIG_TIVA_ADC0_SSE0_STEP5 */
+#            endif /* CONFIG_TIVA_ADC0_SSE0_STEP4 */
+#          endif /* CONFIG_TIVA_ADC0_SSE0_STEP3 */
+#        endif /* CONFIG_TIVA_ADC0_SSE0_STEP2 */
+#      endif /* CONFIG_TIVA_ADC0_SSE0_STEP1 */
+#    endif /* CONFIG_TIVA_ADC0_SSE0_STEP0 */
 }
-#    endif                             /* CONFIG_TIVA_ADC0_SSE0 */
+#  endif /* CONFIG_TIVA_ADC0_SSE0 */
 
-#    ifdef CONFIG_TIVA_ADC0_SSE1
+#  ifdef CONFIG_TIVA_ADC0_SSE1
 static void adc0_sse1_chn_cfg(void)
 {
   uint32_t chncfg = 0;
-#      ifdef CONFIG_TIVA_ADC0_SSE1_STEP0
-#        ifdef CONFIG_TIVA_ADC0_SSE1_STEP0_TS
+#    ifdef CONFIG_TIVA_ADC0_SSE1_STEP0
+#      ifdef CONFIG_TIVA_ADC0_SSE1_STEP0_TS
   chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
-#        else                          /* ADC_SSCTL_IE */
+#      else
   chncfg = ADC_SSCTL_IE;
-#        endif                         /* CONFIG_TIVA_ADC0_SSE1_STEP0_TS */
-
+#      endif
   tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC0_SSE1_STEP0_AIN));
   sse_register_chn(&adc0, 1, 0, CONFIG_TIVA_ADC0_SSE1_STEP0_AIN);
   sse_differential(&adc0, 1, 0, 0);
 #        if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC0_SSE1_TRIGGER == ADC_EMUX_PROC)
   sse_sample_hold_time(&adc0, 1, 0, ADC_SSTH_SHOLD_16);
-#        endif                         /* (CONFIG_TIVA_ADC0_SSE1_TRIGGER ==
-                                        * ADC_EMUX_PROC) && defined
-                                        * (CONFIG_ARCH_CHIP_TM4C129) */
-
+#        endif
 #        ifndef CONFIG_TIVA_ADC0_SSE1_STEP1
   sse_step_cfg(&adc0, 1, 0, chncfg | ADC_SSCTL_END);
-
-#        else                          /* CONFIG_TIVA_ADC0_SSE1_STEP1 */
+#        else
   sse_step_cfg(&adc0, 1, 0, chncfg);
-#        endif                         /* !CONFIG_TIVA_ADC0_SSE1_STEP1 */
-
-#        ifdef CONFIG_TIVA_ADC0_SSE1_STEP1
-#          ifdef CONFIG_TIVA_ADC0_SSE1_STEP1_TS
+#        endif
+#      ifdef CONFIG_TIVA_ADC0_SSE1_STEP1
+#        ifdef CONFIG_TIVA_ADC0_SSE1_STEP1_TS
   chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
-#          else                        /* ADC_SSCTL_IE */
+#        else
   chncfg = ADC_SSCTL_IE;
-#          endif                       /* CONFIG_TIVA_ADC0_SSE1_STEP1_TS */
+#        endif
   tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC0_SSE1_STEP1_AIN));
   sse_register_chn(&adc0, 1, 1, CONFIG_TIVA_ADC0_SSE1_STEP1_AIN);
   sse_differential(&adc0, 1, 1, 0);
 #          if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC0_SSE1_TRIGGER == ADC_EMUX_PROC)
   sse_sample_hold_time(&adc0, 1, 1, ADC_SSTH_SHOLD_16);
-#          endif                       /* (CONFIG_TIVA_ADC0_SSE1_TRIGGER ==
-                                        * ADC_EMUX_PROC) && defined
-                                        * (CONFIG_ARCH_CHIP_TM4C129) */
-
+#          endif
 #          ifndef CONFIG_TIVA_ADC0_SSE1_STEP2
   sse_step_cfg(&adc0, 1, 1, chncfg | ADC_SSCTL_END);
-
-#          else                        /* CONFIG_TIVA_ADC0_SSE1_STEP2 */
+#          else
   sse_step_cfg(&adc0, 1, 1, chncfg);
-#          endif                       /* !CONFIG_TIVA_ADC0_SSE1_STEP2 */
-
-#          ifdef CONFIG_TIVA_ADC0_SSE1_STEP2
-#            ifdef CONFIG_TIVA_ADC0_SSE1_STEP2_TS
+#          endif
+#        ifdef CONFIG_TIVA_ADC0_SSE1_STEP2
+#          ifdef CONFIG_TIVA_ADC0_SSE1_STEP2_TS
   chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
-#            else                      /* ADC_SSCTL_IE */
+#          else
   chncfg = ADC_SSCTL_IE;
-#            endif                     /* CONFIG_TIVA_ADC0_SSE1_STEP2_TS */
+#          endif
   tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC0_SSE1_STEP2_AIN));
   sse_register_chn(&adc0, 1, 2, CONFIG_TIVA_ADC0_SSE1_STEP2_AIN);
   sse_differential(&adc0, 1, 2, 0);
 #            if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC0_SSE1_TRIGGER == ADC_EMUX_PROC)
   sse_sample_hold_time(&adc0, 1, 2, ADC_SSTH_SHOLD_16);
-#            endif                     /* (CONFIG_TIVA_ADC0_SSE1_TRIGGER ==
-                                        * ADC_EMUX_PROC) && defined
-                                        * (CONFIG_ARCH_CHIP_TM4C129) */
-
+#            endif
 #            ifndef CONFIG_TIVA_ADC0_SSE1_STEP3
   sse_step_cfg(&adc0, 1, 2, chncfg | ADC_SSCTL_END);
-
-#            else                      /* CONFIG_TIVA_ADC0_SSE1_STEP3 */
+#            else
   sse_step_cfg(&adc0, 1, 2, chncfg);
-#            endif                     /* !CONFIG_TIVA_ADC0_SSE1_STEP3 */
-#            ifdef CONFIG_TIVA_ADC0_SSE1_STEP3
-#              ifdef CONFIG_TIVA_ADC0_SSE1_STEP3_TS
+#            endif
+#          ifdef CONFIG_TIVA_ADC0_SSE1_STEP3
+#            ifdef CONFIG_TIVA_ADC0_SSE1_STEP3_TS
   chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
-#              else                    /* ADC_SSCTL_IE */
+#            else
   chncfg = ADC_SSCTL_IE;
-#              endif                   /* CONFIG_TIVA_ADC0_SSE1_STEP3_TS */
-
+#            endif
   tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC0_SSE1_STEP3_AIN));
   sse_register_chn(&adc0, 1, 3, CONFIG_TIVA_ADC0_SSE1_STEP3_AIN);
   sse_differential(&adc0, 1, 3, 0);
 #              if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC0_SSE1_TRIGGER == ADC_EMUX_PROC)
   sse_sample_hold_time(&adc0, 1, 3, ADC_SSTH_SHOLD_16);
-#              endif                   /* (CONFIG_TIVA_ADC0_SSE1_TRIGGER ==
-                                        * ADC_EMUX_PROC) && defined
-                                        * (CONFIG_ARCH_CHIP_TM4C129) */
-
+#              endif
   sse_step_cfg(&adc0, 1, 3, chncfg | ADC_SSCTL_END);
-
-#            endif                     /* CONFIG_TIVA_ADC0_SSE1_STEP3 */
-#          endif                       /* CONFIG_TIVA_ADC0_SSE1_STEP2 */
-#        endif                         /* CONFIG_TIVA_ADC0_SSE1_STEP1 */
-#      endif                           /* CONFIG_TIVA_ADC0_SSE1_STEP0 */
+#          endif /* CONFIG_TIVA_ADC0_SSE1_STEP3 */
+#        endif /* CONFIG_TIVA_ADC0_SSE1_STEP2 */
+#      endif /* CONFIG_TIVA_ADC0_SSE1_STEP1 */
+#    endif /* CONFIG_TIVA_ADC0_SSE1_STEP0 */
 }
-#    endif                             /* CONFIG_TIVA_ADC0_SSE1 */
+#  endif /* CONFIG_TIVA_ADC0_SSE1 */
 
-#    ifdef CONFIG_TIVA_ADC0_SSE2
+#  ifdef CONFIG_TIVA_ADC0_SSE2
 static void adc0_sse2_chn_cfg(void)
 {
   uint32_t chncfg = 0;
-#      ifdef CONFIG_TIVA_ADC0_SSE2_STEP0
-#        ifdef CONFIG_TIVA_ADC0_SSE2_STEP0_TS
+#    ifdef CONFIG_TIVA_ADC0_SSE2_STEP0
+#      ifdef CONFIG_TIVA_ADC0_SSE2_STEP0_TS
   chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
-#        else                          /* ADC_SSCTL_IE */
+#      else
   chncfg = ADC_SSCTL_IE;
-#        endif                         /* CONFIG_TIVA_ADC0_SSE2_STEP0_TS */
-
+#      endif
   tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC0_SSE2_STEP0_AIN));
   sse_register_chn(&adc0, 2, 0, CONFIG_TIVA_ADC0_SSE2_STEP0_AIN);
   sse_differential(&adc0, 2, 0, 0);
 #        if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC0_SSE2_TRIGGER == ADC_EMUX_PROC)
   sse_sample_hold_time(&adc0, 2, 0, ADC_SSTH_SHOLD_16);
-#        endif                         /* (CONFIG_TIVA_ADC0_SSE2_TRIGGER ==
-                                        * ADC_EMUX_PROC) && defined
-                                        * (CONFIG_ARCH_CHIP_TM4C129) */
-
+#        endif
 #        ifndef CONFIG_TIVA_ADC0_SSE2_STEP1
   sse_step_cfg(&adc0, 2, 0, chncfg | ADC_SSCTL_END);
-
-#        else                          /* CONFIG_TIVA_ADC0_SSE2_STEP1 */
+#        else
   sse_step_cfg(&adc0, 2, 0, chncfg);
-#        endif                         /* !CONFIG_TIVA_ADC0_SSE2_STEP1 */
-
-#        ifdef CONFIG_TIVA_ADC0_SSE2_STEP1
-#          ifdef CONFIG_TIVA_ADC0_SSE2_STEP1_TS
+#        endif
+#      ifdef CONFIG_TIVA_ADC0_SSE2_STEP1
+#        ifdef CONFIG_TIVA_ADC0_SSE2_STEP1_TS
   chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
-#          else                        /* ADC_SSCTL_IE */
+#        else
   chncfg = ADC_SSCTL_IE;
-#          endif                       /* CONFIG_TIVA_ADC0_SSE2_STEP1_TS */
-
+#        endif
   tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC0_SSE2_STEP1_AIN));
   sse_register_chn(&adc0, 2, 1, CONFIG_TIVA_ADC0_SSE2_STEP1_AIN);
   sse_differential(&adc0, 2, 1, 0);
 #          if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC0_SSE2_TRIGGER == ADC_EMUX_PROC)
   sse_sample_hold_time(&adc0, 2, 1, ADC_SSTH_SHOLD_16);
-#          endif                       /* (CONFIG_TIVA_ADC0_SSE2_TRIGGER ==
-                                        * ADC_EMUX_PROC) && defined
-                                        * (CONFIG_ARCH_CHIP_TM4C129) */
-
+#          endif
 #          ifndef CONFIG_TIVA_ADC0_SSE2_STEP2
   sse_step_cfg(&adc0, 2, 1, chncfg | ADC_SSCTL_END);
-
-#          else                        /* CONFIG_TIVA_ADC0_SSE2_STEP2 */
+#          else
   sse_step_cfg(&adc0, 2, 1, chncfg);
-#          endif                       /* !CONFIG_TIVA_ADC0_SSE2_STEP2 */
-
-#          ifdef CONFIG_TIVA_ADC0_SSE2_STEP2
-#            ifdef CONFIG_TIVA_ADC0_SSE2_STEP2_TS
+#          endif
+#        ifdef CONFIG_TIVA_ADC0_SSE2_STEP2
+#          ifdef CONFIG_TIVA_ADC0_SSE2_STEP2_TS
   chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
-#            else                      /* ADC_SSCTL_IE */
+#          else
   chncfg = ADC_SSCTL_IE;
-#            endif                     /* CONFIG_TIVA_ADC0_SSE2_STEP2_TS */
-
+#          endif
   tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC0_SSE2_STEP2_AIN));
   sse_register_chn(&adc0, 2, 2, CONFIG_TIVA_ADC0_SSE2_STEP2_AIN);
   sse_differential(&adc0, 2, 2, 0);
 #            if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC0_SSE2_TRIGGER == ADC_EMUX_PROC)
   sse_sample_hold_time(&adc0, 2, 2, ADC_SSTH_SHOLD_16);
-#            endif                     /* (CONFIG_TIVA_ADC0_SSE2_TRIGGER ==
-                                        * ADC_EMUX_PROC) && defined
-                                        * (CONFIG_ARCH_CHIP_TM4C129) */
-
+#            endif
 #            ifndef CONFIG_TIVA_ADC0_SSE2_STEP3
   sse_step_cfg(&adc0, 2, 2, chncfg | ADC_SSCTL_END);
-
-#            else                      /* CONFIG_TIVA_ADC0_SSE2_STEP3 */
+#            else
   sse_step_cfg(&adc0, 2, 2, chncfg);
-#            endif                     /* !CONFIG_TIVA_ADC0_SSE2_STEP3 */
-
-#            ifdef CONFIG_TIVA_ADC0_SSE2_STEP3
-#              ifdef CONFIG_TIVA_ADC0_SSE2_STEP3_TS
+#            endif
+#          ifdef CONFIG_TIVA_ADC0_SSE2_STEP3
+#            ifdef CONFIG_TIVA_ADC0_SSE2_STEP3_TS
   chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
-#              else                    /* ADC_SSCTL_IE */
+#            else
   chncfg = ADC_SSCTL_IE;
-#              endif                   /* CONFIG_TIVA_ADC0_SSE2_STEP3_TS */
-
+#            endif
   tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC0_SSE2_STEP3_AIN));
   sse_register_chn(&adc0, 2, 3, CONFIG_TIVA_ADC0_SSE2_STEP3_AIN);
   sse_differential(&adc0, 2, 3, 0);
 #              if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC0_SSE2_TRIGGER == ADC_EMUX_PROC)
   sse_sample_hold_time(&adc0, 2, 3, ADC_SSTH_SHOLD_16);
-#              endif                   /* (CONFIG_TIVA_ADC0_SSE2_TRIGGER ==
-                                        * ADC_EMUX_PROC) && defined
-                                        * (CONFIG_ARCH_CHIP_TM4C129) */
-
+#              endif
   sse_step_cfg(&adc0, 2, 3, chncfg | ADC_SSCTL_END);
-
-#            endif                     /* CONFIG_TIVA_ADC0_SSE2_STEP3 */
-#          endif                       /* CONFIG_TIVA_ADC0_SSE2_STEP2 */
-#        endif                         /* CONFIG_TIVA_ADC0_SSE2_STEP1 */
-#      endif                           /* CONFIG_TIVA_ADC0_SSE2_STEP0 */
+#          endif /* CONFIG_TIVA_ADC0_SSE2_STEP3 */
+#        endif /* CONFIG_TIVA_ADC0_SSE2_STEP2 */
+#      endif /* CONFIG_TIVA_ADC0_SSE2_STEP1 */
+#    endif /* CONFIG_TIVA_ADC0_SSE2_STEP0 */
 }
-#    endif                             /* CONFIG_TIVA_ADC0_SSE2 */
+#  endif /* CONFIG_TIVA_ADC0_SSE2 */
 
-#    ifdef CONFIG_TIVA_ADC0_SSE3
+#  ifdef CONFIG_TIVA_ADC0_SSE3
 static void adc0_sse3_chn_cfg(void)
 {
   uint32_t chncfg = 0;
-#      ifdef CONFIG_TIVA_ADC0_SSE3_STEP0
-#        ifdef CONFIG_TIVA_ADC0_SSE3_STEP0_TS
+#    ifdef CONFIG_TIVA_ADC0_SSE3_STEP0
+#      ifdef CONFIG_TIVA_ADC0_SSE3_STEP0_TS
   chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
-#        else                          /* ADC_SSCTL_IE */
+#      else
   chncfg = ADC_SSCTL_IE;
-#        endif                         /* CONFIG_TIVA_ADC0_SSE3_STEP0_TS */
-
+#      endif
   tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC0_SSE3_STEP0_AIN));
   sse_register_chn(&adc0, 3, 0, CONFIG_TIVA_ADC0_SSE3_STEP0_AIN);
   sse_differential(&adc0, 3, 0, 0);
 #        if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC0_SSE3_TRIGGER == ADC_EMUX_PROC)
   sse_sample_hold_time(&adc0, 3, 0, ADC_SSTH_SHOLD_16);
-#        endif                         /* (CONFIG_TIVA_ADC0_SSE3_TRIGGER ==
-                                        * ADC_EMUX_PROC) && defined
-                                        * (CONFIG_ARCH_CHIP_TM4C129) */
-
+#        endif
   sse_step_cfg(&adc0, 3, 0, chncfg | ADC_SSCTL_END);
-
-#      endif                           /* CONFIG_TIVA_ADC0_SSE3_STEP0 */
+#    endif /* CONFIG_TIVA_ADC0_SSE3_STEP0 */
 }
-#    endif                             /* CONFIG_TIVA_ADC0_SSE3 */
+#  endif /* CONFIG_TIVA_ADC0_SSE3 */
+#endif /* CONFIG_TIVA_ADC0 */
 
-#  endif                               /* CONFIG_TIVA_ADC0 */
-
-#  ifdef CONFIG_TIVA_ADC1
-#    ifdef CONFIG_TIVA_ADC1_SSE0
+#ifdef CONFIG_TIVA_ADC1
+#  ifdef CONFIG_TIVA_ADC1_SSE0
 static void adc1_sse0_chn_cfg(void)
 {
   uint32_t chncfg = 0;
-#      ifdef CONFIG_TIVA_ADC1_SSE0_STEP0
-#        ifdef CONFIG_TIVA_ADC1_SSE0_STEP0_TS
+#    ifdef CONFIG_TIVA_ADC1_SSE0_STEP0
+#      ifdef CONFIG_TIVA_ADC1_SSE0_STEP0_TS
   chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
-#        else                          /* ADC_SSCTL_IE */
+#      else
   chncfg = ADC_SSCTL_IE;
-#        endif                         /* CONFIG_TIVA_ADC1_SSE0_STEP0_TS */
-
+#      endif
   tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC1_SSE0_STEP0_AIN));
   sse_register_chn(&adc1, 0, 0, CONFIG_TIVA_ADC1_SSE0_STEP0_AIN);
   sse_differential(&adc1, 0, 0, 0);
 #        if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC1_SSE0_TRIGGER == ADC_EMUX_PROC)
   sse_sample_hold_time(&adc1, 0, 0, ADC_SSTH_SHOLD_16);
-#        endif                         /* (CONFIG_TIVA_ADC1_SSE0_TRIGGER ==
-                                        * ADC_EMUX_PROC) && defined
-                                        * (CONFIG_ARCH_CHIP_TM4C129) */
-
+#        endif
 #        ifndef CONFIG_TIVA_ADC1_SSE0_STEP1
   sse_step_cfg(&adc1, 0, 0, chncfg | ADC_SSCTL_END);
-
-#        else                          /* CONFIG_TIVA_ADC1_SSE0_STEP1 */
+#        else
   sse_step_cfg(&adc1, 0, 0, chncfg);
-#        endif                         /* !CONFIG_TIVA_ADC1_SSE0_STEP1 */
-
-#        ifdef CONFIG_TIVA_ADC1_SSE0_STEP1
-#          ifdef CONFIG_TIVA_ADC1_SSE0_STEP1_TS
+#        endif
+#      ifdef CONFIG_TIVA_ADC1_SSE0_STEP1
+#        ifdef CONFIG_TIVA_ADC1_SSE0_STEP1_TS
   chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
-#          else                        /* ADC_SSCTL_IE */
+#        else
   chncfg = ADC_SSCTL_IE;
-#          endif                       /* CONFIG_TIVA_ADC1_SSE0_STEP1_TS */
-
+#        endif
   tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC1_SSE0_STEP1_AIN));
   sse_register_chn(&adc1, 0, 1, CONFIG_TIVA_ADC1_SSE0_STEP1_AIN);
   sse_differential(&adc1, 0, 1, 0);
 #          if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC1_SSE0_TRIGGER == ADC_EMUX_PROC)
   sse_sample_hold_time(&adc1, 0, 1, ADC_SSTH_SHOLD_16);
-#          endif                       /* (CONFIG_TIVA_ADC1_SSE0_TRIGGER ==
-                                        * ADC_EMUX_PROC) && defined
-                                        * (CONFIG_ARCH_CHIP_TM4C129) */
-
+#          endif
 #          ifndef CONFIG_TIVA_ADC1_SSE0_STEP2
   sse_step_cfg(&adc1, 0, 1, chncfg | ADC_SSCTL_END);
-
-#          else                        /* CONFIG_TIVA_ADC1_SSE0_STEP2 */
+#          else
   sse_step_cfg(&adc1, 0, 1, chncfg);
-#          endif                       /* !CONFIG_TIVA_ADC1_SSE0_STEP2 */
-
-#          ifdef CONFIG_TIVA_ADC1_SSE0_STEP2
-#            ifdef CONFIG_TIVA_ADC1_SSE0_STEP2_TS
+#          endif
+#        ifdef CONFIG_TIVA_ADC1_SSE0_STEP2
+#          ifdef CONFIG_TIVA_ADC1_SSE0_STEP2_TS
   chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
-#            else                      /* ADC_SSCTL_IE */
+#          else
   chncfg = ADC_SSCTL_IE;
-#            endif                     /* CONFIG_TIVA_ADC1_SSE0_STEP2_TS */
-
+#          endif
   tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC1_SSE0_STEP2_AIN));
   sse_register_chn(&adc1, 0, 2, CONFIG_TIVA_ADC1_SSE0_STEP2_AIN);
   sse_differential(&adc1, 0, 2, 0);
 #            if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC1_SSE0_TRIGGER == ADC_EMUX_PROC)
   sse_sample_hold_time(&adc1, 0, 2, ADC_SSTH_SHOLD_16);
-#            endif                     /* (CONFIG_TIVA_ADC1_SSE0_TRIGGER ==
-                                        * ADC_EMUX_PROC) && defined
-                                        * (CONFIG_ARCH_CHIP_TM4C129) */
-
+#            endif
 #            ifndef CONFIG_TIVA_ADC1_SSE0_STEP3
   sse_step_cfg(&adc1, 0, 2, chncfg | ADC_SSCTL_END);
-
-#            else                      /* CONFIG_TIVA_ADC1_SSE0_STEP3 */
+#            else
   sse_step_cfg(&adc1, 0, 2, chncfg);
-#            endif                     /* !CONFIG_TIVA_ADC1_SSE0_STEP3 */
-
-#            ifdef CONFIG_TIVA_ADC1_SSE0_STEP3
-#              ifdef CONFIG_TIVA_ADC1_SSE0_STEP3_TS
+#            endif
+#          ifdef CONFIG_TIVA_ADC1_SSE0_STEP3
+#            ifdef CONFIG_TIVA_ADC1_SSE0_STEP3_TS
   chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
-#              else                    /* ADC_SSCTL_IE */
+#            else
   chncfg = ADC_SSCTL_IE;
-#              endif                   /* CONFIG_TIVA_ADC1_SSE0_STEP3_TS */
-
+#            endif
   tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC1_SSE0_STEP3_AIN));
   sse_register_chn(&adc1, 0, 3, CONFIG_TIVA_ADC1_SSE0_STEP3_AIN);
   sse_differential(&adc1, 0, 3, 0);
 #              if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC1_SSE0_TRIGGER == ADC_EMUX_PROC)
   sse_sample_hold_time(&adc1, 0, 3, ADC_SSTH_SHOLD_16);
-#              endif                   /* (CONFIG_TIVA_ADC1_SSE0_TRIGGER ==
-                                        * ADC_EMUX_PROC) && defined
-                                        * (CONFIG_ARCH_CHIP_TM4C129) */
-
+#              endif
 #              ifndef CONFIG_TIVA_ADC1_SSE0_STEP4
   sse_step_cfg(&adc1, 0, 3, chncfg | ADC_SSCTL_END);
-
-#              else                    /* CONFIG_TIVA_ADC1_SSE0_STEP4 */
+#              else
   sse_step_cfg(&adc1, 0, 3, chncfg);
-#              endif                   /* !CONFIG_TIVA_ADC1_SSE0_STEP4 */
-
-#              ifdef CONFIG_TIVA_ADC1_SSE0_STEP4
-#                ifdef CONFIG_TIVA_ADC1_SSE0_STEP4_TS
+#              endif
+#            ifdef CONFIG_TIVA_ADC1_SSE0_STEP4
+#              ifdef CONFIG_TIVA_ADC1_SSE0_STEP4_TS
   chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
-#                else                  /* ADC_SSCTL_IE */
+#              else
   chncfg = ADC_SSCTL_IE;
-#                endif                 /* CONFIG_TIVA_ADC1_SSE0_STEP4_TS */
-
+#              endif
   tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC1_SSE0_STEP4_AIN));
   sse_register_chn(&adc1, 0, 4, CONFIG_TIVA_ADC1_SSE0_STEP4_AIN);
   sse_differential(&adc1, 0, 4, 0);
 #                if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC1_SSE0_TRIGGER == ADC_EMUX_PROC)
   sse_sample_hold_time(&adc1, 0, 4, ADC_SSTH_SHOLD_16);
-#                endif                 /* (CONFIG_TIVA_ADC1_SSE0_TRIGGER ==
-                                        * ADC_EMUX_PROC) && defined
-                                        * (CONFIG_ARCH_CHIP_TM4C129) */
-
+#                endif
 #                ifndef CONFIG_TIVA_ADC1_SSE0_STEP5
   sse_step_cfg(&adc1, 0, 4, chncfg | ADC_SSCTL_END);
-
-#                else                  /* CONFIG_TIVA_ADC1_SSE0_STEP5 */
+#                else
   sse_step_cfg(&adc1, 0, 4, chncfg);
-#                endif                 /* !CONFIG_TIVA_ADC1_SSE0_STEP5 */
-
-#                ifdef CONFIG_TIVA_ADC1_SSE0_STEP5
-#                  ifdef CONFIG_TIVA_ADC1_SSE0_STEP5_TS
+#                endif
+#              ifdef CONFIG_TIVA_ADC1_SSE0_STEP5
+#                ifdef CONFIG_TIVA_ADC1_SSE0_STEP5_TS
   chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
-#                  else                /* ADC_SSCTL_IE */
+#                else
   chncfg = ADC_SSCTL_IE;
-#                  endif               /* CONFIG_TIVA_ADC1_SSE0_STEP5_TS */
-
+#                endif
   tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC1_SSE0_STEP5_AIN));
   sse_register_chn(&adc1, 0, 5, CONFIG_TIVA_ADC1_SSE0_STEP5_AIN);
   sse_differential(&adc1, 0, 5, 0);
 #                  if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC1_SSE0_TRIGGER == ADC_EMUX_PROC)
   sse_sample_hold_time(&adc1, 0, 5, ADC_SSTH_SHOLD_16);
-#                  endif               /* (CONFIG_TIVA_ADC1_SSE0_TRIGGER ==
-                                        * ADC_EMUX_PROC) && defined
-                                        * (CONFIG_ARCH_CHIP_TM4C129) */
-
+#                  endif
 #                  ifndef CONFIG_TIVA_ADC1_SSE0_STEP6
   sse_step_cfg(&adc1, 0, 5, chncfg | ADC_SSCTL_END);
-
-#                  else                /* CONFIG_TIVA_ADC1_SSE0_STEP6 */
+#                  else
   sse_step_cfg(&adc1, 0, 5, chncfg);
-#                  endif               /* !CONFIG_TIVA_ADC1_SSE0_STEP6 */
-
-#                  ifdef CONFIG_TIVA_ADC1_SSE0_STEP6
-#                    ifdef CONFIG_TIVA_ADC1_SSE0_STEP6_TS
+#                  endif
+#                ifdef CONFIG_TIVA_ADC1_SSE0_STEP6
+#                  ifdef CONFIG_TIVA_ADC1_SSE0_STEP6_TS
   chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
-#                    else              /* ADC_SSCTL_IE */
+#                  else
   chncfg = ADC_SSCTL_IE;
-#                    endif             /* CONFIG_TIVA_ADC1_SSE0_STEP6_TS */
-
+#                  endif
   tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC1_SSE0_STEP6_AIN));
   sse_register_chn(&adc1, 0, 6, CONFIG_TIVA_ADC1_SSE0_STEP6_AIN);
   sse_differential(&adc1, 0, 6, 0);
 #                    if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC1_SSE0_TRIGGER == ADC_EMUX_PROC)
   sse_sample_hold_time(&adc1, 0, 6, ADC_SSTH_SHOLD_16);
-#                    endif             /* (CONFIG_TIVA_ADC1_SSE0_TRIGGER ==
-                                        * ADC_EMUX_PROC) && defined
-                                        * (CONFIG_ARCH_CHIP_TM4C129) */
-
+#                    endif
 #                    ifndef CONFIG_TIVA_ADC1_SSE0_STEP7
   sse_step_cfg(&adc1, 0, 6, chncfg | ADC_SSCTL_END);
-
-#                    else              /* CONFIG_TIVA_ADC1_SSE0_STEP7 */
+#                    else
   sse_step_cfg(&adc1, 0, 6, chncfg);
-#                    endif             /* !CONFIG_TIVA_ADC1_SSE0_STEP7 */
-
-#                    ifdef CONFIG_TIVA_ADC1_SSE0_STEP7
-#                      ifdef CONFIG_TIVA_ADC1_SSE0_STEP7_TS
+#                    endif
+#                  ifdef CONFIG_TIVA_ADC1_SSE0_STEP7
+#                    ifdef CONFIG_TIVA_ADC1_SSE0_STEP7_TS
   chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
-#                      else            /* ADC_SSCTL_IE */
+#                    else
   chncfg = ADC_SSCTL_IE;
-#                      endif           /* CONFIG_TIVA_ADC1_SSE0_STEP7_TS */
-
+#                    endif
   tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC1_SSE0_STEP7_AIN));
   sse_register_chn(&adc1, 0, 7, CONFIG_TIVA_ADC1_SSE0_STEP7_AIN);
   sse_differential(&adc1, 0, 7, 0);
 #                      if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC1_SSE0_TRIGGER == ADC_EMUX_PROC)
   sse_sample_hold_time(&adc1, 0, 7, ADC_SSTH_SHOLD_16);
-#                      endif           /* (CONFIG_TIVA_ADC1_SSE0_TRIGGER ==
-                                        * ADC_EMUX_PROC) && defined
-                                        * (CONFIG_ARCH_CHIP_TM4C129) */
-
+#                      endif
   sse_step_cfg(&adc1, 0, 7, chncfg | ADC_SSCTL_END);
-
-#                    endif             /* CONFIG_TIVA_ADC1_SSE0_STEP7 */
-#                  endif               /* CONFIG_TIVA_ADC1_SSE0_STEP6 */
-#                endif                 /* CONFIG_TIVA_ADC1_SSE0_STEP5 */
-#              endif                   /* CONFIG_TIVA_ADC1_SSE0_STEP4 */
-#            endif                     /* CONFIG_TIVA_ADC1_SSE0_STEP3 */
-#          endif                       /* CONFIG_TIVA_ADC1_SSE0_STEP2 */
-#        endif                         /* CONFIG_TIVA_ADC1_SSE0_STEP1 */
-#      endif                           /* CONFIG_TIVA_ADC1_SSE0_STEP0 */
+#                  endif /* CONFIG_TIVA_ADC1_SSE0_STEP7 */
+#                endif /* CONFIG_TIVA_ADC1_SSE0_STEP6 */
+#              endif /* CONFIG_TIVA_ADC1_SSE0_STEP5 */
+#            endif /* CONFIG_TIVA_ADC1_SSE0_STEP4 */
+#          endif /* CONFIG_TIVA_ADC1_SSE0_STEP3 */
+#        endif /* CONFIG_TIVA_ADC1_SSE0_STEP2 */
+#      endif /* CONFIG_TIVA_ADC1_SSE0_STEP1 */
+#    endif /* CONFIG_TIVA_ADC1_SSE0_STEP0 */
 }
-#    endif                             /* CONFIG_TIVA_ADC1_SSE0 */
+#  endif /* CONFIG_TIVA_ADC1_SSE0 */
 
-#    ifdef CONFIG_TIVA_ADC1_SSE1
+#  ifdef CONFIG_TIVA_ADC1_SSE1
 static void adc1_sse1_chn_cfg(void)
 {
   uint32_t chncfg = 0;
-#      ifdef CONFIG_TIVA_ADC1_SSE1_STEP0
-#        ifdef CONFIG_TIVA_ADC1_SSE1_STEP0_TS
+#    ifdef CONFIG_TIVA_ADC1_SSE1_STEP0
+#      ifdef CONFIG_TIVA_ADC1_SSE1_STEP0_TS
   chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
-#        else                          /* ADC_SSCTL_IE */
+#      else
   chncfg = ADC_SSCTL_IE;
-#        endif                         /* CONFIG_TIVA_ADC1_SSE1_STEP0_TS */
-
+#      endif
   tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC1_SSE1_STEP0_AIN));
   sse_register_chn(&adc1, 1, 0, CONFIG_TIVA_ADC1_SSE1_STEP0_AIN);
   sse_differential(&adc1, 1, 0, 0);
 #        if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC1_SSE1_TRIGGER == ADC_EMUX_PROC)
   sse_sample_hold_time(&adc1, 1, 0, ADC_SSTH_SHOLD_16);
-#        endif                         /* (CONFIG_TIVA_ADC1_SSE1_TRIGGER ==
-                                        * ADC_EMUX_PROC) && defined
-                                        * (CONFIG_ARCH_CHIP_TM4C129) */
-
+#        endif
 #        ifndef CONFIG_TIVA_ADC1_SSE1_STEP1
   sse_step_cfg(&adc1, 1, 0, chncfg | ADC_SSCTL_END);
-
-#        else                          /* CONFIG_TIVA_ADC1_SSE1_STEP1 */
+#        else
   sse_step_cfg(&adc1, 1, 0, chncfg);
-#        endif                         /* !CONFIG_TIVA_ADC1_SSE1_STEP1 */
-
-#        ifdef CONFIG_TIVA_ADC1_SSE1_STEP1
-#          ifdef CONFIG_TIVA_ADC1_SSE1_STEP1_TS
+#        endif
+#      ifdef CONFIG_TIVA_ADC1_SSE1_STEP1
+#        ifdef CONFIG_TIVA_ADC1_SSE1_STEP1_TS
   chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
-#          else                        /* ADC_SSCTL_IE */
+#        else
   chncfg = ADC_SSCTL_IE;
-#          endif                       /* CONFIG_TIVA_ADC1_SSE1_STEP1_TS */
-
+#        endif
   tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC1_SSE1_STEP1_AIN));
   sse_register_chn(&adc1, 1, 1, CONFIG_TIVA_ADC1_SSE1_STEP1_AIN);
   sse_differential(&adc1, 1, 1, 0);
 #          if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC1_SSE1_TRIGGER == ADC_EMUX_PROC)
   sse_sample_hold_time(&adc1, 1, 1, ADC_SSTH_SHOLD_16);
-#          endif                       /* (CONFIG_TIVA_ADC1_SSE1_TRIGGER ==
-                                        * ADC_EMUX_PROC) && defined
-                                        * (CONFIG_ARCH_CHIP_TM4C129) */
-
+#          endif
 #          ifndef CONFIG_TIVA_ADC1_SSE1_STEP2
   sse_step_cfg(&adc1, 1, 1, chncfg | ADC_SSCTL_END);
-
-#          else                        /* CONFIG_TIVA_ADC1_SSE1_STEP2 */
+#          else
   sse_step_cfg(&adc1, 1, 1, chncfg);
-#          endif                       /* !CONFIG_TIVA_ADC1_SSE1_STEP2 */
-
-#          ifdef CONFIG_TIVA_ADC1_SSE1_STEP2
-#            ifdef CONFIG_TIVA_ADC1_SSE1_STEP2_TS
+#          endif
+#        ifdef CONFIG_TIVA_ADC1_SSE1_STEP2
+#          ifdef CONFIG_TIVA_ADC1_SSE1_STEP2_TS
   chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
-#            else                      /* ADC_SSCTL_IE */
+#          else
   chncfg = ADC_SSCTL_IE;
-#            endif                     /* CONFIG_TIVA_ADC1_SSE1_STEP2_TS */
-
+#          endif
   tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC1_SSE1_STEP2_AIN));
   sse_register_chn(&adc1, 1, 2, CONFIG_TIVA_ADC1_SSE1_STEP2_AIN);
   sse_differential(&adc1, 1, 2, 0);
 #            if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC1_SSE1_TRIGGER == ADC_EMUX_PROC)
   sse_sample_hold_time(&adc1, 1, 2, ADC_SSTH_SHOLD_16);
-#            endif                     /* (CONFIG_TIVA_ADC1_SSE1_TRIGGER ==
-                                        * ADC_EMUX_PROC) && defined
-                                        * (CONFIG_ARCH_CHIP_TM4C129) */
-
+#            endif
 #            ifndef CONFIG_TIVA_ADC1_SSE1_STEP3
   sse_step_cfg(&adc1, 1, 2, chncfg | ADC_SSCTL_END);
-
-#            else                      /* CONFIG_TIVA_ADC1_SSE1_STEP3 */
+#            else
   sse_step_cfg(&adc1, 1, 2, chncfg);
-#            endif                     /* !CONFIG_TIVA_ADC1_SSE1_STEP3 */
-
-#            ifdef CONFIG_TIVA_ADC1_SSE1_STEP3
-#              ifdef CONFIG_TIVA_ADC1_SSE1_STEP3_TS
+#            endif
+#          ifdef CONFIG_TIVA_ADC1_SSE1_STEP3
+#            ifdef CONFIG_TIVA_ADC1_SSE1_STEP3_TS
   chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
-#              else                    /* ADC_SSCTL_IE */
+#            else
   chncfg = ADC_SSCTL_IE;
-#              endif                   /* CONFIG_TIVA_ADC1_SSE1_STEP3_TS */
-
+#            endif
   tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC1_SSE1_STEP3_AIN));
   sse_register_chn(&adc1, 1, 3, CONFIG_TIVA_ADC1_SSE1_STEP3_AIN);
   sse_differential(&adc1, 1, 3, 0);
 #              if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC1_SSE1_TRIGGER == ADC_EMUX_PROC)
   sse_sample_hold_time(&adc1, 1, 3, ADC_SSTH_SHOLD_16);
-#              endif                   /* (CONFIG_TIVA_ADC1_SSE1_TRIGGER ==
-                                        * ADC_EMUX_PROC) && defined
-                                        * (CONFIG_ARCH_CHIP_TM4C129) */
-
+#              endif
   sse_step_cfg(&adc1, 1, 3, chncfg | ADC_SSCTL_END);
-
-#            endif                     /* CONFIG_TIVA_ADC1_SSE1_STEP3 */
-#          endif                       /* CONFIG_TIVA_ADC1_SSE1_STEP2 */
-#        endif                         /* CONFIG_TIVA_ADC1_SSE1_STEP1 */
-#      endif                           /* CONFIG_TIVA_ADC1_SSE1_STEP0 */
+#          endif /* CONFIG_TIVA_ADC1_SSE1_STEP3 */
+#        endif /* CONFIG_TIVA_ADC1_SSE1_STEP2 */
+#      endif /* CONFIG_TIVA_ADC1_SSE1_STEP1 */
+#    endif /* CONFIG_TIVA_ADC1_SSE1_STEP0 */
 }
-#    endif                             /* CONFIG_TIVA_ADC1_SSE1 */
+#  endif /* CONFIG_TIVA_ADC1_SSE1 */
 
-#    ifdef CONFIG_TIVA_ADC1_SSE2
+#  ifdef CONFIG_TIVA_ADC1_SSE2
 static void adc1_sse2_chn_cfg(void)
 {
   uint32_t chncfg = 0;
-#      ifdef CONFIG_TIVA_ADC1_SSE2_STEP0
-#        ifdef CONFIG_TIVA_ADC1_SSE2_STEP0_TS
+#    ifdef CONFIG_TIVA_ADC1_SSE2_STEP0
+#      ifdef CONFIG_TIVA_ADC1_SSE2_STEP0_TS
   chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
-#        else                          /* ADC_SSCTL_IE */
+#      else
   chncfg = ADC_SSCTL_IE;
-#        endif                         /* CONFIG_TIVA_ADC1_SSE2_STEP0_TS */
-
+#      endif
   tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC1_SSE2_STEP0_AIN));
   sse_register_chn(&adc1, 2, 0, CONFIG_TIVA_ADC1_SSE2_STEP0_AIN);
   sse_differential(&adc1, 2, 0, 0);
 #        if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC1_SSE2_TRIGGER == ADC_EMUX_PROC)
   sse_sample_hold_time(&adc1, 2, 0, ADC_SSTH_SHOLD_16);
-#        endif                         /* (CONFIG_TIVA_ADC1_SSE2_TRIGGER ==
-                                        * ADC_EMUX_PROC) && defined
-                                        * (CONFIG_ARCH_CHIP_TM4C129) */
-
+#        endif
 #        ifndef CONFIG_TIVA_ADC1_SSE2_STEP1
   sse_step_cfg(&adc1, 2, 0, chncfg | ADC_SSCTL_END);
-
-#        else                          /* CONFIG_TIVA_ADC1_SSE2_STEP1 */
+#        else
   sse_step_cfg(&adc1, 2, 0, chncfg);
-#        endif                         /* !CONFIG_TIVA_ADC1_SSE2_STEP1 */
-
-#        ifdef CONFIG_TIVA_ADC1_SSE2_STEP1
-#          ifdef CONFIG_TIVA_ADC1_SSE2_STEP1_TS
+#        endif
+#      ifdef CONFIG_TIVA_ADC1_SSE2_STEP1
+#        ifdef CONFIG_TIVA_ADC1_SSE2_STEP1_TS
   chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
-#          else                        /* ADC_SSCTL_IE */
+#        else
   chncfg = ADC_SSCTL_IE;
-#          endif                       /* CONFIG_TIVA_ADC1_SSE2_STEP1_TS */
-
+#        endif
   tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC1_SSE2_STEP1_AIN));
   sse_register_chn(&adc1, 2, 1, CONFIG_TIVA_ADC1_SSE2_STEP1_AIN);
   sse_differential(&adc1, 2, 1, 0);
 #          if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC1_SSE2_TRIGGER == ADC_EMUX_PROC)
   sse_sample_hold_time(&adc1, 2, 1, ADC_SSTH_SHOLD_16);
-#          endif                       /* (CONFIG_TIVA_ADC1_SSE2_TRIGGER ==
-                                        * ADC_EMUX_PROC) && defined
-                                        * (CONFIG_ARCH_CHIP_TM4C129) */
-
+#          endif
 #          ifndef CONFIG_TIVA_ADC1_SSE2_STEP2
   sse_step_cfg(&adc1, 2, 1, chncfg | ADC_SSCTL_END);
-
-#          else                        /* CONFIG_TIVA_ADC1_SSE2_STEP2 */
+#          else
   sse_step_cfg(&adc1, 2, 1, chncfg);
-#          endif                       /* !CONFIG_TIVA_ADC1_SSE2_STEP2 */
-
-#          ifdef CONFIG_TIVA_ADC1_SSE2_STEP2
-#            ifdef CONFIG_TIVA_ADC1_SSE2_STEP2_TS
+#          endif
+#        ifdef CONFIG_TIVA_ADC1_SSE2_STEP2
+#          ifdef CONFIG_TIVA_ADC1_SSE2_STEP2_TS
   chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
-#            else                      /* ADC_SSCTL_IE */
+#          else
   chncfg = ADC_SSCTL_IE;
-#            endif                     /* CONFIG_TIVA_ADC1_SSE2_STEP2_TS */
-
+#          endif
   tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC1_SSE2_STEP2_AIN));
   sse_register_chn(&adc1, 2, 2, CONFIG_TIVA_ADC1_SSE2_STEP2_AIN);
   sse_differential(&adc1, 2, 2, 0);
 #            if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC1_SSE2_TRIGGER == ADC_EMUX_PROC)
   sse_sample_hold_time(&adc1, 2, 2, ADC_SSTH_SHOLD_16);
-#            endif                     /* (CONFIG_TIVA_ADC1_SSE2_TRIGGER ==
-                                        * ADC_EMUX_PROC) && defined
-                                        * (CONFIG_ARCH_CHIP_TM4C129) */
-
+#            endif
 #            ifndef CONFIG_TIVA_ADC1_SSE2_STEP3
   sse_step_cfg(&adc1, 2, 2, chncfg | ADC_SSCTL_END);
-
-#            else                      /* CONFIG_TIVA_ADC1_SSE2_STEP3 */
+#            else
   sse_step_cfg(&adc1, 2, 2, chncfg);
-#            endif                     /* !CONFIG_TIVA_ADC1_SSE2_STEP3 */
-
-#            ifdef CONFIG_TIVA_ADC1_SSE2_STEP3
-#              ifdef CONFIG_TIVA_ADC1_SSE2_STEP3_TS
+#            endif
+#          ifdef CONFIG_TIVA_ADC1_SSE2_STEP3
+#            ifdef CONFIG_TIVA_ADC1_SSE2_STEP3_TS
   chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
-#              else                    /* ADC_SSCTL_IE */
+#            else
   chncfg = ADC_SSCTL_IE;
-#              endif                   /* CONFIG_TIVA_ADC1_SSE2_STEP3_TS */
-
+#            endif
   tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC1_SSE2_STEP3_AIN));
   sse_register_chn(&adc1, 2, 3, CONFIG_TIVA_ADC1_SSE2_STEP3_AIN);
   sse_differential(&adc1, 2, 3, 0);
 #              if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC1_SSE2_TRIGGER == ADC_EMUX_PROC)
   sse_sample_hold_time(&adc1, 2, 3, ADC_SSTH_SHOLD_16);
-#              endif                   /* (CONFIG_TIVA_ADC1_SSE2_TRIGGER ==
-                                        * ADC_EMUX_PROC) && defined
-                                        * (CONFIG_ARCH_CHIP_TM4C129) */
-
+#              endif
   sse_step_cfg(&adc1, 2, 3, chncfg | ADC_SSCTL_END);
-
-#            endif                     /* CONFIG_TIVA_ADC1_SSE2_STEP3 */
-#          endif                       /* CONFIG_TIVA_ADC1_SSE2_STEP2 */
-#        endif                         /* CONFIG_TIVA_ADC1_SSE2_STEP1 */
-#      endif                           /* CONFIG_TIVA_ADC1_SSE2_STEP0 */
+#          endif /* CONFIG_TIVA_ADC1_SSE2_STEP3 */
+#        endif /* CONFIG_TIVA_ADC1_SSE2_STEP2 */
+#      endif /* CONFIG_TIVA_ADC1_SSE2_STEP1 */
+#    endif /* CONFIG_TIVA_ADC1_SSE2_STEP0 */
 }
-#    endif                             /* CONFIG_TIVA_ADC1_SSE2 */
+#  endif /* CONFIG_TIVA_ADC1_SSE2 */
 
-#    ifdef CONFIG_TIVA_ADC1_SSE3
+#  ifdef CONFIG_TIVA_ADC1_SSE3
 static void adc1_sse3_chn_cfg(void)
 {
   uint32_t chncfg = 0;
-#      ifdef CONFIG_TIVA_ADC1_SSE3_STEP0
-#        ifdef CONFIG_TIVA_ADC1_SSE3_STEP0_TS
+#    ifdef CONFIG_TIVA_ADC1_SSE3_STEP0
+#      ifdef CONFIG_TIVA_ADC1_SSE3_STEP0_TS
   chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
-#        else                          /* ADC_SSCTL_IE */
+#      else
   chncfg = ADC_SSCTL_IE;
-#        endif                         /* CONFIG_TIVA_ADC1_SSE3_STEP0_TS */
-
+#      endif
   tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC1_SSE3_STEP0_AIN));
   sse_register_chn(&adc1, 3, 0, CONFIG_TIVA_ADC1_SSE3_STEP0_AIN);
   sse_differential(&adc1, 3, 0, 0);
 #        if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC1_SSE3_TRIGGER == ADC_EMUX_PROC)
   sse_sample_hold_time(&adc1, 3, 0, ADC_SSTH_SHOLD_16);
-#        endif                         /* (CONFIG_TIVA_ADC1_SSE3_TRIGGER ==
-                                        * ADC_EMUX_PROC) && defined
-                                        * (CONFIG_ARCH_CHIP_TM4C129) */
-
+#        endif
   sse_step_cfg(&adc1, 3, 0, chncfg | ADC_SSCTL_END);
-
-#      endif                           /* CONFIG_TIVA_ADC1_SSE3_STEP0 */
+#    endif /* CONFIG_TIVA_ADC1_SSE3_STEP0 */
 }
-#    endif                             /* CONFIG_TIVA_ADC1_SSE3 */
-#  endif                               /* CONFIG_TIVA_ADC1 */
+#  endif /* CONFIG_TIVA_ADC1_SSE3 */
+#endif /* CONFIG_TIVA_ADC1 */
 
-#endif                                 /* CONFIG_TIVA_ADC0 | CONFIG_TIVA_ADC1 */
+#endif /* CONFIG_TIVA_ADC0 | CONFIG_TIVA_ADC1 */
diff --git a/nuttx/arch/arm/src/tiva/tiva_adc.h b/nuttx/arch/arm/src/tiva/tiva_adc.h
index b565a7574..aa86a9be8 100644
--- a/nuttx/arch/arm/src/tiva/tiva_adc.h
+++ b/nuttx/arch/arm/src/tiva/tiva_adc.h
@@ -49,43 +49,19 @@
 
 #ifdef CONFIG_TIVA_ADC
 
-/************************************************************************************
+/****************************************************************************
  * Pre-processor Definitions
- ************************************************************************************/
+ ****************************************************************************/
 
 #define TIVA_ADC_PWM_TRIG_IOCTL _ANIOC(0x00F0)
 
-/* PWM trigger support definitions *************************************************/
-
-#define ADC_TRIG_PWM_MASK \
-    (0xE0000000 & ADC_EMUX_PWM0 & ADC_EMUX_PWM1 & ADC_EMUX_PWM2 & ADC_EMUX_PWM3)
-
-/* Encodes the PWM generator (0 to 3) value to the 2 MSB's of 32-bits;
- * PWM module (0 or 1) value in the 3rd MSB:
- *      0bGGM0.0000.0000.0000,0000.0000.0000.0000
- * To be OR'd with a trigger register value.
- */
-
-#define PWM_GEN_SHIFT (31)
-#define PWM_MOD_SHIFT (30)
-#  define ADC_TRIG_PWM_IOCTL(gen,mod) \
-    (((gen) << PWM_GEN_SHIFT) | ((mod) << PWM_MOD_SHIFT))
+/* PWM trigger ioctl support  ***********************************************/
 
-/* Decodes PWM generator number from trigger */
+#define TIVA_ADC_PWM_TRIG(sse, pwm, mod) ((((mod) << 4) << ((pwm)  * 8)) + (sse))
 
-#define PWM_GEN_MASK             (0xC0000000)
-#  define ADC_TRIG_PWM_GEN(trig) \
-    (((trig)&PWM_GEN_MASK)>>(PWM_GEN_SHIFT-1))
-
-/* Decodes PWM module number from trigger */
-
-#define PWM_MOD_MASK             (0x20000000)
-#  define ADC_TRIG_PWM_MOD(trig) \
-    (((trig)&PWM_MOD_MASK)>>(PWM_MOD_SHIFT-1))
-
-/************************************************************************************
+/****************************************************************************
  * Public Functions
- ************************************************************************************/
+ ****************************************************************************/
 
 #ifndef __ASSEMBLY__
 #  ifdef __cplusplus
diff --git a/nuttx/arch/arm/src/tiva/tiva_timerlib.c b/nuttx/arch/arm/src/tiva/tiva_timerlib.c
index 6eb253ce7..75a49bcac 100644
--- a/nuttx/arch/arm/src/tiva/tiva_timerlib.c
+++ b/nuttx/arch/arm/src/tiva/tiva_timerlib.c
@@ -901,14 +901,6 @@ static int tiva_oneshot_periodic_mode32(struct tiva_gptmstate_s *priv,
   /* Enable and configure ADC trigger outputs */
   if (TIMER_ISADCTIMEOUT(timer) || TIMER_ISADCMATCH(timer))
     {
-      /* Enable ADC trigger outputs by setting the TAOTE bit in the
-       * control register.
-       */
-
-      regval = tiva_getreg(priv, TIVA_TIMER_CTL_OFFSET);
-      regval |= TIMER_CTL_TAOTE;
-      tiva_putreg(priv, TIVA_TIMER_CTL_OFFSET, regval);
-
 #ifdef CONFIG_ARCH_CHIP_TM4C129
       /* Enable timeout triggers now (match triggers will be
        * enabled when the first match value is set).
@@ -918,7 +910,15 @@ static int tiva_oneshot_periodic_mode32(struct tiva_gptmstate_s *priv,
         {
           tiva_putreg(priv, TIVA_TIMER_ADCEV_OFFSET, TIMER_ADCEV_TATOADCEN);
         }
-#endif /* CONFIG_ARCH_CHIP_TM4C129 */
+#endif
+
+      /* Enable ADC trigger outputs by setting the TAOTE bit in the
+       * control register.
+       */
+
+      regval = tiva_getreg(priv, TIVA_TIMER_CTL_OFFSET);
+      regval |= TIMER_CTL_TAOTE;
+      tiva_putreg(priv, TIVA_TIMER_CTL_OFFSET, regval);
     }
 
   /* In addition, if using CCP pins, the TCACT field can be programmed to
diff --git a/nuttx/arch/arm/src/tiva/tiva_timerlow32.c b/nuttx/arch/arm/src/tiva/tiva_timerlow32.c
index 90492678d..2bbf83860 100644
--- a/nuttx/arch/arm/src/tiva/tiva_timerlow32.c
+++ b/nuttx/arch/arm/src/tiva/tiva_timerlow32.c
@@ -591,6 +591,9 @@ int tiva_timer_register(FAR const char *devpath, int gptm, bool altclk)
   config->cmn.mode                   = TIMER32_MODE_PERIODIC;
   config->cmn.alternate              = altclk;
   config->config.flags               = TIMER_FLAG_COUNTUP;
+#ifdef CONFIG_TIVA_TIMER32_ADCEVENT
+  config->config.flags              |= TIMER_FLAG_ADCTIMEOUT;
+#endif
   config->config.handler             = tiva_handler;
   config->config.arg                 = priv;