Updated Tiva ADC files

2 files changed, 1634 insertions, 1544 deletions

diff --git a/nuttx/arch/arm/src/tiva/Kconfig b/nuttx/arch/arm/src/tiva/Kconfig
index acda4530f..94083af81 100644
--- a/nuttx/arch/arm/src/tiva/Kconfig
+++ b/nuttx/arch/arm/src/tiva/Kconfig
@@ -872,159 +872,159 @@ menuconfig TIVA_ADC0_SSE0
 		- priority
 		- input channel step assignment
 
-	config TIVA_ADC0_SSE0_PRIORITY
-		int "Conversion priority, must be a value from 0 to 3, no duplicates"
-		default 0
-		range 0 3
-		depends on TIVA_ADC0_SSE0
-		---help---
-			Set the conversion priority for this SSE. Each ADC has 4 SSEs so the
-			order in which they are serviced is determined by this value.
-
-	config TIVA_ADC0_SSE0_TRIGGER
-		int "Set the trigger source to start a SSE's conversion, see help for options"
-		default 0
-		range 0 15
-		depends on TIVA_ADC0_SSE0
-		---help---
-			Set the trigger source. The following values correspond to the
-			following triggers:
-			- 0x0: Processor (default)
-			- 0x1: *Analog Comparator 0
-			- 0x2: *Analog Comparator 1
-			- 0x3: *Analog Comparator 2
-			- 0x4: External (GPIO Pins)
-			- 0x5: Timer
-			- 0x6: **PWM generator 0
-			- 0x7: **PWM generator 1
-			- 0x8: **PWM generator 2
-			- 0x9: **PWM generator 3
-			- 0xE: Never Trigger
-			- 0xF: Always (continuously sample)
-
-			* Comparators are unsupported
-			** PWM triggering requires additional setup at runtime - There is a special
-			ADC IOCTL defined in the Tiva ADC driver for this purpose.
-
-		menuconfig TIVA_ADC0_SSE0_STEP0
-			bool "Enable and configure ADC0 SSE0 step 0"
-			default n
-			depends on TIVA_ADC0_SSE0
-
-			config TIVA_ADC0_SSE0_STEP0_TS
-				bool "This step will retrieve data from the on-chip temperature sensor."
-				default n
-				depends on TIVA_ADC0_SSE0_STEP0
-
-			config TIVA_ADC0_SSE0_STEP0_AIN
-				int "Set the input AIN. See datasheet for pin to AIN mappings."
-				default 0
-				depends on TIVA_ADC0_SSE0_STEP0
-
-		menuconfig TIVA_ADC0_SSE0_STEP1
-			bool "Enable and configure ADC0 SSE0 step 1"
-			default n
-			depends on TIVA_ADC0_SSE0
-
-			config TIVA_ADC0_SSE0_STEP1_TS
-				bool "This step will retrieve data from the on-chip temperature sensor."
-				default n
-				depends on TIVA_ADC0_SSE0_STEP1
-
-			config TIVA_ADC0_SSE0_STEP1_AIN
-				int "Set the input AIN. See datasheet for pin to AIN mappings."
-				default 0
-				depends on TIVA_ADC0_SSE0_STEP1
-
-		menuconfig TIVA_ADC0_SSE0_STEP2
-			bool "Enable and configure ADC0 SSE0 step 2"
-			default n
-			depends on TIVA_ADC0_SSE0
-
-			config TIVA_ADC0_SSE0_STEP2_TS
-				bool "This step will retrieve data from the on-chip temperature sensor."
-				default n
-				depends on TIVA_ADC0_SSE0_STEP2
-
-			config TIVA_ADC0_SSE0_STEP2_AIN
-				int "Set the input AIN. See datasheet for pin to AIN mappings."
-				default 0
-				depends on TIVA_ADC0_SSE0_STEP2
-
-		menuconfig TIVA_ADC0_SSE0_STEP3
-			bool "Enable and configure ADC0 SSE0 step 3"
-			default n
-			depends on TIVA_ADC0_SSE0
-
-			config TIVA_ADC0_SSE0_STEP3_TS
-				bool "This step will retrieve data from the on-chip temperature sensor."
-				default n
-				depends on TIVA_ADC0_SSE0_STEP3
-
-			config TIVA_ADC0_SSE0_STEP3_AIN
-				int "Set the input AIN. See datasheet for pin to AIN mappings."
-				default 0
-				depends on TIVA_ADC0_SSE0_STEP3
-
-		menuconfig TIVA_ADC0_SSE0_STEP4
-			bool "Enable and configure ADC0 SSE0 step 4"
-			default n
-			depends on TIVA_ADC0_SSE0
-
-			config TIVA_ADC0_SSE0_STEP4_TS
-				bool "This step will retrieve data from the on-chip temperature sensor."
-				default n
-				depends on TIVA_ADC0_SSE0_STEP4
-
-			config TIVA_ADC0_SSE0_STEP4_AIN
-				int "Set the input AIN. See datasheet for pin to AIN mappings."
-				default 0
-				depends on TIVA_ADC0_SSE0_STEP4
-
-		menuconfig TIVA_ADC0_SSE0_STEP5
-			bool "Enable and configure ADC0 SSE0 step 5"
-			default n
-			depends on TIVA_ADC0_SSE0
-
-			config TIVA_ADC0_SSE0_STEP5_TS
-				bool "This step will retrieve data from the on-chip temperature sensor."
-				default n
-				depends on TIVA_ADC0_SSE0_STEP5
-
-			config TIVA_ADC0_SSE0_STEP5_AIN
-				int "Set the input AIN. See datasheet for pin to AIN mappings."
-				default 0
-				depends on TIVA_ADC0_SSE0_STEP5
-
-		menuconfig TIVA_ADC0_SSE0_STEP6
-			bool "Enable and configure ADC0 SSE0 step 6"
-			default n
-			depends on TIVA_ADC0_SSE0
-
-			config TIVA_ADC0_SSE0_STEP6_TS
-				bool "This step will retrieve data from the on-chip temperature sensor."
-				default n
-				depends on TIVA_ADC0_SSE0_STEP6
-
-			config TIVA_ADC0_SSE0_STEP6_AIN
-				int "Set the input AIN. See datasheet for pin to AIN mappings."
-				default 0
-				depends on TIVA_ADC0_SSE0_STEP6
-
-		menuconfig TIVA_ADC0_SSE0_STEP7
-			bool "Enable and configure ADC0 SSE0 step 7"
-			default n
-			depends on TIVA_ADC0_SSE0
-
-			config TIVA_ADC0_SSE0_STEP7_TS
-				bool "This step will retrieve data from the on-chip temperature sensor."
-				default n
-				depends on TIVA_ADC0_SSE0_STEP7
-
-			config TIVA_ADC0_SSE0_STEP7_AIN
-				int "Set the input AIN. See datasheet for pin to AIN mappings."
-				default 0
-				depends on TIVA_ADC0_SSE0_STEP7
+config TIVA_ADC0_SSE0_PRIORITY
+	int "Conversion priority, must be a value from 0 to 3, no duplicates"
+	default 0
+	range 0 3
+	depends on TIVA_ADC0_SSE0
+	---help---
+		Set the conversion priority for this SSE. Each ADC has 4 SSEs so the
+		order in which they are serviced is determined by this value.
+
+config TIVA_ADC0_SSE0_TRIGGER
+	int "Set the trigger source to start a SSE's conversion, see help for options"
+	default 0
+	range 0 15
+	depends on TIVA_ADC0_SSE0
+	---help---
+		Set the trigger source. The following values correspond to the
+		following triggers:
+		- 0x0: Processor (default)
+		- 0x1: *Analog Comparator 0
+		- 0x2: *Analog Comparator 1
+		- 0x3: *Analog Comparator 2
+		- 0x4: External (GPIO Pins)
+		- 0x5: Timer
+		- 0x6: **PWM generator 0
+		- 0x7: **PWM generator 1
+		- 0x8: **PWM generator 2
+		- 0x9: **PWM generator 3
+		- 0xE: Never Trigger
+		- 0xF: Always (continuously sample)
+
+		* Comparators are unsupported
+		** PWM triggering requires additional setup at runtime - There is a special
+		ADC IOCTL defined in the Tiva ADC driver for this purpose.
+
+menuconfig TIVA_ADC0_SSE0_STEP0
+	bool "Enable and configure ADC0 SSE0 step 0"
+	default n
+	depends on TIVA_ADC0_SSE0
+
+config TIVA_ADC0_SSE0_STEP0_TS
+	bool "This step will retrieve data from the on-chip temperature sensor."
+	default n
+	depends on TIVA_ADC0_SSE0_STEP0
+
+config TIVA_ADC0_SSE0_STEP0_AIN
+	int "Set the input AIN. See datasheet for pin to AIN mappings."
+	default 0
+	depends on TIVA_ADC0_SSE0_STEP0
+
+menuconfig TIVA_ADC0_SSE0_STEP1
+	bool "Enable and configure ADC0 SSE0 step 1"
+	default n
+	depends on TIVA_ADC0_SSE0
+
+config TIVA_ADC0_SSE0_STEP1_TS
+	bool "This step will retrieve data from the on-chip temperature sensor."
+	default n
+	depends on TIVA_ADC0_SSE0_STEP1
+
+config TIVA_ADC0_SSE0_STEP1_AIN
+	int "Set the input AIN. See datasheet for pin to AIN mappings."
+	default 0
+	depends on TIVA_ADC0_SSE0_STEP1
+
+menuconfig TIVA_ADC0_SSE0_STEP2
+	bool "Enable and configure ADC0 SSE0 step 2"
+	default n
+	depends on TIVA_ADC0_SSE0
+
+config TIVA_ADC0_SSE0_STEP2_TS
+	bool "This step will retrieve data from the on-chip temperature sensor."
+	default n
+	depends on TIVA_ADC0_SSE0_STEP2
+
+config TIVA_ADC0_SSE0_STEP2_AIN
+	int "Set the input AIN. See datasheet for pin to AIN mappings."
+	default 0
+	depends on TIVA_ADC0_SSE0_STEP2
+
+menuconfig TIVA_ADC0_SSE0_STEP3
+	bool "Enable and configure ADC0 SSE0 step 3"
+	default n
+	depends on TIVA_ADC0_SSE0
+
+config TIVA_ADC0_SSE0_STEP3_TS
+	bool "This step will retrieve data from the on-chip temperature sensor."
+	default n
+	depends on TIVA_ADC0_SSE0_STEP3
+
+config TIVA_ADC0_SSE0_STEP3_AIN
+	int "Set the input AIN. See datasheet for pin to AIN mappings."
+	default 0
+	depends on TIVA_ADC0_SSE0_STEP3
+
+menuconfig TIVA_ADC0_SSE0_STEP4
+	bool "Enable and configure ADC0 SSE0 step 4"
+	default n
+	depends on TIVA_ADC0_SSE0
+
+config TIVA_ADC0_SSE0_STEP4_TS
+	bool "This step will retrieve data from the on-chip temperature sensor."
+	default n
+	depends on TIVA_ADC0_SSE0_STEP4
+
+config TIVA_ADC0_SSE0_STEP4_AIN
+	int "Set the input AIN. See datasheet for pin to AIN mappings."
+	default 0
+	depends on TIVA_ADC0_SSE0_STEP4
+
+menuconfig TIVA_ADC0_SSE0_STEP5
+	bool "Enable and configure ADC0 SSE0 step 5"
+	default n
+	depends on TIVA_ADC0_SSE0
+
+config TIVA_ADC0_SSE0_STEP5_TS
+	bool "This step will retrieve data from the on-chip temperature sensor."
+	default n
+	depends on TIVA_ADC0_SSE0_STEP5
+
+config TIVA_ADC0_SSE0_STEP5_AIN
+	int "Set the input AIN. See datasheet for pin to AIN mappings."
+	default 0
+	depends on TIVA_ADC0_SSE0_STEP5
+
+menuconfig TIVA_ADC0_SSE0_STEP6
+	bool "Enable and configure ADC0 SSE0 step 6"
+	default n
+	depends on TIVA_ADC0_SSE0
+
+config TIVA_ADC0_SSE0_STEP6_TS
+	bool "This step will retrieve data from the on-chip temperature sensor."
+	default n
+	depends on TIVA_ADC0_SSE0_STEP6
+
+config TIVA_ADC0_SSE0_STEP6_AIN
+	int "Set the input AIN. See datasheet for pin to AIN mappings."
+	default 0
+	depends on TIVA_ADC0_SSE0_STEP6
+
+menuconfig TIVA_ADC0_SSE0_STEP7
+	bool "Enable and configure ADC0 SSE0 step 7"
+	default n
+	depends on TIVA_ADC0_SSE0
+
+config TIVA_ADC0_SSE0_STEP7_TS
+	bool "This step will retrieve data from the on-chip temperature sensor."
+	default n
+	depends on TIVA_ADC0_SSE0_STEP7
+
+config TIVA_ADC0_SSE0_STEP7_AIN
+	int "Set the input AIN. See datasheet for pin to AIN mappings."
+	default 0
+	depends on TIVA_ADC0_SSE0_STEP7
 
 menuconfig TIVA_ADC0_SSE1
 	bool "Enable and configure ADC0 SSE1"
@@ -1038,97 +1038,96 @@ menuconfig TIVA_ADC0_SSE1
 		- priority
 		- input channel step assignment
 
-	config TIVA_ADC0_SSE1_PRIORITY
-		int "Conversion priority, must be a value from 0 to 3, no duplicates"
-		default 0
-		depends on TIVA_ADC0_SSE1
-		---help---
-			Set the conversion priority for this SSE. Each ADC has 4 SSEs so the
-			order in which they are serviced is determined by this value.
+config TIVA_ADC0_SSE1_PRIORITY
+	int "Conversion priority, must be a value from 0 to 3, no duplicates"
+	default 0
+	depends on TIVA_ADC0_SSE1
+	---help---
+		Set the conversion priority for this SSE. Each ADC has 4 SSEs so the
+		order in which they are serviced is determined by this value.
+config TIVA_ADC0_SSE1_TRIGGER
+	int "Set the trigger source to start a SSE's conversion, see help for options"
+	default 0
+	depends on TIVA_ADC0_SSE1
+	---help---
+		Set the trigger source. The following values correspond to the
+		following triggers:
+		- 0x0: Processor (default)
+		- 0x1: *Analog Comparator 0
+		- 0x2: *Analog Comparator 1
+		- 0x3: *Analog Comparator 2
+		- 0x4: External (GPIO Pins)
+		- 0x5: Timer
+		- 0x6: **PWM generator 0
+		- 0x7: **PWM generator 1
+		- 0x8: **PWM generator 2
+		- 0x9: **PWM generator 3
+		- 0xE: Never Trigger
+		- 0xF: Always (continuously sample)
+
+		* Comparators are unsupported
+		** PWM triggering requires additional setup at runtime - There is a special
+		ADC IOCTL defined in the Tiva ADC driver for this purpose.
+
+menuconfig TIVA_ADC0_SSE1_STEP0
+	bool "Enable and configure ADC0 SSE1 step 0"
+	default n
+	depends on TIVA_ADC0_SSE1
+
+config TIVA_ADC0_SSE1_STEP0_TS
+	bool "This step will retrieve data from the on-chip temperature sensor."
+	default n
+	depends on TIVA_ADC0_SSE1_STEP0
+
+config TIVA_ADC0_SSE1_STEP0_AIN
+	int "Set the input AIN. See datasheet for pin to AIN mappings."
+	default 0
+	depends on TIVA_ADC0_SSE1_STEP0
 
-	config TIVA_ADC0_SSE1_TRIGGER
-		int "Set the trigger source to start a SSE's conversion, see help for options"
-		default 0
-		depends on TIVA_ADC0_SSE1
-		---help---
-			Set the trigger source. The following values correspond to the
-			following triggers:
-			- 0x0: Processor (default)
-			- 0x1: *Analog Comparator 0
-			- 0x2: *Analog Comparator 1
-			- 0x3: *Analog Comparator 2
-			- 0x4: External (GPIO Pins)
-			- 0x5: Timer
-			- 0x6: **PWM generator 0
-			- 0x7: **PWM generator 1
-			- 0x8: **PWM generator 2
-			- 0x9: **PWM generator 3
-			- 0xE: Never Trigger
-			- 0xF: Always (continuously sample)
-
-			* Comparators are unsupported
-			** PWM triggering requires additional setup at runtime - There is a special
-			ADC IOCTL defined in the Tiva ADC driver for this purpose.
-
-		menuconfig TIVA_ADC0_SSE1_STEP0
-			bool "Enable and configure ADC0 SSE1 step 0"
-			default n
-			depends on TIVA_ADC0_SSE1
-
-			config TIVA_ADC0_SSE1_STEP0_TS
-				bool "This step will retrieve data from the on-chip temperature sensor."
-				default n
-				depends on TIVA_ADC0_SSE1_STEP0
-
-			config TIVA_ADC0_SSE1_STEP0_AIN
-				int "Set the input AIN. See datasheet for pin to AIN mappings."
-				default 0
-				depends on TIVA_ADC0_SSE1_STEP0
-
-		menuconfig TIVA_ADC0_SSE1_STEP1
-			bool "Enable and configure ADC0 SSE1 step 1"
-			default n
-			depends on TIVA_ADC0_SSE1
-
-			config TIVA_ADC0_SSE1_STEP1_TS
-				bool "This step will retrieve data from the on-chip temperature sensor."
-				default n
-				depends on TIVA_ADC0_SSE1_STEP1
-
-			config TIVA_ADC0_SSE1_STEP1_AIN
-				int "Set the input AIN. See datasheet for pin to AIN mappings."
-				default 0
-				depends on TIVA_ADC0_SSE1_STEP1
-
-		menuconfig TIVA_ADC0_SSE1_STEP2
-			bool "Enable and configure ADC0 SSE1 step 2"
-			default n
-			depends on TIVA_ADC0_SSE1
-
-			config TIVA_ADC0_SSE1_STEP2_TS
-				bool "This step will retrieve data from the on-chip temperature sensor."
-				default n
-				depends on TIVA_ADC0_SSE1_STEP2
-
-			config TIVA_ADC0_SSE1_STEP2_AIN
-				int "Set the input AIN. See datasheet for pin to AIN mappings."
-				default 0
-				depends on TIVA_ADC0_SSE1_STEP2
-
-		menuconfig TIVA_ADC0_SSE1_STEP3
-			bool "Enable and configure ADC0 SSE1 step 3"
-			default n
-			depends on TIVA_ADC0_SSE1
-
-			config TIVA_ADC0_SSE1_STEP3_TS
-				bool "This step will retrieve data from the on-chip temperature sensor."
-				default n
-				depends on TIVA_ADC0_SSE1_STEP3
-
-			config TIVA_ADC0_SSE1_STEP3_AIN
-				int "Set the input AIN. See datasheet for pin to AIN mappings."
-				default 0
-				depends on TIVA_ADC0_SSE1_STEP3
+menuconfig TIVA_ADC0_SSE1_STEP1
+	bool "Enable and configure ADC0 SSE1 step 1"
+	default n
+	depends on TIVA_ADC0_SSE1
+
+config TIVA_ADC0_SSE1_STEP1_TS
+	bool "This step will retrieve data from the on-chip temperature sensor."
+	default n
+	depends on TIVA_ADC0_SSE1_STEP1
+
+config TIVA_ADC0_SSE1_STEP1_AIN
+	int "Set the input AIN. See datasheet for pin to AIN mappings."
+	default 0
+	depends on TIVA_ADC0_SSE1_STEP1
+
+menuconfig TIVA_ADC0_SSE1_STEP2
+	bool "Enable and configure ADC0 SSE1 step 2"
+	default n
+	depends on TIVA_ADC0_SSE1
+
+config TIVA_ADC0_SSE1_STEP2_TS
+	bool "This step will retrieve data from the on-chip temperature sensor."
+	default n
+	depends on TIVA_ADC0_SSE1_STEP2
+
+config TIVA_ADC0_SSE1_STEP2_AIN
+	int "Set the input AIN. See datasheet for pin to AIN mappings."
+	default 0
+	depends on TIVA_ADC0_SSE1_STEP2
+
+menuconfig TIVA_ADC0_SSE1_STEP3
+	bool "Enable and configure ADC0 SSE1 step 3"
+	default n
+	depends on TIVA_ADC0_SSE1
+
+config TIVA_ADC0_SSE1_STEP3_TS
+	bool "This step will retrieve data from the on-chip temperature sensor."
+	default n
+	depends on TIVA_ADC0_SSE1_STEP3
+
+config TIVA_ADC0_SSE1_STEP3_AIN
+	int "Set the input AIN. See datasheet for pin to AIN mappings."
+	default 0
+	depends on TIVA_ADC0_SSE1_STEP3
 
 menuconfig TIVA_ADC0_SSE2
 	bool "Enable and configure ADC0 SSE2"
@@ -1142,97 +1141,96 @@ menuconfig TIVA_ADC0_SSE2
 		- priority
 		- input channel step assignment
 
-	config TIVA_ADC0_SSE2_PRIORITY
-		int "Conversion priority, must be a value from 0 to 3, no duplicates"
-		default 0
-		depends on TIVA_ADC0_SSE2
-		---help---
-			Set the conversion priority for this SSE. Each ADC has 4 SSEs so the
-			order in which they are serviced is determined by this value.
+config TIVA_ADC0_SSE2_PRIORITY
+	int "Conversion priority, must be a value from 0 to 3, no duplicates"
+	default 0
+	depends on TIVA_ADC0_SSE2
+	---help---
+		Set the conversion priority for this SSE. Each ADC has 4 SSEs so the
+		order in which they are serviced is determined by this value.
+config TIVA_ADC0_SSE2_TRIGGER
+	int "Set the trigger source to start a SSE's conversion, see help for options"
+	default 0
+	depends on TIVA_ADC0_SSE2
+	---help---
+		Set the trigger source. The following values correspond to the
+		following triggers:
+		- 0x0: Processor (default)
+		- 0x1: *Analog Comparator 0
+		- 0x2: *Analog Comparator 1
+		- 0x3: *Analog Comparator 2
+		- 0x4: External (GPIO Pins)
+		- 0x5: Timer
+		- 0x6: **PWM generator 0
+		- 0x7: **PWM generator 1
+		- 0x8: **PWM generator 2
+		- 0x9: **PWM generator 3
+		- 0xE: Never Trigger
+		- 0xF: Always (continuously sample)
+
+		* Comparators are unsupported
+		** PWM triggering requires additional setup at runtime - There is a special
+		ADC IOCTL defined in the Tiva ADC driver for this purpose.
+
+menuconfig TIVA_ADC0_SSE2_STEP0
+	bool "Enable and configure ADC0 SSE2 step 0"
+	default n
+	depends on TIVA_ADC0_SSE2
+
+config TIVA_ADC0_SSE2_STEP0_TS
+	bool "This step will retrieve data from the on-chip temperature sensor."
+	default n
+	depends on TIVA_ADC0_SSE2_STEP0
+
+config TIVA_ADC0_SSE2_STEP0_AIN
+	int "Set the input AIN. See datasheet for pin to AIN mappings."
+	default 0
+	depends on TIVA_ADC0_SSE2_STEP0
 
-	config TIVA_ADC0_SSE2_TRIGGER
-		int "Set the trigger source to start a SSE's conversion, see help for options"
-		default 0
-		depends on TIVA_ADC0_SSE2
-		---help---
-			Set the trigger source. The following values correspond to the
-			following triggers:
-			- 0x0: Processor (default)
-			- 0x1: *Analog Comparator 0
-			- 0x2: *Analog Comparator 1
-			- 0x3: *Analog Comparator 2
-			- 0x4: External (GPIO Pins)
-			- 0x5: Timer
-			- 0x6: **PWM generator 0
-			- 0x7: **PWM generator 1
-			- 0x8: **PWM generator 2
-			- 0x9: **PWM generator 3
-			- 0xE: Never Trigger
-			- 0xF: Always (continuously sample)
-
-			* Comparators are unsupported
-			** PWM triggering requires additional setup at runtime - There is a special
-			ADC IOCTL defined in the Tiva ADC driver for this purpose.
-
-		menuconfig TIVA_ADC0_SSE2_STEP0
-			bool "Enable and configure ADC0 SSE2 step 0"
-			default n
-			depends on TIVA_ADC0_SSE2
-
-			config TIVA_ADC0_SSE2_STEP0_TS
-				bool "This step will retrieve data from the on-chip temperature sensor."
-				default n
-				depends on TIVA_ADC0_SSE2_STEP0
-
-			config TIVA_ADC0_SSE2_STEP0_AIN
-				int "Set the input AIN. See datasheet for pin to AIN mappings."
-				default 0
-				depends on TIVA_ADC0_SSE2_STEP0
-
-		menuconfig TIVA_ADC0_SSE2_STEP1
-			bool "Enable and configure ADC0 SSE2 step 1"
-			default n
-			depends on TIVA_ADC0_SSE2
-
-			config TIVA_ADC0_SSE2_STEP1_TS
-				bool "This step will retrieve data from the on-chip temperature sensor."
-				default n
-				depends on TIVA_ADC0_SSE2_STEP1
-
-			config TIVA_ADC0_SSE2_STEP1_AIN
-				int "Set the input AIN. See datasheet for pin to AIN mappings."
-				default 0
-				depends on TIVA_ADC0_SSE2_STEP1
-
-		menuconfig TIVA_ADC0_SSE2_STEP2
-			bool "Enable and configure ADC0 SSE2 step 2"
-			default n
-			depends on TIVA_ADC0_SSE2
-
-			config TIVA_ADC0_SSE2_STEP2_TS
-				bool "This step will retrieve data from the on-chip temperature sensor."
-				default n
-				depends on TIVA_ADC0_SSE2_STEP2
-
-			config TIVA_ADC0_SSE2_STEP2_AIN
-				int "Set the input AIN. See datasheet for pin to AIN mappings."
-				default 0
-				depends on TIVA_ADC0_SSE2_STEP2
-
-		menuconfig TIVA_ADC0_SSE2_STEP3
-			bool "Enable and configure ADC0 SSE2 step 3"
-			default n
-			depends on TIVA_ADC0_SSE2
-
-			config TIVA_ADC0_SSE2_STEP3_TS
-				bool "This step will retrieve data from the on-chip temperature sensor."
-				default n
-				depends on TIVA_ADC0_SSE2_STEP3
-
-			config TIVA_ADC0_SSE2_STEP3_AIN
-				int "Set the input AIN. See datasheet for pin to AIN mappings."
-				default 0
-				depends on TIVA_ADC0_SSE2_STEP3
+menuconfig TIVA_ADC0_SSE2_STEP1
+	bool "Enable and configure ADC0 SSE2 step 1"
+	default n
+	depends on TIVA_ADC0_SSE2
+
+config TIVA_ADC0_SSE2_STEP1_TS
+	bool "This step will retrieve data from the on-chip temperature sensor."
+	default n
+	depends on TIVA_ADC0_SSE2_STEP1
+
+config TIVA_ADC0_SSE2_STEP1_AIN
+	int "Set the input AIN. See datasheet for pin to AIN mappings."
+	default 0
+	depends on TIVA_ADC0_SSE2_STEP1
+
+menuconfig TIVA_ADC0_SSE2_STEP2
+	bool "Enable and configure ADC0 SSE2 step 2"
+	default n
+	depends on TIVA_ADC0_SSE2
+
+config TIVA_ADC0_SSE2_STEP2_TS
+	bool "This step will retrieve data from the on-chip temperature sensor."
+	default n
+	depends on TIVA_ADC0_SSE2_STEP2
+
+config TIVA_ADC0_SSE2_STEP2_AIN
+	int "Set the input AIN. See datasheet for pin to AIN mappings."
+	default 0
+	depends on TIVA_ADC0_SSE2_STEP2
+
+menuconfig TIVA_ADC0_SSE2_STEP3
+	bool "Enable and configure ADC0 SSE2 step 3"
+	default n
+	depends on TIVA_ADC0_SSE2
+
+config TIVA_ADC0_SSE2_STEP3_TS
+	bool "This step will retrieve data from the on-chip temperature sensor."
+	default n
+	depends on TIVA_ADC0_SSE2_STEP3
+
+config TIVA_ADC0_SSE2_STEP3_AIN
+	int "Set the input AIN. See datasheet for pin to AIN mappings."
+	default 0
+	depends on TIVA_ADC0_SSE2_STEP3
 
 menuconfig TIVA_ADC0_SSE3
 	bool "Enable and configure ADC0 SSE3"
@@ -1246,52 +1244,51 @@ menuconfig TIVA_ADC0_SSE3
 		- priority
 		- input channel step assignment
 
-	config TIVA_ADC0_SSE3_PRIORITY
-		int "Conversion priority, must be a value from 0 to 3, no duplicates"
-		default 0
-		depends on TIVA_ADC0_SSE3
-		---help---
-			Set the conversion priority for this SSE. Each ADC has 4 SSEs so the
-			order in which they are serviced is determined by this value.
-
-	config TIVA_ADC0_SSE3_TRIGGER
-		int "Set the trigger source to start a SSE's conversion, see help for options"
-		default 0
-		depends on TIVA_ADC0_SSE3
-		---help---
-			Set the trigger source. The following values correspond to the
-			following triggers:
-			- 0x0: Processor (default)
-			- 0x1: *Analog Comparator 0
-			- 0x2: *Analog Comparator 1
-			- 0x3: *Analog Comparator 2
-			- 0x4: External (GPIO Pins)
-			- 0x5: Timer
-			- 0x6: **PWM generator 0
-			- 0x7: **PWM generator 1
-			- 0x8: **PWM generator 2
-			- 0x9: **PWM generator 3
-			- 0xE: Never Trigger
-			- 0xF: Always (continuously sample)
-
-			* Comparators are unsupported
-			** PWM triggering requires additional setup at runtime - There is a special
-			ADC IOCTL defined in the Tiva ADC driver for this purpose.
-
-		menuconfig TIVA_ADC0_SSE3_STEP0
-			bool "Enable and configure ADC0 SSE3 step 0"
-			default n
-			depends on TIVA_ADC0_SSE3
-
-			config TIVA_ADC0_SSE3_STEP0_TS
-				bool "This step will retrieve data from the on-chip temperature sensor."
-				default n
-				depends on TIVA_ADC0_SSE3_STEP0
-
-			config TIVA_ADC0_SSE3_STEP0_AIN
-				int "Set the input AIN. See datasheet for pin to AIN mappings."
-				default 0
-				depends on TIVA_ADC0_SSE3_STEP0
+config TIVA_ADC0_SSE3_PRIORITY
+	int "Conversion priority, must be a value from 0 to 3, no duplicates"
+	default 0
+	depends on TIVA_ADC0_SSE3
+	---help---
+		Set the conversion priority for this SSE. Each ADC has 4 SSEs so the
+		order in which they are serviced is determined by this value.
+config TIVA_ADC0_SSE3_TRIGGER
+	int "Set the trigger source to start a SSE's conversion, see help for options"
+	default 0
+	depends on TIVA_ADC0_SSE3
+	---help---
+		Set the trigger source. The following values correspond to the
+		following triggers:
+		- 0x0: Processor (default)
+		- 0x1: *Analog Comparator 0
+		- 0x2: *Analog Comparator 1
+		- 0x3: *Analog Comparator 2
+		- 0x4: External (GPIO Pins)
+		- 0x5: Timer
+		- 0x6: **PWM generator 0
+		- 0x7: **PWM generator 1
+		- 0x8: **PWM generator 2
+		- 0x9: **PWM generator 3
+		- 0xE: Never Trigger
+		- 0xF: Always (continuously sample)
+
+		* Comparators are unsupported
+		** PWM triggering requires additional setup at runtime - There is a special
+		ADC IOCTL defined in the Tiva ADC driver for this purpose.
+
+menuconfig TIVA_ADC0_SSE3_STEP0
+	bool "Enable and configure ADC0 SSE3 step 0"
+	default n
+	depends on TIVA_ADC0_SSE3
+
+config TIVA_ADC0_SSE3_STEP0_TS
+	bool "This step will retrieve data from the on-chip temperature sensor."
+	default n
+	depends on TIVA_ADC0_SSE3_STEP0
+
+config TIVA_ADC0_SSE3_STEP0_AIN
+	int "Set the input AIN. See datasheet for pin to AIN mappings."
+	default 0
+	depends on TIVA_ADC0_SSE3_STEP0
 
 endmenu # Tiva ADC0 configuration
 endif # TIVA_ADC0
@@ -1311,157 +1308,157 @@ menuconfig TIVA_ADC1_SSE0
 		- priority
 		- input channel step assignment
 
-	config TIVA_ADC1_SSE0_PRIORITY
-		int "Conversion priority, must be a value from 0 to 3, no duplicates"
-		default 0
-		depends on TIVA_ADC1_SSE0
-		---help---
-			Set the conversion priority for this SSE. Each ADC has 4 SSEs so the
-			order in which they are serviced is determined by this value.
+config TIVA_ADC1_SSE0_PRIORITY
+	int "Conversion priority, must be a value from 0 to 3, no duplicates"
+	default 0
+	depends on TIVA_ADC1_SSE0
+	---help---
+		Set the conversion priority for this SSE. Each ADC has 4 SSEs so the
+		order in which they are serviced is determined by this value.
 
-	config TIVA_ADC1_SSE0_TRIGGER
-		int "Set the trigger source to start a SSE's conversion, see help for options"
-		default 0
-		depends on TIVA_ADC1_SSE0
-		---help---
-			Set the trigger source. The following values correspond to the
-			following triggers:
-			- 0x0: Processor (default)
-			- 0x1: *Analog Comparator 0
-			- 0x2: *Analog Comparator 1
-			- 0x3: *Analog Comparator 2
-			- 0x4: External (GPIO Pins)
-			- 0x5: Timer
-			- 0x6: **PWM generator 0
-			- 0x7: **PWM generator 1
-			- 0x8: **PWM generator 2
-			- 0x9: **PWM generator 3
-			- 0xE: Never Trigger
-			- 0xF: Always (continuously sample)
-
-			* Comparators are unsupported
-			** PWM triggering requires additional setup at runtime - There is a special
-			ADC IOCTL defined in the Tiva ADC driver for this purpose.
-
-		menuconfig TIVA_ADC1_SSE0_STEP0
-			bool "Enable and configure ADC1 SSE0 step 0"
-			default n
-			depends on TIVA_ADC1_SSE0
-
-			config TIVA_ADC1_SSE0_STEP0_TS
-				bool "This step will retrieve data from the on-chip temperature sensor."
-				default n
-				depends on TIVA_ADC1_SSE0_STEP0
-
-			config TIVA_ADC1_SSE0_STEP0_AIN
-				int "Set the input AIN. See datasheet for pin to AIN mappings."
-				default 0
-				depends on TIVA_ADC1_SSE0_STEP0
-
-		menuconfig TIVA_ADC1_SSE0_STEP1
-			bool "Enable and configure ADC1 SSE0 step 1"
-			default n
-			depends on TIVA_ADC1_SSE0
-
-			config TIVA_ADC1_SSE0_STEP1_TS
-				bool "This step will retrieve data from the on-chip temperature sensor."
-				default n
-				depends on TIVA_ADC1_SSE0_STEP1
-
-			config TIVA_ADC1_SSE0_STEP1_AIN
-				int "Set the input AIN. See datasheet for pin to AIN mappings."
-				default 0
-				depends on TIVA_ADC1_SSE0_STEP1
-
-		menuconfig TIVA_ADC1_SSE0_STEP2
-			bool "Enable and configure ADC1 SSE0 step 2"
-			default n
-			depends on TIVA_ADC1_SSE0
-
-			config TIVA_ADC1_SSE0_STEP2_TS
-				bool "This step will retrieve data from the on-chip temperature sensor."
-				default n
-				depends on TIVA_ADC1_SSE0_STEP2
-
-			config TIVA_ADC1_SSE0_STEP2_AIN
-				int "Set the input AIN. See datasheet for pin to AIN mappings."
-				default 0
-				depends on TIVA_ADC1_SSE0_STEP2
-
-		menuconfig TIVA_ADC1_SSE0_STEP3
-			bool "Enable and configure ADC1 SSE0 step 3"
-			default n
-			depends on TIVA_ADC1_SSE0
-
-			config TIVA_ADC1_SSE0_STEP3_TS
-				bool "This step will retrieve data from the on-chip temperature sensor."
-				default n
-				depends on TIVA_ADC1_SSE0_STEP3
-
-			config TIVA_ADC1_SSE0_STEP3_AIN
-				int "Set the input AIN. See datasheet for pin to AIN mappings."
-				default 0
-				depends on TIVA_ADC1_SSE0_STEP3
-
-		menuconfig TIVA_ADC1_SSE0_STEP4
-			bool "Enable and configure ADC1 SSE0 step 4"
-			default n
-			depends on TIVA_ADC1_SSE0
-
-			config TIVA_ADC1_SSE0_STEP4_TS
-				bool "This step will retrieve data from the on-chip temperature sensor."
-				default n
-				depends on TIVA_ADC1_SSE0_STEP4
-
-			config TIVA_ADC1_SSE0_STEP4_AIN
-				int "Set the input AIN. See datasheet for pin to AIN mappings."
-				default 0
-				depends on TIVA_ADC1_SSE0_STEP4
-
-		menuconfig TIVA_ADC1_SSE0_STEP5
-			bool "Enable and configure ADC1 SSE0 step 5"
-			default n
-			depends on TIVA_ADC1_SSE0
-
-			config TIVA_ADC1_SSE0_STEP5_TS
-				bool "This step will retrieve data from the on-chip temperature sensor."
-				default n
-				depends on TIVA_ADC1_SSE0_STEP5
-
-			config TIVA_ADC1_SSE0_STEP5_AIN
-				int "Set the input AIN. See datasheet for pin to AIN mappings."
-				default 0
-				depends on TIVA_ADC1_SSE0_STEP5
-
-		menuconfig TIVA_ADC1_SSE0_STEP6
-			bool "Enable and configure ADC1 SSE0 step 6"
-			default n
-			depends on TIVA_ADC1_SSE0
-
-			config TIVA_ADC1_SSE0_STEP6_TS
-				bool "This step will retrieve data from the on-chip temperature sensor."
-				default n
-				depends on TIVA_ADC1_SSE0_STEP6
-
-			config TIVA_ADC1_SSE0_STEP6_AIN
-				int "Set the input AIN. See datasheet for pin to AIN mappings."
-				default 0
-				depends on TIVA_ADC1_SSE0_STEP6
-
-		menuconfig TIVA_ADC1_SSE0_STEP7
-			bool "Enable and configure ADC1 SSE0 step 7"
-			default n
-			depends on TIVA_ADC1_SSE0
-
-			config TIVA_ADC1_SSE0_STEP7_TS
-				bool "This step will retrieve data from the on-chip temperature sensor."
-				default n
-				depends on TIVA_ADC1_SSE0_STEP7
-
-			config TIVA_ADC1_SSE0_STEP7_AIN
-				int "Set the input AIN. See datasheet for pin to AIN mappings."
-				default 0
-				depends on TIVA_ADC1_SSE0_STEP7
+config TIVA_ADC1_SSE0_TRIGGER
+	int "Set the trigger source to start a SSE's conversion, see help for options"
+	default 0
+	depends on TIVA_ADC1_SSE0
+	---help---
+		Set the trigger source. The following values correspond to the
+		following triggers:
+		- 0x0: Processor (default)
+		- 0x1: *Analog Comparator 0
+		- 0x2: *Analog Comparator 1
+		- 0x3: *Analog Comparator 2
+		- 0x4: External (GPIO Pins)
+		- 0x5: Timer
+		- 0x6: **PWM generator 0
+		- 0x7: **PWM generator 1
+		- 0x8: **PWM generator 2
+		- 0x9: **PWM generator 3
+		- 0xE: Never Trigger
+		- 0xF: Always (continuously sample)
+
+		* Comparators are unsupported
+		** PWM triggering requires additional setup at runtime - There is a special
+		ADC IOCTL defined in the Tiva ADC driver for this purpose.
+
+menuconfig TIVA_ADC1_SSE0_STEP0
+	bool "Enable and configure ADC1 SSE0 step 0"
+	default n
+	depends on TIVA_ADC1_SSE0
+
+config TIVA_ADC1_SSE0_STEP0_TS
+	bool "This step will retrieve data from the on-chip temperature sensor."
+	default n
+	depends on TIVA_ADC1_SSE0_STEP0
+
+config TIVA_ADC1_SSE0_STEP0_AIN
+	int "Set the input AIN. See datasheet for pin to AIN mappings."
+	default 0
+	depends on TIVA_ADC1_SSE0_STEP0
+
+menuconfig TIVA_ADC1_SSE0_STEP1
+	bool "Enable and configure ADC1 SSE0 step 1"
+	default n
+	depends on TIVA_ADC1_SSE0
+
+config TIVA_ADC1_SSE0_STEP1_TS
+	bool "This step will retrieve data from the on-chip temperature sensor."
+	default n
+	depends on TIVA_ADC1_SSE0_STEP1
+
+config TIVA_ADC1_SSE0_STEP1_AIN
+	int "Set the input AIN. See datasheet for pin to AIN mappings."
+	default 0
+	depends on TIVA_ADC1_SSE0_STEP1
+
+menuconfig TIVA_ADC1_SSE0_STEP2
+	bool "Enable and configure ADC1 SSE0 step 2"
+	default n
+	depends on TIVA_ADC1_SSE0
+
+config TIVA_ADC1_SSE0_STEP2_TS
+	bool "This step will retrieve data from the on-chip temperature sensor."
+	default n
+	depends on TIVA_ADC1_SSE0_STEP2
+
+config TIVA_ADC1_SSE0_STEP2_AIN
+	int "Set the input AIN. See datasheet for pin to AIN mappings."
+	default 0
+	depends on TIVA_ADC1_SSE0_STEP2
+
+menuconfig TIVA_ADC1_SSE0_STEP3
+	bool "Enable and configure ADC1 SSE0 step 3"
+	default n
+	depends on TIVA_ADC1_SSE0
+
+config TIVA_ADC1_SSE0_STEP3_TS
+	bool "This step will retrieve data from the on-chip temperature sensor."
+	default n
+	depends on TIVA_ADC1_SSE0_STEP3
+
+config TIVA_ADC1_SSE0_STEP3_AIN
+	int "Set the input AIN. See datasheet for pin to AIN mappings."
+	default 0
+	depends on TIVA_ADC1_SSE0_STEP3
+
+menuconfig TIVA_ADC1_SSE0_STEP4
+	bool "Enable and configure ADC1 SSE0 step 4"
+	default n
+	depends on TIVA_ADC1_SSE0
+
+config TIVA_ADC1_SSE0_STEP4_TS
+	bool "This step will retrieve data from the on-chip temperature sensor."
+	default n
+	depends on TIVA_ADC1_SSE0_STEP4
+
+config TIVA_ADC1_SSE0_STEP4_AIN
+	int "Set the input AIN. See datasheet for pin to AIN mappings."
+	default 0
+	depends on TIVA_ADC1_SSE0_STEP4
+
+menuconfig TIVA_ADC1_SSE0_STEP5
+	bool "Enable and configure ADC1 SSE0 step 5"
+	default n
+	depends on TIVA_ADC1_SSE0
+
+config TIVA_ADC1_SSE0_STEP5_TS
+	bool "This step will retrieve data from the on-chip temperature sensor."
+	default n
+	depends on TIVA_ADC1_SSE0_STEP5
+
+config TIVA_ADC1_SSE0_STEP5_AIN
+	int "Set the input AIN. See datasheet for pin to AIN mappings."
+	default 0
+	depends on TIVA_ADC1_SSE0_STEP5
+
+menuconfig TIVA_ADC1_SSE0_STEP6
+	bool "Enable and configure ADC1 SSE0 step 6"
+	default n
+	depends on TIVA_ADC1_SSE0
+
+config TIVA_ADC1_SSE0_STEP6_TS
+	bool "This step will retrieve data from the on-chip temperature sensor."
+	default n
+	depends on TIVA_ADC1_SSE0_STEP6
+
+config TIVA_ADC1_SSE0_STEP6_AIN
+	int "Set the input AIN. See datasheet for pin to AIN mappings."
+	default 0
+	depends on TIVA_ADC1_SSE0_STEP6
+
+menuconfig TIVA_ADC1_SSE0_STEP7
+	bool "Enable and configure ADC1 SSE0 step 7"
+	default n
+	depends on TIVA_ADC1_SSE0
+
+config TIVA_ADC1_SSE0_STEP7_TS
+	bool "This step will retrieve data from the on-chip temperature sensor."
+	default n
+	depends on TIVA_ADC1_SSE0_STEP7
+
+config TIVA_ADC1_SSE0_STEP7_AIN
+	int "Set the input AIN. See datasheet for pin to AIN mappings."
+	default 0
+	depends on TIVA_ADC1_SSE0_STEP7
 
 menuconfig TIVA_ADC1_SSE1
 	bool "Enable and configure ADC1 SSE1"
@@ -1475,97 +1472,96 @@ menuconfig TIVA_ADC1_SSE1
 		- priority
 		- input channel step assignment
 
-	config TIVA_ADC1_SSE1_PRIORITY
-		int "Conversion priority, must be a value from 0 to 3, no duplicates"
-		default 0
-		depends on TIVA_ADC1_SSE1
-		---help---
-			Set the conversion priority for this SSE. Each ADC has 4 SSEs so the
-			order in which they are serviced is determined by this value.
+config TIVA_ADC1_SSE1_PRIORITY
+	int "Conversion priority, must be a value from 0 to 3, no duplicates"
+	default 0
+	depends on TIVA_ADC1_SSE1
+	---help---
+		Set the conversion priority for this SSE. Each ADC has 4 SSEs so the
+		order in which they are serviced is determined by this value.
+config TIVA_ADC1_SSE1_TRIGGER
+	int "Set the trigger source to start a SSE's conversion, see help for options"
+	default 0
+	depends on TIVA_ADC1_SSE1
+	---help---
+		Set the trigger source. The following values correspond to the
+		following triggers:
+		- 0x0: Processor (default)
+		- 0x1: *Analog Comparator 0
+		- 0x2: *Analog Comparator 1
+		- 0x3: *Analog Comparator 2
+		- 0x4: External (GPIO Pins)
+		- 0x5: Timer
+		- 0x6: **PWM generator 0
+		- 0x7: **PWM generator 1
+		- 0x8: **PWM generator 2
+		- 0x9: **PWM generator 3
+		- 0xE: Never Trigger
+		- 0xF: Always (continuously sample)
+
+		* Comparators are unsupported
+		** PWM triggering requires additional setup at runtime - There is a special
+		ADC IOCTL defined in the Tiva ADC driver for this purpose.
+
+menuconfig TIVA_ADC1_SSE1_STEP0
+	bool "Enable and configure ADC1 SSE1 step 0"
+	default n
+	depends on TIVA_ADC1_SSE1
+
+config TIVA_ADC1_SSE1_STEP0_TS
+	bool "This step will retrieve data from the on-chip temperature sensor."
+	default n
+	depends on TIVA_ADC1_SSE1_STEP0
+
+config TIVA_ADC1_SSE1_STEP0_AIN
+	int "Set the input AIN. See datasheet for pin to AIN mappings."
+	default 0
+	depends on TIVA_ADC1_SSE1_STEP0
 
-	config TIVA_ADC1_SSE1_TRIGGER
-		int "Set the trigger source to start a SSE's conversion, see help for options"
-		default 0
-		depends on TIVA_ADC1_SSE1
-		---help---
-			Set the trigger source. The following values correspond to the
-			following triggers:
-			- 0x0: Processor (default)
-			- 0x1: *Analog Comparator 0
-			- 0x2: *Analog Comparator 1
-			- 0x3: *Analog Comparator 2
-			- 0x4: External (GPIO Pins)
-			- 0x5: Timer
-			- 0x6: **PWM generator 0
-			- 0x7: **PWM generator 1
-			- 0x8: **PWM generator 2
-			- 0x9: **PWM generator 3
-			- 0xE: Never Trigger
-			- 0xF: Always (continuously sample)
-
-			* Comparators are unsupported
-			** PWM triggering requires additional setup at runtime - There is a special
-			ADC IOCTL defined in the Tiva ADC driver for this purpose.
-
-		menuconfig TIVA_ADC1_SSE1_STEP0
-			bool "Enable and configure ADC1 SSE1 step 0"
-			default n
-			depends on TIVA_ADC1_SSE1
-
-			config TIVA_ADC1_SSE1_STEP0_TS
-				bool "This step will retrieve data from the on-chip temperature sensor."
-				default n
-				depends on TIVA_ADC1_SSE1_STEP0
-
-			config TIVA_ADC1_SSE1_STEP0_AIN
-				int "Set the input AIN. See datasheet for pin to AIN mappings."
-				default 0
-				depends on TIVA_ADC1_SSE1_STEP0
-
-		menuconfig TIVA_ADC1_SSE1_STEP1
-			bool "Enable and configure ADC1 SSE1 step 1"
-			default n
-			depends on TIVA_ADC1_SSE1
-
-			config TIVA_ADC1_SSE1_STEP1_TS
-				bool "This step will retrieve data from the on-chip temperature sensor."
-				default n
-				depends on TIVA_ADC1_SSE1_STEP1
-
-			config TIVA_ADC1_SSE1_STEP1_AIN
-				int "Set the input AIN. See datasheet for pin to AIN mappings."
-				default 0
-				depends on TIVA_ADC1_SSE1_STEP1
-
-		menuconfig TIVA_ADC1_SSE1_STEP2
-			bool "Enable and configure ADC1 SSE1 step 2"
-			default n
-			depends on TIVA_ADC1_SSE1
-
-			config TIVA_ADC1_SSE1_STEP2_TS
-				bool "This step will retrieve data from the on-chip temperature sensor."
-				default n
-				depends on TIVA_ADC1_SSE1_STEP2
-
-			config TIVA_ADC1_SSE1_STEP2_AIN
-				int "Set the input AIN. See datasheet for pin to AIN mappings."
-				default 0
-				depends on TIVA_ADC1_SSE1_STEP2
-
-		menuconfig TIVA_ADC1_SSE1_STEP3
-			bool "Enable and configure ADC1 SSE1 step 3"
-			default n
-			depends on TIVA_ADC1_SSE1
-
-			config TIVA_ADC1_SSE1_STEP3_TS
-				bool "This step will retrieve data from the on-chip temperature sensor."
-				default n
-				depends on TIVA_ADC1_SSE1_STEP3
-
-			config TIVA_ADC1_SSE1_STEP3_AIN
-				int "Set the input AIN. See datasheet for pin to AIN mappings."
-				default 0
-				depends on TIVA_ADC1_SSE1_STEP3
+menuconfig TIVA_ADC1_SSE1_STEP1
+	bool "Enable and configure ADC1 SSE1 step 1"
+	default n
+	depends on TIVA_ADC1_SSE1
+
+config TIVA_ADC1_SSE1_STEP1_TS
+	bool "This step will retrieve data from the on-chip temperature sensor."
+	default n
+	depends on TIVA_ADC1_SSE1_STEP1
+
+config TIVA_ADC1_SSE1_STEP1_AIN
+	int "Set the input AIN. See datasheet for pin to AIN mappings."
+	default 0
+	depends on TIVA_ADC1_SSE1_STEP1
+
+menuconfig TIVA_ADC1_SSE1_STEP2
+	bool "Enable and configure ADC1 SSE1 step 2"
+	default n
+	depends on TIVA_ADC1_SSE1
+
+config TIVA_ADC1_SSE1_STEP2_TS
+	bool "This step will retrieve data from the on-chip temperature sensor."
+	default n
+	depends on TIVA_ADC1_SSE1_STEP2
+
+config TIVA_ADC1_SSE1_STEP2_AIN
+	int "Set the input AIN. See datasheet for pin to AIN mappings."
+	default 0
+	depends on TIVA_ADC1_SSE1_STEP2
+
+menuconfig TIVA_ADC1_SSE1_STEP3
+	bool "Enable and configure ADC1 SSE1 step 3"
+	default n
+	depends on TIVA_ADC1_SSE1
+
+config TIVA_ADC1_SSE1_STEP3_TS
+	bool "This step will retrieve data from the on-chip temperature sensor."
+	default n
+	depends on TIVA_ADC1_SSE1_STEP3
+
+config TIVA_ADC1_SSE1_STEP3_AIN
+	int "Set the input AIN. See datasheet for pin to AIN mappings."
+	default 0
+	depends on TIVA_ADC1_SSE1_STEP3
 
 menuconfig TIVA_ADC1_SSE2
 	bool "Enable and configure ADC1 SSE2"
@@ -1579,98 +1575,97 @@ menuconfig TIVA_ADC1_SSE2
 		- priority
 		- input channel step assignment
 
-	config TIVA_ADC1_SSE2_PRIORITY
-		int "Conversion priority, must be a value from 0 to 3, no duplicates"
-		default 0
-		depends on TIVA_ADC1_SSE2
-		---help---
-			Set the conversion priority for this SSE. Each ADC has 4 SSEs so the
-			order in which they are serviced is determined by this value.
+config TIVA_ADC1_SSE2_PRIORITY
+	int "Conversion priority, must be a value from 0 to 3, no duplicates"
+	default 0
+	depends on TIVA_ADC1_SSE2
+	---help---
+		Set the conversion priority for this SSE. Each ADC has 4 SSEs so the
+		order in which they are serviced is determined by this value.
+config TIVA_ADC1_SSE2_TRIGGER
+	int "Set the trigger source to start a SSE's conversion, see help for options"
+	default 0
+	range 0 15
+	depends on TIVA_ADC1_SSE2
+	---help---
+		Set the trigger source. The following values correspond to the
+		following triggers:
+		- 0x0: Processor (default)
+		- 0x1: *Analog Comparator 0
+		- 0x2: *Analog Comparator 1
+		- 0x3: *Analog Comparator 2
+		- 0x4: External (GPIO Pins)
+		- 0x5: Timer
+		- 0x6: **PWM generator 0
+		- 0x7: **PWM generator 1
+		- 0x8: **PWM generator 2
+		- 0x9: **PWM generator 3
+		- 0xE: Never Trigger
+		- 0xF: Always (continuously sample)
+
+		* Comparators are unsupported
+		** PWM triggering requires additional setup at runtime - There is a special
+		ADC IOCTL defined in the Tiva ADC driver for this purpose.
+
+menuconfig TIVA_ADC1_SSE2_STEP0
+	bool "Enable and configure ADC1 SSE2 step 0"
+	default n
+	depends on TIVA_ADC1_SSE2
+
+config TIVA_ADC1_SSE2_STEP0_TS
+	bool "This step will retrieve data from the on-chip temperature sensor."
+	default n
+	depends on TIVA_ADC1_SSE2_STEP0
+
+config TIVA_ADC1_SSE2_STEP0_AIN
+	int "Set the input AIN. See datasheet for pin to AIN mappings."
+	default 0
+	depends on TIVA_ADC1_SSE2_STEP0
 
-	config TIVA_ADC1_SSE2_TRIGGER
-		int "Set the trigger source to start a SSE's conversion, see help for options"
-		default 0
-		range 0 15
-		depends on TIVA_ADC1_SSE2
-		---help---
-			Set the trigger source. The following values correspond to the
-			following triggers:
-			- 0x0: Processor (default)
-			- 0x1: *Analog Comparator 0
-			- 0x2: *Analog Comparator 1
-			- 0x3: *Analog Comparator 2
-			- 0x4: External (GPIO Pins)
-			- 0x5: Timer
-			- 0x6: **PWM generator 0
-			- 0x7: **PWM generator 1
-			- 0x8: **PWM generator 2
-			- 0x9: **PWM generator 3
-			- 0xE: Never Trigger
-			- 0xF: Always (continuously sample)
-
-			* Comparators are unsupported
-			** PWM triggering requires additional setup at runtime - There is a special
-			ADC IOCTL defined in the Tiva ADC driver for this purpose.
-
-		menuconfig TIVA_ADC1_SSE2_STEP0
-			bool "Enable and configure ADC1 SSE2 step 0"
-			default n
-			depends on TIVA_ADC1_SSE2
-
-			config TIVA_ADC1_SSE2_STEP0_TS
-				bool "This step will retrieve data from the on-chip temperature sensor."
-				default n
-				depends on TIVA_ADC1_SSE2_STEP0
-
-			config TIVA_ADC1_SSE2_STEP0_AIN
-				int "Set the input AIN. See datasheet for pin to AIN mappings."
-				default 0
-				depends on TIVA_ADC1_SSE2_STEP0
-
-		menuconfig TIVA_ADC1_SSE2_STEP1
-			bool "Enable and configure ADC1 SSE2 step 1"
-			default n
-			depends on TIVA_ADC1_SSE2
-
-			config TIVA_ADC1_SSE2_STEP1_TS
-				bool "This step will retrieve data from the on-chip temperature sensor."
-				default n
-				depends on TIVA_ADC1_SSE2_STEP1
-
-			config TIVA_ADC1_SSE2_STEP1_AIN
-				int "Set the input AIN. See datasheet for pin to AIN mappings."
-				default 0
-				depends on TIVA_ADC1_SSE2_STEP1
-
-		menuconfig TIVA_ADC1_SSE2_STEP2
-			bool "Enable and configure ADC1 SSE2 step 2"
-			default n
-			depends on TIVA_ADC1_SSE2
-
-			config TIVA_ADC1_SSE2_STEP2_TS
-				bool "This step will retrieve data from the on-chip temperature sensor."
-				default n
-				depends on TIVA_ADC1_SSE2_STEP2
-
-			config TIVA_ADC1_SSE2_STEP2_AIN
-				int "Set the input AIN. See datasheet for pin to AIN mappings."
-				default 0
-				depends on TIVA_ADC1_SSE2_STEP2
-
-		menuconfig TIVA_ADC1_SSE2_STEP3
-			bool "Enable and configure ADC1 SSE2 step 3"
-			default n
-			depends on TIVA_ADC1_SSE2
-
-			config TIVA_ADC1_SSE2_STEP3_TS
-				bool "This step will retrieve data from the on-chip temperature sensor."
-				default n
-				depends on TIVA_ADC1_SSE2_STEP3
-
-			config TIVA_ADC1_SSE2_STEP3_AIN
-				int "Set the input AIN. See datasheet for pin to AIN mappings."
-				default 0
-				depends on TIVA_ADC1_SSE2_STEP3
+menuconfig TIVA_ADC1_SSE2_STEP1
+	bool "Enable and configure ADC1 SSE2 step 1"
+	default n
+	depends on TIVA_ADC1_SSE2
+
+config TIVA_ADC1_SSE2_STEP1_TS
+	bool "This step will retrieve data from the on-chip temperature sensor."
+	default n
+	depends on TIVA_ADC1_SSE2_STEP1
+
+config TIVA_ADC1_SSE2_STEP1_AIN
+	int "Set the input AIN. See datasheet for pin to AIN mappings."
+	default 0
+	depends on TIVA_ADC1_SSE2_STEP1
+
+menuconfig TIVA_ADC1_SSE2_STEP2
+	bool "Enable and configure ADC1 SSE2 step 2"
+	default n
+	depends on TIVA_ADC1_SSE2
+
+config TIVA_ADC1_SSE2_STEP2_TS
+	bool "This step will retrieve data from the on-chip temperature sensor."
+	default n
+	depends on TIVA_ADC1_SSE2_STEP2
+
+config TIVA_ADC1_SSE2_STEP2_AIN
+	int "Set the input AIN. See datasheet for pin to AIN mappings."
+	default 0
+	depends on TIVA_ADC1_SSE2_STEP2
+
+menuconfig TIVA_ADC1_SSE2_STEP3
+	bool "Enable and configure ADC1 SSE2 step 3"
+	default n
+	depends on TIVA_ADC1_SSE2
+
+config TIVA_ADC1_SSE2_STEP3_TS
+	bool "This step will retrieve data from the on-chip temperature sensor."
+	default n
+	depends on TIVA_ADC1_SSE2_STEP3
+
+config TIVA_ADC1_SSE2_STEP3_AIN
+	int "Set the input AIN. See datasheet for pin to AIN mappings."
+	default 0
+	depends on TIVA_ADC1_SSE2_STEP3
 
 menuconfig TIVA_ADC1_SSE3
 	bool "Enable and configure ADC1 SSE3"
@@ -1684,52 +1679,51 @@ menuconfig TIVA_ADC1_SSE3
 		- priority
 		- input channel step assignment
 
-	config TIVA_ADC1_SSE3_PRIORITY
-		int "Conversion priority, must be a value from 0 to 3, no duplicates"
-		default 0
+config TIVA_ADC1_SSE3_PRIORITY
+	int "Conversion priority, must be a value from 0 to 3, no duplicates"
+	default 0
+	depends on TIVA_ADC1_SSE3
+	---help---
+		Set the conversion priority for this SSE. Each ADC has 4 SSEs so the
+		order in which they are serviced is determined by this value.
+config TIVA_ADC1_SSE3_TRIGGER
+	int "Set the trigger source to start a SSE's conversion, see help for options"
+	default 0
+	depends on TIVA_ADC1_SSE3
+	---help---
+		Set the trigger source. The following values correspond to the
+		following triggers:
+		- 0x0: Processor (default)
+		- 0x1: *Analog Comparator 0
+		- 0x2: *Analog Comparator 1
+		- 0x3: *Analog Comparator 2
+		- 0x4: External (GPIO Pins)
+		- 0x5: Timer
+		- 0x6: **PWM generator 0
+		- 0x7: **PWM generator 1
+		- 0x8: **PWM generator 2
+		- 0x9: **PWM generator 3
+		- 0xE: Never Trigger
+		- 0xF: Always (continuously sample)
+
+		* Comparators are unsupported
+		** PWM triggering requires additional setup at runtime - There is a special
+		ADC IOCTL defined in the Tiva ADC driver for this purpose.
+
+	menuconfig TIVA_ADC1_SSE3_STEP0
+		bool "Enable and configure ADC1 SSE3 step 0"
+		default n
 		depends on TIVA_ADC1_SSE3
-		---help---
-			Set the conversion priority for this SSE. Each ADC has 4 SSEs so the
-			order in which they are serviced is determined by this value.
 
-	config TIVA_ADC1_SSE3_TRIGGER
-		int "Set the trigger source to start a SSE's conversion, see help for options"
+	config TIVA_ADC1_SSE3_STEP0_TS
+		bool "This step will retrieve data from the on-chip temperature sensor."
+		default n
+		depends on TIVA_ADC1_SSE3_STEP0
+
+	config TIVA_ADC1_SSE3_STEP0_AIN
+		int "Set the input AIN. See datasheet for pin to AIN mappings."
 		default 0
-		depends on TIVA_ADC1_SSE3
-		---help---
-			Set the trigger source. The following values correspond to the
-			following triggers:
-			- 0x0: Processor (default)
-			- 0x1: *Analog Comparator 0
-			- 0x2: *Analog Comparator 1
-			- 0x3: *Analog Comparator 2
-			- 0x4: External (GPIO Pins)
-			- 0x5: Timer
-			- 0x6: **PWM generator 0
-			- 0x7: **PWM generator 1
-			- 0x8: **PWM generator 2
-			- 0x9: **PWM generator 3
-			- 0xE: Never Trigger
-			- 0xF: Always (continuously sample)
-
-			* Comparators are unsupported
-			** PWM triggering requires additional setup at runtime - There is a special
-			ADC IOCTL defined in the Tiva ADC driver for this purpose.
-
-		menuconfig TIVA_ADC1_SSE3_STEP0
-			bool "Enable and configure ADC1 SSE3 step 0"
-			default n
-			depends on TIVA_ADC1_SSE3
-
-			config TIVA_ADC1_SSE3_STEP0_TS
-				bool "This step will retrieve data from the on-chip temperature sensor."
-				default n
-				depends on TIVA_ADC1_SSE3_STEP0
-
-			config TIVA_ADC1_SSE3_STEP0_AIN
-				int "Set the input AIN. See datasheet for pin to AIN mappings."
-				default 0
-				depends on TIVA_ADC1_SSE3_STEP0
+		depends on TIVA_ADC1_SSE3_STEP0
 
 endmenu # Tiva ADC1 configuration
 endif # TIVA_ADC1
diff --git a/nuttx/arch/arm/src/tiva/tiva_adc.c b/nuttx/arch/arm/src/tiva/tiva_adc.c
index 622b80a88..ecf915904 100644
--- a/nuttx/arch/arm/src/tiva/tiva_adc.c
+++ b/nuttx/arch/arm/src/tiva/tiva_adc.c
@@ -46,10 +46,10 @@
  * This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
  *****************************************************************************/
 
-/* Keeping in mind that for every step there should be another entry in the
+/* Keep in mind that for every step there should be another entry in the
  * CONFIG_ADC_FIFOSIZE value.
- * e.g. if there are 12 steps in use; CONFIG_ADC_FIFOSIZE > 12+1
- *      if there are  3 steps in use; CONFIG_ADC_FIFOSIZE > 3+1
+ * e.g. if there are 12 steps in use; CONFIG_ADC_FIFOSIZE = 12+1 = 13
+ *      if there are  3 steps in use; CONFIG_ADC_FIFOSIZE = 3+1 = 4
  */
 
 /****************************************************************************
@@ -94,129 +94,123 @@
 
 /* Misc utility defines *****************************************************/
 
-#define GIGA 1000000000       /* 10E9 */
-#define MEGA    1000000       /* 10E6 */
-#define KILO       1000       /* 10E3 */
+#  define TIVA_ADC_ENABLE  true
+#  define TIVA_ADC_DISABLE false
 
-#define ENABLE  true
-#define DISABLE false
+#  define TIVA_ADC_RESOLUTION 4095
 
-#define TIVA_ADC_SCALE 4095
-
-#ifdef CONFIG_ARCH_CHIP_TM4C123
-#  define TIVA_ADC_CLOCK_MAX (16 * MEGA)
-#  define TIVA_ADC_CLOCK_MIN (16 * MEGA)
-#elif CONFIG_ARCH_CHIP_TM4C129
-#  define TIVA_ADC_CLOCK_MAX (32 * MEGA)
-#  define TIVA_ADC_CLOCK_MIN (16 * MEGA)
-#else
-#  error TIVA_ADC_CLOCK: unsupported architecture
-#endif /* CONFIG_ARCH_CHIP_TM4C129 */
+#  ifdef CONFIG_ARCH_CHIP_TM4C123
+#    define TIVA_ADC_CLOCK_MAX (16000000)
+#    define TIVA_ADC_CLOCK_MIN (16000000)
+#  elif CONFIG_ARCH_CHIP_TM4C129
+#    define TIVA_ADC_CLOCK_MAX (32000000)
+#    define TIVA_ADC_CLOCK_MIN (16000000)
+#  else
+#    error TIVA_ADC_CLOCK: unsupported architecture
+#  endif                               /* CONFIG_ARCH_CHIP_TM4C129 */
 
 /* Allow the same function call to be used for sample rate */
 
-#ifdef CONFIG_ARCH_CHIP_TM4C123
-#  define TIVA_ADC_SAMPLE_RATE_SLOWEST  (ADC_PC_SR_125K)
-#  define TIVA_ADC_SAMPLE_RATE_SLOW     (ADC_PC_SR_250K)
-#  define TIVA_ADC_SAMPLE_RATE_FAST     (ADC_PC_SR_500K)
-#  define TIVA_ADC_SAMPLE_RATE_FASTEST  (ADC_PC_SR_1M)
-#elif CONFIG_ARCH_CHIP_TM4C129
-#  define TIVA_ADC_SAMPLE_RATE_SLOWEST  (ADC_PC_MCR_1_8)
-#  define TIVA_ADC_SAMPLE_RATE_SLOW     (ADC_PC_MCR_1_4)
-#  define TIVA_ADC_SAMPLE_RATE_FAST     (ADC_PC_MCR_1_2)
-#  define TIVA_ADC_SAMPLE_RATE_FASTEST  (ADC_PC_MCR_FULL)
-#else
-#  error TIVA_ADC_SAMPLE_RATE: unsupported architecture
-#endif /* CONFIG_ARCH_CHIP_TM4C12  */
+#  ifdef CONFIG_ARCH_CHIP_TM4C123
+#    define TIVA_ADC_SAMPLE_RATE_SLOWEST  (ADC_PC_SR_125K)
+#    define TIVA_ADC_SAMPLE_RATE_SLOW     (ADC_PC_SR_250K)
+#    define TIVA_ADC_SAMPLE_RATE_FAST     (ADC_PC_SR_500K)
+#    define TIVA_ADC_SAMPLE_RATE_FASTEST  (ADC_PC_SR_1M)
+#  elif CONFIG_ARCH_CHIP_TM4C129
+#    define TIVA_ADC_SAMPLE_RATE_SLOWEST  (ADC_PC_MCR_1_8)
+#    define TIVA_ADC_SAMPLE_RATE_SLOW     (ADC_PC_MCR_1_4)
+#    define TIVA_ADC_SAMPLE_RATE_FAST     (ADC_PC_MCR_1_2)
+#    define TIVA_ADC_SAMPLE_RATE_FASTEST  (ADC_PC_MCR_FULL)
+#  else
+#    error TIVA_ADC_SAMPLE_RATE: unsupported architecture
+#  endif                               /* CONFIG_ARCH_CHIP_TM4C12* */
 
 /* Configuration ************************************************************/
 
-#ifndef CONFIG_TIVA_ADC_CLOCK
-#  define CONFIG_TIVA_ADC_CLOCK TIVA_ADC_CLOCK_MIN
-#endif
+#  ifndef CONFIG_TIVA_ADC_CLOCK
+#    define CONFIG_TIVA_ADC_CLOCK TIVA_ADC_CLOCK_MIN
+#  endif
 
-#ifdef CONFIG_TIVA_ADC_VREF
-#  ifndef CONFIG_ARCH_CHIP_TM4C129
-#    error Voltage reference selection only supported in TM4C129 parts
-#  endif /* CONFIG_ARCH_CHIP_TM4C129 */
-#endif /* CONFIG_TIVA_ADC_VREF */
+#  ifdef CONFIG_TIVA_ADC_VREF
+#    ifndef CONFIG_ARCH_CHIP_TM4C129
+#      error Voltage reference selection only supported in TM4C129 parts
+#    endif                             /* CONFIG_ARCH_CHIP_TM4C129 */
+#  endif                               /* CONFIG_TIVA_ADC_VREF */
 
-#ifdef CONFIG_TIVA_ADC_ALT_CLK
-#  warning CONFIG_TIVA_ADC_ALT_CLK unsupported.
-#endif /* CONFIG_TIVA_ADC_ALT_CLK */
+#  ifdef CONFIG_TIVA_ADC_ALT_CLK
+#    warning CONFIG_TIVA_ADC_ALT_CLK unsupported.
+#  endif                               /* CONFIG_TIVA_ADC_ALT_CLK */
 
 /* Utility macros ***********************************************************/
 
-/* Sequencer level */
-
 /* PWM trigger support definitions ******************************************/
 
 /* Decodes the PWM generator and module from trigger and converts
  * to the TSSEL_PS register
  */
 
-#define ADC_TRIG_PWM_CFG(t) \
+#  define ADC_TRIG_PWM_CFG(t) \
     (1<<(ADC_TSSEL_PS_SHIFT(ADC_TRIG_PWM_GEN(t))))
 
-/* ADC support definitions ***************************************************/
+/* ADC support definitions **************************************************/
 
-#define ADC_CHN_AIN(n)   GPIO_ADC_AIN##n
-#define TIVA_ADC_PIN(n)  ADC_CHN_AIN(n)
+#  define ADC_CHN_AIN(n)   GPIO_ADC_AIN##n
+#  define TIVA_ADC_PIN(n)  ADC_CHN_AIN(n)
 
-#define SSE_PROC_TRIG(n)  (1 << (n))
-#define SSE_PROC_TRIG_ALL (0xF)
+#  define SSE_PROC_TRIG(n)  (1 << (n))
+#  define SSE_PROC_TRIG_ALL (0xF)
 
-#define SSE_IDX(a,s)      (((a)*SSE_PER_BASE) + (s))
+#  define SSE_IDX(a,s)      (((a)*SSE_PER_BASE) + (s))
 
-#define MAX_NORMAL_CHN 15
-#define BASE_PER_ADC   2
-#define SSE_PER_BASE   4
-#define SSE_MAX_STEP   8
-#define NUM_SSE(n)     (sizeof(n)/sizeof(n[0]))
+#  define MAX_NORMAL_CHN 15
+#  define BASE_PER_ADC   2
+#  define SSE_PER_BASE   4
+#  define SSE_MAX_STEP   8
+#  define NUM_SSE(n)     (sizeof(n)/sizeof(n[0]))
 
-#define GET_AIN(a,s,c) (uint8_t)((getreg32( \
+#  define GET_AIN(a,s,c) (uint8_t)((getreg32( \
     TIVA_ADC_BASE(a)+TIVA_ADC_SSMUX(s)) & ADC_SSMUX_MUX_MASK(c)) >> ADC_SSMUX_MUX_SHIFT(c))
 
-#define ADC_SSE_STEP_NULL 0xFF
+#  define ADC_SSE_STEP_NULL 0xFF
 
-#define CLOCK_CONFIG(div, src) \
+#  define CLOCK_CONFIG(div, src) \
     ( ((((div) << ADC_CC_CLKDIV_SHIFT) & ADC_CC_CLKDIV_MASK) | \
     ((src) & ADC_CC_CS_MASK)) & (ADC_CC_CLKDIV_MASK + ADC_CC_CS_MASK) )
 
-#define SEM_PROCESS_PRIVATE 0
-#define SEM_PROCESS_SHARED  1
+#  define SEM_PROCESS_PRIVATE 0
+#  define SEM_PROCESS_SHARED  1
 
-/* Debug *********************************************************************/
+/* Debug ********************************************************************/
 
 /* CONFIG_DEBUG_ADC + CONFIG_DEBUG enables general ADC debug output. */
 
-#ifdef CONFIG_DEBUG_ADC
-#  define adcdbg dbg
-#  define adcvdbg vdbg
-#else
-#  define adcdbg(x...)
-#  define adcvdbg(x...)
-#endif
-
-#ifndef CONFIG_DEBUG
-#  undef CONFIG_TIVA_ADC_REGDEBUG
-#endif
-
-/* ADC event trace logic.  NOTE:  trace uses the internal, non-standard,
- * low-level debug interface syslog() but does not require that any other
- * debug is enabled.
+#  ifdef CONFIG_DEBUG_ADC
+#    define adcdbg dbg
+#    define adcvdbg vdbg
+#  else
+#    define adcdbg(x...)
+#    define adcvdbg(x...)
+#  endif
+
+#  ifndef CONFIG_DEBUG
+#    undef CONFIG_TIVA_ADC_REGDEBUG
+#  endif
+
+/* ADC event trace logic.  NOTE:  trace uses the internal, non-standard, low-level
+ * debug interface syslog() but does not require that any other debug
+ * is enabled.
  */
 
-#ifndef CONFIG_ADC_TRACE
-#  define tiva_adc_tracereset(p)
-#  define tiva_adc_tracenew(p,s)
-#  define tiva_adc_traceevent(p,e,a)
-#  define tiva_adc_tracedump(p)
-#endif
+#  ifndef CONFIG_ADC_TRACE
+#    define tiva_adc_tracereset(p)
+#    define tiva_adc_tracenew(p,s)
+#    define tiva_adc_traceevent(p,e,a)
+#    define tiva_adc_tracedump(p)
+#  endif
 
-#ifndef CONFIG_ADC_NTRACE
-#  define CONFIG_ADC_NTRACE 32
-#endif
+#  ifndef CONFIG_ADC_NTRACE
+#    define CONFIG_ADC_NTRACE 32
+#  endif
 
 /****************************************************************************
  * Public Functions
@@ -250,7 +244,6 @@ static const struct adc_ops_s g_adcops =
  ****************************************************************************/
 
 /* tracks overall ADC peripherals one-time initialization state */
-
 struct tiva_adc_state_s
 {
   bool init[BASE_PER_ADC];
@@ -264,20 +257,17 @@ struct tiva_adc_s
   uint8_t devno;              /* ADC device number */
   struct tiva_adc_sse_s *sse[SSE_PER_BASE];   /* Sample sequencer operation
                                                * state */
-
   /* Debug stuff */
-
-#ifdef CONFIG_TIVA_ADC_REGDEBUG
+#  ifdef CONFIG_TIVA_ADC_REGDEBUG
   bool wrlast;                /* Last was a write */
   uintptr_t addrlast;         /* Last address */
   uint32_t vallast;           /* Last value */
   int ntimes;                 /* Number of times */
-#endif /* CONFIG_TIVA_ADC_REGDEBUG */
+#  endif                        /* CONFIG_TIVA_ADC_REGDEBUG */
 };
 
 struct tiva_adc_sse_s
 {
-//struct works_s work;        /* Supports the interrupt handling "bottom half" */
   sem_t exclsem;              /* Mutual exclusion semaphore */
   bool ena;                   /* Sample sequencer operation state */
   uint32_t irq;               /* SSE interrupt vectors */
@@ -288,19 +278,18 @@ struct tiva_adc_sse_s
  * Private Function Definitions
  ****************************************************************************/
 
-/* Debug ADC functions ******************************************************/
-
-#if defined(CONFIG_TIVA_ADC_REGDEBUG) && defined(CONFIG_DEBUG)
+/* Debug ADC functions **********************************************/
+#  if defined(CONFIG_TIVA_ADC_REGDEBUG) && defined(CONFIG_DEBUG)
 static bool tiva_adc_checkreg(struct tiva_adc_s *priv, bool wr,
                               uint32_t regval, uintptr_t address);
-#endif
+#  endif
 
-#ifdef CONFIG_TIVA_ADC_REGDEBUG
+#  ifdef CONFIG_TIVA_ADC_REGDEBUG
 static void tiva_adc_modifyreg(struct tiva_adc_s *priv, unsigned int addr,
                                uint32_t clearbits, uint32_t setbits);
-#else
-#  define tiva_adc_modifyreg(priv,addr,clearbits,setbits) modifyreg32(addr,clearbits,setbits)
-#endif
+#  else
+#    define tiva_adc_modifyreg(priv,addr,clearbits,setbits) modifyreg32(addr,clearbits,setbits)
+#  endif
 
 /* TM4C-specific ADC functions **********************************************/
 
@@ -308,9 +297,9 @@ static void tiva_adc_modifyreg(struct tiva_adc_s *priv, unsigned int addr,
 
 static int adc_state(struct tiva_adc_s *adc, bool state);
 static void adc_clock(uint32_t freq);
-#ifdef CONFIG_ARCH_CHIP_TM4C129
+#  ifdef CONFIG_ARCH_CHIP_TM4C129
 static void adc_vref(uint8_t vref);
-#endif /* CONFIG_ARCH_CHIP_TM4C129 */
+#  endif                               /* CONFIG_ARCH_CHIP_TM4C129 */
 
 /* Peripheral (base) level */
 
@@ -318,14 +307,14 @@ static void adc_sample_rate(uint8_t rate);
 static void adc_proc_trig(struct tiva_adc_s *adc, uint8_t sse_mask);
 static uint32_t adc_int_status(struct tiva_adc_s *adc);
 
-/* Sample Sequencer (struct tiva_adc_s *adc, SSE) level */
+/* Sample Sequencer (SSE) level */
 
 static void sse_state(struct tiva_adc_s *adc, uint8_t sse, bool state);
 static void sse_trigger(struct tiva_adc_s *adc, uint8_t sse, uint32_t trigger);
-#ifdef CONFIG_EXPERIMENTAL
+#  ifdef CONFIG_EXPERIMENTAL
 static void sse_pwm_trig_ioctl(struct tiva_adc_s *adc, uint8_t sse,
                                uint32_t cfg);
-#endif
+#  endif
 static int sse_data(struct tiva_adc_s *adc, uint8_t sse);
 static void sse_priority(struct tiva_adc_s *adc, uint8_t sse, uint8_t priority);
 
@@ -337,58 +326,58 @@ static void sse_register_chn(struct tiva_adc_s *adc, uint8_t sse, uint8_t chn,
                              uint32_t ain);
 static void sse_differential(struct tiva_adc_s *adc, uint8_t sse, uint8_t chn,
                              uint32_t diff);
-#ifdef CONFIG_EXPERIMENTAL
+#  ifdef CONFIG_EXPERIMENTAL
 static void sse_sample_hold_time(struct tiva_adc_s *adc, uint8_t sse,
                                  uint8_t chn, uint32_t shold);
-#endif
+#  endif
 static void sse_step_cfg(struct tiva_adc_s *adc, uint8_t sse, uint8_t chn,
                          uint8_t cfg);
 
-/* Helper functions **********************************************************/
+/* Helper functions *********************************************************/
 
-#ifdef CONFIG_TIVA_ADC0
+#  ifdef CONFIG_TIVA_ADC0
 static void tiva_adc0_sse_init(void);
 static void tiva_adc0_assign_channels(void);
 static void tiva_adc0_assign_interrupts(void);
-#  ifdef CONFIG_TIVA_ADC0_SSE0
+#    ifdef CONFIG_TIVA_ADC0_SSE0
 static void adc0_sse0_chn_cfg(void);
 static void adc0_sse0_interrupt(int irq, void *context);
-#  endif
-#  ifdef CONFIG_TIVA_ADC0_SSE1
+#    endif
+#    ifdef CONFIG_TIVA_ADC0_SSE1
 static void adc0_sse1_chn_cfg(void);
 static void adc0_sse1_interrupt(int irq, void *context);
-#  endif
-#  ifdef CONFIG_TIVA_ADC0_SSE2
+#    endif
+#    ifdef CONFIG_TIVA_ADC0_SSE2
 static void adc0_sse2_chn_cfg(void);
 static void adc0_sse2_interrupt(int irq, void *context);
-#  endif
-#  ifdef CONFIG_TIVA_ADC0_SSE3
+#    endif
+#    ifdef CONFIG_TIVA_ADC0_SSE3
 static void adc0_sse3_chn_cfg(void);
 static void adc0_sse3_interrupt(int irq, void *context);
+#    endif
 #  endif
-#endif /* CONFIG_TIVA_ADC0 */
 
-#ifdef CONFIG_TIVA_ADC1
+#  ifdef CONFIG_TIVA_ADC1
 static void tiva_adc1_sse_init(void);
 static void tiva_adc1_assign_channels(void);
 static void tiva_adc1_assign_interrupts(void);
-#  ifdef CONFIG_TIVA_ADC1_SSE0
+#    ifdef CONFIG_TIVA_ADC1_SSE0
 static void adc1_sse0_chn_cfg(void);
 static void adc1_sse0_interrupt(int irq, void *context);
-#  endif
-#  ifdef CONFIG_TIVA_ADC1_SSE1
+#    endif
+#    ifdef CONFIG_TIVA_ADC1_SSE1
 static void adc1_sse1_chn_cfg(void);
 static void adc1_sse1_interrupt(int irq, void *context);
-#  endif
-#  ifdef CONFIG_TIVA_ADC1_SSE2
+#    endif
+#    ifdef CONFIG_TIVA_ADC1_SSE2
 static void adc1_sse2_chn_cfg(void);
 static void adc1_sse2_interrupt(int irq, void *context);
-#  endif
-#  ifdef CONFIG_TIVA_ADC1_SSE3
+#    endif
+#    ifdef CONFIG_TIVA_ADC1_SSE3
 static void adc1_sse3_chn_cfg(void);
 static void adc1_sse3_interrupt(int irq, void *context);
+#    endif
 #  endif
-#endif /* CONFIG_TIVA_ADC1 */
 
 /****************************************************************************
  * Private Data
@@ -398,49 +387,59 @@ static void adc1_sse3_interrupt(int irq, void *context);
 
 static struct tiva_adc_state_s adc_common =
 {
-  .init = {false, false},
-  .sse = {false, false, false, false, false, false, false, false},
+  .init = {
+    false,
+    false},
+  .sse = {
+    false,
+    false,
+    false,
+    false,
+    false,
+    false,
+    false,
+    false},
 };
 
-#ifdef CONFIG_TIVA_ADC0
+#  ifdef CONFIG_TIVA_ADC0
 
 /* ADC device instance 0 */
 
 static struct adc_dev_s g_adcdev0;
 static struct tiva_adc_s adc0;
-#  ifdef CONFIG_TIVA_ADC0_SSE0
+#    ifdef CONFIG_TIVA_ADC0_SSE0
 static struct tiva_adc_sse_s sse00;
-#  endif
-#  ifdef CONFIG_TIVA_ADC0_SSE1
+#    endif
+#    ifdef CONFIG_TIVA_ADC0_SSE1
 static struct tiva_adc_sse_s sse01;
-#  endif
-#  ifdef CONFIG_TIVA_ADC0_SSE2
+#    endif
+#    ifdef CONFIG_TIVA_ADC0_SSE2
 static struct tiva_adc_sse_s sse02;
-#  endif
-#  ifdef CONFIG_TIVA_ADC0_SSE3
+#    endif
+#    ifdef CONFIG_TIVA_ADC0_SSE3
 static struct tiva_adc_sse_s sse03;
+#    endif
 #  endif
-#endif
 
-#ifdef CONFIG_TIVA_ADC1
+#  ifdef CONFIG_TIVA_ADC1
 
 /* ADC device instance 1 */
 
 static struct adc_dev_s g_adcdev1;
 static struct tiva_adc_s adc1;
-#  ifdef CONFIG_TIVA_ADC1_SSE0
+#    ifdef CONFIG_TIVA_ADC1_SSE0
 static struct tiva_adc_sse_s sse10;
-#  endif
-#  ifdef CONFIG_TIVA_ADC1_SSE1
+#    endif
+#    ifdef CONFIG_TIVA_ADC1_SSE1
 static struct tiva_adc_sse_s sse11;
-#  endif
-#  ifdef CONFIG_TIVA_ADC1_SSE2
+#    endif
+#    ifdef CONFIG_TIVA_ADC1_SSE2
 static struct tiva_adc_sse_s sse12;
-#  endif
-#  ifdef CONFIG_TIVA_ADC1_SSE3
+#    endif
+#    ifdef CONFIG_TIVA_ADC1_SSE3
 static struct tiva_adc_sse_s sse13;
+#    endif
 #  endif
-#endif
 
 /****************************************************************************
  * Private Functions
@@ -458,9 +457,7 @@ static struct tiva_adc_sse_s sse13;
 static void tiva_adc_reset(struct adc_dev_s *dev)
 {
   struct tiva_adc_s *priv = (struct tiva_adc_s *)dev->ad_priv;
-
   adcvdbg("Resetting...\n");
-
   /* Only if ADCs are active do we run the reset routine: - disable ADC
    * interrupts - clear interrupt bits - disable all active sequences
    * Otherwise, if the peripheral is inactive, perform no operations since
@@ -470,14 +467,13 @@ static void tiva_adc_reset(struct adc_dev_s *dev)
 
   if (priv->ena)
     {
-      tiva_adc_rxint(dev, DISABLE);
+      tiva_adc_rxint(dev, TIVA_ADC_DISABLE);
       uint8_t s;
-
       for (s = 0; s < SSE_PER_BASE; ++s)
         {
           if (adc_common.sse[SSE_IDX(priv->devno, s)])
             {
-              sse_state(priv, s, DISABLE);
+              sse_state(priv, s, TIVA_ADC_DISABLE);
             }
         }
     }
@@ -499,18 +495,16 @@ static void tiva_adc_reset(struct adc_dev_s *dev)
 
 static int tiva_adc_setup(struct adc_dev_s *dev)
 {
-  struct tiva_adc_s *priv = (struct tiva_adc_s *)dev->ad_priv;
-  uint8_t s = 0;
-
   adcvdbg("Setup\n");
-
   /* Only if ADCs are active do we run the reset routine: - enable ADC
-   * interrupts - clear interrupt bits - enable all active sequences - register 
-   * triggers and respective interrupt handlers Otherwise, if the peripheral
-   * is inactive, perform no operations since register access to a peripheral
-   * that is not active will result in a segmentation fault.
+   * interrupts - clear interrupt bits - enable all active sequences - register
+   * triggers and respective interrupt handlers Otherwise, if the peripheral is
+   * inactive, perform no operations since register access to a peripheral that
+   * is not active will result in a segmentation fault.
    */
 
+  struct tiva_adc_s *priv = (struct tiva_adc_s *)dev->ad_priv;
+  uint8_t s = 0;
   for (s = 0; s < SSE_PER_BASE; ++s)
     {
       if (adc_common.sse[SSE_IDX(priv->devno, s)])
@@ -535,14 +529,12 @@ static int tiva_adc_setup(struct adc_dev_s *dev)
 static void tiva_adc_shutdown(struct adc_dev_s *dev)
 {
   struct tiva_adc_s *priv = (struct tiva_adc_s *)dev->ad_priv;
-  uint8_t s = 0;
-
   adcvdbg("Shutdown\n");
 
   /* Reset the ADC peripheral */
-
   tiva_adc_reset(dev);
 
+  uint8_t s = 0;
   for (s = 0; s < SSE_PER_BASE; ++s)
     {
       if (adc_common.sse[SSE_IDX(priv->devno, s)])
@@ -572,10 +564,9 @@ static void tiva_adc_shutdown(struct adc_dev_s *dev)
 static void tiva_adc_rxint(struct adc_dev_s *dev, bool enable)
 {
   struct tiva_adc_s *priv = (struct tiva_adc_s *)dev->ad_priv;
-  uint8_t s = 0;
-
   adcvdbg("rx enable=%d\n", enable);
 
+  uint8_t s = 0;
   for (s = 0; s < SSE_PER_BASE; ++s)
     {
       uint32_t trigger =
@@ -606,48 +597,56 @@ static int tiva_adc_ioctl(struct adc_dev_s *dev, int cmd, unsigned long arg)
 {
   struct tiva_adc_s *priv = (struct tiva_adc_s *)dev->ad_priv;
   int ret = OK;
+  uint32_t stat = 0;
   uint8_t sse = (uint8_t) arg;
 
   adcvdbg("cmd=%d arg=%ld\n", cmd, arg);
-
   switch (cmd)
     {
-    case ANIOC_TRIGGER:        /* Software trigger */
-      /* start conversion and read to buffer */
-
-      adc_proc_trig(priv, (uint8_t) SSE_PROC_TRIG(sse));
-      uint32_t stat = adc_int_status(priv) & (1 << sse);
-      while (!stat)
-        {
-          stat = adc_int_status(priv) & (1 << sse);
-        }
-
-      sse_clear_int(priv, sse);
-      sse_data(priv, sse);
-      break;
-
-#if 0 /* TODO: fix this later: need to encode which SSE since trigger type isn't tracked */
-    case TIVA_ADC_PWM_TRIG_IOCTL:      /* PWM triggering */
-      for (s = 0; s < SSE_PER_BASE; ++s)
-        {
-          if (adc_common.sse[SSE_IDX(priv->devno, s)])
-            {
-              /* TODO: fixme */
-
-              if (priv, s->trigger & ADC_TRIG_PWM_MASK)
-                {
-                  sse_pwm_trig_ioctl(priv, s, (uint32_t) arg);
-                }
-            }
-        }
-      break;
-#endif
+      /* Software trigger */
+
+      case ANIOC_TRIGGER:
+
+        /* start conversion and read to buffer */
+
+        adc_proc_trig(priv, (uint8_t) SSE_PROC_TRIG(sse));
+        stat = adc_int_status(priv) & (1 << sse);
+        while (!stat)
+          {
+            stat = adc_int_status(priv) & (1 << sse);
+          }
+
+        sse_clear_int(priv, sse);
+        sse_data(priv, sse);
+        break;
+
+        /* TODO: Needs to be tested, needs to encode which SSE since trigger type
+         * isn't tracked and, needs a PWM driver to use.
+         */
+
+#  if 0
+      /* PWM triggering */
+
+      case TIVA_ADC_PWM_TRIG_IOCTL:
+        for (s = 0; s < SSE_PER_BASE; ++s)
+          {
+            if (adc_common.sse[SSE_IDX(priv->devno, s)])
+              {
+                /* TODO: fixme */
+                if (priv, s->trigger & ADC_TRIG_PWM_MASK)
+                  {
+                    sse_pwm_trig_ioctl(priv, s, (uint32_t) arg);
+                  }
+              }
+          }
+        break;
+#  endif
 
-    /* Unsupported or invalid command */
+      /* Unsupported or invalid command */
 
-    default:
-      ret = -ENOTTY;
-      break;
+      default:
+        ret = -ENOTTY;
+        break;
     }
 
   return ret;
@@ -657,7 +656,7 @@ static int tiva_adc_ioctl(struct adc_dev_s *dev, int cmd, unsigned long arg)
  * Register Operations
  ****************************************************************************/
 
-#ifdef CONFIG_TIVA_ADC_REGDEBUG
+#  ifdef CONFIG_TIVA_ADC_REGDEBUG
 
 /****************************************************************************
  * Name: tiva_adc_checkreg
@@ -710,7 +709,7 @@ static bool tiva_adc_checkreg(struct tiva_adc_s *priv, bool wr,
 
   return true;
 }
-#endif /* CONFIG_TIVA_ADC_REGDEBUG */
+#  endif /* CONFIG_TIVA_ADC_REGDEBUG */
 
 /****************************************************************************
  * Name: tiva_adc_modifyreg
@@ -723,18 +722,19 @@ static bool tiva_adc_checkreg(struct tiva_adc_s *priv, bool wr,
  *
  ****************************************************************************/
 
-#ifdef CONFIG_TIVA_ADC_REGDEBUG
+#  ifdef CONFIG_TIVA_ADC_REGDEBUG
 static void tiva_adc_modifyreg(struct tiva_adc_s *priv, unsigned int addr,
                                uint32_t clearbits, uint32_t setbits)
 {
+  uint32_t regval = 0;
   irqstate_t flags = irqsave();
-  uint32_t regval = tiva_adc_getreg(priv, addr);
+  regval = tiva_adc_getreg(priv, addr);
   regval &= ~clearbits;
   regval |= setbits;
   tiva_adc_putreg(priv, addr, regval);
   irqrestore(flags);
 }
-#endif /* CONFIG_TIVA_ADC_REGDEBUG */
+#  endif /* CONFIG_TIVA_ADC_REGDEBUG */
 
 /* TM4C-specific ADC functions **********************************************/
 
@@ -750,32 +750,36 @@ static void tiva_adc_modifyreg(struct tiva_adc_s *priv, unsigned int addr,
  *  state - operation state
  *
  ****************************************************************************/
+
 static int adc_state(struct tiva_adc_s *adc, bool state)
 {
-  if (state == ENABLE)
+  if (state == TIVA_ADC_ENABLE)
     {
+
       /* Enable clocking to the ADC peripheral */
 
-#ifdef TIVA_SYSCON_RCGCADC
+#  ifdef TIVA_SYSCON_RCGCADC
       modifyreg32(TIVA_SYSCON_RCGCADC, 0, 1 << adc->devno);
-#else
+#  else
       modifyreg32(TIVA_SYSCON_RCGC0, 0, SYSCON_RCGC0_ADC0);
-#endif /* TIVA_SYSCON_RCGCADC */
+#  endif
       return OK;
     }
-  else if (state == DISABLE)
+  else if (state == TIVA_ADC_DISABLE)
     {
       /* Disable clocking to the ADC peripheral */
 
-#ifdef TIVA_SYSCON_RCGCADC
+#  ifdef TIVA_SYSCON_RCGCADC
       modifyreg32(TIVA_SYSCON_RCGCADC, 1 << adc->devno, 0);
-#else
+#  else
       modifyreg32(TIVA_SYSCON_RCGC0, SYSCON_RCGC0_ADC0, 0);
-#endif /* TIVA_SYSCON_RCGCADC */
+#  endif
       return OK;
     }
 
-  return -1; /* ERROR! */
+  /* ERROR! */
+
+  return -1;
 }
 
 /****************************************************************************
@@ -795,19 +799,20 @@ static int adc_state(struct tiva_adc_s *adc, bool state)
  *  is much more intuitive to allow the clock variable be a frequency value.
  *
  ****************************************************************************/
+
 static void adc_clock(uint32_t freq)
 {
-#if defined(CONFIG_ARCH_CHIP_TM4C123)
+#  if defined(CONFIG_ARCH_CHIP_TM4C123)
   /* For the TM4C123, the ADC clock source does not affect the frequency, it
    * runs at 16 MHz regardless. You end up selecting between the MOSC (default)
    * or the PIOSC. The PIOSC allows the ADC to operate even in deep sleep mode.
-   * Since this is the case, the clock value for.
+   * Since this is the case, the clock value for
    */
 
   uintptr_t ccreg = (TIVA_ADC0_BASE + TIVA_ADC_CC_OFFSET);
   modifyreg32(ccreg, 0, (freq & ADC_CC_CS_MASK));
+#  elif defined (CONFIG_ARCH_CHIP_TM4C129)
 
-#elif defined (CONFIG_ARCH_CHIP_TM4C129)
   /* check clock bounds and specific match cases */
 
   uint32_t clk_src = 0;
@@ -835,12 +840,12 @@ static void adc_clock(uint32_t freq)
 
   uintptr_t ccreg = (TIVA_ADC0_BASE + TIVA_ADC_CC_OFFSET);
   modifyreg32(ccreg, 0, CLOCK_CONFIG(div, clk_src));
-#else
-#  error "Unsupported architecture reported"
-#endif /* defined CONFIG_ARCH_CHIP_TM4C123 | CONFIG_ARCH_CHIP_TM4C129 */
+#  else
+#    error Unsupported architecture reported
+#  endif
 }
 
-#ifdef CONFIG_ARCH_CHIP_TM4C129
+#  ifdef CONFIG_ARCH_CHIP_TM4C129
 
 /****************************************************************************
  * Name: adc_vref
@@ -865,7 +870,7 @@ static void adc_vref(uint8_t vref)
       modifyreg32(ctlreg, 0, vref);
     }
 }
-#endif /* CONFIG_ARCH_CHIP_TM4C129 */
+#  endif
 
 /****************************************************************************
  * Name: adc_sample_rate
@@ -885,7 +890,8 @@ static void adc_sample_rate(uint8_t rate)
 {
   uintptr_t pcreg = (TIVA_ADC0_BASE + TIVA_ADC_PC_OFFSET);
 
-  /* NOTE: ADC_PC_SR_MASK is intended for use with the TM4C123, the
+  /*
+   * NOTE: ADC_PC_SR_MASK is intended for use with the TM4C123, the
    * alternative is ADC_PC_MCR_MASK for the TM4C129. However both masks
    * mask off the first 4 bits (0xF) so there is no need to distinguish
    * between the two.
@@ -917,9 +923,9 @@ static void adc_proc_trig(struct tiva_adc_s *adc, uint8_t sse_mask)
 {
   uintptr_t pssireg = TIVA_ADC_PSSI(adc->devno);
   tiva_adc_modifyreg(adc, pssireg, 0, sse_mask);
-#ifdef CONFIG_TIVA_ADC_SYNC
-#  warning CONFIG_TIVA_ADC_SYNC unsupported at this time.
-#endif /* CONFIG_TIVA_ADC_SYNC */
+#  ifdef CONFIG_TIVA_ADC_SYNC
+#    warning CONFIG_TIVA_ADC_SYNC unsupported at this time.
+#  endif
 }
 
 /****************************************************************************
@@ -953,10 +959,11 @@ static uint32_t adc_int_status(struct tiva_adc_s *adc)
  *   state - sample sequencer enable/disable state
  *
  ****************************************************************************/
+
 static void sse_state(struct tiva_adc_s *adc, uint8_t sse, bool state)
 {
   uintptr_t actssreg = TIVA_ADC_ACTSS(adc->devno);
-  if (state == ENABLE)
+  if (state == TIVA_ADC_ENABLE)
     {
       tiva_adc_modifyreg(adc, actssreg, 0, (1 << sse));
     }
@@ -993,17 +1000,16 @@ static void sse_trigger(struct tiva_adc_s *adc, uint8_t sse, uint32_t trigger)
 {
   uintptr_t emuxreg = (TIVA_ADC_EMUX(adc->devno));
   uint32_t trig = 0;
-
   if ((trigger & ADC_EMUX_MASK(0)) == 0)
     {
-      /* the 0 value is a special case since using modifyregn() results in an
+      /* The 0 value is a special case since using modifyregn() results in an
        * ORing of the register value; we need to unset those bits if it's a 0.
        */
 
       tiva_adc_modifyreg(adc, emuxreg, (0xF << sse), 0);
     }
   else
-    {                           /* > 0 */
+    {
       trig = ((trigger << ADC_EMUX_SHIFT(sse)) & ADC_EMUX_MASK(sse));
       tiva_adc_modifyreg(adc, emuxreg, 0, trig);
     }
@@ -1027,12 +1033,13 @@ static void sse_trigger(struct tiva_adc_s *adc, uint8_t sse, uint32_t trigger)
  *
  ****************************************************************************/
 
-#ifdef CONFIG_EXPERIMENTAL
+#  ifdef CONFIG_EXPERIMENTAL
 static void sse_pwm_trig_ioctl(struct tiva_adc_s *adc, uint8_t sse,
                                uint32_t cfg)
 {
   if ((ADC_TRIG_PWM_MASK & cfg) > 0)
     {
+
       /* PWM triggering needs an additional register to be set (ADC_TSSEL) */
 
       uintptr_t tsselreg = TIVA_ADC_TSSEL(adc->devno);
@@ -1041,13 +1048,13 @@ static void sse_pwm_trig_ioctl(struct tiva_adc_s *adc, uint8_t sse,
         {
           tiva_adc_modifyreg(adc, tsselreg, 0, pwmcfg);
         }
-      else /* == 0 */
+      else
         {
           tiva_adc_modifyreg(adc, tsselreg, pwmcfg, 0);
         }
     }
 }
-#endif
+#  endif
 
 /****************************************************************************
  * Name: sse_int
@@ -1070,8 +1077,7 @@ static void sse_int_state(struct tiva_adc_s *adc, uint8_t sse, bool state)
     {
       sse_clear_int(adc, sse);
     }
-
-  if (state == ENABLE)
+  if (state == TIVA_ADC_ENABLE)
     {
       tiva_adc_modifyreg(adc, imreg, 0, (1 << sse));
     }
@@ -1152,7 +1158,7 @@ static int sse_data(struct tiva_adc_s *adc, uint8_t sse)
       (void)adc_receive(adc->dev, GET_AIN(adc->devno, sse, fifo_count), data);
       fifo_count++;
 
-      /* Refresh fifo status register state */
+      /* refresh fifo status register state */
 
       ssfstatreg =
         tiva_adc_getreg(adc, TIVA_ADC_BASE(adc->devno) + TIVA_ADC_SSFSTAT(sse));
@@ -1179,21 +1185,19 @@ static int sse_data(struct tiva_adc_s *adc, uint8_t sse)
 static void sse_priority(struct tiva_adc_s *adc, uint8_t sse, uint8_t priority)
 {
   uintptr_t ssprireg = TIVA_ADC_SSPRI(adc->devno);
+  uint32_t sspri = 0;
   if (priority == 0)
     {
-      /* the 0 value is a special case since using modifyregn() results in an
+      /* The 0 value is a special case since using modifyregn() results in an
        * ORing of the register value; we need to unset those bits if it's a 0.
        */
 
-      uint32_t sspri = (ADC_SSPRI_MASK(sse) & (0x3 << ADC_SSPRI_SHIFT(sse)));
+      sspri = (ADC_SSPRI_MASK(sse) & (0x3 << ADC_SSPRI_SHIFT(sse)));
       tiva_adc_modifyreg(adc, ssprireg, sspri, 0);
     }
   else
     {
-      /* 1, 2 or 3 */
-
-      uint32_t sspri =
-        (ADC_SSPRI_MASK(sse) & (priority << ADC_SSPRI_SHIFT(sse)));
+      sspri = (ADC_SSPRI_MASK(sse) & (priority << ADC_SSPRI_SHIFT(sse)));
       tiva_adc_modifyreg(adc, ssprireg, 0, sspri);
     }
 }
@@ -1219,27 +1223,23 @@ static void sse_priority(struct tiva_adc_s *adc, uint8_t sse, uint8_t priority)
 static void sse_register_chn(struct tiva_adc_s *adc, uint8_t sse, uint8_t chn,
                              uint32_t ain)
 {
-  /* configure SSE mux (SSMUX) with step number */
+  /* Configure SSE mux (SSMUX) with step number */
 
   uintptr_t ssmuxreg = (TIVA_ADC_BASE(adc->devno) + TIVA_ADC_SSMUX(sse));
-
+  uint32_t step = 0;
   if (ain > 0)
     {
-      uint32_t step =
-        ((ain << ADC_SSMUX_MUX_SHIFT(chn)) & ADC_SSMUX_MUX_MASK(chn));
+      step = ((ain << ADC_SSMUX_MUX_SHIFT(chn)) & ADC_SSMUX_MUX_MASK(chn));
       tiva_adc_modifyreg(adc, ssmuxreg, 0, step);
     }
   else
     {
-      /* ain <= 0 */
-
-      uint32_t step =
-        ((0xF << ADC_SSMUX_MUX_SHIFT(chn)) & ADC_SSMUX_MUX_MASK(chn));
+      step = ((0xF << ADC_SSMUX_MUX_SHIFT(chn)) & ADC_SSMUX_MUX_MASK(chn));
       tiva_adc_modifyreg(adc, ssmuxreg, step, 0);
     }
 
-#ifdef CONFIG_ARCH_CHIP_TM4C129
-  /* configure SSE extended mux (SSEMUX) with step number and configuration */
+#  ifdef CONFIG_ARCH_CHIP_TM4C129
+  /* Configure SSE extended mux (SSEMUX) with step number and configuration */
 
   ssmuxreg = (TIVA_ADC_BASE(adc->devno) + TIVA_ADC_SSMUX(sse));
   step = ((1 << ADC_SSEMUX_MUX_SHIFT(chn)) & ADC_SSEMUX_MUX_MASK(chn));
@@ -1249,11 +1249,9 @@ static void sse_register_chn(struct tiva_adc_s *adc, uint8_t sse, uint8_t chn,
     }
   else
     {
-      /* chn < 16 */
-
       tiva_adc_modifyreg(adc, ssmuxreg, step, 0);
     }
-#endif /* CONFIG_ARCH_CHIP_TM4C129 */
+#  endif
 }
 
 /****************************************************************************
@@ -1273,15 +1271,16 @@ static void sse_register_chn(struct tiva_adc_s *adc, uint8_t sse, uint8_t chn,
 static void sse_differential(struct tiva_adc_s *adc, uint8_t sse, uint8_t chn,
                              uint32_t diff)
 {
-#ifdef CONFIG_TIVA_ADC_DIFFERENTIAL
-#  error CONFIG_TIVA_ADC_DIFFERENTIAL unsupported!!
-#else
+#  ifdef CONFIG_TIVA_ADC_DIFFERENTIAL
+#    error CONFIG_TIVA_ADC_DIFFERENTIAL unsupported!!
+#  else
+
   /* for now, ensure the FIFO is used and differential sampling is disabled */
 
   uintptr_t ssopreg = (TIVA_ADC_BASE(adc->devno) + TIVA_ADC_SSOP(sse));
   uint32_t sdcopcfg = (1 << chn);
   tiva_adc_modifyreg(adc, ssopreg, sdcopcfg, 0);
-#endif /* CONFIG_TIVA_ADC_DIFFERENTIAL */
+#  endif
 }
 
 /****************************************************************************
@@ -1300,7 +1299,8 @@ static void sse_differential(struct tiva_adc_s *adc, uint8_t sse, uint8_t chn,
  *   shold - sample and hold time
  *
  ****************************************************************************/
-#ifdef CONFIG_EXPERIMENTAL
+
+#  ifdef CONFIG_EXPERIMENTAL
 static void sse_sample_hold_time(struct tiva_adc_s *adc, uint8_t sse,
                                  uint8_t chn, uint32_t shold)
 {
@@ -1314,7 +1314,7 @@ static void sse_sample_hold_time(struct tiva_adc_s *adc, uint8_t sse,
       tiva_adc_modifyreg(adc, sstshreg, ADC_SSTSH_MASK(sse), 0);
     }
 }
-#endif
+#  endif
 
 /****************************************************************************
  * Name: sse_step_cfg
@@ -1334,7 +1334,7 @@ static void sse_sample_hold_time(struct tiva_adc_s *adc, uint8_t sse,
  *       temperature sensor does not have a differential option, this bit must
  *       not be set when the TS3 bit is set.
  *
- *  *Comparator/Differential functionality is unsupported and ignored.
+ *  *Comparator/Differental functionality is unsupported and ignored.
  *
  * Input parameters:
  *   adc - peripheral state
@@ -1363,20 +1363,19 @@ static void sse_step_cfg(struct tiva_adc_s *adc, uint8_t sse, uint8_t chn,
  *   Initialize the ADC
  *
  * Returned Value:
- *   Valid can device structure reference on success; a NULL on failure
+ *   Valid can device structure reference on succcess; a NULL on failure
  *
  ****************************************************************************/
 
 struct adc_dev_s *tiva_adc_initialize(int adc_num)
 {
-  struct tiva_adc_s *adc;
-  uint8_t s;
-
   adcvdbg("tiva_adc_initialize\n");
 
   /* Initialize the private ADC device data structure */
 
-#ifdef CONFIG_TIVA_ADC0
+  struct tiva_adc_s *adc;
+  uint8_t s;
+#  ifdef CONFIG_TIVA_ADC0
   if (adc_num == 0)
     {
       adc0.ena = false;
@@ -1384,46 +1383,46 @@ struct adc_dev_s *tiva_adc_initialize(int adc_num)
 
       /* Debug stuff */
 
-#  ifdef CONFIG_TIVA_ADC_REGDEBUG
+#    ifdef CONFIG_TIVA_ADC_REGDEBUG
       adc0.wrlast = false;
       adc0.addrlast = 0x0;
       adc0.vallast = 0x0;
       adc0.ntimes = 0;
-#  endif /* CONFIG_TIVA_ADC_REGDEBUG */
+#    endif                             /* CONFIG_TIVA_ADC_REGDEBUG */
 
       /* Initialize SSEs */
 
-#  ifdef CONFIG_TIVA_ADC0_SSE0
+#    ifdef CONFIG_TIVA_ADC0_SSE0
       sse00.ena = false;
       sse00.irq = TIVA_IRQ_ADC0;
       sse00.num = 0;
       sem_init(&sse00.exclsem, SEM_PROCESS_PRIVATE, 1);
       adc0.sse[0] = &sse00;
-#  endif /* CONFIG_TIVA_ADC0_SSE0 */
+#    endif                             /* CONFIG_TIVA_ADC0_SSE0 */
 
-#  ifdef CONFIG_TIVA_ADC0_SSE1
+#    ifdef CONFIG_TIVA_ADC0_SSE1
       sse01.ena = false;
       sse01.irq = TIVA_IRQ_ADC0;
       sse01.num = 1;
       sem_init(&sse01.exclsem, SEM_PROCESS_PRIVATE, 1);
       adc0.sse[1] = &sse01;
-#  endif /* CONFIG_TIVA_ADC0_SSE1 */
+#    endif                             /* CONFIG_TIVA_ADC0_SSE1 */
 
-#  ifdef CONFIG_TIVA_ADC0_SSE2
+#    ifdef CONFIG_TIVA_ADC0_SSE2
       sse02.ena = false;
       sse02.irq = TIVA_IRQ_ADC0;
       sse02.num = 2;
       sem_init(&sse02.exclsem, SEM_PROCESS_PRIVATE, 1);
       adc0.sse[2] = &sse02;
-#  endif /* CONFIG_TIVA_ADC0_SSE2 */
+#    endif                             /* CONFIG_TIVA_ADC0_SSE2 */
 
-#  ifdef CONFIG_TIVA_ADC0_SSE3
+#    ifdef CONFIG_TIVA_ADC0_SSE3
       sse03.ena = false;
       sse03.irq = TIVA_IRQ_ADC0;
       sse03.num = 3;
       sem_init(&sse03.exclsem, SEM_PROCESS_PRIVATE, 1);
       adc0.sse[3] = &sse03;
-#  endif /* CONFIG_TIVA_ADC0_SSE3 */
+#    endif                             /* CONFIG_TIVA_ADC0_SSE3 */
 
       adc0.dev = &g_adcdev0;
       adc = &adc0;
@@ -1433,9 +1432,9 @@ struct adc_dev_s *tiva_adc_initialize(int adc_num)
       g_adcdev0.ad_ops = &g_adcops;
       g_adcdev0.ad_priv = &adc0;
     }
-#endif /* CONFIG_TIVA_ADC0 */
+#  endif                               /* CONFIG_TIVA_ADC0 */
 
-#ifdef CONFIG_TIVA_ADC1
+#  ifdef CONFIG_TIVA_ADC1
   if (adc_num == 1)
     {
       adc1.ena = false;
@@ -1443,46 +1442,46 @@ struct adc_dev_s *tiva_adc_initialize(int adc_num)
 
       /* Debug stuff */
 
-#  ifdef CONFIG_TIVA_ADC_REGDEBUG
+#    ifdef CONFIG_TIVA_ADC_REGDEBUG
       adc1.wrlast = false;
       adc1.addrlast = 0x0;
       adc1.vallast = 0x0;
       adc1.ntimes = 0;
-#  endif /* CONFIG_TIVA_ADC_REGDEBUG */
+#    endif                             /* CONFIG_TIVA_ADC_REGDEBUG */
 
       /* Initialize SSEs */
 
-#  ifdef CONFIG_TIVA_ADC1_SSE0
+#    ifdef CONFIG_TIVA_ADC1_SSE0
       sse10.ena = false;
       sse10.irq = TIVA_IRQ_ADC0;
       sse10.num = 0;
       sem_init(&sse10.exclsem, SEM_PROCESS_PRIVATE, 1);
       adc1.sse[0] = &sse10;
-#  endif /* CONFIG_TIVA_ADC1_SSE0 */
+#    endif                             /* CONFIG_TIVA_ADC1_SSE0 */
 
-#  ifdef CONFIG_TIVA_ADC1_SSE1
+#    ifdef CONFIG_TIVA_ADC1_SSE1
       sse11.ena = false;
       sse11.irq = TIVA_IRQ_ADC0;
       sse11.num = 1;
       sem_init(&sse11.exclsem, SEM_PROCESS_PRIVATE, 1);
       adc1.sse[1] = &sse11;
-#  endif /* CONFIG_TIVA_ADC1_SSE1 */
+#    endif                             /* CONFIG_TIVA_ADC1_SSE1 */
 
-#  ifdef CONFIG_TIVA_ADC1_SSE2
+#    ifdef CONFIG_TIVA_ADC1_SSE2
       sse12.ena = false;
       sse12.irq = TIVA_IRQ_ADC0;
       sse12.num = 2;
       sem_init(&sse12.exclsem, SEM_PROCESS_PRIVATE, 1);
       adc1.sse[2] = &sse12;
-#  endif /* CONFIG_TIVA_ADC1_SSE2 */
+#    endif                             /* CONFIG_TIVA_ADC1_SSE2 */
 
-#  ifdef CONFIG_TIVA_ADC1_SSE3
+#    ifdef CONFIG_TIVA_ADC1_SSE3
       sse13.ena = false;
       sse13.irq = TIVA_IRQ_ADC0;
       sse13.num = 3;
       sem_init(&sse13.exclsem, SEM_PROCESS_PRIVATE, 1);
       adc1.sse[3] = &sse13;
-#  endif /* CONFIG_TIVA_ADC1_SSE3 */
+#    endif                             /* CONFIG_TIVA_ADC1_SSE3 */
 
       adc1.dev = &g_adcdev1;
       adc = &adc1;
@@ -1492,7 +1491,7 @@ struct adc_dev_s *tiva_adc_initialize(int adc_num)
       g_adcdev1.ad_ops = &g_adcops;
       g_adcdev1.ad_priv = &adc1;
     }
-#endif /* CONFIG_TIVA_ADC1 */
+#  endif                               /* CONFIG_TIVA_ADC1 */
 
   if (adc_num > 1)
     {
@@ -1506,40 +1505,41 @@ struct adc_dev_s *tiva_adc_initialize(int adc_num)
    */
 
   if (adc_common.init[adc->devno] == false)
-    {                           /* turn on peripheral */
-      if (adc_state(adc, ENABLE) < 0)
+    {
+      /* turn on peripheral */
+
+      if (adc_state(adc, TIVA_ADC_ENABLE) < 0)
         {
           adcvdbg("ERROR: failure to power ADC peripheral (devno=%d)\n",
                   adc_num);
           return NULL;
         }
 
-      /* Set clock */
+      /* set clock */
 
       adc_clock(CONFIG_TIVA_ADC_CLOCK);
 
-      /* Set sampling rate */
+      /* set sampling rate */
 
       adc_sample_rate(TIVA_ADC_SAMPLE_RATE_FASTEST);
 
-#ifdef CONFIG_ARCH_CHIP_TM4C129
-      /* Voltage reference */
+#  ifdef CONFIG_ARCH_CHIP_TM4C129
+      /* voltage reference */
 
       adc_vref();
-#endif /* CONFIG_ARCH_CHIP_TM4C129 */
-
+#  endif                               /* CONFIG_ARCH_CHIP_TM4C129 */
       adc_common.init[adc->devno] = true;
     }
 
   /* Initialize peripheral */
 
-  /* Have we already been initialized? If yes, than just hand out the interface 
+  /* Have we already been initialized? If yes, than just hand out the interface
    * one more time.
    */
 
   if (adc->ena == false)
     {
-#if CONFIG_TIVA_ADC0
+#  if CONFIG_TIVA_ADC0
       if (adc_num == 0)
         {
           /* Configure sample sequencers */
@@ -1551,9 +1551,9 @@ struct adc_dev_s *tiva_adc_initialize(int adc_num)
           tiva_adc0_assign_interrupts();
           tiva_adc0_assign_channels();
         }
-#endif
+#  endif
 
-#if CONFIG_TIVA_ADC1
+#  if CONFIG_TIVA_ADC1
       if (adc_num == 1)
         {
           /* Configure sample sequencers */
@@ -1565,14 +1565,15 @@ struct adc_dev_s *tiva_adc_initialize(int adc_num)
           tiva_adc1_assign_interrupts();
           tiva_adc1_assign_channels();
         }
-#endif
+#  endif
+
       /* Enable SSEs */
 
       for (s = 0; s < SSE_PER_BASE; ++s)
         {
           if (adc_common.sse[SSE_IDX(adc_num, s)])
             {
-              sse_state(adc, s, ENABLE);
+              sse_state(adc, s, TIVA_ADC_ENABLE);
               sse_clear_int(adc, s);
             }
         }
@@ -1604,7 +1605,7 @@ void tiva_adc_lock(FAR struct tiva_adc_s *priv, int sse)
     {
       ret = sem_wait(&priv->sse[sse]->exclsem);
 
-      /* This should only fail if the wait was canceled by an signal * (and the 
+      /* This should only fail if the wait was canceled by an signal (and the
        * worker thread will receive a lot of signals).
        */
 
@@ -1635,7 +1636,7 @@ void tiva_adc_unlock(FAR struct tiva_adc_s *priv, int sse)
  *
  ****************************************************************************/
 
-#ifdef CONFIG_TIVA_ADC_REGDEBUG
+#  ifdef CONFIG_TIVA_ADC_REGDEBUG
 uint32_t tiva_adc_getreg(struct tiva_adc_s *priv, uintptr_t address)
 {
   uint32_t regval = getreg32(address);
@@ -1666,7 +1667,7 @@ void tiva_adc_putreg(struct tiva_adc_s *priv, uintptr_t address,
 
   putreg32(regval, address);
 }
-#endif /* CONFIG_TIVA_ADC_REGDEBUG */
+#  endif                               /* CONFIG_TIVA_ADC_REGDEBUG */
 
 /****************************************************************************
  * Name: Verbose, generated code
@@ -1679,79 +1680,79 @@ void tiva_adc_putreg(struct tiva_adc_s *priv, uintptr_t address,
 
 /* Sample sequencer initialization ******************************************/
 
-#ifdef CONFIG_TIVA_ADC0
+#  ifdef CONFIG_TIVA_ADC0
 static void tiva_adc0_sse_init(void)
 {
-#  ifdef CONFIG_TIVA_ADC0_SSE0
-  sse_state(&adc0, 0, DISABLE);
+#    ifdef CONFIG_TIVA_ADC0_SSE0
+  sse_state(&adc0, 0, TIVA_ADC_DISABLE);
   sse_priority(&adc0, 0, CONFIG_TIVA_ADC0_SSE0_PRIORITY);
   sse_trigger(&adc0, 0, CONFIG_TIVA_ADC0_SSE0_TRIGGER);
   adc_common.sse[SSE_IDX(0, 0)] = true;
-#  endif
+#    endif
 
-#  ifdef CONFIG_TIVA_ADC0_SSE1
-  sse_state(&adc0, 1, DISABLE);
+#    ifdef CONFIG_TIVA_ADC0_SSE1
+  sse_state(&adc0, 1, TIVA_ADC_DISABLE);
   sse_priority(&adc0, 1, CONFIG_TIVA_ADC0_SSE1_PRIORITY);
   sse_trigger(&adc0, 1, CONFIG_TIVA_ADC0_SSE1_TRIGGER);
   adc_common.sse[SSE_IDX(0, 1)] = true;
-#  endif
+#    endif
 
-#  ifdef CONFIG_TIVA_ADC0_SSE2
-  sse_state(&adc0, 2, DISABLE);
+#    ifdef CONFIG_TIVA_ADC0_SSE2
+  sse_state(&adc0, 2, TIVA_ADC_DISABLE);
   sse_priority(&adc0, 2, CONFIG_TIVA_ADC0_SSE2_PRIORITY);
   sse_trigger(&adc0, 2, CONFIG_TIVA_ADC0_SSE2_TRIGGER);
   adc_common.sse[SSE_IDX(0, 2)] = true;
-#  endif
+#    endif
 
-#  ifdef CONFIG_TIVA_ADC0_SSE3
-  sse_state(&adc0, 3, DISABLE);
+#    ifdef CONFIG_TIVA_ADC0_SSE3
+  sse_state(&adc0, 3, TIVA_ADC_DISABLE);
   sse_priority(&adc0, 3, CONFIG_TIVA_ADC0_SSE3_PRIORITY);
   sse_trigger(&adc0, 3, CONFIG_TIVA_ADC0_SSE3_TRIGGER);
   adc_common.sse[SSE_IDX(0, 3)] = true;
-#  endif
+#    endif
 }
-#endif /* CONFIG_TIVA_ADC0 */
+#  endif                               /* CONFIG_TIVA_ADC0 */
 
-#ifdef CONFIG_TIVA_ADC1
+#  ifdef CONFIG_TIVA_ADC1
 static void tiva_adc1_sse_init(void)
 {
-#  ifdef CONFIG_TIVA_ADC1_SSE0
-  sse_state(&adc1, 0, DISABLE);
+#    ifdef CONFIG_TIVA_ADC1_SSE0
+  sse_state(&adc1, 0, TIVA_ADC_DISABLE);
   sse_priority(&adc1, 0, CONFIG_TIVA_ADC1_SSE0_PRIORITY);
   sse_trigger(&adc1, 0, CONFIG_TIVA_ADC1_SSE0_TRIGGER);
   adc_common.sse[SSE_IDX(1, 0)] = true;
-#  endif
+#    endif
 
-#  ifdef CONFIG_TIVA_ADC1_SSE1
-  sse_state(&adc1, 1, DISABLE);
+#    ifdef CONFIG_TIVA_ADC1_SSE1
+  sse_state(&adc1, 1, TIVA_ADC_DISABLE);
   sse_priority(&adc1, 1, CONFIG_TIVA_ADC1_SSE1_PRIORITY);
   sse_trigger(&adc1, 1, CONFIG_TIVA_ADC1_SSE1_TRIGGER);
   adc_common.sse[SSE_IDX(1, 1)] = true;
-#  endif
+#    endif
 
-#  ifdef CONFIG_TIVA_ADC1_SSE2
-  sse_state(&adc1, 2, DISABLE);
+#    ifdef CONFIG_TIVA_ADC1_SSE2
+  sse_state(&adc1, 2, TIVA_ADC_DISABLE);
   sse_priority(&adc1, 2, CONFIG_TIVA_ADC1_SSE2_PRIORITY);
   sse_trigger(&adc1, 2, CONFIG_TIVA_ADC1_SSE2_TRIGGER);
   adc_common.sse[SSE_IDX(1, 2)] = true;
-#  endif
+#    endif
 
-#  ifdef CONFIG_TIVA_ADC1_SSE3
-  sse_state(&adc1, 3, DISABLE);
+#    ifdef CONFIG_TIVA_ADC1_SSE3
+  sse_state(&adc1, 3, TIVA_ADC_DISABLE);
   sse_priority(&adc1, 3, CONFIG_TIVA_ADC1_SSE3_PRIORITY);
   sse_trigger(&adc1, 3, CONFIG_TIVA_ADC1_SSE3_TRIGGER);
   adc_common.sse[SSE_IDX(1, 3)] = true;
-#  endif
+#    endif
 }
-#endif /* CONFIG_TIVA_ADC1 */
+#  endif                               /* CONFIG_TIVA_ADC1 */
 
 /* Sample sequencer interrupt initialization ********************************/
 
-#ifdef CONFIG_TIVA_ADC0
+#  ifdef CONFIG_TIVA_ADC0
 static void tiva_adc0_assign_interrupts(void)
 {
   uint32_t ret = 0;
-#  ifdef CONFIG_TIVA_ADC0_SSE0
+#    ifdef CONFIG_TIVA_ADC0_SSE0
   ret = irq_attach(sse00.irq, (xcpt_t) adc0_sse0_interrupt);
   if (ret < 0)
     {
@@ -1760,9 +1761,9 @@ static void tiva_adc0_assign_interrupts(void)
     }
 
   up_enable_irq(sse00.irq);
-#  endif /* CONFIG_TIVA_ADC0_SSE0 */
+#    endif                             /* CONFIG_TIVA_ADC0_SSE0 */
 
-#  ifdef CONFIG_TIVA_ADC0_SSE1
+#    ifdef CONFIG_TIVA_ADC0_SSE1
   ret = irq_attach(sse01.irq, (xcpt_t) adc0_sse1_interrupt);
   if (ret < 0)
     {
@@ -1771,9 +1772,9 @@ static void tiva_adc0_assign_interrupts(void)
     }
 
   up_enable_irq(sse01.irq);
-#  endif /* CONFIG_TIVA_ADC0_SSE1 */
+#    endif                             /* CONFIG_TIVA_ADC0_SSE1 */
 
-#  ifdef CONFIG_TIVA_ADC0_SSE2
+#    ifdef CONFIG_TIVA_ADC0_SSE2
   ret = irq_attach(sse02.irq, (xcpt_t) adc0_sse2_interrupt);
   if (ret < 0)
     {
@@ -1782,9 +1783,9 @@ static void tiva_adc0_assign_interrupts(void)
     }
 
   up_enable_irq(sse02.irq);
-#  endif /* CONFIG_TIVA_ADC0_SSE2 */
+#    endif                             /* CONFIG_TIVA_ADC0_SSE2 */
 
-#  ifdef CONFIG_TIVA_ADC0_SSE3
+#    ifdef CONFIG_TIVA_ADC0_SSE3
   ret = irq_attach(sse03.irq, (xcpt_t) adc0_sse3_interrupt);
   if (ret < 0)
     {
@@ -1793,15 +1794,15 @@ static void tiva_adc0_assign_interrupts(void)
     }
 
   up_enable_irq(sse03.irq);
-#  endif /* CONFIG_TIVA_ADC0_SSE3 */
+#    endif                             /* CONFIG_TIVA_ADC0_SSE3 */
 };
-#endif /* CONFIG_TIVA_ADC0 */
+#  endif                               /* CONFIG_TIVA_ADC0 */
 
-#ifdef CONFIG_TIVA_ADC1
+#  ifdef CONFIG_TIVA_ADC1
 static void tiva_adc1_assign_interrupts(void)
 {
   uint32_t ret = 0;
-#  ifdef CONFIG_TIVA_ADC1_SSE0
+#    ifdef CONFIG_TIVA_ADC1_SSE0
   ret = irq_attach(sse10.irq, (xcpt_t) adc1_sse0_interrupt);
   if (ret < 0)
     {
@@ -1810,9 +1811,9 @@ static void tiva_adc1_assign_interrupts(void)
     }
 
   up_enable_irq(sse10.irq);
-#  endif /* CONFIG_TIVA_ADC1_SSE0 */
+#    endif                             /* CONFIG_TIVA_ADC1_SSE0 */
 
-#  ifdef CONFIG_TIVA_ADC1_SSE1
+#    ifdef CONFIG_TIVA_ADC1_SSE1
   ret = irq_attach(sse11.irq, (xcpt_t) adc1_sse1_interrupt);
   if (ret < 0)
     {
@@ -1821,9 +1822,9 @@ static void tiva_adc1_assign_interrupts(void)
     }
 
   up_enable_irq(sse11.irq);
-#  endif /* CONFIG_TIVA_ADC1_SSE1 */
+#    endif                             /* CONFIG_TIVA_ADC1_SSE1 */
 
-#  ifdef CONFIG_TIVA_ADC1_SSE2
+#    ifdef CONFIG_TIVA_ADC1_SSE2
   ret = irq_attach(sse12.irq, (xcpt_t) adc1_sse2_interrupt);
   if (ret < 0)
     {
@@ -1832,9 +1833,9 @@ static void tiva_adc1_assign_interrupts(void)
     }
 
   up_enable_irq(sse12.irq);
-#  endif /* CONFIG_TIVA_ADC1_SSE2 */
+#    endif                             /* CONFIG_TIVA_ADC1_SSE2 */
 
-#  ifdef CONFIG_TIVA_ADC1_SSE3
+#    ifdef CONFIG_TIVA_ADC1_SSE3
   ret = irq_attach(sse13.irq, (xcpt_t) adc1_sse3_interrupt);
   if (ret < 0)
     {
@@ -1843,18 +1844,18 @@ static void tiva_adc1_assign_interrupts(void)
     }
 
   up_enable_irq(sse13.irq);
-#  endif /* CONFIG_TIVA_ADC1_SSE3 */
+#    endif                             /* CONFIG_TIVA_ADC1_SSE3 */
 };
-#endif /* CONFIG_TIVA_ADC1 */
+#  endif                               /* CONFIG_TIVA_ADC1 */
 
 /* Sample sequencer interrupt declaration ********************************/
 
-#ifdef CONFIG_TIVA_ADC0
-#  ifdef CONFIG_TIVA_ADC0_SSE0
+#  ifdef CONFIG_TIVA_ADC0
+#    ifdef CONFIG_TIVA_ADC0_SSE0
 static void adc0_sse0_interrupt(int irq, void *context)
 {
   uint8_t fifo_count = 0;
-  sse_int_state(&adc0, 0, DISABLE);
+  sse_int_state(&adc0, 0, TIVA_ADC_DISABLE);
   sse_clear_int(&adc0, 0);
   tiva_adc_lock(&adc0, 0);
   while (!(tiva_adc_getreg(&adc0, TIVA_ADC_BASE(0) + TIVA_ADC_SSFSTAT(0)) &
@@ -1865,16 +1866,16 @@ static void adc0_sse0_interrupt(int irq, void *context)
       (void)adc_receive(adc0.dev, GET_AIN(0, 0, fifo_count), data);
     }
 
-  sse_int_state(&adc0, 0, ENABLE);
+  sse_int_state(&adc0, 0, TIVA_ADC_ENABLE);
   tiva_adc_unlock(&adc0, 0);
 }
-#  endif /* CONFIG_TIVA_ADC0_SSE0 */
+#    endif                             /* CONFIG_TIVA_ADC0_SSE0 */
 
-#  ifdef CONFIG_TIVA_ADC0_SSE1
+#    ifdef CONFIG_TIVA_ADC0_SSE1
 static void adc0_sse1_interrupt(int irq, void *context)
 {
   uint8_t fifo_count = 0;
-  sse_int_state(&adc0, 1, DISABLE);
+  sse_int_state(&adc0, 1, TIVA_ADC_DISABLE);
   sse_clear_int(&adc0, 1);
   tiva_adc_lock(&adc0, 1);
   while (!(tiva_adc_getreg(&adc0, TIVA_ADC_BASE(0) + TIVA_ADC_SSFSTAT(1)) &
@@ -1885,16 +1886,16 @@ static void adc0_sse1_interrupt(int irq, void *context)
       (void)adc_receive(adc0.dev, GET_AIN(0, 1, fifo_count), data);
     }
 
-  sse_int_state(&adc0, 1, ENABLE);
+  sse_int_state(&adc0, 1, TIVA_ADC_ENABLE);
   tiva_adc_unlock(&adc0, 1);
 }
-#  endif /* CONFIG_TIVA_ADC0_SSE1 */
+#    endif                             /* CONFIG_TIVA_ADC0_SSE1 */
 
-#  ifdef CONFIG_TIVA_ADC0_SSE2
+#    ifdef CONFIG_TIVA_ADC0_SSE2
 static void adc0_sse2_interrupt(int irq, void *context)
 {
   uint8_t fifo_count = 0;
-  sse_int_state(&adc0, 2, DISABLE);
+  sse_int_state(&adc0, 2, TIVA_ADC_DISABLE);
   sse_clear_int(&adc0, 2);
   tiva_adc_lock(&adc0, 2);
   while (!(tiva_adc_getreg(&adc0, TIVA_ADC_BASE(0) + TIVA_ADC_SSFSTAT(2)) &
@@ -1905,16 +1906,16 @@ static void adc0_sse2_interrupt(int irq, void *context)
       (void)adc_receive(adc0.dev, GET_AIN(0, 2, fifo_count), data);
     }
 
-  sse_int_state(&adc0, 2, ENABLE);
+  sse_int_state(&adc0, 2, TIVA_ADC_ENABLE);
   tiva_adc_unlock(&adc0, 2);
 }
-#  endif /* CONFIG_TIVA_ADC0_SSE2 */
+#    endif                             /* CONFIG_TIVA_ADC0_SSE2 */
 
-#  ifdef CONFIG_TIVA_ADC0_SSE3
+#    ifdef CONFIG_TIVA_ADC0_SSE3
 static void adc0_sse3_interrupt(int irq, void *context)
 {
   uint8_t fifo_count = 0;
-  sse_int_state(&adc0, 3, DISABLE);
+  sse_int_state(&adc0, 3, TIVA_ADC_DISABLE);
   sse_clear_int(&adc0, 3);
   tiva_adc_lock(&adc0, 3);
   while (!(tiva_adc_getreg(&adc0, TIVA_ADC_BASE(0) + TIVA_ADC_SSFSTAT(3)) &
@@ -1925,18 +1926,18 @@ static void adc0_sse3_interrupt(int irq, void *context)
       (void)adc_receive(adc0.dev, GET_AIN(0, 3, fifo_count), data);
     }
 
-  sse_int_state(&adc0, 3, ENABLE);
+  sse_int_state(&adc0, 3, TIVA_ADC_ENABLE);
   tiva_adc_unlock(&adc0, 3);
 }
-#  endif /* CONFIG_TIVA_ADC0_SSE3 */
-#endif /* CONFIG_TIVA_ADC0 */
+#    endif                             /* CONFIG_TIVA_ADC0_SSE3 */
+#  endif                               /* CONFIG_TIVA_ADC0 */
 
-#ifdef CONFIG_TIVA_ADC1
-#  ifdef CONFIG_TIVA_ADC1_SSE0
+#  ifdef CONFIG_TIVA_ADC1
+#    ifdef CONFIG_TIVA_ADC1_SSE0
 static void adc1_sse0_interrupt(int irq, void *context)
 {
   uint8_t fifo_count = 0;
-  sse_int_state(&adc1, 0, DISABLE);
+  sse_int_state(&adc1, 0, TIVA_ADC_DISABLE);
   sse_clear_int(&adc1, 0);
   tiva_adc_lock(&adc1, 0);
   while (!(tiva_adc_getreg(&adc1, TIVA_ADC_BASE(1) + TIVA_ADC_SSFSTAT(0)) &
@@ -1947,16 +1948,16 @@ static void adc1_sse0_interrupt(int irq, void *context)
       (void)adc_receive(adc1.dev, GET_AIN(1, 0, fifo_count), data);
     }
 
-  sse_int_state(&adc1, 0, ENABLE);
+  sse_int_state(&adc1, 0, TIVA_ADC_ENABLE);
   tiva_adc_unlock(&adc1, 0);
 }
-#  endif /* CONFIG_TIVA_ADC1_SSE0 */
+#    endif                             /* CONFIG_TIVA_ADC1_SSE0 */
 
-#  ifdef CONFIG_TIVA_ADC1_SSE1
+#    ifdef CONFIG_TIVA_ADC1_SSE1
 static void adc1_sse1_interrupt(int irq, void *context)
 {
   uint8_t fifo_count = 0;
-  sse_int_state(&adc1, 1, DISABLE);
+  sse_int_state(&adc1, 1, TIVA_ADC_DISABLE);
   sse_clear_int(&adc1, 1);
   tiva_adc_lock(&adc1, 1);
   while (!(tiva_adc_getreg(&adc1, TIVA_ADC_BASE(1) + TIVA_ADC_SSFSTAT(1)) &
@@ -1967,16 +1968,16 @@ static void adc1_sse1_interrupt(int irq, void *context)
       (void)adc_receive(adc1.dev, GET_AIN(1, 1, fifo_count), data);
     }
 
-  sse_int_state(&adc1, 1, ENABLE);
+  sse_int_state(&adc1, 1, TIVA_ADC_ENABLE);
   tiva_adc_unlock(&adc1, 1);
 }
-#  endif /* CONFIG_TIVA_ADC1_SSE1 */
+#    endif                             /* CONFIG_TIVA_ADC1_SSE1 */
 
-#  ifdef CONFIG_TIVA_ADC1_SSE2
+#    ifdef CONFIG_TIVA_ADC1_SSE2
 static void adc1_sse2_interrupt(int irq, void *context)
 {
   uint8_t fifo_count = 0;
-  sse_int_state(&adc1, 2, DISABLE);
+  sse_int_state(&adc1, 2, TIVA_ADC_DISABLE);
   sse_clear_int(&adc1, 2);
   tiva_adc_lock(&adc1, 2);
   while (!(tiva_adc_getreg(&adc1, TIVA_ADC_BASE(1) + TIVA_ADC_SSFSTAT(2)) &
@@ -1987,16 +1988,16 @@ static void adc1_sse2_interrupt(int irq, void *context)
       (void)adc_receive(adc1.dev, GET_AIN(1, 2, fifo_count), data);
     }
 
-  sse_int_state(&adc1, 2, ENABLE);
+  sse_int_state(&adc1, 2, TIVA_ADC_ENABLE);
   tiva_adc_unlock(&adc1, 2);
 }
-#  endif /* CONFIG_TIVA_ADC1_SSE2 */
+#    endif                             /* CONFIG_TIVA_ADC1_SSE2 */
 
-#  ifdef CONFIG_TIVA_ADC1_SSE3
+#    ifdef CONFIG_TIVA_ADC1_SSE3
 static void adc1_sse3_interrupt(int irq, void *context)
 {
   uint8_t fifo_count = 0;
-  sse_int_state(&adc1, 3, DISABLE);
+  sse_int_state(&adc1, 3, TIVA_ADC_DISABLE);
   sse_clear_int(&adc1, 3);
   tiva_adc_lock(&adc1, 3);
   while (!(tiva_adc_getreg(&adc1, TIVA_ADC_BASE(1) + TIVA_ADC_SSFSTAT(3)) &
@@ -2007,792 +2008,887 @@ static void adc1_sse3_interrupt(int irq, void *context)
       (void)adc_receive(adc1.dev, GET_AIN(1, 3, fifo_count), data);
     }
 
-  sse_int_state(&adc1, 3, ENABLE);
+  sse_int_state(&adc1, 3, TIVA_ADC_ENABLE);
   tiva_adc_unlock(&adc1, 3);
 }
-#  endif /* CONFIG_TIVA_ADC1_SSE3 */
-#endif /* CONFIG_TIVA_ADC1 */
+#    endif                             /* CONFIG_TIVA_ADC1_SSE3 */
+#  endif                               /* CONFIG_TIVA_ADC1 */
 
 /* Channel assignment *******************************************************/
 
-#ifdef CONFIG_TIVA_ADC0
+#  ifdef CONFIG_TIVA_ADC0
 static void tiva_adc0_assign_channels(void)
 {
-#  ifdef CONFIG_TIVA_ADC0_SSE0
+#    ifdef CONFIG_TIVA_ADC0_SSE0
   adc0_sse0_chn_cfg();
-#  endif
+#    endif
 
-#  ifdef CONFIG_TIVA_ADC0_SSE1
+#    ifdef CONFIG_TIVA_ADC0_SSE1
   adc0_sse1_chn_cfg();
-#  endif
+#    endif
 
-#  ifdef CONFIG_TIVA_ADC0_SSE2
+#    ifdef CONFIG_TIVA_ADC0_SSE2
   adc0_sse2_chn_cfg();
-#  endif
+#    endif
 
-#  ifdef CONFIG_TIVA_ADC0_SSE3
+#    ifdef CONFIG_TIVA_ADC0_SSE3
   adc0_sse3_chn_cfg();
-#  endif
+#    endif
 }
-#endif /* CONFIG_TIVA_ADC0 */
+#  endif                               /* CONFIG_TIVA_ADC0 */
 
-#ifdef CONFIG_TIVA_ADC1
+#  ifdef CONFIG_TIVA_ADC1
 static void tiva_adc1_assign_channels(void)
 {
-#  ifdef CONFIG_TIVA_ADC1_SSE0
+#    ifdef CONFIG_TIVA_ADC1_SSE0
   adc1_sse0_chn_cfg();
-#  endif
+#    endif
 
-#  ifdef CONFIG_TIVA_ADC1_SSE1
+#    ifdef CONFIG_TIVA_ADC1_SSE1
   adc1_sse1_chn_cfg();
-#  endif
+#    endif
 
-#  ifdef CONFIG_TIVA_ADC1_SSE2
+#    ifdef CONFIG_TIVA_ADC1_SSE2
   adc1_sse2_chn_cfg();
-#  endif
+#    endif
 
-#  ifdef CONFIG_TIVA_ADC1_SSE3
+#    ifdef CONFIG_TIVA_ADC1_SSE3
   adc1_sse3_chn_cfg();
-#  endif
+#    endif
 }
-#endif /* CONFIG_TIVA_ADC1 */
+#  endif                               /* CONFIG_TIVA_ADC1 */
 
-/* Channel config ************************************************************/
+/* Channel config ***********************************************************/
 
-#ifdef CONFIG_TIVA_ADC0
-#  ifdef CONFIG_TIVA_ADC0_SSE0
+#  ifdef CONFIG_TIVA_ADC0
+#    ifdef CONFIG_TIVA_ADC0_SSE0
 static void adc0_sse0_chn_cfg(void)
 {
   uint32_t chncfg = 0;
-#    ifdef CONFIG_TIVA_ADC0_SSE0_STEP0
-#      ifdef CONFIG_TIVA_ADC0_SSE0_STEP0_TS
+#      ifdef CONFIG_TIVA_ADC0_SSE0_STEP0
+#        ifdef CONFIG_TIVA_ADC0_SSE0_STEP0_TS
   chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
-#      else /* ADC_SSCTL_IE */
+#        else                          /* ADC_SSCTL_IE */
   chncfg = ADC_SSCTL_IE;
-#      endif /* CONFIG_TIVA_ADC0_SSE0_STEP0_TS */
+#        endif                         /* CONFIG_TIVA_ADC0_SSE0_STEP0_TS */
 
   tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC0_SSE0_STEP0_AIN));
   sse_register_chn(&adc0, 0, 0, CONFIG_TIVA_ADC0_SSE0_STEP0_AIN);
   sse_differential(&adc0, 0, 0, 0);
-#      if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC0_SSE0_TRIGGER == ADC_EMUX_PROC)
+#        if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC0_SSE0_TRIGGER == ADC_EMUX_PROC)
   sse_sample_hold_time(&adc0, 0, 0, ADC_SSTH_SHOLD_16);
-#      endif /* (CONFIG_TIVA_ADC0_SSE0_TRIGGER == ADC_EMUX_PROC) && defined(CONFIG_ARCH_CHIP_TM4C129) */
+#        endif                         /* (CONFIG_TIVA_ADC0_SSE0_TRIGGER ==
+                                        * ADC_EMUX_PROC) && defined
+                                        * (CONFIG_ARCH_CHIP_TM4C129) */
+
+#        ifndef CONFIG_TIVA_ADC0_SSE0_STEP1
+  sse_step_cfg(&adc0, 0, 0, chncfg | ADC_SSCTL_END);
 
-#      ifndef CONFIG_TIVA_ADC0_SSE0_STEP1
-  sse_step_cfg(&adc0, 0, 0, chncfg | ADC_SSCTL_END);    /* Signal as last step in the sequence */
-#      else /* CONFIG_TIVA_ADC0_SSE0_STEP1 */
+#        else                          /* CONFIG_TIVA_ADC0_SSE0_STEP1 */
   sse_step_cfg(&adc0, 0, 0, chncfg);
-#      endif /* !CONFIG_TIVA_ADC0_SSE0_STEP1 */
+#        endif                         /* !CONFIG_TIVA_ADC0_SSE0_STEP1 */
 
-#      ifdef CONFIG_TIVA_ADC0_SSE0_STEP1
-#        ifdef CONFIG_TIVA_ADC0_SSE0_STEP1_TS
+#        ifdef CONFIG_TIVA_ADC0_SSE0_STEP1
+#          ifdef CONFIG_TIVA_ADC0_SSE0_STEP1_TS
   chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
-#        else /* ADC_SSCTL_IE */
+#          else                        /* ADC_SSCTL_IE */
   chncfg = ADC_SSCTL_IE;
-#        endif /* CONFIG_TIVA_ADC0_SSE0_STEP1_TS */
+#          endif                       /* CONFIG_TIVA_ADC0_SSE0_STEP1_TS */
 
   tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC0_SSE0_STEP1_AIN));
   sse_register_chn(&adc0, 0, 1, CONFIG_TIVA_ADC0_SSE0_STEP1_AIN);
   sse_differential(&adc0, 0, 1, 0);
-#        if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC0_SSE0_TRIGGER == ADC_EMUX_PROC)
+#          if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC0_SSE0_TRIGGER == ADC_EMUX_PROC)
   sse_sample_hold_time(&adc0, 0, 1, ADC_SSTH_SHOLD_16);
-#        endif /* (CONFIG_TIVA_ADC0_SSE0_TRIGGER == ADC_EMUX_PROC) && defined(CONFIG_ARCH_CHIP_TM4C129) */
+#          endif                       /* (CONFIG_TIVA_ADC0_SSE0_TRIGGER ==
+                                        * ADC_EMUX_PROC) && defined
+                                        * (CONFIG_ARCH_CHIP_TM4C129) */
+
+#          ifndef CONFIG_TIVA_ADC0_SSE0_STEP2
+  sse_step_cfg(&adc0, 0, 1, chncfg | ADC_SSCTL_END);
 
-#        ifndef CONFIG_TIVA_ADC0_SSE0_STEP2
-  sse_step_cfg(&adc0, 0, 1, chncfg | ADC_SSCTL_END);    /* Signal as last step in the sequence */
-#        else /* CONFIG_TIVA_ADC0_SSE0_STEP2 */
+#          else                        /* CONFIG_TIVA_ADC0_SSE0_STEP2 */
   sse_step_cfg(&adc0, 0, 1, chncfg);
-#        endif /* !CONFIG_TIVA_ADC0_SSE0_STEP2 */
+#          endif                       /* !CONFIG_TIVA_ADC0_SSE0_STEP2 */
 
-#        ifdef CONFIG_TIVA_ADC0_SSE0_STEP2
-#          ifdef CONFIG_TIVA_ADC0_SSE0_STEP2_TS
+#          ifdef CONFIG_TIVA_ADC0_SSE0_STEP2
+#            ifdef CONFIG_TIVA_ADC0_SSE0_STEP2_TS
   chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
-#          else /* ADC_SSCTL_IE */
+#            else                      /* ADC_SSCTL_IE */
   chncfg = ADC_SSCTL_IE;
-#          endif /* CONFIG_TIVA_ADC0_SSE0_STEP2_TS */
+#            endif                     /* CONFIG_TIVA_ADC0_SSE0_STEP2_TS */
 
   tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC0_SSE0_STEP2_AIN));
   sse_register_chn(&adc0, 0, 2, CONFIG_TIVA_ADC0_SSE0_STEP2_AIN);
   sse_differential(&adc0, 0, 2, 0);
-#          if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC0_SSE0_TRIGGER == ADC_EMUX_PROC)
+#            if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC0_SSE0_TRIGGER == ADC_EMUX_PROC)
   sse_sample_hold_time(&adc0, 0, 2, ADC_SSTH_SHOLD_16);
-#          endif /* (CONFIG_TIVA_ADC0_SSE0_TRIGGER == ADC_EMUX_PROC) && defined(CONFIG_ARCH_CHIP_TM4C129) */
+#            endif                     /* (CONFIG_TIVA_ADC0_SSE0_TRIGGER ==
+                                        * ADC_EMUX_PROC) && defined
+                                        * (CONFIG_ARCH_CHIP_TM4C129) */
+
+#            ifndef CONFIG_TIVA_ADC0_SSE0_STEP3
+  sse_step_cfg(&adc0, 0, 2, chncfg | ADC_SSCTL_END);
 
-#          ifndef CONFIG_TIVA_ADC0_SSE0_STEP3
-  sse_step_cfg(&adc0, 0, 2, chncfg | ADC_SSCTL_END);    /* Signal as last step in the sequence */
-#          else /* CONFIG_TIVA_ADC0_SSE0_STEP3 */
+#            else                      /* CONFIG_TIVA_ADC0_SSE0_STEP3 */
   sse_step_cfg(&adc0, 0, 2, chncfg);
-#          endif /* !CONFIG_TIVA_ADC0_SSE0_STEP3 */
+#            endif                     /* !CONFIG_TIVA_ADC0_SSE0_STEP3 */
 
-#          ifdef CONFIG_TIVA_ADC0_SSE0_STEP3
-#            ifdef CONFIG_TIVA_ADC0_SSE0_STEP3_TS
+#            ifdef CONFIG_TIVA_ADC0_SSE0_STEP3
+#              ifdef CONFIG_TIVA_ADC0_SSE0_STEP3_TS
   chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
-#            else /* ADC_SSCTL_IE */
+#              else                    /* ADC_SSCTL_IE */
   chncfg = ADC_SSCTL_IE;
-#            endif /* CONFIG_TIVA_ADC0_SSE0_STEP3_TS */
-
+#              endif                   /* CONFIG_TIVA_ADC0_SSE0_STEP3_TS */
   tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC0_SSE0_STEP3_AIN));
   sse_register_chn(&adc0, 0, 3, CONFIG_TIVA_ADC0_SSE0_STEP3_AIN);
   sse_differential(&adc0, 0, 3, 0);
-#            if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC0_SSE0_TRIGGER == ADC_EMUX_PROC)
+#              if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC0_SSE0_TRIGGER == ADC_EMUX_PROC)
   sse_sample_hold_time(&adc0, 0, 3, ADC_SSTH_SHOLD_16);
-#            endif /* (CONFIG_TIVA_ADC0_SSE0_TRIGGER == ADC_EMUX_PROC) && defined(CONFIG_ARCH_CHIP_TM4C129) */
+#              endif                   /* (CONFIG_TIVA_ADC0_SSE0_TRIGGER ==
+                                        * ADC_EMUX_PROC) && defined
+                                        * (CONFIG_ARCH_CHIP_TM4C129) */
 
-#            ifndef CONFIG_TIVA_ADC0_SSE0_STEP4
-  sse_step_cfg(&adc0, 0, 3, chncfg | ADC_SSCTL_END);    /* Signal as last step in the sequence */
-#            else /* CONFIG_TIVA_ADC0_SSE0_STEP4 */
+#              ifndef CONFIG_TIVA_ADC0_SSE0_STEP4
+  sse_step_cfg(&adc0, 0, 3, chncfg | ADC_SSCTL_END);
+#              else                    /* CONFIG_TIVA_ADC0_SSE0_STEP4 */
   sse_step_cfg(&adc0, 0, 3, chncfg);
-#            endif /* !CONFIG_TIVA_ADC0_SSE0_STEP4 */
+#              endif                   /* !CONFIG_TIVA_ADC0_SSE0_STEP4 */
 
-#            ifdef CONFIG_TIVA_ADC0_SSE0_STEP4
-#              ifdef CONFIG_TIVA_ADC0_SSE0_STEP4_TS
+#              ifdef CONFIG_TIVA_ADC0_SSE0_STEP4
+#                ifdef CONFIG_TIVA_ADC0_SSE0_STEP4_TS
   chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
-#              else /* ADC_SSCTL_IE */
+#                else                  /* ADC_SSCTL_IE */
   chncfg = ADC_SSCTL_IE;
-#              endif /* CONFIG_TIVA_ADC0_SSE0_STEP4_TS */
+#                endif                 /* CONFIG_TIVA_ADC0_SSE0_STEP4_TS */
 
   tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC0_SSE0_STEP4_AIN));
   sse_register_chn(&adc0, 0, 4, CONFIG_TIVA_ADC0_SSE0_STEP4_AIN);
   sse_differential(&adc0, 0, 4, 0);
-#              if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC0_SSE0_TRIGGER == ADC_EMUX_PROC)
+#                if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC0_SSE0_TRIGGER == ADC_EMUX_PROC)
   sse_sample_hold_time(&adc0, 0, 4, ADC_SSTH_SHOLD_16);
-#              endif /* (CONFIG_TIVA_ADC0_SSE0_TRIGGER == ADC_EMUX_PROC) && defined(CONFIG_ARCH_CHIP_TM4C129) */
+#                endif                 /* (CONFIG_TIVA_ADC0_SSE0_TRIGGER ==
+                                        * ADC_EMUX_PROC) && defined
+                                        * (CONFIG_ARCH_CHIP_TM4C129) */
 
-#              ifndef CONFIG_TIVA_ADC0_SSE0_STEP5
-  sse_step_cfg(&adc0, 0, 4, chncfg | ADC_SSCTL_END);    /* Signal as last step in the sequence */
-#              else /* CONFIG_TIVA_ADC0_SSE0_STEP5 */
+#                ifndef CONFIG_TIVA_ADC0_SSE0_STEP5
+  sse_step_cfg(&adc0, 0, 4, chncfg | ADC_SSCTL_END);
+
+#                else                  /* CONFIG_TIVA_ADC0_SSE0_STEP5 */
   sse_step_cfg(&adc0, 0, 4, chncfg);
-#              endif /* !CONFIG_TIVA_ADC0_SSE0_STEP5 */
+#                endif                 /* !CONFIG_TIVA_ADC0_SSE0_STEP5 */
 
-#              ifdef CONFIG_TIVA_ADC0_SSE0_STEP5
-#                ifdef CONFIG_TIVA_ADC0_SSE0_STEP5_TS
+#                ifdef CONFIG_TIVA_ADC0_SSE0_STEP5
+#                  ifdef CONFIG_TIVA_ADC0_SSE0_STEP5_TS
   chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
-#                else /* ADC_SSCTL_IE */
+#                  else                /* ADC_SSCTL_IE */
   chncfg = ADC_SSCTL_IE;
-#                endif /* CONFIG_TIVA_ADC0_SSE0_STEP5_TS */
-
+#                  endif               /* CONFIG_TIVA_ADC0_SSE0_STEP5_TS */
   tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC0_SSE0_STEP5_AIN));
   sse_register_chn(&adc0, 0, 5, CONFIG_TIVA_ADC0_SSE0_STEP5_AIN);
   sse_differential(&adc0, 0, 5, 0);
-#                if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC0_SSE0_TRIGGER == ADC_EMUX_PROC)
+#                  if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC0_SSE0_TRIGGER == ADC_EMUX_PROC)
   sse_sample_hold_time(&adc0, 0, 5, ADC_SSTH_SHOLD_16);
-#                endif /* (CONFIG_TIVA_ADC0_SSE0_TRIGGER == ADC_EMUX_PROC) && defined(CONFIG_ARCH_CHIP_TM4C129) */
+#                  endif               /* (CONFIG_TIVA_ADC0_SSE0_TRIGGER ==
+                                        * ADC_EMUX_PROC) && defined
+                                        * (CONFIG_ARCH_CHIP_TM4C129) */
+
+#                  ifndef CONFIG_TIVA_ADC0_SSE0_STEP6
+  sse_step_cfg(&adc0, 0, 5, chncfg | ADC_SSCTL_END);
 
-#                ifndef CONFIG_TIVA_ADC0_SSE0_STEP6
-  sse_step_cfg(&adc0, 0, 5, chncfg | ADC_SSCTL_END);    /* Signal as last step in the sequence */
-#                else /* CONFIG_TIVA_ADC0_SSE0_STEP6 */
+#                  else                /* CONFIG_TIVA_ADC0_SSE0_STEP6 */
   sse_step_cfg(&adc0, 0, 5, chncfg);
-#                endif /* !CONFIG_TIVA_ADC0_SSE0_STEP6 */
+#                  endif               /* !CONFIG_TIVA_ADC0_SSE0_STEP6 */
 
-#                ifdef CONFIG_TIVA_ADC0_SSE0_STEP6
-#                  ifdef CONFIG_TIVA_ADC0_SSE0_STEP6_TS
+#                  ifdef CONFIG_TIVA_ADC0_SSE0_STEP6
+#                    ifdef CONFIG_TIVA_ADC0_SSE0_STEP6_TS
   chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
-#                  else /* ADC_SSCTL_IE */
+#                    else              /* ADC_SSCTL_IE */
   chncfg = ADC_SSCTL_IE;
-#                  endif /* CONFIG_TIVA_ADC0_SSE0_STEP6_TS */
+#                    endif             /* CONFIG_TIVA_ADC0_SSE0_STEP6_TS */
 
   tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC0_SSE0_STEP6_AIN));
   sse_register_chn(&adc0, 0, 6, CONFIG_TIVA_ADC0_SSE0_STEP6_AIN);
   sse_differential(&adc0, 0, 6, 0);
-#                  if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC0_SSE0_TRIGGER == ADC_EMUX_PROC)
+#                    if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC0_SSE0_TRIGGER == ADC_EMUX_PROC)
   sse_sample_hold_time(&adc0, 0, 6, ADC_SSTH_SHOLD_16);
-#                  endif /* (CONFIG_TIVA_ADC0_SSE0_TRIGGER == ADC_EMUX_PROC) && defined(CONFIG_ARCH_CHIP_TM4C129) */
+#                    endif             /* (CONFIG_TIVA_ADC0_SSE0_TRIGGER ==
+                                        * ADC_EMUX_PROC) && defined
+                                        * (CONFIG_ARCH_CHIP_TM4C129) */
+
+#                    ifndef CONFIG_TIVA_ADC0_SSE0_STEP7
+  sse_step_cfg(&adc0, 0, 6, chncfg | ADC_SSCTL_END);
 
-#                  ifndef CONFIG_TIVA_ADC0_SSE0_STEP7
-  sse_step_cfg(&adc0, 0, 6, chncfg | ADC_SSCTL_END);    /* Signal as last step in the sequence */
-#                  else /* CONFIG_TIVA_ADC0_SSE0_STEP7 */
+#                    else              /* CONFIG_TIVA_ADC0_SSE0_STEP7 */
   sse_step_cfg(&adc0, 0, 6, chncfg);
-#                  endif /* !CONFIG_TIVA_ADC0_SSE0_STEP7 */
+#                    endif             /* !CONFIG_TIVA_ADC0_SSE0_STEP7 */
 
-#                  ifdef CONFIG_TIVA_ADC0_SSE0_STEP7
-#                    ifdef CONFIG_TIVA_ADC0_SSE0_STEP7_TS
+#                    ifdef CONFIG_TIVA_ADC0_SSE0_STEP7
+#                      ifdef CONFIG_TIVA_ADC0_SSE0_STEP7_TS
   chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
-#                    else /* ADC_SSCTL_IE */
+#                      else            /* ADC_SSCTL_IE */
   chncfg = ADC_SSCTL_IE;
-#                    endif /* CONFIG_TIVA_ADC0_SSE0_STEP7_TS */
+#                      endif           /* CONFIG_TIVA_ADC0_SSE0_STEP7_TS */
 
   tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC0_SSE0_STEP7_AIN));
   sse_register_chn(&adc0, 0, 7, CONFIG_TIVA_ADC0_SSE0_STEP7_AIN);
   sse_differential(&adc0, 0, 7, 0);
-#                    if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC0_SSE0_TRIGGER == ADC_EMUX_PROC)
+#                      if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC0_SSE0_TRIGGER == ADC_EMUX_PROC)
   sse_sample_hold_time(&adc0, 0, 7, ADC_SSTH_SHOLD_16);
-#                    endif /* (CONFIG_TIVA_ADC0_SSE0_TRIGGER == ADC_EMUX_PROC) && defined(CONFIG_ARCH_CHIP_TM4C129) */
-
-  sse_step_cfg(&adc0, 0, 7, chncfg | ADC_SSCTL_END);    /* Signal as last step in the sequence */
-#                  endif /* CONFIG_TIVA_ADC0_SSE0_STEP7 */
-#                endif /* CONFIG_TIVA_ADC0_SSE0_STEP6 */
-#              endif /* CONFIG_TIVA_ADC0_SSE0_STEP5 */
-#            endif /* CONFIG_TIVA_ADC0_SSE0_STEP4 */
-#          endif /* CONFIG_TIVA_ADC0_SSE0_STEP3 */
-#        endif /* CONFIG_TIVA_ADC0_SSE0_STEP2 */
-#      endif /* CONFIG_TIVA_ADC0_SSE0_STEP1 */
-#    endif /* CONFIG_TIVA_ADC0_SSE0_STEP0 */
+#                      endif           /* (CONFIG_TIVA_ADC0_SSE0_TRIGGER ==
+                                        * ADC_EMUX_PROC) && defined
+                                        * (CONFIG_ARCH_CHIP_TM4C129) */
+
+  sse_step_cfg(&adc0, 0, 7, chncfg | ADC_SSCTL_END);
+
+#                    endif             /* CONFIG_TIVA_ADC0_SSE0_STEP7 */
+#                  endif               /* CONFIG_TIVA_ADC0_SSE0_STEP6 */
+#                endif                 /* CONFIG_TIVA_ADC0_SSE0_STEP5 */
+#              endif                   /* CONFIG_TIVA_ADC0_SSE0_STEP4 */
+#            endif                     /* CONFIG_TIVA_ADC0_SSE0_STEP3 */
+#          endif                       /* CONFIG_TIVA_ADC0_SSE0_STEP2 */
+#        endif                         /* CONFIG_TIVA_ADC0_SSE0_STEP1 */
+#      endif                           /* CONFIG_TIVA_ADC0_SSE0_STEP0 */
 }
-#  endif /* CONFIG_TIVA_ADC0_SSE0 */
+#    endif                             /* CONFIG_TIVA_ADC0_SSE0 */
 
-#  ifdef CONFIG_TIVA_ADC0_SSE1
+#    ifdef CONFIG_TIVA_ADC0_SSE1
 static void adc0_sse1_chn_cfg(void)
 {
   uint32_t chncfg = 0;
-#    ifdef CONFIG_TIVA_ADC0_SSE1_STEP0
-#      ifdef CONFIG_TIVA_ADC0_SSE1_STEP0_TS
+#      ifdef CONFIG_TIVA_ADC0_SSE1_STEP0
+#        ifdef CONFIG_TIVA_ADC0_SSE1_STEP0_TS
   chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
-#      else /* ADC_SSCTL_IE */
+#        else                          /* ADC_SSCTL_IE */
   chncfg = ADC_SSCTL_IE;
-#      endif /* CONFIG_TIVA_ADC0_SSE1_STEP0_TS */
+#        endif                         /* CONFIG_TIVA_ADC0_SSE1_STEP0_TS */
 
   tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC0_SSE1_STEP0_AIN));
   sse_register_chn(&adc0, 1, 0, CONFIG_TIVA_ADC0_SSE1_STEP0_AIN);
   sse_differential(&adc0, 1, 0, 0);
-#      if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC0_SSE1_TRIGGER == ADC_EMUX_PROC)
+#        if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC0_SSE1_TRIGGER == ADC_EMUX_PROC)
   sse_sample_hold_time(&adc0, 1, 0, ADC_SSTH_SHOLD_16);
-#      endif /* (CONFIG_TIVA_ADC0_SSE1_TRIGGER == ADC_EMUX_PROC) && defined(CONFIG_ARCH_CHIP_TM4C129) */
+#        endif                         /* (CONFIG_TIVA_ADC0_SSE1_TRIGGER ==
+                                        * ADC_EMUX_PROC) && defined
+                                        * (CONFIG_ARCH_CHIP_TM4C129) */
+
+#        ifndef CONFIG_TIVA_ADC0_SSE1_STEP1
+  sse_step_cfg(&adc0, 1, 0, chncfg | ADC_SSCTL_END);
 
-#      ifndef CONFIG_TIVA_ADC0_SSE1_STEP1
-  sse_step_cfg(&adc0, 1, 0, chncfg | ADC_SSCTL_END);    /* Signal as last step in the sequence */
-#      else /* CONFIG_TIVA_ADC0_SSE1_STEP1 */
+#        else                          /* CONFIG_TIVA_ADC0_SSE1_STEP1 */
   sse_step_cfg(&adc0, 1, 0, chncfg);
-#      endif /* !CONFIG_TIVA_ADC0_SSE1_STEP1 */
+#        endif                         /* !CONFIG_TIVA_ADC0_SSE1_STEP1 */
 
-#      ifdef CONFIG_TIVA_ADC0_SSE1_STEP1
-#        ifdef CONFIG_TIVA_ADC0_SSE1_STEP1_TS
+#        ifdef CONFIG_TIVA_ADC0_SSE1_STEP1
+#          ifdef CONFIG_TIVA_ADC0_SSE1_STEP1_TS
   chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
-#        else /* ADC_SSCTL_IE */
+#          else                        /* ADC_SSCTL_IE */
   chncfg = ADC_SSCTL_IE;
-#        endif /* CONFIG_TIVA_ADC0_SSE1_STEP1_TS */
-
+#          endif                       /* CONFIG_TIVA_ADC0_SSE1_STEP1_TS */
   tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC0_SSE1_STEP1_AIN));
   sse_register_chn(&adc0, 1, 1, CONFIG_TIVA_ADC0_SSE1_STEP1_AIN);
   sse_differential(&adc0, 1, 1, 0);
-#        if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC0_SSE1_TRIGGER == ADC_EMUX_PROC)
+#          if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC0_SSE1_TRIGGER == ADC_EMUX_PROC)
   sse_sample_hold_time(&adc0, 1, 1, ADC_SSTH_SHOLD_16);
-#        endif /* (CONFIG_TIVA_ADC0_SSE1_TRIGGER == ADC_EMUX_PROC) && defined(CONFIG_ARCH_CHIP_TM4C129) */
+#          endif                       /* (CONFIG_TIVA_ADC0_SSE1_TRIGGER ==
+                                        * ADC_EMUX_PROC) && defined
+                                        * (CONFIG_ARCH_CHIP_TM4C129) */
+
+#          ifndef CONFIG_TIVA_ADC0_SSE1_STEP2
+  sse_step_cfg(&adc0, 1, 1, chncfg | ADC_SSCTL_END);
 
-#        ifndef CONFIG_TIVA_ADC0_SSE1_STEP2
-  sse_step_cfg(&adc0, 1, 1, chncfg | ADC_SSCTL_END);    /* Signal as last step in the sequence */
-#        else /* CONFIG_TIVA_ADC0_SSE1_STEP2 */
+#          else                        /* CONFIG_TIVA_ADC0_SSE1_STEP2 */
   sse_step_cfg(&adc0, 1, 1, chncfg);
-#        endif /* !CONFIG_TIVA_ADC0_SSE1_STEP2 */
+#          endif                       /* !CONFIG_TIVA_ADC0_SSE1_STEP2 */
 
-#        ifdef CONFIG_TIVA_ADC0_SSE1_STEP2
-#          ifdef CONFIG_TIVA_ADC0_SSE1_STEP2_TS
+#          ifdef CONFIG_TIVA_ADC0_SSE1_STEP2
+#            ifdef CONFIG_TIVA_ADC0_SSE1_STEP2_TS
   chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
-#          else /* ADC_SSCTL_IE */
+#            else                      /* ADC_SSCTL_IE */
   chncfg = ADC_SSCTL_IE;
-#          endif /* CONFIG_TIVA_ADC0_SSE1_STEP2_TS */
-
+#            endif                     /* CONFIG_TIVA_ADC0_SSE1_STEP2_TS */
   tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC0_SSE1_STEP2_AIN));
   sse_register_chn(&adc0, 1, 2, CONFIG_TIVA_ADC0_SSE1_STEP2_AIN);
   sse_differential(&adc0, 1, 2, 0);
-#          if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC0_SSE1_TRIGGER == ADC_EMUX_PROC)
+#            if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC0_SSE1_TRIGGER == ADC_EMUX_PROC)
   sse_sample_hold_time(&adc0, 1, 2, ADC_SSTH_SHOLD_16);
-#          endif /* (CONFIG_TIVA_ADC0_SSE1_TRIGGER == ADC_EMUX_PROC) && defined(CONFIG_ARCH_CHIP_TM4C129) */
+#            endif                     /* (CONFIG_TIVA_ADC0_SSE1_TRIGGER ==
+                                        * ADC_EMUX_PROC) && defined
+                                        * (CONFIG_ARCH_CHIP_TM4C129) */
 
-#          ifndef CONFIG_TIVA_ADC0_SSE1_STEP3
-  sse_step_cfg(&adc0, 1, 2, chncfg | ADC_SSCTL_END);    /* Signal as last step in the sequence */
-#          else /* CONFIG_TIVA_ADC0_SSE1_STEP3 */
-  sse_step_cfg(&adc0, 1, 2, chncfg);
-#          endif /* !CONFIG_TIVA_ADC0_SSE1_STEP3 */
+#            ifndef CONFIG_TIVA_ADC0_SSE1_STEP3
+  sse_step_cfg(&adc0, 1, 2, chncfg | ADC_SSCTL_END);
 
-#          ifdef CONFIG_TIVA_ADC0_SSE1_STEP3
-#            ifdef CONFIG_TIVA_ADC0_SSE1_STEP3_TS
+#            else                      /* CONFIG_TIVA_ADC0_SSE1_STEP3 */
+  sse_step_cfg(&adc0, 1, 2, chncfg);
+#            endif                     /* !CONFIG_TIVA_ADC0_SSE1_STEP3 */
+#            ifdef CONFIG_TIVA_ADC0_SSE1_STEP3
+#              ifdef CONFIG_TIVA_ADC0_SSE1_STEP3_TS
   chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
-#            else /* ADC_SSCTL_IE */
+#              else                    /* ADC_SSCTL_IE */
   chncfg = ADC_SSCTL_IE;
-#            endif /* CONFIG_TIVA_ADC0_SSE1_STEP3_TS */
+#              endif                   /* CONFIG_TIVA_ADC0_SSE1_STEP3_TS */
 
   tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC0_SSE1_STEP3_AIN));
   sse_register_chn(&adc0, 1, 3, CONFIG_TIVA_ADC0_SSE1_STEP3_AIN);
   sse_differential(&adc0, 1, 3, 0);
-#            if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC0_SSE1_TRIGGER == ADC_EMUX_PROC)
+#              if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC0_SSE1_TRIGGER == ADC_EMUX_PROC)
   sse_sample_hold_time(&adc0, 1, 3, ADC_SSTH_SHOLD_16);
-#            endif /* (CONFIG_TIVA_ADC0_SSE1_TRIGGER == ADC_EMUX_PROC) && defined(CONFIG_ARCH_CHIP_TM4C129) */
+#              endif                   /* (CONFIG_TIVA_ADC0_SSE1_TRIGGER ==
+                                        * ADC_EMUX_PROC) && defined
+                                        * (CONFIG_ARCH_CHIP_TM4C129) */
 
-  sse_step_cfg(&adc0, 1, 3, chncfg | ADC_SSCTL_END);    /* Signal as last step in the sequence */
-#          endif /* CONFIG_TIVA_ADC0_SSE1_STEP3 */
-#        endif /* CONFIG_TIVA_ADC0_SSE1_STEP2 */
-#      endif /* CONFIG_TIVA_ADC0_SSE1_STEP1 */
-#    endif /* CONFIG_TIVA_ADC0_SSE1_STEP0 */
+  sse_step_cfg(&adc0, 1, 3, chncfg | ADC_SSCTL_END);
+
+#            endif                     /* CONFIG_TIVA_ADC0_SSE1_STEP3 */
+#          endif                       /* CONFIG_TIVA_ADC0_SSE1_STEP2 */
+#        endif                         /* CONFIG_TIVA_ADC0_SSE1_STEP1 */
+#      endif                           /* CONFIG_TIVA_ADC0_SSE1_STEP0 */
 }
-#  endif /* CONFIG_TIVA_ADC0_SSE1 */
+#    endif                             /* CONFIG_TIVA_ADC0_SSE1 */
 
-#  ifdef CONFIG_TIVA_ADC0_SSE2
+#    ifdef CONFIG_TIVA_ADC0_SSE2
 static void adc0_sse2_chn_cfg(void)
 {
   uint32_t chncfg = 0;
-#    ifdef CONFIG_TIVA_ADC0_SSE2_STEP0
-#      ifdef CONFIG_TIVA_ADC0_SSE2_STEP0_TS
+#      ifdef CONFIG_TIVA_ADC0_SSE2_STEP0
+#        ifdef CONFIG_TIVA_ADC0_SSE2_STEP0_TS
   chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
-#      else /* ADC_SSCTL_IE */
+#        else                          /* ADC_SSCTL_IE */
   chncfg = ADC_SSCTL_IE;
-#      endif /* CONFIG_TIVA_ADC0_SSE2_STEP0_TS */
+#        endif                         /* CONFIG_TIVA_ADC0_SSE2_STEP0_TS */
 
   tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC0_SSE2_STEP0_AIN));
   sse_register_chn(&adc0, 2, 0, CONFIG_TIVA_ADC0_SSE2_STEP0_AIN);
   sse_differential(&adc0, 2, 0, 0);
-#      if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC0_SSE2_TRIGGER == ADC_EMUX_PROC)
+#        if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC0_SSE2_TRIGGER == ADC_EMUX_PROC)
   sse_sample_hold_time(&adc0, 2, 0, ADC_SSTH_SHOLD_16);
-#      endif /* (CONFIG_TIVA_ADC0_SSE2_TRIGGER == ADC_EMUX_PROC) && defined(CONFIG_ARCH_CHIP_TM4C129) */
+#        endif                         /* (CONFIG_TIVA_ADC0_SSE2_TRIGGER ==
+                                        * ADC_EMUX_PROC) && defined
+                                        * (CONFIG_ARCH_CHIP_TM4C129) */
+
+#        ifndef CONFIG_TIVA_ADC0_SSE2_STEP1
+  sse_step_cfg(&adc0, 2, 0, chncfg | ADC_SSCTL_END);
 
-#      ifndef CONFIG_TIVA_ADC0_SSE2_STEP1
-  sse_step_cfg(&adc0, 2, 0, chncfg | ADC_SSCTL_END);    /* Signal as last step in the sequence */
-#      else /* CONFIG_TIVA_ADC0_SSE2_STEP1 */
+#        else                          /* CONFIG_TIVA_ADC0_SSE2_STEP1 */
   sse_step_cfg(&adc0, 2, 0, chncfg);
-#      endif /* !CONFIG_TIVA_ADC0_SSE2_STEP1 */
+#        endif                         /* !CONFIG_TIVA_ADC0_SSE2_STEP1 */
 
-#      ifdef CONFIG_TIVA_ADC0_SSE2_STEP1
-#        ifdef CONFIG_TIVA_ADC0_SSE2_STEP1_TS
+#        ifdef CONFIG_TIVA_ADC0_SSE2_STEP1
+#          ifdef CONFIG_TIVA_ADC0_SSE2_STEP1_TS
   chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
-#        else /* ADC_SSCTL_IE */
+#          else                        /* ADC_SSCTL_IE */
   chncfg = ADC_SSCTL_IE;
-#        endif /* CONFIG_TIVA_ADC0_SSE2_STEP1_TS */
+#          endif                       /* CONFIG_TIVA_ADC0_SSE2_STEP1_TS */
 
   tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC0_SSE2_STEP1_AIN));
   sse_register_chn(&adc0, 2, 1, CONFIG_TIVA_ADC0_SSE2_STEP1_AIN);
   sse_differential(&adc0, 2, 1, 0);
-#        if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC0_SSE2_TRIGGER == ADC_EMUX_PROC)
+#          if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC0_SSE2_TRIGGER == ADC_EMUX_PROC)
   sse_sample_hold_time(&adc0, 2, 1, ADC_SSTH_SHOLD_16);
-#        endif /* (CONFIG_TIVA_ADC0_SSE2_TRIGGER == ADC_EMUX_PROC) && defined(CONFIG_ARCH_CHIP_TM4C129) */
+#          endif                       /* (CONFIG_TIVA_ADC0_SSE2_TRIGGER ==
+                                        * ADC_EMUX_PROC) && defined
+                                        * (CONFIG_ARCH_CHIP_TM4C129) */
 
-#        ifndef CONFIG_TIVA_ADC0_SSE2_STEP2
-  sse_step_cfg(&adc0, 2, 1, chncfg | ADC_SSCTL_END);    /* Signal as last step in the sequence */
-#        else /* CONFIG_TIVA_ADC0_SSE2_STEP2 */
+#          ifndef CONFIG_TIVA_ADC0_SSE2_STEP2
+  sse_step_cfg(&adc0, 2, 1, chncfg | ADC_SSCTL_END);
+
+#          else                        /* CONFIG_TIVA_ADC0_SSE2_STEP2 */
   sse_step_cfg(&adc0, 2, 1, chncfg);
-#        endif /* !CONFIG_TIVA_ADC0_SSE2_STEP2 */
+#          endif                       /* !CONFIG_TIVA_ADC0_SSE2_STEP2 */
 
-#        ifdef CONFIG_TIVA_ADC0_SSE2_STEP2
-#          ifdef CONFIG_TIVA_ADC0_SSE2_STEP2_TS
+#          ifdef CONFIG_TIVA_ADC0_SSE2_STEP2
+#            ifdef CONFIG_TIVA_ADC0_SSE2_STEP2_TS
   chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
-#          else /* ADC_SSCTL_IE */
+#            else                      /* ADC_SSCTL_IE */
   chncfg = ADC_SSCTL_IE;
-#          endif /* CONFIG_TIVA_ADC0_SSE2_STEP2_TS */
+#            endif                     /* CONFIG_TIVA_ADC0_SSE2_STEP2_TS */
 
   tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC0_SSE2_STEP2_AIN));
   sse_register_chn(&adc0, 2, 2, CONFIG_TIVA_ADC0_SSE2_STEP2_AIN);
   sse_differential(&adc0, 2, 2, 0);
-#          if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC0_SSE2_TRIGGER == ADC_EMUX_PROC)
+#            if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC0_SSE2_TRIGGER == ADC_EMUX_PROC)
   sse_sample_hold_time(&adc0, 2, 2, ADC_SSTH_SHOLD_16);
-#          endif /* (CONFIG_TIVA_ADC0_SSE2_TRIGGER == ADC_EMUX_PROC) && defined(CONFIG_ARCH_CHIP_TM4C129) */
+#            endif                     /* (CONFIG_TIVA_ADC0_SSE2_TRIGGER ==
+                                        * ADC_EMUX_PROC) && defined
+                                        * (CONFIG_ARCH_CHIP_TM4C129) */
+
+#            ifndef CONFIG_TIVA_ADC0_SSE2_STEP3
+  sse_step_cfg(&adc0, 2, 2, chncfg | ADC_SSCTL_END);
 
-#          ifndef CONFIG_TIVA_ADC0_SSE2_STEP3
-  sse_step_cfg(&adc0, 2, 2, chncfg | ADC_SSCTL_END);    /* Signal as last step in the sequence */
-#          else /* CONFIG_TIVA_ADC0_SSE2_STEP3 */
+#            else                      /* CONFIG_TIVA_ADC0_SSE2_STEP3 */
   sse_step_cfg(&adc0, 2, 2, chncfg);
-#          endif /* !CONFIG_TIVA_ADC0_SSE2_STEP3 */
+#            endif                     /* !CONFIG_TIVA_ADC0_SSE2_STEP3 */
 
-#          ifdef CONFIG_TIVA_ADC0_SSE2_STEP3
-#            ifdef CONFIG_TIVA_ADC0_SSE2_STEP3_TS
+#            ifdef CONFIG_TIVA_ADC0_SSE2_STEP3
+#              ifdef CONFIG_TIVA_ADC0_SSE2_STEP3_TS
   chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
-#            else /* ADC_SSCTL_IE */
+#              else                    /* ADC_SSCTL_IE */
   chncfg = ADC_SSCTL_IE;
-#            endif /* CONFIG_TIVA_ADC0_SSE2_STEP3_TS */
+#              endif                   /* CONFIG_TIVA_ADC0_SSE2_STEP3_TS */
 
   tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC0_SSE2_STEP3_AIN));
   sse_register_chn(&adc0, 2, 3, CONFIG_TIVA_ADC0_SSE2_STEP3_AIN);
   sse_differential(&adc0, 2, 3, 0);
-#            if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC0_SSE2_TRIGGER == ADC_EMUX_PROC)
+#              if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC0_SSE2_TRIGGER == ADC_EMUX_PROC)
   sse_sample_hold_time(&adc0, 2, 3, ADC_SSTH_SHOLD_16);
-#            endif /* (CONFIG_TIVA_ADC0_SSE2_TRIGGER == ADC_EMUX_PROC) && defined(CONFIG_ARCH_CHIP_TM4C129) */
+#              endif                   /* (CONFIG_TIVA_ADC0_SSE2_TRIGGER ==
+                                        * ADC_EMUX_PROC) && defined
+                                        * (CONFIG_ARCH_CHIP_TM4C129) */
 
-  sse_step_cfg(&adc0, 2, 3, chncfg | ADC_SSCTL_END);    /* Signal as last step in the sequence */
-#          endif /* CONFIG_TIVA_ADC0_SSE2_STEP3 */
-#        endif /* CONFIG_TIVA_ADC0_SSE2_STEP2 */
-#      endif /* CONFIG_TIVA_ADC0_SSE2_STEP1 */
-#    endif /* CONFIG_TIVA_ADC0_SSE2_STEP0 */
+  sse_step_cfg(&adc0, 2, 3, chncfg | ADC_SSCTL_END);
+
+#            endif                     /* CONFIG_TIVA_ADC0_SSE2_STEP3 */
+#          endif                       /* CONFIG_TIVA_ADC0_SSE2_STEP2 */
+#        endif                         /* CONFIG_TIVA_ADC0_SSE2_STEP1 */
+#      endif                           /* CONFIG_TIVA_ADC0_SSE2_STEP0 */
 }
-#  endif /* CONFIG_TIVA_ADC0_SSE2 */
+#    endif                             /* CONFIG_TIVA_ADC0_SSE2 */
 
-#  ifdef CONFIG_TIVA_ADC0_SSE3
+#    ifdef CONFIG_TIVA_ADC0_SSE3
 static void adc0_sse3_chn_cfg(void)
 {
   uint32_t chncfg = 0;
-#    ifdef CONFIG_TIVA_ADC0_SSE3_STEP0
-#      ifdef CONFIG_TIVA_ADC0_SSE3_STEP0_TS
+#      ifdef CONFIG_TIVA_ADC0_SSE3_STEP0
+#        ifdef CONFIG_TIVA_ADC0_SSE3_STEP0_TS
   chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
-#      else /* ADC_SSCTL_IE */
+#        else                          /* ADC_SSCTL_IE */
   chncfg = ADC_SSCTL_IE;
-#      endif /* CONFIG_TIVA_ADC0_SSE3_STEP0_TS */
+#        endif                         /* CONFIG_TIVA_ADC0_SSE3_STEP0_TS */
 
   tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC0_SSE3_STEP0_AIN));
   sse_register_chn(&adc0, 3, 0, CONFIG_TIVA_ADC0_SSE3_STEP0_AIN);
   sse_differential(&adc0, 3, 0, 0);
-#      if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC0_SSE3_TRIGGER == ADC_EMUX_PROC)
+#        if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC0_SSE3_TRIGGER == ADC_EMUX_PROC)
   sse_sample_hold_time(&adc0, 3, 0, ADC_SSTH_SHOLD_16);
-#      endif /* (CONFIG_TIVA_ADC0_SSE3_TRIGGER == ADC_EMUX_PROC) && defined (CONFIG_ARCH_CHIP_TM4C129) */
+#        endif                         /* (CONFIG_TIVA_ADC0_SSE3_TRIGGER ==
+                                        * ADC_EMUX_PROC) && defined
+                                        * (CONFIG_ARCH_CHIP_TM4C129) */
+
+  sse_step_cfg(&adc0, 3, 0, chncfg | ADC_SSCTL_END);
 
-  sse_step_cfg(&adc0, 3, 0, chncfg | ADC_SSCTL_END);    /* Signal as last step in the sequence */
-#    endif /* CONFIG_TIVA_ADC0_SSE3_STEP0 */
+#      endif                           /* CONFIG_TIVA_ADC0_SSE3_STEP0 */
 }
-#  endif /* CONFIG_TIVA_ADC0_SSE3 */
+#    endif                             /* CONFIG_TIVA_ADC0_SSE3 */
 
-#endif /* CONFIG_TIVA_ADC0 */
+#  endif                               /* CONFIG_TIVA_ADC0 */
 
-#ifdef CONFIG_TIVA_ADC1
-#  ifdef CONFIG_TIVA_ADC1_SSE0
+#  ifdef CONFIG_TIVA_ADC1
+#    ifdef CONFIG_TIVA_ADC1_SSE0
 static void adc1_sse0_chn_cfg(void)
 {
   uint32_t chncfg = 0;
-#    ifdef CONFIG_TIVA_ADC1_SSE0_STEP0
-#      ifdef CONFIG_TIVA_ADC1_SSE0_STEP0_TS
+#      ifdef CONFIG_TIVA_ADC1_SSE0_STEP0
+#        ifdef CONFIG_TIVA_ADC1_SSE0_STEP0_TS
   chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
-#      else /* ADC_SSCTL_IE */
+#        else                          /* ADC_SSCTL_IE */
   chncfg = ADC_SSCTL_IE;
-#      endif /* CONFIG_TIVA_ADC1_SSE0_STEP0_TS */
+#        endif                         /* CONFIG_TIVA_ADC1_SSE0_STEP0_TS */
 
   tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC1_SSE0_STEP0_AIN));
   sse_register_chn(&adc1, 0, 0, CONFIG_TIVA_ADC1_SSE0_STEP0_AIN);
   sse_differential(&adc1, 0, 0, 0);
-#      if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC1_SSE0_TRIGGER == ADC_EMUX_PROC)
+#        if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC1_SSE0_TRIGGER == ADC_EMUX_PROC)
   sse_sample_hold_time(&adc1, 0, 0, ADC_SSTH_SHOLD_16);
-#      endif /* (CONFIG_TIVA_ADC1_SSE0_TRIGGER == ADC_EMUX_PROC) && defined(CONFIG_ARCH_CHIP_TM4C129) */
+#        endif                         /* (CONFIG_TIVA_ADC1_SSE0_TRIGGER ==
+                                        * ADC_EMUX_PROC) && defined
+                                        * (CONFIG_ARCH_CHIP_TM4C129) */
 
-#      ifndef CONFIG_TIVA_ADC1_SSE0_STEP1
-  sse_step_cfg(&adc1, 0, 0, chncfg | ADC_SSCTL_END);    /* Signal as last step in the sequence */
-#      else /* CONFIG_TIVA_ADC1_SSE0_STEP1 */
+#        ifndef CONFIG_TIVA_ADC1_SSE0_STEP1
+  sse_step_cfg(&adc1, 0, 0, chncfg | ADC_SSCTL_END);
+
+#        else                          /* CONFIG_TIVA_ADC1_SSE0_STEP1 */
   sse_step_cfg(&adc1, 0, 0, chncfg);
-#      endif /* !CONFIG_TIVA_ADC1_SSE0_STEP1 */
+#        endif                         /* !CONFIG_TIVA_ADC1_SSE0_STEP1 */
 
-#      ifdef CONFIG_TIVA_ADC1_SSE0_STEP1
-#        ifdef CONFIG_TIVA_ADC1_SSE0_STEP1_TS
+#        ifdef CONFIG_TIVA_ADC1_SSE0_STEP1
+#          ifdef CONFIG_TIVA_ADC1_SSE0_STEP1_TS
   chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
-#        else /* ADC_SSCTL_IE */
+#          else                        /* ADC_SSCTL_IE */
   chncfg = ADC_SSCTL_IE;
-#        endif /* CONFIG_TIVA_ADC1_SSE0_STEP1_TS */
+#          endif                       /* CONFIG_TIVA_ADC1_SSE0_STEP1_TS */
 
   tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC1_SSE0_STEP1_AIN));
   sse_register_chn(&adc1, 0, 1, CONFIG_TIVA_ADC1_SSE0_STEP1_AIN);
   sse_differential(&adc1, 0, 1, 0);
-#        if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC1_SSE0_TRIGGER == ADC_EMUX_PROC)
+#          if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC1_SSE0_TRIGGER == ADC_EMUX_PROC)
   sse_sample_hold_time(&adc1, 0, 1, ADC_SSTH_SHOLD_16);
-#        endif /* (CONFIG_TIVA_ADC1_SSE0_TRIGGER == ADC_EMUX_PROC) && defined(CONFIG_ARCH_CHIP_TM4C129) */
+#          endif                       /* (CONFIG_TIVA_ADC1_SSE0_TRIGGER ==
+                                        * ADC_EMUX_PROC) && defined
+                                        * (CONFIG_ARCH_CHIP_TM4C129) */
 
-#        ifndef CONFIG_TIVA_ADC1_SSE0_STEP2
-  sse_step_cfg(&adc1, 0, 1, chncfg | ADC_SSCTL_END);    /* Signal as last step in the sequence */
-#        else /* CONFIG_TIVA_ADC1_SSE0_STEP2 */
+#          ifndef CONFIG_TIVA_ADC1_SSE0_STEP2
+  sse_step_cfg(&adc1, 0, 1, chncfg | ADC_SSCTL_END);
+
+#          else                        /* CONFIG_TIVA_ADC1_SSE0_STEP2 */
   sse_step_cfg(&adc1, 0, 1, chncfg);
-#        endif /* !CONFIG_TIVA_ADC1_SSE0_STEP2 */
+#          endif                       /* !CONFIG_TIVA_ADC1_SSE0_STEP2 */
 
-#        ifdef CONFIG_TIVA_ADC1_SSE0_STEP2
-#          ifdef CONFIG_TIVA_ADC1_SSE0_STEP2_TS
+#          ifdef CONFIG_TIVA_ADC1_SSE0_STEP2
+#            ifdef CONFIG_TIVA_ADC1_SSE0_STEP2_TS
   chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
-#          else /* ADC_SSCTL_IE */
+#            else                      /* ADC_SSCTL_IE */
   chncfg = ADC_SSCTL_IE;
-#          endif /* CONFIG_TIVA_ADC1_SSE0_STEP2_TS */
+#            endif                     /* CONFIG_TIVA_ADC1_SSE0_STEP2_TS */
 
   tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC1_SSE0_STEP2_AIN));
   sse_register_chn(&adc1, 0, 2, CONFIG_TIVA_ADC1_SSE0_STEP2_AIN);
   sse_differential(&adc1, 0, 2, 0);
-#          if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC1_SSE0_TRIGGER == ADC_EMUX_PROC)
+#            if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC1_SSE0_TRIGGER == ADC_EMUX_PROC)
   sse_sample_hold_time(&adc1, 0, 2, ADC_SSTH_SHOLD_16);
-#          endif /* (CONFIG_TIVA_ADC1_SSE0_TRIGGER == ADC_EMUX_PROC) && defined(CONFIG_ARCH_CHIP_TM4C129) */
+#            endif                     /* (CONFIG_TIVA_ADC1_SSE0_TRIGGER ==
+                                        * ADC_EMUX_PROC) && defined
+                                        * (CONFIG_ARCH_CHIP_TM4C129) */
+
+#            ifndef CONFIG_TIVA_ADC1_SSE0_STEP3
+  sse_step_cfg(&adc1, 0, 2, chncfg | ADC_SSCTL_END);
 
-#          ifndef CONFIG_TIVA_ADC1_SSE0_STEP3
-  sse_step_cfg(&adc1, 0, 2, chncfg | ADC_SSCTL_END);    /* Signal as last step in the sequence */
-#          else /* CONFIG_TIVA_ADC1_SSE0_STEP3 */
+#            else                      /* CONFIG_TIVA_ADC1_SSE0_STEP3 */
   sse_step_cfg(&adc1, 0, 2, chncfg);
-#          endif /* !CONFIG_TIVA_ADC1_SSE0_STEP3 */
+#            endif                     /* !CONFIG_TIVA_ADC1_SSE0_STEP3 */
 
-#          ifdef CONFIG_TIVA_ADC1_SSE0_STEP3
-#            ifdef CONFIG_TIVA_ADC1_SSE0_STEP3_TS
+#            ifdef CONFIG_TIVA_ADC1_SSE0_STEP3
+#              ifdef CONFIG_TIVA_ADC1_SSE0_STEP3_TS
   chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
-#            else /* ADC_SSCTL_IE */
+#              else                    /* ADC_SSCTL_IE */
   chncfg = ADC_SSCTL_IE;
-#            endif /* CONFIG_TIVA_ADC1_SSE0_STEP3_TS */
+#              endif                   /* CONFIG_TIVA_ADC1_SSE0_STEP3_TS */
 
   tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC1_SSE0_STEP3_AIN));
   sse_register_chn(&adc1, 0, 3, CONFIG_TIVA_ADC1_SSE0_STEP3_AIN);
   sse_differential(&adc1, 0, 3, 0);
-#            if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC1_SSE0_TRIGGER == ADC_EMUX_PROC)
+#              if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC1_SSE0_TRIGGER == ADC_EMUX_PROC)
   sse_sample_hold_time(&adc1, 0, 3, ADC_SSTH_SHOLD_16);
-#            endif /* (CONFIG_TIVA_ADC1_SSE0_TRIGGER == ADC_EMUX_PROC) && defined(CONFIG_ARCH_CHIP_TM4C129) */
+#              endif                   /* (CONFIG_TIVA_ADC1_SSE0_TRIGGER ==
+                                        * ADC_EMUX_PROC) && defined
+                                        * (CONFIG_ARCH_CHIP_TM4C129) */
+
+#              ifndef CONFIG_TIVA_ADC1_SSE0_STEP4
+  sse_step_cfg(&adc1, 0, 3, chncfg | ADC_SSCTL_END);
 
-#            ifndef CONFIG_TIVA_ADC1_SSE0_STEP4
-  sse_step_cfg(&adc1, 0, 3, chncfg | ADC_SSCTL_END);    /* Signal as last step in the sequence */
-#            else /* CONFIG_TIVA_ADC1_SSE0_STEP4 */
+#              else                    /* CONFIG_TIVA_ADC1_SSE0_STEP4 */
   sse_step_cfg(&adc1, 0, 3, chncfg);
-#            endif /* !CONFIG_TIVA_ADC1_SSE0_STEP4 */
+#              endif                   /* !CONFIG_TIVA_ADC1_SSE0_STEP4 */
 
-#            ifdef CONFIG_TIVA_ADC1_SSE0_STEP4
-#              ifdef CONFIG_TIVA_ADC1_SSE0_STEP4_TS
+#              ifdef CONFIG_TIVA_ADC1_SSE0_STEP4
+#                ifdef CONFIG_TIVA_ADC1_SSE0_STEP4_TS
   chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
-#              else /* ADC_SSCTL_IE */
+#                else                  /* ADC_SSCTL_IE */
   chncfg = ADC_SSCTL_IE;
-#              endif /* CONFIG_TIVA_ADC1_SSE0_STEP4_TS */
+#                endif                 /* CONFIG_TIVA_ADC1_SSE0_STEP4_TS */
 
   tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC1_SSE0_STEP4_AIN));
   sse_register_chn(&adc1, 0, 4, CONFIG_TIVA_ADC1_SSE0_STEP4_AIN);
   sse_differential(&adc1, 0, 4, 0);
-#              if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC1_SSE0_TRIGGER == ADC_EMUX_PROC)
+#                if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC1_SSE0_TRIGGER == ADC_EMUX_PROC)
   sse_sample_hold_time(&adc1, 0, 4, ADC_SSTH_SHOLD_16);
-#              endif /* (CONFIG_TIVA_ADC1_SSE0_TRIGGER == ADC_EMUX_PROC) && defined(CONFIG_ARCH_CHIP_TM4C129) */
+#                endif                 /* (CONFIG_TIVA_ADC1_SSE0_TRIGGER ==
+                                        * ADC_EMUX_PROC) && defined
+                                        * (CONFIG_ARCH_CHIP_TM4C129) */
+
+#                ifndef CONFIG_TIVA_ADC1_SSE0_STEP5
+  sse_step_cfg(&adc1, 0, 4, chncfg | ADC_SSCTL_END);
 
-#              ifndef CONFIG_TIVA_ADC1_SSE0_STEP5
-  sse_step_cfg(&adc1, 0, 4, chncfg | ADC_SSCTL_END);    /* Signal as last step in the sequence */
-#              else /* CONFIG_TIVA_ADC1_SSE0_STEP5 */
+#                else                  /* CONFIG_TIVA_ADC1_SSE0_STEP5 */
   sse_step_cfg(&adc1, 0, 4, chncfg);
-#              endif /* !CONFIG_TIVA_ADC1_SSE0_STEP5 */
+#                endif                 /* !CONFIG_TIVA_ADC1_SSE0_STEP5 */
 
-#              ifdef CONFIG_TIVA_ADC1_SSE0_STEP5
-#                ifdef CONFIG_TIVA_ADC1_SSE0_STEP5_TS
+#                ifdef CONFIG_TIVA_ADC1_SSE0_STEP5
+#                  ifdef CONFIG_TIVA_ADC1_SSE0_STEP5_TS
   chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
-#                else /* ADC_SSCTL_IE */
+#                  else                /* ADC_SSCTL_IE */
   chncfg = ADC_SSCTL_IE;
-#                endif /* CONFIG_TIVA_ADC1_SSE0_STEP5_TS */
+#                  endif               /* CONFIG_TIVA_ADC1_SSE0_STEP5_TS */
 
   tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC1_SSE0_STEP5_AIN));
   sse_register_chn(&adc1, 0, 5, CONFIG_TIVA_ADC1_SSE0_STEP5_AIN);
   sse_differential(&adc1, 0, 5, 0);
-#                if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC1_SSE0_TRIGGER == ADC_EMUX_PROC)
+#                  if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC1_SSE0_TRIGGER == ADC_EMUX_PROC)
   sse_sample_hold_time(&adc1, 0, 5, ADC_SSTH_SHOLD_16);
-#                endif /* (CONFIG_TIVA_ADC1_SSE0_TRIGGER == ADC_EMUX_PROC) && defined(CONFIG_ARCH_CHIP_TM4C129) */
+#                  endif               /* (CONFIG_TIVA_ADC1_SSE0_TRIGGER ==
+                                        * ADC_EMUX_PROC) && defined
+                                        * (CONFIG_ARCH_CHIP_TM4C129) */
+
+#                  ifndef CONFIG_TIVA_ADC1_SSE0_STEP6
+  sse_step_cfg(&adc1, 0, 5, chncfg | ADC_SSCTL_END);
 
-#                ifndef CONFIG_TIVA_ADC1_SSE0_STEP6
-  sse_step_cfg(&adc1, 0, 5, chncfg | ADC_SSCTL_END);    /* Signal as last step in the sequence */
-#                else /* CONFIG_TIVA_ADC1_SSE0_STEP6 */
+#                  else                /* CONFIG_TIVA_ADC1_SSE0_STEP6 */
   sse_step_cfg(&adc1, 0, 5, chncfg);
-#                endif /* !CONFIG_TIVA_ADC1_SSE0_STEP6 */
+#                  endif               /* !CONFIG_TIVA_ADC1_SSE0_STEP6 */
 
-#                ifdef CONFIG_TIVA_ADC1_SSE0_STEP6
-#                  ifdef CONFIG_TIVA_ADC1_SSE0_STEP6_TS
+#                  ifdef CONFIG_TIVA_ADC1_SSE0_STEP6
+#                    ifdef CONFIG_TIVA_ADC1_SSE0_STEP6_TS
   chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
-#                  else /* ADC_SSCTL_IE */
+#                    else              /* ADC_SSCTL_IE */
   chncfg = ADC_SSCTL_IE;
-#                  endif /* CONFIG_TIVA_ADC1_SSE0_STEP6_TS */
+#                    endif             /* CONFIG_TIVA_ADC1_SSE0_STEP6_TS */
 
   tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC1_SSE0_STEP6_AIN));
   sse_register_chn(&adc1, 0, 6, CONFIG_TIVA_ADC1_SSE0_STEP6_AIN);
   sse_differential(&adc1, 0, 6, 0);
-#                  if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC1_SSE0_TRIGGER == ADC_EMUX_PROC)
+#                    if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC1_SSE0_TRIGGER == ADC_EMUX_PROC)
   sse_sample_hold_time(&adc1, 0, 6, ADC_SSTH_SHOLD_16);
-#                  endif /* (CONFIG_TIVA_ADC1_SSE0_TRIGGER == ADC_EMUX_PROC) && defined(CONFIG_ARCH_CHIP_TM4C129) */
+#                    endif             /* (CONFIG_TIVA_ADC1_SSE0_TRIGGER ==
+                                        * ADC_EMUX_PROC) && defined
+                                        * (CONFIG_ARCH_CHIP_TM4C129) */
 
-#                  ifndef CONFIG_TIVA_ADC1_SSE0_STEP7
-  sse_step_cfg(&adc1, 0, 6, chncfg | ADC_SSCTL_END);    /* Signal as last step in the sequence */
-#                  else /* CONFIG_TIVA_ADC1_SSE0_STEP7 */
+#                    ifndef CONFIG_TIVA_ADC1_SSE0_STEP7
+  sse_step_cfg(&adc1, 0, 6, chncfg | ADC_SSCTL_END);
+
+#                    else              /* CONFIG_TIVA_ADC1_SSE0_STEP7 */
   sse_step_cfg(&adc1, 0, 6, chncfg);
-#                  endif /* !CONFIG_TIVA_ADC1_SSE0_STEP7 */
+#                    endif             /* !CONFIG_TIVA_ADC1_SSE0_STEP7 */
 
-#                  ifdef CONFIG_TIVA_ADC1_SSE0_STEP7
-#                    ifdef CONFIG_TIVA_ADC1_SSE0_STEP7_TS
+#                    ifdef CONFIG_TIVA_ADC1_SSE0_STEP7
+#                      ifdef CONFIG_TIVA_ADC1_SSE0_STEP7_TS
   chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
-#                    else /* ADC_SSCTL_IE */
+#                      else            /* ADC_SSCTL_IE */
   chncfg = ADC_SSCTL_IE;
-#                    endif /* CONFIG_TIVA_ADC1_SSE0_STEP7_TS */
+#                      endif           /* CONFIG_TIVA_ADC1_SSE0_STEP7_TS */
 
   tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC1_SSE0_STEP7_AIN));
   sse_register_chn(&adc1, 0, 7, CONFIG_TIVA_ADC1_SSE0_STEP7_AIN);
   sse_differential(&adc1, 0, 7, 0);
-#                    if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC1_SSE0_TRIGGER == ADC_EMUX_PROC)
+#                      if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC1_SSE0_TRIGGER == ADC_EMUX_PROC)
   sse_sample_hold_time(&adc1, 0, 7, ADC_SSTH_SHOLD_16);
-#                    endif /* (CONFIG_TIVA_ADC1_SSE0_TRIGGER == ADC_EMUX_PROC) && defined(CONFIG_ARCH_CHIP_TM4C129) */
-
-  sse_step_cfg(&adc1, 0, 7, chncfg | ADC_SSCTL_END);    /* Signal as last step in the sequence */
-#                  endif /* CONFIG_TIVA_ADC1_SSE0_STEP7 */
-#                endif /* CONFIG_TIVA_ADC1_SSE0_STEP6 */
-#              endif /* CONFIG_TIVA_ADC1_SSE0_STEP5 */
-#            endif /* CONFIG_TIVA_ADC1_SSE0_STEP4 */
-#          endif /* CONFIG_TIVA_ADC1_SSE0_STEP3 */
-#        endif /* CONFIG_TIVA_ADC1_SSE0_STEP2 */
-#      endif /* CONFIG_TIVA_ADC1_SSE0_STEP1 */
-#    endif /* CONFIG_TIVA_ADC1_SSE0_STEP0 */
+#                      endif           /* (CONFIG_TIVA_ADC1_SSE0_TRIGGER ==
+                                        * ADC_EMUX_PROC) && defined
+                                        * (CONFIG_ARCH_CHIP_TM4C129) */
+
+  sse_step_cfg(&adc1, 0, 7, chncfg | ADC_SSCTL_END);
+
+#                    endif             /* CONFIG_TIVA_ADC1_SSE0_STEP7 */
+#                  endif               /* CONFIG_TIVA_ADC1_SSE0_STEP6 */
+#                endif                 /* CONFIG_TIVA_ADC1_SSE0_STEP5 */
+#              endif                   /* CONFIG_TIVA_ADC1_SSE0_STEP4 */
+#            endif                     /* CONFIG_TIVA_ADC1_SSE0_STEP3 */
+#          endif                       /* CONFIG_TIVA_ADC1_SSE0_STEP2 */
+#        endif                         /* CONFIG_TIVA_ADC1_SSE0_STEP1 */
+#      endif                           /* CONFIG_TIVA_ADC1_SSE0_STEP0 */
 }
-#  endif /* CONFIG_TIVA_ADC1_SSE0 */
+#    endif                             /* CONFIG_TIVA_ADC1_SSE0 */
 
-#  ifdef CONFIG_TIVA_ADC1_SSE1
+#    ifdef CONFIG_TIVA_ADC1_SSE1
 static void adc1_sse1_chn_cfg(void)
 {
   uint32_t chncfg = 0;
-#    ifdef CONFIG_TIVA_ADC1_SSE1_STEP0
-#      ifdef CONFIG_TIVA_ADC1_SSE1_STEP0_TS
+#      ifdef CONFIG_TIVA_ADC1_SSE1_STEP0
+#        ifdef CONFIG_TIVA_ADC1_SSE1_STEP0_TS
   chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
-#      else /* ADC_SSCTL_IE */
+#        else                          /* ADC_SSCTL_IE */
   chncfg = ADC_SSCTL_IE;
-#      endif /* CONFIG_TIVA_ADC1_SSE1_STEP0_TS */
+#        endif                         /* CONFIG_TIVA_ADC1_SSE1_STEP0_TS */
 
   tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC1_SSE1_STEP0_AIN));
   sse_register_chn(&adc1, 1, 0, CONFIG_TIVA_ADC1_SSE1_STEP0_AIN);
   sse_differential(&adc1, 1, 0, 0);
-#      if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC1_SSE1_TRIGGER == ADC_EMUX_PROC)
+#        if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC1_SSE1_TRIGGER == ADC_EMUX_PROC)
   sse_sample_hold_time(&adc1, 1, 0, ADC_SSTH_SHOLD_16);
-#      endif /* (CONFIG_TIVA_ADC1_SSE1_TRIGGER == ADC_EMUX_PROC) && defined(CONFIG_ARCH_CHIP_TM4C129) */
+#        endif                         /* (CONFIG_TIVA_ADC1_SSE1_TRIGGER ==
+                                        * ADC_EMUX_PROC) && defined
+                                        * (CONFIG_ARCH_CHIP_TM4C129) */
+
+#        ifndef CONFIG_TIVA_ADC1_SSE1_STEP1
+  sse_step_cfg(&adc1, 1, 0, chncfg | ADC_SSCTL_END);
 
-#      ifndef CONFIG_TIVA_ADC1_SSE1_STEP1
-  sse_step_cfg(&adc1, 1, 0, chncfg | ADC_SSCTL_END);    /* Signal as last step in the sequence */
-#      else /* CONFIG_TIVA_ADC1_SSE1_STEP1 */
+#        else                          /* CONFIG_TIVA_ADC1_SSE1_STEP1 */
   sse_step_cfg(&adc1, 1, 0, chncfg);
-#      endif /* !CONFIG_TIVA_ADC1_SSE1_STEP1 */
+#        endif                         /* !CONFIG_TIVA_ADC1_SSE1_STEP1 */
 
-#      ifdef CONFIG_TIVA_ADC1_SSE1_STEP1
-#        ifdef CONFIG_TIVA_ADC1_SSE1_STEP1_TS
+#        ifdef CONFIG_TIVA_ADC1_SSE1_STEP1
+#          ifdef CONFIG_TIVA_ADC1_SSE1_STEP1_TS
   chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
-#        else /* ADC_SSCTL_IE */
+#          else                        /* ADC_SSCTL_IE */
   chncfg = ADC_SSCTL_IE;
-#        endif /* CONFIG_TIVA_ADC1_SSE1_STEP1_TS */
+#          endif                       /* CONFIG_TIVA_ADC1_SSE1_STEP1_TS */
 
   tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC1_SSE1_STEP1_AIN));
   sse_register_chn(&adc1, 1, 1, CONFIG_TIVA_ADC1_SSE1_STEP1_AIN);
   sse_differential(&adc1, 1, 1, 0);
-#        if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC1_SSE1_TRIGGER == ADC_EMUX_PROC)
+#          if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC1_SSE1_TRIGGER == ADC_EMUX_PROC)
   sse_sample_hold_time(&adc1, 1, 1, ADC_SSTH_SHOLD_16);
-#        endif /* (CONFIG_TIVA_ADC1_SSE1_TRIGGER == ADC_EMUX_PROC) && defined(CONFIG_ARCH_CHIP_TM4C129) */
+#          endif                       /* (CONFIG_TIVA_ADC1_SSE1_TRIGGER ==
+                                        * ADC_EMUX_PROC) && defined
+                                        * (CONFIG_ARCH_CHIP_TM4C129) */
+
+#          ifndef CONFIG_TIVA_ADC1_SSE1_STEP2
+  sse_step_cfg(&adc1, 1, 1, chncfg | ADC_SSCTL_END);
 
-#        ifndef CONFIG_TIVA_ADC1_SSE1_STEP2
-  sse_step_cfg(&adc1, 1, 1, chncfg | ADC_SSCTL_END);    /* Signal as last step in the sequence */
-#        else /* CONFIG_TIVA_ADC1_SSE1_STEP2 */
+#          else                        /* CONFIG_TIVA_ADC1_SSE1_STEP2 */
   sse_step_cfg(&adc1, 1, 1, chncfg);
-#        endif /* !CONFIG_TIVA_ADC1_SSE1_STEP2 */
+#          endif                       /* !CONFIG_TIVA_ADC1_SSE1_STEP2 */
 
-#        ifdef CONFIG_TIVA_ADC1_SSE1_STEP2
-#          ifdef CONFIG_TIVA_ADC1_SSE1_STEP2_TS
+#          ifdef CONFIG_TIVA_ADC1_SSE1_STEP2
+#            ifdef CONFIG_TIVA_ADC1_SSE1_STEP2_TS
   chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
-#          else /* ADC_SSCTL_IE */
+#            else                      /* ADC_SSCTL_IE */
   chncfg = ADC_SSCTL_IE;
-#          endif /* CONFIG_TIVA_ADC1_SSE1_STEP2_TS */
+#            endif                     /* CONFIG_TIVA_ADC1_SSE1_STEP2_TS */
 
   tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC1_SSE1_STEP2_AIN));
   sse_register_chn(&adc1, 1, 2, CONFIG_TIVA_ADC1_SSE1_STEP2_AIN);
   sse_differential(&adc1, 1, 2, 0);
-#          if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC1_SSE1_TRIGGER == ADC_EMUX_PROC)
+#            if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC1_SSE1_TRIGGER == ADC_EMUX_PROC)
   sse_sample_hold_time(&adc1, 1, 2, ADC_SSTH_SHOLD_16);
-#          endif /* (CONFIG_TIVA_ADC1_SSE1_TRIGGER == ADC_EMUX_PROC) && defined(CONFIG_ARCH_CHIP_TM4C129) */
+#            endif                     /* (CONFIG_TIVA_ADC1_SSE1_TRIGGER ==
+                                        * ADC_EMUX_PROC) && defined
+                                        * (CONFIG_ARCH_CHIP_TM4C129) */
+
+#            ifndef CONFIG_TIVA_ADC1_SSE1_STEP3
+  sse_step_cfg(&adc1, 1, 2, chncfg | ADC_SSCTL_END);
 
-#          ifndef CONFIG_TIVA_ADC1_SSE1_STEP3
-  sse_step_cfg(&adc1, 1, 2, chncfg | ADC_SSCTL_END);    /* Signal as last step in the sequence */
-#          else /* CONFIG_TIVA_ADC1_SSE1_STEP3 */
+#            else                      /* CONFIG_TIVA_ADC1_SSE1_STEP3 */
   sse_step_cfg(&adc1, 1, 2, chncfg);
-#          endif /* !CONFIG_TIVA_ADC1_SSE1_STEP3 */
+#            endif                     /* !CONFIG_TIVA_ADC1_SSE1_STEP3 */
 
-#          ifdef CONFIG_TIVA_ADC1_SSE1_STEP3
-#            ifdef CONFIG_TIVA_ADC1_SSE1_STEP3_TS
+#            ifdef CONFIG_TIVA_ADC1_SSE1_STEP3
+#              ifdef CONFIG_TIVA_ADC1_SSE1_STEP3_TS
   chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
-#            else /* ADC_SSCTL_IE */
+#              else                    /* ADC_SSCTL_IE */
   chncfg = ADC_SSCTL_IE;
-#            endif /* CONFIG_TIVA_ADC1_SSE1_STEP3_TS */
+#              endif                   /* CONFIG_TIVA_ADC1_SSE1_STEP3_TS */
 
   tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC1_SSE1_STEP3_AIN));
   sse_register_chn(&adc1, 1, 3, CONFIG_TIVA_ADC1_SSE1_STEP3_AIN);
   sse_differential(&adc1, 1, 3, 0);
-#            if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC1_SSE1_TRIGGER == ADC_EMUX_PROC)
+#              if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC1_SSE1_TRIGGER == ADC_EMUX_PROC)
   sse_sample_hold_time(&adc1, 1, 3, ADC_SSTH_SHOLD_16);
-#            endif /* (CONFIG_TIVA_ADC1_SSE1_TRIGGER == ADC_EMUX_PROC) && defined(CONFIG_ARCH_CHIP_TM4C129) */
+#              endif                   /* (CONFIG_TIVA_ADC1_SSE1_TRIGGER ==
+                                        * ADC_EMUX_PROC) && defined
+                                        * (CONFIG_ARCH_CHIP_TM4C129) */
 
-  sse_step_cfg(&adc1, 1, 3, chncfg | ADC_SSCTL_END);    /* Signal as last step in the sequence */
-#          endif /* CONFIG_TIVA_ADC1_SSE1_STEP3 */
-#        endif /* CONFIG_TIVA_ADC1_SSE1_STEP2 */
-#      endif /* CONFIG_TIVA_ADC1_SSE1_STEP1 */
-#    endif /* CONFIG_TIVA_ADC1_SSE1_STEP0 */
+  sse_step_cfg(&adc1, 1, 3, chncfg | ADC_SSCTL_END);
+
+#            endif                     /* CONFIG_TIVA_ADC1_SSE1_STEP3 */
+#          endif                       /* CONFIG_TIVA_ADC1_SSE1_STEP2 */
+#        endif                         /* CONFIG_TIVA_ADC1_SSE1_STEP1 */
+#      endif                           /* CONFIG_TIVA_ADC1_SSE1_STEP0 */
 }
-#  endif /* CONFIG_TIVA_ADC1_SSE1 */
+#    endif                             /* CONFIG_TIVA_ADC1_SSE1 */
 
-#  ifdef CONFIG_TIVA_ADC1_SSE2
+#    ifdef CONFIG_TIVA_ADC1_SSE2
 static void adc1_sse2_chn_cfg(void)
 {
   uint32_t chncfg = 0;
-#    ifdef CONFIG_TIVA_ADC1_SSE2_STEP0
-#      ifdef CONFIG_TIVA_ADC1_SSE2_STEP0_TS
+#      ifdef CONFIG_TIVA_ADC1_SSE2_STEP0
+#        ifdef CONFIG_TIVA_ADC1_SSE2_STEP0_TS
   chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
-#      else /* ADC_SSCTL_IE */
+#        else                          /* ADC_SSCTL_IE */
   chncfg = ADC_SSCTL_IE;
-#      endif /* CONFIG_TIVA_ADC1_SSE2_STEP0_TS */
+#        endif                         /* CONFIG_TIVA_ADC1_SSE2_STEP0_TS */
 
   tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC1_SSE2_STEP0_AIN));
   sse_register_chn(&adc1, 2, 0, CONFIG_TIVA_ADC1_SSE2_STEP0_AIN);
   sse_differential(&adc1, 2, 0, 0);
-#      if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC1_SSE2_TRIGGER == ADC_EMUX_PROC)
+#        if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC1_SSE2_TRIGGER == ADC_EMUX_PROC)
   sse_sample_hold_time(&adc1, 2, 0, ADC_SSTH_SHOLD_16);
-#      endif /* (CONFIG_TIVA_ADC1_SSE2_TRIGGER == ADC_EMUX_PROC) && defined(CONFIG_ARCH_CHIP_TM4C129) */
+#        endif                         /* (CONFIG_TIVA_ADC1_SSE2_TRIGGER ==
+                                        * ADC_EMUX_PROC) && defined
+                                        * (CONFIG_ARCH_CHIP_TM4C129) */
 
-#      ifndef CONFIG_TIVA_ADC1_SSE2_STEP1
-  sse_step_cfg(&adc1, 2, 0, chncfg | ADC_SSCTL_END);    /* Signal as last step in the sequence */
-#      else /* CONFIG_TIVA_ADC1_SSE2_STEP1 */
+#        ifndef CONFIG_TIVA_ADC1_SSE2_STEP1
+  sse_step_cfg(&adc1, 2, 0, chncfg | ADC_SSCTL_END);
+
+#        else                          /* CONFIG_TIVA_ADC1_SSE2_STEP1 */
   sse_step_cfg(&adc1, 2, 0, chncfg);
-#      endif /* !CONFIG_TIVA_ADC1_SSE2_STEP1 */
+#        endif                         /* !CONFIG_TIVA_ADC1_SSE2_STEP1 */
 
-#      ifdef CONFIG_TIVA_ADC1_SSE2_STEP1
-#        ifdef CONFIG_TIVA_ADC1_SSE2_STEP1_TS
+#        ifdef CONFIG_TIVA_ADC1_SSE2_STEP1
+#          ifdef CONFIG_TIVA_ADC1_SSE2_STEP1_TS
   chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
-#        else /* ADC_SSCTL_IE */
+#          else                        /* ADC_SSCTL_IE */
   chncfg = ADC_SSCTL_IE;
-#        endif /* CONFIG_TIVA_ADC1_SSE2_STEP1_TS */
+#          endif                       /* CONFIG_TIVA_ADC1_SSE2_STEP1_TS */
 
   tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC1_SSE2_STEP1_AIN));
   sse_register_chn(&adc1, 2, 1, CONFIG_TIVA_ADC1_SSE2_STEP1_AIN);
   sse_differential(&adc1, 2, 1, 0);
-#        if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC1_SSE2_TRIGGER == ADC_EMUX_PROC)
+#          if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC1_SSE2_TRIGGER == ADC_EMUX_PROC)
   sse_sample_hold_time(&adc1, 2, 1, ADC_SSTH_SHOLD_16);
-#        endif /* (CONFIG_TIVA_ADC1_SSE2_TRIGGER == ADC_EMUX_PROC) && defined(CONFIG_ARCH_CHIP_TM4C129) */
+#          endif                       /* (CONFIG_TIVA_ADC1_SSE2_TRIGGER ==
+                                        * ADC_EMUX_PROC) && defined
+                                        * (CONFIG_ARCH_CHIP_TM4C129) */
+
+#          ifndef CONFIG_TIVA_ADC1_SSE2_STEP2
+  sse_step_cfg(&adc1, 2, 1, chncfg | ADC_SSCTL_END);
 
-#        ifndef CONFIG_TIVA_ADC1_SSE2_STEP2
-  sse_step_cfg(&adc1, 2, 1, chncfg | ADC_SSCTL_END);    /* Signal as last step in the sequence */
-#        else /* CONFIG_TIVA_ADC1_SSE2_STEP2 */
+#          else                        /* CONFIG_TIVA_ADC1_SSE2_STEP2 */
   sse_step_cfg(&adc1, 2, 1, chncfg);
-#        endif /* !CONFIG_TIVA_ADC1_SSE2_STEP2 *
+#          endif                       /* !CONFIG_TIVA_ADC1_SSE2_STEP2 */
 
-#        ifdef CONFIG_TIVA_ADC1_SSE2_STEP2
-#          ifdef CONFIG_TIVA_ADC1_SSE2_STEP2_TS
+#          ifdef CONFIG_TIVA_ADC1_SSE2_STEP2
+#            ifdef CONFIG_TIVA_ADC1_SSE2_STEP2_TS
   chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
-#          else /* ADC_SSCTL_IE */
+#            else                      /* ADC_SSCTL_IE */
   chncfg = ADC_SSCTL_IE;
-#          endif /* CONFIG_TIVA_ADC1_SSE2_STEP2_TS */
+#            endif                     /* CONFIG_TIVA_ADC1_SSE2_STEP2_TS */
 
   tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC1_SSE2_STEP2_AIN));
   sse_register_chn(&adc1, 2, 2, CONFIG_TIVA_ADC1_SSE2_STEP2_AIN);
   sse_differential(&adc1, 2, 2, 0);
-#          if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC1_SSE2_TRIGGER == ADC_EMUX_PROC)
+#            if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC1_SSE2_TRIGGER == ADC_EMUX_PROC)
   sse_sample_hold_time(&adc1, 2, 2, ADC_SSTH_SHOLD_16);
-#          endif /* (CONFIG_TIVA_ADC1_SSE2_TRIGGER == ADC_EMUX_PROC) && defined(CONFIG_ARCH_CHIP_TM4C129) */
+#            endif                     /* (CONFIG_TIVA_ADC1_SSE2_TRIGGER ==
+                                        * ADC_EMUX_PROC) && defined
+                                        * (CONFIG_ARCH_CHIP_TM4C129) */
+
+#            ifndef CONFIG_TIVA_ADC1_SSE2_STEP3
+  sse_step_cfg(&adc1, 2, 2, chncfg | ADC_SSCTL_END);
 
-#          ifndef CONFIG_TIVA_ADC1_SSE2_STEP3
-  sse_step_cfg(&adc1, 2, 2, chncfg | ADC_SSCTL_END);    /* Signal as last step in the sequence */
-#          else /* CONFIG_TIVA_ADC1_SSE2_STEP3 */
+#            else                      /* CONFIG_TIVA_ADC1_SSE2_STEP3 */
   sse_step_cfg(&adc1, 2, 2, chncfg);
-#          endif /* !CONFIG_TIVA_ADC1_SSE2_STEP3 */
+#            endif                     /* !CONFIG_TIVA_ADC1_SSE2_STEP3 */
 
-#          ifdef CONFIG_TIVA_ADC1_SSE2_STEP3
-#            ifdef CONFIG_TIVA_ADC1_SSE2_STEP3_TS
+#            ifdef CONFIG_TIVA_ADC1_SSE2_STEP3
+#              ifdef CONFIG_TIVA_ADC1_SSE2_STEP3_TS
   chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
-#            else /* ADC_SSCTL_IE */
+#              else                    /* ADC_SSCTL_IE */
   chncfg = ADC_SSCTL_IE;
-#            endif /* CONFIG_TIVA_ADC1_SSE2_STEP3_TS */
+#              endif                   /* CONFIG_TIVA_ADC1_SSE2_STEP3_TS */
 
   tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC1_SSE2_STEP3_AIN));
   sse_register_chn(&adc1, 2, 3, CONFIG_TIVA_ADC1_SSE2_STEP3_AIN);
   sse_differential(&adc1, 2, 3, 0);
-#            if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC1_SSE2_TRIGGER == ADC_EMUX_PROC)
+#              if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC1_SSE2_TRIGGER == ADC_EMUX_PROC)
   sse_sample_hold_time(&adc1, 2, 3, ADC_SSTH_SHOLD_16);
-#            endif /* (CONFIG_TIVA_ADC1_SSE2_TRIGGER == ADC_EMUX_PROC) && defined(CONFIG_ARCH_CHIP_TM4C129) */
+#              endif                   /* (CONFIG_TIVA_ADC1_SSE2_TRIGGER ==
+                                        * ADC_EMUX_PROC) && defined
+                                        * (CONFIG_ARCH_CHIP_TM4C129) */
 
-  sse_step_cfg(&adc1, 2, 3, chncfg | ADC_SSCTL_END);    /* Signal as last step in the sequence */
-#          endif /* CONFIG_TIVA_ADC1_SSE2_STEP3 */
-#        endif /* CONFIG_TIVA_ADC1_SSE2_STEP2 */
-#      endif /* CONFIG_TIVA_ADC1_SSE2_STEP1 */
-#    endif /* CONFIG_TIVA_ADC1_SSE2_STEP0 */
+  sse_step_cfg(&adc1, 2, 3, chncfg | ADC_SSCTL_END);
+
+#            endif                     /* CONFIG_TIVA_ADC1_SSE2_STEP3 */
+#          endif                       /* CONFIG_TIVA_ADC1_SSE2_STEP2 */
+#        endif                         /* CONFIG_TIVA_ADC1_SSE2_STEP1 */
+#      endif                           /* CONFIG_TIVA_ADC1_SSE2_STEP0 */
 }
-#  endif /* CONFIG_TIVA_ADC1_SSE2 */
+#    endif                             /* CONFIG_TIVA_ADC1_SSE2 */
 
-#  ifdef CONFIG_TIVA_ADC1_SSE3
+#    ifdef CONFIG_TIVA_ADC1_SSE3
 static void adc1_sse3_chn_cfg(void)
 {
   uint32_t chncfg = 0;
-#    ifdef CONFIG_TIVA_ADC1_SSE3_STEP0
-#      ifdef CONFIG_TIVA_ADC1_SSE3_STEP0_TS
+#      ifdef CONFIG_TIVA_ADC1_SSE3_STEP0
+#        ifdef CONFIG_TIVA_ADC1_SSE3_STEP0_TS
   chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
-#      else /* ADC_SSCTL_IE */
+#        else                          /* ADC_SSCTL_IE */
   chncfg = ADC_SSCTL_IE;
-#      endif /* CONFIG_TIVA_ADC1_SSE3_STEP0_TS */
+#        endif                         /* CONFIG_TIVA_ADC1_SSE3_STEP0_TS */
 
   tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC1_SSE3_STEP0_AIN));
   sse_register_chn(&adc1, 3, 0, CONFIG_TIVA_ADC1_SSE3_STEP0_AIN);
   sse_differential(&adc1, 3, 0, 0);
-#      if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC1_SSE3_TRIGGER == ADC_EMUX_PROC)
+#        if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC1_SSE3_TRIGGER == ADC_EMUX_PROC)
   sse_sample_hold_time(&adc1, 3, 0, ADC_SSTH_SHOLD_16);
-#      endif /* (CONFIG_TIVA_ADC1_SSE3_TRIGGER == ADC_EMUX_PROC) && defined (CONFIG_ARCH_CHIP_TM4C129) */
+#        endif                         /* (CONFIG_TIVA_ADC1_SSE3_TRIGGER ==
+                                        * ADC_EMUX_PROC) && defined
+                                        * (CONFIG_ARCH_CHIP_TM4C129) */
 
-  sse_step_cfg(&adc1, 3, 0, chncfg | ADC_SSCTL_END);    /* Signal as last step in the sequence */
-#  endif /* CONFIG_TIVA_ADC1_SSE3_STEP0 */
-}
-#  endif /* CONFIG_TIVA_ADC1_SSE3 */
+  sse_step_cfg(&adc1, 3, 0, chncfg | ADC_SSCTL_END);
 
-#endif /* CONFIG_TIVA_ADC1 */
+#      endif                           /* CONFIG_TIVA_ADC1_SSE3_STEP0 */
+}
+#    endif                             /* CONFIG_TIVA_ADC1_SSE3 */
+#  endif                               /* CONFIG_TIVA_ADC1 */
 
-#endif /* CONFIG_TIVA_ADC0 | CONFIG_TIVA_ADC1 */
+#endif                                 /* CONFIG_TIVA_ADC0 | CONFIG_TIVA_ADC1 */