diff options
| author | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2013-01-22 01:25:40 +0000 |
|---|---|---|
| committer | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2013-01-22 01:25:40 +0000 |
| commit | fefa8ee3353d5ac7ef0e925ba8dcbbb89f2c96ae (patch) | |
| tree | a1914fb5c45a61232078c98064198ac8818f07b4 /nuttx/arch | |
| parent | c86261aac88dcc280ca37e532ba96435c1c54699 (diff) | |
| download | nuttx-fefa8ee3353d5ac7ef0e925ba8dcbbb89f2c96ae.tar.gz nuttx-fefa8ee3353d5ac7ef0e925ba8dcbbb89f2c96ae.tar.bz2 nuttx-fefa8ee3353d5ac7ef0e925ba8dcbbb89f2c96ae.zip | |
Add option to use BASEPRI instead of PRIMASK to disable interrupts in all ARMv7-M architectures
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5546 42af7a65-404d-4744-a932-0658087f49c3
Diffstat (limited to 'nuttx/arch')
24 files changed, 1399 insertions, 979 deletions
diff --git a/nuttx/arch/arm/Kconfig b/nuttx/arch/arm/Kconfig index 36343e319..5709f890f 100644 --- a/nuttx/arch/arm/Kconfig +++ b/nuttx/arch/arm/Kconfig @@ -46,7 +46,6 @@ config ARCH_CHIP_KINETIS bool "Freescale Kinetis" select ARCH_CORTEXM4 select ARCH_HAVE_MPU - select ARCH_IRQPRIO select ARCH_HAVE_RAMFUNCS select ARCH_RAMFUNCS ---help--- @@ -55,7 +54,6 @@ config ARCH_CHIP_KINETIS config ARCH_CHIP_LM bool "TI Stellaris" select ARCH_HAVE_MPU - select ARCH_IRQPRIO ---help--- TI Stellaris LMS3 architecutres (ARM Cortex-M3) @@ -63,7 +61,6 @@ config ARCH_CHIP_LPC17XX bool "NXP LPC17xx" select ARCH_CORTEXM3 select ARCH_HAVE_MPU - select ARCH_IRQPRIO ---help--- NXP LPC17xx architectures (ARM Cortex-M3) @@ -95,7 +92,6 @@ config ARCH_CHIP_LPC43XX select ARCH_HAVE_CMNVECTOR select ARMV7M_CMNVECTOR select ARCH_HAVE_MPU - select ARCH_IRQPRIO ---help--- NPX LPC43XX architectures (ARM Cortex-M4). @@ -103,7 +99,6 @@ config ARCH_CHIP_SAM3U bool "Atmel AT91SAM3U" select ARCH_CORTEXM3 select ARCH_HAVE_MPU - select ARCH_IRQPRIO ---help--- Atmel AT91SAM3U architectures (ARM Cortex-M3) @@ -112,7 +107,6 @@ config ARCH_CHIP_STM32 select ARCH_HAVE_CMNVECTOR select ARCH_HAVE_MPU select ARCH_HAVE_I2CRESET - select ARCH_IRQPRIO ---help--- STMicro STM32 architectures (ARM Cortex-M3/4). @@ -136,9 +130,11 @@ config ARCH_ARM920T config ARCH_CORTEXM3 bool + select ARCH_IRQPRIO config ARCH_CORTEXM4 bool + select ARCH_IRQPRIO config ARCH_FAMILY string @@ -162,6 +158,17 @@ config ARCH_CHIP default "stm32" if ARCH_CHIP_STM32 default "str71x" if ARCH_CHIP_STR71X +config ARMV7M_USEBASEPRI + bool "Use BASEPRI Register" + default n + depends on ARCH_CORTEXM3 || ARCH_CORTEXM4 + ---help--- + Use the BASEPRI register to enable and disable able interrupts. By + default, the PRIMASK register is used for this purpose. This + usually results in hardfaults that are properly handling by the + RTOS. Using the BASEPRI register will avoid these hardfault. + That is needed primarily for integration with some toolchains. + config ARCH_HAVE_CMNVECTOR bool diff --git a/nuttx/arch/arm/include/armv7-m/irq.h b/nuttx/arch/arm/include/armv7-m/irq.h index 606b3988f..9491e57c0 100644 --- a/nuttx/arch/arm/include/armv7-m/irq.h +++ b/nuttx/arch/arm/include/armv7-m/irq.h @@ -60,6 +60,10 @@ # include <arch/armv7-m/irq_lazyfpu.h> #endif +#ifdef CONFIG_ARMV7M_USEBASEPRI +# include <arch/chip/chip.h> +#endif + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -130,64 +134,6 @@ struct xcptcontext #ifndef __ASSEMBLY__ -/* Disable IRQs */ - -static inline void irqdisable(void) inline_function; -static inline void irqdisable(void) -{ - __asm__ __volatile__ ("\tcpsid i\n"); -} - -/* Save the current primask state & disable IRQs */ - -static inline irqstate_t irqsave(void) inline_function; -static inline irqstate_t irqsave(void) -{ - unsigned short primask; - - /* Return the current value of primask register and set - * bit 0 of the primask register to disable interrupts - */ - - __asm__ __volatile__ - ( - "\tmrs %0, primask\n" - "\tcpsid i\n" - : "=r" (primask) - : - : "memory"); - - return primask; -} - -/* Enable IRQs */ - -static inline void irqenable(void) inline_function; -static inline void irqenable(void) -{ - __asm__ __volatile__ ("\tcpsie i\n"); -} - -/* Restore saved primask state */ - -static inline void irqrestore(irqstate_t primask) inline_function; -static inline void irqrestore(irqstate_t primask) -{ - /* If bit 0 of the primask is 0, then we need to restore - * interupts. - */ - - __asm__ __volatile__ - ( - "\ttst %0, #1\n" - "\tbne 1f\n" - "\tcpsie i\n" - "1:\n" - : - : "r" (primask) - : "memory"); -} - /* Get/set the primask register */ static inline uint8_t getprimask(void) inline_function; @@ -243,6 +189,85 @@ static inline void setbasepri(uint32_t basepri) : "memory"); } +/* Disable IRQs */ + +static inline void irqdisable(void) inline_function; +static inline void irqdisable(void) +{ +#ifdef CONFIG_ARMV7M_USEBASEPRI + setbasepri(NVIC_SYSH_DISABLE_PRIORITY); +#else + __asm__ __volatile__ ("\tcpsid i\n"); +#endif +} + +/* Save the current primask state & disable IRQs */ + +static inline irqstate_t irqsave(void) inline_function; +static inline irqstate_t irqsave(void) +{ +#ifdef CONFIG_ARMV7M_USEBASEPRI + + uint8_t basepri = getbasepri(); + setbasepri(NVIC_SYSH_DISABLE_PRIORITY); + return basepri; + +#else + + unsigned short primask; + + /* Return the current value of primask register and set + * bit 0 of the primask register to disable interrupts + */ + + __asm__ __volatile__ + ( + "\tmrs %0, primask\n" + "\tcpsid i\n" + : "=r" (primask) + : + : "memory"); + + return primask; +#endif +} + +/* Enable IRQs */ + +static inline void irqenable(void) inline_function; +static inline void irqenable(void) +{ +#ifdef CONFIG_ARMV7M_USEBASEPRI + setbasepri(NVIC_SYSH_PRIORITY_MIN); +#else + __asm__ __volatile__ ("\tcpsie i\n"); +#endif +} + +/* Restore saved primask state */ + +static inline void irqrestore(irqstate_t flags) inline_function; +static inline void irqrestore(irqstate_t flags) +{ +#ifdef CONFIG_ARMV7M_USEBASEPRI + setbasepri(flags); +#else + /* If bit 0 of the primask is 0, then we need to restore + * interupts. + */ + + __asm__ __volatile__ + ( + "\ttst %0, #1\n" + "\tbne 1f\n" + "\tcpsie i\n" + "1:\n" + : + : "r" (flags) + : "memory"); +#endif +} + /* Get/set IPSR */ static inline uint32_t getipsr(void) inline_function; diff --git a/nuttx/arch/arm/include/kinetis/chip.h b/nuttx/arch/arm/include/kinetis/chip.h new file mode 100644 index 000000000..cb686c5d6 --- /dev/null +++ b/nuttx/arch/arm/include/kinetis/chip.h @@ -0,0 +1,850 @@ +/************************************************************************************ + * arch/arm/include/kinetis/chip.h + * + * Copyright (C) 2011, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_KINETIS_CHIP_H +#define __ARCH_ARM_INCLUDE_KINETIS_CHIP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Get customizations for each supported chip */ + +#if defined(CONFIG_ARCH_CHIP_MK40X64VFX50) || defined(CONFIG_ARCH_CHIP_MK40X64VLH50) || \ + defined(CONFIG_ARCH_CHIP_MK40X64VLK50) || defined(CONFIG_ARCH_CHIP_MK40X64VMB50) +# define KINETIS_K40 1 /* Kinetics K40 family */ +# undef KINETIS_K60 /* Not Kinetis K60 family */ +# define KINETIS_FLASH_SIZE (64*1024) /* 64Kb */ +# define KINETIS_FLEXMEM_SIZE (32*1024) /* 32Kb */ +# define KINETIS_SRAM_SIZE (16*1024) /* 16Kb */ +# undef KINETIS_MPU /* No memory protection unit */ +# undef KINETIS_EXTBUS /* No external bus interface */ +# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ +# undef KINETIS_NENET /* No Ethernet controller */ +# define KINETIS_NUSBHOST 1 /* One USB host controller */ +# define KINETIS_NUSBOTG 1 /* With USB OTG controller */ +# define KINETIS_NUSBDEV 1 /* One USB device controller */ +# undef KINETIS_NSDHC /* No SD host controller */ +# undef KINETIS_NTOUCHIF /* Xtrinsic touch sensing interface */ +# define KINETIS_NI2C 2 /* Two I2C modules */ +# undef KINETIS_NISO7816 /* No UART with ISO-786 */ +# define KINETIS_NUART 6 /* Six UARTs */ +# define KINETIS_NSPI 3 /* Three SPI modules */ +# if defined(CONFIG_ARCH_CHIP_MK40X64VLK50) || defined(CONFIG_ARCH_CHIP_MK40X64VMB50) +# define KINETIS_NCAN 2 /* Two CAN controllers */ +# else +# undef KINETIS_NCAN /* No CAN in 64-pin chips */ +# endif +# define KINETIS_NI2S 1 /* One I2S module */ +# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 25x8/29x4) */ +# define KINETIS_NADC16 4 /* Four 16-bit ADC */ +# undef KINETIS_NADC12 /* No 12-channel ADC */ +# undef KINETIS_NADC13 /* No 13-channel ADC */ +# undef KINETIS_NADC15 /* No 15-channel ADC */ +# undef KINETIS_NADC18 /* No 18-channel ADC */ +# define KINETIS_NPGA 2 /* Two Programmable Gain Amplifiers */ +# define KINETIS_NCMP 3 /* Three analog comparators */ +# define KINETIS_NDAC6 3 /* Three 6-bit DAC */ +# define KINETIS_NDAC12 2 /* Two 12-bit DAC */ +# define KINETIS_NVREF 1 /* Voltage reference */ +# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ +# undef KINETIS_NTIMERS20 /* No 20 channel timers */ +# undef KINETIS_NRNG /* No random number generator */ +# define KINETIS_NRTC 1 /* Real time clock */ +# undef KINETIS_NMMCAU /* No hardware encryption */ +# undef KINETIS_NTAMPER /* No tamper detect */ +# define KINETIS_NCRC 1 /* CRC */ + +#elif defined(CONFIG_ARCH_CHIP_MK40X128VFX50) || defined(CONFIG_ARCH_CHIP_MK40X128VLH50) || \ + defined(CONFIG_ARCH_CHIP_MK40X128VLK50) || defined(CONFIG_ARCH_CHIP_MK40X128VMB50) || \ + defined(CONFIG_ARCH_CHIP_MK40X128VLL50) || defined(CONFIG_ARCH_CHIP_MK40X128VML50) || \ + defined(CONFIG_ARCH_CHIP_MK40X128VFX72) || defined(CONFIG_ARCH_CHIP_MK40X128VLH72) || \ + defined(CONFIG_ARCH_CHIP_MK40X128VLK72) || defined(CONFIG_ARCH_CHIP_MK40X128VMB72) || \ + defined(CONFIG_ARCH_CHIP_MK40X128VLL72) || defined(CONFIG_ARCH_CHIP_MK40X128VML72) +# define KINETIS_K40 1 /* Kinetics K40 family */ +# undef KINETIS_K60 /* Not Kinetis K60 family */ +# define KINETIS_FLASH_SIZE (128*1024) /* 128Kb */ +# define KINETIS_FLEXMEM_SIZE (32*1024) /* 32Kb */ +# define KINETIS_SRAM_SIZE (32*1024) /* 32Kb */ +# undef KINETIS_MPU /* No memory protection unit */ +# undef KINETIS_EXTBUS /* No external bus interface */ +# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ +# undef KINETIS_NENET /* No Ethernet controller */ +# define KINETIS_NUSBHOST 1 /* One USB host controller */ +# define KINETIS_NUSBOTG 1 /* With USB OTG controller */ +# define KINETIS_NUSBDEV 1 /* One USB device controller */ +# undef KINETIS_NSDHC /* No SD host controller */ +# undef KINETIS_NTOUCHIF /* Xtrinsic touch sensing interface */ +# define KINETIS_NI2C 2 /* Two I2C modules */ +# undef KINETIS_NISO7816 /* No UART with ISO-786 */ +# define KINETIS_NUART 6 /* Six UARTs */ +# define KINETIS_NSPI 3 /* Three SPI modules */ +# define KINETIS_NCAN 2 /* Two CAN controllers */ +# define KINETIS_NI2S 1 /* One I2S module */ +# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */ +# define KINETIS_NADC16 4 /* Four 16-bit ADC */ +# undef KINETIS_NADC12 /* No 12-channel ADC */ +# undef KINETIS_NADC13 /* No 13-channel ADC */ +# undef KINETIS_NADC15 /* No 15-channel ADC */ +# undef KINETIS_NADC18 /* No 18-channel ADC */ +# define KINETIS_NPGA 2 /* Two Programmable Gain Amplifiers */ +# define KINETIS_NCMP 3 /* Three analog comparators */ +# define KINETIS_NDAC6 3 /* Three 6-bit DAC */ +# define KINETIS_NDAC12 2 /* Two 12-bit DAC */ +# define KINETIS_NVREF 1 /* Voltage reference */ +# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ +# undef KINETIS_NTIMERS20 /* No 20 channel timers */ +# define KINETIS_NRTC 1 /* Real time clock */ +# undef KINETIS_NRNG /* No random number generator */ +# undef KINETIS_NMMCAU /* No hardware encryption */ +# undef KINETIS_NTAMPER /* No tamper detect */ +# define KINETIS_NCRC 1 /* CRC */ + +#elif defined(CONFIG_ARCH_CHIP_MK40X256VLK72) || defined(CONFIG_ARCH_CHIP_MK40X256VMB72) || \ + defined(CONFIG_ARCH_CHIP_MK40X256VLL72) || defined(CONFIG_ARCH_CHIP_MK40X256VML72) +# define KINETIS_K40 1 /* Kinetics K40 family */ +# undef KINETIS_K60 /* Not Kinetis K60 family */ +# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */ +# define KINETIS_FLEXMEM_SIZE (32*1024) /* 32Kb */ +# define KINETIS_SRAM_SIZE (32*1024) /* 64Kb */ +# undef KINETIS_MPU /* No memory protection unit */ +# undef KINETIS_EXTBUS /* No external bus interface */ +# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ +# undef KINETIS_NENET /* No Ethernet controller */ +# define KINETIS_NUSBHOST 1 /* One USB host controller */ +# define KINETIS_NUSBOTG 1 /* With USB OTG controller */ +# define KINETIS_NUSBDEV 1 /* One USB device controller */ +# undef KINETIS_NSDHC /* No SD host controller */ +# undef KINETIS_NTOUCHIF /* Xtrinsic touch sensing interface */ +# define KINETIS_NI2C 2 /* Two I2C modules */ +# undef KINETIS_NISO7816 /* No UART with ISO-786 */ +# define KINETIS_NUART 6 /* Six UARTs */ +# define KINETIS_NSPI 3 /* Three SPI modules */ +# define KINETIS_NCAN 2 /* Two CAN controllers */ +# define KINETIS_NI2S 1 /* One I2S module */ +# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */ +# define KINETIS_NADC16 4 /* Four 16-bit ADC */ +# undef KINETIS_NADC12 /* No 12-channel ADC */ +# undef KINETIS_NADC13 /* No 13-channel ADC */ +# undef KINETIS_NADC15 /* No 15-channel ADC */ +# undef KINETIS_NADC18 /* No 18-channel ADC */ +# define KINETIS_NPGA 2 /* Two Programmable Gain Amplifiers */ +# define KINETIS_NCMP 3 /* Three analog comparators */ +# define KINETIS_NDAC6 3 /* Three 6-bit DAC */ +# define KINETIS_NDAC12 2 /* Two 12-bit DAC */ +# define KINETIS_NVREF 1 /* Voltage reference */ +# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ +# undef KINETIS_NTIMERS20 /* No 20 channel timers */ +# define KINETIS_NRTC 1 /* Real time clock */ +# undef KINETIS_NRNG /* No random number generator */ +# undef KINETIS_NMMCAU /* No hardware encryption */ +# undef KINETIS_NTAMPER /* No tamper detect */ +# define KINETIS_NCRC 1 /* CRC */ + +#elif defined(CONFIG_ARCH_CHIP_MK40X128VLQ100) || defined(CONFIG_ARCH_CHIP_MK40X128VMD100) +# define KINETIS_K40 1 /* Kinetics K40 family */ +# undef KINETIS_K60 /* Not Kinetis K60 family */ +# define KINETIS_FLASH_SIZE (128*1024) /* 128Kb */ +# define KINETIS_FLEXMEM_SIZE (128*1024) /* 128Kb */ +# define KINETIS_SRAM_SIZE (32*1024) /* 32Kb */ +# define KINETIS_MPU 1 /* Memory protection unit */ +# define KINETIS_EXTBUS 1 /* External bus interface */ +# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ +# undef KINETIS_NENET /* No Ethernet controller */ +# define KINETIS_NUSBHOST 1 /* One USB host controller */ +# define KINETIS_NUSBOTG 1 /* With USB OTG controller */ +# define KINETIS_NUSBDEV 1 /* One USB device controller */ +# define KINETIS_NSDHC 1 /* One SD host controller */ +# undef KINETIS_NTOUCHIF /* Xtrinsic touch sensing interface */ +# define KINETIS_NI2C 2 /* Two I2C modules */ +# undef KINETIS_NISO7816 /* No UART with ISO-786 */ +# define KINETIS_NUART 6 /* Six UARTs */ +# define KINETIS_NSPI 3 /* Three SPI modules */ +# define KINETIS_NCAN 2 /* Two CAN controllers */ +# define KINETIS_NI2S 1 /* One I2S module */ +# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 40x8/44x4)*/ +# define KINETIS_NADC16 4 /* Four 16-bit ADC */ +# undef KINETIS_NADC12 /* No 12-channel ADC */ +# undef KINETIS_NADC13 /* No 13-channel ADC */ +# undef KINETIS_NADC15 /* No 15-channel ADC */ +# undef KINETIS_NADC18 /* No 18-channel ADC */ +# define KINETIS_NPGA 2 /* Two Programmable Gain Amplifiers */ +# define KINETIS_NCMP 3 /* Three analog comparators */ +# define KINETIS_NDAC6 3 /* Three 6-bit DAC */ +# define KINETIS_NDAC12 2 /* Two 12-bit DAC */ +# define KINETIS_NVREF 1 /* Voltage reference */ +# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ +# undef KINETIS_NTIMERS20 /* No 20 channel timers */ +# define KINETIS_NRTC 1 /* Real time clock */ +# undef KINETIS_NRNG /* No random number generator */ +# undef KINETIS_NMMCAU /* No hardware encryption */ +# undef KINETIS_NTAMPER /* No tamper detect */ +# define KINETIS_NCRC 1 /* CRC */ + +#elif defined(CONFIG_ARCH_CHIP_MK40X256VLQ100) || defined(CONFIG_ARCH_CHIP_MK40X256VMD100) +# define KINETIS_K40 1 /* Kinetics K40 family */ +# undef KINETIS_K60 /* Not Kinetis K60 family */ +# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */ +# define KINETIS_FLEXMEM_SIZE (256*1024) /* 256Kb */ +# define KINETIS_SRAM_SIZE (64*1024) /* 32Kb */ +# define KINETIS_MPU 1 /* Memory protection unit */ +# define KINETIS_EXTBUS 1 /* External bus interface */ +# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ +# undef KINETIS_NENET /* No Ethernet controller */ +# define KINETIS_NUSBHOST 1 /* One USB host controller */ +# define KINETIS_NUSBOTG 1 /* With USB OTG controller */ +# define KINETIS_NUSBDEV 1 /* One USB device controller */ +# define KINETIS_NSDHC 1 /* One SD host controller */ +# undef KINETIS_NTOUCHIF /* Xtrinsic touch sensing interface */ +# define KINETIS_NI2C 2 /* Two I2C modules */ +# undef KINETIS_NISO7816 /* No UART with ISO-786 */ +# define KINETIS_NUART 6 /* Six UARTs */ +# define KINETIS_NSPI 3 /* Three SPI modules */ +# define KINETIS_NCAN 2 /* Two CAN controllers */ +# define KINETIS_NI2S 1 /* One I2S module */ +# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 40x8/44x4)*/ +# define KINETIS_NADC16 4 /* Four 16-bit ADC */ +# undef KINETIS_NADC12 /* No 12-channel ADC */ +# undef KINETIS_NADC13 /* No 13-channel ADC */ +# undef KINETIS_NADC15 /* No 15-channel ADC */ +# undef KINETIS_NADC18 /* No 18-channel ADC */ +# define KINETIS_NPGA 2 /* Two Programmable Gain Amplifiers */ +# define KINETIS_NCMP 3 /* Three analog comparators */ +# define KINETIS_NDAC6 3 /* Three 6-bit DAC */ +# define KINETIS_NDAC12 2 /* Two 12-bit DAC */ +# define KINETIS_NVREF 1 /* Voltage reference */ +# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ +# undef KINETIS_NTIMERS20 /* No 20 channel timers */ +# define KINETIS_NRTC 1 /* Real time clock */ +# undef KINETIS_NRNG /* No random number generator */ +# undef KINETIS_NMMCAU /* No hardware encryption */ +# undef KINETIS_NTAMPER /* No tamper detect */ +# define KINETIS_NCRC 1 /* CRC */ + +#elif defined(CONFIG_ARCH_CHIP_MK40N512VLK100) || defined(CONFIG_ARCH_CHIP_MK40N512VMB100) || \ + defined(CONFIG_ARCH_CHIP_MK40N512VLL100) || defined(CONFIG_ARCH_CHIP_MK40N512VML100) || \ + defined(CONFIG_ARCH_CHIP_MK40N512VLQ100) || defined(CONFIG_ARCH_CHIP_MK40N512VMD100) +# define KINETIS_K40 1 /* Kinetics K40 family */ +# undef KINETIS_K60 /* Not Kinetis K60 family */ +# define KINETIS_FLASH_SIZE (512*1024) /* 512Kb */ +# undef KINETIS_FLEXMEM_SIZE /* No FlexMemory */ +# define KINETIS_SRAM_SIZE (128*1024) /* 128Kb */ +# define KINETIS_MPU 1 /* Memory protection unit */ +# define KINETIS_EXTBUS 1 /* External bus interface */ +# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ +# undef KINETIS_NENET /* No Ethernet controller */ +# define KINETIS_NUSBHOST 1 /* One USB host controller */ +# define KINETIS_NUSBOTG 1 /* With USB OTG controller */ +# define KINETIS_NUSBDEV 1 /* One USB device controller */ +# define KINETIS_NSDHC 1 /* One SD host controller */ +# undef KINETIS_NTOUCHIF /* Xtrinsic touch sensing interface */ +# define KINETIS_NI2C 2 /* Two I2C modules */ +# undef KINETIS_NISO7816 /* No UART with ISO-786 */ +# define KINETIS_NUART 6 /* Six UARTs */ +# define KINETIS_NSPI 3 /* Three SPI modules */ +# define KINETIS_NCAN 2 /* Two CAN controllers */ +# define KINETIS_NI2S 1 /* One I2S module */ +# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 40x8/44x4)*/ +# define KINETIS_NADC16 4 /* Four 16-bit ADC */ +# undef KINETIS_NADC12 /* No 12-channel ADC */ +# undef KINETIS_NADC13 /* No 13-channel ADC */ +# undef KINETIS_NADC15 /* No 15-channel ADC */ +# undef KINETIS_NADC18 /* No 18-channel ADC */ +# define KINETIS_NPGA 2 /* Two Programmable Gain Amplifiers */ +# define KINETIS_NCMP 3 /* Three analog comparators */ +# define KINETIS_NDAC6 3 /* Three 6-bit DAC */ +# define KINETIS_NDAC12 2 /* Two 12-bit DAC */ +# define KINETIS_NVREF 1 /* Voltage reference */ +# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ +# undef KINETIS_NTIMERS20 /* No 20 channel timers */ +# define KINETIS_NRTC 1 /* Real time clock */ +# undef KINETIS_NRNG /* No random number generator */ +# undef KINETIS_NMMCAU /* No hardware encryption */ +# undef KINETIS_NTAMPER /* No tamper detect */ +# define KINETIS_NCRC 1 /* CRC */ + +#elif defined(CONFIG_ARCH_CHIP_MK60N256VLL100) +# undef KINETIS_K40 /* Not Kinetics K40 family */ +# define KINETIS_K60 1 /* Kinetis K60 family */ +# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */ +# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */ +# undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */ +# define KINETIS_SRAM_SIZE (64*1024) /* 64Kb */ +# define KINETIS_MPU 1 /* Memory protection unit */ +# define KINETIS_EXTBUS 1 /* External bus interface */ +# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ +# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */ +# define KINETIS_NUSBHOST 1 /* One USB host controller */ +# define KINETIS_NUSBOTG 1 /* With USB OTG controller */ +# define KINETIS_NUSBDEV 1 /* One USB device controller */ +# define KINETIS_NSDHC 1 /* SD host controller */ +# define KINETIS_NTOUCHIF 1 /* Xtrinsic touch sensing interface */ +# define KINETIS_NI2C 3 /* Three I2C modules */ +# define KINETIS_NISO7816 1 /* One UART with ISO-786 */ +# define KINETIS_NUART 4 /* Four additional UARTs */ +# define KINETIS_NSPI 3 /* Three SPI modules */ +# define KINETIS_NCAN 2 /* Two CAN controllers */ +# define KINETIS_NI2S 2 /* Two I2S modules */ +# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */ +# define KINETIS_NADC16 4 /* Four 16-bit ADC */ +# define KINETIS_NADC12 1 /* One 12-channel ADC (ADC0)*/ +# define KINETIS_NADC13 1 /* No 13-channel ADC (ADC1) */ +# undef KINETIS_NADC15 /* No 15-channel ADC */ +# undef KINETIS_NADC18 /* No 18-channel ADC */ +# define KINETIS_NPGA 4 /* Four Programmable Gain Amplifiers */ +# define KINETIS_NCMP 3 /* Three analog comparators */ +# undef KINETIS_NDAC6 /* No 6-bit DAC */ +# define KINETIS_NDAC12 1 /* One 12-bit DAC */ +# define KINETIS_NVREF 1 /* Voltage reference */ +# undef KINETIS_NTIMERS12 /* No 12 channel timers */ +# define KINETIS_NTIMERS20 4 /* Four 20 channel timers */ +# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ +# undef KINETIS_NTIMERS20 /* No 20 channel timers */ +# define KINETIS_NRTC 1 /* Real time clock */ +# undef KINETIS_NRNG /* No random number generator */ +# undef KINETIS_NMMCAU /* No hardware encryption */ +# undef KINETIS_NTAMPER /* No tamper detect */ +# define KINETIS_NCRC 1 /* CRC */ + +#elif defined(CONFIG_ARCH_CHIP_MK60X256VLL100) +# undef KINETIS_K40 /* Not Kinetics K40 family */ +# define KINETIS_K60 1 /* Kinetis K60 family */ +# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */ +# define KINETIS_FLEXNVM_SIZE (256*1024) /* 256Kb */ +# define KINETIS_FLEXRAM_SIZE (4*1024) /* 32Kb */ +# define KINETIS_SRAM_SIZE (64*1024) /* 64Kb */ +# define KINETIS_MPU 1 /* Memory protection unit */ +# define KINETIS_EXTBUS 1 /* External bus interface */ +# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ +# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */ +# define KINETIS_NUSBHOST 1 /* One USB host controller */ +# define KINETIS_NUSBOTG 1 /* With USB OTG controller */ +# define KINETIS_NUSBDEV 1 /* One USB device controller */ +# define KINETIS_NSDHC 1 /* SD host controller */ +# define KINETIS_NTOUCHIF 1 /* Xtrinsic touch sensing interface */ +# define KINETIS_NI2C 3 /* Three I2C modules */ +# define KINETIS_NISO7816 1 /* One UART with ISO-786 */ +# define KINETIS_NUART 4 /* Four additional UARTs */ +# define KINETIS_NSPI 3 /* Three SPI modules */ +# define KINETIS_NCAN 2 /* Two CAN controllers */ +# define KINETIS_NI2S 2 /* Two I2S modules */ +# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */ +# define KINETIS_NADC16 4 /* Four 16-bit ADC */ +# define KINETIS_NADC12 1 /* One 12-channel ADC (ADC0)*/ +# define KINETIS_NADC13 1 /* No 13-channel ADC (ADC1) */ +# undef KINETIS_NADC15 /* No 15-channel ADC */ +# undef KINETIS_NADC18 /* No 18-channel ADC */ +# define KINETIS_NPGA 4 /* Four Programmable Gain Amplifiers */ +# define KINETIS_NCMP 3 /* Three analog comparators */ +# undef KINETIS_NDAC6 /* No 6-bit DAC */ +# define KINETIS_NDAC12 1 /* One 12-bit DAC */ +# define KINETIS_NVREF 1 /* Voltage reference */ +# undef KINETIS_NTIMERS12 /* No 12 channel timers */ +# define KINETIS_NTIMERS20 4 /* Four 20 channel timers */ +# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ +# undef KINETIS_NTIMERS20 /* No 20 channel timers */ +# define KINETIS_NRTC 1 /* Real time clock */ +# undef KINETIS_NRNG /* No random number generator */ +# undef KINETIS_NMMCAU /* No hardware encryption */ +# undef KINETIS_NTAMPER /* No tamper detect */ +# define KINETIS_NCRC 1 /* CRC */ + +#elif defined(CONFIG_ARCH_CHIP_MK60N512VLL100) +# undef KINETIS_K40 /* Not Kinetics K40 family */ +# define KINETIS_K60 1 /* Kinetis K60 family */ +# define KINETIS_FLASH_SIZE (512*1024) /* 256Kb */ +# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */ +# undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */ +# define KINETIS_SRAM_SIZE (128*1024) /* 128Kb */ +# define KINETIS_MPU 1 /* Memory protection unit */ +# define KINETIS_EXTBUS 1 /* External bus interface */ +# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ +# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */ +# define KINETIS_NUSBHOST 1 /* One USB host controller */ +# define KINETIS_NUSBOTG 1 /* With USB OTG controller */ +# define KINETIS_NUSBDEV 1 /* One USB device controller */ +# define KINETIS_NSDHC 1 /* SD host controller */ +# define KINETIS_NTOUCHIF 1 /* Xtrinsic touch sensing interface */ +# define KINETIS_NI2C 3 /* Three I2C modules */ +# define KINETIS_NISO7816 1 /* One UART with ISO-786 */ +# define KINETIS_NUART 4 /* Four additional UARTs */ +# define KINETIS_NSPI 3 /* Three SPI modules */ +# define KINETIS_NCAN 2 /* Two CAN controllers */ +# define KINETIS_NI2S 2 /* Two I2S modules */ +# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */ +# define KINETIS_NADC16 4 /* Four 16-bit ADC */ +# define KINETIS_NADC12 1 /* One 12-channel ADC (ADC0)*/ +# define KINETIS_NADC13 1 /* No 13-channel ADC (ADC1) */ +# undef KINETIS_NADC15 /* No 15-channel ADC */ +# undef KINETIS_NADC18 /* No 18-channel ADC */ +# define KINETIS_NPGA 4 /* Four Programmable Gain Amplifiers */ +# define KINETIS_NCMP 3 /* Three analog comparators */ +# undef KINETIS_NDAC6 /* No 6-bit DAC */ +# define KINETIS_NDAC12 1 /* One 12-bit DAC */ +# define KINETIS_NVREF 1 /* Voltage reference */ +# undef KINETIS_NTIMERS12 /* No 12 channel timers */ +# define KINETIS_NTIMERS20 4 /* Four 20 channel timers */ +# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ +# undef KINETIS_NTIMERS20 /* No 20 channel timers */ +# define KINETIS_NRTC 1 /* Real time clock */ +# undef KINETIS_NRNG /* No random number generator */ +# undef KINETIS_NMMCAU /* No hardware encryption */ +# undef KINETIS_NTAMPER /* No tamper detect */ +# define KINETIS_NCRC 1 /* CRC */ + +#elif defined(CONFIG_ARCH_CHIP_MK60N256VML100) +# undef KINETIS_K40 /* Not Kinetics K40 family */ +# define KINETIS_K60 1 /* Kinetis K60 family */ +# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */ +# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */ +# undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */ +# define KINETIS_SRAM_SIZE (64*1024) /* 64Kb */ +# define KINETIS_MPU 1 /* Memory protection unit */ +# define KINETIS_EXTBUS 1 /* External bus interface */ +# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ +# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */ +# define KINETIS_NUSBHOST 1 /* One USB host controller */ +# define KINETIS_NUSBOTG 1 /* With USB OTG controller */ +# define KINETIS_NUSBDEV 1 /* One USB device controller */ +# define KINETIS_NSDHC 1 /* SD host controller */ +# define KINETIS_NTOUCHIF 1 /* Xtrinsic touch sensing interface */ +# define KINETIS_NI2C 3 /* Three I2C modules */ +# define KINETIS_NISO7816 1 /* One UART with ISO-786 */ +# define KINETIS_NUART 4 /* Four additional UARTs */ +# define KINETIS_NSPI 3 /* Three SPI modules */ +# define KINETIS_NCAN 2 /* Two CAN controllers */ +# define KINETIS_NI2S 2 /* Two I2S modules */ +# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */ +# define KINETIS_NADC16 4 /* Four 16-bit ADC */ +# define KINETIS_NADC12 1 /* One 12-channel ADC (ADC0)*/ +# undef KINETIS_NADC13 /* No 13-channel ADC */ +# define KINETIS_NADC15 1 /* One 15-channel ADC (ADC1) */ +# undef KINETIS_NADC18 /* No 18-channel ADC */ +# define KINETIS_NPGA 4 /* Four Programmable Gain Amplifiers */ +# define KINETIS_NCMP 3 /* Three analog comparators */ +# undef KINETIS_NDAC6 /* No 6-bit DAC */ +# define KINETIS_NDAC12 1 /* One 12-bit DAC */ +# define KINETIS_NVREF 1 /* Voltage reference */ +# undef KINETIS_NTIMERS12 /* No 12 channel timers */ +# define KINETIS_NTIMERS20 4 /* Four 20 channel timers */ +# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ +# undef KINETIS_NTIMERS20 /* No 20 channel timers */ +# define KINETIS_NRTC 1 /* Real time clock */ +# undef KINETIS_NRNG /* No random number generator */ +# undef KINETIS_NMMCAU /* No hardware encryption */ +# undef KINETIS_NTAMPER /* No tamper detect */ +# define KINETIS_NCRC 1 /* CRC */ + +#elif defined(CONFIG_ARCH_CHIP_MK60X256VML100) +# undef KINETIS_K40 /* Not Kinetics K40 family */ +# define KINETIS_K60 1 /* Kinetis K60 family */ +# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */ +# define KINETIS_FLEXNVM_SIZE (256*1024) /* 256Kb */ +# define KINETIS_FLEXRAM_SIZE (4*1024) /* 4Kb */ +# define KINETIS_SRAM_SIZE (64*1024) /* 64Kb */ +# define KINETIS_MPU 1 /* Memory protection unit */ +# define KINETIS_EXTBUS 1 /* External bus interface */ +# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ +# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */ +# define KINETIS_NUSBHOST 1 /* One USB host controller */ +# define KINETIS_NUSBOTG 1 /* With USB OTG controller */ +# define KINETIS_NUSBDEV 1 /* One USB device controller */ +# define KINETIS_NSDHC 1 /* SD host controller */ +# define KINETIS_NTOUCHIF 1 /* Xtrinsic touch sensing interface */ +# define KINETIS_NI2C 3 /* Three I2C modules */ +# define KINETIS_NISO7816 1 /* One UART with ISO-786 */ +# define KINETIS_NUART 4 /* Four additional UARTs */ +# define KINETIS_NSPI 3 /* Three SPI modules */ +# define KINETIS_NCAN 2 /* Two CAN controllers */ +# define KINETIS_NI2S 2 /* Two I2S modules */ +# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */ +# define KINETIS_NADC16 4 /* Four 16-bit ADC */ +# define KINETIS_NADC12 1 /* One 12-channel ADC (ADC0)*/ +# undef KINETIS_NADC13 /* No 13-channel ADC */ +# define KINETIS_NADC15 1 /* One 15-channel ADC (ADC1) */ +# undef KINETIS_NADC18 /* No 18-channel ADC */ +# define KINETIS_NPGA 4 /* Four Programmable Gain Amplifiers */ +# define KINETIS_NCMP 3 /* Three analog comparators */ +# undef KINETIS_NDAC6 /* No 6-bit DAC */ +# define KINETIS_NDAC12 1 /* One 12-bit DAC */ +# define KINETIS_NVREF 1 /* Voltage reference */ +# undef KINETIS_NTIMERS12 /* No 12 channel timers */ +# define KINETIS_NTIMERS20 4 /* Four 20 channel timers */ +# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ +# undef KINETIS_NTIMERS20 /* No 20 channel timers */ +# define KINETIS_NRTC 1 /* Real time clock */ +# undef KINETIS_NRNG /* No random number generator */ +# undef KINETIS_NMMCAU /* No hardware encryption */ +# undef KINETIS_NTAMPER /* No tamper detect */ +# define KINETIS_NCRC 1 /* CRC */ + +#elif defined(CONFIG_ARCH_CHIP_MK60N512VML100) +# undef KINETIS_K40 /* Not Kinetics K40 family */ +# define KINETIS_K60 1 /* Kinetis K60 family */ +# define KINETIS_FLASH_SIZE (512*1024) /* 256Kb */ +# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */ +# undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */ +# define KINETIS_SRAM_SIZE (128*1024) /* 128Kb */ +# define KINETIS_MPU 1 /* Memory protection unit */ +# define KINETIS_EXTBUS 1 /* External bus interface */ +# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ +# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */ +# define KINETIS_NUSBHOST 1 /* One USB host controller */ +# define KINETIS_NUSBOTG 1 /* With USB OTG controller */ +# define KINETIS_NUSBDEV 1 /* One USB device controller */ +# define KINETIS_NSDHC 1 /* SD host controller */ +# define KINETIS_NTOUCHIF 1 /* Xtrinsic touch sensing interface */ +# define KINETIS_NI2C 3 /* Three I2C modules */ +# define KINETIS_NISO7816 1 /* One UART with ISO-786 */ +# define KINETIS_NUART 4 /* Four additional UARTs */ +# define KINETIS_NSPI 3 /* Three SPI modules */ +# define KINETIS_NCAN 2 /* Two CAN controllers */ +# define KINETIS_NI2S 2 /* Two I2S modules */ +# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */ +# define KINETIS_NADC16 4 /* Four 16-bit ADC */ +# define KINETIS_NADC12 1 /* One 12-channel ADC (ADC0)*/ +# undef KINETIS_NADC13 /* No 13-channel ADC */ +# define KINETIS_NADC15 1 /* One 15-channel ADC (ADC1) */ +# undef KINETIS_NADC18 /* No 18-channel ADC */ +# define KINETIS_NPGA 4 /* Four Programmable Gain Amplifiers */ +# define KINETIS_NCMP 3 /* Three analog comparators */ +# undef KINETIS_NDAC6 /* No 6-bit DAC */ +# define KINETIS_NDAC12 1 /* One 12-bit DAC */ +# define KINETIS_NVREF 1 /* Voltage reference */ +# undef KINETIS_NTIMERS12 /* No 12 channel timers */ +# define KINETIS_NTIMERS20 4 /* Four 20 channel timers */ +# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ +# undef KINETIS_NTIMERS20 /* No 20 channel timers */ +# define KINETIS_NRTC 1 /* Real time clock */ +# undef KINETIS_NRNG /* No random number generator */ +# undef KINETIS_NMMCAU /* No hardware encryption */ +# undef KINETIS_NTAMPER /* No tamper detect */ +# define KINETIS_NCRC 1 /* CRC */ + +#elif defined(CONFIG_ARCH_CHIP_MK60N256VLQ100) +# undef KINETIS_K40 /* Not Kinetics K40 family */ +# define KINETIS_K60 1 /* Kinetis K60 family */ +# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */ +# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */ +# undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */ +# define KINETIS_SRAM_SIZE (64*1024) /* 64Kb */ +# define KINETIS_MPU 1 /* Memory protection unit */ +# define KINETIS_EXTBUS 1 /* External bus interface */ +# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ +# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */ +# define KINETIS_NUSBHOST 1 /* One USB host controller */ +# define KINETIS_NUSBOTG 1 /* With USB OTG controller */ +# define KINETIS_NUSBDEV 1 /* One USB device controller */ +# define KINETIS_NSDHC 1 /* SD host controller */ +# define KINETIS_NTOUCHIF 1 /* Xtrinsic touch sensing interface */ +# define KINETIS_NI2C 3 /* Three I2C modules */ +# define KINETIS_NISO7816 1 /* One UART with ISO-786 */ +# define KINETIS_NUART 5 /* Five additional UARTs */ +# define KINETIS_NSPI 3 /* Three SPI modules */ +# define KINETIS_NCAN 2 /* Two CAN controllers */ +# define KINETIS_NI2S 2 /* Two I2S modules */ +# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */ +# define KINETIS_NADC16 4 /* Four 16-bit ADC */ +# undef KINETIS_NADC12 /* No 12-channel ADC */ +# undef KINETIS_NADC13 /* No 13-channel ADC */ +# define KINETIS_NADC15 1 /* One 15-channel ADC (ADC0) */ +# define KINETIS_NADC18 1 /* One 18-channel ADC (ADC1) */ +# define KINETIS_NPGA 4 /* Four Programmable Gain Amplifiers */ +# define KINETIS_NCMP 3 /* Three analog comparators */ +# undef KINETIS_NDAC6 /* No 6-bit DAC */ +# define KINETIS_NDAC12 2 /* Twp 12-bit DACs */ +# define KINETIS_NVREF 1 /* Voltage reference */ +# undef KINETIS_NTIMERS12 /* No 12 channel timers */ +# define KINETIS_NTIMERS20 4 /* Four 20 channel timers */ +# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ +# undef KINETIS_NTIMERS20 /* No 20 channel timers */ +# define KINETIS_NRTC 1 /* Real time clock */ +# undef KINETIS_NRNG /* No random number generator */ +# undef KINETIS_NMMCAU /* No hardware encryption */ +# undef KINETIS_NTAMPER /* No tamper detect */ +# define KINETIS_NCRC 1 /* CRC */ + +#elif defined(CONFIG_ARCH_CHIP_MK60X256VLQ100) +# undef KINETIS_K40 /* Not Kinetics K40 family */ +# define KINETIS_K60 1 /* Kinetis K60 family */ +# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */ +# define KINETIS_FLEXNVM_SIZE (256*1024) /* 256Kb */ +# define KINETIS_FLEXRAM_SIZE (4*1024) /* 4Kb */ +# define KINETIS_SRAM_SIZE (64*1024) /* 64Kb */ +# define KINETIS_MPU 1 /* Memory protection unit */ +# define KINETIS_EXTBUS 1 /* External bus interface */ +# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ +# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */ +# define KINETIS_NUSBHOST 1 /* One USB host controller */ +# define KINETIS_NUSBOTG 1 /* With USB OTG controller */ +# define KINETIS_NUSBDEV 1 /* One USB device controller */ +# define KINETIS_NSDHC 1 /* SD host controller */ +# define KINETIS_NTOUCHIF 1 /* Xtrinsic touch sensing interface */ +# define KINETIS_NI2C 3 /* Three I2C modules */ +# define KINETIS_NISO7816 1 /* One UART with ISO-786 */ +# define KINETIS_NUART 5 /* Five additional UARTs */ +# define KINETIS_NSPI 3 /* Three SPI modules */ +# define KINETIS_NCAN 2 /* Two CAN controllers */ +# define KINETIS_NI2S 2 /* Two I2S modules */ +# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */ +# define KINETIS_NADC16 4 /* Four 16-bit ADC */ +# undef KINETIS_NADC12 /* No 12-channel ADC */ +# undef KINETIS_NADC13 /* No 13-channel ADC */ +# define KINETIS_NADC15 1 /* One 15-channel ADC (ADC0) */ +# define KINETIS_NADC18 1 /* One 18-channel ADC (ADC1) */ +# define KINETIS_NPGA 4 /* Four Programmable Gain Amplifiers */ +# define KINETIS_NCMP 3 /* Three analog comparators */ +# undef KINETIS_NDAC6 /* No 6-bit DAC */ +# define KINETIS_NDAC12 2 /* Twp 12-bit DACs */ +# define KINETIS_NVREF 1 /* Voltage reference */ +# undef KINETIS_NTIMERS12 /* No 12 channel timers */ +# define KINETIS_NTIMERS20 4 /* Four 20 channel timers */ +# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ +# undef KINETIS_NTIMERS20 /* No 20 channel timers */ +# define KINETIS_NRTC 1 /* Real time clock */ +# undef KINETIS_NRNG /* No random number generator */ +# undef KINETIS_NMMCAU /* No hardware encryption */ +# undef KINETIS_NTAMPER /* No tamper detect */ +# define KINETIS_NCRC 1 /* CRC */ + +#elif defined(CONFIG_ARCH_CHIP_MK60N512VLQ100) +# undef KINETIS_K40 /* Not Kinetics K40 family */ +# define KINETIS_K60 1 /* Kinetis K60 family */ +# define KINETIS_FLASH_SIZE (512*1024) /* 512Kb */ +# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */ +# undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */ +# define KINETIS_SRAM_SIZE (128*1024) /* 128Kb */ +# define KINETIS_MPU 1 /* Memory protection unit */ +# define KINETIS_EXTBUS 1 /* External bus interface */ +# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ +# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */ +# define KINETIS_NUSBHOST 1 /* One USB host controller */ +# define KINETIS_NUSBOTG 1 /* With USB OTG controller */ +# define KINETIS_NUSBDEV 1 /* One USB device controller */ +# define KINETIS_NSDHC 1 /* SD host controller */ +# define KINETIS_NTOUCHIF 1 /* Xtrinsic touch sensing interface */ +# define KINETIS_NI2C 3 /* Three I2C modules */ +# define KINETIS_NISO7816 1 /* One UART with ISO-786 */ +# define KINETIS_NUART 5 /* Five additional UARTs */ +# define KINETIS_NSPI 3 /* Three SPI modules */ +# define KINETIS_NCAN 2 /* Two CAN controllers */ +# define KINETIS_NI2S 2 /* Two I2S modules */ +# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */ +# define KINETIS_NADC16 4 /* Four 16-bit ADC */ +# undef KINETIS_NADC12 /* No 12-channel ADC */ +# undef KINETIS_NADC13 /* No 13-channel ADC */ +# define KINETIS_NADC15 1 /* One 15-channel ADC (ADC0) */ +# define KINETIS_NADC18 1 /* One 18-channel ADC (ADC1) */ +# define KINETIS_NPGA 4 /* Four Programmable Gain Amplifiers */ +# define KINETIS_NCMP 3 /* Three analog comparators */ +# undef KINETIS_NDAC6 /* No 6-bit DAC */ +# define KINETIS_NDAC12 2 /* Twp 12-bit DACs */ +# define KINETIS_NVREF 1 /* Voltage reference */ +# undef KINETIS_NTIMERS12 /* No 12 channel timers */ +# define KINETIS_NTIMERS20 4 /* Four 20 channel timers */ +# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ +# undef KINETIS_NTIMERS20 /* No 20 channel timers */ +# define KINETIS_NRTC 1 /* Real time clock */ +# undef KINETIS_NRNG /* No random number generator */ +# undef KINETIS_NMMCAU /* No hardware encryption */ +# undef KINETIS_NTAMPER /* No tamper detect */ +# define KINETIS_NCRC 1 /* CRC */ + +#elif defined(CONFIG_ARCH_CHIP_MK60N256VMD100) +# undef KINETIS_K40 /* Not Kinetics K40 family */ +# define KINETIS_K60 1 /* Kinetis K60 family */ +# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */ +# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */ +# undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */ +# define KINETIS_SRAM_SIZE (64*1024) /* 64Kb */ +# define KINETIS_MPU 1 /* Memory protection unit */ +# define KINETIS_EXTBUS 1 /* External bus interface */ +# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ +# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */ +# define KINETIS_NUSBHOST 1 /* One USB host controller */ +# define KINETIS_NUSBOTG 1 /* With USB OTG controller */ +# define KINETIS_NUSBDEV 1 /* One USB device controller */ +# define KINETIS_NSDHC 1 /* SD host controller */ +# define KINETIS_NTOUCHIF 1 /* Xtrinsic touch sensing interface */ +# define KINETIS_NI2C 3 /* Three I2C modules */ +# define KINETIS_NISO7816 1 /* One UART with ISO-786 */ +# define KINETIS_NUART 5 /* Five additional UARTs */ +# define KINETIS_NSPI 3 /* Three SPI modules */ +# define KINETIS_NCAN 2 /* Two CAN controllers */ +# define KINETIS_NI2S 2 /* Two I2S modules */ +# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */ +# define KINETIS_NADC16 4 /* Four 16-bit ADC */ +# undef KINETIS_NADC12 /* No 12-channel ADC */ +# undef KINETIS_NADC13 /* No 13-channel ADC */ +# define KINETIS_NADC15 1 /* One 15-channel ADC (ADC0) */ +# define KINETIS_NADC18 1 /* One 18-channel ADC (ADC1) */ +# define KINETIS_NPGA 4 /* Four Programmable Gain Amplifiers */ +# define KINETIS_NCMP 3 /* Three analog comparators */ +# undef KINETIS_NDAC6 /* No 6-bit DAC */ +# define KINETIS_NDAC12 2 /* Twp 12-bit DACs */ +# define KINETIS_NVREF 1 /* Voltage reference */ +# undef KINETIS_NTIMERS12 /* No 12 channel timers */ +# define KINETIS_NTIMERS20 4 /* Four 20 channel timers */ +# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ +# undef KINETIS_NTIMERS20 /* No 20 channel timers */ +# define KINETIS_NRTC 1 /* Real time clock */ +# undef KINETIS_NRNG /* No random number generator */ +# undef KINETIS_NMMCAU /* No hardware encryption */ +# undef KINETIS_NTAMPER /* No tamper detect */ +# define KINETIS_NCRC 1 /* CRC */ + +#elif defined(CONFIG_ARCH_CHIP_MK60X256VMD100) +# undef KINETIS_K40 /* Not Kinetics K40 family */ +# define KINETIS_K60 1 /* Kinetis K60 family */ +# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */ +# define KINETIS_FLEXNVM_SIZE (256*1024) /* 256Kb */ +# define KINETIS_FLEXRAM_SIZE (4*1024) /* 4Kb */ +# define KINETIS_SRAM_SIZE (64*1024) /* 64Kb */ +# define KINETIS_MPU 1 /* Memory protection unit */ +# define KINETIS_EXTBUS 1 /* External bus interface */ +# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ +# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */ +# define KINETIS_NUSBHOST 1 /* One USB host controller */ +# define KINETIS_NUSBOTG 1 /* With USB OTG controller */ +# define KINETIS_NUSBDEV 1 /* One USB device controller */ +# define KINETIS_NSDHC 1 /* SD host controller */ +# define KINETIS_NTOUCHIF 1 /* Xtrinsic touch sensing interface */ +# define KINETIS_NI2C 3 /* Three I2C modules */ +# define KINETIS_NISO7816 1 /* One UART with ISO-786 */ +# define KINETIS_NUART 5 /* Five additional UARTs */ +# define KINETIS_NSPI 3 /* Three SPI modules */ +# define KINETIS_NCAN 2 /* Two CAN controllers */ +# define KINETIS_NI2S 2 /* Two I2S modules */ +# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */ +# define KINETIS_NADC16 4 /* Four 16-bit ADC */ +# undef KINETIS_NADC12 /* No 12-channel ADC */ +# undef KINETIS_NADC13 /* No 13-channel ADC */ +# define KINETIS_NADC15 1 /* One 15-channel ADC (ADC0) */ +# define KINETIS_NADC18 1 /* One 18-channel ADC (ADC1) */ +# define KINETIS_NPGA 4 /* Four Programmable Gain Amplifiers */ +# define KINETIS_NCMP 3 /* Three analog comparators */ +# undef KINETIS_NDAC6 /* No 6-bit DAC */ +# define KINETIS_NDAC12 2 /* Twp 12-bit DACs */ +# define KINETIS_NVREF 1 /* Voltage reference */ +# undef KINETIS_NTIMERS12 /* No 12 channel timers */ +# define KINETIS_NTIMERS20 4 /* Four 20 channel timers */ +# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ +# undef KINETIS_NTIMERS20 /* No 20 channel timers */ +# define KINETIS_NRTC 1 /* Real time clock */ +# undef KINETIS_NRNG /* No random number generator */ +# undef KINETIS_NMMCAU /* No hardware encryption */ +# undef KINETIS_NTAMPER /* No tamper detect */ +# define KINETIS_NCRC 1 /* CRC */ + +#elif defined(CONFIG_ARCH_CHIP_MK60N512VMD100) +# undef KINETIS_K40 /* Not Kinetics K40 family */ +# define KINETIS_K60 1 /* Kinetis K60 family */ +# define KINETIS_FLASH_SIZE (512*1024) /* 512Kb */ +# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */ +# undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */ +# define KINETIS_SRAM_SIZE (128*1024) /* 128Kb */ +# define KINETIS_MPU 1 /* Memory protection unit */ +# define KINETIS_EXTBUS 1 /* External bus interface */ +# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ +# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */ +# define KINETIS_NUSBHOST 1 /* One USB host controller */ +# define KINETIS_NUSBOTG 1 /* With USB OTG controller */ +# define KINETIS_NUSBDEV 1 /* One USB device controller */ +# define KINETIS_NSDHC 1 /* SD host controller */ +# define KINETIS_NTOUCHIF 1 /* Xtrinsic touch sensing interface */ +# define KINETIS_NI2C 3 /* Three I2C modules */ +# define KINETIS_NISO7816 1 /* One UART with ISO-786 */ +# define KINETIS_NUART 5 /* Five additional UARTs */ +# define KINETIS_NSPI 3 /* Three SPI modules */ +# define KINETIS_NCAN 2 /* Two CAN controllers */ +# define KINETIS_NI2S 2 /* Two I2S modules */ +# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */ +# define KINETIS_NADC16 4 /* Four 16-bit ADC */ +# undef KINETIS_NADC12 /* No 12-channel ADC */ +# undef KINETIS_NADC13 /* No 13-channel ADC */ +# define KINETIS_NADC15 1 /* One 15-channel ADC (ADC0) */ +# define KINETIS_NADC18 1 /* One 18-channel ADC (ADC1) */ +# define KINETIS_NPGA 4 /* Four Programmable Gain Amplifiers */ +# define KINETIS_NCMP 3 /* Three analog comparators */ +# undef KINETIS_NDAC6 /* No 6-bit DAC */ +# define KINETIS_NDAC12 2 /* Twp 12-bit DACs */ +# define KINETIS_NVREF 1 /* Voltage reference */ +# undef KINETIS_NTIMERS12 /* No 12 channel timers */ +# define KINETIS_NTIMERS20 4 /* Four 20 channel timers */ +# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ +# undef KINETIS_NTIMERS20 /* No 20 channel timers */ +# define KINETIS_NRTC 1 /* Real time clock */ +# undef KINETIS_NRNG /* No random number generator */ +# undef KINETIS_NMMCAU /* No hardware encryption */ +# undef KINETIS_NTAMPER /* No tamper detect */ +# define KINETIS_NCRC 1 /* CRC */ + +#else +# error "Unsupported Kinetis chip" +#endif + +/* NVIC priority levels *************************************************************/ +/* Each priority field holds a priority value, 0-15. The lower the value, the greater + * the priority of the corresponding interrupt. The processor implements only + * bits[7:4] of each field, bits[3:0] read as zero and ignore writes. + */ + +#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits[7:4] set is minimum priority */ +#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ +#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ +#define NVIC_SYSH_PRIORITY_STEP 0x10 /* Steps between supported priority values */ + +#define NVIC_SYSH_DISABLE_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP) +#define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_INCLUDE_KINETIS_CHIP_H */ diff --git a/nuttx/arch/arm/include/lm/chip.h b/nuttx/arch/arm/include/lm/chip.h index 8293c7938..6b49fe2ce 100644 --- a/nuttx/arch/arm/include/lm/chip.h +++ b/nuttx/arch/arm/include/lm/chip.h @@ -108,6 +108,20 @@ # error "Capabilities not specified for this Stellaris chip" #endif +/* The LM3S69xx only supports 8 priority levels. The hardware priority mechanism + * will only look at the upper N bits of the 8-bit priority level (where N is 3 for + * the Stellaris family), so any prioritization must be performed in those bits. + * The default priority level is set to the middle value + */ + +#define NVIC_SYSH_PRIORITY_MIN 0xe0 /* Bits [5:7] set in minimum priority */ +#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ +#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ +#define NVIC_SYSH_PRIORITY_STEP 0x20 /* Three bits of interrupt priority used */ + +#define NVIC_SYSH_DISABLE_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP) +#define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX + /************************************************************************************ * Public Types ************************************************************************************/ diff --git a/nuttx/arch/arm/include/lm/irq.h b/nuttx/arch/arm/include/lm/irq.h index 3b984a826..4f72e9824 100644 --- a/nuttx/arch/arm/include/lm/irq.h +++ b/nuttx/arch/arm/include/lm/irq.h @@ -43,6 +43,26 @@ #include <nuttx/config.h> #include <nuttx/irq.h> +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Processor Exceptions (vectors 0-15) */ + +#define LM_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG) */ + /* Vector 0: Reset stack pointer value */ + /* Vector 1: Reset (not handler as an IRQ) */ +#define LM_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ +#define LM_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ +#define LM_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */ +#define LM_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */ +#define LM_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */ +#define LM_IRQ_SVCALL (11) /* Vector 11: SVC call */ +#define LM_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */ + /* Vector 13: Reserved */ +#define LM_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ +#define LM_IRQ_SYSTICK (15) /* Vector 15: System tick */ + #if defined(CONFIG_ARCH_CHIP_LM3S) # include <arch/lm/lm3s_irq.h> #elif defined(CONFIG_ARCH_CHIP_LM4F) @@ -51,10 +71,6 @@ # error "Unsupported Stellaris IRQ file" #endif -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - /* GPIO IRQs -- Note that support for individual GPIO ports can * be disabled in order to reduce the size of the implemenation. */ diff --git a/nuttx/arch/arm/include/lm/lm3s_irq.h b/nuttx/arch/arm/include/lm/lm3s_irq.h index a9d0640d9..e9cfe8bdc 100644 --- a/nuttx/arch/arm/include/lm/lm3s_irq.h +++ b/nuttx/arch/arm/include/lm/lm3s_irq.h @@ -51,22 +51,6 @@ * to handle mapping tables. */ -/* Processor Exceptions (vectors 0-15) */ - -#define LM_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG) */ - /* Vector 0: Reset stack pointer value */ - /* Vector 1: Reset (not handler as an IRQ) */ -#define LM_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ -#define LM_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ -#define LM_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */ -#define LM_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */ -#define LM_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */ -#define LM_IRQ_SVCALL (11) /* Vector 11: SVC call */ -#define LM_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */ - /* Vector 13: Reserved */ -#define LM_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ -#define LM_IRQ_SYSTICK (15) /* Vector 15: System tick */ - /* External interrupts (vectors >= 16) */ #define LM_IRQ_INTERRUPTS (16) /* Vector number of the first external interrupt */ diff --git a/nuttx/arch/arm/include/lpc17xx/chip.h b/nuttx/arch/arm/include/lpc17xx/chip.h index d2c436d35..c22c6aa60 100644 --- a/nuttx/arch/arm/include/lpc17xx/chip.h +++ b/nuttx/arch/arm/include/lpc17xx/chip.h @@ -362,6 +362,20 @@ # error "Unsupported LPC17xx chip" #endif +/* NVIC priority levels *************************************************************/ +/* Each priority field holds a priority value, 0-31. The lower the value, the greater + * the priority of the corresponding interrupt. The processor implements only + * bits[7:3] of each field, bits[2:0] read as zero and ignore writes. + */ + +#define NVIC_SYSH_PRIORITY_MIN 0xf8 /* All bits[7:3] set is minimum priority */ +#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ +#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ +#define NVIC_SYSH_PRIORITY_STEP 0x08 /* Five bits of interrupt priority used */ + +#define NVIC_SYSH_DISABLE_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP) +#define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX + /************************************************************************************ * Public Types ************************************************************************************/ diff --git a/nuttx/arch/arm/include/lpc43xx/chip.h b/nuttx/arch/arm/include/lpc43xx/chip.h index 220ce38d0..7ff787e48 100644 --- a/nuttx/arch/arm/include/lpc43xx/chip.h +++ b/nuttx/arch/arm/include/lpc43xx/chip.h @@ -1,7 +1,7 @@ /************************************************************************************ * arch/arm/include/lpc43xx/chip.h * - * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2012-2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without @@ -542,6 +542,35 @@ # error "Unsupported LPC43xx chip" #endif +/* NVIC priority levels *************************************************************/ +/* Each priority field holds a priority value, 0-31. The lower the value, the greater + * the priority of the corresponding interrupt. + * + * The Cortex-M4 core supports up to 53 interrupts an 8 prgrammable interrupt + * priority levels; The Cortex-M0 core supports up to 32 interrupts with 4 + * programmable interrupt priorities. + */ + +#define LPC43M4_SYSH_PRIORITY_MIN 0xe0 /* All bits[7:5] set is minimum priority */ +#define LPC43M4_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ +#define LPC43M4_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ +#define LPC43M4_SYSH_PRIORITY_STEP 0x10 /* Steps between priorities */ + +#define LPC43M0_SYSH_PRIORITY_MIN 0xc0 /* All bits[7:6] set is minimum priority */ +#define LPC43M0_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ +#define LPC43M0_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ +#define LPC43M0_SYSH_PRIORITY_STEP 0x20 /* Steps between priorities */ + +/* Only the Cortex-M4 is supported by Nuttx */ + +#define NVIC_SYSH_PRIORITY_MIN LPC43M4_SYSH_PRIORITY_MIN +#define NVIC_SYSH_PRIORITY_DEFAULT LPC43M4_SYSH_PRIORITY_DEFAULT +#define NVIC_SYSH_PRIORITY_MAX LPC43M4_SYSH_PRIORITY_MAX +#define NVIC_SYSH_PRIORITY_STEP LPC43M4_SYSH_PRIORITY_INCR + +#define NVIC_SYSH_DISABLE_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP) +#define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX + /************************************************************************************ * Public Types ************************************************************************************/ diff --git a/nuttx/arch/arm/include/sam3u/chip.h b/nuttx/arch/arm/include/sam3u/chip.h new file mode 100644 index 000000000..da8c28345 --- /dev/null +++ b/nuttx/arch/arm/include/sam3u/chip.h @@ -0,0 +1,95 @@ +/************************************************************************************ + * arch/arm/include/sam3u/chip.h + * + * Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_SAM3U_CHIP_H +#define __ARCH_ARM_INCLUDE_SAM3U_CHIP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Get customizations for each supported chip */ + +#ifdef CONFIG_ARCH_CHIP_AT91SAM3U4E +/* Internal memory */ + +# define CONFIG_SAM3U_SRAM0_SIZE 0x00008000 /* 32Kb */ +# define CONFIG_SAM3U_SRAM1_SIZE 0x00004000 /* 16Kb */ +# define CONFIG_SAM3U_NFCSRAM_SIZE 0x00001000 /* 4Kb */ + +/* DMA */ + +# define CONFIG_SAM3U_NDMACHAN 4 /* 4 DMA Channels */ + +/* Memory card interface */ + +# define CONFIG_SAM3U_MCI2 1 +#else +# error "Unknown SAM3U chip type" +#endif + +/* NVIC priority levels *************************************************************/ +/* Each priority field holds a priority value, 0-15. The lower the value, the greater + * the priority of the corresponding interrupt. The processor implements only + * bits[7:4] of each field, bits[3:0] read as zero and ignore writes. + */ + +#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits[7:4] set is minimum priority */ +#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ +#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ +#define NVIC_SYSH_PRIORITY_STEP 0x10 /* Four bits of interrupt priority used */ + +#define NVIC_SYSH_DISABLE_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP) +#define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_INCLUDE_SAM3U_CHIP_H */ diff --git a/nuttx/arch/arm/include/stm32/chip.h b/nuttx/arch/arm/include/stm32/chip.h index b7ec7dbba..14d92ea3d 100644 --- a/nuttx/arch/arm/include/stm32/chip.h +++ b/nuttx/arch/arm/include/stm32/chip.h @@ -692,5 +692,15 @@ # error "Unsupported STM32 chip" #endif +/* NVIC priority levels *************************************************************/ + +#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits set in minimum priority */ +#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ +#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ +#define NVIC_SYSH_PRIORITY_STEP 0x10 /* Four bits of interrupt priority used */ + +#define NVIC_SYSH_DISABLE_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP) +#define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX + #endif /* __ARCH_ARM_INCLUDE_STM32_CHIP_H */ diff --git a/nuttx/arch/arm/src/armv7-m/up_hardfault.c b/nuttx/arch/arm/src/armv7-m/up_hardfault.c index c30015ad2..b043db3df 100644 --- a/nuttx/arch/arm/src/armv7-m/up_hardfault.c +++ b/nuttx/arch/arm/src/armv7-m/up_hardfault.c @@ -93,17 +93,16 @@ int up_hardfault(int irq, FAR void *context) { uint32_t *regs = (uint32_t*)context; - uint16_t *pc; - uint16_t insn; /* Get the value of the program counter where the fault occurred */ - pc = (uint16_t*)regs[REG_PC] - 1; +#ifndef CONFIG_ARMV7M_USEBASEPRI + uint16_t *pc = (uint16_t*)regs[REG_PC] - 1; if ((void*)pc >= (void*)&_stext && (void*)pc < (void*)&_etext) { /* Fetch the instruction that caused the Hard fault */ - insn = *pc; + uint16_t insn = *pc; hfdbg(" PC: %p INSN: %04x\n", pc, insn); /* If this was the instruction 'svc 0', then forward processing @@ -116,6 +115,7 @@ int up_hardfault(int irq, FAR void *context) return up_svcall(irq, context); } } +#endif /* Dump some hard fault info */ diff --git a/nuttx/arch/arm/src/kinetis/chip.h b/nuttx/arch/arm/src/kinetis/chip.h index 6ad781c20..0ed152bac 100644 --- a/nuttx/arch/arm/src/kinetis/chip.h +++ b/nuttx/arch/arm/src/kinetis/chip.h @@ -42,801 +42,16 @@ #include <nuttx/config.h> -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Get customizations for each supported chip */ - -#if defined(CONFIG_ARCH_CHIP_MK40X64VFX50) || defined(CONFIG_ARCH_CHIP_MK40X64VLH50) || \ - defined(CONFIG_ARCH_CHIP_MK40X64VLK50) || defined(CONFIG_ARCH_CHIP_MK40X64VMB50) -# define KINETIS_K40 1 /* Kinetics K40 family */ -# undef KINETIS_K60 /* Not Kinetis K60 family */ -# define KINETIS_FLASH_SIZE (64*1024) /* 64Kb */ -# define KINETIS_FLEXMEM_SIZE (32*1024) /* 32Kb */ -# define KINETIS_SRAM_SIZE (16*1024) /* 16Kb */ -# undef KINETIS_MPU /* No memory protection unit */ -# undef KINETIS_EXTBUS /* No external bus interface */ -# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ -# undef KINETIS_NENET /* No Ethernet controller */ -# define KINETIS_NUSBHOST 1 /* One USB host controller */ -# define KINETIS_NUSBOTG 1 /* With USB OTG controller */ -# define KINETIS_NUSBDEV 1 /* One USB device controller */ -# undef KINETIS_NSDHC /* No SD host controller */ -# undef KINETIS_NTOUCHIF /* Xtrinsic touch sensing interface */ -# define KINETIS_NI2C 2 /* Two I2C modules */ -# undef KINETIS_NISO7816 /* No UART with ISO-786 */ -# define KINETIS_NUART 6 /* Six UARTs */ -# define KINETIS_NSPI 3 /* Three SPI modules */ -# if defined(CONFIG_ARCH_CHIP_MK40X64VLK50) || defined(CONFIG_ARCH_CHIP_MK40X64VMB50) -# define KINETIS_NCAN 2 /* Two CAN controllers */ -# else -# undef KINETIS_NCAN /* No CAN in 64-pin chips */ -# endif -# define KINETIS_NI2S 1 /* One I2S module */ -# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 25x8/29x4) */ -# define KINETIS_NADC16 4 /* Four 16-bit ADC */ -# undef KINETIS_NADC12 /* No 12-channel ADC */ -# undef KINETIS_NADC13 /* No 13-channel ADC */ -# undef KINETIS_NADC15 /* No 15-channel ADC */ -# undef KINETIS_NADC18 /* No 18-channel ADC */ -# define KINETIS_NPGA 2 /* Two Programmable Gain Amplifiers */ -# define KINETIS_NCMP 3 /* Three analog comparators */ -# define KINETIS_NDAC6 3 /* Three 6-bit DAC */ -# define KINETIS_NDAC12 2 /* Two 12-bit DAC */ -# define KINETIS_NVREF 1 /* Voltage reference */ -# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ -# undef KINETIS_NTIMERS20 /* No 20 channel timers */ -# undef KINETIS_NRNG /* No random number generator */ -# define KINETIS_NRTC 1 /* Real time clock */ -# undef KINETIS_NMMCAU /* No hardware encryption */ -# undef KINETIS_NTAMPER /* No tamper detect */ -# define KINETIS_NCRC 1 /* CRC */ - -#elif defined(CONFIG_ARCH_CHIP_MK40X128VFX50) || defined(CONFIG_ARCH_CHIP_MK40X128VLH50) || \ - defined(CONFIG_ARCH_CHIP_MK40X128VLK50) || defined(CONFIG_ARCH_CHIP_MK40X128VMB50) || \ - defined(CONFIG_ARCH_CHIP_MK40X128VLL50) || defined(CONFIG_ARCH_CHIP_MK40X128VML50) || \ - defined(CONFIG_ARCH_CHIP_MK40X128VFX72) || defined(CONFIG_ARCH_CHIP_MK40X128VLH72) || \ - defined(CONFIG_ARCH_CHIP_MK40X128VLK72) || defined(CONFIG_ARCH_CHIP_MK40X128VMB72) || \ - defined(CONFIG_ARCH_CHIP_MK40X128VLL72) || defined(CONFIG_ARCH_CHIP_MK40X128VML72) -# define KINETIS_K40 1 /* Kinetics K40 family */ -# undef KINETIS_K60 /* Not Kinetis K60 family */ -# define KINETIS_FLASH_SIZE (128*1024) /* 128Kb */ -# define KINETIS_FLEXMEM_SIZE (32*1024) /* 32Kb */ -# define KINETIS_SRAM_SIZE (32*1024) /* 32Kb */ -# undef KINETIS_MPU /* No memory protection unit */ -# undef KINETIS_EXTBUS /* No external bus interface */ -# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ -# undef KINETIS_NENET /* No Ethernet controller */ -# define KINETIS_NUSBHOST 1 /* One USB host controller */ -# define KINETIS_NUSBOTG 1 /* With USB OTG controller */ -# define KINETIS_NUSBDEV 1 /* One USB device controller */ -# undef KINETIS_NSDHC /* No SD host controller */ -# undef KINETIS_NTOUCHIF /* Xtrinsic touch sensing interface */ -# define KINETIS_NI2C 2 /* Two I2C modules */ -# undef KINETIS_NISO7816 /* No UART with ISO-786 */ -# define KINETIS_NUART 6 /* Six UARTs */ -# define KINETIS_NSPI 3 /* Three SPI modules */ -# define KINETIS_NCAN 2 /* Two CAN controllers */ -# define KINETIS_NI2S 1 /* One I2S module */ -# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */ -# define KINETIS_NADC16 4 /* Four 16-bit ADC */ -# undef KINETIS_NADC12 /* No 12-channel ADC */ -# undef KINETIS_NADC13 /* No 13-channel ADC */ -# undef KINETIS_NADC15 /* No 15-channel ADC */ -# undef KINETIS_NADC18 /* No 18-channel ADC */ -# define KINETIS_NPGA 2 /* Two Programmable Gain Amplifiers */ -# define KINETIS_NCMP 3 /* Three analog comparators */ -# define KINETIS_NDAC6 3 /* Three 6-bit DAC */ -# define KINETIS_NDAC12 2 /* Two 12-bit DAC */ -# define KINETIS_NVREF 1 /* Voltage reference */ -# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ -# undef KINETIS_NTIMERS20 /* No 20 channel timers */ -# define KINETIS_NRTC 1 /* Real time clock */ -# undef KINETIS_NRNG /* No random number generator */ -# undef KINETIS_NMMCAU /* No hardware encryption */ -# undef KINETIS_NTAMPER /* No tamper detect */ -# define KINETIS_NCRC 1 /* CRC */ - -#elif defined(CONFIG_ARCH_CHIP_MK40X256VLK72) || defined(CONFIG_ARCH_CHIP_MK40X256VMB72) || \ - defined(CONFIG_ARCH_CHIP_MK40X256VLL72) || defined(CONFIG_ARCH_CHIP_MK40X256VML72) -# define KINETIS_K40 1 /* Kinetics K40 family */ -# undef KINETIS_K60 /* Not Kinetis K60 family */ -# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */ -# define KINETIS_FLEXMEM_SIZE (32*1024) /* 32Kb */ -# define KINETIS_SRAM_SIZE (32*1024) /* 64Kb */ -# undef KINETIS_MPU /* No memory protection unit */ -# undef KINETIS_EXTBUS /* No external bus interface */ -# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ -# undef KINETIS_NENET /* No Ethernet controller */ -# define KINETIS_NUSBHOST 1 /* One USB host controller */ -# define KINETIS_NUSBOTG 1 /* With USB OTG controller */ -# define KINETIS_NUSBDEV 1 /* One USB device controller */ -# undef KINETIS_NSDHC /* No SD host controller */ -# undef KINETIS_NTOUCHIF /* Xtrinsic touch sensing interface */ -# define KINETIS_NI2C 2 /* Two I2C modules */ -# undef KINETIS_NISO7816 /* No UART with ISO-786 */ -# define KINETIS_NUART 6 /* Six UARTs */ -# define KINETIS_NSPI 3 /* Three SPI modules */ -# define KINETIS_NCAN 2 /* Two CAN controllers */ -# define KINETIS_NI2S 1 /* One I2S module */ -# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */ -# define KINETIS_NADC16 4 /* Four 16-bit ADC */ -# undef KINETIS_NADC12 /* No 12-channel ADC */ -# undef KINETIS_NADC13 /* No 13-channel ADC */ -# undef KINETIS_NADC15 /* No 15-channel ADC */ -# undef KINETIS_NADC18 /* No 18-channel ADC */ -# define KINETIS_NPGA 2 /* Two Programmable Gain Amplifiers */ -# define KINETIS_NCMP 3 /* Three analog comparators */ -# define KINETIS_NDAC6 3 /* Three 6-bit DAC */ -# define KINETIS_NDAC12 2 /* Two 12-bit DAC */ -# define KINETIS_NVREF 1 /* Voltage reference */ -# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ -# undef KINETIS_NTIMERS20 /* No 20 channel timers */ -# define KINETIS_NRTC 1 /* Real time clock */ -# undef KINETIS_NRNG /* No random number generator */ -# undef KINETIS_NMMCAU /* No hardware encryption */ -# undef KINETIS_NTAMPER /* No tamper detect */ -# define KINETIS_NCRC 1 /* CRC */ - -#elif defined(CONFIG_ARCH_CHIP_MK40X128VLQ100) || defined(CONFIG_ARCH_CHIP_MK40X128VMD100) -# define KINETIS_K40 1 /* Kinetics K40 family */ -# undef KINETIS_K60 /* Not Kinetis K60 family */ -# define KINETIS_FLASH_SIZE (128*1024) /* 128Kb */ -# define KINETIS_FLEXMEM_SIZE (128*1024) /* 128Kb */ -# define KINETIS_SRAM_SIZE (32*1024) /* 32Kb */ -# define KINETIS_MPU 1 /* Memory protection unit */ -# define KINETIS_EXTBUS 1 /* External bus interface */ -# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ -# undef KINETIS_NENET /* No Ethernet controller */ -# define KINETIS_NUSBHOST 1 /* One USB host controller */ -# define KINETIS_NUSBOTG 1 /* With USB OTG controller */ -# define KINETIS_NUSBDEV 1 /* One USB device controller */ -# define KINETIS_NSDHC 1 /* One SD host controller */ -# undef KINETIS_NTOUCHIF /* Xtrinsic touch sensing interface */ -# define KINETIS_NI2C 2 /* Two I2C modules */ -# undef KINETIS_NISO7816 /* No UART with ISO-786 */ -# define KINETIS_NUART 6 /* Six UARTs */ -# define KINETIS_NSPI 3 /* Three SPI modules */ -# define KINETIS_NCAN 2 /* Two CAN controllers */ -# define KINETIS_NI2S 1 /* One I2S module */ -# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 40x8/44x4)*/ -# define KINETIS_NADC16 4 /* Four 16-bit ADC */ -# undef KINETIS_NADC12 /* No 12-channel ADC */ -# undef KINETIS_NADC13 /* No 13-channel ADC */ -# undef KINETIS_NADC15 /* No 15-channel ADC */ -# undef KINETIS_NADC18 /* No 18-channel ADC */ -# define KINETIS_NPGA 2 /* Two Programmable Gain Amplifiers */ -# define KINETIS_NCMP 3 /* Three analog comparators */ -# define KINETIS_NDAC6 3 /* Three 6-bit DAC */ -# define KINETIS_NDAC12 2 /* Two 12-bit DAC */ -# define KINETIS_NVREF 1 /* Voltage reference */ -# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ -# undef KINETIS_NTIMERS20 /* No 20 channel timers */ -# define KINETIS_NRTC 1 /* Real time clock */ -# undef KINETIS_NRNG /* No random number generator */ -# undef KINETIS_NMMCAU /* No hardware encryption */ -# undef KINETIS_NTAMPER /* No tamper detect */ -# define KINETIS_NCRC 1 /* CRC */ - -#elif defined(CONFIG_ARCH_CHIP_MK40X256VLQ100) || defined(CONFIG_ARCH_CHIP_MK40X256VMD100) -# define KINETIS_K40 1 /* Kinetics K40 family */ -# undef KINETIS_K60 /* Not Kinetis K60 family */ -# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */ -# define KINETIS_FLEXMEM_SIZE (256*1024) /* 256Kb */ -# define KINETIS_SRAM_SIZE (64*1024) /* 32Kb */ -# define KINETIS_MPU 1 /* Memory protection unit */ -# define KINETIS_EXTBUS 1 /* External bus interface */ -# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ -# undef KINETIS_NENET /* No Ethernet controller */ -# define KINETIS_NUSBHOST 1 /* One USB host controller */ -# define KINETIS_NUSBOTG 1 /* With USB OTG controller */ -# define KINETIS_NUSBDEV 1 /* One USB device controller */ -# define KINETIS_NSDHC 1 /* One SD host controller */ -# undef KINETIS_NTOUCHIF /* Xtrinsic touch sensing interface */ -# define KINETIS_NI2C 2 /* Two I2C modules */ -# undef KINETIS_NISO7816 /* No UART with ISO-786 */ -# define KINETIS_NUART 6 /* Six UARTs */ -# define KINETIS_NSPI 3 /* Three SPI modules */ -# define KINETIS_NCAN 2 /* Two CAN controllers */ -# define KINETIS_NI2S 1 /* One I2S module */ -# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 40x8/44x4)*/ -# define KINETIS_NADC16 4 /* Four 16-bit ADC */ -# undef KINETIS_NADC12 /* No 12-channel ADC */ -# undef KINETIS_NADC13 /* No 13-channel ADC */ -# undef KINETIS_NADC15 /* No 15-channel ADC */ -# undef KINETIS_NADC18 /* No 18-channel ADC */ -# define KINETIS_NPGA 2 /* Two Programmable Gain Amplifiers */ -# define KINETIS_NCMP 3 /* Three analog comparators */ -# define KINETIS_NDAC6 3 /* Three 6-bit DAC */ -# define KINETIS_NDAC12 2 /* Two 12-bit DAC */ -# define KINETIS_NVREF 1 /* Voltage reference */ -# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ -# undef KINETIS_NTIMERS20 /* No 20 channel timers */ -# define KINETIS_NRTC 1 /* Real time clock */ -# undef KINETIS_NRNG /* No random number generator */ -# undef KINETIS_NMMCAU /* No hardware encryption */ -# undef KINETIS_NTAMPER /* No tamper detect */ -# define KINETIS_NCRC 1 /* CRC */ - -#elif defined(CONFIG_ARCH_CHIP_MK40N512VLK100) || defined(CONFIG_ARCH_CHIP_MK40N512VMB100) || \ - defined(CONFIG_ARCH_CHIP_MK40N512VLL100) || defined(CONFIG_ARCH_CHIP_MK40N512VML100) || \ - defined(CONFIG_ARCH_CHIP_MK40N512VLQ100) || defined(CONFIG_ARCH_CHIP_MK40N512VMD100) -# define KINETIS_K40 1 /* Kinetics K40 family */ -# undef KINETIS_K60 /* Not Kinetis K60 family */ -# define KINETIS_FLASH_SIZE (512*1024) /* 512Kb */ -# undef KINETIS_FLEXMEM_SIZE /* No FlexMemory */ -# define KINETIS_SRAM_SIZE (128*1024) /* 128Kb */ -# define KINETIS_MPU 1 /* Memory protection unit */ -# define KINETIS_EXTBUS 1 /* External bus interface */ -# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ -# undef KINETIS_NENET /* No Ethernet controller */ -# define KINETIS_NUSBHOST 1 /* One USB host controller */ -# define KINETIS_NUSBOTG 1 /* With USB OTG controller */ -# define KINETIS_NUSBDEV 1 /* One USB device controller */ -# define KINETIS_NSDHC 1 /* One SD host controller */ -# undef KINETIS_NTOUCHIF /* Xtrinsic touch sensing interface */ -# define KINETIS_NI2C 2 /* Two I2C modules */ -# undef KINETIS_NISO7816 /* No UART with ISO-786 */ -# define KINETIS_NUART 6 /* Six UARTs */ -# define KINETIS_NSPI 3 /* Three SPI modules */ -# define KINETIS_NCAN 2 /* Two CAN controllers */ -# define KINETIS_NI2S 1 /* One I2S module */ -# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 40x8/44x4)*/ -# define KINETIS_NADC16 4 /* Four 16-bit ADC */ -# undef KINETIS_NADC12 /* No 12-channel ADC */ -# undef KINETIS_NADC13 /* No 13-channel ADC */ -# undef KINETIS_NADC15 /* No 15-channel ADC */ -# undef KINETIS_NADC18 /* No 18-channel ADC */ -# define KINETIS_NPGA 2 /* Two Programmable Gain Amplifiers */ -# define KINETIS_NCMP 3 /* Three analog comparators */ -# define KINETIS_NDAC6 3 /* Three 6-bit DAC */ -# define KINETIS_NDAC12 2 /* Two 12-bit DAC */ -# define KINETIS_NVREF 1 /* Voltage reference */ -# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ -# undef KINETIS_NTIMERS20 /* No 20 channel timers */ -# define KINETIS_NRTC 1 /* Real time clock */ -# undef KINETIS_NRNG /* No random number generator */ -# undef KINETIS_NMMCAU /* No hardware encryption */ -# undef KINETIS_NTAMPER /* No tamper detect */ -# define KINETIS_NCRC 1 /* CRC */ - -#elif defined(CONFIG_ARCH_CHIP_MK60N256VLL100) -# undef KINETIS_K40 /* Not Kinetics K40 family */ -# define KINETIS_K60 1 /* Kinetis K60 family */ -# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */ -# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */ -# undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */ -# define KINETIS_SRAM_SIZE (64*1024) /* 64Kb */ -# define KINETIS_MPU 1 /* Memory protection unit */ -# define KINETIS_EXTBUS 1 /* External bus interface */ -# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ -# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */ -# define KINETIS_NUSBHOST 1 /* One USB host controller */ -# define KINETIS_NUSBOTG 1 /* With USB OTG controller */ -# define KINETIS_NUSBDEV 1 /* One USB device controller */ -# define KINETIS_NSDHC 1 /* SD host controller */ -# define KINETIS_NTOUCHIF 1 /* Xtrinsic touch sensing interface */ -# define KINETIS_NI2C 3 /* Three I2C modules */ -# define KINETIS_NISO7816 1 /* One UART with ISO-786 */ -# define KINETIS_NUART 4 /* Four additional UARTs */ -# define KINETIS_NSPI 3 /* Three SPI modules */ -# define KINETIS_NCAN 2 /* Two CAN controllers */ -# define KINETIS_NI2S 2 /* Two I2S modules */ -# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */ -# define KINETIS_NADC16 4 /* Four 16-bit ADC */ -# define KINETIS_NADC12 1 /* One 12-channel ADC (ADC0)*/ -# define KINETIS_NADC13 1 /* No 13-channel ADC (ADC1) */ -# undef KINETIS_NADC15 /* No 15-channel ADC */ -# undef KINETIS_NADC18 /* No 18-channel ADC */ -# define KINETIS_NPGA 4 /* Four Programmable Gain Amplifiers */ -# define KINETIS_NCMP 3 /* Three analog comparators */ -# undef KINETIS_NDAC6 /* No 6-bit DAC */ -# define KINETIS_NDAC12 1 /* One 12-bit DAC */ -# define KINETIS_NVREF 1 /* Voltage reference */ -# undef KINETIS_NTIMERS12 /* No 12 channel timers */ -# define KINETIS_NTIMERS20 4 /* Four 20 channel timers */ -# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ -# undef KINETIS_NTIMERS20 /* No 20 channel timers */ -# define KINETIS_NRTC 1 /* Real time clock */ -# undef KINETIS_NRNG /* No random number generator */ -# undef KINETIS_NMMCAU /* No hardware encryption */ -# undef KINETIS_NTAMPER /* No tamper detect */ -# define KINETIS_NCRC 1 /* CRC */ - -#elif defined(CONFIG_ARCH_CHIP_MK60X256VLL100) -# undef KINETIS_K40 /* Not Kinetics K40 family */ -# define KINETIS_K60 1 /* Kinetis K60 family */ -# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */ -# define KINETIS_FLEXNVM_SIZE (256*1024) /* 256Kb */ -# define KINETIS_FLEXRAM_SIZE (4*1024) /* 32Kb */ -# define KINETIS_SRAM_SIZE (64*1024) /* 64Kb */ -# define KINETIS_MPU 1 /* Memory protection unit */ -# define KINETIS_EXTBUS 1 /* External bus interface */ -# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ -# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */ -# define KINETIS_NUSBHOST 1 /* One USB host controller */ -# define KINETIS_NUSBOTG 1 /* With USB OTG controller */ -# define KINETIS_NUSBDEV 1 /* One USB device controller */ -# define KINETIS_NSDHC 1 /* SD host controller */ -# define KINETIS_NTOUCHIF 1 /* Xtrinsic touch sensing interface */ -# define KINETIS_NI2C 3 /* Three I2C modules */ -# define KINETIS_NISO7816 1 /* One UART with ISO-786 */ -# define KINETIS_NUART 4 /* Four additional UARTs */ -# define KINETIS_NSPI 3 /* Three SPI modules */ -# define KINETIS_NCAN 2 /* Two CAN controllers */ -# define KINETIS_NI2S 2 /* Two I2S modules */ -# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */ -# define KINETIS_NADC16 4 /* Four 16-bit ADC */ -# define KINETIS_NADC12 1 /* One 12-channel ADC (ADC0)*/ -# define KINETIS_NADC13 1 /* No 13-channel ADC (ADC1) */ -# undef KINETIS_NADC15 /* No 15-channel ADC */ -# undef KINETIS_NADC18 /* No 18-channel ADC */ -# define KINETIS_NPGA 4 /* Four Programmable Gain Amplifiers */ -# define KINETIS_NCMP 3 /* Three analog comparators */ -# undef KINETIS_NDAC6 /* No 6-bit DAC */ -# define KINETIS_NDAC12 1 /* One 12-bit DAC */ -# define KINETIS_NVREF 1 /* Voltage reference */ -# undef KINETIS_NTIMERS12 /* No 12 channel timers */ -# define KINETIS_NTIMERS20 4 /* Four 20 channel timers */ -# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ -# undef KINETIS_NTIMERS20 /* No 20 channel timers */ -# define KINETIS_NRTC 1 /* Real time clock */ -# undef KINETIS_NRNG /* No random number generator */ -# undef KINETIS_NMMCAU /* No hardware encryption */ -# undef KINETIS_NTAMPER /* No tamper detect */ -# define KINETIS_NCRC 1 /* CRC */ - -#elif defined(CONFIG_ARCH_CHIP_MK60N512VLL100) -# undef KINETIS_K40 /* Not Kinetics K40 family */ -# define KINETIS_K60 1 /* Kinetis K60 family */ -# define KINETIS_FLASH_SIZE (512*1024) /* 256Kb */ -# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */ -# undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */ -# define KINETIS_SRAM_SIZE (128*1024) /* 128Kb */ -# define KINETIS_MPU 1 /* Memory protection unit */ -# define KINETIS_EXTBUS 1 /* External bus interface */ -# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ -# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */ -# define KINETIS_NUSBHOST 1 /* One USB host controller */ -# define KINETIS_NUSBOTG 1 /* With USB OTG controller */ -# define KINETIS_NUSBDEV 1 /* One USB device controller */ -# define KINETIS_NSDHC 1 /* SD host controller */ -# define KINETIS_NTOUCHIF 1 /* Xtrinsic touch sensing interface */ -# define KINETIS_NI2C 3 /* Three I2C modules */ -# define KINETIS_NISO7816 1 /* One UART with ISO-786 */ -# define KINETIS_NUART 4 /* Four additional UARTs */ -# define KINETIS_NSPI 3 /* Three SPI modules */ -# define KINETIS_NCAN 2 /* Two CAN controllers */ -# define KINETIS_NI2S 2 /* Two I2S modules */ -# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */ -# define KINETIS_NADC16 4 /* Four 16-bit ADC */ -# define KINETIS_NADC12 1 /* One 12-channel ADC (ADC0)*/ -# define KINETIS_NADC13 1 /* No 13-channel ADC (ADC1) */ -# undef KINETIS_NADC15 /* No 15-channel ADC */ -# undef KINETIS_NADC18 /* No 18-channel ADC */ -# define KINETIS_NPGA 4 /* Four Programmable Gain Amplifiers */ -# define KINETIS_NCMP 3 /* Three analog comparators */ -# undef KINETIS_NDAC6 /* No 6-bit DAC */ -# define KINETIS_NDAC12 1 /* One 12-bit DAC */ -# define KINETIS_NVREF 1 /* Voltage reference */ -# undef KINETIS_NTIMERS12 /* No 12 channel timers */ -# define KINETIS_NTIMERS20 4 /* Four 20 channel timers */ -# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ -# undef KINETIS_NTIMERS20 /* No 20 channel timers */ -# define KINETIS_NRTC 1 /* Real time clock */ -# undef KINETIS_NRNG /* No random number generator */ -# undef KINETIS_NMMCAU /* No hardware encryption */ -# undef KINETIS_NTAMPER /* No tamper detect */ -# define KINETIS_NCRC 1 /* CRC */ - -#elif defined(CONFIG_ARCH_CHIP_MK60N256VML100) -# undef KINETIS_K40 /* Not Kinetics K40 family */ -# define KINETIS_K60 1 /* Kinetis K60 family */ -# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */ -# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */ -# undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */ -# define KINETIS_SRAM_SIZE (64*1024) /* 64Kb */ -# define KINETIS_MPU 1 /* Memory protection unit */ -# define KINETIS_EXTBUS 1 /* External bus interface */ -# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ -# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */ -# define KINETIS_NUSBHOST 1 /* One USB host controller */ -# define KINETIS_NUSBOTG 1 /* With USB OTG controller */ -# define KINETIS_NUSBDEV 1 /* One USB device controller */ -# define KINETIS_NSDHC 1 /* SD host controller */ -# define KINETIS_NTOUCHIF 1 /* Xtrinsic touch sensing interface */ -# define KINETIS_NI2C 3 /* Three I2C modules */ -# define KINETIS_NISO7816 1 /* One UART with ISO-786 */ -# define KINETIS_NUART 4 /* Four additional UARTs */ -# define KINETIS_NSPI 3 /* Three SPI modules */ -# define KINETIS_NCAN 2 /* Two CAN controllers */ -# define KINETIS_NI2S 2 /* Two I2S modules */ -# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */ -# define KINETIS_NADC16 4 /* Four 16-bit ADC */ -# define KINETIS_NADC12 1 /* One 12-channel ADC (ADC0)*/ -# undef KINETIS_NADC13 /* No 13-channel ADC */ -# define KINETIS_NADC15 1 /* One 15-channel ADC (ADC1) */ -# undef KINETIS_NADC18 /* No 18-channel ADC */ -# define KINETIS_NPGA 4 /* Four Programmable Gain Amplifiers */ -# define KINETIS_NCMP 3 /* Three analog comparators */ -# undef KINETIS_NDAC6 /* No 6-bit DAC */ -# define KINETIS_NDAC12 1 /* One 12-bit DAC */ -# define KINETIS_NVREF 1 /* Voltage reference */ -# undef KINETIS_NTIMERS12 /* No 12 channel timers */ -# define KINETIS_NTIMERS20 4 /* Four 20 channel timers */ -# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ -# undef KINETIS_NTIMERS20 /* No 20 channel timers */ -# define KINETIS_NRTC 1 /* Real time clock */ -# undef KINETIS_NRNG /* No random number generator */ -# undef KINETIS_NMMCAU /* No hardware encryption */ -# undef KINETIS_NTAMPER /* No tamper detect */ -# define KINETIS_NCRC 1 /* CRC */ - -#elif defined(CONFIG_ARCH_CHIP_MK60X256VML100) -# undef KINETIS_K40 /* Not Kinetics K40 family */ -# define KINETIS_K60 1 /* Kinetis K60 family */ -# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */ -# define KINETIS_FLEXNVM_SIZE (256*1024) /* 256Kb */ -# define KINETIS_FLEXRAM_SIZE (4*1024) /* 4Kb */ -# define KINETIS_SRAM_SIZE (64*1024) /* 64Kb */ -# define KINETIS_MPU 1 /* Memory protection unit */ -# define KINETIS_EXTBUS 1 /* External bus interface */ -# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ -# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */ -# define KINETIS_NUSBHOST 1 /* One USB host controller */ -# define KINETIS_NUSBOTG 1 /* With USB OTG controller */ -# define KINETIS_NUSBDEV 1 /* One USB device controller */ -# define KINETIS_NSDHC 1 /* SD host controller */ -# define KINETIS_NTOUCHIF 1 /* Xtrinsic touch sensing interface */ -# define KINETIS_NI2C 3 /* Three I2C modules */ -# define KINETIS_NISO7816 1 /* One UART with ISO-786 */ -# define KINETIS_NUART 4 /* Four additional UARTs */ -# define KINETIS_NSPI 3 /* Three SPI modules */ -# define KINETIS_NCAN 2 /* Two CAN controllers */ -# define KINETIS_NI2S 2 /* Two I2S modules */ -# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */ -# define KINETIS_NADC16 4 /* Four 16-bit ADC */ -# define KINETIS_NADC12 1 /* One 12-channel ADC (ADC0)*/ -# undef KINETIS_NADC13 /* No 13-channel ADC */ -# define KINETIS_NADC15 1 /* One 15-channel ADC (ADC1) */ -# undef KINETIS_NADC18 /* No 18-channel ADC */ -# define KINETIS_NPGA 4 /* Four Programmable Gain Amplifiers */ -# define KINETIS_NCMP 3 /* Three analog comparators */ -# undef KINETIS_NDAC6 /* No 6-bit DAC */ -# define KINETIS_NDAC12 1 /* One 12-bit DAC */ -# define KINETIS_NVREF 1 /* Voltage reference */ -# undef KINETIS_NTIMERS12 /* No 12 channel timers */ -# define KINETIS_NTIMERS20 4 /* Four 20 channel timers */ -# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ -# undef KINETIS_NTIMERS20 /* No 20 channel timers */ -# define KINETIS_NRTC 1 /* Real time clock */ -# undef KINETIS_NRNG /* No random number generator */ -# undef KINETIS_NMMCAU /* No hardware encryption */ -# undef KINETIS_NTAMPER /* No tamper detect */ -# define KINETIS_NCRC 1 /* CRC */ - -#elif defined(CONFIG_ARCH_CHIP_MK60N512VML100) -# undef KINETIS_K40 /* Not Kinetics K40 family */ -# define KINETIS_K60 1 /* Kinetis K60 family */ -# define KINETIS_FLASH_SIZE (512*1024) /* 256Kb */ -# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */ -# undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */ -# define KINETIS_SRAM_SIZE (128*1024) /* 128Kb */ -# define KINETIS_MPU 1 /* Memory protection unit */ -# define KINETIS_EXTBUS 1 /* External bus interface */ -# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ -# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */ -# define KINETIS_NUSBHOST 1 /* One USB host controller */ -# define KINETIS_NUSBOTG 1 /* With USB OTG controller */ -# define KINETIS_NUSBDEV 1 /* One USB device controller */ -# define KINETIS_NSDHC 1 /* SD host controller */ -# define KINETIS_NTOUCHIF 1 /* Xtrinsic touch sensing interface */ -# define KINETIS_NI2C 3 /* Three I2C modules */ -# define KINETIS_NISO7816 1 /* One UART with ISO-786 */ -# define KINETIS_NUART 4 /* Four additional UARTs */ -# define KINETIS_NSPI 3 /* Three SPI modules */ -# define KINETIS_NCAN 2 /* Two CAN controllers */ -# define KINETIS_NI2S 2 /* Two I2S modules */ -# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */ -# define KINETIS_NADC16 4 /* Four 16-bit ADC */ -# define KINETIS_NADC12 1 /* One 12-channel ADC (ADC0)*/ -# undef KINETIS_NADC13 /* No 13-channel ADC */ -# define KINETIS_NADC15 1 /* One 15-channel ADC (ADC1) */ -# undef KINETIS_NADC18 /* No 18-channel ADC */ -# define KINETIS_NPGA 4 /* Four Programmable Gain Amplifiers */ -# define KINETIS_NCMP 3 /* Three analog comparators */ -# undef KINETIS_NDAC6 /* No 6-bit DAC */ -# define KINETIS_NDAC12 1 /* One 12-bit DAC */ -# define KINETIS_NVREF 1 /* Voltage reference */ -# undef KINETIS_NTIMERS12 /* No 12 channel timers */ -# define KINETIS_NTIMERS20 4 /* Four 20 channel timers */ -# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ -# undef KINETIS_NTIMERS20 /* No 20 channel timers */ -# define KINETIS_NRTC 1 /* Real time clock */ -# undef KINETIS_NRNG /* No random number generator */ -# undef KINETIS_NMMCAU /* No hardware encryption */ -# undef KINETIS_NTAMPER /* No tamper detect */ -# define KINETIS_NCRC 1 /* CRC */ - -#elif defined(CONFIG_ARCH_CHIP_MK60N256VLQ100) -# undef KINETIS_K40 /* Not Kinetics K40 family */ -# define KINETIS_K60 1 /* Kinetis K60 family */ -# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */ -# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */ -# undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */ -# define KINETIS_SRAM_SIZE (64*1024) /* 64Kb */ -# define KINETIS_MPU 1 /* Memory protection unit */ -# define KINETIS_EXTBUS 1 /* External bus interface */ -# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ -# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */ -# define KINETIS_NUSBHOST 1 /* One USB host controller */ -# define KINETIS_NUSBOTG 1 /* With USB OTG controller */ -# define KINETIS_NUSBDEV 1 /* One USB device controller */ -# define KINETIS_NSDHC 1 /* SD host controller */ -# define KINETIS_NTOUCHIF 1 /* Xtrinsic touch sensing interface */ -# define KINETIS_NI2C 3 /* Three I2C modules */ -# define KINETIS_NISO7816 1 /* One UART with ISO-786 */ -# define KINETIS_NUART 5 /* Five additional UARTs */ -# define KINETIS_NSPI 3 /* Three SPI modules */ -# define KINETIS_NCAN 2 /* Two CAN controllers */ -# define KINETIS_NI2S 2 /* Two I2S modules */ -# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */ -# define KINETIS_NADC16 4 /* Four 16-bit ADC */ -# undef KINETIS_NADC12 /* No 12-channel ADC */ -# undef KINETIS_NADC13 /* No 13-channel ADC */ -# define KINETIS_NADC15 1 /* One 15-channel ADC (ADC0) */ -# define KINETIS_NADC18 1 /* One 18-channel ADC (ADC1) */ -# define KINETIS_NPGA 4 /* Four Programmable Gain Amplifiers */ -# define KINETIS_NCMP 3 /* Three analog comparators */ -# undef KINETIS_NDAC6 /* No 6-bit DAC */ -# define KINETIS_NDAC12 2 /* Twp 12-bit DACs */ -# define KINETIS_NVREF 1 /* Voltage reference */ -# undef KINETIS_NTIMERS12 /* No 12 channel timers */ -# define KINETIS_NTIMERS20 4 /* Four 20 channel timers */ -# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ -# undef KINETIS_NTIMERS20 /* No 20 channel timers */ -# define KINETIS_NRTC 1 /* Real time clock */ -# undef KINETIS_NRNG /* No random number generator */ -# undef KINETIS_NMMCAU /* No hardware encryption */ -# undef KINETIS_NTAMPER /* No tamper detect */ -# define KINETIS_NCRC 1 /* CRC */ - -#elif defined(CONFIG_ARCH_CHIP_MK60X256VLQ100) -# undef KINETIS_K40 /* Not Kinetics K40 family */ -# define KINETIS_K60 1 /* Kinetis K60 family */ -# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */ -# define KINETIS_FLEXNVM_SIZE (256*1024) /* 256Kb */ -# define KINETIS_FLEXRAM_SIZE (4*1024) /* 4Kb */ -# define KINETIS_SRAM_SIZE (64*1024) /* 64Kb */ -# define KINETIS_MPU 1 /* Memory protection unit */ -# define KINETIS_EXTBUS 1 /* External bus interface */ -# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ -# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */ -# define KINETIS_NUSBHOST 1 /* One USB host controller */ -# define KINETIS_NUSBOTG 1 /* With USB OTG controller */ -# define KINETIS_NUSBDEV 1 /* One USB device controller */ -# define KINETIS_NSDHC 1 /* SD host controller */ -# define KINETIS_NTOUCHIF 1 /* Xtrinsic touch sensing interface */ -# define KINETIS_NI2C 3 /* Three I2C modules */ -# define KINETIS_NISO7816 1 /* One UART with ISO-786 */ -# define KINETIS_NUART 5 /* Five additional UARTs */ -# define KINETIS_NSPI 3 /* Three SPI modules */ -# define KINETIS_NCAN 2 /* Two CAN controllers */ -# define KINETIS_NI2S 2 /* Two I2S modules */ -# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */ -# define KINETIS_NADC16 4 /* Four 16-bit ADC */ -# undef KINETIS_NADC12 /* No 12-channel ADC */ -# undef KINETIS_NADC13 /* No 13-channel ADC */ -# define KINETIS_NADC15 1 /* One 15-channel ADC (ADC0) */ -# define KINETIS_NADC18 1 /* One 18-channel ADC (ADC1) */ -# define KINETIS_NPGA 4 /* Four Programmable Gain Amplifiers */ -# define KINETIS_NCMP 3 /* Three analog comparators */ -# undef KINETIS_NDAC6 /* No 6-bit DAC */ -# define KINETIS_NDAC12 2 /* Twp 12-bit DACs */ -# define KINETIS_NVREF 1 /* Voltage reference */ -# undef KINETIS_NTIMERS12 /* No 12 channel timers */ -# define KINETIS_NTIMERS20 4 /* Four 20 channel timers */ -# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ -# undef KINETIS_NTIMERS20 /* No 20 channel timers */ -# define KINETIS_NRTC 1 /* Real time clock */ -# undef KINETIS_NRNG /* No random number generator */ -# undef KINETIS_NMMCAU /* No hardware encryption */ -# undef KINETIS_NTAMPER /* No tamper detect */ -# define KINETIS_NCRC 1 /* CRC */ - -#elif defined(CONFIG_ARCH_CHIP_MK60N512VLQ100) -# undef KINETIS_K40 /* Not Kinetics K40 family */ -# define KINETIS_K60 1 /* Kinetis K60 family */ -# define KINETIS_FLASH_SIZE (512*1024) /* 512Kb */ -# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */ -# undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */ -# define KINETIS_SRAM_SIZE (128*1024) /* 128Kb */ -# define KINETIS_MPU 1 /* Memory protection unit */ -# define KINETIS_EXTBUS 1 /* External bus interface */ -# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ -# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */ -# define KINETIS_NUSBHOST 1 /* One USB host controller */ -# define KINETIS_NUSBOTG 1 /* With USB OTG controller */ -# define KINETIS_NUSBDEV 1 /* One USB device controller */ -# define KINETIS_NSDHC 1 /* SD host controller */ -# define KINETIS_NTOUCHIF 1 /* Xtrinsic touch sensing interface */ -# define KINETIS_NI2C 3 /* Three I2C modules */ -# define KINETIS_NISO7816 1 /* One UART with ISO-786 */ -# define KINETIS_NUART 5 /* Five additional UARTs */ -# define KINETIS_NSPI 3 /* Three SPI modules */ -# define KINETIS_NCAN 2 /* Two CAN controllers */ -# define KINETIS_NI2S 2 /* Two I2S modules */ -# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */ -# define KINETIS_NADC16 4 /* Four 16-bit ADC */ -# undef KINETIS_NADC12 /* No 12-channel ADC */ -# undef KINETIS_NADC13 /* No 13-channel ADC */ -# define KINETIS_NADC15 1 /* One 15-channel ADC (ADC0) */ -# define KINETIS_NADC18 1 /* One 18-channel ADC (ADC1) */ -# define KINETIS_NPGA 4 /* Four Programmable Gain Amplifiers */ -# define KINETIS_NCMP 3 /* Three analog comparators */ -# undef KINETIS_NDAC6 /* No 6-bit DAC */ -# define KINETIS_NDAC12 2 /* Twp 12-bit DACs */ -# define KINETIS_NVREF 1 /* Voltage reference */ -# undef KINETIS_NTIMERS12 /* No 12 channel timers */ -# define KINETIS_NTIMERS20 4 /* Four 20 channel timers */ -# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ -# undef KINETIS_NTIMERS20 /* No 20 channel timers */ -# define KINETIS_NRTC 1 /* Real time clock */ -# undef KINETIS_NRNG /* No random number generator */ -# undef KINETIS_NMMCAU /* No hardware encryption */ -# undef KINETIS_NTAMPER /* No tamper detect */ -# define KINETIS_NCRC 1 /* CRC */ - -#elif defined(CONFIG_ARCH_CHIP_MK60N256VMD100) -# undef KINETIS_K40 /* Not Kinetics K40 family */ -# define KINETIS_K60 1 /* Kinetis K60 family */ -# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */ -# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */ -# undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */ -# define KINETIS_SRAM_SIZE (64*1024) /* 64Kb */ -# define KINETIS_MPU 1 /* Memory protection unit */ -# define KINETIS_EXTBUS 1 /* External bus interface */ -# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ -# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */ -# define KINETIS_NUSBHOST 1 /* One USB host controller */ -# define KINETIS_NUSBOTG 1 /* With USB OTG controller */ -# define KINETIS_NUSBDEV 1 /* One USB device controller */ -# define KINETIS_NSDHC 1 /* SD host controller */ -# define KINETIS_NTOUCHIF 1 /* Xtrinsic touch sensing interface */ -# define KINETIS_NI2C 3 /* Three I2C modules */ -# define KINETIS_NISO7816 1 /* One UART with ISO-786 */ -# define KINETIS_NUART 5 /* Five additional UARTs */ -# define KINETIS_NSPI 3 /* Three SPI modules */ -# define KINETIS_NCAN 2 /* Two CAN controllers */ -# define KINETIS_NI2S 2 /* Two I2S modules */ -# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */ -# define KINETIS_NADC16 4 /* Four 16-bit ADC */ -# undef KINETIS_NADC12 /* No 12-channel ADC */ -# undef KINETIS_NADC13 /* No 13-channel ADC */ -# define KINETIS_NADC15 1 /* One 15-channel ADC (ADC0) */ -# define KINETIS_NADC18 1 /* One 18-channel ADC (ADC1) */ -# define KINETIS_NPGA 4 /* Four Programmable Gain Amplifiers */ -# define KINETIS_NCMP 3 /* Three analog comparators */ -# undef KINETIS_NDAC6 /* No 6-bit DAC */ -# define KINETIS_NDAC12 2 /* Twp 12-bit DACs */ -# define KINETIS_NVREF 1 /* Voltage reference */ -# undef KINETIS_NTIMERS12 /* No 12 channel timers */ -# define KINETIS_NTIMERS20 4 /* Four 20 channel timers */ -# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ -# undef KINETIS_NTIMERS20 /* No 20 channel timers */ -# define KINETIS_NRTC 1 /* Real time clock */ -# undef KINETIS_NRNG /* No random number generator */ -# undef KINETIS_NMMCAU /* No hardware encryption */ -# undef KINETIS_NTAMPER /* No tamper detect */ -# define KINETIS_NCRC 1 /* CRC */ - -#elif defined(CONFIG_ARCH_CHIP_MK60X256VMD100) -# undef KINETIS_K40 /* Not Kinetics K40 family */ -# define KINETIS_K60 1 /* Kinetis K60 family */ -# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */ -# define KINETIS_FLEXNVM_SIZE (256*1024) /* 256Kb */ -# define KINETIS_FLEXRAM_SIZE (4*1024) /* 4Kb */ -# define KINETIS_SRAM_SIZE (64*1024) /* 64Kb */ -# define KINETIS_MPU 1 /* Memory protection unit */ -# define KINETIS_EXTBUS 1 /* External bus interface */ -# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ -# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */ -# define KINETIS_NUSBHOST 1 /* One USB host controller */ -# define KINETIS_NUSBOTG 1 /* With USB OTG controller */ -# define KINETIS_NUSBDEV 1 /* One USB device controller */ -# define KINETIS_NSDHC 1 /* SD host controller */ -# define KINETIS_NTOUCHIF 1 /* Xtrinsic touch sensing interface */ -# define KINETIS_NI2C 3 /* Three I2C modules */ -# define KINETIS_NISO7816 1 /* One UART with ISO-786 */ -# define KINETIS_NUART 5 /* Five additional UARTs */ -# define KINETIS_NSPI 3 /* Three SPI modules */ -# define KINETIS_NCAN 2 /* Two CAN controllers */ -# define KINETIS_NI2S 2 /* Two I2S modules */ -# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */ -# define KINETIS_NADC16 4 /* Four 16-bit ADC */ -# undef KINETIS_NADC12 /* No 12-channel ADC */ -# undef KINETIS_NADC13 /* No 13-channel ADC */ -# define KINETIS_NADC15 1 /* One 15-channel ADC (ADC0) */ -# define KINETIS_NADC18 1 /* One 18-channel ADC (ADC1) */ -# define KINETIS_NPGA 4 /* Four Programmable Gain Amplifiers */ -# define KINETIS_NCMP 3 /* Three analog comparators */ -# undef KINETIS_NDAC6 /* No 6-bit DAC */ -# define KINETIS_NDAC12 2 /* Twp 12-bit DACs */ -# define KINETIS_NVREF 1 /* Voltage reference */ -# undef KINETIS_NTIMERS12 /* No 12 channel timers */ -# define KINETIS_NTIMERS20 4 /* Four 20 channel timers */ -# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ -# undef KINETIS_NTIMERS20 /* No 20 channel timers */ -# define KINETIS_NRTC 1 /* Real time clock */ -# undef KINETIS_NRNG /* No random number generator */ -# undef KINETIS_NMMCAU /* No hardware encryption */ -# undef KINETIS_NTAMPER /* No tamper detect */ -# define KINETIS_NCRC 1 /* CRC */ - -#elif defined(CONFIG_ARCH_CHIP_MK60N512VMD100) -# undef KINETIS_K40 /* Not Kinetics K40 family */ -# define KINETIS_K60 1 /* Kinetis K60 family */ -# define KINETIS_FLASH_SIZE (512*1024) /* 512Kb */ -# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */ -# undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */ -# define KINETIS_SRAM_SIZE (128*1024) /* 128Kb */ -# define KINETIS_MPU 1 /* Memory protection unit */ -# define KINETIS_EXTBUS 1 /* External bus interface */ -# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ -# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */ -# define KINETIS_NUSBHOST 1 /* One USB host controller */ -# define KINETIS_NUSBOTG 1 /* With USB OTG controller */ -# define KINETIS_NUSBDEV 1 /* One USB device controller */ -# define KINETIS_NSDHC 1 /* SD host controller */ -# define KINETIS_NTOUCHIF 1 /* Xtrinsic touch sensing interface */ -# define KINETIS_NI2C 3 /* Three I2C modules */ -# define KINETIS_NISO7816 1 /* One UART with ISO-786 */ -# define KINETIS_NUART 5 /* Five additional UARTs */ -# define KINETIS_NSPI 3 /* Three SPI modules */ -# define KINETIS_NCAN 2 /* Two CAN controllers */ -# define KINETIS_NI2S 2 /* Two I2S modules */ -# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */ -# define KINETIS_NADC16 4 /* Four 16-bit ADC */ -# undef KINETIS_NADC12 /* No 12-channel ADC */ -# undef KINETIS_NADC13 /* No 13-channel ADC */ -# define KINETIS_NADC15 1 /* One 15-channel ADC (ADC0) */ -# define KINETIS_NADC18 1 /* One 18-channel ADC (ADC1) */ -# define KINETIS_NPGA 4 /* Four Programmable Gain Amplifiers */ -# define KINETIS_NCMP 3 /* Three analog comparators */ -# undef KINETIS_NDAC6 /* No 6-bit DAC */ -# define KINETIS_NDAC12 2 /* Twp 12-bit DACs */ -# define KINETIS_NVREF 1 /* Voltage reference */ -# undef KINETIS_NTIMERS12 /* No 12 channel timers */ -# define KINETIS_NTIMERS20 4 /* Four 20 channel timers */ -# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ -# undef KINETIS_NTIMERS20 /* No 20 channel timers */ -# define KINETIS_NRTC 1 /* Real time clock */ -# undef KINETIS_NRNG /* No random number generator */ -# undef KINETIS_NMMCAU /* No hardware encryption */ -# undef KINETIS_NTAMPER /* No tamper detect */ -# define KINETIS_NCRC 1 /* CRC */ - -#else -# error "Unsupported Kinetis chip" -#endif - -/* Include only the memory map. Other chip hardware files should then include this - * file for the proper setup +/* Include the memory map and the chip definitions file. Other chip hardware files + * should then include this file for the proper setup. */ +#include <arch/kinetis/chip.h> #include "kinetis_memorymap.h" -/* NVIC priority levels *************************************************************/ -/* Each priority field holds a priority value, 0-15. The lower the value, the greater - * the priority of the corresponding interrupt. The processor implements only - * bits[7:4] of each field, bits[3:0] read as zero and ignore writes. - */ - -#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits[7:4] set is minimum priority */ -#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ -#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ -#define NVIC_SYSH_PRIORITY_STEP 0x10 /* Steps between supported priority values */ +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ /************************************************************************************ * Public Types diff --git a/nuttx/arch/arm/src/kinetis/kinetis_irq.c b/nuttx/arch/arm/src/kinetis/kinetis_irq.c index 6fb58c6bf..31310b03c 100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_irq.c +++ b/nuttx/arch/arm/src/kinetis/kinetis_irq.c @@ -2,7 +2,7 @@ * arch/arm/src/lpc17/kinetis_irq.c * arch/arm/src/chip/kinetis_irq.c * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2011, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without @@ -209,6 +209,35 @@ static int kinetis_reserved(int irq, FAR void *context) #endif /**************************************************************************** + * Name: up_prioritize_irq + * + * Description: + * Set the priority of an exception. This function may be needed + * internally even if support for prioritized interrupts is not enabled. + * + ****************************************************************************/ + +#if !defined(CONFIG_ARCH_IRQPRIO) && defined(CONFIG_ARMV7M_USEBASEPRI) +static int up_prioritize_irq(int irq, int priority) +{ + uint32_t regaddr; + uint32_t regval; + int shift; + + irq -= 4; + regaddr = NVIC_SYSH_PRIORITY(irq); + regval = getreg32(regaddr); + shift = ((irq & 3) << 3); + regval &= ~(0xff << shift); + regval |= (priority << shift); + putreg32(regval, regaddr); + + stm32_dumpnvic("prioritize", irq); + return OK; +} +#endif + +/**************************************************************************** * Name: kinetis_irqinfo * * Description: @@ -359,6 +388,9 @@ void up_irqinitialize(void) #ifdef CONFIG_ARCH_IRQPRIO /* up_prioritize_irq(KINETIS_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ #endif +#ifdef CONFIG_ARMV7M_USEBASEPRI + up_prioritize_irq(KINETIS_IRQ_SVCALL, NVIC_SYSH_SVCALL_PRIORITY); +#endif /* If the MPU is enabled, then attach and enable the Memory Management * Fault handler. @@ -486,7 +518,14 @@ int up_prioritize_irq(int irq, int priority) uint32_t regval; int shift; - DEBUGASSERT(irq >= KINETIS_IRQ_MEMFAULT && irq < NR_IRQS && (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN); +#ifdef CONFIG_ARMV7M_USEBASEPRI + DEBUGASSERT(irq >= KINETIS_IRQ_MEMFAULT && irq < NR_IRQS && + priority >= NVIC_SYSH_DISABLE_PRIORITY && + priority <= NVIC_SYSH_PRIORITY_MIN); +#else + DEBUGASSERT(irq >= KINETIS_IRQ_MEMFAULT && irq < NR_IRQS && + (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN); +#endif if (irq < KINETIS_IRQ_EXTINT) { diff --git a/nuttx/arch/arm/src/lm/chip.h b/nuttx/arch/arm/src/lm/chip.h index b5974b5dc..e476ce435 100644 --- a/nuttx/arch/arm/src/lm/chip.h +++ b/nuttx/arch/arm/src/lm/chip.h @@ -43,10 +43,6 @@ #include <nuttx/config.h> #include <arch/lm/chip.h> -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - /* Then get all of the register definitions */ #include "chip/lm_memorymap.h" /* Memory map */ @@ -58,15 +54,9 @@ #include "chip/lm_ethernet.h" /* Ethernet MAC and PHY */ #include "chip/lm_flash.h" /* FLASH */ -/* The LM3S69xx only supports 8 priority levels. The hardware priority mechanism - * will only look at the upper N bits of the 8-bit priority level (where N is 3 for - * the Stellaris family), so any prioritization must be performed in those bits. - * The default priority level is set to the middle value - */ - -#define NVIC_SYSH_PRIORITY_MIN 0xe0 /* All bits set in minimum priority */ -#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ -#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ /************************************************************************************ * Public Types diff --git a/nuttx/arch/arm/src/lm/lm_irq.c b/nuttx/arch/arm/src/lm/lm_irq.c index fa8e271bc..dc9997afa 100644 --- a/nuttx/arch/arm/src/lm/lm_irq.c +++ b/nuttx/arch/arm/src/lm/lm_irq.c @@ -2,7 +2,7 @@ * arch/arm/src/lm/lm_irq.c * arch/arm/src/chip/lm_irq.c * - * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2009, 2011, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without @@ -191,6 +191,35 @@ static int lm_reserved(int irq, FAR void *context) #endif /**************************************************************************** + * Name: up_prioritize_irq + * + * Description: + * Set the priority of an exception. This function may be needed + * internally even if support for prioritized interrupts is not enabled. + * + ****************************************************************************/ + +#if !defined(CONFIG_ARCH_IRQPRIO) && defined(CONFIG_ARMV7M_USEBASEPRI) +static int up_prioritize_irq(int irq, int priority) +{ + uint32_t regaddr; + uint32_t regval; + int shift; + + irq -= 4; + regaddr = NVIC_SYSH_PRIORITY(irq); + regval = getreg32(regaddr); + shift = ((irq & 3) << 3); + regval &= ~(0xff << shift); + regval |= (priority << shift); + putreg32(regval, regaddr); + + stm32_dumpnvic("prioritize", irq); + return OK; +} +#endif + +/**************************************************************************** * Name: lm_irqinfo * * Description: @@ -317,6 +346,9 @@ void up_irqinitialize(void) #ifdef CONFIG_ARCH_IRQPRIO /* up_prioritize_irq(LM_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ #endif +#ifdef CONFIG_ARMV7M_USEBASEPRI + up_prioritize_irq(LM_IRQ_SVCALL, NVIC_SYSH_SVCALL_PRIORITY); +#endif /* If the MPU is enabled, then attach and enable the Memory Management * Fault handler. @@ -433,7 +465,14 @@ int up_prioritize_irq(int irq, int priority) uint32_t regval; int shift; - DEBUGASSERT(irq >= LM_IRQ_MEMFAULT && irq < NR_IRQS && (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN); +#ifdef CONFIG_ARMV7M_USEBASEPRI + DEBUGASSERT(irq >= LM_IRQ_MEMFAULT && irq < NR_IRQS && + priority >= NVIC_SYSH_DISABLE_PRIORITY && + priority <= NVIC_SYSH_PRIORITY_MIN); +#else + DEBUGASSERT(irq >= LM_IRQ_MEMFAULT && irq < NR_IRQS && + (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN); +#endif if (irq < LM_IRQ_INTERRUPTS) { diff --git a/nuttx/arch/arm/src/lpc17xx/chip.h b/nuttx/arch/arm/src/lpc17xx/chip.h index d9b3998fe..7bc1ab345 100644 --- a/nuttx/arch/arm/src/lpc17xx/chip.h +++ b/nuttx/arch/arm/src/lpc17xx/chip.h @@ -41,28 +41,18 @@ ************************************************************************************/ #include <nuttx/config.h> -#include <arch/lpc17xx/chip.h> -/* Include only the memory map. Other chip hardware files should then include this - * file for the proper setup +/* Include the memory map and the chip definitions file. Other chip hardware files + * should then include this file for the proper setup. */ +#include <arch/lpc17xx/chip.h> #include "chip/lpc17_memorymap.h" /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ -/* NVIC priority levels *************************************************************/ -/* Each priority field holds a priority value, 0-31. The lower the value, the greater - * the priority of the corresponding interrupt. The processor implements only - * bits[7:3] of each field, bits[2:0] read as zero and ignore writes. - */ - -#define NVIC_SYSH_PRIORITY_MIN 0xf8 /* All bits[7:3] set is minimum priority */ -#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ -#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ - /************************************************************************************ * Public Types ************************************************************************************/ diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_irq.c b/nuttx/arch/arm/src/lpc17xx/lpc17_irq.c index f3e93ffc2..2d66dd0b1 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_irq.c +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_irq.c @@ -2,7 +2,7 @@ * arch/arm/src/lpc17/lpc17_irq.c * arch/arm/src/chip/lpc17_irq.c * - * Copyright (C) 2010-2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2010-2011, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without @@ -190,6 +190,35 @@ static int lpc17_reserved(int irq, FAR void *context) #endif /**************************************************************************** + * Name: up_prioritize_irq + * + * Description: + * Set the priority of an exception. This function may be needed + * internally even if support for prioritized interrupts is not enabled. + * + ****************************************************************************/ + +#if !defined(CONFIG_ARCH_IRQPRIO) && defined(CONFIG_ARMV7M_USEBASEPRI) +static int up_prioritize_irq(int irq, int priority) +{ + uint32_t regaddr; + uint32_t regval; + int shift; + + irq -= 4; + regaddr = NVIC_SYSH_PRIORITY(irq); + regval = getreg32(regaddr); + shift = ((irq & 3) << 3); + regval &= ~(0xff << shift); + regval |= (priority << shift); + putreg32(regval, regaddr); + + stm32_dumpnvic("prioritize", irq); + return OK; +} +#endif + +/**************************************************************************** * Name: lpc17_irqinfo * * Description: @@ -305,6 +334,9 @@ void up_irqinitialize(void) #ifdef CONFIG_ARCH_IRQPRIO /* up_prioritize_irq(LPC17_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ #endif +#ifdef CONFIG_ARMV7M_USEBASEPRI + up_prioritize_irq(LPC17_IRQ_SVCALL, NVIC_SYSH_SVCALL_PRIORITY); +#endif /* If the MPU is enabled, then attach and enable the Memory Management * Fault handler. @@ -448,7 +480,14 @@ int up_prioritize_irq(int irq, int priority) uint32_t regval; int shift; - DEBUGASSERT(irq >= LPC17_IRQ_MEMFAULT && irq < LPC17_IRQ_NIRQS && (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN); +#ifdef CONFIG_ARMV7M_USEBASEPRI + DEBUGASSERT(irq >= LPC17_IRQ_MEMFAULT && irq < LPC17_IRQ_NIRQS && + priority >= NVIC_SYSH_DISABLE_PRIORITY && + priority <= NVIC_SYSH_PRIORITY_MIN); +#else + DEBUGASSERT(irq >= LPC17_IRQ_MEMFAULT && irq < LPC17_IRQ_NIRQS && + (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN); +#endif if (irq < LPC17_IRQ_EXTINT) { diff --git a/nuttx/arch/arm/src/lpc43xx/chip.h b/nuttx/arch/arm/src/lpc43xx/chip.h index 35150d08c..151571e74 100644 --- a/nuttx/arch/arm/src/lpc43xx/chip.h +++ b/nuttx/arch/arm/src/lpc43xx/chip.h @@ -1,7 +1,7 @@ /************************************************************************************ * arch/arm/src/lpc43xx/chip.h * - * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2012-2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without @@ -141,23 +141,6 @@ * Pre-processor Definitions ************************************************************************************/ -/* NVIC priority levels *************************************************************/ -/* Each priority field holds a priority value, 0-31. The lower the value, the greater - * the priority of the corresponding interrupt. - * - * The Cortex-M4 core supports up to 53 interrupts an 8 prgrammable interrupt - * priority levels; The Cortex-M0 core supports up to 32 interrupts with 4 - * programmable interrupt priorities. - */ - -#define LPC43M4_SYSH_PRIORITY_MIN 0xe0 /* All bits[7:5] set is minimum priority */ -#define LPC43M4_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ -#define LPC43M4_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ - -#define LPC43M0_SYSH_PRIORITY_MIN 0xc0 /* All bits[7:6] set is minimum priority */ -#define LPC43M0_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ -#define LPC43M0_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ - /************************************************************************************ * Public Types ************************************************************************************/ diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_irq.c b/nuttx/arch/arm/src/lpc43xx/lpc43_irq.c index 9cbb8238c..2fddd79ad 100644 --- a/nuttx/arch/arm/src/lpc43xx/lpc43_irq.c +++ b/nuttx/arch/arm/src/lpc43xx/lpc43_irq.c @@ -2,7 +2,7 @@ * arch/arm/src/lpc43/lpc43_irq.c * arch/arm/src/chip/lpc43_irq.c * - * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2012-2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without @@ -192,6 +192,35 @@ static int lpc43_reserved(int irq, FAR void *context) #endif /**************************************************************************** + * Name: up_prioritize_irq + * + * Description: + * Set the priority of an exception. This function may be needed + * internally even if support for prioritized interrupts is not enabled. + * + ****************************************************************************/ + +#if !defined(CONFIG_ARCH_IRQPRIO) && defined(CONFIG_ARMV7M_USEBASEPRI) +static int up_prioritize_irq(int irq, int priority) +{ + uint32_t regaddr; + uint32_t regval; + int shift; + + irq -= 4; + regaddr = NVIC_SYSH_PRIORITY(irq); + regval = getreg32(regaddr); + shift = ((irq & 3) << 3); + regval &= ~(0xff << shift); + regval |= (priority << shift); + putreg32(regval, regaddr); + + stm32_dumpnvic("prioritize", irq); + return OK; +} +#endif + +/**************************************************************************** * Name: lpc43_irqinfo * * Description: @@ -334,6 +363,9 @@ void up_irqinitialize(void) #ifdef CONFIG_ARCH_IRQPRIO /* up_prioritize_irq(LPC43_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ #endif +#ifdef CONFIG_ARMV7M_USEBASEPRI + up_prioritize_irq(LPC43_IRQ_SVCALL, NVIC_SYSH_SVCALL_PRIORITY); +#endif /* If the MPU is enabled, then attach and enable the Memory Management * Fault handler. @@ -477,8 +509,14 @@ int up_prioritize_irq(int irq, int priority) uint32_t regval; int shift; +#ifdef CONFIG_ARMV7M_USEBASEPRI DEBUGASSERT(irq >= LPC43_IRQ_MEMFAULT && irq < NR_IRQS && - (unsigned)priority <= LPC43M4_SYSH_PRIORITY_MIN); + priority >= NVIC_SYSH_DISABLE_PRIORITY && + priority <= NVIC_SYSH_PRIORITY_MIN); +#else + DEBUGASSERT(irq >= LPC43_IRQ_MEMFAULT && irq < NR_IRQS && + (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN); +#endif if (irq < LPC43_IRQ_EXTINT) { diff --git a/nuttx/arch/arm/src/sam3u/chip.h b/nuttx/arch/arm/src/sam3u/chip.h index 865cad5ea..1ce104ab2 100644 --- a/nuttx/arch/arm/src/sam3u/chip.h +++ b/nuttx/arch/arm/src/sam3u/chip.h @@ -1,7 +1,7 @@ /************************************************************************************ * arch/arm/src/sam3u/chip.h * - * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. + * Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without @@ -42,45 +42,16 @@ #include <nuttx/config.h> -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Get customizations for each supported chip */ - -#ifdef CONFIG_ARCH_CHIP_AT91SAM3U4E -/* Internal memory */ - -# define CONFIG_SAM3U_SRAM0_SIZE 0x00008000 /* 32Kb */ -# define CONFIG_SAM3U_SRAM1_SIZE 0x00004000 /* 16Kb */ -# define CONFIG_SAM3U_NFCSRAM_SIZE 0x00001000 /* 4Kb */ - -/* DMA */ - -# define CONFIG_SAM3U_NDMACHAN 4 /* 4 DMA Channels */ - -/* Memory card interface */ - -# define CONFIG_SAM3U_MCI2 1 -#else -# error "Unknown SAM3U chip type" -#endif - -/* Include only the memory map. Other chip hardware files should then include this - * file for the proper setup +/* Include the memory map and the chip definitions file. Other chip hardware files + * should then include this file for the proper setup. */ +#include <arch/sam3u/chip.h> #include "sam3u_memorymap.h" -/* NVIC priority levels *************************************************************/ -/* Each priority field holds a priority value, 0-15. The lower the value, the greater - * the priority of the corresponding interrupt. The processor implements only - * bits[7:4] of each field, bits[3:0] read as zero and ignore writes. - */ - -#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits[7:4] set is minimum priority */ -#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ -#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ /************************************************************************************ * Public Types diff --git a/nuttx/arch/arm/src/sam3u/sam3u_irq.c b/nuttx/arch/arm/src/sam3u/sam3u_irq.c index db79314c0..d9fd4dac8 100644 --- a/nuttx/arch/arm/src/sam3u/sam3u_irq.c +++ b/nuttx/arch/arm/src/sam3u/sam3u_irq.c @@ -2,7 +2,7 @@ * arch/arm/src/sam3u/sam3u_irq.c * arch/arm/src/chip/sam3u_irq.c * - * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2009, 2011, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without @@ -185,6 +185,35 @@ static int sam3u_reserved(int irq, FAR void *context) #endif /**************************************************************************** + * Name: up_prioritize_irq + * + * Description: + * Set the priority of an exception. This function may be needed + * internally even if support for prioritized interrupts is not enabled. + * + ****************************************************************************/ + +#if !defined(CONFIG_ARCH_IRQPRIO) && defined(CONFIG_ARMV7M_USEBASEPRI) +static int up_prioritize_irq(int irq, int priority) +{ + uint32_t regaddr; + uint32_t regval; + int shift; + + irq -= 4; + regaddr = NVIC_SYSH_PRIORITY(irq); + regval = getreg32(regaddr); + shift = ((irq & 3) << 3); + regval &= ~(0xff << shift); + regval |= (priority << shift); + putreg32(regval, regaddr); + + stm32_dumpnvic("prioritize", irq); + return OK; +} +#endif + +/**************************************************************************** * Name: sam3u_irqinfo * * Description: @@ -296,6 +325,9 @@ void up_irqinitialize(void) #ifdef CONFIG_ARCH_IRQPRIO /* up_prioritize_irq(SAM3U_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ #endif +#ifdef CONFIG_ARMV7M_USEBASEPRI + up_prioritize_irq(SAM3U_IRQ_SVCALL, NVIC_SYSH_SVCALL_PRIORITY); +#endif /* If the MPU is enabled, then attach and enable the Memory Management * Fault handler. @@ -436,7 +468,14 @@ int up_prioritize_irq(int irq, int priority) uint32_t regval; int shift; - DEBUGASSERT(irq >= SAM3U_IRQ_MEMFAULT && irq < SAM3U_IRQ_NIRQS && (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN); +#ifdef CONFIG_ARMV7M_USEBASEPRI + DEBUGASSERT(irq >= SAM3U_IRQ_MEMFAULT && irq < SAM3U_IRQ_NIRQS && + priority >= NVIC_SYSH_DISABLE_PRIORITY && + priority <= NVIC_SYSH_PRIORITY_MIN); +#else + DEBUGASSERT(irq >= SAM3U_IRQ_MEMFAULT && irq < SAM3U_IRQ_NIRQS && + (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN); +#endif if (irq < SAM3U_IRQ_EXTINT) { diff --git a/nuttx/arch/arm/src/stm32/chip.h b/nuttx/arch/arm/src/stm32/chip.h index 3fac597ef..41a87feae 100644 --- a/nuttx/arch/arm/src/stm32/chip.h +++ b/nuttx/arch/arm/src/stm32/chip.h @@ -1,7 +1,7 @@ /************************************************************************************ * arch/arm/src/stm32/chip.h * - * Copyright (C) 2009, 2011-2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2009, 2011-2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without diff --git a/nuttx/arch/arm/src/stm32/stm32.h b/nuttx/arch/arm/src/stm32/stm32.h index 44a23aece..95fd19779 100644 --- a/nuttx/arch/arm/src/stm32/stm32.h +++ b/nuttx/arch/arm/src/stm32/stm32.h @@ -68,12 +68,6 @@ # undef CONFIG_DEBUG_QENCODER #endif -/* NVIC priority levels *************************************************************/ - -#define NVIC_SYSH_PRIORITY_MIN 0xff /* All bits set in minimum priority */ -#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ -#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ - /* Peripherals **********************************************************************/ #include "chip.h" diff --git a/nuttx/arch/arm/src/stm32/stm32_irq.c b/nuttx/arch/arm/src/stm32/stm32_irq.c index 36a5cf5fa..8f2b070fb 100644 --- a/nuttx/arch/arm/src/stm32/stm32_irq.c +++ b/nuttx/arch/arm/src/stm32/stm32_irq.c @@ -2,7 +2,7 @@ * arch/arm/src/stm32/stm32_irq.c * arch/arm/src/chip/stm32_irq.c * - * Copyright (C) 2009-2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2009-2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without @@ -195,6 +195,35 @@ static int stm32_reserved(int irq, FAR void *context) #endif /**************************************************************************** + * Name: up_prioritize_irq + * + * Description: + * Set the priority of an exception. This function may be needed + * internally even if support for prioritized interrupts is not enabled. + * + ****************************************************************************/ + +#if !defined(CONFIG_ARCH_IRQPRIO) && defined(CONFIG_ARMV7M_USEBASEPRI) +static int up_prioritize_irq(int irq, int priority) +{ + uint32_t regaddr; + uint32_t regval; + int shift; + + irq -= 4; + regaddr = NVIC_SYSH_PRIORITY(irq); + regval = getreg32(regaddr); + shift = ((irq & 3) << 3); + regval &= ~(0xff << shift); + regval |= (priority << shift); + putreg32(regval, regaddr); + + stm32_dumpnvic("prioritize", irq); + return OK; +} +#endif + +/**************************************************************************** * Name: stm32_irqinfo * * Description: @@ -335,6 +364,9 @@ void up_irqinitialize(void) #ifdef CONFIG_ARCH_IRQPRIO /* up_prioritize_irq(STM32_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ #endif +#ifdef CONFIG_ARMV7M_USEBASEPRI + up_prioritize_irq(STM32_IRQ_SVCALL, NVIC_SYSH_SVCALL_PRIORITY); +#endif /* If the MPU is enabled, then attach and enable the Memory Management * Fault handler. @@ -451,7 +483,14 @@ int up_prioritize_irq(int irq, int priority) uint32_t regval; int shift; - DEBUGASSERT(irq >= STM32_IRQ_MEMFAULT && irq < NR_IRQS && (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN); +#ifdef CONFIG_ARMV7M_USEBASEPRI + DEBUGASSERT(irq >= STM32_IRQ_MEMFAULT && irq < NR_IRQS && + priority >= NVIC_SYSH_DISABLE_PRIORITY && + priority <= NVIC_SYSH_PRIORITY_MIN); +#else + DEBUGASSERT(irq >= STM32_IRQ_MEMFAULT && irq < NR_IRQS && + (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN); +#endif if (irq < STM32_IRQ_INTERRUPTS) { |