More trailing whilespace removal

7 files changed, 16 insertions, 16 deletions

diff --git a/nuttx/configs/cloudctrl/README.txt b/nuttx/configs/cloudctrl/README.txt
index 24d673726..7de88edf3 100644
--- a/nuttx/configs/cloudctrl/README.txt
+++ b/nuttx/configs/cloudctrl/README.txt
@@ -2,7 +2,7 @@ README
 ======
 
 This README discusses issues unique to NuttX configurations for the CloudController
-development board featuring the STMicro STM32F107VCT MCU.  
+development board featuring the STMicro STM32F107VCT MCU.
 
 Features of the CloudController board include:
 
@@ -392,7 +392,7 @@ NXFLAT Toolchain
   tools -- just the NXFLAT tools.  The buildroot with the NXFLAT tools can
   be downloaded from the NuttX SourceForge download site
   (https://sourceforge.net/projects/nuttx/files/).
- 
+
   This GNU toolchain builds and executes in the Linux or Cygwin environment.
 
   1. You must have already configured Nuttx in <some-dir>/nuttx.
@@ -700,14 +700,14 @@ Cloudctrl-specific Configuration Options
   STM32 USB OTG FS Host Driver Support
 
   Pre-requisites
- 
+
    CONFIG_USBHOST         - Enable USB host support
    CONFIG_STM32_OTGFS     - Enable the STM32 USB OTG FS block
    CONFIG_STM32_SYSCFG    - Needed
    CONFIG_SCHED_WORKQUEUE - Worker thread support is required
- 
+
   Options:
- 
+
    CONFIG_STM32_OTGFS_RXFIFO_SIZE - Size of the RX FIFO in 32-bit words.
      Default 128 (512 bytes)
    CONFIG_STM32_OTGFS_NPTXFIFO_SIZE - Size of the non-periodic Tx FIFO
@@ -760,7 +760,7 @@ Where <subdir> is one of the following:
          ADC1_IN10(PC0) Potentiometer
 
        External signals are also available on CON5 CN14:
-    
+
          ADC_IN8 (PB0) CON5 CN14 Pin2
          ADC_IN9 (PB1) CON5 CN14 Pin1
 
@@ -855,7 +855,7 @@ Where <subdir> is one of the following:
 
       -CONFIG_NX_WRITEONLY=y
       +# CONFIG_NX_WRITEONLY is not set
- 
+
   thttpd
   ------
 
diff --git a/nuttx/configs/cloudctrl/include/board.h b/nuttx/configs/cloudctrl/include/board.h
index aa47ad1d2..00c453fe4 100644
--- a/nuttx/configs/cloudctrl/include/board.h
+++ b/nuttx/configs/cloudctrl/include/board.h
@@ -112,7 +112,7 @@
 
 /* MCO output driven by PLL3. From above, we already have PLL3 input frequency as:
  *
- *  STM32_PLL_PREDIV2 = 5, 25MHz / 5 => 5MHz 
+ *  STM32_PLL_PREDIV2 = 5, 25MHz / 5 => 5MHz
  */
 
 #if defined(CONFIG_STM32_MII_MCO) || defined(CONFIG_STM32_RMII_MCO)
@@ -160,7 +160,7 @@
 #define BUTTON_KEY2         1
 #define BUTTON_KEY3         2
 #define NUM_BUTTONS         3
- 
+
 #define BUTTON_USERKEY      BUTTON_KEY1 /* Names in schematic */
 #define BUTTON_TAMPER       BUTTON_KEY2
 #define BUTTON_WAKEUP       BUTTON_KEY3
@@ -196,7 +196,7 @@
  * 56 PD9  MII_RXD0       Ethernet PHY.  Requires CONFIG_STM32_ETH_REMAP
  * 57 PD10 MII_RXD1       Ethernet PHY.  Requires CONFIG_STM32_ETH_REMAP
  *
- * The board desdign can support a 50MHz external clock to drive the PHY 
+ * The board desdign can support a 50MHz external clock to drive the PHY
  * (U9).  However, on my board, U9 is not present.
  *
  * 67 PA8  MCO            DM9161AEP
diff --git a/nuttx/configs/cloudctrl/nsh/Make.defs b/nuttx/configs/cloudctrl/nsh/Make.defs
index 63801f76d..b5474d9d1 100644
--- a/nuttx/configs/cloudctrl/nsh/Make.defs
+++ b/nuttx/configs/cloudctrl/nsh/Make.defs
@@ -54,7 +54,7 @@ ifeq ($(WINTOOL),y)
   ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}"
   ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}"
 else
-  # Linux/Cygwin-native toolchain 
+  # Linux/Cygwin-native toolchain
   MKDEP = $(TOPDIR)/tools/mkdeps.sh
   ARCHINCLUDES = -I. -isystem $(TOPDIR)/include
   ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx
diff --git a/nuttx/configs/cloudctrl/src/Makefile b/nuttx/configs/cloudctrl/src/Makefile
index e04853115..248886fc3 100644
--- a/nuttx/configs/cloudctrl/src/Makefile
+++ b/nuttx/configs/cloudctrl/src/Makefile
@@ -38,7 +38,7 @@
 
 CFLAGS		+= -I$(TOPDIR)/sched
 
-ASRCS		= 
+ASRCS		=
 AOBJS		= $(ASRCS:.S=$(OBJEXT))
 
 CSRCS		= up_boot.c up_spi.c up_chipid.c
diff --git a/nuttx/configs/cloudctrl/src/cloudctrl-internal.h b/nuttx/configs/cloudctrl/src/cloudctrl-internal.h
index f731a455e..b31b873d8 100644
--- a/nuttx/configs/cloudctrl/src/cloudctrl-internal.h
+++ b/nuttx/configs/cloudctrl/src/cloudctrl-internal.h
@@ -84,7 +84,7 @@
  * 56 PD9  MII_RXD0       Ethernet PHY.  Requires CONFIG_STM32_ETH_REMAP
  * 57 PD10 MII_RXD1       Ethernet PHY.  Requires CONFIG_STM32_ETH_REMAP
  *
- * The board desdign can support a 50MHz external clock to drive the PHY 
+ * The board desdign can support a 50MHz external clock to drive the PHY
  * (U9).  However, on my board, U9 is not present.
  *
  * 67 PA8  MCO            DM9161AEP
diff --git a/nuttx/configs/cloudctrl/src/up_buttons.c b/nuttx/configs/cloudctrl/src/up_buttons.c
index 18e4d9057..d823d28fc 100644
--- a/nuttx/configs/cloudctrl/src/up_buttons.c
+++ b/nuttx/configs/cloudctrl/src/up_buttons.c
@@ -88,7 +88,7 @@ void board_button_initialize(void)
 {
   int i;
 
-  /* Configure the GPIO pins as inputs.  NOTE that EXTI interrupts are 
+  /* Configure the GPIO pins as inputs.  NOTE that EXTI interrupts are
    * configured for some pins but NOT used in this file
    */
 
diff --git a/nuttx/configs/cloudctrl/src/up_userleds.c b/nuttx/configs/cloudctrl/src/up_userleds.c
index 633aa7d98..cac8c5045 100644
--- a/nuttx/configs/cloudctrl/src/up_userleds.c
+++ b/nuttx/configs/cloudctrl/src/up_userleds.c
@@ -76,9 +76,9 @@
  ****************************************************************************/
 /* This array maps an LED number to GPIO pin configuration */
 
-static uint32_t g_ledcfg[BOARD_NLEDS] = 
+static uint32_t g_ledcfg[BOARD_NLEDS] =
 {
-  GPIO_LED1, GPIO_LED2, GPIO_LED3, GPIO_LED4 
+  GPIO_LED1, GPIO_LED2, GPIO_LED3, GPIO_LED4
 };
 
 /****************************************************************************