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authorGregory Nutt <gnutt@nuttx.org>2014-07-03 12:28:11 -0600
committerGregory Nutt <gnutt@nuttx.org>2014-07-03 12:28:11 -0600
commit2ed9c34e69eac7bef96d4ff17971458fbd92e2ab (patch)
treef633f9289122fc299f378b389639ec2d019b6c43 /nuttx
parent6c6e515f384deeb7c51dcc0e01a58e4eb1ac18f6 (diff)
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SAMA5D3/4: UPLL divisor to generate 48MHz for OHCI is different from the two families. No idea why.
Diffstat (limited to 'nuttx')
-rw-r--r--nuttx/arch/arm/src/sama5/sam_clockconfig.c12
-rw-r--r--nuttx/arch/arm/src/sama5/sam_ohci.c2
-rw-r--r--nuttx/configs/sama5d3-xplained/include/board_396mhz.h6
-rw-r--r--nuttx/configs/sama5d3-xplained/include/board_528mhz.h6
-rw-r--r--nuttx/configs/sama5d3-xplained/include/board_sdram.h6
-rw-r--r--nuttx/configs/sama5d3x-ek/include/board_396mhz.h6
-rw-r--r--nuttx/configs/sama5d3x-ek/include/board_528mhz.h6
-rw-r--r--nuttx/configs/sama5d3x-ek/include/board_sdram.h6
-rw-r--r--nuttx/configs/sama5d4-ek/include/board_396mhz.h1
-rw-r--r--nuttx/configs/sama5d4-ek/include/board_528mhz.h1
-rw-r--r--nuttx/configs/sama5d4-ek/include/board_sdram.h1
11 files changed, 45 insertions, 8 deletions
diff --git a/nuttx/arch/arm/src/sama5/sam_clockconfig.c b/nuttx/arch/arm/src/sama5/sam_clockconfig.c
index a561bb9a2..d34a07fa0 100644
--- a/nuttx/arch/arm/src/sama5/sam_clockconfig.c
+++ b/nuttx/arch/arm/src/sama5/sam_clockconfig.c
@@ -492,15 +492,13 @@ static inline void sam_usbclockconfig(void)
* PMC_USB register. USBDIV must be 9 (division by 10) if UPLLCK is
* selected.
*
- * REVISIT: The divisor of 10 produces a rate that is too high. Division
- * by 5, however, seems to work just fine. No idea why?
+ * REVISIT: The divisor of 10 produces a rate that is too high with
+ * SAMA5D3. A divisor of 5, however, seems to work just fine for the
+ * SAMA5D3. The SAMA5D4, on the other hand, needs the divisor of 10.
+ * No idea why? Let the board.h file decide which to use.
*/
-#if 1 /* REVISIT */
- regval |= PMC_USB_USBDIV(4); /* Division by 5 */
-#else
- regval |= PMC_USB_USBDIV(9); /* Division by 10 */
-#endif
+ regval |= PMC_USB_USBDIV(BOARD_UPLL_OHCI_DIV-1);
putreg32(regval, SAM_PMC_USB);
#else /* BOARD_USE_UPLL */
diff --git a/nuttx/arch/arm/src/sama5/sam_ohci.c b/nuttx/arch/arm/src/sama5/sam_ohci.c
index 84f9ac601..cdf040adc 100644
--- a/nuttx/arch/arm/src/sama5/sam_ohci.c
+++ b/nuttx/arch/arm/src/sama5/sam_ohci.c
@@ -1880,7 +1880,7 @@ static void sam_wdh_bottomhalf(void)
/* Invalidate D-cache to force re-reading of the Done Head */
-# if 0 /* Apparently insufficient */
+#if 0 /* Apparently insufficient */
cp15_invalidate_dcache((uintptr_t)&g_hcca.donehead,
(uintptr_t)&g_hcca.donehead + sizeof(uint32_t));
#else
diff --git a/nuttx/configs/sama5d3-xplained/include/board_396mhz.h b/nuttx/configs/sama5d3-xplained/include/board_396mhz.h
index 7293956a5..88369eb49 100644
--- a/nuttx/configs/sama5d3-xplained/include/board_396mhz.h
+++ b/nuttx/configs/sama5d3-xplained/include/board_396mhz.h
@@ -162,6 +162,12 @@
# define BOARD_USE_UPLL 1 /* Use UPLL for clock source */
# define BOARD_CKGR_UCKR_UPLLCOUNT (15) /* Maximum value */
# define BOARD_CKGR_UCKR_BIASCOUNT (15) /* Maximum value */
+
+/* REVISIT: The divisor of 10 produces a rate that is too high. Division
+ * by 5, however, seems to work just fine. No idea why?
+ */
+
+# define BOARD_UPLL_OHCI_DIV (5) /* Divide by 5 */
#endif
/* HSMCI clocking
diff --git a/nuttx/configs/sama5d3-xplained/include/board_528mhz.h b/nuttx/configs/sama5d3-xplained/include/board_528mhz.h
index dc857bee4..78be010ca 100644
--- a/nuttx/configs/sama5d3-xplained/include/board_528mhz.h
+++ b/nuttx/configs/sama5d3-xplained/include/board_528mhz.h
@@ -161,6 +161,12 @@
# define BOARD_USE_UPLL 1 /* Use UPLL for clock source */
# define BOARD_CKGR_UCKR_UPLLCOUNT (15) /* Maximum value */
# define BOARD_CKGR_UCKR_BIASCOUNT (15) /* Maximum value */
+
+/* REVISIT: The divisor of 10 produces a rate that is too high. Division
+ * by 5, however, seems to work just fine. No idea why?
+ */
+
+# define BOARD_UPLL_OHCI_DIV (5) /* Divide by 5 */
#endif
/* HSMCI clocking
diff --git a/nuttx/configs/sama5d3-xplained/include/board_sdram.h b/nuttx/configs/sama5d3-xplained/include/board_sdram.h
index 4f2e5f971..cd5a5b5df 100644
--- a/nuttx/configs/sama5d3-xplained/include/board_sdram.h
+++ b/nuttx/configs/sama5d3-xplained/include/board_sdram.h
@@ -100,6 +100,12 @@
# define BOARD_USE_UPLL 1 /* Use UPLL for clock source */
# define BOARD_CKGR_UCKR_UPLLCOUNT (15) /* Maximum value */
# define BOARD_CKGR_UCKR_BIASCOUNT (15) /* Maximum value */
+
+/* REVISIT: The divisor of 10 produces a rate that is too high. Division
+ * by 5, however, seems to work just fine. No idea why?
+ */
+
+# define BOARD_UPLL_OHCI_DIV (5) /* Divide by 5 */
#endif
/* ADC Configuration
diff --git a/nuttx/configs/sama5d3x-ek/include/board_396mhz.h b/nuttx/configs/sama5d3x-ek/include/board_396mhz.h
index ef850fda8..3fbe75b17 100644
--- a/nuttx/configs/sama5d3x-ek/include/board_396mhz.h
+++ b/nuttx/configs/sama5d3x-ek/include/board_396mhz.h
@@ -162,6 +162,12 @@
# define BOARD_USE_UPLL 1 /* Use UPLL for clock source */
# define BOARD_CKGR_UCKR_UPLLCOUNT (15) /* Maximum value */
# define BOARD_CKGR_UCKR_BIASCOUNT (15) /* Maximum value */
+
+/* REVISIT: The divisor of 10 produces a rate that is too high. Division
+ * by 5, however, seems to work just fine. No idea why?
+ */
+
+# define BOARD_UPLL_OHCI_DIV (5) /* Divide by 5 */
#endif
/* HSMCI clocking
diff --git a/nuttx/configs/sama5d3x-ek/include/board_528mhz.h b/nuttx/configs/sama5d3x-ek/include/board_528mhz.h
index 0b2744030..08a6fba26 100644
--- a/nuttx/configs/sama5d3x-ek/include/board_528mhz.h
+++ b/nuttx/configs/sama5d3x-ek/include/board_528mhz.h
@@ -160,6 +160,12 @@
# define BOARD_USE_UPLL 1 /* Use UPLL for clock source */
# define BOARD_CKGR_UCKR_UPLLCOUNT (15) /* Maximum value */
# define BOARD_CKGR_UCKR_BIASCOUNT (15) /* Maximum value */
+
+/* REVISIT: The divisor of 10 produces a rate that is too high. Division
+ * by 5, however, seems to work just fine. No idea why?
+ */
+
+# define BOARD_UPLL_OHCI_DIV (5) /* Divide by 5 */
#endif
/* HSMCI clocking
diff --git a/nuttx/configs/sama5d3x-ek/include/board_sdram.h b/nuttx/configs/sama5d3x-ek/include/board_sdram.h
index 9e4b60469..990673aaa 100644
--- a/nuttx/configs/sama5d3x-ek/include/board_sdram.h
+++ b/nuttx/configs/sama5d3x-ek/include/board_sdram.h
@@ -100,6 +100,12 @@
# define BOARD_USE_UPLL 1 /* Use UPLL for clock source */
# define BOARD_CKGR_UCKR_UPLLCOUNT (15) /* Maximum value */
# define BOARD_CKGR_UCKR_BIASCOUNT (15) /* Maximum value */
+
+/* REVISIT: The divisor of 10 produces a rate that is too high. Division
+ * by 5, however, seems to work just fine. No idea why?
+ */
+
+# define BOARD_UPLL_OHCI_DIV (5) /* Divide by 5 */
#endif
/* ADC Configuration
diff --git a/nuttx/configs/sama5d4-ek/include/board_396mhz.h b/nuttx/configs/sama5d4-ek/include/board_396mhz.h
index 11af935ed..34441910f 100644
--- a/nuttx/configs/sama5d4-ek/include/board_396mhz.h
+++ b/nuttx/configs/sama5d4-ek/include/board_396mhz.h
@@ -161,6 +161,7 @@
# define BOARD_USE_UPLL 1 /* Use UPLL for clock source */
# define BOARD_CKGR_UCKR_UPLLCOUNT (15) /* Maximum value */
# define BOARD_CKGR_UCKR_BIASCOUNT (15) /* Maximum value */
+# define BOARD_UPLL_OHCI_DIV (10) /* Divide by 10 */
#endif
/* HSMCI clocking
diff --git a/nuttx/configs/sama5d4-ek/include/board_528mhz.h b/nuttx/configs/sama5d4-ek/include/board_528mhz.h
index aa6a336e8..7b34f09b4 100644
--- a/nuttx/configs/sama5d4-ek/include/board_528mhz.h
+++ b/nuttx/configs/sama5d4-ek/include/board_528mhz.h
@@ -160,6 +160,7 @@
# define BOARD_USE_UPLL 1 /* Use UPLL for clock source */
# define BOARD_CKGR_UCKR_UPLLCOUNT (15) /* Maximum value */
# define BOARD_CKGR_UCKR_BIASCOUNT (15) /* Maximum value */
+# define BOARD_UPLL_OHCI_DIV (10) /* Divide by 10 */
#endif
/* HSMCI clocking
diff --git a/nuttx/configs/sama5d4-ek/include/board_sdram.h b/nuttx/configs/sama5d4-ek/include/board_sdram.h
index 5b113d17e..f86d2827d 100644
--- a/nuttx/configs/sama5d4-ek/include/board_sdram.h
+++ b/nuttx/configs/sama5d4-ek/include/board_sdram.h
@@ -101,6 +101,7 @@
# define BOARD_USE_UPLL 1 /* Use UPLL for clock source */
# define BOARD_CKGR_UCKR_UPLLCOUNT (15) /* Maximum value */
# define BOARD_CKGR_UCKR_BIASCOUNT (15) /* Maximum value */
+# define BOARD_UPLL_OHCI_DIV (10) /* Divide by 10 */
#endif
/* ADC Configuration