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| author | Gregory Nutt <gnutt@nuttx.org> | 2014-06-19 14:16:36 -0600 |
|---|---|---|
| committer | Gregory Nutt <gnutt@nuttx.org> | 2014-06-19 14:16:36 -0600 |
| commit | 18fcff8a4ae716169aa2b9fb6ce959ad2a668455 (patch) | |
| tree | e611d3cba5fceddc2081d35e52d9ac1dd8f97447 /nuttx | |
| parent | 4259e65dae6e3b6f99e13a53a7773b6a768d0ec2 (diff) | |
| download | nuttx-18fcff8a4ae716169aa2b9fb6ce959ad2a668455.tar.gz nuttx-18fcff8a4ae716169aa2b9fb6ce959ad2a668455.tar.bz2 nuttx-18fcff8a4ae716169aa2b9fb6ce959ad2a668455.zip | |
SAMA5D4: Initial bring-up fixes
Diffstat (limited to 'nuttx')
| -rw-r--r-- | nuttx/arch/arm/src/sama5/chip/sam_pmc.h | 12 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/sama5/sam_clockconfig.c | 9 | ||||
| -rw-r--r-- | nuttx/configs/sama5d4-ek/ramtest/defconfig | 2 |
3 files changed, 17 insertions, 6 deletions
diff --git a/nuttx/arch/arm/src/sama5/chip/sam_pmc.h b/nuttx/arch/arm/src/sama5/chip/sam_pmc.h index c8f6ec378..feb796d7f 100644 --- a/nuttx/arch/arm/src/sama5/chip/sam_pmc.h +++ b/nuttx/arch/arm/src/sama5/chip/sam_pmc.h @@ -228,22 +228,32 @@ /* PMC Clock Generator PLLA Register */ #undef SAMA5_HAVE_PLLAR_DIV -#ifdef ATSAMA5D3 +#if defined(ATSAMA5D3) # define PMC_CKGR_PLLAR_DIV_SHIFT (0) /* Bits 0-7: Divider */ # define PMC_CKGR_PLLAR_DIV_MASK (0xff << PMC_CKGR_PLLAR_DIV_SHIFT) # define PMC_CKGR_PLLAR_DIV_ZERO (0 << PMC_CKGR_PLLAR_DIV_SHIFT) /* Divider output is 0 */ # define PMC_CKGR_PLLAR_DIV_BYPASS (1 << PMC_CKGR_PLLAR_DIV_SHIFT) /* Divider is bypassed (DIV=1) */ # define PMC_CKGR_PLLAR_DIV(n) ((n) << PMC_CKGR_PLLAR_DIV_SHIFT) /* Divider output is DIV=n, n=2..255 */ # define SAMA5_HAVE_PLLAR_DIV 1 + +/* According the preliminary documentation, there is no DIV field in the SAMA5D4 + * PLLAR register. However, through trial and error, I find that the PLL output + * is still disabled if the DIV field is set to zero. + */ + +#elif defined(ATSAMA5D4) +# define PMC_CKGR_PLLAR_DIV_BYPASS (1) /* Divider is bypassed (DIV=1) */ #endif #define PMC_CKGR_PLLAR_COUNT_SHIFT (8) /* Bits 8-13: PLLA Counter */ #define PMC_CKGR_PLLAR_COUNT_MASK (63 << PMC_CKGR_PLLAR_COUNT_SHIFT) +# define PMC_CKGR_PLLAR_COUNT(n) ((uint32_t)(n) << PMC_CKGR_PLLAR_COUNT_SHIFT) #define PMC_CKGR_PLLAR_OUT_SHIFT (14) /* Bits 14-17: PLLA Clock Frequency Range */ #define PMC_CKGR_PLLAR_OUT_MASK (15 << PMC_CKGR_PLLAR_OUT_SHIFT) # define PMC_CKGR_PLLAR_OUT (0 << PMC_CKGR_PLLAR_OUT_SHIFT) /* To be programmed to 0 */ #define PMC_CKGR_PLLAR_MUL_SHIFT (18) /* Bits 18-24: PLLA Multiplier */ #define PMC_CKGR_PLLAR_MUL_MASK (0x7f << PMC_CKGR_PLLAR_MUL_SHIFT) +# define PMC_CKGR_PLLAR_MUL(n) ((uint32_t)(n) << PMC_CKGR_PLLAR_MUL_SHIFT) #define PMC_CKGR_PLLAR_ONE (1 << 29) /* Bit 29: Always one */ /* PMC Master Clock Register */ diff --git a/nuttx/arch/arm/src/sama5/sam_clockconfig.c b/nuttx/arch/arm/src/sama5/sam_clockconfig.c index 769d63fbe..2c5fa7d0e 100644 --- a/nuttx/arch/arm/src/sama5/sam_clockconfig.c +++ b/nuttx/arch/arm/src/sama5/sam_clockconfig.c @@ -225,12 +225,13 @@ static inline void __ramfunc__ sam_pllasetup(void) /* Configure PLLA */ #ifdef SAMA5_HAVE_PLLAR_DIV - regval = (BOARD_CKGR_PLLAR_DIV | BOARD_CKGR_PLLAR_COUNT | - BOARD_CKGR_PLLAR_OUT | BOARD_CKGR_PLLAR_MUL | + regval = (BOARD_CKGR_PLLAR_DIV | BOARD_CKGR_PLLAR_COUNT | + BOARD_CKGR_PLLAR_OUT | BOARD_CKGR_PLLAR_MUL | PMC_CKGR_PLLAR_ONE); #else - regval = (BOARD_CKGR_PLLAR_COUNT | BOARD_CKGR_PLLAR_OUT | - BOARD_CKGR_PLLAR_MUL | PMC_CKGR_PLLAR_ONE); + regval = (PMC_CKGR_PLLAR_DIV_BYPASS | BOARD_CKGR_PLLAR_COUNT | + BOARD_CKGR_PLLAR_OUT | BOARD_CKGR_PLLAR_MUL | + PMC_CKGR_PLLAR_ONE); #endif putreg32(regval, SAM_PMC_CKGR_PLLAR); diff --git a/nuttx/configs/sama5d4-ek/ramtest/defconfig b/nuttx/configs/sama5d4-ek/ramtest/defconfig index 899ec9ab8..dbdbcebe0 100644 --- a/nuttx/configs/sama5d4-ek/ramtest/defconfig +++ b/nuttx/configs/sama5d4-ek/ramtest/defconfig @@ -217,7 +217,7 @@ CONFIG_SAMA5_MPDDRC=y # External Memory Configuration # CONFIG_SAMA5_DDRCS=y -CONFIG_SAMA5_DDRCS_SIZE=26843456 +CONFIG_SAMA5_DDRCS_SIZE=268435456 # CONFIG_SAMA5_DDRCS_LPDDR1 is not set CONFIG_SAMA5_DDRCS_LPDDR2=y # CONFIG_SAMA5_EBICS0 is not set |