diff options
-rw-r--r-- | nuttx/ChangeLog | 4 | ||||
-rw-r--r-- | nuttx/arch/arm/src/kl/Kconfig | 4 | ||||
-rw-r--r-- | nuttx/arch/arm/src/kl/Make.defs | 12 | ||||
-rw-r--r-- | nuttx/arch/arm/src/kl/chip/kl_sim.h | 2 | ||||
-rw-r--r-- | nuttx/arch/arm/src/kl/chip/kl_spi.h | 5 | ||||
-rwxr-xr-x | nuttx/arch/arm/src/kl/kl_spi.c | 737 | ||||
-rw-r--r-- | nuttx/arch/arm/src/kl/kl_spi.h | 72 | ||||
-rw-r--r-- | nuttx/arch/arm/src/kl/kl_start.c | 1 | ||||
-rw-r--r-- | nuttx/arch/arm/src/lpc17xx/lpc17_spi.c | 18 |
9 files changed, 797 insertions, 58 deletions
diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index c4d29d7fe..e44edb6dd 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -5006,6 +5006,6 @@ Freedom KL25Z board from Alan Carvalho de Assis (2013-6-18). * arch/arm/src/sam34/sam_spi.c: Correct an incorrect pointer test. Was checking if the wrong pointer was NULL (2013-6-18). - * arch/arm/src/kl/chip/kl_spi.h: Add SPI register definitions for - the Freescale KL25Z (2013-6-19). + * arch/arm/src/kl/kl_spi.c and chip/kl_spi.h: Add SPI driver and + register definitions for the Freescale KL25Z (2013-6-19). diff --git a/nuttx/arch/arm/src/kl/Kconfig b/nuttx/arch/arm/src/kl/Kconfig index 3a0c4873d..808ca87bc 100644 --- a/nuttx/arch/arm/src/kl/Kconfig +++ b/nuttx/arch/arm/src/kl/Kconfig @@ -79,12 +79,16 @@ config KL_FLEXCAN1 config KL_SPI0 bool "SPI0" default n + select SPI + select SPI_EXCHANGE ---help--- Support SPI0 config KL_SPI1 bool "SPI1" default n + select SPI + select SPI_EXCHANGE ---help--- Support SPI1 diff --git a/nuttx/arch/arm/src/kl/Make.defs b/nuttx/arch/arm/src/kl/Make.defs index 38c739506..e43059399 100644 --- a/nuttx/arch/arm/src/kl/Make.defs +++ b/nuttx/arch/arm/src/kl/Make.defs @@ -33,7 +33,7 @@ # ############################################################################ -HEAD_ASRC = +HEAD_ASRC = CMN_ASRCS = up_exception.S up_saveusercontext.S up_fullcontextrestore.S CMN_ASRCS += up_switchcontext.S vfork.S @@ -67,7 +67,7 @@ ifeq ($(CONFIG_DEBUG),y) CMN_CSRCS += up_dumpnvic.c endif -CHIP_ASRCS = +CHIP_ASRCS = CHIP_CSRCS = kl_clockconfig.c kl_gpio.c kl_idle.c kl_irq.c kl_irqprio.c CHIP_CSRCS += kl_lowputc.c kl_serial.c kl_start.c kl_timerisr.c kl_cfmconfig.c @@ -75,6 +75,14 @@ ifeq ($(CONFIG_NUTTX_KERNEL),y) CHIP_CSRCS += kl_userspace.c endif +ifeq ($(CONFIG_KL_SPI0),y) +CHIP_CSRCS += kl_spi.c +else +ifeq ($(CONFIG_KL_SPI1),y) +CHIP_CSRCS += kl_spi.c +endif +endif + ifeq ($(CONFIG_DEBUG),y) CHIP_CSRCS += kl_dumpgpio.c endif diff --git a/nuttx/arch/arm/src/kl/chip/kl_sim.h b/nuttx/arch/arm/src/kl/chip/kl_sim.h index de59824aa..001324eb4 100644 --- a/nuttx/arch/arm/src/kl/chip/kl_sim.h +++ b/nuttx/arch/arm/src/kl/chip/kl_sim.h @@ -260,7 +260,7 @@ #define SIM_SCGC4_USBOTG (1 << 18) /* Bit 18: USB Clock Gate Control */ #define SIM_SCGC4_CMP (1 << 19) /* Bit 19: Comparator Clock Gate Control */ /* Bits 20-21: Reserved */ -#define SIM_SCGC4_SPI10 (1 << 22) /* Bit 22: SPI0 Clock Gate Control */ +#define SIM_SCGC4_SPI0 (1 << 22) /* Bit 22: SPI0 Clock Gate Control */ #define SIM_SCGC4_SPI1 (1 << 23) /* Bit 23: SPI1 Clock Gate Control */ /* Bits 24-31: Reserved */ /* System Clock Gating Control Register 5 */ diff --git a/nuttx/arch/arm/src/kl/chip/kl_spi.h b/nuttx/arch/arm/src/kl/chip/kl_spi.h index b9bfa1ad3..f24633457 100644 --- a/nuttx/arch/arm/src/kl/chip/kl_spi.h +++ b/nuttx/arch/arm/src/kl/chip/kl_spi.h @@ -77,7 +77,6 @@ /* SPI control register 1 */ - #define SPI_C1_LSBFE (1 << 0) /* Bit 0: LSB first (shifter direction) */ #define SPI_C1_SSOE (1 << 1) /* Bit 1: Slave select output enable */ #define SPI_C1_CPHA (1 << 2) /* Bit 2: Clock phase */ @@ -87,7 +86,6 @@ #define SPI_C1_SPE (1 << 6) /* Bit 6: SPI system enable */ #define SPI_C1_SPIE (1 << 7) /* Bit 7: SPI interrupt enable: for SPRF and MODF */ - /* SPI control register 2 */ #define SPI_C2_SPC0 (1 << 0) /* Bit 0: SPI pin control 0 */ @@ -102,6 +100,7 @@ #define SPI_BR_SPR_SHIFT (0) /* Bits 0-3: SPI baud rate divisor */ #define SPI_BR_SPR_MASK (15 << SPI_BR_SPR_SHIFT) +# define SPI_BR_SPR_DIV(n) (((n)-1) << SPI_BR_SPR_SHIFT) /* Baud rate divisor is 2^(n-1) */ # define SPI_BR_SPR_DIV2 (0 << SPI_BR_SPR_SHIFT) /* Baud rate divisor is 2 */ # define SPI_BR_SPR_DIV4 (1 << SPI_BR_SPR_SHIFT) /* Baud rate divisor is 4 */ # define SPI_BR_SPR_DIV8 (2 << SPI_BR_SPR_SHIFT) /* Baud rate divisor is 8 */ @@ -113,7 +112,7 @@ # define SPI_BR_SPR_DIV512 (8 << SPI_BR_SPR_SHIFT) /* Baud rate divisor is 512 */ #define SPI_BR_SPPR_SHIFT (4) /* Bits 4-6: SPI baud rate prescale divisor */ #define SPI_BR_SPPR_MASK (7 << SPI_BR_SPPR_SHIFT) -# define SPI_BR_SPPR(n) (((n)-1) << SPI_BR_SPPR_SHIFT) /* Prescaler=n, n=1-8 */ +# define SPI_BR_SPPR(n) (((n)-1) << SPI_BR_SPPR_SHIFT) /* Prescaler=n, n=1-8 */ /* Bit 7: Reserved */ /* SPI status register */ /* Bits 0-3: Reserved */ diff --git a/nuttx/arch/arm/src/kl/kl_spi.c b/nuttx/arch/arm/src/kl/kl_spi.c new file mode 100755 index 000000000..9d9e2adfa --- /dev/null +++ b/nuttx/arch/arm/src/kl/kl_spi.c @@ -0,0 +1,737 @@ +/**************************************************************************** + * arch/arm/src/kl/kl_start.c + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include <stdint.h> +#include <semaphore.h> +#include <errno.h> +#include <assert.h> +#include <debug.h> + +#include <nuttx/spi.h> +#include <arch/irq.h> +#include <arch/board/board.h> + +#include "up_arch.h" +#include "kl_spi.h" +#include "kl_gpio.h" +#include "chip/kl_memorymap.h" +#include "chip/kl_spi.h" +#include "chip/kl_pinmux.h" + +#if defined(CONFIG_KL_SPI0) || defined(CONFIG_KL_SPI1) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ +/* Debug ********************************************************************/ +/* The following enable debug output from this file: + * + * CONFIG_DEBUG - Define to enable general debug features + * CONFIG_DEBUG_SPI - Define to enable basic SSP debug (needs CONFIG_DEBUG) + * CONFIG_DEBUG_VERBOSE - Define to enable verbose SSP debug + */ + +#ifdef CONFIG_DEBUG_SPI +# define spidbg lldbg +# ifdef CONFIG_DEBUG_VERBOSE +# define spivdbg lldbg +# else +# define spivdbg(x...) +# endif +#else +# define spidbg(x...) +# define spivdbg(x...) +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct kl_spidev_s +{ + struct spi_dev_s spidev; /* Externally visible part of the SPI interface */ + uint32_t spibase; /* Base address of SPI registers */ +#ifndef CONFIG_SPI_OWNBUS + sem_t exclsem; /* Held while chip is selected for mutual exclusion */ + uint32_t frequency; /* Requested clock frequency */ + uint32_t actual; /* Actual clock frequency */ + uint8_t nbits; /* Width of word in bits (8 to 16) */ + uint8_t mode; /* Mode 0,1,2,3 */ +#endif +}; + +/************************************************************************************ + * Private Function Prototypes + ************************************************************************************/ + +/* Helpers */ + +static inline uint8_t spi_getreg(FAR struct kl_spidev_s *priv, uint8_t offset); +static inline void spi_putreg(FAR struct kl_spidev_s *priv, uint8_t offset, + uint8_t value); + +/* SPI methods */ + +#ifndef CONFIG_SPI_OWNBUS +static int spi_lock(FAR struct spi_dev_s *dev, bool lock); +#endif +static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency); +static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode); +static void spi_setbits(FAR struct spi_dev_s *dev, int nbits); +static uint16_t spi_send(FAR struct spi_dev_s *dev, uint16_t wd); +static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer, + FAR void *rxbuffer, size_t nwords); +#ifndef CONFIG_SPI_EXCHANGE +static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *txbuffer, + size_t nwords); +static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *rxbuffer, + size_t nwords); +#endif + +/************************************************************************************ + * Private Data + ************************************************************************************/ + +#ifdef CONFIG_KL_SPI0 +static const struct spi_ops_s g_sp0iops = +{ +#ifndef CONFIG_SPI_OWNBUS + .lock = spi_lock, +#endif + .select = kl_spi0select, + .setfrequency = spi_setfrequency, + .setmode = spi_setmode, + .setbits = spi_setbits, + .status = kl_spi0status, +#ifdef CONFIG_SPI_CMDDATA + .cmddata = kl_spi0cmddata, +#endif + .send = spi_send, +#ifdef CONFIG_SPI_EXCHANGE + .exchange = spi_exchange, +#else + .sndblock = spi_sndblock, + .recvblock = spi_recvblock, +#endif + .registercallback = 0, +}; + +static struct kl_spidev_s g_spi0dev = +{ + .spidev = { &g_sp0iops }, + .spibase = KL_SPI0_BASE, +}; +#endif + +#ifdef CONFIG_KL_SPI1 +static const struct spi_ops_s g_spi1ops = +{ +#ifndef CONFIG_SPI_OWNBUS + .lock = spi_lock, +#endif + .select = kl_spi1select, + .setfrequency = spi_setfrequency, + .setmode = spi_setmode, + .setbits = spi_setbits, + .status = kl_spi1status, +#ifdef CONFIG_SPI_CMDDATA + .cmddata = kl_spi1cmddata, +#endif + .send = spi_send, +#ifdef CONFIG_SPI_EXCHANGE + .exchange = spi_exchange, +#else + .sndblock = spi_sndblock, + .recvblock = spi_recvblock, +#endif + .registercallback = 0, +}; + +static struct kl_spidev_s g_spi1dev = +{ + .spidev = { &g_spi1ops }, + .spibase = KL_SPI1_BASE, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/************************************************************************************ + * Name: spi_getreg + * + * Description: + * Get the contents of the SPI register at offset + * + * Input Parameters: + * priv - private SPI device structure + * offset - offset to the register of interest + * + * Returned Value: + * The contents of the 16-bit register + * + ************************************************************************************/ + +static inline uint8_t spi_getreg(FAR struct kl_spidev_s *priv, uint8_t offset) +{ + return getreg8(priv->spibase + offset); +} + +/************************************************************************************ + * Name: spi_putreg + * + * Description: + * Write a 16-bit value to the SPI register at offset + * + * Input Parameters: + * priv - private SPI device structure + * offset - offset to the register of interest + * value - the 16-bit value to be written + * + * Returned Value: + * The contents of the 16-bit register + * + ************************************************************************************/ + +static inline void spi_putreg(FAR struct kl_spidev_s *priv, uint8_t offset, + uint8_t value) +{ + putreg8(value, priv->spibase + offset); +} + +/************************************************************************************ + * Name: spi_lock + * + * Description: + * On SPI busses where there are multiple devices, it will be necessary to + * lock SPI to have exclusive access to the busses for a sequence of + * transfers. The bus should be locked before the chip is selected. After + * locking the SPI bus, the caller should then also call the setfrequency, + * setbits, and setmode methods to make sure that the SPI is properly + * configured for the device. If the SPI buss is being shared, then it + * may have been left in an incompatible state. + * + * Input Parameters: + * dev - Device-specific state data + * lock - true: Lock spi bus, false: unlock SPI bus + * + * Returned Value: + * None + * + ************************************************************************************/ + +#ifndef CONFIG_SPI_OWNBUS +static int spi_lock(FAR struct spi_dev_s *dev, bool lock) +{ + FAR struct kl_spidev_s *priv = (FAR struct kl_spidev_s *)dev; + + if (lock) + { + /* Take the semaphore (perhaps waiting) */ + + while (sem_wait(&priv->exclsem) != 0) + { + /* The only case that an error should occur here is if the wait was awakened + * by a signal. + */ + + ASSERT(errno == EINTR); + } + } + else + { + (void)sem_post(&priv->exclsem); + } + return OK; +} +#endif + +/************************************************************************************ + * Name: spi_setfrequency + * + * Description: + * Set the SPI frequency. + * + * Input Parameters: + * dev - Device-specific state data + * frequency - The SPI frequency requested + * + * Returned Value: + * Returns the actual frequency selected + * + ************************************************************************************/ + +static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency) +{ + FAR struct kl_spidev_s *priv = (FAR struct kl_spidev_s *)dev; + uint32_t divisor; + uint32_t actual; + unsigned int spr; + unsigned int sppr; + + /* Check if the requested frequence is the same as the frequency selection */ + + DEBUGASSERT(priv && frequency <= SPI_CLOCK / 2); +#ifndef CONFIG_SPI_OWNBUS + if (priv->frequency == frequency) + { + /* We are already at this frequency. Return the actual. */ + + return priv->actual; + } +#endif + + /* The clock source for the SPI baud rate generator is the bus clock. We + * need to pick a prescaler value 1, 2, 3, 4, 5, 6, 7, or 8 and then a + * divisor in the range {2, 4, 8, 16, 32, 64, 128, 256, or 512). + * + * + * BaudRateDivisor = (SPPR + 1) × 2^(SPR + 1) + * BaudRate = BusClock / BaudRateDivisor + * + * The strategy is to pick the smallest divisor that yields an in-range + * solution. I am not sure if this *always* results in an optimal solution. + * But consider, for example, with a 24Mhz bus clock and a target of 400KHz + * + * target divisor is 24,000,000 / 400,000 = 60 + * spr = 1 -> sppr = 60 / (1 << 1) = 30 -> out of range + * spr = 2 -> sppr = 60 / (1 << 2) = 15 -> out of range + * spr = 3 -> sppr = 60 / (1 << 3) = 7 -> actual = 24000000 / 7 * 8 = 428571 + * spr = 4 -> sppr = 60 / (1 << 4) = 3 -> actual = 24000000 / 3 * 16 = 500000 + * spr = 5 -> sppr = 60 / (1 << 5) = 1 -> actual = 24000000 / 1 * 32 = 750000 + */ + + divisor = BOARD_BUSCLK_FREQ / frequency; + for (spr = 1; spr < 10; spr++) + { + sppr = divisor / (1 << spr); + if (sppr < 9) + { + break; + } + } + + /* Handle failures to find a solution by forcing spr to the maximum value */ + + DEBUGASSERT(spr < 10); + if (spr > 9) + { + spr = 9; + sppr = divisor / 512; + } + + /* Write the new dividers to the BR register */ + + spi_putreg(priv, KL_SPI_BR_OFFSET, SPI_BR_SPR_DIV(spr) | SPI_BR_SPPR(sppr)); + + /* Calculate the actual divisor and frequency */ + + divisor = sppr * (1 << spr); + actual = BOARD_BUSCLK_FREQ / divisor; + + /* Save the frequency setting */ + +#ifndef CONFIG_SPI_OWNBUS + priv->frequency = frequency; + priv->actual = actual; +#endif + + spidbg("Frequency %d->%d\n", frequency, actual); + return actual; +} + +/************************************************************************************ + * Name: spi_setmode + * + * Description: + * Set the SPI mode. see enum spi_mode_e for mode definitions + * + * Input Parameters: + * dev - Device-specific state data + * mode - The SPI mode requested + * + * Returned Value: + * Returns the actual frequency selected + * + ************************************************************************************/ + +static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode) +{ + FAR struct kl_spidev_s *priv = (FAR struct kl_spidev_s *)dev; + uint8_t regval; + + spivdbg("mode=%d\n", mode); + + /* Has the mode changed? */ + +#ifndef CONFIG_SPI_OWNBUS + if (mode != priv->mode) + { +#endif + /* Yes... Set C1 appropriately */ + + regval = spi_getreg(priv, KL_SPI_C1_OFFSET); + regval &= ~(SPI_C1_CPOL | SPI_C1_CPHA); + + switch (mode) + { + case SPIDEV_MODE0: /* CPOL=0; CPHA=0 */ + break; + + case SPIDEV_MODE1: /* CPOL=0; CPHA=1 */ + regval |= SPI_C1_CPHA; + break; + + case SPIDEV_MODE2: /* CPOL=1; CPHA=0 */ + regval |= SPI_C1_CPOL; + break; + + case SPIDEV_MODE3: /* CPOL=1; CPHA=1 */ + regval |= (SPI_C1_CPOL | SPI_C1_CPHA); + break; + + default: + DEBUGASSERT(FALSE); + return; + } + + spi_putreg(priv, KL_SPI_C1_OFFSET, regval); + + /* Save the mode so that subsequent re-configuratins will be faster */ + +#ifndef CONFIG_SPI_OWNBUS + priv->mode = mode; + } +#endif +} + +/************************************************************************************ + * Name: spi_setbits + * + * Description: + * Set the number of bits per word. + * + * Input Parameters: + * dev - Device-specific state data + * nbits - The number of bits requested + * + * Returned Value: + * None + * + ************************************************************************************/ + +static void spi_setbits(FAR struct spi_dev_s *dev, int nbits) +{ + /* Only 8-bit mode is supported */ + + DEBUGASSERT(nbits == 8); +} + +/************************************************************************************ + * Name: spi_send + * + * Description: + * Exchange one word on SPI + * + * Input Parameters: + * dev - Device-specific state data + * wd - The word to send. the size of the data is determined by the + * number of bits selected for the SPI interface. + * + * Returned Value: + * response + * + ************************************************************************************/ + +static uint16_t spi_send(FAR struct spi_dev_s *dev, uint16_t wd) +{ + FAR struct kl_spidev_s *priv = (FAR struct kl_spidev_s *)dev; + + /* Make sure that the transmit buffer is empty */ + + while ((spi_getreg(priv, KL_SPI_S_OFFSET) & SPI_S_SPTEF) != 0); + + /* Write the data to transmitted to the SPI Data Register */ + + spi_putreg(priv, KL_SPI_D_OFFSET, (uint8_t)wd); + + /* Wait for the SPRF bit in the SPI Status Register to be set to 1. SPRF is set + * at the completion of an SPI transfer to indicate that received data may be read + * from the SPI data registr + */ + + while ((spi_getreg(priv, KL_SPI_S_OFFSET) & SPI_S_SPRF) == 0); + + /* Return the data */ + + return (uint16_t)spi_getreg(priv, KL_SPI_D_OFFSET); +} + +/************************************************************************************ + * Name: spi_exchange + * + * Description: + * Exchange a block of data on SPI without using DMA + * + * Input Parameters: + * dev - Device-specific state data + * txbuffer - A pointer to the buffer of data to be sent + * rxbuffer - A pointer to a buffer in which to receive data + * nwords - the length of data to be exchaned in units of words. + * The wordsize is determined by the number of bits-per-word + * selected for the SPI interface. If nbits <= 8, the data is + * packed into uint8_t's; if nbits >8, the data is packed into uint16_t's + * + * Returned Value: + * None + * + ************************************************************************************/ + +static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer, + FAR void *rxbuffer, size_t nwords) +{ + FAR struct kl_spidev_s *priv = (FAR struct kl_spidev_s *)dev; + FAR uint8_t *rxptr = (FAR uint8_t*)rxbuffer; + FAR uint8_t *txptr = (FAR uint8_t*)txbuffer; + uint8_t data; + + spivdbg("txbuffer=%p rxbuffer=%p nwords=%d\n", txbuffer, rxbuffer, nwords); + + /* Loop, sending each word in the user-provied data buffer. */ + + for ( ; nwords > 0; nwords--) + { + /* Get the data to send (0xff if there is no data source) */ + + if (txptr) + { + data = (uint8_t)*txptr++; + } + else + { + data = 0xff; + } + + /* Wait for any previous data written to the TDR to be transferred + * to the serializer. + */ + + while ((spi_getreg(priv, KL_SPI_S_OFFSET) & SPI_S_SPTEF) != 0); + + /* Write the data to transmitted to the Transmit Data Register (TDR) */ + + spi_putreg(priv, KL_SPI_D_OFFSET, data); + + /* Wait for the read data to be available in the data regiter */ + + while ((spi_getreg(priv, KL_SPI_S_OFFSET) & SPI_S_SPRF) == 0); + + /* Read the received data from the SPI Data Register.. + * TODO: The following only works if nbits <= 8. + */ + + data = spi_getreg(priv, KL_SPI_D_OFFSET); + if (rxptr) + { + *rxptr++ = (uint8_t)data; + } + } +} + +/************************************************************************* + * Name: spi_sndblock + * + * Description: + * Send a block of data on SPI + * + * Input Parameters: + * dev - Device-specific state data + * txbuffer - A pointer to the buffer of data to be sent + * nwords - the length of data to send from the buffer in number of words. + * The wordsize is determined by the number of bits-per-word + * selected for the SPI interface. If nbits <= 8, the data is + * packed into uint8_t's; if nbits >8, the data is packed into uint16_t's + * + * Returned Value: + * None + * + ************************************************************************************/ + +#ifndef CONFIG_SPI_EXCHANGE +static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *txbuffer, size_t nwords) +{ + spivdbg("txbuffer=%p nwords=%d\n", txbuffer, nwords); + return spi_exchange(dev, txbuffer, NULL, nwords); +} +#endif + +/************************************************************************************ + * Name: spi_recvblock + * + * Description: + * Receive a block of data from SPI + * + * Input Parameters: + * dev - Device-specific state data + * rxbuffer - A pointer to the buffer in which to recieve data + * nwords - the length of data that can be received in the buffer in number + * of words. The wordsize is determined by the number of bits-per-word + * selected for the SPI interface. If nbits <= 8, the data is + * packed into uint8_t's; if nbits >8, the data is packed into uint16_t's + * + * Returned Value: + * None + * + ************************************************************************************/ + +#ifndef CONFIG_SPI_EXCHANGE +static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *rxbuffer, size_t nwords) +{ + spivdbg("rxbuffer=%p nwords=%d\n", rxbuffer, nwords); + return spi_exchange(dev, NULL, rxbuffer, nwords); +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: kl_spiinitialize + * + * Description: + * Initialize the selected SPI port. + * + * Input Parameter: + * Port number (for hardware that has mutiple SPI interfaces) + * + * Returned Value: + * Valid SPI device structure reference on succcess; a NULL on failure + * + ****************************************************************************/ + +FAR struct spi_dev_s *kl_spiinitialize(int port) +{ + FAR struct kl_spidev_s *priv; + uint32_t regval; + + /* Configure multiplexed pins as connected on the board. Chip select pins + * must be configured by board-specific logic. Most SPI pins multiple, + * alternative pin selection. Definitions in the board.h file must be\ + * provided to resolve the board-specific pin configuration like: + * + * #define PIN_SPI0_SCK PIN_SPI0_SCK_1 + */ + +#ifdef CONFIG_KL_SPI0 + if (port == 0) + { + priv = &g_spi0dev; + + /* Configure pins for SPI0 */ + + kl_configgpio(PIN_SPI0_SCK); + kl_configgpio(PIN_SPI0_MISO); + kl_configgpio(PIN_SPI0_MOSI); + + /* Enable clocking */ + + regval = getreg32(KL_SIM_SCGC4); + regval |= SIM_SCGC4_SPI1; + putreg32(regval, KL_SIM_SCGC4); + } + else +#endif +#ifdef CONFIG_KL_SPI0 + if (port == 0) + { + priv = &g_spi1dev; + + /* Configure pins for SPI0 */ + + kl_configgpio(PIN_SPI1_SCK); + kl_configgpio(PIN_SPI1_MISO); + kl_configgpio(PIN_SPI1_MOSI); + + /* Enable clocking */ + + regval = getreg32(KL_SIM_SCGC4); + regval |= SIM_SCGC4_SPI1; + putreg32(regval, KL_SIM_SCGC4); + } + else +#endif + { + spidbg("ERROR: Port %d not configured\n", port); + return NULL; + } + + /* Configure master mode, select mode 0, MSB first. Disable interrupts. */ + + spi_putreg(priv, KL_SPI_C1_OFFSET, SPI_C1_SPIE | SPI_C1_MSTR); + + /* Disable interrupts, DMA, bidirectional mode, stop-in-wait mode, enable + * master mode fault detection + */ + + spi_putreg(priv, KL_SPI_C1_OFFSET, 0); + + /* Set the initial SPI configuration */ + +#ifndef CONFIG_SPI_OWNBUS + priv->frequency = 0; + priv->mode = SPIDEV_MODE0; +#endif + + /* Select a default frequency of approx. 400KHz */ + + spi_setfrequency((FAR struct spi_dev_s *)priv, 400000); + + /* Initialize the SPI semaphore that enforces mutually exclusive access */ + +#ifndef CONFIG_SPI_OWNBUS + sem_init(&priv->exclsem, 0, 1); +#endif + return &priv->spidev; +} + +#endif /* CONFIG_KL_SPI0 || CONFIG_KL_SPI1 */ diff --git a/nuttx/arch/arm/src/kl/kl_spi.h b/nuttx/arch/arm/src/kl/kl_spi.h index e6252a488..7b93a444d 100644 --- a/nuttx/arch/arm/src/kl/kl_spi.h +++ b/nuttx/arch/arm/src/kl/kl_spi.h @@ -1,4 +1,4 @@ -/**************************************************************************** +/************************************************************************************ * arch/arm/src/kl/kl_gpio.h * * Copyright (C) 2013 Gregory Nutt. All rights reserved. @@ -31,24 +31,26 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ****************************************************************************/ + ************************************************************************************/ #ifndef __ARCH_ARM_SRC_KL_KL_SPI_H #define __ARCH_ARM_SRC_KL_KL_SPI_H -/**************************************************************************** +/************************************************************************************ * Included Files - ****************************************************************************/ + ************************************************************************************/ #include <nuttx/config.h> -/**************************************************************************** +#if defined(CONFIG_KL_SPI0) || defined(CONFIG_KL_SPI1) + +/************************************************************************************ * Pre-processor Declarations - ****************************************************************************/ + ************************************************************************************/ -/**************************************************************************** +/************************************************************************************ * Public Data - ****************************************************************************/ + ************************************************************************************/ #ifndef __ASSEMBLY__ @@ -60,17 +62,34 @@ extern "C" { #define EXTERN extern #endif -/**************************************************************************** +/************************************************************************************ * Public Function Prototypes + ************************************************************************************/ + +/**************************************************************************** + * Name: kl_spiinitialize + * + * Description: + * Initialize the selected SPI port. + * + * Input Parameter: + * Port number (for hardware that has mutiple SPI interfaces) + * + * Returned Value: + * Valid SPI device structure reference on succcess; a NULL on failure + * ****************************************************************************/ +struct spi_dev_s; +FAR struct spi_dev_s *kl_spiinitialize(int port); + /************************************************************************************ * Name: kl_spi[n]select, kl_spi[n]status, and kl_spi[n]cmddata * * Description: * These external functions must be provided by board-specific logic. They are * implementations of the select, status, and cmddata methods of the SPI interface - * defined by struct spi_ops_s (see include/nuttx/spi.h). All other methods + * defined by struct spi_ops_s (see include/nuttx/spi.h). All other methods * including up_spiinitialize()) are provided by common Kinetis logic. To use * this common SPI logic on your board: * @@ -86,13 +105,12 @@ extern "C" { * 3. Add a call to up_spiinitialize() in your low level application * initialization logic * 4. The handle returned by up_spiinitialize() may then be used to bind the - * SPI driver to higher level logic (e.g., calling + * SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). * ************************************************************************************/ -struct spi_dev_s; enum spi_dev_e; #ifdef CONFIG_KL_SPI0 @@ -102,6 +120,7 @@ uint8_t kl_spi0status(FAR struct spi_dev_s *dev, enum spi_dev_e devid); int kl_spi0cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd); #endif #endif + #ifdef CONFIG_KL_SPI1 void kl_spi1select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected); uint8_t kl_spi1status(FAR struct spi_dev_s *dev, enum spi_dev_e devid); @@ -109,34 +128,7 @@ uint8_t kl_spi1status(FAR struct spi_dev_s *dev, enum spi_dev_e devid); int kl_spi1cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd); #endif #endif -#ifdef CONFIG_KL_SPI2 -void kl_spi2select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected); -uint8_t kl_spi2status(FAR struct spi_dev_s *dev, enum spi_dev_e devid); -#ifdef CONFIG_SPI_CMDDATA -int kl_spi2cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd); -#endif -#endif - -/**************************************************************************** - * Name: ssp_flush - * - * Description: - * Flush and discard any words left in the RX fifo. This can be called - * from spi[n]select after a device is deselected (if you worry about such - * things). - * - * Input Parameters: - * dev - Device-specific state data - * - * Returned Value: - * None - * - ****************************************************************************/ - -#if defined(CONFIG_KL_SPI0) || defined(CONFIG_KL_SPI0) || defined(CONFIG_KL_SPI2) -struct spi_dev_s; -void spi_flush(FAR struct spi_dev_s *dev); -#endif #endif /* __ASSEMBLY__ */ +#endif /* CONFIG_KL_SPI0 || CONFIG_KL_SPI1 */ #endif /* __ARCH_ARM_SRC_KL_KL_SPI_H */ diff --git a/nuttx/arch/arm/src/kl/kl_start.c b/nuttx/arch/arm/src/kl/kl_start.c index ee411be83..46f505c93 100644 --- a/nuttx/arch/arm/src/kl/kl_start.c +++ b/nuttx/arch/arm/src/kl/kl_start.c @@ -1,6 +1,5 @@ /**************************************************************************** * arch/arm/src/kl/kl_start.c - * arch/arm/src/chip/kl_start.c * * Copyright (C) 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt <gnutt@nuttx.org> diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_spi.c b/nuttx/arch/arm/src/lpc17xx/lpc17_spi.c index 75a483591..4eccb290b 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_spi.c +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_spi.c @@ -72,7 +72,7 @@ /* Debug ********************************************************************/ /* The following enable debug output from this file: - * + * * CONFIG_DEBUG - Define to enable general debug features * CONFIG_DEBUG_SPI - Define to enable basic SSP debug (needs CONFIG_DEBUG) * CONFIG_DEBUG_VERBOSE - Define to enable verbose SSP debug @@ -171,7 +171,7 @@ static const struct spi_ops_s g_spiops = static struct lpc17_spidev_s g_spidev = { .spidev = { &g_spiops }, -}; +}; /**************************************************************************** * Public Data @@ -279,7 +279,7 @@ static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency) divisor = (divisor + 1) & ~1; /* Save the new divisor value */ - + putreg32(divisor, LPC17_SPI_CCR); /* Calculate the new actual */ @@ -332,19 +332,19 @@ static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode) { case SPIDEV_MODE0: /* CPOL=0; CPHA=0 */ break; - + case SPIDEV_MODE1: /* CPOL=0; CPHA=1 */ regval |= SPI_CR_CPHA; break; - + case SPIDEV_MODE2: /* CPOL=1; CPHA=0 */ regval |= SPI_CR_CPOL; break; - + case SPIDEV_MODE3: /* CPOL=1; CPHA=1 */ regval |= (SPI_CR_CPOL|SPI_CR_CPHA); break; - + default: DEBUGASSERT(FALSE); return; @@ -527,7 +527,7 @@ static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nw (void)getreg32(LPC17_SPI_SR); - /* Read the received data from the SPI Data Register */ + /* Read the received data from the SPI Data Register */ *ptr++ = (uint8_t)getreg32(LPC17_SPI_DR); nwords--; @@ -585,7 +585,7 @@ FAR struct spi_dev_s *lpc17_spiinitialize(int port) regval |= SYSCON_PCONP_PCSPI; putreg32(regval, LPC17_SYSCON_PCONP); irqrestore(flags); - + /* Configure 8-bit SPI mode and master mode */ putreg32(SPI_CR_BITS_8BITS|SPI_CR_BITENABLE|SPI_CR_MSTR, LPC17_SPI_CR); |