diff options
| -rw-r--r-- | nuttx/arch/arm/src/stm32/chip/stm32_pwr.h | 6 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/stm32/stm32_lowputc.c | 2 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/stm32/stm32_pwr.c | 53 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/stm32/stm32_pwr.h | 27 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/stm32/stm32_serial.c | 1 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/stm32/stm32l15xxx_rcc.c | 25 | ||||
| -rw-r--r-- | nuttx/configs/stm32ldiscovery/include/board.h | 129 | ||||
| -rw-r--r-- | nuttx/configs/stm32ldiscovery/nsh/defconfig | 2 |
8 files changed, 170 insertions, 75 deletions
diff --git a/nuttx/arch/arm/src/stm32/chip/stm32_pwr.h b/nuttx/arch/arm/src/stm32/chip/stm32_pwr.h index 9f1220ba9..430624d3b 100644 --- a/nuttx/arch/arm/src/stm32/chip/stm32_pwr.h +++ b/nuttx/arch/arm/src/stm32/chip/stm32_pwr.h @@ -108,9 +108,9 @@ # define PWR_CR_ULP (1 << 9) /* Ultralow power mode */ # define PWR_CR_FWU (1 << 10) /* Low power run mode */ # define PWR_CR_VOS_MASK (3 << 11) /* Bits 11-12: Regulator voltage scaling output selection */ -# define PWR_CR_VOS_SCALE_1 (1 << 11) /* 1.8 V (range 1) */ -# define PWR_CR_VOS_SCALE_2 (2 << 11) /* 1.5 V (range 2) */ -# define PWR_CR_VOS_SCALE_3 (3 << 11) /* 1.2 V (range 3) */ +# define PWR_CR_VOS_SCALE_1 (1 << 11) /* 1.8 V (range 1) PLL VCO Max = 96MHz */ +# define PWR_CR_VOS_SCALE_2 (2 << 11) /* 1.5 V (range 2) PLL VCO Max = 64MHz */ +# define PWR_CR_VOS_SCALE_3 (3 << 11) /* 1.2 V (range 3) PLL VCO Max = 24MHz */ # define PWR_CR_LPRUN (1 << 14) /* Low power run mode */ #endif diff --git a/nuttx/arch/arm/src/stm32/stm32_lowputc.c b/nuttx/arch/arm/src/stm32/stm32_lowputc.c index 49ac15e9a..f733aad80 100644 --- a/nuttx/arch/arm/src/stm32/stm32_lowputc.c +++ b/nuttx/arch/arm/src/stm32/stm32_lowputc.c @@ -621,5 +621,3 @@ void stm32_lowsetup(void) #else # error "Unsupported STM32 chip" #endif - - diff --git a/nuttx/arch/arm/src/stm32/stm32_pwr.c b/nuttx/arch/arm/src/stm32/stm32_pwr.c index 14149922f..1c9513541 100644 --- a/nuttx/arch/arm/src/stm32/stm32_pwr.c +++ b/nuttx/arch/arm/src/stm32/stm32_pwr.c @@ -2,7 +2,9 @@ * arch/arm/src/stm32/stm32_pwr.c * * Copyright (C) 2011 Uros Platise. All rights reserved. - * Author: Uros Platise <uros.platise@isotel.eu> + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Authors: Uros Platise <uros.platise@isotel.eu> + * Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -58,17 +60,17 @@ static inline uint16_t stm32_pwr_getreg(uint8_t offset) { - return getreg32(STM32_PWR_BASE + offset); + return (uint16_t)getreg32(STM32_PWR_BASE + (uint32_t)offset); } static inline void stm32_pwr_putreg(uint8_t offset, uint16_t value) { - putreg32(value, STM32_PWR_BASE + offset); + putreg32((uint32_t)value, STM32_PWR_BASE + (uint32_t)offset); } static inline void stm32_pwr_modifyreg(uint8_t offset, uint16_t clearbits, uint16_t setbits) { - modifyreg32(STM32_PWR_BASE + offset, clearbits, setbits); + modifyreg32(STM32_PWR_BASE + (uint32_t)offset, (uint32_t)clearbits, (uint32_t)setbits); } /************************************************************************************ @@ -95,4 +97,47 @@ void stm32_pwr_enablebkp(void) stm32_pwr_modifyreg(STM32_PWR_CR_OFFSET, 0, PWR_CR_DBP); } +/************************************************************************************ + * Name: stm32_pwr_setvos + * + * Description: + * Set voltage scaling for EneryLite devices. + * + * Input Parameters: + * vos - Properly aligned voltage scaling select bits for the PWR_CR register. + * + * Returned Values: + * None + * + * Assumptions: + * At present, this function is called only from initialization logic. If used + * for any other purpose that protection to assure that its operation is atomic + * will be required. + * + ************************************************************************************/ + +#ifdef CONFIG_STM32_ENERGYLITE +void stm32_pwr_setvos(uint16_t vos) +{ + uint16_t regval; + + /* The following sequence is required to program the voltage regulator ranges: + * 1. Check VDD to identify which ranges are allowed... + * 2. Poll VOSF bit of in PWR_CSR. Wait until it is reset to 0. + * 3. Configure the voltage scaling range by setting the VOS bits in the PWR_CR + * register. + * 4. Poll VOSF bit of in PWR_CSR register. Wait until it is reset to 0. + */ + + while((stm32_pwr_getreg(STM32_PWR_CSR_OFFSET) & PWR_CSR_VOSF) != 0); + + regval = stm32_pwr_getreg(STM32_PWR_CR_OFFSET); + regval &= ~PWR_CR_VOS_MASK; + regval |= (vos & PWR_CR_VOS_MASK); + stm32_pwr_putreg(STM32_PWR_CR_OFFSET, regval); + + while((stm32_pwr_getreg(STM32_PWR_CSR_OFFSET) & PWR_CSR_VOSF) != 0); +} +#endif + #endif /* CONFIG_STM32_PWR */ diff --git a/nuttx/arch/arm/src/stm32/stm32_pwr.h b/nuttx/arch/arm/src/stm32/stm32_pwr.h index 7a2751677..63ae14429 100644 --- a/nuttx/arch/arm/src/stm32/stm32_pwr.h +++ b/nuttx/arch/arm/src/stm32/stm32_pwr.h @@ -1,7 +1,7 @@ /************************************************************************************ * arch/arm/src/stm32/stm32_pwr.h * - * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without @@ -78,7 +78,30 @@ extern "C" { * ************************************************************************************/ -EXTERN void stm32_pwr_enablebkp(void); +void stm32_pwr_enablebkp(void); + +/************************************************************************************ + * Name: stm32_pwr_setvos + * + * Description: + * Set voltage scaling for EneryLite devices. + * + * Input Parameters: + * vos - Properly aligned voltage scaling select bits for the PWR_CR register. + * + * Returned Values: + * None + * + * Assumptions: + * At present, this function is called only from initialization logic. If used + * for any other purpose that protection to assure that its operation is atomic + * will be required. + * + ************************************************************************************/ + +#ifdef CONFIG_STM32_ENERGYLITE +void stm32_pwr_setvos(uint16_t vos); +#endif #undef EXTERN #if defined(__cplusplus) diff --git a/nuttx/arch/arm/src/stm32/stm32_serial.c b/nuttx/arch/arm/src/stm32/stm32_serial.c index 4a06faee6..af95244f0 100644 --- a/nuttx/arch/arm/src/stm32/stm32_serial.c +++ b/nuttx/arch/arm/src/stm32/stm32_serial.c @@ -1214,6 +1214,7 @@ static void up_setspeed(struct uart_dev_s *dev) static int up_setup(struct uart_dev_s *dev) { struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + #ifndef CONFIG_SUPPRESS_UART_CONFIG uint32_t regval; diff --git a/nuttx/arch/arm/src/stm32/stm32l15xxx_rcc.c b/nuttx/arch/arm/src/stm32/stm32l15xxx_rcc.c index e8895dd89..1063c27c1 100644 --- a/nuttx/arch/arm/src/stm32/stm32l15xxx_rcc.c +++ b/nuttx/arch/arm/src/stm32/stm32l15xxx_rcc.c @@ -1,5 +1,7 @@ /**************************************************************************** * arch/arm/src/stm32/stm32l15xxx_rcc.c + * For STM32L100xx, STM32L151xx, STM32L152xx and STM32L162xx advanced ARM- + * based 32-bit MCUs * * Copyright (C) 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt <gnutt@nuttx.org> @@ -134,7 +136,11 @@ static inline void rcc_reset(void) putreg32(0, STM32_RCC_CIR); /* Disable all interrupts */ - /* Rest the FLASH controller to 32-bit mode, no wait states. + /* Go to the (default) voltage range 2 */ + + stm32_pwr_setvos(PWR_CR_VOS_SCALE_2); + + /* Reset the FLASH controller to 32-bit mode, no wait states. * * First, program the new number of WS to the LATENCY bit in Flash access * control register (FLASH_ACR) @@ -490,8 +496,21 @@ static void stm32_stdclockconfig(void) { uint32_t regval; - /* First, enable the source clock only the PLL (via HSE or HSI), HSE, and HSI - * are supported in this implementation. + /* Go to the high performance voltage range 1 if necessary. In this mode, + * the PLL VCO frequency can be up to 96MHz. USB and SDIO can be supported. + * + * Range 1: PLLVCO up to 96MHz in range 1 (1.8V) + * Range 2: PLLVCO up to 48MHz in range 2 (1.5V) + * Range 3: PLLVCO up to 24MHz in range 3 (1.2V) + */ + +#if STM32_PLL_FREQUENCY > 48000000 + stm32_pwr_setvos(PWR_CR_VOS_SCALE_1); +#endif + + /* Enable the source clock for the PLL (via HSE or HSI), HSE, and HSI. + * NOTE that only PLL, HSE, or HSI are supported for the system clock + * in this implementation */ #if (STM32_CFGR_PLLSRC == RCC_CFGR_PLLSRC) || (STM32_SYSCLK_SW == RCC_CFGR_SW_HSE) diff --git a/nuttx/configs/stm32ldiscovery/include/board.h b/nuttx/configs/stm32ldiscovery/include/board.h index d6f57492f..83edb182c 100644 --- a/nuttx/configs/stm32ldiscovery/include/board.h +++ b/nuttx/configs/stm32ldiscovery/include/board.h @@ -75,21 +75,21 @@ * Driven by 32.768KHz crystal (X2) on the OSC32_IN and OSC32_OUT pins. */ -#define STM32_BOARD_XTAL 8000000ul /* X3 on board (not fitted)*/ +#define STM32_BOARD_XTAL 8000000ul /* X3 on board (not fitted)*/ -#define STM32_HSI_FREQUENCY 16000000ul /* Approximately 16MHz */ -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL -#define STM32_MSI_FREQUENCY 2097000 /* Default is approximately 2.097Mhz */ -#define STM32_LSI_FREQUENCY 37000 /* Approximately 37KHz */ -#define STM32_LSE_FREQUENCY 32768 /* X2 on board */ +#define STM32_HSI_FREQUENCY 16000000ul /* Approximately 16MHz */ +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_MSI_FREQUENCY 2097000 /* Default is approximately 2.097Mhz */ +#define STM32_LSI_FREQUENCY 37000 /* Approximately 37KHz */ +#define STM32_LSE_FREQUENCY 32768 /* X2 on board */ /* PLL Configuration * * - PLL source is HSI -> 16MHz input (nominal) - * - PLL multipler is 4 -> 64MHz PLL VCO clock output - * - PLL output divider 2 -> 32MHz divided down PLL VCO clock output + * - PLL multipler is 6 -> 96MHz PLL VCO clock output (for USB) + * - PLL output divider 3 -> 32MHz divided down PLL VCO clock output * - * Resulting SYSCLK frequency is 16MHz x 4 / 2 = 32MHz + * Resulting SYSCLK frequency is 16MHz x 6 / 3 = 32MHz * * USB/SDIO: * If the USB or SDIO interface is used in the application, the PLL VCO @@ -106,50 +106,60 @@ * The minimum input clock frequency for PLL is 2 MHz (when using HSE as PLL source). */ -#define STM32_CFGR_PLLSRC 0 /* Source is 16MHz HSI */ -#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx4 /* PLLMUL = 4 */ -#define STM32_CFGR_PLLDIV RCC_CFGR_PLLDIV_2 /* PLLDIV = 2 */ -#define STM32_PLL_FREQUENCY (4*STM32_HSE_FREQUENCY) /* PLL VCO Frequency is 64MHz */ +#define STM32_CFGR_PLLSRC 0 /* Source is 16MHz HSI */ +#ifdef CONFIG_STM32_USB +# define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx6 /* PLLMUL = 6 */ +# define STM32_CFGR_PLLDIV RCC_CFGR_PLLDIV_3 /* PLLDIV = 3 */ +# define STM32_PLL_FREQUENCY (6*STM32_HSI_FREQUENCY) /* PLL VCO Frequency is 96MHz */ +#else +# define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx4 /* PLLMUL = 4 */ +# define STM32_CFGR_PLLDIV RCC_CFGR_PLLDIV_2 /* PLLDIV = 2 */ +# define STM32_PLL_FREQUENCY (4*STM32_HSI_FREQUENCY) /* PLL VCO Frequency is 64MHz */ +#endif -/* Use the PLL and set the SYSCLK source to be the diveded down PLL VCO output +/* Use the PLL and set the SYSCLK source to be the divided down PLL VCO output * frequency (STM32_PLL_FREQUENCY divided by the PLLDIV value). */ -#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL /* Use the PLL as the SYSCLK */ -#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL -#define STM32_SYSCLK_FREQUENCY (STM32_PLL_FREQUENCY/2) /* SYSCLK frequence is 64MHz/PLLDIV = 32MHz */ +#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL /* Use the PLL as the SYSCLK */ +#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL +#ifdef CONFIG_STM32_USB +# define STM32_SYSCLK_FREQUENCY (STM32_PLL_FREQUENCY/3) /* SYSCLK frequence is 96MHz/PLLDIV = 32MHz */ +#else +# define STM32_SYSCLK_FREQUENCY (STM32_PLL_FREQUENCY/2) /* SYSCLK frequence is 64MHz/PLLDIV = 32MHz */ +#endif /* AHB clock (HCLK) is SYSCLK (32MHz) */ -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK -#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY -#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */ +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY +#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* Same as above, to satisfy compiler */ /* APB2 clock (PCLK2) is HCLK (32MHz) */ -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK -#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY -#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK +#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY) /* APB2 timers 9, 10, and 11 will receive PCLK2. */ -#define STM32_APB2_TIM9_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM10_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM11_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM9_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM10_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM11_CLKIN (STM32_PCLK2_FREQUENCY) /* APB1 clock (PCLK1) is HCLK (32MHz) */ -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY) /* APB1 timers 2-7 will receive PCLK1 */ -#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) /* LED definitions ******************************************************************/ /* The STM32L-Discovery board has four LEDs. Two of these are controlled by @@ -172,14 +182,14 @@ /* LED index values for use with stm32_setled() */ -#define BOARD_LED1 0 /* User LD3 */ -#define BOARD_LED2 1 /* User LD4 */ -#define BOARD_NLEDS 2 +#define BOARD_LED1 0 /* User LD3 */ +#define BOARD_LED2 1 /* User LD4 */ +#define BOARD_NLEDS 2 /* LED bits for use with stm32_setleds() */ -#define BOARD_LED1_BIT (1 << BOARD_LED1) -#define BOARD_LED2_BIT (1 << BOARD_LED2) +#define BOARD_LED1_BIT (1 << BOARD_LED1) +#define BOARD_LED2_BIT (1 << BOARD_LED2) /* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 8 LEDs on board the * STM32L-Discovery. The following definitions describe how NuttX controls the LEDs: @@ -198,14 +208,14 @@ * LED_IDLE STM32 is is sleep mode Not used */ -#define LED_STARTED 0 -#define LED_HEAPALLOCATE 0 -#define LED_IRQSENABLED 0 -#define LED_STACKCREATED 1 -#define LED_INIRQ 2 -#define LED_SIGNAL 2 -#define LED_ASSERTION 2 -#define LED_PANIC 3 +#define LED_STARTED 0 +#define LED_HEAPALLOCATE 0 +#define LED_IRQSENABLED 0 +#define LED_STACKCREATED 1 +#define LED_INIRQ 2 +#define LED_SIGNAL 2 +#define LED_ASSERTION 2 +#define LED_PANIC 3 /* Button definitions ***************************************************************/ /* The STM32L-Discovery supports two buttons; only one button is controllable by @@ -215,13 +225,12 @@ * B2 RESET: pushbutton connected to NRST is used to RESET the STM32L152RBT6. */ -#define BUTTON_USER 0 - -#define NUM_BUTTONS 1 +#define BUTTON_USER 0 +#define NUM_BUTTONS 1 -#define BUTTON_USER_BIT (1 << BUTTON_USER) +#define BUTTON_USER_BIT (1 << BUTTON_USER) -/* Alternat Pin Functions **********************************************************/ +/* Alternate Pin Functions **********************************************************/ /* The STM32L-Discovery has no on-board RS-232 driver. Further, there are no USART * pins that do not conflict with the on board resources, in particular, the LCD: * Most USART pins are available if the LCD is enabled; USART2 may be used if either @@ -244,25 +253,25 @@ #if !defined(CONFIG_STM32_LCD) /* Select PA9 and PA10 if the LCD is not enabled */ -# define GPIO_USART1_RX GPIO_USART1_RX_1 -# define GPIO_USART1_TX GPIO_USART1_TX_1 +# define GPIO_USART1_RX GPIO_USART1_RX_1 +# define GPIO_USART1_TX GPIO_USART1_TX_1 /* This there are no other options for USART1 on this part */ -# define GPIO_USART2_RX GPIO_USART2_RX_1 -# define GPIO_USART2_TX GPIO_USART2_TX_1 +# define GPIO_USART2_RX GPIO_USART2_RX_1 +# define GPIO_USART2_TX GPIO_USART2_TX_1 /* Arbirtrarily select PB10 and PB11 */ -# define GPIO_USART3_RX GPIO_USART3_RX_1 -# define GPIO_USART3_TX GPIO_USART3_TX_1 +# define GPIO_USART3_RX GPIO_USART3_RX_1 +# define GPIO_USART3_TX GPIO_USART3_TX_1 #elif !defined(CONFIG_ARCH_LEDS) /* Select PB6 and PB7 if the LEDs are not enabled */ -# define GPIO_USART1_RX GPIO_USART1_RX_2 -# define GPIO_USART1_TX GPIO_USART1_TX_2 +# define GPIO_USART1_RX GPIO_USART1_RX_2 +# define GPIO_USART1_TX GPIO_USART1_TX_2 #endif diff --git a/nuttx/configs/stm32ldiscovery/nsh/defconfig b/nuttx/configs/stm32ldiscovery/nsh/defconfig index 97fdf010b..e3f20a28e 100644 --- a/nuttx/configs/stm32ldiscovery/nsh/defconfig +++ b/nuttx/configs/stm32ldiscovery/nsh/defconfig @@ -266,7 +266,7 @@ CONFIG_ARCH_HAVE_RAMVECTORS=y # # Board Settings # -CONFIG_BOARD_LOOPSPERMSEC=2500 +CONFIG_BOARD_LOOPSPERMSEC=2796 # CONFIG_ARCH_CALIBRATION is not set CONFIG_DRAM_START=0x20000000 CONFIG_DRAM_SIZE=16384 |