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-rw-r--r--apps/examples/pwm/pwm_main.c2
-rw-r--r--nuttx/ChangeLog3
-rw-r--r--nuttx/arch/arm/src/stm32/chip/stm32_tim.h60
-rw-r--r--nuttx/arch/arm/src/stm32/stm32_dumpgpio.c37
-rwxr-xr-xnuttx/configs/stm3240g-eval/README.txt10
5 files changed, 64 insertions, 48 deletions
diff --git a/apps/examples/pwm/pwm_main.c b/apps/examples/pwm/pwm_main.c
index 501667ae7..465fa8d5d 100644
--- a/apps/examples/pwm/pwm_main.c
+++ b/apps/examples/pwm/pwm_main.c
@@ -114,7 +114,7 @@ static void pwm_help(FAR struct pwm_state_s *pwm)
message(" [-t duration] is the duration of the pulse train in seconds. "
"Default: %d Current: %d\n",
CONFIG_EXAMPLES_PWM_DURATION, pwm->duration);
- message(" [-t] shows this message and exits\n");
+ message(" [-h] shows this message and exits\n");
}
/****************************************************************************
diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog
index d2e9ff1f1..ec26460ff 100644
--- a/nuttx/ChangeLog
+++ b/nuttx/ChangeLog
@@ -2355,4 +2355,5 @@
way of managing UART pin configurations.
* include/nuttx/pwm.h, drivers/pwm.c, arch/arm/src/stm32/stm32_pwm.c: Add
support for pulse count in order to better support stepper motors.
-
+ * arch/arm/src/stm32/stm32_dumpgpio.c: Checking wrong register to see if
+ GPIO is enabled. Also not adding the GPIO base address to several offsets.
diff --git a/nuttx/arch/arm/src/stm32/chip/stm32_tim.h b/nuttx/arch/arm/src/stm32/chip/stm32_tim.h
index 4ecd79b84..104eba3de 100644
--- a/nuttx/arch/arm/src/stm32/chip/stm32_tim.h
+++ b/nuttx/arch/arm/src/stm32/chip/stm32_tim.h
@@ -406,15 +406,28 @@
/* Slave mode control register */
-#define ATIM_SMCR_ETP (1 << 15) /* Bit 15: External trigger polarity */
-#define ATIM_SMCR_ECE (1 << 14) /* Bit 14: External clock enable */
-#define ATIM_SMCR_ETPS_SHIFT (12) /* Bits 13-12: External trigger prescaler */
-#define ATIM_SMCR_ETPS_MASK (3 << ATIM_SMCR_ETPS_SHIFT)
-# define ATIM_SMCR_PSCOFF (0 << ATIM_SMCR_ETPS_SHIFT) /* 00: Prescaler OFF */
-# define ATIM_SMCR_ETRPd2 (1 << ATIM_SMCR_ETPS_SHIFT) /* 01: ETRP frequency divided by 2 */
-# define ATIM_SMCR_ETRPd4 (2 << ATIM_SMCR_ETPS_SHIFT) /* 10: ETRP frequency divided by 4 */
-# define ATIM_SMCR_ETRPd8 (3 << ATIM_SMCR_ETPS_SHIFT) /* 11: ETRP frequency divided by 8 */
-#define ATIM_SMCR_ETF_SHIFT (8) /* Bits 11-8: External trigger filter */
+#define ATIM_SMCR_SMS_SHIFT (0) /* Bits 0-2: Slave mode selection */
+#define ATIM_SMCR_SMS_MASK (7 << ATIM_SMCR_SMS_SHIFT)
+# define ATIM_SMCR_DISAB (0 << ATIM_SMCR_SMS_SHIFT) /* 000: Slave mode disabled */
+# define ATIM_SMCR_ENCMD1 (1 << ATIM_SMCR_SMS_SHIFT) /* 001: Encoder mode 1 */
+# define ATIM_SMCR_ENCMD2 (2 << ATIM_SMCR_SMS_SHIFT) /* 010: Encoder mode 2 */
+# define ATIM_SMCR_ENCMD3 (3 << ATIM_SMCR_SMS_SHIFT) /* 011: Encoder mode 3 */
+# define ATIM_SMCR_RESET (4 << ATIM_SMCR_SMS_SHIFT) /* 100: Reset Mode */
+# define ATIM_SMCR_GATED (5 << ATIM_SMCR_SMS_SHIFT) /* 101: Gated Mode */
+# define ATIM_SMCR_TRIGGER (6 << ATIM_SMCR_SMS_SHIFT) /* 110: Trigger Mode */
+# define ATIM_SMCR_EXTCLK1 (7 << ATIM_SMCR_SMS_SHIFT) /* 111: External Clock Mode 1 */
+#define ATIM_SMCR_TS_SHIFT (4) /* Bits 4-6: Trigger selection */
+#define ATIM_SMCR_TS_MASK (7 << ATIM_SMCR_TS_SHIFT)
+# define ATIM_SMCR_ITR0 (0 << ATIM_SMCR_TS_SHIFT) /* 000: Internal trigger 0 (ITR0) */
+# define ATIM_SMCR_ITR1 (1 << ATIM_SMCR_TS_SHIFT) /* 001: Internal trigger 1 (ITR1) */
+# define ATIM_SMCR_ITR2 (2 << ATIM_SMCR_TS_SHIFT) /* 010: Internal trigger 2 (ITR2) */
+# define ATIM_SMCR_ITR3 (3 << ATIM_SMCR_TS_SHIFT) /* 011: Internal trigger 3 (ITR3) */
+# define ATIM_SMCR_T1FED (4 << ATIM_SMCR_TS_SHIFT) /* 100: TI1 Edge Detector (TI1F_ED) */
+# define ATIM_SMCR_TI1FP1 (5 << ATIM_SMCR_TS_SHIFT) /* 101: Filtered Timer Input 1 (TI1FP1) */
+# define ATIM_SMCR_T12FP2 (6 << ATIM_SMCR_TS_SHIFT) /* 110: Filtered Timer Input 2 (TI2FP2) */
+# define ATIM_SMCR_ETRF (7 << ATIM_SMCR_TS_SHIFT) /* 111: External Trigger input (ETRF) */
+#define ATIM_SMCR_MSM (1 << 7) /* Bit 7: Master/slave mode */
+#define ATIM_SMCR_ETF_SHIFT (8) /* Bits 8-11: External trigger filter */
#define ATIM_SMCR_ETF_MASK (0x0f << ATIM_SMCR_ETF_SHIFT)
# define ATIM_SMCR_NOFILT (0 << ATIM_SMCR_ETF_SHIFT) /* 0000: No filter, sampling is done at fDTS */
# define ATIM_SMCR_FCKINT2 (1 << ATIM_SMCR_ETF_SHIFT) /* 0001: fSAMPLING=fCK_INT, N=2 */
@@ -432,27 +445,14 @@
# define ATIM_SMCR_FDTSd325 (13 << ATIM_SMCR_ETF_SHIFT) /* 1101: fSAMPLING=fDTS/32, N=5 */
# define ATIM_SMCR_FDTSd326 (14 << ATIM_SMCR_ETF_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */
# define ATIM_SMCR_FDTSd328 (15 << ATIM_SMCR_ETF_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */
-#define ATIM_SMCR_MSM (1 << 7) /* Bit 7: Master/slave mode */
-#define ATIM_SMCR_TS_SHIFT (4) /* Bits 6-4: Trigger selection */
-#define ATIM_SMCR_TS_MASK (7 << ATIM_SMCR_TS_SHIFT)
-# define ATIM_SMCR_ITR0 (0 << ATIM_SMCR_TS_SHIFT) /* 000: Internal trigger 0 (ITR0) */
-# define ATIM_SMCR_ITR1 (1 << ATIM_SMCR_TS_SHIFT) /* 001: Internal trigger 1 (ITR1) */
-# define ATIM_SMCR_ITR2 (2 << ATIM_SMCR_TS_SHIFT) /* 010: Internal trigger 2 (ITR2) */
-# define ATIM_SMCR_ITR3 (3 << ATIM_SMCR_TS_SHIFT) /* 011: Internal trigger 3 (ITR3) */
-# define ATIM_SMCR_T1FED (4 << ATIM_SMCR_TS_SHIFT) /* 100: TI1 Edge Detector (TI1F_ED) */
-# define ATIM_SMCR_TI1FP1 (5 << ATIM_SMCR_TS_SHIFT) /* 101: Filtered Timer Input 1 (TI1FP1) */
-# define ATIM_SMCR_T12FP2 (6 << ATIM_SMCR_TS_SHIFT) /* 110: Filtered Timer Input 2 (TI2FP2) */
-# define ATIM_SMCR_ETRF (7 << ATIM_SMCR_TS_SHIFT) /* 111: External Trigger input (ETRF) */
-#define ATIM_SMCR_SMS_SHIFT (0) /* Bits 2:0: Slave mode selection */
-#define ATIM_SMCR_SMS_MASK (7 << ATIM_SMCR_SMS_SHIFT)
-# define ATIM_SMCR_DISAB (0 << ATIM_SMCR_SMS_SHIFT) /* 000: Slave mode disabled */
-# define ATIM_SMCR_ENCMD1 (1 << ATIM_SMCR_SMS_SHIFT) /* 001: Encoder mode 1 */
-# define ATIM_SMCR_ENCMD2 (2 << ATIM_SMCR_SMS_SHIFT) /* 010: Encoder mode 2 */
-# define ATIM_SMCR_ENCMD3 (3 << ATIM_SMCR_SMS_SHIFT) /* 011: Encoder mode 3 */
-# define ATIM_SMCR_RESET (4 << ATIM_SMCR_SMS_SHIFT) /* 100: Reset Mode */
-# define ATIM_SMCR_GATED (5 << ATIM_SMCR_SMS_SHIFT) /* 101: Gated Mode */
-# define ATIM_SMCR_TRIGGER (6 << ATIM_SMCR_SMS_SHIFT) /* 110: Trigger Mode */
-# define ATIM_SMCR_EXTCLK1 (7 << ATIM_SMCR_SMS_SHIFT) /* 111: External Clock Mode 1 */
+#define ATIM_SMCR_ETPS_SHIFT (12) /* Bits 12-13: External trigger prescaler */
+#define ATIM_SMCR_ETPS_MASK (3 << ATIM_SMCR_ETPS_SHIFT)
+# define ATIM_SMCR_PSCOFF (0 << ATIM_SMCR_ETPS_SHIFT) /* 00: Prescaler OFF */
+# define ATIM_SMCR_ETRPd2 (1 << ATIM_SMCR_ETPS_SHIFT) /* 01: ETRP frequency divided by 2 */
+# define ATIM_SMCR_ETRPd4 (2 << ATIM_SMCR_ETPS_SHIFT) /* 10: ETRP frequency divided by 4 */
+# define ATIM_SMCR_ETRPd8 (3 << ATIM_SMCR_ETPS_SHIFT) /* 11: ETRP frequency divided by 8 */
+#define ATIM_SMCR_ECE (1 << 14) /* Bit 14: External clock enable */
+#define ATIM_SMCR_ETP (1 << 15) /* Bit 15: External trigger polarity */
/* DMA/Interrupt enable register */
diff --git a/nuttx/arch/arm/src/stm32/stm32_dumpgpio.c b/nuttx/arch/arm/src/stm32/stm32_dumpgpio.c
index 71d3a3d74..b0ebc84d9 100644
--- a/nuttx/arch/arm/src/stm32/stm32_dumpgpio.c
+++ b/nuttx/arch/arm/src/stm32/stm32_dumpgpio.c
@@ -126,13 +126,17 @@ int stm32_dumpgpio(uint32_t pinset, const char *msg)
if ((getreg32(STM32_RCC_APB2ENR) & RCC_APB2ENR_IOPEN(port)) != 0)
{
lldbg(" CR: %08x %08x IDR: %04x ODR: %04x LCKR: %04x\n",
- getreg32(base + STM32_GPIO_CRH_OFFSET), getreg32(base + STM32_GPIO_CRL_OFFSET),
- getreg32(base + STM32_GPIO_IDR_OFFSET), getreg32(base + STM32_GPIO_ODR_OFFSET),
+ getreg32(base + STM32_GPIO_CRH_OFFSET),
+ getreg32(base + STM32_GPIO_CRL_OFFSET),
+ getreg32(base + STM32_GPIO_IDR_OFFSET),
+ getreg32(base + STM32_GPIO_ODR_OFFSET),
getreg32(base + STM32_GPIO_LCKR_OFFSET));
lldbg(" EVCR: %02x MAPR: %08x CR: %04x %04x %04x %04x\n",
getreg32(STM32_AFIO_EVCR), getreg32(STM32_AFIO_MAPR),
- getreg32(STM32_AFIO_EXTICR1), getreg32(STM32_AFIO_EXTICR2),
- getreg32(STM32_AFIO_EXTICR3), getreg32(STM32_AFIO_EXTICR4));
+ getreg32(STM32_AFIO_EXTICR1),
+ getreg32(STM32_AFIO_EXTICR2),
+ getreg32(STM32_AFIO_EXTICR3),
+ getreg32(STM32_AFIO_EXTICR4));
}
else
{
@@ -144,21 +148,26 @@ int stm32_dumpgpio(uint32_t pinset, const char *msg)
lldbg("GPIO%c pinset: %08x base: %08x -- %s\n",
g_portchar[port], pinset, base, msg);
- if ((getreg32(STM32_RCC_APB1ENR) & RCC_AHB1ENR_GPIOEN(port)) != 0)
+ if ((getreg32(STM32_RCC_AHB1ENR) & RCC_AHB1ENR_GPIOEN(port)) != 0)
{
- lldbg(" MODE: %08x OTYPE: %04x OSPEED: %08x PUPDR: %08x\n",
- getreg32(base + STM32_GPIO_MODER_OFFSET), getreg32(base + STM32_GPIO_OTYPER_OFFSET),
- getreg32(base + STM32_GPIO_OSPEED_OFFSET), getreg32(base + STM32_GPIO_PUPDR_OFFSET));
- lldbg(" IDR: %04x ODR: %04x BSRR: %08x LCKR: %04x\n",
- getreg32(STM32_GPIO_IDR_OFFSET), getreg32(STM32_GPIO_ODR_OFFSET),
- getreg32(STM32_GPIO_BSRR_OFFSET), getreg32(STM32_GPIO_LCKR_OFFSET));
+ lldbg(" MODE: %08x OTYPE: %04x OSPEED: %08x PUPDR: %08x\n",
+ getreg32(base + STM32_GPIO_MODER_OFFSET),
+ getreg32(base + STM32_GPIO_OTYPER_OFFSET),
+ getreg32(base + STM32_GPIO_OSPEED_OFFSET),
+ getreg32(base + STM32_GPIO_PUPDR_OFFSET));
+ lldbg(" IDR: %04x ODR: %04x BSRR: %08x LCKR: %04x\n",
+ getreg32(base + STM32_GPIO_IDR_OFFSET),
+ getreg32(base + STM32_GPIO_ODR_OFFSET),
+ getreg32(base + STM32_GPIO_BSRR_OFFSET),
+ getreg32(base + STM32_GPIO_LCKR_OFFSET));
lldbg(" AFRH: %08x AFRL: %08x\n",
- getreg32(STM32_GPIO_ARFH_OFFSET), getreg32(STM32_GPIO_AFRL_OFFSET));
+ getreg32(base + STM32_GPIO_ARFH_OFFSET),
+ getreg32(base + STM32_GPIO_AFRL_OFFSET));
}
else
{
- lldbg(" GPIO%c not enabled: APB1ENR: %08x\n",
- g_portchar[port], getreg32(STM32_RCC_APB1ENR));
+ lldbg(" GPIO%c not enabled: AHB1ENR: %08x\n",
+ g_portchar[port], getreg32(STM32_RCC_AHB1ENR));
}
#else
# error "Unsupported STM32 chip"
diff --git a/nuttx/configs/stm3240g-eval/README.txt b/nuttx/configs/stm3240g-eval/README.txt
index 9702bf03e..93c1d0efe 100755
--- a/nuttx/configs/stm3240g-eval/README.txt
+++ b/nuttx/configs/stm3240g-eval/README.txt
@@ -595,19 +595,25 @@ Where <subdir> is one of the following:
be manually enabled by selecting:
CONFIG_PWM=y : Enable the generic PWM infrastructure
- CONFIG_PWM_PULSECOUNT=n : Disable to support TIM1/8 pulse counts
+ CONFIG_PWM_PULSECOUNT=n : Disable to support for TIM1/8 pulse counts
CONFIG_STM32_TIM4=y : Enable TIM4
CONFIG_STM32_TIM4_PWM=y : Use TIM4 to generate PWM output
CONFIG_STM32_TIM4_CHANNEL=2
+
+ If CONFIG_STM32_FSMC is disabled, output will appear on CN3, pin 32.
+ Ground is available on CN3, pin1.
Or..
CONFIG_PWM=y : Enable the generic PWM infrastructure
- CONFIG_PWM_PULSECOUNT=y : Enable to support TIM1/8 pulse counts
+ CONFIG_PWM_PULSECOUNT=y : Enable to support for TIM1/8 pulse counts
CONFIG_STM32_TIM1=y : Enable TIM1
CONFIG_STM32_TIM1_PWM=y : Use TIM1 to generate PWM output
CONFIG_STM32_TIM1_CHANNEL=1
+ If CONFIG_STM32_FSMC is disabled, output will appear on CN2, pin 24
+ Ground is available on CN2, pin1.
+
See also include/board.h and apps/examples/README.txt
Special PWM-only debug options:
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-26 05:59:58 +0000