diff options
-rw-r--r-- | nuttx/arch/arm/src/kinetis/kinetis_irq.c | 39 | ||||
-rw-r--r-- | nuttx/arch/arm/src/lm/lm_irq.c | 39 | ||||
-rw-r--r-- | nuttx/arch/arm/src/lpc17xx/lpc17_irq.c | 41 | ||||
-rw-r--r-- | nuttx/arch/arm/src/lpc43xx/lpc43_irq.c | 39 | ||||
-rw-r--r-- | nuttx/arch/arm/src/sam34/sam_irq.c | 39 | ||||
-rw-r--r-- | nuttx/arch/arm/src/stm32/stm32_irq.c | 39 |
6 files changed, 133 insertions, 103 deletions
diff --git a/nuttx/arch/arm/src/kinetis/kinetis_irq.c b/nuttx/arch/arm/src/kinetis/kinetis_irq.c index 9e6ab4e04..3ab9d3cba 100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_irq.c +++ b/nuttx/arch/arm/src/kinetis/kinetis_irq.c @@ -450,28 +450,22 @@ void up_disable_irq(int irq) if (kinetis_irqinfo(irq, ®addr, &bit, NVIC_CLRENA_OFFSET) == 0) { - /* Modify the appropriate bit in the register to disable the interrupt */ - - regval = getreg32(regaddr); - - /* This is awkward... For normal interrupts, we need to set the bit - * in the associated Interrupt Clear Enable register. For other - * exceptions, we need to clear the bit in the System Handler Control - * and State Register. + /* Modify the appropriate bit in the register to disable the interrupt. + * For normal interrupts, we need to set the bit in the associated + * Interrupt Clear Enable register. For other exceptions, we need to + * clear the bit in the System Handler Control and State Register. */ if (irq >= KINETIS_IRQ_EXTINT) { - regval |= bit; + putreg32(bit, regaddr); } else { + regval = getreg32(regaddr); regval &= ~bit; + putreg32(regval, regaddr); } - - /* Save the appropriately modified register */ - - putreg32(regval, regaddr); } kinetis_dumpnvic("disable", irq); @@ -493,11 +487,22 @@ void up_enable_irq(int irq) if (kinetis_irqinfo(irq, ®addr, &bit, NVIC_ENA_OFFSET) == 0) { - /* Set the appropriate bit in the register to enable the interrupt */ + /* Modify the appropriate bit in the register to enable the interrupt. + * For normal interrupts, we need to set the bit in the associated + * Interrupt Set Enable register. For other exceptions, we need to + * set the bit in the System Handler Control and State Register. + */ - regval = getreg32(regaddr); - regval |= bit; - putreg32(regval, regaddr); + if (irq >= KINETIS_IRQ_EXTINT) + { + putreg32(bit, regaddr); + } + else + { + regval = getreg32(regaddr); + regval |= bit; + putreg32(regval, regaddr); + } } kinetis_dumpnvic("enable", irq); diff --git a/nuttx/arch/arm/src/lm/lm_irq.c b/nuttx/arch/arm/src/lm/lm_irq.c index b46e99684..6ada4d3e9 100644 --- a/nuttx/arch/arm/src/lm/lm_irq.c +++ b/nuttx/arch/arm/src/lm/lm_irq.c @@ -404,28 +404,22 @@ void up_disable_irq(int irq) if (lm_irqinfo(irq, ®addr, &bit, NVIC_CLRENA_OFFSET) == 0) { - /* Modify the appropriate bit in the register to disable the interrupt */ - - regval = getreg32(regaddr); - - /* This is awkward... For normal interrupts, we need to set the bit - * in the associated Interrupt Clear Enable register. For other - * exceptions, we need to clear the bit in the System Handler Control - * and State Register. + /* Modify the appropriate bit in the register to disable the interrupt. + * For normal interrupts, we need to set the bit in the associated + * Interrupt Clear Enable register. For other exceptions, we need to + * clear the bit in the System Handler Control and State Register. */ if (irq >= LM_IRQ_INTERRUPTS) { - regval |= bit; + putreg32(bit, regaddr); } else { + regval = getreg32(regaddr); regval &= ~bit; + putreg32(regval, regaddr); } - - /* Save the appropriately modified register */ - - putreg32(regval, regaddr); } lm_dumpnvic("disable", irq); @@ -447,11 +441,22 @@ void up_enable_irq(int irq) if (lm_irqinfo(irq, ®addr, &bit, NVIC_ENA_OFFSET) == 0) { - /* Set the appropriate bit in the register to enable the interrupt */ + /* Modify the appropriate bit in the register to enable the interrupt. + * For normal interrupts, we need to set the bit in the associated + * Interrupt Set Enable register. For other exceptions, we need to + * set the bit in the System Handler Control and State Register. + */ - regval = getreg32(regaddr); - regval |= bit; - putreg32(regval, regaddr); + if (irq >= LM_IRQ_INTERRUPTS) + { + putreg32(bit, regaddr); + } + else + { + regval = getreg32(regaddr); + regval |= bit; + putreg32(regval, regaddr); + } } lm_dumpnvic("enable", irq); diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_irq.c b/nuttx/arch/arm/src/lpc17xx/lpc17_irq.c index a9c7bcee9..6b163d257 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_irq.c +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_irq.c @@ -395,30 +395,24 @@ void up_disable_irq(int irq) uint32_t regval; uint32_t bit; - if (lpc17_irqinfo(irq, ®addr, &bit) == 0) + if (lpc17_irqinfo(irq, ®addr, &bit, NVIC_CLRENA_OFFSET) == 0) { - /* Modify the appropriate bit in the register to disable the interrupt */ - - regval = getreg32(regaddr); - - /* This is awkward... For normal interrupts, we need to set the bit - * in the associated Interrupt Clear Enable register. For other - * exceptions, we need to clear the bit in the System Handler Control - * and State Register. + /* Modify the appropriate bit in the register to disable the interrupt. + * For normal interrupts, we need to set the bit in the associated + * Interrupt Clear Enable register. For other exceptions, we need to + * clear the bit in the System Handler Control and State Register. */ if (irq >= LPC17_IRQ_EXTINT) { - regval |= bit; + putreg32(bit, regaddr); } else { + regval = getreg32(regaddr); regval &= ~bit; + putreg32(regval, regaddr); } - - /* Save the appropriately modified register */ - - putreg32(regval, regaddr); } #ifdef CONFIG_GPIO_IRQ else if (irq >= LPC17_VALID_FIRST0L) @@ -448,11 +442,22 @@ void up_enable_irq(int irq) if (lpc17_irqinfo(irq, ®addr, &bit, NVIC_ENA_OFFSET) == 0) { - /* Set the appropriate bit in the register to enable the interrupt */ + /* Modify the appropriate bit in the register to enable the interrupt. + * For normal interrupts, we need to set the bit in the associated + * Interrupt Set Enable register. For other exceptions, we need to + * set the bit in the System Handler Control and State Register. + */ - regval = getreg32(regaddr); - regval |= bit; - putreg32(regval, regaddr); + if (irq >= LPC17_IRQ_EXTINT) + { + putreg32(bit, regaddr); + } + else + { + regval = getreg32(regaddr); + regval |= bit; + putreg32(regval, regaddr); + } } #ifdef CONFIG_GPIO_IRQ else if (irq >= LPC17_VALID_FIRST0L) diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_irq.c b/nuttx/arch/arm/src/lpc43xx/lpc43_irq.c index 06221ec49..0827b22cc 100644 --- a/nuttx/arch/arm/src/lpc43xx/lpc43_irq.c +++ b/nuttx/arch/arm/src/lpc43xx/lpc43_irq.c @@ -435,28 +435,22 @@ void up_disable_irq(int irq) if (lpc43_irqinfo(irq, ®addr, &bit, NVIC_CLRENA_OFFSET) == 0) { - /* Modify the appropriate bit in the register to disable the interrupt */ - - regval = getreg32(regaddr); - - /* This is awkward... For normal interrupts, we need to set the bit - * in the associated Interrupt Clear Enable register. For other - * exceptions, we need to clear the bit in the System Handler Control - * and State Register. + /* Modify the appropriate bit in the register to disable the interrupt. + * For normal interrupts, we need to set the bit in the associated + * Interrupt Clear Enable register. For other exceptions, we need to + * clear the bit in the System Handler Control and State Register. */ if (irq >= LPC43_IRQ_EXTINT) { - regval |= bit; + putreg32(bit, regaddr); } else { + regval = getreg32(regaddr); regval &= ~bit; + putreg32(regval, regaddr); } - - /* Save the appropriately modified register */ - - putreg32(regval, regaddr); } #ifdef CONFIG_GPIO_IRQ else if (irq >= LPC43_VALID_FIRST0L) @@ -486,11 +480,22 @@ void up_enable_irq(int irq) if (lpc43_irqinfo(irq, ®addr, &bit, NVIC_ENA_OFFSET) == 0) { - /* Set the appropriate bit in the register to enable the interrupt */ + /* Modify the appropriate bit in the register to enable the interrupt. + * For normal interrupts, we need to set the bit in the associated + * Interrupt Set Enable register. For other exceptions, we need to + * set the bit in the System Handler Control and State Register. + */ - regval = getreg32(regaddr); - regval |= bit; - putreg32(regval, regaddr); + if (irq >= LPC43_IRQ_EXTINT) + { + putreg32(bit, regaddr); + } + else + { + regval = getreg32(regaddr); + regval |= bit; + putreg32(regval, regaddr); + } } #ifdef CONFIG_GPIO_IRQ else if (irq >= LPC43_VALID_FIRST0L) diff --git a/nuttx/arch/arm/src/sam34/sam_irq.c b/nuttx/arch/arm/src/sam34/sam_irq.c index c633e5d65..2189c5783 100644 --- a/nuttx/arch/arm/src/sam34/sam_irq.c +++ b/nuttx/arch/arm/src/sam34/sam_irq.c @@ -464,28 +464,22 @@ void up_disable_irq(int irq) if (sam_irqinfo(irq, ®addr, &bit, NVIC_CLRENA_OFFSET) == 0) { - /* Modify the appropriate bit in the register to disable the interrupt */ - - regval = getreg32(regaddr); - - /* This is awkward... For normal interrupts, we need to set the bit - * in the associated Interrupt Clear Enable register. For other - * exceptions, we need to clear the bit in the System Handler Control - * and State Register. + /* Modify the appropriate bit in the register to disable the interrupt. + * For normal interrupts, we need to set the bit in the associated + * Interrupt Clear Enable register. For other exceptions, we need to + * clear the bit in the System Handler Control and State Register. */ if (irq >= SAM_IRQ_EXTINT) { - regval |= bit; + putreg32(bit, regaddr); } else { + regval = getreg32(regaddr); regval &= ~bit; + putreg32(regval, regaddr); } - - /* Save the appropriately modified register */ - - putreg32(regval, regaddr); } #ifdef CONFIG_GPIO_IRQ else @@ -514,11 +508,22 @@ void up_enable_irq(int irq) if (sam_irqinfo(irq, ®addr, &bit, NVIC_ENA_OFFSET) == 0) { - /* Set the appropriate bit in the register to enable the interrupt */ + /* Modify the appropriate bit in the register to enable the interrupt. + * For normal interrupts, we need to set the bit in the associated + * Interrupt Set Enable register. For other exceptions, we need to + * set the bit in the System Handler Control and State Register. + */ - regval = getreg32(regaddr); - regval |= bit; - putreg32(regval, regaddr); + if (irq >= SAM_IRQ_EXTINT) + { + putreg32(bit, regaddr); + } + else + { + regval = getreg32(regaddr); + regval |= bit; + putreg32(regval, regaddr); + } } #ifdef CONFIG_GPIO_IRQ else diff --git a/nuttx/arch/arm/src/stm32/stm32_irq.c b/nuttx/arch/arm/src/stm32/stm32_irq.c index 76b5d9e64..f815fe5be 100644 --- a/nuttx/arch/arm/src/stm32/stm32_irq.c +++ b/nuttx/arch/arm/src/stm32/stm32_irq.c @@ -429,28 +429,22 @@ void up_disable_irq(int irq) if (stm32_irqinfo(irq, ®addr, &bit, NVIC_CLRENA_OFFSET) == 0) { - /* Modify the appropriate bit in the register to disable the interrupt */ - - regval = getreg32(regaddr); - - /* This is awkward... For normal interrupts, we need to set the bit - * in the associated Interrupt Clear Enable register. For other - * exceptions, we need to clear the bit in the System Handler Control - * and State Register. + /* Modify the appropriate bit in the register to disable the interrupt. + * For normal interrupts, we need to set the bit in the associated + * Interrupt Clear Enable register. For other exceptions, we need to + * clear the bit in the System Handler Control and State Register. */ if (irq >= STM32_IRQ_INTERRUPTS) { - regval |= bit; + putreg32(bit, regaddr); } else { + regval = getreg32(regaddr); regval &= ~bit; + putreg32(regval, regaddr); } - - /* Save the appropriately modified register */ - - putreg32(regval, regaddr); } // stm32_dumpnvic("disable", irq); @@ -472,11 +466,22 @@ void up_enable_irq(int irq) if (stm32_irqinfo(irq, ®addr, &bit, NVIC_ENA_OFFSET) == 0) { - /* Set the appropriate bit in the register to enable the interrupt */ + /* Modify the appropriate bit in the register to enable the interrupt. + * For normal interrupts, we need to set the bit in the associated + * Interrupt Set Enable register. For other exceptions, we need to + * set the bit in the System Handler Control and State Register. + */ - regval = getreg32(regaddr); - regval |= bit; - putreg32(regval, regaddr); + if (irq >= STM32_IRQ_INTERRUPTS) + { + putreg32(bit, regaddr); + } + else + { + regval = getreg32(regaddr); + regval |= bit; + putreg32(regval, regaddr); + } } // stm32_dumpnvic("enable", irq); |