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-rw-r--r--nuttx/arch/arm/include/tiva/chip.h28
-rw-r--r--nuttx/arch/arm/include/tiva/lm3s_irq.h2
-rw-r--r--nuttx/arch/arm/include/tiva/tm4c_irq.h158
-rw-r--r--nuttx/arch/arm/src/tiva/Kconfig7
-rw-r--r--nuttx/arch/arm/src/tiva/chip/tiva_flash.h2
-rw-r--r--nuttx/arch/arm/src/tiva/chip/tm4c_memorymap.h179
-rw-r--r--nuttx/arch/arm/src/tiva/chip/tm4c_pinmap.h170
-rw-r--r--nuttx/arch/arm/src/tiva/chip/tm4c_vectors.h173
-rw-r--r--nuttx/configs/Kconfig4
-rw-r--r--nuttx/configs/tm4c123g-launchpad/README.txt26
-rw-r--r--nuttx/configs/tm4c123g-launchpad/nsh/defconfig2
-rw-r--r--nuttx/configs/tm4c123g-launchpad/tools/lm4f120-launchpad.cfg71
-rw-r--r--nuttx/configs/tm4c123g-launchpad/tools/oocd.sh8
-rw-r--r--nuttx/configs/tm4c123g-launchpad/tools/tm4c123g-launchpad.cfg12
14 files changed, 741 insertions, 101 deletions
diff --git a/nuttx/arch/arm/include/tiva/chip.h b/nuttx/arch/arm/include/tiva/chip.h
index 04f4ae108..5d5de8373 100644
--- a/nuttx/arch/arm/include/tiva/chip.h
+++ b/nuttx/arch/arm/include/tiva/chip.h
@@ -174,14 +174,32 @@
# define TIVA_NPORTS 15 /* Fifteen Ports (GPIOA-H, J-N, P-Q) */
# define TIVA_NCANCONTROLLER 2 /* Two CAN controllers */
# define TIVA_NUSBOTGFS 1 /* One USB 2.0 OTG FS */
+#elif defined(CONFIG_ARCH_CHIP_TM4C123GH6PMI)
+# undef LM3S /* Not LM3S family */
+# undef LM4F /* Not LM4F family */
+# define TM4C 1 /* TM4C family */
+# define TIVA_NTIMERS 6 /* Six general purpose timers */
+# define TIVA_NWIDETIMERS 6 /* Six general purpose wide timers */
+# define TIVA_NWDT 2 /* Two watchdog timers */
+# define TIVA_NETHCONTROLLERS 0 /* No Ethernet controller */
+# define TIVA_NSSI 4 /* Four SSI module */
+# define TIVA_NUARTS 8 /* Eight UART modules */
+# define TIVA_NI2C 4 /* Four I2C modules */
+# define TIVA_NADC 2 /* Two ADC modules */
+# define TIVA_NPWM 2 /* Two PWM generator modules */
+# define TIVA_NQEI 2 /* Two quadrature encoders */
+# define TIVA_NPORTS 6 /* Six Ports (GPIOA-F) */
+# define TIVA_NCANCONTROLLER 2 /* Two CAN controllers */
+# define TIVA_NUSBOTGFS 1 /* One USB 2.0 OTG FS */
#else
-# error "Capabilities not specified for this Stellaris chip"
+# error "Capabilities not specified for this TIVA/Stellaris chip"
#endif
-/* The LM3S69xx only supports 8 priority levels. The hardware priority mechanism
- * will only look at the upper N bits of the 8-bit priority level (where N is 3 for
- * the Stellaris family), so any prioritization must be performed in those bits.
- * The default priority level is set to the middle value
+/* The TIVA/Stellaris only supports 8 priority levels. The hardware priority
+ * mechanism will only look at the upper N bits of the 8-bit priority level
+ * (where N is 3 for the Tiva/Stellaris family), so any prioritization must be
+ * performed in those bits. The default priority level is set to the middle
+ * value
*/
#define NVIC_SYSH_PRIORITY_MIN 0xe0 /* Bits [5:7] set in minimum priority */
diff --git a/nuttx/arch/arm/include/tiva/lm3s_irq.h b/nuttx/arch/arm/include/tiva/lm3s_irq.h
index fb9b66430..241ff20a6 100644
--- a/nuttx/arch/arm/include/tiva/lm3s_irq.h
+++ b/nuttx/arch/arm/include/tiva/lm3s_irq.h
@@ -53,7 +53,7 @@
/* External interrupts (vectors >= 16) */
-#define TIVA_IRQ_INTERRUPTS (16) /* Vector number of the first external interrupt */
+#define TIVA_IRQ_INTERRUPTS (16) /* Vector number of the first external interrupt */
#if defined(CONFIG_ARCH_CHIP_LM3S6918)
# define TIVA_IRQ_GPIOA (16) /* Vector 16: GPIO Port A */
diff --git a/nuttx/arch/arm/include/tiva/tm4c_irq.h b/nuttx/arch/arm/include/tiva/tm4c_irq.h
index d6486aad9..87f2b4052 100644
--- a/nuttx/arch/arm/include/tiva/tm4c_irq.h
+++ b/nuttx/arch/arm/include/tiva/tm4c_irq.h
@@ -213,6 +213,164 @@
# define NR_VECTORS (155)
# define NR_IRQS (123) /* (Really fewer because of reserved vectors) */
+#elif defined(CONFIG_ARCH_CHIP_TM4C123GH6PMI)
+# define TIVA_IRQ_GPIOA (16) /* Vector 16: GPIO Port A */
+# define TIVA_IRQ_GPIOB (17) /* Vector 17: GPIO Port B */
+# define TIVA_IRQ_GPIOC (18) /* Vector 18: GPIO Port C */
+# define TIVA_IRQ_GPIOD (19) /* Vector 19: GPIO Port D */
+
+# define TIVA_IRQ_GPIOE (20) /* Vector 20: GPIO Port E */
+# define TIVA_IRQ_UART0 (21) /* Vector 21: UART 0 */
+# define TIVA_IRQ_UART1 (22) /* Vector 22: UART 1 */
+# define TIVA_IRQ_SSI0 (23) /* Vector 23: SSI 0 */
+# define TIVA_IRQ_I2C0 (24) /* Vector 24: I2C 0 */
+# define TIVA_IRQ_PWM0_FAULT (25) /* Vector 25: PWM0 Fault */
+# define TIVA_IRQ_PWM0_GEN0 (26) /* Vector 26: PWM0 Generator 0 */
+# define TIVA_IRQ_PWM0_GEN1 (27) /* Vector 27: PWM0 Generator 1 */
+# define TIVA_IRQ_PWM0_GEN2 (28) /* Vector 28: PWM0 Generator 2 */
+# define TIVA_IRQ_QEI0 (29) /* Vector 29: QEI0 */
+
+# define TIVA_IRQ_ADC0 (30) /* Vector 30: ADC Sequence 0 */
+# define TIVA_IRQ_ADC1 (31) /* Vector 31: ADC Sequence 1 */
+# define TIVA_IRQ_ADC2 (32) /* Vector 32: ADC Sequence 2 */
+# define TIVA_IRQ_ADC3 (33) /* Vector 33: ADC Sequence 3 */
+# define TIVA_IRQ_WDOG (34) /* Vector 34: Watchdog Timers 0 and 1 */
+# define TIVA_IRQ_TIMER0A (35) /* Vector 35: 16/32-Bit Timer 0 A */
+# define TIVA_IRQ_TIMER0B (36) /* Vector 36: 16/32-Bit Timer 0 B */
+# define TIVA_IRQ_TIMER1A (37) /* Vector 37: 16/32-Bit Timer 1 A */
+# define TIVA_IRQ_TIMER1B (38) /* Vector 38: 16/32-Bit Timer 1 B */
+# define TIVA_IRQ_TIMER2A (39) /* Vector 39: 16/32-Bit Timer 2 A */
+
+# define TIVA_IRQ_TIMER2B (40) /* Vector 40: 16/32-Bit Timer 2 B */
+# define TIVA_IRQ_COMPARE0 (41) /* Vector 41: Analog Comparator 0 */
+# define TIVA_IRQ_COMPARE1 (42) /* Vector 42: Analog Comparator 1 */
+# define TIVA_IRQ_COMPARE2 (43) /* Vector 43: Analog Comparator 2 */
+# define TIVA_IRQ_SYSCON (44) /* Vector 44: System Control */
+# define TIVA_IRQ_FLASHCON (45) /* Vector 45: FLASH and EEPROM Control */
+# define TIVA_IRQ_GPIOF (46) /* Vector 46: GPIO Port F */
+# define TIVA_RESERVED_47 (47) /* Vector 47: Reserved */
+# define TIVA_RESERVED_48 (48) /* Vector 48: Reserved */
+# define TIVA_IRQ_UART2 (49) /* Vector 49: UART 2 */
+
+# define TIVA_IRQ_SSI1 (50) /* Vector 50: SSI 1 */
+# define TIVA_IRQ_TIMER3A (51) /* Vector 51: 16/32-Bit Timer 3 A */
+# define TIVA_IRQ_TIMER3B (52) /* Vector 52: 16/32-Bit Timer 3 B */
+# define TIVA_IRQ_I2C1 (53) /* Vector 53: I2C 1 */
+# define TIVA_IRQ_QEI1 (54) /* Vector 54: QEI1 */
+# define TIVA_IRQ_CAN0 (55) /* Vector 55: CAN 0 */
+# define TIVA_IRQ_CAN1 (56) /* Vector 56: CAN 1 */
+# define TIVA_RESERVED_57 (57) /* Vector 57: Reserved */
+# define TIVA_RESERVED_58 (58) /* Vector 58: Reserved */
+# define TIVA_IRQ_HIBERNATE (59) /* Vector 59: Hibernation Module */
+
+# define TIVA_IRQ_USB (60) /* Vector 60: USB */
+# define TIVA_IRQ_PWM0_GEN3 (61) /* Vector 61: PWM0 Generator 3 */
+# define TIVA_IRQ_UDMASOFT (62) /* Vector 62: uDMA Software */
+# define TIVA_IRQ_UDMAERROR (63) /* Vector 63: uDMA Error */
+# define TIVA_IRQ_ADC1_0 (64) /* Vector 64: ADC1 Sequence 0 */
+# define TIVA_IRQ_ADC1_1 (65) /* Vector 65: ADC1 Sequence 1 */
+# define TIVA_IRQ_ADC1_2 (66) /* Vector 66: ADC1 Sequence 2 */
+# define TIVA_IRQ_ADC1_3 (67) /* Vector 67: ADC1 Sequence 3 */
+# define TIVA_RESERVED_68 (68) /* Vector 68: Reserved */
+# define TIVA_RESERVED_69 (69) /* Vector 69: Reserved */
+
+# define TIVA_RESERVED_70 (70) /* Vector 70: Reserved */
+# define TIVA_RESERVED_71 (71) /* Vector 71: Reserved */
+# define TIVA_RESERVED_72 (72) /* Vector 72: Reserved */
+# define TIVA_IRQ_SSI2 (73) /* Vector 73: SSI 2 */
+# define TIVA_IRQ_SSI3 (74) /* Vector 74: SSI 3 */
+# define TIVA_IRQ_UART3 (75) /* Vector 75: UART 3 */
+# define TIVA_IRQ_UART4 (76) /* Vector 76: UART 4 */
+# define TIVA_IRQ_UART5 (77) /* Vector 77: UART 5 */
+# define TIVA_IRQ_UART6 (78) /* Vector 78: UART 6 */
+# define TIVA_IRQ_UART7 (79) /* Vector 79: UART 7 */
+
+# define TIVA_RESERVED_80 (80) /* Vector 80: Reserved */
+# define TIVA_RESERVED_81 (81) /* Vector 81: Reserved */
+# define TIVA_RESERVED_82 (82) /* Vector 82: Reserved */
+# define TIVA_RESERVED_83 (83) /* Vector 83: Reserved */
+# define TIVA_IRQ_I2C2 (84) /* Vector 84: I2C 2 */
+# define TIVA_IRQ_I2C3 (85) /* Vector 85: I2C 3 */
+# define TIVA_IRQ_TIMER4A (86) /* Vector 86: 16/32-Bit Timer 4 A */
+# define TIVA_IRQ_TIMER4B (87) /* Vector 87: 16/32-Bit Timer 4 B */
+# define TIVA_RESERVED_88 (88) /* Vector 88: Reserved */
+# define TIVA_RESERVED_89 (89) /* Vector 89: Reserved */
+
+# define TIVA_RESERVED_90 (90) /* Vector 90: Reserved */
+# define TIVA_RESERVED_91 (91) /* Vector 91: Reserved */
+# define TIVA_RESERVED_92 (92) /* Vector 92: Reserved */
+# define TIVA_RESERVED_93 (93) /* Vector 93: Reserved */
+# define TIVA_RESERVED_94 (94) /* Vector 94: Reserved */
+# define TIVA_RESERVED_95 (95) /* Vector 95: Reserved */
+# define TIVA_RESERVED_96 (96) /* Vector 96: Reserved */
+# define TIVA_RESERVED_97 (97) /* Vector 97: Reserved */
+# define TIVA_RESERVED_98 (98) /* Vector 98: Reserved */
+# define TIVA_RESERVED_99 (99) /* Vector 99: Reserved */
+
+# define TIVA_RESERVED_100 (100) /* Vector 100: Reserved */
+# define TIVA_RESERVED_101 (101) /* Vector 101: Reserved */
+# define TIVA_RESERVED_102 (102) /* Vector 102: Reserved */
+# define TIVA_RESERVED_103 (103) /* Vector 103: Reserved */
+# define TIVA_RESERVED_104 (104) /* Vector 104: Reserved */
+# define TIVA_RESERVED_105 (105) /* Vector 105: Reserved */
+# define TIVA_RESERVED_106 (106) /* Vector 106: Reserved */
+# define TIVA_RESERVED_107 (107) /* Vector 107: Reserved */
+# define TIVA_IRQ_TIMER5A (108) /* Vector 108: 16/32-Bit Timer 5 A */
+# define TIVA_IRQ_TIMER5B (109) /* Vector 109: 16/32-Bit Timer 5 B */
+
+# define TIVA_IRQ_WTIMER0A (110) /* Vector 110: 32/64-Bit Timer 0 A */
+# define TIVA_IRQ_WTIMER0B (111) /* Vector 111: 32/64-Bit Timer 0 B */
+# define TIVA_IRQ_WTIMER1A (112) /* Vector 112: 32/64-Bit Timer 1 A */
+# define TIVA_IRQ_WTIMER1B (113) /* Vector 113: 32/64-Bit Timer 1 B */
+# define TIVA_IRQ_WTIMER2A (114) /* Vector 114: 32/64-Bit Timer 2 A */
+# define TIVA_IRQ_WTIMER2B (115) /* Vector 115: 32/64-Bit Timer 2 B */
+# define TIVA_IRQ_WTIMER3A (116) /* Vector 116: 32/64-Bit Timer 3 A */
+# define TIVA_IRQ_WTIMER3B (117) /* Vector 117: 32/64-Bit Timer 3 B */
+# define TIVA_IRQ_WTIMER4A (118) /* Vector 118: 32/64-Bit Timer 4 A */
+# define TIVA_IRQ_WTIMER4B (119) /* Vector 119: 32/64-Bit Timer 4 B */
+
+# define TIVA_IRQ_WTIMER5A (120) /* Vector 120: 32/64-Bit Timer 5 A */
+# define TIVA_IRQ_WTIMER5B (121) /* Vector 121: 32/64-Bit Timer 5 B */
+# define TIVA_IRQ_SYSTEM (122) /* Vector 122: System Exception (imprecise) */
+# define TIVA_RESERVED_123 (123) /* Vector 123: Reserved */
+# define TIVA_RESERVED_124 (124) /* Vector 124: Reserved */
+# define TIVA_RESERVED_125 (125) /* Vector 125: Reserved */
+# define TIVA_RESERVED_126 (126) /* Vector 126: Reserved */
+# define TIVA_RESERVED_127 (127) /* Vector 127: Reserved */
+# define TIVA_RESERVED_128 (128) /* Vector 128: Reserved */
+# define TIVA_RESERVED_129 (129) /* Vector 129: Reserved */
+
+# define TIVA_RESERVED_130 (130) /* Vector 130: Reserved */
+# define TIVA_RESERVED_131 (131) /* Vector 131: Reserved */
+# define TIVA_RESERVED_132 (132) /* Vector 132: Reserved */
+# define TIVA_RESERVED_133 (133) /* Vector 133: Reserved */
+# define TIVA_RESERVED_134 (134) /* Vector 134: Reserved */
+# define TIVA_RESERVED_135 (135) /* Vector 135: Reserved */
+# define TIVA_RESERVED_136 (136) /* Vector 136: Reserved */
+# define TIVA_RESERVED_137 (137) /* Vector 137: Reserved */
+# define TIVA_RESERVED_138 (138) /* Vector 138: Reserved */
+# define TIVA_RESERVED_139 (139) /* Vector 139: Reserved */
+
+# define TIVA_RESERVED_140 (140) /* Vector 140: Reserved */
+# define TIVA_RESERVED_141 (141) /* Vector 141: Reserved */
+# define TIVA_RESERVED_142 (142) /* Vector 142: Reserved */
+# define TIVA_RESERVED_143 (143) /* Vector 143: Reserved */
+# define TIVA_RESERVED_144 (144) /* Vector 144: Reserved */
+# define TIVA_RESERVED_145 (145) /* Vector 145: Reserved */
+# define TIVA_RESERVED_146 (146) /* Vector 146: Reserved */
+# define TIVA_RESERVED_147 (147) /* Vector 147: Reserved */
+# define TIVA_RESERVED_148 (148) /* Vector 148: Reserved */
+# define TIVA_RESERVED_149 (149) /* Vector 149: Reserved */
+
+# define TIVA_IRQ_PWM1_GEN0 (150) /* Vector 150: PWM1 Generator 0 */
+# define TIVA_IRQ_PWM1_GEN1 (151) /* Vector 151: PWM1 Generator 1 */
+# define TIVA_IRQ_PWM1_GEN2 (152) /* Vector 152: PWM1 Generator 2 */
+# define TIVA_IRQ_PWM1_GEN3 (153) /* Vector 153: PWM1 Generator 3 */
+# define TIVA_IRQ_PWM1_FAULT (154) /* Vector 154: PWM1 Fault */
+
+# define NR_VECTORS (155)
+# define NR_IRQS (123) /* (Really fewer because of reserved vectors) */
+
#else
# error "IRQ Numbers not known for this Tiva chip"
#endif
diff --git a/nuttx/arch/arm/src/tiva/Kconfig b/nuttx/arch/arm/src/tiva/Kconfig
index 55231b97c..b9c8ffa38 100644
--- a/nuttx/arch/arm/src/tiva/Kconfig
+++ b/nuttx/arch/arm/src/tiva/Kconfig
@@ -55,6 +55,13 @@ config ARCH_CHIP_TM4C123GH6ZRB
select ARCH_CHIP_TM4C
select ARCH_HAVE_FPU
+config ARCH_CHIP_TM4C123GH6PMI
+ bool "TM4C123GH6PMI"
+ depends on ARCH_CHIP_TIVA
+ select ARCH_CORTEXM4
+ select ARCH_CHIP_TM4C
+ select ARCH_HAVE_FPU
+
endchoice
# Chip families
diff --git a/nuttx/arch/arm/src/tiva/chip/tiva_flash.h b/nuttx/arch/arm/src/tiva/chip/tiva_flash.h
index f80a3f9d4..a4d1b63b5 100644
--- a/nuttx/arch/arm/src/tiva/chip/tiva_flash.h
+++ b/nuttx/arch/arm/src/tiva/chip/tiva_flash.h
@@ -50,7 +50,7 @@
#if defined(CONFIG_ARCH_CHIP_LM3S6965) || defined(CONFIG_ARCH_CHIP_LM4F120) || \
defined(CONFIG_ARCH_CHIP_LM3S8962) || defined(CONFIG_ARCH_CHIP_LM3S9B96) || \
- defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB)
+ defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || defined(CONFIG_ARCH_CHIP_TM4C123GH6PMI)
# define TIVA_FLASH_NPAGES 256
# define TIVA_FLASH_PAGESIZE 1024
#else
diff --git a/nuttx/arch/arm/src/tiva/chip/tm4c_memorymap.h b/nuttx/arch/arm/src/tiva/chip/tm4c_memorymap.h
index bbd528772..cba7e5f3b 100644
--- a/nuttx/arch/arm/src/tiva/chip/tm4c_memorymap.h
+++ b/nuttx/arch/arm/src/tiva/chip/tm4c_memorymap.h
@@ -69,6 +69,28 @@
# define TIVA_TPIU_BASE 0xe0040000 /* -0xe0040fff: Trace Port Interface Unit */
# define TIVA_ETM_BASE 0xe0041000 /* -0xe0041fff: Embedded Trace Macrocell */
/* -0xffffffff: Reserved */
+
+#elif defined(CONFIG_ARCH_CHIP_TM4C123GH6PMI)
+# define TIVA_FLASH_BASE 0x00000000 /* -0x0003ffff: On-chip FLASH */
+ /* -0x00ffffff: Reserved */
+# define TIVA_ROM_BASE 0x01000000 /* -0x1fffffff: Reserved for ROM */
+# define TIVA_SRAM_BASE 0x20000000 /* -0x20007fff: Bit-banded on-chip SRAM */
+ /* -0x21ffffff: Reserved */
+# define TIVA_ASRAM_BASE 0x22000000 /* -0x220fffff: Bit-band alias of 20000000- */
+ /* -0x3fffffff: Reserved */
+# define TIVA_PERIPH_BASE 0x40000000 /* -0x4001ffff: FiRM Peripherals */
+ /* -0x41ffffff: Peripherals */
+# define TIVA_APERIPH_BASE 0x42000000 /* -0x43ffffff: Bit-band alias of 40000000- */
+ /* -0xdfffffff: Reserved */
+# define TIVA_ITM_BASE 0xe0000000 /* -0xe0000fff: Instrumentation Trace Macrocell */
+# define TIVA_DWT_BASE 0xe0001000 /* -0xe0001fff: Data Watchpoint and Trace */
+# define TIVA_FPB_BASE 0xe0002000 /* -0xe0002fff: Flash Patch and Breakpoint */
+ /* -0xe000dfff: Reserved */
+# define TIVA_NVIC_BASE 0xe000e000 /* -0xe000efff: Nested Vectored Interrupt Controller */
+ /* -0xe003ffff: Reserved */
+# define TIVA_TPIU_BASE 0xe0040000 /* -0xe0040fff: Trace Port Interface Unit */
+# define TIVA_ETM_BASE 0xe0041000 /* -0xe0041fff: Embedded Trace Macrocell */
+ /* -0xffffffff: Reserved */
#else
# error "Memory map not specified for this TM4C chip"
#endif
@@ -172,6 +194,163 @@
# define TIVA_FLASHCON_BASE (TIVA_PERIPH_BASE + 0xfd000) /* -0xfdfff: FLASH Control */
# define TIVA_SYSCON_BASE (TIVA_PERIPH_BASE + 0xfe000) /* -0xfefff: System Control */
# define TIVA_UDMA_BASE (TIVA_PERIPH_BASE + 0xff000) /* -0xfffff: Micro Direct Memory Access */
+
+#elif defined(CONFIG_ARCH_CHIP_TM4C123GH6PMI)
+
+# define TIVA_WDOG0_BASE (TIVA_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer 0 */
+# define TIVA_WDOG1_BASE (TIVA_PERIPH_BASE + 0x01000) /* -0x00fff: Watchdog Timer 1 */
+ /* -0x03fff: Reserved */
+# define TIVA_GPIOA_BASE (TIVA_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */
+# define TIVA_GPIOB_BASE (TIVA_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */
+# define TIVA_GPIOC_BASE (TIVA_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */
+# define TIVA_GPIOD_BASE (TIVA_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */
+# define TIVA_SSI0_BASE (TIVA_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */
+# define TIVA_SSI1_BASE (TIVA_PERIPH_BASE + 0x09000) /* -0x09fff: SSI1 */
+# define TIVA_SSI2_BASE (TIVA_PERIPH_BASE + 0x0a000) /* -0x0afff: SSI2 */
+# define TIVA_SSI3_BASE (TIVA_PERIPH_BASE + 0x0b000) /* -0x0bfff: SSI3 */
+# define TIVA_UART0_BASE (TIVA_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */
+# define TIVA_UART1_BASE (TIVA_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */
+# define TIVA_UART2_BASE (TIVA_PERIPH_BASE + 0x0e000) /* -0x0efff: UART2 */
+# define TIVA_UART3_BASE (TIVA_PERIPH_BASE + 0x0f000) /* -0x0ffff: UART3 */
+# define TIVA_UART4_BASE (TIVA_PERIPH_BASE + 0x10000) /* -0x10fff: UART4 */
+# define TIVA_UART5_BASE (TIVA_PERIPH_BASE + 0x11000) /* -0x11fff: UART5 */
+# define TIVA_UART6_BASE (TIVA_PERIPH_BASE + 0x12000) /* -0x12fff: UART6 */
+# define TIVA_UART7_BASE (TIVA_PERIPH_BASE + 0x13000) /* -0x13fff: UART7 */
+ /* -0x1ffff: Reserved */
+/* Peripheral Base Addresses */
+
+# define TIVA_I2CM0_BASE (TIVA_PERIPH_BASE + 0x20000) /* -0x207ff: I2C Master 0 */
+# define TIVA_I2CS0_BASE (TIVA_PERIPH_BASE + 0x20800) /* -0x20fbf: I2C Slave 0 */
+# define TIVA_I2CSC0_BASE (TIVA_PERIPH_BASE + 0x20fc0) /* -0x20fff: I2C Status and Control 0 */
+# define TIVA_I2CM1_BASE (TIVA_PERIPH_BASE + 0x21000) /* -0x217ff: I2C Master 1 */
+# define TIVA_I2CS1_BASE (TIVA_PERIPH_BASE + 0x21800) /* -0x21fbf: I2C Slave 1 */
+# define TIVA_I2CSC1_BASE (TIVA_PERIPH_BASE + 0x21fc0) /* -0x21fff: I2C Status and Control 1 */
+# define TIVA_I2CM2_BASE (TIVA_PERIPH_BASE + 0x22000) /* -0x227ff: I2C Master 2 */
+# define TIVA_I2CS2_BASE (TIVA_PERIPH_BASE + 0x22800) /* -0x22fbf: I2C Slave 2 */
+# define TIVA_I2CSC2_BASE (TIVA_PERIPH_BASE + 0x22fc0) /* -0x22fff: I2C Status and Control 2 */
+# define TIVA_I2CM3_BASE (TIVA_PERIPH_BASE + 0x23000) /* -0x237ff: I2C Master 3 */
+# define TIVA_I2CS3_BASE (TIVA_PERIPH_BASE + 0x23800) /* -0x23fbf: I2C Slave 3 */
+# define TIVA_I2CSC3_BASE (TIVA_PERIPH_BASE + 0x23fc0) /* -0x23fff: I2C Status and Control 3 */
+# define TIVA_GPIOE_BASE (TIVA_PERIPH_BASE + 0x24000) /* -0x24fff: GPIO Port E */
+# define TIVA_GPIOF_BASE (TIVA_PERIPH_BASE + 0x25000) /* -0x25fff: GPIO Port F */
+# define TIVA_PWM0_BASE (TIVA_PERIPH_BASE + 0x28000) /* -0x28fff: PWM 0 */
+# define TIVA_PWM1_BASE (TIVA_PERIPH_BASE + 0x29000) /* -0x29fff: PWM 1 */
+ /* -0x2ffff: Reserved */
+# define TIVA_TIMER0_BASE (TIVA_PERIPH_BASE + 0x30000) /* -0x30fff: 16/32 Timer 0 */
+# define TIVA_TIMER1_BASE (TIVA_PERIPH_BASE + 0x31000) /* -0x31fff: 16/32 Timer 1 */
+# define TIVA_TIMER2_BASE (TIVA_PERIPH_BASE + 0x32000) /* -0x32fff: 16/32 Timer 2 */
+# define TIVA_TIMER3_BASE (TIVA_PERIPH_BASE + 0x33000) /* -0x33fff: 16/32 Timer 3 */
+# define TIVA_TIMER4_BASE (TIVA_PERIPH_BASE + 0x34000) /* -0x34fff: 16/32 Timer 4 */
+# define TIVA_TIMER5_BASE (TIVA_PERIPH_BASE + 0x35000) /* -0x35fff: 16/32 Timer 5 */
+# define TIVA_WTIMER0_BASE (TIVA_PERIPH_BASE + 0x36000) /* -0x36fff: 32/64 Wide Timer 0 */
+# define TIVA_WTIMER1_BASE (TIVA_PERIPH_BASE + 0x37000) /* -0x37fff: 32/64 Wide Timer 1 */
+# define TIVA_ADC0_BASE (TIVA_PERIPH_BASE + 0x38000) /* -0x38fff: ADC 0 */
+# define TIVA_ADC1_BASE (TIVA_PERIPH_BASE + 0x39000) /* -0x39fff: ADC 1 */
+ /* -0x3bfff: Reserved */
+# define TIVA_CMP_BASE (TIVA_PERIPH_BASE + 0x3c000) /* -0x3cfff: Analog Comparators */
+ /* -0x3ffff: Reserved */
+# define TIVA_CAN0_BASE (TIVA_PERIPH_BASE + 0x40000) /* -0x40fff: CAN Controller 0 */
+# define TIVA_CAN1_BASE (TIVA_PERIPH_BASE + 0x41000) /* -0x41fff: CAN Controller 1 */
+ /* -0x4bfff: Reserved */
+# define TIVA_WTIMER2_BASE (TIVA_PERIPH_BASE + 0x4c000) /* -0x4cfff: 32/64 Wide Timer 2 */
+# define TIVA_WTIMER3_BASE (TIVA_PERIPH_BASE + 0x4d000) /* -0x4dfff: 32/64 Wide Timer 3 */
+# define TIVA_WTIMER4_BASE (TIVA_PERIPH_BASE + 0x4e000) /* -0x4efff: 32/64 Wide Timer 4 */
+# define TIVA_WTIMER5_BASE (TIVA_PERIPH_BASE + 0x4f000) /* -0x4ffff: 32/64 Wide Timer 5 */
+# define TIVA_USB_BASE (TIVA_PERIPH_BASE + 0x50000) /* -0x50fff: USB */
+ /* -0x57fff: Reserved */
+# define TIVA_GPIOAAHB_BASE (TIVA_PERIPH_BASE + 0x58000) /* -0x58fff: GPIO Port A (AHB aperture) */
+# define TIVA_GPIOBAHB_BASE (TIVA_PERIPH_BASE + 0x59000) /* -0x59fff: GPIO Port B (AHB aperture) */
+# define TIVA_GPIOCAHB_BASE (TIVA_PERIPH_BASE + 0x5a000) /* -0x5afff: GPIO Port C (AHB aperture) */
+# define TIVA_GPIODAHB_BASE (TIVA_PERIPH_BASE + 0x5b000) /* -0x5bfff: GPIO Port D (AHB aperture) */
+# define TIVA_GPIOEAHB_BASE (TIVA_PERIPH_BASE + 0x5c000) /* -0x5cfff: GPIO Port E (AHB aperture) */
+# define TIVA_GPIOFAHB_BASE (TIVA_PERIPH_BASE + 0x5d000) /* -0x5dfff: GPIO Port F (AHB aperture) */
+ /* -0xaefff: Reserved */
+# define TIVA_EEPROM_BASE (TIVA_PERIPH_BASE + 0xaf000) /* -0xaffff: EEPROM and Key Locker */
+ /* -0xf8fff: Reserved */
+# define TIVA_SYSEXC_BASE (TIVA_PERIPH_BASE + 0xf9000) /* -0xf9fff: System Exception Control */
+ /* -0xfbfff: Reserved */
+# define TIVA_HIBERNATE_BASE (TIVA_PERIPH_BASE + 0xfc000) /* -0xfcfff: Hibernation Controller */
+# define TIVA_FLASHCON_BASE (TIVA_PERIPH_BASE + 0xfd000) /* -0xfdfff: FLASH Control */
+# define TIVA_SYSCON_BASE (TIVA_PERIPH_BASE + 0xfe000) /* -0xfefff: System Control */
+# define TIVA_UDMA_BASE (TIVA_PERIPH_BASE + 0xff000) /* -0xfffff: Micro Direct Memory Access */
+#elif defined(CONFIG_ARCH_CHIP_TM4C123GH6PM)
+
+# define TIVA_WDOG0_BASE (TIVA_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer 0 */
+# define TIVA_WDOG1_BASE (TIVA_PERIPH_BASE + 0x01000) /* -0x00fff: Watchdog Timer 1 */
+ /* -0x03fff: Reserved */
+# define TIVA_GPIOA_BASE (TIVA_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */
+# define TIVA_GPIOB_BASE (TIVA_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */
+# define TIVA_GPIOC_BASE (TIVA_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */
+# define TIVA_GPIOD_BASE (TIVA_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */
+# define TIVA_SSI0_BASE (TIVA_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */
+# define TIVA_SSI1_BASE (TIVA_PERIPH_BASE + 0x09000) /* -0x09fff: SSI1 */
+# define TIVA_SSI2_BASE (TIVA_PERIPH_BASE + 0x0a000) /* -0x0afff: SSI2 */
+# define TIVA_SSI3_BASE (TIVA_PERIPH_BASE + 0x0b000) /* -0x0bfff: SSI3 */
+# define TIVA_UART0_BASE (TIVA_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */
+# define TIVA_UART1_BASE (TIVA_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */
+# define TIVA_UART2_BASE (TIVA_PERIPH_BASE + 0x0e000) /* -0x0efff: UART2 */
+# define TIVA_UART3_BASE (TIVA_PERIPH_BASE + 0x0f000) /* -0x0ffff: UART3 */
+# define TIVA_UART4_BASE (TIVA_PERIPH_BASE + 0x10000) /* -0x10fff: UART4 */
+# define TIVA_UART5_BASE (TIVA_PERIPH_BASE + 0x11000) /* -0x11fff: UART5 */
+# define TIVA_UART6_BASE (TIVA_PERIPH_BASE + 0x12000) /* -0x12fff: UART6 */
+# define TIVA_UART7_BASE (TIVA_PERIPH_BASE + 0x13000) /* -0x13fff: UART7 */
+ /* -0x1ffff: Reserved */
+/* Peripheral Base Addresses */
+
+# define TIVA_I2CM0_BASE (TIVA_PERIPH_BASE + 0x20000) /* -0x207ff: I2C Master 0 */
+# define TIVA_I2CS0_BASE (TIVA_PERIPH_BASE + 0x20800) /* -0x20fbf: I2C Slave 0 */
+# define TIVA_I2CSC0_BASE (TIVA_PERIPH_BASE + 0x20fc0) /* -0x20fff: I2C Status and Control 0 */
+# define TIVA_I2CM1_BASE (TIVA_PERIPH_BASE + 0x21000) /* -0x217ff: I2C Master 1 */
+# define TIVA_I2CS1_BASE (TIVA_PERIPH_BASE + 0x21800) /* -0x21fbf: I2C Slave 1 */
+# define TIVA_I2CSC1_BASE (TIVA_PERIPH_BASE + 0x21fc0) /* -0x21fff: I2C Status and Control 1 */
+# define TIVA_I2CM2_BASE (TIVA_PERIPH_BASE + 0x22000) /* -0x227ff: I2C Master 2 */
+# define TIVA_I2CS2_BASE (TIVA_PERIPH_BASE + 0x22800) /* -0x22fbf: I2C Slave 2 */
+# define TIVA_I2CSC2_BASE (TIVA_PERIPH_BASE + 0x22fc0) /* -0x22fff: I2C Status and Control 2 */
+# define TIVA_I2CM3_BASE (TIVA_PERIPH_BASE + 0x23000) /* -0x237ff: I2C Master 3 */
+# define TIVA_I2CS3_BASE (TIVA_PERIPH_BASE + 0x23800) /* -0x23fbf: I2C Slave 3 */
+# define TIVA_I2CSC3_BASE (TIVA_PERIPH_BASE + 0x23fc0) /* -0x23fff: I2C Status and Control 3 */
+# define TIVA_GPIOE_BASE (TIVA_PERIPH_BASE + 0x24000) /* -0x24fff: GPIO Port E */
+# define TIVA_GPIOF_BASE (TIVA_PERIPH_BASE + 0x25000) /* -0x25fff: GPIO Port F */
+# define TIVA_PWM0_BASE (TIVA_PERIPH_BASE + 0x28000) /* -0x28fff: PWM 0 */
+# define TIVA_PWM1_BASE (TIVA_PERIPH_BASE + 0x29000) /* -0x29fff: PWM 1 */
+ /* -0x2ffff: Reserved */
+# define TIVA_TIMER0_BASE (TIVA_PERIPH_BASE + 0x30000) /* -0x30fff: 16/32 Timer 0 */
+# define TIVA_TIMER1_BASE (TIVA_PERIPH_BASE + 0x31000) /* -0x31fff: 16/32 Timer 1 */
+# define TIVA_TIMER2_BASE (TIVA_PERIPH_BASE + 0x32000) /* -0x32fff: 16/32 Timer 2 */
+# define TIVA_TIMER3_BASE (TIVA_PERIPH_BASE + 0x33000) /* -0x33fff: 16/32 Timer 3 */
+# define TIVA_TIMER4_BASE (TIVA_PERIPH_BASE + 0x34000) /* -0x34fff: 16/32 Timer 4 */
+# define TIVA_TIMER5_BASE (TIVA_PERIPH_BASE + 0x35000) /* -0x35fff: 16/32 Timer 5 */
+# define TIVA_WTIMER0_BASE (TIVA_PERIPH_BASE + 0x36000) /* -0x36fff: 32/64 Wide Timer 0 */
+# define TIVA_WTIMER1_BASE (TIVA_PERIPH_BASE + 0x37000) /* -0x37fff: 32/64 Wide Timer 1 */
+# define TIVA_ADC0_BASE (TIVA_PERIPH_BASE + 0x38000) /* -0x38fff: ADC 0 */
+# define TIVA_ADC1_BASE (TIVA_PERIPH_BASE + 0x39000) /* -0x39fff: ADC 1 */
+ /* -0x3bfff: Reserved */
+# define TIVA_CMP_BASE (TIVA_PERIPH_BASE + 0x3c000) /* -0x3cfff: Analog Comparators */
+ /* -0x3ffff: Reserved */
+# define TIVA_CAN0_BASE (TIVA_PERIPH_BASE + 0x40000) /* -0x40fff: CAN Controller 0 */
+# define TIVA_CAN1_BASE (TIVA_PERIPH_BASE + 0x41000) /* -0x41fff: CAN Controller 1 */
+ /* -0x4bfff: Reserved */
+# define TIVA_WTIMER2_BASE (TIVA_PERIPH_BASE + 0x4c000) /* -0x4cfff: 32/64 Wide Timer 2 */
+# define TIVA_WTIMER3_BASE (TIVA_PERIPH_BASE + 0x4d000) /* -0x4dfff: 32/64 Wide Timer 3 */
+# define TIVA_WTIMER4_BASE (TIVA_PERIPH_BASE + 0x4e000) /* -0x4efff: 32/64 Wide Timer 4 */
+# define TIVA_WTIMER5_BASE (TIVA_PERIPH_BASE + 0x4f000) /* -0x4ffff: 32/64 Wide Timer 5 */
+# define TIVA_USB_BASE (TIVA_PERIPH_BASE + 0x50000) /* -0x50fff: USB */
+ /* -0x57fff: Reserved */
+# define TIVA_GPIOAAHB_BASE (TIVA_PERIPH_BASE + 0x58000) /* -0x58fff: GPIO Port A (AHB aperture) */
+# define TIVA_GPIOBAHB_BASE (TIVA_PERIPH_BASE + 0x59000) /* -0x59fff: GPIO Port B (AHB aperture) */
+# define TIVA_GPIOCAHB_BASE (TIVA_PERIPH_BASE + 0x5a000) /* -0x5afff: GPIO Port C (AHB aperture) */
+# define TIVA_GPIODAHB_BASE (TIVA_PERIPH_BASE + 0x5b000) /* -0x5bfff: GPIO Port D (AHB aperture) */
+# define TIVA_GPIOEAHB_BASE (TIVA_PERIPH_BASE + 0x5c000) /* -0x5cfff: GPIO Port E (AHB aperture) */
+# define TIVA_GPIOFAHB_BASE (TIVA_PERIPH_BASE + 0x5d000) /* -0x5dfff: GPIO Port F (AHB aperture) */
+ /* -0xaefff: Reserved */
+# define TIVA_EEPROM_BASE (TIVA_PERIPH_BASE + 0xaf000) /* -0xaffff: EEPROM and Key Locker */
+ /* -0xf8fff: Reserved */
+# define TIVA_SYSEXC_BASE (TIVA_PERIPH_BASE + 0xf9000) /* -0xf9fff: System Exception Control */
+ /* -0xfbfff: Reserved */
+# define TIVA_HIBERNATE_BASE (TIVA_PERIPH_BASE + 0xfc000) /* -0xfcfff: Hibernation Controller */
+# define TIVA_FLASHCON_BASE (TIVA_PERIPH_BASE + 0xfd000) /* -0xfdfff: FLASH Control */
+# define TIVA_SYSCON_BASE (TIVA_PERIPH_BASE + 0xfe000) /* -0xfefff: System Control */
+# define TIVA_UDMA_BASE (TIVA_PERIPH_BASE + 0xff000) /* -0xfffff: Micro Direct Memory Access */
#else
# error "Peripheral base addresses not specified for this Stellaris chip"
#endif
diff --git a/nuttx/arch/arm/src/tiva/chip/tm4c_pinmap.h b/nuttx/arch/arm/src/tiva/chip/tm4c_pinmap.h
index a38659b78..cecac78ea 100644
--- a/nuttx/arch/arm/src/tiva/chip/tm4c_pinmap.h
+++ b/nuttx/arch/arm/src/tiva/chip/tm4c_pinmap.h
@@ -451,8 +451,176 @@
# define GPIO_WTIM5_CCP1_3 (GPIO_FUNC_PFIO | GPIO_ALT_7 | GPIO_PORTQ | GPIO_PIN_7)
# define GPIO_WTIM5_CCP1_4 (GPIO_FUNC_PFIO | GPIO_ALT_8 | GPIO_PORTM | GPIO_PIN_3)
+#elif defined(CONFIG_ARCH_CHIP_TM4C123GH6PMI)
+
+# define GPIO_ADC_AIN0 (GPIO_FUNC_ANINPUT | GPIO_PORTE | GPIO_PIN_3)
+# define GPIO_ADC_AIN1 (GPIO_FUNC_ANINPUT | GPIO_PORTE | GPIO_PIN_2)
+# define GPIO_ADC_AIN2 (GPIO_FUNC_ANINPUT | GPIO_PORTE | GPIO_PIN_1)
+# define GPIO_ADC_AIN3 (GPIO_FUNC_ANINPUT | GPIO_PORTE | GPIO_PIN_0)
+# define GPIO_ADC_AIN4 (GPIO_FUNC_ANINPUT | GPIO_PORTD | GPIO_PIN_3)
+# define GPIO_ADC_AIN5 (GPIO_FUNC_ANINPUT | GPIO_PORTD | GPIO_PIN_2)
+# define GPIO_ADC_AIN6 (GPIO_FUNC_ANINPUT | GPIO_PORTD | GPIO_PIN_1)
+# define GPIO_ADC_AIN7 (GPIO_FUNC_ANINPUT | GPIO_PORTD | GPIO_PIN_0)
+# define GPIO_ADC_AIN8 (GPIO_FUNC_ANINPUT | GPIO_PORTE | GPIO_PIN_5)
+# define GPIO_ADC_AIN9 (GPIO_FUNC_ANINPUT | GPIO_PORTE | GPIO_PIN_4)
+# define GPIO_ADC_AIN10 (GPIO_FUNC_ANINPUT | GPIO_PORTB | GPIO_PIN_4)
+# define GPIO_ADC_AIN11 (GPIO_FUNC_ANINPUT | GPIO_PORTB | GPIO_PIN_5)
+
+# define GPIO_CAN0_RX_1 (GPIO_FUNC_PFINPUT | GPIO_ALT_3 | GPIO_PORTF | GPIO_PIN_0)
+# define GPIO_CAN0_RX_2 (GPIO_FUNC_PFINPUT | GPIO_ALT_8 | GPIO_PORTB | GPIO_PIN_4)
+# define GPIO_CAN0_RX_3 (GPIO_FUNC_PFINPUT | GPIO_ALT_8 | GPIO_PORTE | GPIO_PIN_4)
+# define GPIO_CAN0_TX_1 (GPIO_FUNC_PFOUTPUT | GPIO_ALT_3 | GPIO_PORTF | GPIO_PIN_3)
+# define GPIO_CAN0_TX_2 (GPIO_FUNC_PFOUTPUT | GPIO_ALT_8 | GPIO_PORTB | GPIO_PIN_5)
+# define GPIO_CAN0_TX_3 (GPIO_FUNC_PFOUTPUT | GPIO_ALT_8 | GPIO_PORTE | GPIO_PIN_5)
+# define GPIO_CAN1_RX_1 (GPIO_FUNC_PFINPUT | GPIO_ALT_8 | GPIO_PORTA | GPIO_PIN_0)
+# define GPIO_CAN1_TX_1 (GPIO_FUNC_PFOUTPUT | GPIO_ALT_8 | GPIO_PORTA | GPIO_PIN_1)
+
+# define GPIO_CMP0_NIN (GPIO_FUNC_ANINPUT | GPIO_PORTC | GPIO_PIN_7)
+# define GPIO_CMP0_OUT_2 (GPIO_FUNC_PFOUTPUT | GPIO_ALT_9 | GPIO_PORTF | GPIO_PIN_0)
+# define GPIO_CMP0_PIN (GPIO_FUNC_ANINPUT | GPIO_PORTC | GPIO_PIN_6)
+# define GPIO_CMP1_NIN (GPIO_FUNC_ANINPUT | GPIO_PORTC | GPIO_PIN_4)
+# define GPIO_CMP1_OUT_2 (GPIO_FUNC_PFOUTPUT | GPIO_ALT_9 | GPIO_PORTF | GPIO_PIN_1)
+# define GPIO_CMP1_PIN (GPIO_FUNC_ANINPUT | GPIO_PORTC | GPIO_PIN_5)
+
+# define GPIO_I2C0_SCL (GPIO_FUNC_PFIO | GPIO_ALT_3 | GPIO_PORTB | GPIO_PIN_2)
+# define GPIO_I2C0_SDA (GPIO_FUNC_PFIO | GPIO_ALT_3 | GPIO_PORTB | GPIO_PIN_3)
+# define GPIO_I2C1_SCL (GPIO_FUNC_PFIO | GPIO_ALT_3 | GPIO_PORTA | GPIO_PIN_6)
+# define GPIO_I2C1_SDA (GPIO_FUNC_PFIO | GPIO_ALT_3 | GPIO_PORTA | GPIO_PIN_7)
+# define GPIO_I2C2_SCL (GPIO_FUNC_PFIO | GPIO_ALT_3 | GPIO_PORTE | GPIO_PIN_4)
+# define GPIO_I2C2_SDA (GPIO_FUNC_PFIO | GPIO_ALT_3 | GPIO_PORTE | GPIO_PIN_5)
+# define GPIO_I2C3_SCL (GPIO_FUNC_PFIO | GPIO_ALT_3 | GPIO_PORTD | GPIO_PIN_0)
+# define GPIO_I2C3_SDA (GPIO_FUNC_PFIO | GPIO_ALT_3 | GPIO_PORTD | GPIO_PIN_1)
+
+# define GPIO_M0_PWM0 (GPIO_FUNC_PFOUTPUT | GPIO_ALT_4 | GPIO_PORTB | GPIO_PIN_6)
+# define GPIO_M0_PWM1 (GPIO_FUNC_PFOUTPUT | GPIO_ALT_4 | GPIO_PORTB | GPIO_PIN_7)
+# define GPIO_M0_PWM2 (GPIO_FUNC_PFOUTPUT | GPIO_ALT_4 | GPIO_PORTB | GPIO_PIN_4)
+# define GPIO_M0_PWM3 (GPIO_FUNC_PFOUTPUT | GPIO_ALT_4 | GPIO_PORTB | GPIO_PIN_5)
+# define GPIO_M0_PWM4 (GPIO_FUNC_PFOUTPUT | GPIO_ALT_4 | GPIO_PORTE | GPIO_PIN_4)
+# define GPIO_M0_PWM5 (GPIO_FUNC_PFOUTPUT | GPIO_ALT_4 | GPIO_PORTE | GPIO_PIN_5)
+# define GPIO_M0_PWM6 (GPIO_FUNC_PFOUTPUT | GPIO_ALT_4 | GPIO_PORTC | GPIO_PIN_4)
+# define GPIO_M0_PWM7 (GPIO_FUNC_PFOUTPUT | GPIO_ALT_4 | GPIO_PORTC | GPIO_PIN_5)
+# define GPIO_M0_PWM_FAULT0_1 (GPIO_FUNC_PFINPUT | GPIO_ALT_4 | GPIO_PORTD | GPIO_PIN_2)
+# define GPIO_M0_PWM_FAULT0_2 (GPIO_FUNC_PFINPUT | GPIO_ALT_4 | GPIO_PORTD | GPIO_PIN_6)
+# define GPIO_M0_PWM_FAULT0_3 (GPIO_FUNC_PFINPUT | GPIO_ALT_4 | GPIO_PORTF | GPIO_PIN_2)
+# define GPIO_M1_PWM0 (GPIO_FUNC_PFOUTPUT | GPIO_ALT_5 | GPIO_PORTD | GPIO_PIN_0)
+# define GPIO_M1_PWM1 (GPIO_FUNC_PFOUTPUT | GPIO_ALT_5 | GPIO_PORTD | GPIO_PIN_1)
+# define GPIO_M1_PWM2_1 (GPIO_FUNC_PFOUTPUT | GPIO_ALT_5 | GPIO_PORTA | GPIO_PIN_6)
+# define GPIO_M1_PWM2_2 (GPIO_FUNC_PFOUTPUT | GPIO_ALT_5 | GPIO_PORTE | GPIO_PIN_4)
+# define GPIO_M1_PWM3_1 (GPIO_FUNC_PFOUTPUT | GPIO_ALT_5 | GPIO_PORTA | GPIO_PIN_7)
+# define GPIO_M1_PWM3_2 (GPIO_FUNC_PFOUTPUT | GPIO_ALT_5 | GPIO_PORTE | GPIO_PIN_5)
+# define GPIO_M1_PWM4 (GPIO_FUNC_PFOUTPUT | GPIO_ALT_5 | GPIO_PORTF | GPIO_PIN_0)
+# define GPIO_M1_PWM5 (GPIO_FUNC_PFOUTPUT | GPIO_ALT_5 | GPIO_PORTF | GPIO_PIN_1)
+# define GPIO_M1_PWM6 (GPIO_FUNC_PFOUTPUT | GPIO_ALT_5 | GPIO_PORTF | GPIO_PIN_2)
+# define GPIO_M1_PWM7 (GPIO_FUNC_PFOUTPUT | GPIO_ALT_5 | GPIO_PORTF | GPIO_PIN_3)
+# define GPIO_M1_PWM_FAULT0_1 (GPIO_FUNC_PFINPUT | GPIO_ALT_5 | GPIO_PORTF | GPIO_PIN_4)
+
+# define GPIO_NMI_1 (GPIO_FUNC_PFIO | GPIO_ALT_8 | GPIO_PORTD | GPIO_PIN_7)
+# define GPIO_NMI_2 (GPIO_FUNC_PFIO | GPIO_ALT_8 | GPIO_PORTF | GPIO_PIN_0)
+
+# define GPIO_QEI0_IDX_1 (GPIO_FUNC_PFIO | GPIO_ALT_6 | GPIO_PORTD | GPIO_PIN_3)
+# define GPIO_QEI0_IDX_2 (GPIO_FUNC_PFIO | GPIO_ALT_6 | GPIO_PORTF | GPIO_PIN_4)
+# define GPIO_QEI0_PHA_1 (GPIO_FUNC_PFIO | GPIO_ALT_6 | GPIO_PORTD | GPIO_PIN_6)
+# define GPIO_QEI0_PHA_2 (GPIO_FUNC_PFIO | GPIO_ALT_6 | GPIO_PORTF | GPIO_PIN_0)
+# define GPIO_QEI0_PHB_1 (GPIO_FUNC_PFIO | GPIO_ALT_6 | GPIO_PORTD | GPIO_PIN_7)
+# define GPIO_QEI0_PHB_2 (GPIO_FUNC_PFIO | GPIO_ALT_6 | GPIO_PORTF | GPIO_PIN_1)
+# define GPIO_QEI1_IDX (GPIO_FUNC_PFIO | GPIO_ALT_6 | GPIO_PORTC | GPIO_PIN_4)
+# define GPIO_QEI1_PHA (GPIO_FUNC_PFIO | GPIO_ALT_6 | GPIO_PORTC | GPIO_PIN_5)
+# define GPIO_QEI1_PHB (GPIO_FUNC_PFIO | GPIO_ALT_6 | GPIO_PORTC | GPIO_PIN_6)
+
+# define GPIO_SSI0_CLK (GPIO_FUNC_PFIO | GPIO_ALT_2 | GPIO_PORTA | GPIO_PIN_2)
+# define GPIO_SSI0_FSS (GPIO_FUNC_PFIO | GPIO_ALT_2 | GPIO_PORTA | GPIO_PIN_3)
+# define GPIO_SSI0_RX (GPIO_FUNC_PFIO | GPIO_ALT_2 | GPIO_PORTA | GPIO_PIN_4)
+# define GPIO_SSI0_TX (GPIO_FUNC_PFIO | GPIO_ALT_2 | GPIO_PORTA | GPIO_PIN_5)
+# define GPIO_SSI1_CLK_1 (GPIO_FUNC_PFIO | GPIO_ALT_2 | GPIO_PORTD | GPIO_PIN_0)
+# define GPIO_SSI1_CLK_2 (GPIO_FUNC_PFIO | GPIO_ALT_2 | GPIO_PORTF | GPIO_PIN_2)
+# define GPIO_SSI1_FSS_1 (GPIO_FUNC_PFIO | GPIO_ALT_2 | GPIO_PORTD | GPIO_PIN_1)
+# define GPIO_SSI1_FSS_2 (GPIO_FUNC_PFIO | GPIO_ALT_2 | GPIO_PORTF | GPIO_PIN_3)
+# define GPIO_SSI1_RX_1 (GPIO_FUNC_PFIO | GPIO_ALT_2 | GPIO_PORTD | GPIO_PIN_2)
+# define GPIO_SSI1_RX_2 (GPIO_FUNC_PFIO | GPIO_ALT_2 | GPIO_PORTF | GPIO_PIN_0)
+# define GPIO_SSI1_TX_1 (GPIO_FUNC_PFIO | GPIO_ALT_2 | GPIO_PORTD | GPIO_PIN_3)
+# define GPIO_SSI1_TX_2 (GPIO_FUNC_PFIO | GPIO_ALT_2 | GPIO_PORTF | GPIO_PIN_1)
+# define GPIO_SSI2_CLK_1 (GPIO_FUNC_PFIO | GPIO_ALT_2 | GPIO_PORTB | GPIO_PIN_4)
+# define GPIO_SSI2_FSS_1 (GPIO_FUNC_PFIO | GPIO_ALT_2 | GPIO_PORTB | GPIO_PIN_5)
+# define GPIO_SSI2_RX_1 (GPIO_FUNC_PFIO | GPIO_ALT_2 | GPIO_PORTB | GPIO_PIN_6)
+# define GPIO_SSI2_TX_1 (GPIO_FUNC_PFIO | GPIO_ALT_2 | GPIO_PORTB | GPIO_PIN_7)
+# define GPIO_SSI3_CLK_1 (GPIO_FUNC_PFIO | GPIO_ALT_1 | GPIO_PORTD | GPIO_PIN_0)
+# define GPIO_SSI3_FSS_1 (GPIO_FUNC_PFIO | GPIO_ALT_1 | GPIO_PORTD | GPIO_PIN_1)
+# define GPIO_SSI3_RX_1 (GPIO_FUNC_PFIO | GPIO_ALT_1 | GPIO_PORTD | GPIO_PIN_2)
+# define GPIO_SSI3_TX_1 (GPIO_FUNC_PFIO | GPIO_ALT_1 | GPIO_PORTD | GPIO_PIN_3)
+
+# define GPIO_TCK_SWCLK (GPIO_FUNC_PFIO | GPIO_ALT_1 | GPIO_PORTC | GPIO_PIN_0)
+# define GPIO_TDI (GPIO_FUNC_PFIO | GPIO_ALT_1 | GPIO_PORTC | GPIO_PIN_2)
+# define GPIO_TDO_SWO (GPIO_FUNC_PFIO | GPIO_ALT_1 | GPIO_PORTC | GPIO_PIN_3)
+# define GPIO_TMS_SWDIO (GPIO_FUNC_PFIO | GPIO_ALT_1 | GPIO_PORTC | GPIO_PIN_1)
+
+# define GPIO_TR_CLK (GPIO_FUNC_PFIO | GPIO_ALT_14 | GPIO_PORTF | GPIO_PIN_3)
+# define GPIO_TR_D0 (GPIO_FUNC_PFIO | GPIO_ALT_14 | GPIO_PORTF | GPIO_PIN_2)
+# define GPIO_TR_D1 (GPIO_FUNC_PFIO | GPIO_ALT_14 | GPIO_PORTF | GPIO_PIN_1)
+
+# define GPIO_TIM0_CCP0_1 (GPIO_FUNC_PFIO | GPIO_ALT_7 | GPIO_PORTB | GPIO_PIN_6)
+# define GPIO_TIM0_CCP0_2 (GPIO_FUNC_PFIO | GPIO_ALT_7 | GPIO_PORTF | GPIO_PIN_0)
+# define GPIO_TIM0_CCP1_1 (GPIO_FUNC_PFIO | GPIO_ALT_7 | GPIO_PORTB | GPIO_PIN_7)
+# define GPIO_TIM0_CCP1_2 (GPIO_FUNC_PFIO | GPIO_ALT_7 | GPIO_PORTF | GPIO_PIN_1)
+# define GPIO_TIM1_CCP0_1 (GPIO_FUNC_PFIO | GPIO_ALT_7 | GPIO_PORTB | GPIO_PIN_4)
+# define GPIO_TIM1_CCP0_2 (GPIO_FUNC_PFIO | GPIO_ALT_7 | GPIO_PORTF | GPIO_PIN_2)
+# define GPIO_TIM1_CCP1_1 (GPIO_FUNC_PFIO | GPIO_ALT_7 | GPIO_PORTB | GPIO_PIN_5)
+# define GPIO_TIM1_CCP1_2 (GPIO_FUNC_PFIO | GPIO_ALT_7 | GPIO_PORTF | GPIO_PIN_3)
+# define GPIO_TIM2_CCP0_1 (GPIO_FUNC_PFIO | GPIO_ALT_7 | GPIO_PORTB | GPIO_PIN_0)
+# define GPIO_TIM2_CCP0_2 (GPIO_FUNC_PFIO | GPIO_ALT_7 | GPIO_PORTF | GPIO_PIN_4)
+# define GPIO_TIM2_CCP1_1 (GPIO_FUNC_PFIO | GPIO_ALT_7 | GPIO_PORTB | GPIO_PIN_1)
+# define GPIO_TIM3_CCP0_1 (GPIO_FUNC_PFIO | GPIO_ALT_7 | GPIO_PORTB | GPIO_PIN_2)
+# define GPIO_TIM3_CCP1_1 (GPIO_FUNC_PFIO | GPIO_ALT_7 | GPIO_PORTB | GPIO_PIN_3)
+# define GPIO_TIM4_CCP0_1 (GPIO_FUNC_PFIO | GPIO_ALT_7 | GPIO_PORTC | GPIO_PIN_0)
+# define GPIO_TIM4_CCP1_1 (GPIO_FUNC_PFIO | GPIO_ALT_7 | GPIO_PORTC | GPIO_PIN_1)
+# define GPIO_TIM5_CCP0_1 (GPIO_FUNC_PFIO | GPIO_ALT_7 | GPIO_PORTC | GPIO_PIN_2)
+# define GPIO_TIM5_CCP1_1 (GPIO_FUNC_PFIO | GPIO_ALT_7 | GPIO_PORTC | GPIO_PIN_3)
+
+# define GPIO_UART0_RX (GPIO_FUNC_PFINPUT | GPIO_ALT_1 | GPIO_PORTA | GPIO_PIN_0)
+# define GPIO_UART0_TX (GPIO_FUNC_PFOUTPUT | GPIO_ALT_1 | GPIO_PORTA | GPIO_PIN_1)
+# define GPIO_UART1_CTS_1 (GPIO_FUNC_PFINPUT | GPIO_ALT_1 | GPIO_PORTF | GPIO_PIN_1)
+# define GPIO_UART1_CTS_2 (GPIO_FUNC_PFINPUT | GPIO_ALT_8 | GPIO_PORTC | GPIO_PIN_5)
+# define GPIO_UART1_RTS_1 (GPIO_FUNC_PFOUTPUT | GPIO_ALT_1 | GPIO_PORTF | GPIO_PIN_0)
+# define GPIO_UART1_RTS_2 (GPIO_FUNC_PFOUTPUT | GPIO_ALT_8 | GPIO_PORTC | GPIO_PIN_4)
+# define GPIO_UART1_RX_1 (GPIO_FUNC_PFINPUT | GPIO_ALT_1 | GPIO_PORTB | GPIO_PIN_0)
+# define GPIO_UART1_RX_2 (GPIO_FUNC_PFINPUT | GPIO_ALT_2 | GPIO_PORTC | GPIO_PIN_4)
+# define GPIO_UART1_TX_1 (GPIO_FUNC_PFOUTPUT | GPIO_ALT_1 | GPIO_PORTB | GPIO_PIN_1)
+# define GPIO_UART1_TX_2 (GPIO_FUNC_PFOUTPUT | GPIO_ALT_2 | GPIO_PORTC | GPIO_PIN_5)
+# define GPIO_UART2_RX (GPIO_FUNC_PFINPUT | GPIO_ALT_1 | GPIO_PORTD | GPIO_PIN_6)
+# define GPIO_UART2_TX (GPIO_FUNC_PFOUTPUT | GPIO_ALT_1 | GPIO_PORTD | GPIO_PIN_7)
+# define GPIO_UART3_RX (GPIO_FUNC_PFINPUT | GPIO_ALT_1 | GPIO_PORTC | GPIO_PIN_6)
+# define GPIO_UART3_TX (GPIO_FUNC_PFOUTPUT | GPIO_ALT_1 | GPIO_PORTC | GPIO_PIN_7)
+# define GPIO_UART4_RX (GPIO_FUNC_PFINPUT | GPIO_ALT_1 | GPIO_PORTC | GPIO_PIN_4)
+# define GPIO_UART4_TX (GPIO_FUNC_PFOUTPUT | GPIO_ALT_1 | GPIO_PORTC | GPIO_PIN_5)
+# define GPIO_UART5_RX (GPIO_FUNC_PFINPUT | GPIO_ALT_1 | GPIO_PORTE | GPIO_PIN_4)
+# define GPIO_UART5_TX (GPIO_FUNC_PFOUTPUT | GPIO_ALT_1 | GPIO_PORTE | GPIO_PIN_5)
+# define GPIO_UART6_RX (GPIO_FUNC_PFINPUT | GPIO_ALT_1 | GPIO_PORTD | GPIO_PIN_4)
+# define GPIO_UART6_TX (GPIO_FUNC_PFOUTPUT | GPIO_ALT_1 | GPIO_PORTD | GPIO_PIN_5)
+# define GPIO_UART7_RX (GPIO_FUNC_PFINPUT | GPIO_ALT_1 | GPIO_PORTE | GPIO_PIN_0)
+# define GPIO_UART7_TX (GPIO_FUNC_PFOUTPUT | GPIO_ALT_1 | GPIO_PORTE | GPIO_PIN_1)
+
+# define GPIO_USB0_EPEN_1 (GPIO_FUNC_PFOUTPUT | GPIO_ALT_8 | GPIO_PORTC | GPIO_PIN_6)
+# define GPIO_USB0_EPEN_2 (GPIO_FUNC_PFOUTPUT | GPIO_ALT_8 | GPIO_PORTD | GPIO_PIN_2)
+# define GPIO_USB0_EPEN_3 (GPIO_FUNC_PFOUTPUT | GPIO_ALT_8 | GPIO_PORTF | GPIO_PIN_4)
+# define GPIO_USB0_ID (GPIO_FUNC_ANINPUT | GPIO_PORTB | GPIO_PIN_0)
+# define GPIO_USB0_PFLT_1 (GPIO_FUNC_PFINPUT | GPIO_ALT_8 | GPIO_PORTC | GPIO_PIN_7)
+# define GPIO_USB0_PFLT_2 (GPIO_FUNC_PFINPUT | GPIO_ALT_8 | GPIO_PORTD | GPIO_PIN_3)
+# define GPIO_USB0_VBUS (GPIO_FUNC_ANIO | GPIO_PORTB | GPIO_PIN_1)
+
+# define GPIO_WTIM0_CCP0 (GPIO_FUNC_PFIO | GPIO_ALT_7 | GPIO_PORTC | GPIO_PIN_4)
+# define GPIO_WTIM0_CCP1 (GPIO_FUNC_PFIO | GPIO_ALT_7 | GPIO_PORTC | GPIO_PIN_5)
+# define GPIO_WTIM1_CCP0 (GPIO_FUNC_PFIO | GPIO_ALT_7 | GPIO_PORTC | GPIO_PIN_6)
+# define GPIO_WTIM1_CCP1 (GPIO_FUNC_PFIO | GPIO_ALT_7 | GPIO_PORTC | GPIO_PIN_7)
+# define GPIO_WTIM2_CCP0 (GPIO_FUNC_PFIO | GPIO_ALT_7 | GPIO_PORTD | GPIO_PIN_0)
+# define GPIO_WTIM2_CCP1 (GPIO_FUNC_PFIO | GPIO_ALT_7 | GPIO_PORTD | GPIO_PIN_1)
+# define GPIO_WTIM3_CCP0 (GPIO_FUNC_PFIO | GPIO_ALT_7 | GPIO_PORTD | GPIO_PIN_2)
+# define GPIO_WTIM3_CCP1 (GPIO_FUNC_PFIO | GPIO_ALT_7 | GPIO_PORTD | GPIO_PIN_3)
+# define GPIO_WTIM4_CCP0 (GPIO_FUNC_PFIO | GPIO_ALT_7 | GPIO_PORTD | GPIO_PIN_4)
+# define GPIO_WTIM4_CCP1 (GPIO_FUNC_PFIO | GPIO_ALT_7 | GPIO_PORTD | GPIO_PIN_5)
+# define GPIO_WTIM5_CCP0 (GPIO_FUNC_PFIO | GPIO_ALT_7 | GPIO_PORTD | GPIO_PIN_6)
+# define GPIO_WTIM5_CCP1 (GPIO_FUNC_PFIO | GPIO_ALT_7 | GPIO_PORTD | GPIO_PIN_7)
+
#else
-# error "Unknown Stellaris chip"
+# error "Unknown TIVA chip"
#endif
/************************************************************************************
diff --git a/nuttx/arch/arm/src/tiva/chip/tm4c_vectors.h b/nuttx/arch/arm/src/tiva/chip/tm4c_vectors.h
index ef8e72b1c..529bc2f9b 100644
--- a/nuttx/arch/arm/src/tiva/chip/tm4c_vectors.h
+++ b/nuttx/arch/arm/src/tiva/chip/tm4c_vectors.h
@@ -72,7 +72,6 @@ VECTOR(tiva_uart0, TIVA_IRQ_UART0) /* Vector 21: UART 0 */
VECTOR(tiva_uart1, TIVA_IRQ_UART1) /* Vector 22: UART 1 */
VECTOR(tiva_ssi0, TIVA_IRQ_SSI0) /* Vector 23: SSI 0 */
VECTOR(tiva_i2c0, TIVA_IRQ_I2C0) /* Vector 24: I2C 0 */
-
VECTOR(tiva_pwm0_fault, TIVA_IRQ_PWM0_FAULT) /* Vector 25: PWM0 Fault */
VECTOR(tiva_pwm0_gen0, TIVA_IRQ_PWM0_GEN0) /* Vector 26: PWM0 Generator 0 */
VECTOR(tiva_pwm0_gen1, TIVA_IRQ_PWM0_GEN1) /* Vector 27: PWM0 Generator 1 */
@@ -99,7 +98,7 @@ VECTOR(tiva_flashcon, TIVA_IRQ_FLASHCON) /* Vector 45: FLASH and EEPROM Cont
VECTOR(tiva_gpiof, TIVA_IRQ_GPIOF) /* Vector 46: GPIO Port F */
VECTOR(tiva_gpiog, TIVA_IRQ_GPIOG) /* Vector 47: GPIO Port G */
VECTOR(tiva_gpioh, TIVA_IRQ_GPIOH) /* Vector 48: GPIO Port H */
-VECTOR(tiva_uart2, TIVA_IRQ_UART2) /* Vector 22: UART 2 */
+VECTOR(tiva_uart2, TIVA_IRQ_UART2) /* Vector 49: UART 2 */
VECTOR(tiva_ssi1, TIVA_IRQ_SSI1) /* Vector 50: SSI 1 */
VECTOR(tiva_timer3a, TIVA_IRQ_TIMER3A) /* Vector 51: 16/32-Bit Timer 3 A */
@@ -219,6 +218,176 @@ VECTOR(tiva_pwm1_fault, TIVA_IRQ_PWM1_FAULT) /* Vector 154: PWM1 Fault */
# endif /* CONFIG_ARMV7M_CMNVECTOR */
+#elif defined(CONFIG_ARCH_CHIP_TM4C123GH6PMI)
+
+/* If the common ARMv7-M vector handling is used, then all it needs is the following
+ * definition that provides the number of supported vectors.
+ */
+
+# ifdef CONFIG_ARMV7M_CMNVECTOR
+
+/* Reserve 155 interrupt table entries for I/O interrupts. */
+
+ARMV7M_PERIPHERAL_INTERRUPTS 155
+
+# else
+
+VECTOR(tiva_gpioa, TIVA_IRQ_GPIOA) /* Vector 16: GPIO Port A */
+VECTOR(tiva_gpiob, TIVA_IRQ_GPIOB) /* Vector 17: GPIO Port B */
+VECTOR(tiva_gpioc, TIVA_IRQ_GPIOC) /* Vector 18: GPIO Port C */
+VECTOR(tiva_gpiod, TIVA_IRQ_GPIOD) /* Vector 19: GPIO Port D */
+
+VECTOR(tiva_gpioe, TIVA_IRQ_GPIOE) /* Vector 20: GPIO Port E */
+VECTOR(tiva_uart0, TIVA_IRQ_UART0) /* Vector 21: UART 0 */
+VECTOR(tiva_uart1, TIVA_IRQ_UART1) /* Vector 22: UART 1 */
+VECTOR(tiva_ssi0, TIVA_IRQ_SSI0) /* Vector 23: SSI 0 */
+VECTOR(tiva_i2c0, TIVA_IRQ_I2C0) /* Vector 24: I2C 0 */
+VECTOR(tiva_pwm0_fault, TIVA_IRQ_PWM0_FAULT) /* Vector 25: PWM0 Fault */
+VECTOR(tiva_pwm0_gen0, TIVA_IRQ_PWM0_GEN0) /* Vector 26: PWM0 Generator 0 */
+VECTOR(tiva_pwm0_gen1, TIVA_IRQ_PWM0_GEN1) /* Vector 27: PWM0 Generator 1 */
+VECTOR(tiva_pwm0_gen2, TIVA_IRQ_PWM0_GEN2) /* Vector 28: PWM0 Generator 2 */
+VECTOR(tiva_qei0, TIVA_IRQ_QEI0) /* Vector 29: QEI0 */
+
+VECTOR(tiva_adc0, TIVA_IRQ_ADC0) /* Vector 30: ADC Sequence 0 */
+VECTOR(tiva_adc1, TIVA_IRQ_ADC1) /* Vector 31: ADC Sequence 1 */
+VECTOR(tiva_adc2, TIVA_IRQ_ADC2) /* Vector 32: ADC Sequence 2 */
+VECTOR(tiva_adc3, TIVA_IRQ_ADC3) /* Vector 33: ADC Sequence 3 */
+VECTOR(tiva_wdog, TIVA_IRQ_WDOG) /* Vector 34: Watchdog Timers 0 and 1 */
+VECTOR(tiva_timer0a, TIVA_IRQ_TIMER0A) /* Vector 35: 16/32-Bit Timer 0 A */
+VECTOR(tiva_timer0b, TIVA_IRQ_TIMER0B) /* Vector 36: 16/32-Bit Timer 0 B */
+VECTOR(tiva_timer1a, TIVA_IRQ_TIMER1A) /* Vector 37: 16/32-Bit Timer 1 A */
+VECTOR(tiva_timer1b, TIVA_IRQ_TIMER1B) /* Vector 38: 16/32-Bit Timer 1 B */
+VECTOR(tiva_timer2a, TIVA_IRQ_TIMER2A) /* Vector 39: 16/32-Bit Timer 2 A */
+
+VECTOR(tiva_timer2b, TIVA_IRQ_TIMER2B) /* Vector 40: 16/32-Bit Timer 2 B */
+VECTOR(tiva_compare0, TIVA_IRQ_COMPARE0) /* Vector 41: Analog Comparator 0 */
+VECTOR(tiva_compare1, TIVA_IRQ_COMPARE1) /* Vector 42: Analog Comparator 1 */
+VECTOR(tiva_compare2, TIVA_IRQ_COMPARE2) /* Vector 43: Analog Comparator 2 */
+VECTOR(tiva_syscon, TIVA_IRQ_SYSCON) /* Vector 44: System Control */
+VECTOR(tiva_flashcon, TIVA_IRQ_FLASHCON) /* Vector 45: FLASH and EEPROM Control */
+VECTOR(tiva_gpiof, TIVA_IRQ_GPIOF) /* Vector 46: GPIO Port F */
+UNUSED(TIVA_RESERVED_47) /* Vector 47: GPIO Port G */
+UNUSED(TIVA_RESERVED_48) /* Vector 48: GPIO Port H */
+VECTOR(tiva_uart2, TIVA_IRQ_UART2) /* Vector 49: UART 2 */
+
+VECTOR(tiva_ssi1, TIVA_IRQ_SSI1) /* Vector 50: SSI 1 */
+VECTOR(tiva_timer3a, TIVA_IRQ_TIMER3A) /* Vector 51: 16/32-Bit Timer 3 A */
+VECTOR(tiva_timer3b, TIVA_IRQ_TIMER3B) /* Vector 52: 16/32-Bit Timer 3 B */
+VECTOR(tiva_i2c1, TIVA_IRQ_I2C1) /* Vector 53: I2C 1 */
+VECTOR(tiva_qei1, TIVA_IRQ_QEI1) /* Vector 54: QEI1 */
+VECTOR(tiva_can0, TIVA_IRQ_CAN0) /* Vector 55: CAN 0 */
+VECTOR(tiva_can1, TIVA_IRQ_CAN1) /* Vector 56: CAN 1 */
+UNUSED(TIVA_RESERVED_57) /* Vector 57: Reserved */
+UNUSED(TIVA_RESERVED_58) /* Vector 58: Reserved */
+VECTOR(tiva_hibernate, TIVA_IRQ_HIBERNATE) /* Vector 59: Hibernation Module */
+
+VECTOR(tiva_usb, TIVA_IRQ_USB) /* Vector 60: USB */
+VECTOR(tiva_pwm0_gen3, TIVA_IRQ_PWM0_GEN3) /* Vector 61: PWM0 Generator 3 */
+VECTOR(tiva_udmasoft, TIVA_IRQ_UDMASOFT) /* Vector 62: uDMA Software */
+VECTOR(tiva_udmaerro, TIVA_IRQ_UDMAERROR) /* Vector 63: uDMA Error */
+VECTOR(tiva_adc1_0, TIVA_IRQ_ADC1_0) /* Vector 64: ADC1 Sequence 0 */
+VECTOR(tiva_adc1_1, TIVA_IRQ_ADC1_1) /* Vector 65: ADC1 Sequence 1 */
+VECTOR(tiva_adc1_2, TIVA_IRQ_ADC1_2) /* Vector 66: ADC1 Sequence 2 */
+VECTOR(tiva_adc1_3, TIVA_IRQ_ADC1_3) /* Vector 67: ADC1 Sequence 3 */
+UNUSED(TIVA_RESERVED_68) /* Vector 68: Reserved */
+UNUSED(TIVA_RESERVED_69) /* Vector 69: Reserved */
+
+UNUSED(TIVA_RESERVED_70) /* Vector 70: GPIO Port J */
+UNUSED(TIVA_RESERVED_71) /* Vector 71: GPIO Port K */
+UNUSED(TIVA_RESERVED_72) /* Vector 72: GPIO Port L */
+VECTOR(tiva_ssi2, TIVA_IRQ_SSI2) /* Vector 73: SSI 2 */
+VECTOR(tiva_ssi3, TIVA_IRQ_SSI3) /* Vector 74: SSI 3 */
+VECTOR(tiva_uart3, TIVA_IRQ_UART3) /* Vector 75: UART 3 */
+VECTOR(tiva_uart4, TIVA_IRQ_UART4) /* Vector 76: UART 4 */
+VECTOR(tiva_uart5, TIVA_IRQ_UART5) /* Vector 77: UART 5 */
+VECTOR(tiva_uart6, TIVA_IRQ_UART6) /* Vector 78: UART 6 */
+VECTOR(tiva_uart7, TIVA_IRQ_UART7) /* Vector 79: UART 7 */
+
+UNUSED(TIVA_RESERVED_80) /* Vector 80: Reserved */
+UNUSED(TIVA_RESERVED_81) /* Vector 81: Reserved */
+UNUSED(TIVA_RESERVED_82) /* Vector 82: Reserved */
+UNUSED(TIVA_RESERVED_83) /* Vector 83: Reserved */
+VECTOR(tiva_i2c2, TIVA_IRQ_I2C2) /* Vector 84: I2C 2 */
+VECTOR(tiva_i2c3, TIVA_IRQ_I2C3) /* Vector 85: I2C 3 */
+VECTOR(tiva_timer4a, TIVA_IRQ_TIMER4A) /* Vector 86: 16/32-Bit Timer 4 A */
+VECTOR(tiva_timer4b, TIVA_IRQ_TIMER4B) /* Vector 87: 16/32-Bit Timer 4 B */
+UNUSED(TIVA_RESERVED_88) /* Vector 88: Reserved */
+UNUSED(TIVA_RESERVED_89) /* Vector 89: Reserved */
+
+UNUSED(TIVA_RESERVED_90) /* Vector 90: Reserved */
+UNUSED(TIVA_RESERVED_91) /* Vector 91: Reserved */
+UNUSED(TIVA_RESERVED_92) /* Vector 92: Reserved */
+UNUSED(TIVA_RESERVED_93) /* Vector 93: Reserved */
+UNUSED(TIVA_RESERVED_94) /* Vector 94: Reserved */
+UNUSED(TIVA_RESERVED_95) /* Vector 95: Reserved */
+UNUSED(TIVA_RESERVED_96) /* Vector 96: Reserved */
+UNUSED(TIVA_RESERVED_97) /* Vector 97: Reserved */
+UNUSED(TIVA_RESERVED_98) /* Vector 98: Reserved */
+UNUSED(TIVA_RESERVED_99) /* Vector 99: Reserved */
+
+UNUSED(TIVA_RESERVED_100) /* Vector 100: Reserved */
+UNUSED(TIVA_RESERVED_101) /* Vector 101: Reserved */
+UNUSED(TIVA_RESERVED_102) /* Vector 102: Reserved */
+UNUSED(TIVA_RESERVED_103) /* Vector 103: Reserved */
+UNUSED(TIVA_RESERVED_104) /* Vector 104: Reserved */
+UNUSED(TIVA_RESERVED_105) /* Vector 105: Reserved */
+UNUSED(TIVA_RESERVED_106) /* Vector 106: Reserved */
+UNUSED(TIVA_RESERVED_107) /* Vector 107: Reserved */
+VECTOR(tiva_timer5a, TIVA_IRQ_TIMER5A) /* Vector 108: 16/32-Bit Timer 5 A */
+VECTOR(tiva_timer5b, TIVA_IRQ_TIMER5B) /* Vector 109: 16/32-Bit Timer 5 B */
+
+VECTOR(tiva_wtimer0a, TIVA_IRQ_WTIMER0A) /* Vector 110: 32/64-Bit Timer 0 A */
+VECTOR(tiva_wtimer0b, TIVA_IRQ_WTIMER0B) /* Vector 111: 32/64-Bit Timer 0 B */
+VECTOR(tiva_wtimer1a, TIVA_IRQ_WTIMER1A) /* Vector 112: 32/64-Bit Timer 1 A */
+VECTOR(tiva_wtimer1b, TIVA_IRQ_WTIMER1B) /* Vector 113: 32/64-Bit Timer 1 B */
+VECTOR(tiva_wtimer2a, TIVA_IRQ_WTIMER2A) /* Vector 114: 32/64-Bit Timer 2 A */
+VECTOR(tiva_wtimer2b, TIVA_IRQ_WTIMER2B) /* Vector 115: 32/64-Bit Timer 2 B */
+VECTOR(tiva_wtimer3a, TIVA_IRQ_WTIMER3A) /* Vector 116: 32/64-Bit Timer 3 A */
+VECTOR(tiva_wtimer3b, TIVA_IRQ_WTIMER3B) /* Vector 117: 32/64-Bit Timer 3 B */
+VECTOR(tiva_wtimer4a, TIVA_IRQ_WTIMER4A) /* Vector 118: 32/64-Bit Timer 4 A */
+VECTOR(tiva_WTIMER4B, TIVA_IRQ_WTIMER4B) /* Vector 119: 32/64-Bit Timer 4 B */
+
+VECTOR(tiva_wtimer5a, TIVA_IRQ_WTIMER5A) /* Vector 120: 32/64-Bit Timer 5 A */
+VECTOR(tiva_wtimer5b, TIVA_IRQ_WTIMER5B) /* Vector 121: 32/64-Bit Timer 5 B */
+VECTOR(tiva_system, TIVA_IRQ_SYSTEM) /* Vector 122: System Exception (imprecise) */
+UNUSED(TIVA_RESERVED_123) /* Vector 123: Reserved */
+UNUSED(TIVA_RESERVED_124) /* Vector 124: Reserved */
+UNUSED(TIVA_RESERVED_125) /* Vector 125: Reserved */
+UNUSED(TIVA_RESERVED_126) /* Vector 126: Reserved */
+UNUSED(TIVA_RESERVED_127) /* Vector 127: Reserved */
+UNUSED(TIVA_RESERVED_128) /* Vector 128: Reserved */
+UNUSED(TIVA_RESERVED_129) /* Vector 129: Reserved */
+
+UNUSED(TIVA_RESERVED_130) /* Vector 130: Reserved */
+UNUSED(TIVA_RESERVED_131) /* Vector 131: Reserved */
+UNUSED(TIVA_RESERVED_132) /* Vector 132: Reserved */
+UNUSED(TIVA_RESERVED_133) /* Vector 133: Reserved */
+UNUSED(TIVA_RESERVED_134) /* Vector 134: Reserved */
+UNUSED(TIVA_RESERVED_135) /* Vector 135: Reserved */
+UNUSED(TIVA_RESERVED_136) /* Vector 136: Reserved */
+UNUSED(TIVA_RESERVED_137) /* Vector 137: Reserved */
+UNUSED(TIVA_RESERVED_138) /* Vector 138: Reserved */
+UNUSED(TIVA_RESERVED_139) /* Vector 139: Reserved */
+
+UNUSED(TIVA_RESERVED_140) /* Vector 140: Reserved */
+UNUSED(TIVA_RESERVED_141) /* Vector 141: Reserved */
+UNUSED(TIVA_RESERVED_142) /* Vector 142: Reserved */
+UNUSED(TIVA_RESERVED_143) /* Vector 143: Reserved */
+UNUSED(TIVA_RESERVED_144) /* Vector 144: Reserved */
+UNUSED(TIVA_RESERVED_145) /* Vector 145: Reserved */
+UNUSED(TIVA_RESERVED_146) /* Vector 146: Reserved */
+UNUSED(TIVA_RESERVED_147) /* Vector 147: Reserved */
+UNUSED(TIVA_RESERVED_148) /* Vector 148: Reserved */
+UNUSED(TIVA_RESERVED_149) /* Vector 149: Reserved */
+
+VECTOR(tiva_pwm1_gen0, TIVA_IRQ_PWM1_GEN0) /* Vector 150: PWM1 Generator 0 */
+VECTOR(tiva_pwm1_gen1, TIVA_IRQ_PWM1_GEN1) /* Vector 151: PWM1 Generator 1 */
+VECTOR(tiva_pwm1_gen2, TIVA_IRQ_PWM1_GEN2) /* Vector 152: PWM1 Generator 2 */
+VECTOR(tiva_pwm1_gen3, TIVA_IRQ_PWM1_GEN3) /* Vector 153: PWM1 Generator 3 */
+VECTOR(tiva_pwm1_fault, TIVA_IRQ_PWM1_FAULT) /* Vector 154: PWM1 Fault */
+
+# endif /* CONFIG_ARMV7M_CMNVECTOR */
+
#else
# error "Vectors not known for this Tiva chip"
#endif
diff --git a/nuttx/configs/Kconfig b/nuttx/configs/Kconfig
index 8b7f8c78a..121ab0f18 100644
--- a/nuttx/configs/Kconfig
+++ b/nuttx/configs/Kconfig
@@ -748,8 +748,8 @@ config ARCH_BOARD_TEENSY
on an Atmel AT90USB1286 MCU.
config ARCH_BOARD_TM4C123G_LAUNCHPAD
- bool "Tiva TM4C124G LaunchPad"
- depends on ARCH_CHIP_TM4C123GH6ZRB
+ bool "Tiva TM4C123G LaunchPad"
+ depends on ARCH_CHIP_TM4C123GH6PMI
select ARCH_HAVE_LEDS
select ARCH_HAVE_BUTTONS
select ARCH_HAVE_IRQBUTTONS
diff --git a/nuttx/configs/tm4c123g-launchpad/README.txt b/nuttx/configs/tm4c123g-launchpad/README.txt
index daef9f545..08dbb37cd 100644
--- a/nuttx/configs/tm4c123g-launchpad/README.txt
+++ b/nuttx/configs/tm4c123g-launchpad/README.txt
@@ -33,7 +33,7 @@ PIN SIGNAL(S) LanchPad Function
20 PA3/SSIOFSS GPIO, J2 pin 9
21 PA4/SSIORX GPIO, J2 pin 8
22 PA5/SSIOTX GPIO, J1 pin 8
- 23 PA6/I2CLSCL GPIO, J1 pin 9
+ 23 PA6/I2CLSCL GPIO, J1 pin 9
24 PA7/I2CLSDA GPIO, J1 pin 10
45 PB0/T2CCP0/U1Rx GPIO, J1 pin 3
@@ -102,7 +102,7 @@ Using OpenOCD and GDB with an FT2232 JTAG emulator
git fetch http://openocd.zylin.com/openocd refs/changes/22/922/14 && git checkout FETCH_HEAD
./bootstrap
./configure --enable-maintainer-mode --enable-ti-icdi
- make
+ make
sudo make install
For additional help, see http://processors.wiki.ti.com/index.php/Tiva_Launchpad_with_OpenOCD_and_Linux
@@ -111,7 +111,7 @@ Using OpenOCD and GDB with an FT2232 JTAG emulator
I have been using the on-board In-Circuit Debug Interface (ICDI) interface.
OpenOCD requires a configuration file. I keep the one I used last here:
-
+
configs/tm4c123g-launchpad/tools/tm4c123g-launchpad.cfg
However, the "correct" configuration script to use with OpenOCD may
@@ -127,7 +127,7 @@ Using OpenOCD and GDB with an FT2232 JTAG emulator
There is also a script on the tools/ directory that I use to start
the OpenOCD daemon on my system called oocd.sh. That script will
probably require some modifications to work in another environment:
-
+
- Possibly the value of OPENOCD_PATH and TARGET_PATH
- It assumes that the correct script to use is the one at
configs/tm4c123g-launchpad/tools/tm4c123g-launchpad.cfg
@@ -142,7 +142,7 @@ Using OpenOCD and GDB with an FT2232 JTAG emulator
The relative path to the oocd.sh script is configs/tm4c123g-launchpad/tools,
but that should have been added to your PATH variable when you sourced
the setenv.sh script.
-
+
Note that OpenOCD needs to be run with administrator privileges in
some environments (sudo).
@@ -170,11 +170,11 @@ Using OpenOCD and GDB with an FT2232 JTAG emulator
.config file).
2. The MCU must be halted prior to loading code using 'mon reset'
as described below.
-
+
OpenOCD will support several special 'monitor' commands. These
GDB commands will send comments to the OpenOCD monitor. Here
are a couple that you will need to use:
-
+
(gdb) monitor reset
(gdb) monitor halt
@@ -261,7 +261,7 @@ IDEs
NuttX is built using command-line make. It can be used with an IDE, but some
effort will be required to create the project.
-
+
Makefile Build
--------------
Under Eclipse, it is pretty easy to set up an "empty makefile project" and
@@ -356,7 +356,7 @@ NXFLAT Toolchain
tools -- just the NXFLAT tools. The buildroot with the NXFLAT tools can
be downloaded from the NuttX SourceForge download site
(https://sourceforge.net/projects/nuttx/files/).
-
+
This GNU toolchain builds and executes in the Linux or Cygwin environment.
1. You must have already configured Nuttx in <some-dir>/nuttx.
@@ -473,7 +473,7 @@ USB Device Controller Functions
Debugging with JTAG/SWD
- The FT2232 USB device performs JTAG/SWD serial operations under the control
+ The FT2232 USB device performs JTAG/SWD serial operations under the control
of the debugger or the Luminary Flash Programmer. It also operate as an
In-Circuit Debugger Interface (ICDI), allowing debugging of any external
target board. Debugging modes:
@@ -520,7 +520,7 @@ TM4C123G LaunchPad Configuration Options
CONFIG_ARCH_CHIP_name - For use in C code to identify the exact
chip:
- CONFIG_ARCH_CHIP_TM4C123GH6ZRB
+ CONFIG_ARCH_CHIP_TM4C123GH6PMI
CONFIG_ARCH_BOARD - Identifies the configs subdirectory and
hence, the board that supports the particular chip or SoC.
@@ -588,7 +588,7 @@ TM4C123G LaunchPad Configuration Options
CONFIG_TIVA_DISABLE_GPION_IRQS=n
CONFIG_TIVA_DISABLE_GPIOP_IRQS=n
CONFIG_TIVA_DISABLE_GPIOQ_IRQS=n
-
+
TM4C123G specific device driver settings
CONFIG_UARTn_SERIAL_CONSOLE - selects the UARTn for the
@@ -646,7 +646,7 @@ Where <subdir> is one of the following:
builtin applications are selected.
NOTES:
-
+
1. This configuration uses the mconf-based configuration tool. To
change this configuration using that tool, you should:
diff --git a/nuttx/configs/tm4c123g-launchpad/nsh/defconfig b/nuttx/configs/tm4c123g-launchpad/nsh/defconfig
index 0ea9c59a0..74471c757 100644
--- a/nuttx/configs/tm4c123g-launchpad/nsh/defconfig
+++ b/nuttx/configs/tm4c123g-launchpad/nsh/defconfig
@@ -117,7 +117,7 @@ CONFIG_ARMV7M_OABI_TOOLCHAIN=y
#
# Tiva/Stellaris Configuration Options
#
-CONFIG_ARCH_CHIP_TM4C123GH6ZRB=y
+CONFIG_ARCH_CHIP_TM4C123GH6PMI=y
CONFIG_ARCH_CHIP_TM4C=y
#
diff --git a/nuttx/configs/tm4c123g-launchpad/tools/lm4f120-launchpad.cfg b/nuttx/configs/tm4c123g-launchpad/tools/lm4f120-launchpad.cfg
deleted file mode 100644
index c91b3b1d5..000000000
--- a/nuttx/configs/tm4c123g-launchpad/tools/lm4f120-launchpad.cfg
+++ /dev/null
@@ -1,71 +0,0 @@
-#
-# TI Tiva Launchpad ek-tm4c123gxl Evaluation Kits
-#
-# http://www.ti.com/tool/ek-tm4c123gxl
-#
-
-#
-# NOTE: using the bundled ICDI interface is optional!
-# This interface is not ftdi based as previous boards were
-#
-
-# Interface configuration
-
-#
-# TI Tiva In-Circuit Debug Interface (ICDI) Board
-#
-# This is the propriety ICDI interface used on newer boards such as
-# LM4F232 Evaluation Kit - http://www.ti.com/tool/ek-lm4f232
-# Tiva Launchpad - http://www.ti.com/stellaris-launchpad
-# http://www.ti.com/tool/ek-lm4f232
-#
-
-interface hla
-hla_layout ti-icdi
-hla_vid_pid 0x1cbe 0x00fd
-
-# Board configuration
-
-# unused but set to disable warnings
-adapter_khz 1000
-
-set WORKAREASIZE 0x8000
-set CHIPNAME tm4c123gh5qr
-
-# Target configuration
-
-#
-# lm3s icdi pseudo target
-#
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME lm3s
-}
-
-# Work-area is a space in RAM used for flash programming
-# By default use 16kB
-if { [info exists WORKAREASIZE] } {
- set _WORKAREASIZE $WORKAREASIZE
-} else {
- set _WORKAREASIZE 0x4000
-}
-
-#
-# possible value are hla_jtag
-# currently swd is not supported
-#
-transport select hla_jtag
-
-# do not check id as icdi currently does not support it
-hla newtap $_CHIPNAME cpu -expected-id 0
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME hla_target -chain-position $_TARGETNAME
-
-$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
-
-# flash configuration ... autodetects sizes, autoprobed
-flash bank $_CHIPNAME.flash stellaris 0 0 0 0 $_TARGETNAME
-
diff --git a/nuttx/configs/tm4c123g-launchpad/tools/oocd.sh b/nuttx/configs/tm4c123g-launchpad/tools/oocd.sh
index bbe08e207..aa97bafb3 100644
--- a/nuttx/configs/tm4c123g-launchpad/tools/oocd.sh
+++ b/nuttx/configs/tm4c123g-launchpad/tools/oocd.sh
@@ -15,12 +15,12 @@ fi
# the following to run directly from the build directory
# OPENOCD_PATH="/home/OpenOCD/openocd/src"
-# OPENOCD_PATH="/usr/bin"
-OPENOCD_PATH="/usr/local/bin"
+OPENOCD_PATH="/usr/bin"
+# OPENOCD_PATH="/usr/local/bin"
# TARGET_PATH="/home/OpenOCD/openocd/tcl"
-# TARGET_PATH="/usr/share/openocd/scripts"
-TARGET_PATH="/usr/local/share/openocd/scripts"
+TARGET_PATH="/usr/share/openocd/scripts"
+# TARGET_PATH="/usr/local/share/openocd/scripts"
# Assume a Unix development environment. Uncomment to use a Windows
# like environment
diff --git a/nuttx/configs/tm4c123g-launchpad/tools/tm4c123g-launchpad.cfg b/nuttx/configs/tm4c123g-launchpad/tools/tm4c123g-launchpad.cfg
new file mode 100644
index 000000000..62fe9812b
--- /dev/null
+++ b/nuttx/configs/tm4c123g-launchpad/tools/tm4c123g-launchpad.cfg
@@ -0,0 +1,12 @@
+#
+# TI Tiva C Series ek-tm4c123gxl Launchpad Evaluation Kit
+#
+# http://www.ti.com/tool/ek-tm4c123gxl
+#
+
+source [find interface/ti-icdi.cfg]
+
+set WORKAREASIZE 0x8000
+set CHIPNAME tm4c123gh6pm
+source [find target/stellaris_icdi.cfg]
+
generated by cgit v1.2.3 (git 2.39.1) at 2024-08-01 13:41:00 +0000