diff options
Diffstat (limited to 'nuttx/arch/arm/include/stm32/chip.h')
| -rw-r--r-- | nuttx/arch/arm/include/stm32/chip.h | 73 |
1 files changed, 55 insertions, 18 deletions
diff --git a/nuttx/arch/arm/include/stm32/chip.h b/nuttx/arch/arm/include/stm32/chip.h index 5bf286d6b..13d5683a1 100644 --- a/nuttx/arch/arm/include/stm32/chip.h +++ b/nuttx/arch/arm/include/stm32/chip.h @@ -478,12 +478,9 @@ # define STM32_NRNG 0 /* No random number generator (RNG) */ # define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ -/* STM32 F103 Medium Density Family *************************************************/ -/* STM32F103RB is in the Medium-density performance line and is provided in 64 pin - * packages with 128K Flash, USB, CAN, 7 timers, 2 ADCs, 9 com. interfaces - */ +/* STM32 F103 Medium Density Performance Line ***************************************/ -#elif defined(CONFIG_ARCH_CHIP_STM32F103RBT6) +#elif defined(CONFIG_ARCH_CHIP_STM32F103T8) || defined(CONFIG_ARCH_CHIP_STM32F103TB) # undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */ # undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite vamily */ # define CONFIG_STM32_STM32F10XX 1 /* STM32F10xxx family */ @@ -491,24 +488,60 @@ # define CONFIG_STM32_MEDIUMDENSITY 1 /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */ # undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */ # undef CONFIG_STM32_VALUELINE /* STM32F100x */ +# define CONFIG_STM32_PERFORMANCELINE 1 /* STM32F103x8 and STM32F103xB */ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ -# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ # undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */ -# define STM32_NFSMC 0 /* FSMC */ +# define STM32_NFSMC 0 /* No FSMC */ # define STM32_NATIM 1 /* One advanced timer TIM1 */ # define STM32_NGTIM 3 /* General timers TIM2,3,4 */ -# define STM32_NBTIM 0 /* Two basic timers TIM6 and TIM7 */ -# define STM32_NDMA 1 /* DMA1 */ +# define STM32_NBTIM 0 /* No basic timers */ +# define STM32_NDMA 1 /* DMA1, 7 channels */ +# define STM32_NSPI 1 /* SPI1 */ +# define STM32_NI2S 0 /* No I2S */ +# define STM32_NUSART 2 /* USART1-2 */ +# define STM32_NI2C 1 /* I2C1 */ +# define STM32_NCAN 1 /* bxCAN1 */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ +# define STM32_NGPIO 26 /* GPIOA-E */ +# define STM32_NADC 2 /* ADC1-2 */ +# define STM32_NDAC 0 /* No DAC */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NTHERNET 0 /* No ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F103C8) || defined(CONFIG_ARCH_CHIP_STM32F103CB) +# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */ +# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite vamily */ +# define CONFIG_STM32_STM32F10XX 1 /* STM32F10xxx family */ +# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */ +# define CONFIG_STM32_MEDIUMDENSITY 1 /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */ +# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */ +# undef CONFIG_STM32_VALUELINE /* STM32F100x */ +# define CONFIG_STM32_PERFORMANCELINE 1 /* STM32F103x8 and STM32F103xB */ +# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ +# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ +# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */ +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 1 /* One advanced timer TIM1 */ +# define STM32_NGTIM 3 /* General timers TIM2,3,4 */ +# define STM32_NBTIM 0 /* No basic timers */ +# define STM32_NDMA 1 /* DMA1, 7 channels */ # define STM32_NSPI 2 /* SPI1-2 */ -# define STM32_NI2S 0 /* No I2S (?) */ +# define STM32_NI2S 0 /* No I2S */ # define STM32_NUSART 3 /* USART1-3 */ # define STM32_NI2C 2 /* I2C1-2 */ # define STM32_NCAN 1 /* bxCAN1 */ # define STM32_NSDIO 0 /* No SDIO */ # define STM32_NLCD 0 /* No LCD */ # define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ -# define STM32_NGPIO 51 /* GPIOA-E */ +# define STM32_NGPIO 37 /* GPIOA-C */ # define STM32_NADC 2 /* ADC1-2 */ # define STM32_NDAC 0 /* No DAC */ # define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ @@ -517,32 +550,36 @@ # define STM32_NRNG 0 /* No random number generator (RNG) */ # define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ -/* STM32F103C8, STM32F103CB (Medium-density performance line and is provided in 48 pin package) */ -#elif defined(CONFIG_ARCH_CHIP_STM32F103C8) +#elif defined(CONFIG_ARCH_CHIP_STM32F103R8) || defined(CONFIG_ARCH_CHIP_STM32F103RB) +# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */ +# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite vamily */ # define CONFIG_STM32_STM32F10XX 1 /* STM32F10xxx family */ # undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */ # define CONFIG_STM32_MEDIUMDENSITY 1 /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */ # undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */ # undef CONFIG_STM32_VALUELINE /* STM32F100x */ +# define CONFIG_STM32_PERFORMANCELINE 1 /* STM32F103x8 and STM32F103xB */ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ -# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ # undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */ -# define STM32_NFSMC 0 /* FSMC */ +# define STM32_NFSMC 0 /* No FSMC */ # define STM32_NATIM 1 /* One advanced timer TIM1 */ # define STM32_NGTIM 3 /* General timers TIM2,3,4 */ -# define STM32_NBTIM 0 /* No basic timer */ -# define STM32_NDMA 1 /* DMA1 */ +# define STM32_NBTIM 0 /* No basic timers */ +# define STM32_NDMA 1 /* DMA1, 7 channels */ # define STM32_NSPI 2 /* SPI1-2 */ # define STM32_NI2S 0 /* No I2S */ # define STM32_NUSART 3 /* USART1-3 */ # define STM32_NI2C 2 /* I2C1-2 */ # define STM32_NCAN 1 /* bxCAN1 */ # define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 0 /* No LCD */ # define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ -# define STM32_NGPIO 37 /* GPIOA-C */ +# define STM32_NGPIO 51 /* GPIOA-E */ # define STM32_NADC 2 /* ADC1-2 */ # define STM32_NDAC 0 /* No DAC */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ # define STM32_NCRC 1 /* CRC */ # define STM32_NTHERNET 0 /* No ethernet */ # define STM32_NRNG 0 /* No random number generator (RNG) */ |