diff options
Diffstat (limited to 'nuttx/arch/arm/src/lpc17xx/lpc17_lcd.c')
-rw-r--r-- | nuttx/arch/arm/src/lpc17xx/lpc17_lcd.c | 133 |
1 files changed, 63 insertions, 70 deletions
diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_lcd.c b/nuttx/arch/arm/src/lpc17xx/lpc17_lcd.c index cf326ea5f..4050356e4 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_lcd.c +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_lcd.c @@ -466,16 +466,12 @@ int up_fbinitialize(void) gvdbg("Entry\n"); - /* Disable LCD controller */ + /* Give LCD bus priority */ - regval = getreg32(LPC17_LCD_CTRL); - regval &= ~LCD_CTRL_LCDPWR; - putreg32(regval, LPC17_LCD_CTRL); - - for (i = LPC17_LCD_PWRDIS_DELAY; i; i--); - - regval &= ~LCD_CTRL_LCDEN; - putreg32(regval, LPC17_LCD_CTRL); + regval = ((SYSCON_MATRIXARB_PRI_ICODE(SYSCON_MATRIXARB_PRI_LOW)) | + (SYSCON_MATRIXARB_PRI_DCODE(SYSCON_MATRIXARB_PRI_HIGHEST)) | + (SYSCON_MATRIXARB_PRI_LCD(SYSCON_MATRIXARB_PRI_HIGHEST))); + putreg32(regval, LPC17_SYSCON_MATRIXARB); /* Configure pins */ /* Video data */ @@ -519,22 +515,31 @@ int up_fbinitialize(void) lpc17_configgpio(GPIO_LCD_ENABM); lpc17_configgpio(GPIO_LCD_PWR); - gvdbg("Configuring the LCD controller\n"); - /* Turn on LCD clock */ modifyreg32(LPC17_SYSCON_PCONP, 0, SYSCON_PCONP_PCLCD); + gvdbg("Configuring the LCD controller\n"); + /* Disable the cursor */ regval = getreg32(LPC17_LCD_CRSR_CRTL); regval &= ~LCD_CRSR_CTRL_CRSON; putreg32(regval, LPC17_LCD_CRSR_CRTL); + /* Clear any pending interrupts */ + + putreg32(LCD_INTCLR_ALL, LPC17_LCD_INTCLR); + /* Disable GLCD controller */ putreg32(0, LPC17_LCD_CTRL); + /* Initialize pixel clock (assuming clock source is the peripheral clock) */ + + putreg32(((uint32_t)BOARD_PCLK_FREQUENCY / (uint32_t)LPC17_LCD_PIXEL_CLOCK)+1, + LPC17_SYSCON_LCDCFG); + /* Set the bits per pixel */ regval = getreg32(LPC17_LCD_CTRL); @@ -558,24 +563,19 @@ int up_fbinitialize(void) regval |= LCD_CTRL_LCDBPP_444; /* 12 bpp, 4:4:4 mode */ #endif - putreg32(regval, LPC17_LCD_CTRL); - /* TFT panel */ #if CONFIG_LPC17_LCD_TFTPANEL regval |= LCD_CTRL_LCDTFT; - putreg32(regval, LPC17_LCD_CTRL); #endif - /* Single panel */ + /* Swap red and blue */ - regval &= ~LCD_CTRL_LCDDUAL; - putreg32(regval, LPC17_LCD_CTRL); + regval |= LCD_CTRL_BGR; - /* Normal RGB output */ + /* Single panel */ - regval &= ~LCD_CTRL_BGR; - putreg32(regval, LPC17_LCD_CTRL); + regval &= ~LCD_CTRL_LCDDUAL; /* Select monochrome or color LCD */ @@ -583,96 +583,83 @@ int up_fbinitialize(void) /* Select monochrome LCD */ regval &= ~LCD_CTRL_BGR; - putreg32(regval, LPC17_LCD_CTRL); /* Select 4- or 8-bit monochrome interface */ -#if LPC17_BPP > 4 +# if LPC17_BPP > 4 regval |= LCD_CTRL_LCDMONO8; -#else +# else regval &= ~LCD_CTRL_LCDMONO8; -#endif - putreg32(regval, LPC17_LCD_CTRL); +# endif #else /* Select color LCD */ regval &= ~(LCD_CTRL_LCDBW | LCD_CTRL_LCDMONO8); - putreg32(regval, LPC17_LCD_CTRL); -#endif + +#endif /* CONFIG_LPC17_LCD_MONOCHROME */ /* Little endian byte order */ regval &= ~LCD_CTRL_BEBO; - putreg32(regval, LPC17_LCD_CTRL); /* Little endian pixel order */ regval &= ~LCD_CTRL_BEPO; putreg32(regval, LPC17_LCD_CTRL); - /* Disable power */ + /* Initialize horizontal timing */ - regval &= ~LCD_CTRL_LCDPWR; - putreg32(regval, LPC17_LCD_CTRL); + putreg32(0, LPC17_LCD_TIMH); - /* Initialize pixel clock (assuming clock source is the peripheral clock) */ + regval = (((CONFIG_LPC17_LCD_HWIDTH/16) - 1) << LCD_TIMH_PPL_SHIFT | + (CONFIG_LPC17_LCD_HPULSE - 1) << LCD_TIMH_HSW_SHIFT | + (CONFIG_LPC17_LCD_HFRONTPORCH - 1) << LCD_TIMH_HFP_SHIFT | + (CONFIG_LPC17_LCD_HBACKPORCH - 1) << LCD_TIMH_HBP_SHIFT); + putreg32(regval, LPC17_LCD_TIMH); - putreg32(BOARD_PCLK_FREQUENCY / LPC17_LCD_PIXEL_CLOCK, LPC17_SYSCON_LCDCFG); + /* Initialize vertical timing */ - /* Bypass internal pixel clock divider */ + putreg32(0, LPC17_LCD_TIMV); - regval = getreg32(LPC17_LCD_POL); - regval |= LCD_POL_BCD; - putreg32(regval, LPC17_LCD_POL); + regval = ((CONFIG_LPC17_LCD_VHEIGHT - 1) << LCD_TIMV_LPP_SHIFT | + (CONFIG_LPC17_LCD_VPULSE - 1) << LCD_TIMV_VSW_SHIFT | + (CONFIG_LPC17_LCD_VFRONTPORCH) << LCD_TIMV_VFP_SHIFT | + (CONFIG_LPC17_LCD_VBACKPORCH) << LCD_TIMV_VBP_SHIFT); + putreg32(regval, LPC17_LCD_TIMV); - /* Select the PCLK for the LCD block clock source */ + /* Initialize clock and signal polarity */ - regval &= ~LCD_POL_CLKSEL; - putreg32(regval, LPC17_LCD_POL); + regval = getreg32(LPC17_LCD_POL); /* LCDFP pin is active LOW and inactive HIGH */ regval |= LCD_POL_IVS; - putreg32(regval, LPC17_LCD_POL); /* LCDLP pin is active LOW and inactive HIGH */ regval |= LCD_POL_IHS; - putreg32(regval, LPC17_LCD_POL); /* Data is driven out into the LCD on the falling edge */ regval &= ~LCD_POL_IPC; - putreg32(regval, LPC17_LCD_POL); - - /* Active high */ - regval &= ~LCD_POL_IOE; - putreg32(regval, LPC17_LCD_POL); + /* Set number of clocks per line */ - regval &= ~LCD_POL_CPL_MASK; - regval |= (CONFIG_LPC17_LCD_HWIDTH-1) << LCD_POL_CPL_SHIFT; - putreg32(regval, LPC17_LCD_POL); + regval |= ((CONFIG_LPC17_LCD_HWIDTH-1) << LCD_POL_CPL_SHIFT); - /* Initialize horizontal timing */ + /* Bypass internal pixel clock divider */ - putreg32(0, LPC17_LCD_TIMH); + regval |= LCD_POL_BCD; - regval = (((CONFIG_LPC17_LCD_HWIDTH/16) - 1) << LCD_TIMH_PPL_SHIFT | - (CONFIG_LPC17_LCD_HPULSE - 1) << LCD_TIMH_HSW_SHIFT | - (CONFIG_LPC17_LCD_HFRONTPORCH - 1) << LCD_TIMH_HFP_SHIFT | - (CONFIG_LPC17_LCD_HBACKPORCH - 1) << LCD_TIMH_HBP_SHIFT); - putreg32(regval, LPC17_LCD_TIMH); + /* LCD_ENAB_M is active high */ - /* Initialize vertical timing */ + regval &= ~LCD_POL_IOE; - putreg32(0, LPC17_LCD_TIMV); + /* Select CCLK for the LCD block clock source */ - regval = ((CONFIG_LPC17_LCD_VHEIGHT - 1) << LCD_TIMV_LPP_SHIFT | - (CONFIG_LPC17_LCD_VPULSE - 1) << LCD_TIMV_VSW_SHIFT | - (CONFIG_LPC17_LCD_VFRONTPORCH) << LCD_TIMV_VFP_SHIFT | - (CONFIG_LPC17_LCD_VBACKPORCH) << LCD_TIMV_VBP_SHIFT); + regval &= ~LCD_POL_CLKSEL; + putreg32(regval, LPC17_LCD_POL); /* Frame base address doubleword aligned */ @@ -682,26 +669,32 @@ int up_fbinitialize(void) /* Clear the display */ lpc17_lcdclear(CONFIG_LPC17_LCD_BACKCOLOR); - for (i = LPC17_LCD_PWREN_DELAY; i; i--); - /* Enable LCD */ +#ifdef CONFIG_LPC17_LCD_BACKLIGHT + /* Turn on the back light */ + + lpc17_backlight(true); +#endif + putreg32(0, LPC17_LCD_INTMSK); gvdbg("Enabling the display\n"); + for (i = LPC17_LCD_PWREN_DELAY; i; i--); + + /* Enable LCD */ + regval = getreg32(LPC17_LCD_CTRL); regval |= LCD_CTRL_LCDEN; putreg32(regval, LPC17_LCD_CTRL); + /* Enable LCD power */ + for (i = LPC17_LCD_PWREN_DELAY; i; i--); + regval = getreg32(LPC17_LCD_CTRL); regval |= LCD_CTRL_LCDPWR; putreg32(regval, LPC17_LCD_CTRL); -#ifdef CONFIG_LPC17_LCD_BACKLIGHT - /* Turn on the back light */ - - lpc17_backlight(true); -#endif return OK; } |