diff options
Diffstat (limited to 'nuttx/arch/arm')
345 files changed, 15407 insertions, 15406 deletions
diff --git a/nuttx/arch/arm/include/arch.h b/nuttx/arch/arm/include/arch.h index dd750ad77..d0b2602eb 100644 --- a/nuttx/arch/arm/include/arch.h +++ b/nuttx/arch/arm/include/arch.h @@ -2,7 +2,7 @@ * arch/arm/include/arch.h * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/include/arm/irq.h b/nuttx/arch/arm/include/arm/irq.h index 6b4f05539..a06abe888 100644 --- a/nuttx/arch/arm/include/arm/irq.h +++ b/nuttx/arch/arm/include/arm/irq.h @@ -2,7 +2,7 @@ * arch/arm/include/arm/irq.h * * Copyright (C) 2009-2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/include/arm/syscall.h b/nuttx/arch/arm/include/arm/syscall.h index e06de1a3c..3fc36c3db 100644 --- a/nuttx/arch/arm/include/arm/syscall.h +++ b/nuttx/arch/arm/include/arm/syscall.h @@ -2,7 +2,7 @@ * arch/arm/include/arm/syscall.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/include/armv7-m/syscall.h b/nuttx/arch/arm/include/armv7-m/syscall.h index 4c7b84302..4278c3a36 100644 --- a/nuttx/arch/arm/include/armv7-m/syscall.h +++ b/nuttx/arch/arm/include/armv7-m/syscall.h @@ -2,7 +2,7 @@ * arch/arm/include/armv7-m/syscall.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/include/c5471/irq.h b/nuttx/arch/arm/include/c5471/irq.h index 7f6dcd343..97aa0352a 100644 --- a/nuttx/arch/arm/include/c5471/irq.h +++ b/nuttx/arch/arm/include/c5471/irq.h @@ -2,7 +2,7 @@ * arch/arm/include/c5471/irq.h * * Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/include/dm320/irq.h b/nuttx/arch/arm/include/dm320/irq.h index c8c89af5e..320b56614 100644 --- a/nuttx/arch/arm/include/dm320/irq.h +++ b/nuttx/arch/arm/include/dm320/irq.h @@ -2,7 +2,7 @@ * arch/arm/include/dm320/irq.h * * Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/include/imx/irq.h b/nuttx/arch/arm/include/imx/irq.h index c2fd93d89..28158bb8d 100644 --- a/nuttx/arch/arm/include/imx/irq.h +++ b/nuttx/arch/arm/include/imx/irq.h @@ -2,7 +2,7 @@ * arch/arm/include/imx/irq.h * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/include/irq.h b/nuttx/arch/arm/include/irq.h index 71493a9fe..bde751b99 100644 --- a/nuttx/arch/arm/include/irq.h +++ b/nuttx/arch/arm/include/irq.h @@ -2,7 +2,7 @@ * arch/arm/include/irq.h * * Copyright (C) 2007-2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/include/kinetis/irq.h b/nuttx/arch/arm/include/kinetis/irq.h index af10ce6f4..8a020ea1b 100644 --- a/nuttx/arch/arm/include/kinetis/irq.h +++ b/nuttx/arch/arm/include/kinetis/irq.h @@ -2,7 +2,7 @@ * arch/arm/include/kinetis/irq.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/include/lm3s/irq.h b/nuttx/arch/arm/include/lm3s/irq.h index 3eca0e0e8..6ffc7dec0 100644 --- a/nuttx/arch/arm/include/lm3s/irq.h +++ b/nuttx/arch/arm/include/lm3s/irq.h @@ -2,7 +2,7 @@ * arch/arm/include/lm3s/irq.h * * Copyright (C) 2009-2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/include/lpc17xx/irq.h b/nuttx/arch/arm/include/lpc17xx/irq.h index aebdc3159..a7eebb32c 100755 --- a/nuttx/arch/arm/include/lpc17xx/irq.h +++ b/nuttx/arch/arm/include/lpc17xx/irq.h @@ -2,7 +2,7 @@ * arch/lpc17xxx/irq.h * * Copyright (C) 2010-2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/include/lpc214x/irq.h b/nuttx/arch/arm/include/lpc214x/irq.h index 221644a07..5652fc7a9 100644 --- a/nuttx/arch/arm/include/lpc214x/irq.h +++ b/nuttx/arch/arm/include/lpc214x/irq.h @@ -2,7 +2,7 @@ * arch/lpc214x/irq.h * * Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/include/lpc2378/irq.h b/nuttx/arch/arm/include/lpc2378/irq.h index 3ea09d7af..807c99119 100755 --- a/nuttx/arch/arm/include/lpc2378/irq.h +++ b/nuttx/arch/arm/include/lpc2378/irq.h @@ -7,7 +7,7 @@ * This file is part of the NuttX RTOS and based on the lpc2148 port: * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/include/lpc31xx/irq.h b/nuttx/arch/arm/include/lpc31xx/irq.h index 5a701239b..d3654a507 100755 --- a/nuttx/arch/arm/include/lpc31xx/irq.h +++ b/nuttx/arch/arm/include/lpc31xx/irq.h @@ -2,7 +2,7 @@ * arch/arm/include/lpc31xx/irq.h * * Copyright (C) 2009-2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/include/sam3u/irq.h b/nuttx/arch/arm/include/sam3u/irq.h index 2c6940b68..481db74a2 100755 --- a/nuttx/arch/arm/include/sam3u/irq.h +++ b/nuttx/arch/arm/include/sam3u/irq.h @@ -2,7 +2,7 @@ * arch/arm/include/sam3u/irq.h * * Copyright (C) 2009-2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/include/serial.h b/nuttx/arch/arm/include/serial.h index 80eefb2b4..844f78a2b 100644 --- a/nuttx/arch/arm/include/serial.h +++ b/nuttx/arch/arm/include/serial.h @@ -2,7 +2,7 @@ * arch/arm/include/serial.h * * Copyright (C) 2007-2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/include/str71x/irq.h b/nuttx/arch/arm/include/str71x/irq.h index bac58bb2a..5ce85416a 100644 --- a/nuttx/arch/arm/include/str71x/irq.h +++ b/nuttx/arch/arm/include/str71x/irq.h @@ -2,7 +2,7 @@ * arch/arm/include/str71x/irq.h * * Copyright (C) 2008-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/include/syscall.h b/nuttx/arch/arm/include/syscall.h index 4c9eee63e..8b438200a 100644 --- a/nuttx/arch/arm/include/syscall.h +++ b/nuttx/arch/arm/include/syscall.h @@ -2,7 +2,7 @@ * arch/arm/include/syscall.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/include/types.h b/nuttx/arch/arm/include/types.h index c3471ca59..c06b28950 100644 --- a/nuttx/arch/arm/include/types.h +++ b/nuttx/arch/arm/include/types.h @@ -2,7 +2,7 @@ * arch/arm/include/types.h * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/include/watchdog.h b/nuttx/arch/arm/include/watchdog.h index f70b8d2e9..43fbac2be 100644 --- a/nuttx/arch/arm/include/watchdog.h +++ b/nuttx/arch/arm/include/watchdog.h @@ -2,7 +2,7 @@ * arch/arm/include/watchdog.h * * Copyright (C) 2007, 2008, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/arm/arm.h b/nuttx/arch/arm/src/arm/arm.h index 433283814..2ad31fc46 100644 --- a/nuttx/arch/arm/src/arm/arm.h +++ b/nuttx/arch/arm/src/arm/arm.h @@ -2,7 +2,7 @@ * arch/arm/src/arm/arm.h * * Copyright (C) 2007-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/arm/pg_macros.h b/nuttx/arch/arm/src/arm/pg_macros.h index fc50f6146..dc65a5d06 100644 --- a/nuttx/arch/arm/src/arm/pg_macros.h +++ b/nuttx/arch/arm/src/arm/pg_macros.h @@ -2,7 +2,7 @@ * arch/arm/src/arm/pg_macros.h * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/arm/up_allocpage.c b/nuttx/arch/arm/src/arm/up_allocpage.c index c2a31d09c..0284e48bc 100755 --- a/nuttx/arch/arm/src/arm/up_allocpage.c +++ b/nuttx/arch/arm/src/arm/up_allocpage.c @@ -3,7 +3,7 @@ * Allocate a new page and map it to the fault address of a task. * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/arm/up_assert.c b/nuttx/arch/arm/src/arm/up_assert.c index f52dc1b94..023e6e22d 100644 --- a/nuttx/arch/arm/src/arm/up_assert.c +++ b/nuttx/arch/arm/src/arm/up_assert.c @@ -2,7 +2,7 @@ * arch/arm/src/arm/up_assert.c * * Copyright (C) 2007-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/arm/up_blocktask.c b/nuttx/arch/arm/src/arm/up_blocktask.c index 36c8740d6..f72a02465 100755 --- a/nuttx/arch/arm/src/arm/up_blocktask.c +++ b/nuttx/arch/arm/src/arm/up_blocktask.c @@ -2,7 +2,7 @@ * arch/arm/src/arm/up_blocktask.c * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/arm/up_cache.S b/nuttx/arch/arm/src/arm/up_cache.S index 05926fbb4..1d459e693 100644 --- a/nuttx/arch/arm/src/arm/up_cache.S +++ b/nuttx/arch/arm/src/arm/up_cache.S @@ -2,7 +2,7 @@ * arch/arm/src/arm/up_cache.S * * Copyright (C) 2007, 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/arm/up_checkmapping.c b/nuttx/arch/arm/src/arm/up_checkmapping.c index 370c94c9d..ca8c3a032 100755 --- a/nuttx/arch/arm/src/arm/up_checkmapping.c +++ b/nuttx/arch/arm/src/arm/up_checkmapping.c @@ -4,7 +4,7 @@ * address space. * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/arm/up_copystate.c b/nuttx/arch/arm/src/arm/up_copystate.c index 44f027b32..c76ee8e70 100644 --- a/nuttx/arch/arm/src/arm/up_copystate.c +++ b/nuttx/arch/arm/src/arm/up_copystate.c @@ -2,7 +2,7 @@ * arch/arm/src/arm/up_copystate.c * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/arm/up_dataabort.c b/nuttx/arch/arm/src/arm/up_dataabort.c index c36970c1b..f01941968 100644 --- a/nuttx/arch/arm/src/arm/up_dataabort.c +++ b/nuttx/arch/arm/src/arm/up_dataabort.c @@ -2,7 +2,7 @@ * arch/arm/src/arm/up_dataabort.c * * Copyright (C) 2007-2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/arm/up_doirq.c b/nuttx/arch/arm/src/arm/up_doirq.c index 1f1c77473..c82587fff 100644 --- a/nuttx/arch/arm/src/arm/up_doirq.c +++ b/nuttx/arch/arm/src/arm/up_doirq.c @@ -2,7 +2,7 @@ * arch/arm/src/arm/up_doirq.c * * Copyright (C) 2007-2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/arm/up_fullcontextrestore.S b/nuttx/arch/arm/src/arm/up_fullcontextrestore.S index d0745ef5b..44573a5f4 100644 --- a/nuttx/arch/arm/src/arm/up_fullcontextrestore.S +++ b/nuttx/arch/arm/src/arm/up_fullcontextrestore.S @@ -2,7 +2,7 @@ * arch/arm/src/arm/up_fullcontextrestore.S * * Copyright (C) 2007, 2009-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/arm/up_head.S b/nuttx/arch/arm/src/arm/up_head.S index c04dddf8a..91d67fd15 100644 --- a/nuttx/arch/arm/src/arm/up_head.S +++ b/nuttx/arch/arm/src/arm/up_head.S @@ -2,7 +2,7 @@ * arch/arm/src/arm/up_head.S * * Copyright (C) 2007, 2009-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/arm/up_initialstate.c b/nuttx/arch/arm/src/arm/up_initialstate.c index 4711c9f44..fb672a2ac 100644 --- a/nuttx/arch/arm/src/arm/up_initialstate.c +++ b/nuttx/arch/arm/src/arm/up_initialstate.c @@ -2,7 +2,7 @@ * arch/arm/src/arm/up_initialstate.c * * Copyright (C) 2007-2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/arm/up_pginitialize.c b/nuttx/arch/arm/src/arm/up_pginitialize.c index 1aea95113..5470f73e3 100755 --- a/nuttx/arch/arm/src/arm/up_pginitialize.c +++ b/nuttx/arch/arm/src/arm/up_pginitialize.c @@ -3,7 +3,7 @@ * Initialize the MMU for on-demand paging support. * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/arm/up_prefetchabort.c b/nuttx/arch/arm/src/arm/up_prefetchabort.c index ed3dd91d3..9af644fc0 100644 --- a/nuttx/arch/arm/src/arm/up_prefetchabort.c +++ b/nuttx/arch/arm/src/arm/up_prefetchabort.c @@ -2,7 +2,7 @@ * arch/arm/src/src/up_prefetchabort.c * * Copyright (C) 2007-2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/arm/up_releasepending.c b/nuttx/arch/arm/src/arm/up_releasepending.c index dcad40159..8adeeb26d 100755 --- a/nuttx/arch/arm/src/arm/up_releasepending.c +++ b/nuttx/arch/arm/src/arm/up_releasepending.c @@ -2,7 +2,7 @@ * arch/arm/src/arm/up_releasepending.c * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/arm/up_reprioritizertr.c b/nuttx/arch/arm/src/arm/up_reprioritizertr.c index 38bce2a72..02bc39d62 100755 --- a/nuttx/arch/arm/src/arm/up_reprioritizertr.c +++ b/nuttx/arch/arm/src/arm/up_reprioritizertr.c @@ -2,7 +2,7 @@ * arch/arm/src/arm/up_reprioritizertr.c * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/arm/up_saveusercontext.S b/nuttx/arch/arm/src/arm/up_saveusercontext.S index 8d154d187..43487cc42 100644 --- a/nuttx/arch/arm/src/arm/up_saveusercontext.S +++ b/nuttx/arch/arm/src/arm/up_saveusercontext.S @@ -2,7 +2,7 @@ * arch/arm/src/arm/up_saveusercontext.S * * Copyright (C) 2007, 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/arm/up_schedulesigaction.c b/nuttx/arch/arm/src/arm/up_schedulesigaction.c index 0dfb6e540..a76438f94 100644 --- a/nuttx/arch/arm/src/arm/up_schedulesigaction.c +++ b/nuttx/arch/arm/src/arm/up_schedulesigaction.c @@ -2,7 +2,7 @@ * arch/arm/src/arm/up_schedulesigaction.c * * Copyright (C) 2007-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/arm/up_sigdeliver.c b/nuttx/arch/arm/src/arm/up_sigdeliver.c index f92f85e7e..868449448 100644 --- a/nuttx/arch/arm/src/arm/up_sigdeliver.c +++ b/nuttx/arch/arm/src/arm/up_sigdeliver.c @@ -2,7 +2,7 @@ * arch/arm/src/arm/up_sigdeliver.c * * Copyright (C) 2007-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/arm/up_syscall.c b/nuttx/arch/arm/src/arm/up_syscall.c index f331a1314..1bcd66502 100644 --- a/nuttx/arch/arm/src/arm/up_syscall.c +++ b/nuttx/arch/arm/src/arm/up_syscall.c @@ -2,7 +2,7 @@ * arch/arm/src/arm/up_syscall.c * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/arm/up_unblocktask.c b/nuttx/arch/arm/src/arm/up_unblocktask.c index 73e292561..633dc4e82 100755 --- a/nuttx/arch/arm/src/arm/up_unblocktask.c +++ b/nuttx/arch/arm/src/arm/up_unblocktask.c @@ -2,7 +2,7 @@ * arch/arm/src/arm/up_unblocktask.c * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/arm/up_undefinedinsn.c b/nuttx/arch/arm/src/arm/up_undefinedinsn.c index 4c50991b0..d61abe11b 100644 --- a/nuttx/arch/arm/src/arm/up_undefinedinsn.c +++ b/nuttx/arch/arm/src/arm/up_undefinedinsn.c @@ -2,7 +2,7 @@ * arch/arm/src/arm/up_undefinedinsn.c * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/arm/up_va2pte.c b/nuttx/arch/arm/src/arm/up_va2pte.c index 5f92ad821..eb5a4c56b 100755 --- a/nuttx/arch/arm/src/arm/up_va2pte.c +++ b/nuttx/arch/arm/src/arm/up_va2pte.c @@ -3,7 +3,7 @@ * Utility to map a virtual address to a L2 page table entry. * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/arm/up_vectoraddrexcptn.S b/nuttx/arch/arm/src/arm/up_vectoraddrexcptn.S index e034c394f..ba5787cb9 100644 --- a/nuttx/arch/arm/src/arm/up_vectoraddrexcptn.S +++ b/nuttx/arch/arm/src/arm/up_vectoraddrexcptn.S @@ -2,7 +2,7 @@ * arch/arm/src/src/up_vectoraddrexceptn.S * * Copyright (C) 2008-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/arm/up_vectors.S b/nuttx/arch/arm/src/arm/up_vectors.S index 00c5d52b0..bcf9c37d0 100644 --- a/nuttx/arch/arm/src/arm/up_vectors.S +++ b/nuttx/arch/arm/src/arm/up_vectors.S @@ -2,7 +2,7 @@ * arch/arm/src/arm/up_vectors.S * * Copyright (C) 2007-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/arm/up_vectortab.S b/nuttx/arch/arm/src/arm/up_vectortab.S index a7972fa3c..8eae70055 100644 --- a/nuttx/arch/arm/src/arm/up_vectortab.S +++ b/nuttx/arch/arm/src/arm/up_vectortab.S @@ -2,7 +2,7 @@ * arch/arm/src/arm/up_vectortab.S * * Copyright (C) 2007, 2009-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/armv7-m/psr.h b/nuttx/arch/arm/src/armv7-m/psr.h index 30913f7c9..b8b33c80f 100644 --- a/nuttx/arch/arm/src/armv7-m/psr.h +++ b/nuttx/arch/arm/src/armv7-m/psr.h @@ -2,7 +2,7 @@ * arch/arm/src/armv7-m/psr.h * * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/armv7-m/svcall.h b/nuttx/arch/arm/src/armv7-m/svcall.h index 51b5b9111..9a4db89b1 100644 --- a/nuttx/arch/arm/src/armv7-m/svcall.h +++ b/nuttx/arch/arm/src/armv7-m/svcall.h @@ -2,7 +2,7 @@ * arch/arm/src/armv7-m/svcall.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/armv7-m/up_assert.c b/nuttx/arch/arm/src/armv7-m/up_assert.c index 77fd0b596..2662cbe37 100644 --- a/nuttx/arch/arm/src/armv7-m/up_assert.c +++ b/nuttx/arch/arm/src/armv7-m/up_assert.c @@ -2,7 +2,7 @@ * arch/arm/src/armv7-m/up_assert.c * * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/armv7-m/up_copystate.c b/nuttx/arch/arm/src/armv7-m/up_copystate.c index a5ad312f5..e9eede8f9 100644 --- a/nuttx/arch/arm/src/armv7-m/up_copystate.c +++ b/nuttx/arch/arm/src/armv7-m/up_copystate.c @@ -2,7 +2,7 @@ * arch/arm/src/armv7-m/up_copystate.c * * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/armv7-m/up_doirq.c b/nuttx/arch/arm/src/armv7-m/up_doirq.c index 7ac1ec34d..375054fba 100644 --- a/nuttx/arch/arm/src/armv7-m/up_doirq.c +++ b/nuttx/arch/arm/src/armv7-m/up_doirq.c @@ -2,7 +2,7 @@ * arch/arm/src/armv7-m/up_doirq.c * * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/armv7-m/up_hardfault.c b/nuttx/arch/arm/src/armv7-m/up_hardfault.c index a9eea8103..cb3ce9e8a 100644 --- a/nuttx/arch/arm/src/armv7-m/up_hardfault.c +++ b/nuttx/arch/arm/src/armv7-m/up_hardfault.c @@ -2,7 +2,7 @@ * arch/arm/src/armv7-m/up_hardfault.c * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/armv7-m/up_memfault.c b/nuttx/arch/arm/src/armv7-m/up_memfault.c index bbe3f6573..ab93c7697 100644 --- a/nuttx/arch/arm/src/armv7-m/up_memfault.c +++ b/nuttx/arch/arm/src/armv7-m/up_memfault.c @@ -2,7 +2,7 @@ * arch/arm/src/armv7-m/up_memfault.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/armv7-m/up_mpu.c b/nuttx/arch/arm/src/armv7-m/up_mpu.c index 27936562c..4bb3f21d9 100644 --- a/nuttx/arch/arm/src/armv7-m/up_mpu.c +++ b/nuttx/arch/arm/src/armv7-m/up_mpu.c @@ -2,7 +2,7 @@ * arch/arm/src/armv7-m/up_mpu.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/armv7-m/up_saveusercontext.S b/nuttx/arch/arm/src/armv7-m/up_saveusercontext.S index c8da07430..06eb183d2 100755 --- a/nuttx/arch/arm/src/armv7-m/up_saveusercontext.S +++ b/nuttx/arch/arm/src/armv7-m/up_saveusercontext.S @@ -2,7 +2,7 @@ * arch/arm/src/armv7-m/up_saveusercontext.S * * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/armv7-m/up_sigdeliver.c b/nuttx/arch/arm/src/armv7-m/up_sigdeliver.c index 3c340b8d3..38673c41d 100644 --- a/nuttx/arch/arm/src/armv7-m/up_sigdeliver.c +++ b/nuttx/arch/arm/src/armv7-m/up_sigdeliver.c @@ -2,7 +2,7 @@ * arch/arm/src/armv7-m/up_sigdeliver.c * * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/armv7-m/up_switchcontext.S b/nuttx/arch/arm/src/armv7-m/up_switchcontext.S index 854f6fa16..762e2066e 100755 --- a/nuttx/arch/arm/src/armv7-m/up_switchcontext.S +++ b/nuttx/arch/arm/src/armv7-m/up_switchcontext.S @@ -2,7 +2,7 @@ * arch/arm/src/armv7-m/up_switchcontext.S * * Copyright (C) 2009-2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/c5471/Make.defs b/nuttx/arch/arm/src/c5471/Make.defs index 636197f4e..d1c2cf0ac 100644 --- a/nuttx/arch/arm/src/c5471/Make.defs +++ b/nuttx/arch/arm/src/c5471/Make.defs @@ -2,7 +2,7 @@ # c5471/Make.defs # # Copyright (C) 2007 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt <spudmonkey@racsa.co.cr> +# Author: Gregory Nutt <gnutt@nuttx.org> # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/c5471/c5471_ethernet.c b/nuttx/arch/arm/src/c5471/c5471_ethernet.c index 507f63cf9..142e0f084 100644 --- a/nuttx/arch/arm/src/c5471/c5471_ethernet.c +++ b/nuttx/arch/arm/src/c5471/c5471_ethernet.c @@ -2,7 +2,7 @@ * arch/arm/src/c5471/c5471_ethernet.c * * Copyright (C) 2007, 2009-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Based one a C5471 Linux driver and released under this BSD license with * special permisson from the copyright holder of the Linux driver: diff --git a/nuttx/arch/arm/src/c5471/c5471_lowputc.S b/nuttx/arch/arm/src/c5471/c5471_lowputc.S index 096742a70..b56483b87 100644 --- a/nuttx/arch/arm/src/c5471/c5471_lowputc.S +++ b/nuttx/arch/arm/src/c5471/c5471_lowputc.S @@ -2,7 +2,7 @@ * c5471/c5471_lowputc.S * * Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/c5471/c5471_timerisr.c b/nuttx/arch/arm/src/c5471/c5471_timerisr.c index c9ff79055..1a221674d 100644 --- a/nuttx/arch/arm/src/c5471/c5471_timerisr.c +++ b/nuttx/arch/arm/src/c5471/c5471_timerisr.c @@ -2,7 +2,7 @@ * c5471/c5471_timerisr.c * * Copyright (C) 2007, 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/c5471/c5471_vectors.S b/nuttx/arch/arm/src/c5471/c5471_vectors.S index 34f9e1b23..aa514b03f 100644 --- a/nuttx/arch/arm/src/c5471/c5471_vectors.S +++ b/nuttx/arch/arm/src/c5471/c5471_vectors.S @@ -2,7 +2,7 @@ * arch/arm/src/c5471/c5471_vectors.S * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/c5471/chip.h b/nuttx/arch/arm/src/c5471/chip.h index 7121fd220..d465ba834 100644 --- a/nuttx/arch/arm/src/c5471/chip.h +++ b/nuttx/arch/arm/src/c5471/chip.h @@ -2,7 +2,7 @@ * c5471/chip.h * * Copyright (C) 2007 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/calypso/Make.defs b/nuttx/arch/arm/src/calypso/Make.defs index d8f1613b0..1552f17d1 100644 --- a/nuttx/arch/arm/src/calypso/Make.defs +++ b/nuttx/arch/arm/src/calypso/Make.defs @@ -2,7 +2,7 @@ # calypso/Make.defs # # Copyright (C) 2007 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt <spudmonkey@racsa.co.cr> +# Author: Gregory Nutt <gnutt@nuttx.org> # # Copyright (C) 2011 Stefan Richter. All rights reserved. # Author: Stefan Richter <ichgeh@l--putt.de> diff --git a/nuttx/arch/arm/src/calypso/calypso_lowputc.S b/nuttx/arch/arm/src/calypso/calypso_lowputc.S index 951ea03d5..16e5ef4c1 100644 --- a/nuttx/arch/arm/src/calypso/calypso_lowputc.S +++ b/nuttx/arch/arm/src/calypso/calypso_lowputc.S @@ -6,7 +6,7 @@ * * based on: c5471/c5471_lowputc.S * Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/calypso/calypso_serial.c b/nuttx/arch/arm/src/calypso/calypso_serial.c index 5175d25bb..62e20409b 100644 --- a/nuttx/arch/arm/src/calypso/calypso_serial.c +++ b/nuttx/arch/arm/src/calypso/calypso_serial.c @@ -6,7 +6,7 @@ * * based on c5471/c5471_serial.c * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/calypso/chip.h b/nuttx/arch/arm/src/calypso/chip.h index d190dbc22..c607fc718 100644 --- a/nuttx/arch/arm/src/calypso/chip.h +++ b/nuttx/arch/arm/src/calypso/chip.h @@ -6,7 +6,7 @@ * * based on: c5471/chip.h * Copyright (C) 2007 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/common/up_allocateheap.c b/nuttx/arch/arm/src/common/up_allocateheap.c index fbd1421a7..d4b763196 100644 --- a/nuttx/arch/arm/src/common/up_allocateheap.c +++ b/nuttx/arch/arm/src/common/up_allocateheap.c @@ -2,7 +2,7 @@ * arch/arm/src/common/up_allocateheap.c * * Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/common/up_arch.h b/nuttx/arch/arm/src/common/up_arch.h index b612f6af2..af29bbf65 100644 --- a/nuttx/arch/arm/src/common/up_arch.h +++ b/nuttx/arch/arm/src/common/up_arch.h @@ -2,7 +2,7 @@ * arch/arm/src/common/up_arch.h * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/common/up_checkstack.c b/nuttx/arch/arm/src/common/up_checkstack.c index 6c13f63d1..ac8d9e7b9 100644 --- a/nuttx/arch/arm/src/common/up_checkstack.c +++ b/nuttx/arch/arm/src/common/up_checkstack.c @@ -2,7 +2,7 @@ * arch/arm/src/common/up_checkstack.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/common/up_etherstub.c b/nuttx/arch/arm/src/common/up_etherstub.c index 1c4a71ce6..407e7b45b 100755 --- a/nuttx/arch/arm/src/common/up_etherstub.c +++ b/nuttx/arch/arm/src/common/up_etherstub.c @@ -2,7 +2,7 @@ * arch/arm/src/common/up_etherstub.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/common/up_idle.c b/nuttx/arch/arm/src/common/up_idle.c index 62557c3a8..187af76e7 100644 --- a/nuttx/arch/arm/src/common/up_idle.c +++ b/nuttx/arch/arm/src/common/up_idle.c @@ -2,7 +2,7 @@ * arch/arm/src/common/up_idle.c * * Copyright (C) 2007-2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/common/up_interruptcontext.c b/nuttx/arch/arm/src/common/up_interruptcontext.c index b67ad523a..0039692bc 100644 --- a/nuttx/arch/arm/src/common/up_interruptcontext.c +++ b/nuttx/arch/arm/src/common/up_interruptcontext.c @@ -2,7 +2,7 @@ * arch/arm/src/common/up_interruptcontext.c * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/common/up_lowputs.c b/nuttx/arch/arm/src/common/up_lowputs.c index 8b2919a05..890167e0e 100644 --- a/nuttx/arch/arm/src/common/up_lowputs.c +++ b/nuttx/arch/arm/src/common/up_lowputs.c @@ -2,7 +2,7 @@ * arch/arm/src/common/up_lowputs.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/common/up_mdelay.c b/nuttx/arch/arm/src/common/up_mdelay.c index b9b9ffc0e..2c0447620 100644 --- a/nuttx/arch/arm/src/common/up_mdelay.c +++ b/nuttx/arch/arm/src/common/up_mdelay.c @@ -2,7 +2,7 @@ * arch/arm/src/common/up_mdelay.c * * Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/common/up_modifyreg16.c b/nuttx/arch/arm/src/common/up_modifyreg16.c index e488a6eee..32ebd6f96 100644 --- a/nuttx/arch/arm/src/common/up_modifyreg16.c +++ b/nuttx/arch/arm/src/common/up_modifyreg16.c @@ -2,7 +2,7 @@ * arch/arm/src/common/up_modifyreg16.c * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/common/up_modifyreg32.c b/nuttx/arch/arm/src/common/up_modifyreg32.c index 8b93f6b84..a87873284 100644 --- a/nuttx/arch/arm/src/common/up_modifyreg32.c +++ b/nuttx/arch/arm/src/common/up_modifyreg32.c @@ -2,7 +2,7 @@ * arch/arm/src/common/up_modifyreg32.c * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/common/up_modifyreg8.c b/nuttx/arch/arm/src/common/up_modifyreg8.c index 2c9dbac25..92ed48eff 100644 --- a/nuttx/arch/arm/src/common/up_modifyreg8.c +++ b/nuttx/arch/arm/src/common/up_modifyreg8.c @@ -2,7 +2,7 @@ * arch/arm/src/common/up_modifyreg8.c * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/common/up_puts.c b/nuttx/arch/arm/src/common/up_puts.c index 4e74f0cdc..f56dbf07e 100644 --- a/nuttx/arch/arm/src/common/up_puts.c +++ b/nuttx/arch/arm/src/common/up_puts.c @@ -2,7 +2,7 @@ * arch/arm/src/common/up_puts.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/common/up_releasestack.c b/nuttx/arch/arm/src/common/up_releasestack.c index 407bd1b54..82f5db88f 100644 --- a/nuttx/arch/arm/src/common/up_releasestack.c +++ b/nuttx/arch/arm/src/common/up_releasestack.c @@ -2,7 +2,7 @@ * arch/arm/src/common/up_releasestack.c * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/common/up_udelay.c b/nuttx/arch/arm/src/common/up_udelay.c index d2d5b74d9..8fcb93522 100644 --- a/nuttx/arch/arm/src/common/up_udelay.c +++ b/nuttx/arch/arm/src/common/up_udelay.c @@ -2,7 +2,7 @@ * arch/arm/src/common/up_udelay.c * * Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/common/up_usestack.c b/nuttx/arch/arm/src/common/up_usestack.c index f46be0cc9..a3f4f4816 100644 --- a/nuttx/arch/arm/src/common/up_usestack.c +++ b/nuttx/arch/arm/src/common/up_usestack.c @@ -2,7 +2,7 @@ * arch/arm/src/common/up_usestack.c * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/dm320/Make.defs b/nuttx/arch/arm/src/dm320/Make.defs index 7962d8178..957196672 100644 --- a/nuttx/arch/arm/src/dm320/Make.defs +++ b/nuttx/arch/arm/src/dm320/Make.defs @@ -2,7 +2,7 @@ # dm320/Make.defs # # Copyright (C) 2007, 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt <spudmonkey@racsa.co.cr> +# Author: Gregory Nutt <gnutt@nuttx.org> # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/dm320/chip.h b/nuttx/arch/arm/src/dm320/chip.h index 102d6caa3..7ac681e11 100644 --- a/nuttx/arch/arm/src/dm320/chip.h +++ b/nuttx/arch/arm/src/dm320/chip.h @@ -2,7 +2,7 @@ * arch/arm/src/dm320/chip.h * * Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/dm320/dm320_ahb.h b/nuttx/arch/arm/src/dm320/dm320_ahb.h index 7e238f54b..6a3654666 100644 --- a/nuttx/arch/arm/src/dm320/dm320_ahb.h +++ b/nuttx/arch/arm/src/dm320/dm320_ahb.h @@ -2,7 +2,7 @@ * dm320/dm320_uart.h * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/dm320/dm320_allocateheap.c b/nuttx/arch/arm/src/dm320/dm320_allocateheap.c index 19875276b..5d4b90093 100644 --- a/nuttx/arch/arm/src/dm320/dm320_allocateheap.c +++ b/nuttx/arch/arm/src/dm320/dm320_allocateheap.c @@ -2,7 +2,7 @@ * dm320/dm320_allocateheap.c * * Copyright (C) 2007 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/dm320/dm320_busc.h b/nuttx/arch/arm/src/dm320/dm320_busc.h index b7c3287e5..8c3590946 100644 --- a/nuttx/arch/arm/src/dm320/dm320_busc.h +++ b/nuttx/arch/arm/src/dm320/dm320_busc.h @@ -2,7 +2,7 @@ * dm320/dm320_busc.h * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/dm320/dm320_clkc.h b/nuttx/arch/arm/src/dm320/dm320_clkc.h index 1e8e7da91..7019b11dc 100644 --- a/nuttx/arch/arm/src/dm320/dm320_clkc.h +++ b/nuttx/arch/arm/src/dm320/dm320_clkc.h @@ -2,7 +2,7 @@ * dm320/dm320_clkc.h * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/dm320/dm320_decodeirq.c b/nuttx/arch/arm/src/dm320/dm320_decodeirq.c index cb3efa5b9..c7032c4b1 100644 --- a/nuttx/arch/arm/src/dm320/dm320_decodeirq.c +++ b/nuttx/arch/arm/src/dm320/dm320_decodeirq.c @@ -3,7 +3,7 @@ * arch/arm/src/chip/dm320_decodeirq.c * * Copyright (C) 2007, 2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/dm320/dm320_emif.h b/nuttx/arch/arm/src/dm320/dm320_emif.h index 0675595d0..653e20fe0 100644 --- a/nuttx/arch/arm/src/dm320/dm320_emif.h +++ b/nuttx/arch/arm/src/dm320/dm320_emif.h @@ -2,7 +2,7 @@ * dm320/dm320_emif.h * * Copyright (C) 2007, 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/dm320/dm320_framebuffer.c b/nuttx/arch/arm/src/dm320/dm320_framebuffer.c index fc29fa007..1b1197d53 100644 --- a/nuttx/arch/arm/src/dm320/dm320_framebuffer.c +++ b/nuttx/arch/arm/src/dm320/dm320_framebuffer.c @@ -2,7 +2,7 @@ * arch/arm/src/dm320/dm320_framebuffer.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/dm320/dm320_gio.h b/nuttx/arch/arm/src/dm320/dm320_gio.h index da21c6755..4ad277047 100644 --- a/nuttx/arch/arm/src/dm320/dm320_gio.h +++ b/nuttx/arch/arm/src/dm320/dm320_gio.h @@ -2,7 +2,7 @@ * dm320/dm320_gio.h * * Copyright (C) 2007, 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/dm320/dm320_intc.h b/nuttx/arch/arm/src/dm320/dm320_intc.h index 245eb30ca..f05febb2f 100644 --- a/nuttx/arch/arm/src/dm320/dm320_intc.h +++ b/nuttx/arch/arm/src/dm320/dm320_intc.h @@ -2,7 +2,7 @@ * dm320/dm320_intc.h * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/dm320/dm320_lowputc.S b/nuttx/arch/arm/src/dm320/dm320_lowputc.S index 52953fc2c..e60fa9527 100644 --- a/nuttx/arch/arm/src/dm320/dm320_lowputc.S +++ b/nuttx/arch/arm/src/dm320/dm320_lowputc.S @@ -3,7 +3,7 @@ * arch/arm/src/chip/dm320_lowputc.S * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/dm320/dm320_memorymap.h b/nuttx/arch/arm/src/dm320/dm320_memorymap.h index 8b8e9c447..a8aafbb71 100644 --- a/nuttx/arch/arm/src/dm320/dm320_memorymap.h +++ b/nuttx/arch/arm/src/dm320/dm320_memorymap.h @@ -2,7 +2,7 @@ * dm320/dm320_memorymap.h * * Copyright (C) 2007, 2009-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/dm320/dm320_osd.h b/nuttx/arch/arm/src/dm320/dm320_osd.h index 496e49ff2..199651e69 100644 --- a/nuttx/arch/arm/src/dm320/dm320_osd.h +++ b/nuttx/arch/arm/src/dm320/dm320_osd.h @@ -2,7 +2,7 @@ * dm320/dm320_osd.h * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/dm320/dm320_restart.S b/nuttx/arch/arm/src/dm320/dm320_restart.S index ccbdfc2d9..7e25d8ff2 100644 --- a/nuttx/arch/arm/src/dm320/dm320_restart.S +++ b/nuttx/arch/arm/src/dm320/dm320_restart.S @@ -2,7 +2,7 @@ * arch/arm/src/dm320/dm320_restart.S * * Copyright (C) 2007, 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/dm320/dm320_timer.h b/nuttx/arch/arm/src/dm320/dm320_timer.h index 31839a091..2ef407906 100644 --- a/nuttx/arch/arm/src/dm320/dm320_timer.h +++ b/nuttx/arch/arm/src/dm320/dm320_timer.h @@ -2,7 +2,7 @@ * dm320/dm320_timer.h * * Copyright (C) 2007, 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/dm320/dm320_timerisr.c b/nuttx/arch/arm/src/dm320/dm320_timerisr.c index 18e88b448..59efa53d3 100644 --- a/nuttx/arch/arm/src/dm320/dm320_timerisr.c +++ b/nuttx/arch/arm/src/dm320/dm320_timerisr.c @@ -3,7 +3,7 @@ * arch/arm/src/chip/dm320_timerisr.c * * Copyright (C) 2007, 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/dm320/dm320_uart.h b/nuttx/arch/arm/src/dm320/dm320_uart.h index f92a5ccdd..d66848941 100644 --- a/nuttx/arch/arm/src/dm320/dm320_uart.h +++ b/nuttx/arch/arm/src/dm320/dm320_uart.h @@ -2,7 +2,7 @@ * dm320/dm320_uart.h * * Copyright (C) 2007, 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/dm320/dm320_usb.h b/nuttx/arch/arm/src/dm320/dm320_usb.h index 229c2857e..6db7aef3d 100644 --- a/nuttx/arch/arm/src/dm320/dm320_usb.h +++ b/nuttx/arch/arm/src/dm320/dm320_usb.h @@ -2,7 +2,7 @@ * dm320/dm320_uart.h * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/imx/Make.defs b/nuttx/arch/arm/src/imx/Make.defs index f26bd0575..3b2e6ad77 100644 --- a/nuttx/arch/arm/src/imx/Make.defs +++ b/nuttx/arch/arm/src/imx/Make.defs @@ -2,7 +2,7 @@ # arch/arm/src/imx/Make.defs # # Copyright (C) 2009 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt <spudmonkey@racsa.co.cr> +# Author: Gregory Nutt <gnutt@nuttx.org> # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/imx/chip.h b/nuttx/arch/arm/src/imx/chip.h index c8a6615d7..94985efb6 100644 --- a/nuttx/arch/arm/src/imx/chip.h +++ b/nuttx/arch/arm/src/imx/chip.h @@ -2,7 +2,7 @@ * arch/arm/src/imx/chip.h * * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/imx/imx_aitc.h b/nuttx/arch/arm/src/imx/imx_aitc.h index fdd8a5cf3..5b83c5f46 100644 --- a/nuttx/arch/arm/src/imx/imx_aitc.h +++ b/nuttx/arch/arm/src/imx/imx_aitc.h @@ -2,7 +2,7 @@ * arch/arm/src/imx/imx_aitc.h * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/imx/imx_allocateheap.c b/nuttx/arch/arm/src/imx/imx_allocateheap.c index a42b2fb85..4831c8c8b 100644 --- a/nuttx/arch/arm/src/imx/imx_allocateheap.c +++ b/nuttx/arch/arm/src/imx/imx_allocateheap.c @@ -3,7 +3,7 @@ * arch/arm/src/chip/imx_allocateheap.c * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/imx/imx_cspi.h b/nuttx/arch/arm/src/imx/imx_cspi.h index 421b6a4e3..1a60730d5 100755 --- a/nuttx/arch/arm/src/imx/imx_cspi.h +++ b/nuttx/arch/arm/src/imx/imx_cspi.h @@ -2,7 +2,7 @@ * arch/arm/src/imx/imx_cspi.h * * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/imx/imx_decodeirq.c b/nuttx/arch/arm/src/imx/imx_decodeirq.c index 55c72ed76..ba37a60a2 100644 --- a/nuttx/arch/arm/src/imx/imx_decodeirq.c +++ b/nuttx/arch/arm/src/imx/imx_decodeirq.c @@ -3,7 +3,7 @@ * arch/arm/src/chip/imx_decodeirq.c * * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/imx/imx_dma.h b/nuttx/arch/arm/src/imx/imx_dma.h index bf3b03673..2d5d553ce 100755 --- a/nuttx/arch/arm/src/imx/imx_dma.h +++ b/nuttx/arch/arm/src/imx/imx_dma.h @@ -1,250 +1,250 @@ -/************************************************************************************
- * arch/arm/src/imx/imx_dma.h
- *
- * Copyright (C) 2009 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_IMX_DMA_H
-#define __ARCH_ARM_IMX_DMA_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-/************************************************************************************
- * Definitions
- ************************************************************************************/
-
-/* DMA Register Offsets *************************************************************/
-
-#define DMA_SYS_OFFSET 0x0000
-#define DMA_M2D_OFFSET 0x0040
-#define DMA_CH0_OFFSET 0x0080
-#define DMA_CH1_OFFSET 0x00c0
-#define DMA_CH2_OFFSET 0x0100
-#define DMA_CH3_OFFSET 0x0140
-#define DMA_CH4_OFFSET 0x0180
-#define DMA_CH5_OFFSET 0x01C0
-#define DMA_CH6_OFFSET 0x0200
-#define DMA_CH7_OFFSET 0x0240
-#define DMA_CH8_OFFSET 0x0280
-#define DMA_CH9_OFFSET 0x02c0
-#define DMA_CH10_OFFSET 0x0300
-#define DMA_CH_OFFSET(n) (DMA_CH0_OFFSET + (n)*0x0040)
-#define DMA_TST_OFFSET 0x0340
-
-#define DMA_DCR_OFFSET 0x0000
-#define DMA_ISR_OFFSET 0x0004
-#define DMA_IMR_OFFSET 0x0008
-#define DMA_BTOSR_OFFSET 0x000c
-#define DMA_RTOSR_OFFSET 0x0010
-#define DMA_TESR_OFFSET 0x0014
-#define DMA_BOSR_OFFSET 0x0018
-#define DMA_BTOCR_OFFSET 0x001c
-
-#define DMA_WSRA_OFFSET 0x0000
-#define DMA_XSRA_OFFSET 0x0004
-#define DMA_YSRA_OFFSET 0x0008
-#define DMA_WSRB_OFFSET 0x000c
-#define DMA_XSRB_OFFSET 0x0010
-#define DMA_YSRB_OFFSET 0x0014
-
-#define DMA_SAR_OFFSET 0x0000
-#define DMA_DAR_OFFSET 0x0004
-#define DMA_CNTR_OFFSET 0x0008
-#define DMA_CCR_OFFSET 0x000c
-#define DMA_RSSR_OFFSET 0x0010
-#define DMA_BLR_OFFSET 0x0014
-#define DMA_RTOR_OFFSET 0x0018
-#define DMA_BUCR_OFFSET 0x0018
-
-#define DMA_TCR_OFFSET 0x0000
-#define DMA_TFIFOA_OFFSET 0x0004
-#define DMA_TDRR_OFFSET 0x0008
-#define DMA_TDIPR_OFFSET 0x000c
-#define DMA_TFIFOB_OFFSET 0x0010
-
-/* DMA Register Addresses ***********************************************************/
-
-#define IMX_DMA_SYS_BASE (IMX_DMA_VBASE + DMA_SYS_OFFSET)
-#define IMX_DMA_M2D_BASE (IMX_DMA_VBASE + DMA_M2D_OFFSET)
-#define IMX_DMA_CH0_BASE (IMX_DMA_VBASE + DMA_CH0_OFFSET)
-#define IMX_DMA_CH1_BASE (IMX_DMA_VBASE + DMA_CH1_OFFSET)
-#define IMX_DMA_CH2_BASE (IMX_DMA_VBASE + DMA_CH2_OFFSET)
-#define IMX_DMA_CH3_BASE (IMX_DMA_VBASE + DMA_CH3_OFFSET)
-#define IMX_DMA_CH4_BASE (IMX_DMA_VBASE + DMA_CH4_OFFSET)
-#define IMX_DMA_CH5_BASE (IMX_DMA_VBASE + DMA_CH5_OFFSET)
-#define IMX_DMA_CH6_BASE (IMX_DMA_VBASE + DMA_CH6_OFFSET)
-#define IMX_DMA_CH7_BASE (IMX_DMA_VBASE + DMA_CH7_OFFSET)
-#define IMX_DMA_CH8_BASE (IMX_DMA_VBASE + DMA_CH8_OFFSET)
-#define IMX_DMA_CH9_BASE (IMX_DMA_VBASE + DMA_CH9_OFFSET)
-#define IMX_DMA_CH10_BASE (IMX_DMA_VBASE + DMA_CH10_OFFSET)
-#define IMX_DMA_CH_BASE(n) (IMX_DMA_VBASE + DMA_CH_OFFSET(n))
-#define IMX_DMA_TST_BASE (IMX_DMA_VBASE + DMA_TST_OFFSET)
-
-#define IMX_DMA_DCR (DMA_SYS_BASE + DMA_DCR_OFFSET)
-#define IMX_DMA_ISR (DMA_SYS_BASE + DMA_ISR_OFFSET)
-#define IMX_DMA_IMR (DMA_SYS_BASE + DMA_IMR_OFFSET)
-#define IMX_DMA_BTOSR (DMA_SYS_BASE + DMA_BTOSR_OFFSET)
-#define IMX_DMA_RTOSR (DMA_SYS_BASE + DMA_RTOSR_OFFSET)
-#define IMX_DMA_TESR (DMA_SYS_BASE + DMA_TESR_OFFSET)
-#define IMX_DMA_BOSR (DMA_SYS_BASE + DMA_BOSR_OFFSET)
-#define IMX_DMA_BTOCR (DMA_SYS_BASE + DMA_BTOCR_OFFSET)
-
-#define IMX_DMA_WSRA (DMA_M2D_BASE + DMA_WSRA_OFFSET)
-#define IMX_DMA_XSRA (DMA_M2D_BASE + DMA_XSRA_OFFSET)
-#define IMX_DMA_YSRA (DMA_M2D_BASE + DMA_YSRA_OFFSET)
-#define IMX_DMA_WSRB (DMA_M2D_BASE + DMA_WSRB_OFFSET)
-#define IMX_DMA_XSRB (DMA_M2D_BASE + DMA_XSRB_OFFSET)
-#define IMX_DMA_YSRB (DMA_M2D_BASE + DMA_YSRB_OFFSET)
-
-#define IMX_DMA_SAR0 (DMA_CH0_BASE + DMA_SAR_OFFSET)
-#define IMX_DMA_DAR0 (DMA_CH0_BASE + DMA_DAR_OFFSET)
-#define IMX_DMA_CNTR0 (DMA_CH0_BASE + DMA_CNTR_OFFSET)
-#define IMX_DMA_CCR0 (DMA_CH0_BASE + DMA_CCR_OFFSET)
-#define IMX_DMA_RSSR0 (DMA_CH0_BASE + DMA_RSSR_OFFSET)
-#define IMX_DMA_BLR0 (DMA_CH0_BASE + DMA_BLR_OFFSET)
-#define IMX_DMA_RTOR0 (DMA_CH0_BASE + DMA_RTOR_OFFSET)
-#define IMX_DMA_BUCR0 (DMA_CH0_BASE + DMA_BUCR_OFFSET)
-
-#define IMX_DMA_SAR1 (DMA_CH1_BASE + DMA_SAR_OFFSET)
-#define IMX_DMA_DAR1 (DMA_CH1_BASE + DMA_DAR_OFFSET)
-#define IMX_DMA_CNTR1 (DMA_CH1_BASE + DMA_CNTR_OFFSET)
-#define IMX_DMA_CCR1 (DMA_CH1_BASE + DMA_CCR_OFFSET)
-#define IMX_DMA_RSSR1 (DMA_CH1_BASE + DMA_RSSR_OFFSET)
-#define IMX_DMA_BLR1 (DMA_CH1_BASE + DMA_BLR_OFFSET)
-#define IMX_DMA_RTOR1 (DMA_CH1_BASE + DMA_RTOR_OFFSET)
-#define IMX_DMA_BUCR1 (DMA_CH1_BASE + DMA_BUCR_OFFSET)
-
-#define IMX_DMA_SAR2 (DMA_CH2_BASE + DMA_SAR_OFFSET)
-#define IMX_DMA_DAR2 (DMA_CH2_BASE + DMA_DAR_OFFSET)
-#define IMX_DMA_CNTR2 (DMA_CH2_BASE + DMA_CNTR_OFFSET)
-#define IMX_DMA_CCR2 (DMA_CH2_BASE + DMA_CCR_OFFSET)
-#define IMX_DMA_RSSR2 (DMA_CH2_BASE + DMA_RSSR_OFFSET)
-#define IMX_DMA_BLR2 (DMA_CH2_BASE + DMA_BLR_OFFSET)
-#define IMX_DMA_RTOR2 (DMA_CH2_BASE + DMA_RTOR_OFFSET)
-#define IMX_DMA_BUCR2 (DMA_CH2_BASE + DMA_BUCR_OFFSET)
-
-#define IMX_DMA_SAR3 (DMA_CH3_BASE + DMA_SAR_OFFSET)
-#define IMX_DMA_DAR3 (DMA_CH3_BASE + DMA_DAR_OFFSET)
-#define IMX_DMA_CNTR3 (DMA_CH3_BASE + DMA_CNTR_OFFSET)
-#define IMX_DMA_CCR3 (DMA_CH3_BASE + DMA_CCR_OFFSET)
-#define IMX_DMA_RSSR3 (DMA_CH3_BASE + DMA_RSSR_OFFSET)
-#define IMX_DMA_BLR3 (DMA_CH3_BASE + DMA_BLR_OFFSET)
-#define IMX_DMA_RTOR3 (DMA_CH3_BASE + DMA_RTOR_OFFSET)
-#define IMX_DMA_BUCR3 (DMA_CH3_BASE + DMA_BUCR_OFFSET)
-
-#define IMX_DMA_SAR4 (DMA_CH4_BASE + DMA_SAR_OFFSET)
-#define IMX_DMA_DAR4 (DMA_CH4_BASE + DMA_DAR_OFFSET)
-#define IMX_DMA_CNTR4 (DMA_CH4_BASE + DMA_CNTR_OFFSET)
-#define IMX_DMA_CCR4 (DMA_CH4_BASE + DMA_CCR_OFFSET)
-#define IMX_DMA_RSSR4 (DMA_CH4_BASE + DMA_RSSR_OFFSET)
-#define IMX_DMA_BLR4 (DMA_CH4_BASE + DMA_BLR_OFFSET)
-#define IMX_DMA_RTOR4 (DMA_CH4_BASE + DMA_RTOR_OFFSET)
-#define IMX_DMA_BUCR4 (DMA_CH4_BASE + DMA_BUCR_OFFSET)
-
-#define IMX_DMA_SAR5 (DMA_CH5_BASE + DMA_SAR_OFFSET)
-#define IMX_DMA_DAR5 (DMA_CH5_BASE + DMA_DAR_OFFSET)
-#define IMX_DMA_CNTR5 (DMA_CH5_BASE + DMA_CNTR_OFFSET)
-#define IMX_DMA_CCR5 (DMA_CH5_BASE + DMA_CCR_OFFSET)
-#define IMX_DMA_RSSR5 (DMA_CH5_BASE + DMA_RSSR_OFFSET)
-#define IMX_DMA_BLR5 (DMA_CH5_BASE + DMA_BLR_OFFSET)
-#define IMX_DMA_RTOR5 (DMA_CH5_BASE + DMA_RTOR_OFFSET)
-#define IMX_DMA_BUCR5 (DMA_CH5_BASE + DMA_BUCR_OFFSET)
-
-#define IMX_DMA_SAR6 (DMA_CH6_BASE + DMA_SAR_OFFSET)
-#define IMX_DMA_DAR6 (DMA_CH6_BASE + DMA_DAR_OFFSET)
-#define IMX_DMA_CNTR6 (DMA_CH6_BASE + DMA_CNTR_OFFSET)
-#define IMX_DMA_CCR6 (DMA_CH6_BASE + DMA_CCR_OFFSET)
-#define IMX_DMA_RSSR6 (DMA_CH6_BASE + DMA_RSSR_OFFSET)
-#define IMX_DMA_BLR6 (DMA_CH6_BASE + DMA_BLR_OFFSET)
-#define IMX_DMA_RTOR6 (DMA_CH6_BASE + DMA_RTOR_OFFSET)
-#define IMX_DMA_BUCR6 (DMA_CH6_BASE + DMA_BUCR_OFFSET)
-
-#define IMX_DMA_SAR7 (DMA_CH7_BASE + DMA_SAR_OFFSET)
-#define IMX_DMA_DAR7 (DMA_CH7_BASE + DMA_DAR_OFFSET)
-#define IMX_DMA_CNTR7 (DMA_CH7_BASE + DMA_CNTR_OFFSET)
-#define IMX_DMA_CCR7 (DMA_CH7_BASE + DMA_CCR_OFFSET)
-#define IMX_DMA_RSSR7 (DMA_CH7_BASE + DMA_RSSR_OFFSET)
-#define IMX_DMA_BLR7 (DMA_CH7_BASE + DMA_BLR_OFFSET)
-#define IMX_DMA_RTOR7 (DMA_CH7_BASE + DMA_RTOR_OFFSET)
-#define IMX_DMA_BUCR7 (DMA_CH7_BASE + DMA_BUCR_OFFSET)
-
-#define IMX_DMA_SAR8 (DMA_CH8_BASE + DMA_SAR_OFFSET)
-#define IMX_DMA_DAR8 (DMA_CH8_BASE + DMA_DAR_OFFSET)
-#define IMX_DMA_CNTR8 (DMA_CH8_BASE + DMA_CNTR_OFFSET)
-#define IMX_DMA_CCR8 (DMA_CH8_BASE + DMA_CCR_OFFSET)
-#define IMX_DMA_RSSR8 (DMA_CH8_BASE + DMA_RSSR_OFFSET)
-#define IMX_DMA_BLR8 (DMA_CH8_BASE + DMA_BLR_OFFSET)
-#define IMX_DMA_RTOR8 (DMA_CH8_BASE + DMA_RTOR_OFFSET)
-#define IMX_DMA_BUCR8 (DMA_CH8_BASE + DMA_BUCR_OFFSET)
-
-#define IMX_DMA_SAR9 (DMA_CH9_BASE + DMA_SAR_OFFSET)
-#define IMX_DMA_DAR9 (DMA_CH9_BASE + DMA_DAR_OFFSET)
-#define IMX_DMA_CNTR9 (DMA_CH9_BASE + DMA_CNTR_OFFSET)
-#define IMX_DMA_CCR9 (DMA_CH9_BASE + DMA_CCR_OFFSET)
-#define IMX_DMA_RSSR9 (DMA_CH9_BASE + DMA_RSSR_OFFSET)
-#define IMX_DMA_BLR9 (DMA_CH9_BASE + DMA_BLR_OFFSET)
-#define IMX_DMA_RTOR9 (DMA_CH9_BASE + DMA_RTOR_OFFSET)
-#define IMX_DMA_BUCR9 (DMA_CH9_BASE + DMA_BUCR_OFFSET)
-
-#define IMX_DMA_SAR10 (DMA_CH10_BASE + DMA_SAR_OFFSET)
-#define IMX_DMA_DAR10 (DMA_CH10_BASE + DMA_DAR_OFFSET)
-#define IMX_DMA_CNTR10 (DMA_CH10_BASE + DMA_CNTR_OFFSET)
-#define IMX_DMA_CCR10 (DMA_CH10_BASE + DMA_CCR_OFFSET)
-#define IMX_DMA_RSSR10 (DMA_CH10_BASE + DMA_RSSR_OFFSET)
-#define IMX_DMA_BLR10 (DMA_CH10_BASE + DMA_BLR_OFFSET)
-#define IMX_DMA_RTOR10 (DMA_CH10_BASE + DMA_RTOR_OFFSET)
-#define IMX_DMA_BUCR10 (DMA_CH10_BASE + DMA_BUCR_OFFSET)
-
-#define IMX_DMA_SAR(n) (DMA_CH_BASE(n) + DMA_SAR_OFFSET)
-#define IMX_DMA_DAR(n) (DMA_CH_BASE(n) + DMA_DAR_OFFSET)
-#define IMX_DMA_CNTR(n) (DMA_CH_BASE(n) + DMA_CNTR_OFFSET)
-#define IMX_DMA_CCR(n) (DMA_CH_BASE(n) + DMA_CCR_OFFSET)
-#define IMX_DMA_RSSR(n) (DMA_CH_BASE(n) + DMA_RSSR_OFFSET)
-#define IMX_DMA_BLR(n) (DMA_CH_BASE(n) + DMA_BLR_OFFSET)
-#define IMX_DMA_RTOR(n) (DMA_CH_BASE(n) + DMA_RTOR_OFFSET)
-#define IMX_DMA_BUCR(n) (DMA_CH_BASE(n) + DMA_BUCR_OFFSET)
-
-#define IMX_DMA_TCR (DMA_TST_BASE + DMA_TCR_OFFSET)
-#define IMX_DMA_TFIFOA (DMA_TST_BASE + DMA_TFIFOA_OFFSET)
-#define IMX_DMA_TDRR (DMA_TST_BASE + DMA_TDRR_OFFSET)
-#define IMX_DMA_TDIPR (DMA_TST_BASE + DMA_TDIPR_OFFSET)
-#define IMX_DMA_TFIFOB (DMA_TST_BASE + DMA_TFIFOB_OFFSET)
-
-/* DMA Register Bit Definitions *****************************************************/
-
-/************************************************************************************
- * Inline Functions
- ************************************************************************************/
-
-#endif /* __ARCH_ARM_IMX_DMA_H */
+/************************************************************************************ + * arch/arm/src/imx/imx_dma.h + * + * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_IMX_DMA_H +#define __ARCH_ARM_IMX_DMA_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +/************************************************************************************ + * Definitions + ************************************************************************************/ + +/* DMA Register Offsets *************************************************************/ + +#define DMA_SYS_OFFSET 0x0000 +#define DMA_M2D_OFFSET 0x0040 +#define DMA_CH0_OFFSET 0x0080 +#define DMA_CH1_OFFSET 0x00c0 +#define DMA_CH2_OFFSET 0x0100 +#define DMA_CH3_OFFSET 0x0140 +#define DMA_CH4_OFFSET 0x0180 +#define DMA_CH5_OFFSET 0x01C0 +#define DMA_CH6_OFFSET 0x0200 +#define DMA_CH7_OFFSET 0x0240 +#define DMA_CH8_OFFSET 0x0280 +#define DMA_CH9_OFFSET 0x02c0 +#define DMA_CH10_OFFSET 0x0300 +#define DMA_CH_OFFSET(n) (DMA_CH0_OFFSET + (n)*0x0040) +#define DMA_TST_OFFSET 0x0340 + +#define DMA_DCR_OFFSET 0x0000 +#define DMA_ISR_OFFSET 0x0004 +#define DMA_IMR_OFFSET 0x0008 +#define DMA_BTOSR_OFFSET 0x000c +#define DMA_RTOSR_OFFSET 0x0010 +#define DMA_TESR_OFFSET 0x0014 +#define DMA_BOSR_OFFSET 0x0018 +#define DMA_BTOCR_OFFSET 0x001c + +#define DMA_WSRA_OFFSET 0x0000 +#define DMA_XSRA_OFFSET 0x0004 +#define DMA_YSRA_OFFSET 0x0008 +#define DMA_WSRB_OFFSET 0x000c +#define DMA_XSRB_OFFSET 0x0010 +#define DMA_YSRB_OFFSET 0x0014 + +#define DMA_SAR_OFFSET 0x0000 +#define DMA_DAR_OFFSET 0x0004 +#define DMA_CNTR_OFFSET 0x0008 +#define DMA_CCR_OFFSET 0x000c +#define DMA_RSSR_OFFSET 0x0010 +#define DMA_BLR_OFFSET 0x0014 +#define DMA_RTOR_OFFSET 0x0018 +#define DMA_BUCR_OFFSET 0x0018 + +#define DMA_TCR_OFFSET 0x0000 +#define DMA_TFIFOA_OFFSET 0x0004 +#define DMA_TDRR_OFFSET 0x0008 +#define DMA_TDIPR_OFFSET 0x000c +#define DMA_TFIFOB_OFFSET 0x0010 + +/* DMA Register Addresses ***********************************************************/ + +#define IMX_DMA_SYS_BASE (IMX_DMA_VBASE + DMA_SYS_OFFSET) +#define IMX_DMA_M2D_BASE (IMX_DMA_VBASE + DMA_M2D_OFFSET) +#define IMX_DMA_CH0_BASE (IMX_DMA_VBASE + DMA_CH0_OFFSET) +#define IMX_DMA_CH1_BASE (IMX_DMA_VBASE + DMA_CH1_OFFSET) +#define IMX_DMA_CH2_BASE (IMX_DMA_VBASE + DMA_CH2_OFFSET) +#define IMX_DMA_CH3_BASE (IMX_DMA_VBASE + DMA_CH3_OFFSET) +#define IMX_DMA_CH4_BASE (IMX_DMA_VBASE + DMA_CH4_OFFSET) +#define IMX_DMA_CH5_BASE (IMX_DMA_VBASE + DMA_CH5_OFFSET) +#define IMX_DMA_CH6_BASE (IMX_DMA_VBASE + DMA_CH6_OFFSET) +#define IMX_DMA_CH7_BASE (IMX_DMA_VBASE + DMA_CH7_OFFSET) +#define IMX_DMA_CH8_BASE (IMX_DMA_VBASE + DMA_CH8_OFFSET) +#define IMX_DMA_CH9_BASE (IMX_DMA_VBASE + DMA_CH9_OFFSET) +#define IMX_DMA_CH10_BASE (IMX_DMA_VBASE + DMA_CH10_OFFSET) +#define IMX_DMA_CH_BASE(n) (IMX_DMA_VBASE + DMA_CH_OFFSET(n)) +#define IMX_DMA_TST_BASE (IMX_DMA_VBASE + DMA_TST_OFFSET) + +#define IMX_DMA_DCR (DMA_SYS_BASE + DMA_DCR_OFFSET) +#define IMX_DMA_ISR (DMA_SYS_BASE + DMA_ISR_OFFSET) +#define IMX_DMA_IMR (DMA_SYS_BASE + DMA_IMR_OFFSET) +#define IMX_DMA_BTOSR (DMA_SYS_BASE + DMA_BTOSR_OFFSET) +#define IMX_DMA_RTOSR (DMA_SYS_BASE + DMA_RTOSR_OFFSET) +#define IMX_DMA_TESR (DMA_SYS_BASE + DMA_TESR_OFFSET) +#define IMX_DMA_BOSR (DMA_SYS_BASE + DMA_BOSR_OFFSET) +#define IMX_DMA_BTOCR (DMA_SYS_BASE + DMA_BTOCR_OFFSET) + +#define IMX_DMA_WSRA (DMA_M2D_BASE + DMA_WSRA_OFFSET) +#define IMX_DMA_XSRA (DMA_M2D_BASE + DMA_XSRA_OFFSET) +#define IMX_DMA_YSRA (DMA_M2D_BASE + DMA_YSRA_OFFSET) +#define IMX_DMA_WSRB (DMA_M2D_BASE + DMA_WSRB_OFFSET) +#define IMX_DMA_XSRB (DMA_M2D_BASE + DMA_XSRB_OFFSET) +#define IMX_DMA_YSRB (DMA_M2D_BASE + DMA_YSRB_OFFSET) + +#define IMX_DMA_SAR0 (DMA_CH0_BASE + DMA_SAR_OFFSET) +#define IMX_DMA_DAR0 (DMA_CH0_BASE + DMA_DAR_OFFSET) +#define IMX_DMA_CNTR0 (DMA_CH0_BASE + DMA_CNTR_OFFSET) +#define IMX_DMA_CCR0 (DMA_CH0_BASE + DMA_CCR_OFFSET) +#define IMX_DMA_RSSR0 (DMA_CH0_BASE + DMA_RSSR_OFFSET) +#define IMX_DMA_BLR0 (DMA_CH0_BASE + DMA_BLR_OFFSET) +#define IMX_DMA_RTOR0 (DMA_CH0_BASE + DMA_RTOR_OFFSET) +#define IMX_DMA_BUCR0 (DMA_CH0_BASE + DMA_BUCR_OFFSET) + +#define IMX_DMA_SAR1 (DMA_CH1_BASE + DMA_SAR_OFFSET) +#define IMX_DMA_DAR1 (DMA_CH1_BASE + DMA_DAR_OFFSET) +#define IMX_DMA_CNTR1 (DMA_CH1_BASE + DMA_CNTR_OFFSET) +#define IMX_DMA_CCR1 (DMA_CH1_BASE + DMA_CCR_OFFSET) +#define IMX_DMA_RSSR1 (DMA_CH1_BASE + DMA_RSSR_OFFSET) +#define IMX_DMA_BLR1 (DMA_CH1_BASE + DMA_BLR_OFFSET) +#define IMX_DMA_RTOR1 (DMA_CH1_BASE + DMA_RTOR_OFFSET) +#define IMX_DMA_BUCR1 (DMA_CH1_BASE + DMA_BUCR_OFFSET) + +#define IMX_DMA_SAR2 (DMA_CH2_BASE + DMA_SAR_OFFSET) +#define IMX_DMA_DAR2 (DMA_CH2_BASE + DMA_DAR_OFFSET) +#define IMX_DMA_CNTR2 (DMA_CH2_BASE + DMA_CNTR_OFFSET) +#define IMX_DMA_CCR2 (DMA_CH2_BASE + DMA_CCR_OFFSET) +#define IMX_DMA_RSSR2 (DMA_CH2_BASE + DMA_RSSR_OFFSET) +#define IMX_DMA_BLR2 (DMA_CH2_BASE + DMA_BLR_OFFSET) +#define IMX_DMA_RTOR2 (DMA_CH2_BASE + DMA_RTOR_OFFSET) +#define IMX_DMA_BUCR2 (DMA_CH2_BASE + DMA_BUCR_OFFSET) + +#define IMX_DMA_SAR3 (DMA_CH3_BASE + DMA_SAR_OFFSET) +#define IMX_DMA_DAR3 (DMA_CH3_BASE + DMA_DAR_OFFSET) +#define IMX_DMA_CNTR3 (DMA_CH3_BASE + DMA_CNTR_OFFSET) +#define IMX_DMA_CCR3 (DMA_CH3_BASE + DMA_CCR_OFFSET) +#define IMX_DMA_RSSR3 (DMA_CH3_BASE + DMA_RSSR_OFFSET) +#define IMX_DMA_BLR3 (DMA_CH3_BASE + DMA_BLR_OFFSET) +#define IMX_DMA_RTOR3 (DMA_CH3_BASE + DMA_RTOR_OFFSET) +#define IMX_DMA_BUCR3 (DMA_CH3_BASE + DMA_BUCR_OFFSET) + +#define IMX_DMA_SAR4 (DMA_CH4_BASE + DMA_SAR_OFFSET) +#define IMX_DMA_DAR4 (DMA_CH4_BASE + DMA_DAR_OFFSET) +#define IMX_DMA_CNTR4 (DMA_CH4_BASE + DMA_CNTR_OFFSET) +#define IMX_DMA_CCR4 (DMA_CH4_BASE + DMA_CCR_OFFSET) +#define IMX_DMA_RSSR4 (DMA_CH4_BASE + DMA_RSSR_OFFSET) +#define IMX_DMA_BLR4 (DMA_CH4_BASE + DMA_BLR_OFFSET) +#define IMX_DMA_RTOR4 (DMA_CH4_BASE + DMA_RTOR_OFFSET) +#define IMX_DMA_BUCR4 (DMA_CH4_BASE + DMA_BUCR_OFFSET) + +#define IMX_DMA_SAR5 (DMA_CH5_BASE + DMA_SAR_OFFSET) +#define IMX_DMA_DAR5 (DMA_CH5_BASE + DMA_DAR_OFFSET) +#define IMX_DMA_CNTR5 (DMA_CH5_BASE + DMA_CNTR_OFFSET) +#define IMX_DMA_CCR5 (DMA_CH5_BASE + DMA_CCR_OFFSET) +#define IMX_DMA_RSSR5 (DMA_CH5_BASE + DMA_RSSR_OFFSET) +#define IMX_DMA_BLR5 (DMA_CH5_BASE + DMA_BLR_OFFSET) +#define IMX_DMA_RTOR5 (DMA_CH5_BASE + DMA_RTOR_OFFSET) +#define IMX_DMA_BUCR5 (DMA_CH5_BASE + DMA_BUCR_OFFSET) + +#define IMX_DMA_SAR6 (DMA_CH6_BASE + DMA_SAR_OFFSET) +#define IMX_DMA_DAR6 (DMA_CH6_BASE + DMA_DAR_OFFSET) +#define IMX_DMA_CNTR6 (DMA_CH6_BASE + DMA_CNTR_OFFSET) +#define IMX_DMA_CCR6 (DMA_CH6_BASE + DMA_CCR_OFFSET) +#define IMX_DMA_RSSR6 (DMA_CH6_BASE + DMA_RSSR_OFFSET) +#define IMX_DMA_BLR6 (DMA_CH6_BASE + DMA_BLR_OFFSET) +#define IMX_DMA_RTOR6 (DMA_CH6_BASE + DMA_RTOR_OFFSET) +#define IMX_DMA_BUCR6 (DMA_CH6_BASE + DMA_BUCR_OFFSET) + +#define IMX_DMA_SAR7 (DMA_CH7_BASE + DMA_SAR_OFFSET) +#define IMX_DMA_DAR7 (DMA_CH7_BASE + DMA_DAR_OFFSET) +#define IMX_DMA_CNTR7 (DMA_CH7_BASE + DMA_CNTR_OFFSET) +#define IMX_DMA_CCR7 (DMA_CH7_BASE + DMA_CCR_OFFSET) +#define IMX_DMA_RSSR7 (DMA_CH7_BASE + DMA_RSSR_OFFSET) +#define IMX_DMA_BLR7 (DMA_CH7_BASE + DMA_BLR_OFFSET) +#define IMX_DMA_RTOR7 (DMA_CH7_BASE + DMA_RTOR_OFFSET) +#define IMX_DMA_BUCR7 (DMA_CH7_BASE + DMA_BUCR_OFFSET) + +#define IMX_DMA_SAR8 (DMA_CH8_BASE + DMA_SAR_OFFSET) +#define IMX_DMA_DAR8 (DMA_CH8_BASE + DMA_DAR_OFFSET) +#define IMX_DMA_CNTR8 (DMA_CH8_BASE + DMA_CNTR_OFFSET) +#define IMX_DMA_CCR8 (DMA_CH8_BASE + DMA_CCR_OFFSET) +#define IMX_DMA_RSSR8 (DMA_CH8_BASE + DMA_RSSR_OFFSET) +#define IMX_DMA_BLR8 (DMA_CH8_BASE + DMA_BLR_OFFSET) +#define IMX_DMA_RTOR8 (DMA_CH8_BASE + DMA_RTOR_OFFSET) +#define IMX_DMA_BUCR8 (DMA_CH8_BASE + DMA_BUCR_OFFSET) + +#define IMX_DMA_SAR9 (DMA_CH9_BASE + DMA_SAR_OFFSET) +#define IMX_DMA_DAR9 (DMA_CH9_BASE + DMA_DAR_OFFSET) +#define IMX_DMA_CNTR9 (DMA_CH9_BASE + DMA_CNTR_OFFSET) +#define IMX_DMA_CCR9 (DMA_CH9_BASE + DMA_CCR_OFFSET) +#define IMX_DMA_RSSR9 (DMA_CH9_BASE + DMA_RSSR_OFFSET) +#define IMX_DMA_BLR9 (DMA_CH9_BASE + DMA_BLR_OFFSET) +#define IMX_DMA_RTOR9 (DMA_CH9_BASE + DMA_RTOR_OFFSET) +#define IMX_DMA_BUCR9 (DMA_CH9_BASE + DMA_BUCR_OFFSET) + +#define IMX_DMA_SAR10 (DMA_CH10_BASE + DMA_SAR_OFFSET) +#define IMX_DMA_DAR10 (DMA_CH10_BASE + DMA_DAR_OFFSET) +#define IMX_DMA_CNTR10 (DMA_CH10_BASE + DMA_CNTR_OFFSET) +#define IMX_DMA_CCR10 (DMA_CH10_BASE + DMA_CCR_OFFSET) +#define IMX_DMA_RSSR10 (DMA_CH10_BASE + DMA_RSSR_OFFSET) +#define IMX_DMA_BLR10 (DMA_CH10_BASE + DMA_BLR_OFFSET) +#define IMX_DMA_RTOR10 (DMA_CH10_BASE + DMA_RTOR_OFFSET) +#define IMX_DMA_BUCR10 (DMA_CH10_BASE + DMA_BUCR_OFFSET) + +#define IMX_DMA_SAR(n) (DMA_CH_BASE(n) + DMA_SAR_OFFSET) +#define IMX_DMA_DAR(n) (DMA_CH_BASE(n) + DMA_DAR_OFFSET) +#define IMX_DMA_CNTR(n) (DMA_CH_BASE(n) + DMA_CNTR_OFFSET) +#define IMX_DMA_CCR(n) (DMA_CH_BASE(n) + DMA_CCR_OFFSET) +#define IMX_DMA_RSSR(n) (DMA_CH_BASE(n) + DMA_RSSR_OFFSET) +#define IMX_DMA_BLR(n) (DMA_CH_BASE(n) + DMA_BLR_OFFSET) +#define IMX_DMA_RTOR(n) (DMA_CH_BASE(n) + DMA_RTOR_OFFSET) +#define IMX_DMA_BUCR(n) (DMA_CH_BASE(n) + DMA_BUCR_OFFSET) + +#define IMX_DMA_TCR (DMA_TST_BASE + DMA_TCR_OFFSET) +#define IMX_DMA_TFIFOA (DMA_TST_BASE + DMA_TFIFOA_OFFSET) +#define IMX_DMA_TDRR (DMA_TST_BASE + DMA_TDRR_OFFSET) +#define IMX_DMA_TDIPR (DMA_TST_BASE + DMA_TDIPR_OFFSET) +#define IMX_DMA_TFIFOB (DMA_TST_BASE + DMA_TFIFOB_OFFSET) + +/* DMA Register Bit Definitions *****************************************************/ + +/************************************************************************************ + * Inline Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_IMX_DMA_H */ diff --git a/nuttx/arch/arm/src/imx/imx_eim.h b/nuttx/arch/arm/src/imx/imx_eim.h index 50849794a..decd54e46 100755 --- a/nuttx/arch/arm/src/imx/imx_eim.h +++ b/nuttx/arch/arm/src/imx/imx_eim.h @@ -1,85 +1,85 @@ -/************************************************************************************
- * arch/arm/src/imx/imx_eim.h
- *
- * Copyright (C) 2009 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_IMX_WIEM_H
-#define __ARCH_ARM_IMX_WIEM_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-/************************************************************************************
- * Definitions
- ************************************************************************************/
-
-/* EIM Register Offsets ************************************************************/
-
-#define EIM_CS0H_OFFSET 0x00
-#define EIM_CS0L_OFFSET 0x04
-#define EIM_CS1H_OFFSET 0x08
-#define EIM_CS1L_OFFSET 0x0c
-#define EIM_CS2H_OFFSET 0x10
-#define EIM_CS2L_OFFSET 0x14
-#define EIM_CS3H_OFFSET 0x18
-#define EIM_CS3L_OFFSET 0x1c
-#define EIM_CS4H_OFFSET 0x20
-#define EIM_CS4L_OFFSET 0x24
-#define EIM_CS5H_OFFSET 0x28
-#define EIM_CS5L_OFFSET 0x2c
-#define EIM_WEIM_OFFSET 0x30
-
-/* EIM Register Addresses ***********************************************************/
-
-#define IMX_EIM_CS0H (EIM_BASE_ADDR + EIM_CS0H_OFFSET)
-#define IMX_EIM_CS0L (EIM_BASE_ADDR + EIM_CS0L_OFFSET)
-#define IMX_EIM_CS1H (EIM_BASE_ADDR + EIM_CS1H_OFFSET)
-#define IMX_EIM_CS1L (EIM_BASE_ADDR + EIM_CS1L_OFFSET)
-#define IMX_EIM_CS2H (EIM_BASE_ADDR + EIM_CS2H_OFFSET)
-#define IMX_EIM_CS2L (EIM_BASE_ADDR + EIM_CS2L_OFFSET)
-#define IMX_EIM_CS3H (EIM_BASE_ADDR + EIM_CS3H_OFFSET)
-#define IMX_EIM_CS3L (EIM_BASE_ADDR + EIM_CS3L_OFFSET)
-#define IMX_EIM_CS4H (EIM_BASE_ADDR + EIM_CS4H_OFFSET)
-#define IMX_EIM_CS4L (EIM_BASE_ADDR + EIM_CS4L_OFFSET)
-#define IMX_EIM_CS5H (EIM_BASE_ADDR + EIM_CS5H_OFFSET)
-#define IMX_EIM_CS5L (EIM_BASE_ADDR + EIM_CS5L_OFFSET)
-#define IMX_EIM_WEIM (EIM_BASE_ADDR + EIM_WEIM_OFFSET)
-
-/* EIM Register Bit Definitions *****************************************************/
-
-/************************************************************************************
- * Inline Functions
- ************************************************************************************/
-
-#endif /* __ARCH_ARM_IMX_EIM_H */
+/************************************************************************************ + * arch/arm/src/imx/imx_eim.h + * + * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_IMX_WIEM_H +#define __ARCH_ARM_IMX_WIEM_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +/************************************************************************************ + * Definitions + ************************************************************************************/ + +/* EIM Register Offsets ************************************************************/ + +#define EIM_CS0H_OFFSET 0x00 +#define EIM_CS0L_OFFSET 0x04 +#define EIM_CS1H_OFFSET 0x08 +#define EIM_CS1L_OFFSET 0x0c +#define EIM_CS2H_OFFSET 0x10 +#define EIM_CS2L_OFFSET 0x14 +#define EIM_CS3H_OFFSET 0x18 +#define EIM_CS3L_OFFSET 0x1c +#define EIM_CS4H_OFFSET 0x20 +#define EIM_CS4L_OFFSET 0x24 +#define EIM_CS5H_OFFSET 0x28 +#define EIM_CS5L_OFFSET 0x2c +#define EIM_WEIM_OFFSET 0x30 + +/* EIM Register Addresses ***********************************************************/ + +#define IMX_EIM_CS0H (EIM_BASE_ADDR + EIM_CS0H_OFFSET) +#define IMX_EIM_CS0L (EIM_BASE_ADDR + EIM_CS0L_OFFSET) +#define IMX_EIM_CS1H (EIM_BASE_ADDR + EIM_CS1H_OFFSET) +#define IMX_EIM_CS1L (EIM_BASE_ADDR + EIM_CS1L_OFFSET) +#define IMX_EIM_CS2H (EIM_BASE_ADDR + EIM_CS2H_OFFSET) +#define IMX_EIM_CS2L (EIM_BASE_ADDR + EIM_CS2L_OFFSET) +#define IMX_EIM_CS3H (EIM_BASE_ADDR + EIM_CS3H_OFFSET) +#define IMX_EIM_CS3L (EIM_BASE_ADDR + EIM_CS3L_OFFSET) +#define IMX_EIM_CS4H (EIM_BASE_ADDR + EIM_CS4H_OFFSET) +#define IMX_EIM_CS4L (EIM_BASE_ADDR + EIM_CS4L_OFFSET) +#define IMX_EIM_CS5H (EIM_BASE_ADDR + EIM_CS5H_OFFSET) +#define IMX_EIM_CS5L (EIM_BASE_ADDR + EIM_CS5L_OFFSET) +#define IMX_EIM_WEIM (EIM_BASE_ADDR + EIM_WEIM_OFFSET) + +/* EIM Register Bit Definitions *****************************************************/ + +/************************************************************************************ + * Inline Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_IMX_EIM_H */ diff --git a/nuttx/arch/arm/src/imx/imx_gpio.c b/nuttx/arch/arm/src/imx/imx_gpio.c index f6099310f..94e87fdfe 100644 --- a/nuttx/arch/arm/src/imx/imx_gpio.c +++ b/nuttx/arch/arm/src/imx/imx_gpio.c @@ -3,7 +3,7 @@ * arch/arm/src/chip/imx_gpio.c * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/imx/imx_gpio.h b/nuttx/arch/arm/src/imx/imx_gpio.h index 26c1c4346..dcdf9c68e 100755 --- a/nuttx/arch/arm/src/imx/imx_gpio.h +++ b/nuttx/arch/arm/src/imx/imx_gpio.h @@ -1,562 +1,562 @@ -/************************************************************************************
- * arch/arm/src/imx/imx_gpio.h
- * arch/arm/src/chip/imx_gpio.h
- *
- * Copyright (C) 2009 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_IMX_GPIO_H
-#define __ARCH_ARM_IMX_GPIO_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#ifndef __ASSEMBLY__
-# include <stdint.h>
-#endif
-#include "up_arch.h" /* getreg32(), putreg32() */
-
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-
-/* GPIO Register Offsets ************************************************************/
-
-#define GPIO_DDIR_OFFSET 0x0000 /* Data Direction Register */
-#define GPIO_OCR1_OFFSET 0x0004 /* Output Configuration Register 1 */
-#define GPIO_OCR2_OFFSET 0x0008 /* Output Configuration Register 2 */
-#define GPIO_ICONFA1_OFFSET 0x000c /* Input Configuration Register A1 */
-#define GPIO_ICONFA2_OFFSET 0x0010 /* Input Configuration Register A2 */
-#define GPIO_ICONFB1_OFFSET 0x0014 /* Input Configuration Register B1 */
-#define GPIO_ICONFB2_OFFSET 0x0018 /* Input Configuration Register B2 */
-#define GPIO_DR_OFFSET 0x001c /* Data Register */
-#define GPIO_GIUS_OFFSET 0x0020 /* GPIO In Use Register */
-#define GPIO_SSR_OFFSET 0x0024 /* Sample Status Register */
-#define GPIO_ICR1_OFFSET 0x0028 /* Interrupt Configuration Register 1 */
-#define GPIO_ICR2_OFFSET 0x002c /* Interrupt Configuration Register 2 */
-#define GPIO_IMR_OFFSET 0x0030 /* Interrupt Mask Register */
-#define GPIO_ISR_OFFSET 0x0034 /* Interrupt Status Register */
-#define GPIO_GPR_OFFSET 0x0038 /* General Purpose Register */
-#define GPIO_SWR_OFFSET 0x003c /* Software Reset Register */
-#define GPIO_PUEN_OFFSET 0x0040 /* Pull_Up Enable Register */
-
-#define GPIO_PTA_OFFSET 0x0000 /* Port A offset */
-#define GPIO_PTB_OFFSET 0x0100 /* Port B offset */
-#define GPIO_PTC_OFFSET 0x0200 /* Port C offset */
-#define GPIO_PTD_OFFSET 0x0300 /* Port D offset */
-
-#define GPIOA 0 /* Port A index */
-#define GPIOB 1 /* Port B index */
-#define GPIOC 2 /* Port C index */
-#define GPIOD 3 /* Port D index */
-#define GPIO_PT_OFFSET(n) (GPIO_PTA_OFFSET + (n)*0x0100)
-
-/* GPIO Register Addresses **********************************************************/
-
-#define IMX_PTA_VBASE (IMX_GPIO_VBASE + GPIO_PTA_OFFSET)
-#define IMX_PTB_VBASE (IMX_GPIO_VBASE + GPIO_PTB_OFFSET)
-#define IMX_PTC_VBASE (IMX_GPIO_VBASE + GPIO_PTC_OFFSET)
-#define IMX_PTD_VBASE (IMX_GPIO_VBASE + GPIO_PTD_OFFSET)
-#define IMX_PT_VBASE(n) (IMX_GPIO_VBASE + GPIO_PT_OFFSET(n))
-
-#define IMX_GPIOA_DDIR (IMX_PTA_VBASE + GPIO_DDIR_OFFSET)
-#define IMX_GPIOA_OCR1 (IMX_PTA_VBASE + GPIO_OCR1_OFFSET)
-#define IMX_GPIOA_OCR2 (IMX_PTA_VBASE + GPIO_OCR2_OFFSET)
-#define IMX_GPIOA_ICONFA1 (IMX_PTA_VBASE + GPIO_ICONFA1_OFFSET)
-#define IMX_GPIOA_ICONFA2 (IMX_PTA_VBASE + GPIO_ICONFA2_OFFSET)
-#define IMX_GPIOA_ICONFB1 (IMX_PTA_VBASE + GPIO_ICONFB1_OFFSET)
-#define IMX_GPIOA_ICONFB2 (IMX_PTA_VBASE + GPIO_ICONFB2_OFFSET)
-#define IMX_GPIOA_DR (IMX_PTA_VBASE + GPIO_DR_OFFSET)
-#define IMX_GPIOA_GIUS (IMX_PTA_VBASE + GPIO_GIUS_OFFSET)
-#define IMX_GPIOA_SSR (IMX_PTA_VBASE + GPIO_SSR_OFFSET)
-#define IMX_GPIOA_ICR1 (IMX_PTA_VBASE + GPIO_ICR1_OFFSET)
-#define IMX_GPIOA_ICR2 (IMX_PTA_VBASE + GPIO_ICR2_OFFSET)
-#define IMX_GPIOA_IMR (IMX_PTA_VBASE + GPIO_IMR_OFFSET)
-#define IMX_GPIOA_ISR (IMX_PTA_VBASE + GPIO_ISR_OFFSET)
-#define IMX_GPIOA_GPR (IMX_PTA_VBASE + GPIO_GPR_OFFSET)
-#define IMX_GPIOA_SWR (IMX_PTA_VBASE + GPIO_SWR_OFFSET)
-#define IMX_GPIOA_PUEN (IMX_PTA_VBASE + GPIO_PUEN_OFFSET)
-
-#define IMX_GPIOB_DDIR (IMX_PTB_VBASE + GPIO_DDIR_OFFSET)
-#define IMX_GPIOB_OCR1 (IMX_PTB_VBASE + GPIO_OCR1_OFFSET)
-#define IMX_GPIOB_OCR2 (IMX_PTB_VBASE + GPIO_OCR2_OFFSET)
-#define IMX_GPIOB_ICONFA1 (IMX_PTB_VBASE + GPIO_ICONFA1_OFFSET)
-#define IMX_GPIOB_ICONFA2 (IMX_PTB_VBASE + GPIO_ICONFA2_OFFSET)
-#define IMX_GPIOB_ICONFB1 (IMX_PTB_VBASE + GPIO_ICONFB1_OFFSET)
-#define IMX_GPIOB_ICONFB2 (IMX_PTB_VBASE + GPIO_ICONFB2_OFFSET)
-#define IMX_GPIOB_DR (IMX_PTB_VBASE + GPIO_DR_OFFSET)
-#define IMX_GPIOB_GIUS (IMX_PTB_VBASE + GPIO_GIUS_OFFSET)
-#define IMX_GPIOB_SSR (IMX_PTB_VBASE + GPIO_SSR_OFFSET)
-#define IMX_GPIOB_ICR1 (IMX_PTB_VBASE + GPIO_ICR1_OFFSET)
-#define IMX_GPIOB_ICR2 (IMX_PTB_VBASE + GPIO_ICR2_OFFSET)
-#define IMX_GPIOB_IMR (IMX_PTB_VBASE + GPIO_IMR_OFFSET)
-#define IMX_GPIOB_ISR (IMX_PTB_VBASE + GPIO_ISR_OFFSET)
-#define IMX_GPIOB_GPR (IMX_PTB_VBASE + GPIO_GPR_OFFSET)
-#define IMX_GPIOB_SWR (IMX_PTB_VBASE + GPIO_SWR_OFFSET)
-#define IMX_GPIOB_PUEN (IMX_PTB_VBASE + GPIO_PUEN_OFFSET)
-
-#define IMX_GPIOC_DDIR (IMX_PTC_VBASE + GPIO_DDIR_OFFSET)
-#define IMX_GPIOC_OCR1 (IMX_PTC_VBASE + GPIO_OCR1_OFFSET)
-#define IMX_GPIOC_OCR2 (IMX_PTC_VBASE + GPIO_OCR2_OFFSET)
-#define IMX_GPIOC_ICONFA1 (IMX_PTC_VBASE + GPIO_ICONFA1_OFFSET)
-#define IMX_GPIOC_ICONFA2 (IMX_PTC_VBASE + GPIO_ICONFA2_OFFSET)
-#define IMX_GPIOC_ICONFB1 (IMX_PTC_VBASE + GPIO_ICONFB1_OFFSET)
-#define IMX_GPIOC_ICONFB2 (IMX_PTC_VBASE + GPIO_ICONFB2_OFFSET)
-#define IMX_GPIOC_DR (IMX_PTC_VBASE + GPIO_DR_OFFSET)
-#define IMX_GPIOC_GIUS (IMX_PTC_VBASE + GPIO_GIUS_OFFSET)
-#define IMX_GPIOC_SSR (IMX_PTC_VBASE + GPIO_SSR_OFFSET)
-#define IMX_GPIOC_ICR1 (IMX_PTC_VBASE + GPIO_ICR1_OFFSET)
-#define IMX_GPIOC_ICR2 (IMX_PTC_VBASE + GPIO_ICR2_OFFSET)
-#define IMX_GPIOC_IMR (IMX_PTC_VBASE + GPIO_IMR_OFFSET)
-#define IMX_GPIOC_ISR (IMX_PTC_VBASE + GPIO_ISR_OFFSET)
-#define IMX_GPIOC_GPR (IMX_PTC_VBASE + GPIO_GPR_OFFSET)
-#define IMX_GPIOC_SWR (IMX_PTC_VBASE + GPIO_SWR_OFFSET)
-#define IMX_GPIOC_PUEN (IMX_PTC_VBASE + GPIO_PUEN_OFFSET)
-
-#define IMX_GPIOD_DDIR (IMX_PTD_VBASE + GPIO_DDIR_OFFSET)
-#define IMX_GPIOD_OCR1 (IMX_PTD_VBASE + GPIO_OCR1_OFFSET)
-#define IMX_GPIOD_OCR2 (IMX_PTD_VBASE + GPIO_OCR2_OFFSET)
-#define IMX_GPIOD_ICONFA1 (IMX_PTD_VBASE + GPIO_ICONFA1_OFFSET)
-#define IMX_GPIOD_ICONFA2 (IMX_PTD_VBASE + GPIO_ICONFA2_OFFSET)
-#define IMX_GPIOD_ICONFB1 (IMX_PTD_VBASE + GPIO_ICONFB1_OFFSET)
-#define IMX_GPIOD_ICONFB2 (IMX_PTD_VBASE + GPIO_ICONFB2_OFFSET)
-#define IMX_GPIOD_DR (IMX_PTD_VBASE + GPIO_DR_OFFSET)
-#define IMX_GPIOD_GIUS (IMX_PTD_VBASE + GPIO_GIUS_OFFSET)
-#define IMX_GPIOD_SSR (IMX_PTD_VBASE + GPIO_SSR_OFFSET)
-#define IMX_GPIOD_ICR1 (IMX_PTD_VBASE + GPIO_ICR1_OFFSET)
-#define IMX_GPIOD_ICR2 (IMX_PTD_VBASE + GPIO_ICR2_OFFSET)
-#define IMX_GPIOD_IMR (IMX_PTD_VBASE + GPIO_IMR_OFFSET)
-#define IMX_GPIOD_ISR (IMX_PTD_VBASE + GPIO_ISR_OFFSET)
-#define IMX_GPIOD_GPR (IMX_PTD_VBASE + GPIO_GPR_OFFSET)
-#define IMX_GPIOD_SWR (IMX_PTD_VBASE + GPIO_SWR_OFFSET)
-#define IMX_GPIOD_PUEN (IMX_PTD_VBASE + GPIO_PUEN_OFFSET)
-
-#define IMX_GPIO_DDIR(n) (IMX_PT_VBASE(n) + GPIO_DDIR_OFFSET)
-#define IMX_GPIO_OCR1(n) (IMX_PT_VBASE(n) + GPIO_OCR1_OFFSET)
-#define IMX_GPIO_OCR2(n) (IMX_PT_VBASE(n) + GPIO_OCR2_OFFSET)
-#define IMX_GPIO_ICONFA1(n) (IMX_PT_VBASE(n) + GPIO_ICONFA1_OFFSET)
-#define IMX_GPIO_ICONFA2(n) (IMX_PT_VBASE(n) + GPIO_ICONFA2_OFFSET)
-#define IMX_GPIO_ICONFB1(n) (IMX_PT_VBASE(n) + GPIO_ICONFB1_OFFSET)
-#define IMX_GPIO_ICONFB2(n) (IMX_PT_VBASE(n) + GPIO_ICONFB2_OFFSET)
-#define IMX_GPIO_DR(n) (IMX_PT_VBASE(n) + GPIO_DR_OFFSET)
-#define IMX_GPIO_GIUS(n) (IMX_PT_VBASE(n) + GPIO_GIUS_OFFSET)
-#define IMX_GPIO_SSR(n) (IMX_PT_VBASE(n) + GPIO_SSR_OFFSET)
-#define IMX_GPIO_ICR1(n) (IMX_PT_VBASE(n) + GPIO_ICR1_OFFSET)
-#define IMX_GPIO_ICR2(n) (IMX_PT_VBASE(n) + GPIO_ICR2_OFFSET)
-#define IMX_GPIO_IMR(n) (IMX_PT_VBASE(n) + GPIO_IMR_OFFSET)
-#define IMX_GPIO_ISR(n) (IMX_PT_VBASE(n) + GPIO_ISR_OFFSET)
-#define IMX_GPIO_GPR(n) (IMX_PT_VBASE(n) + GPIO_GPR_OFFSET)
-#define IMX_GPIO_SWR(n) (IMX_PT_VBASE(n) + GPIO_SWR_OFFSET)
-#define IMX_GPIO_PUEN(n) (IMX_PT_VBASE(n) + GPIO_PUEN_OFFSET)
-
-/* GPIO Register Bit Definitions ****************************************************/
-
-/************************************************************************************
- * Inline Functions
- ************************************************************************************/
-
-#endif /* __ARCH_ARM_IMX_GPIO_H */
-
-#ifndef __ASSEMBLY__
-
-/* Handler circular include... This file includes up_arch.h, but this file is
- * included by up_arch.h (via chip.h) BEFORE getreg32 is defined.
- */
-
-#if !defined(__ARCH_ARM_IMX_GPIOHELPERS_H) && defined(getreg32)
-#define __ARCH_ARM_IMX_GPIOHELPERS_H
-
-/* Select whether the pin is an input or output */
-
-static inline void imxgpio_dirout(int port, int bit)
-{
- uint32_t regval = getreg32(IMX_GPIO_DDIR(port));
- regval |= (1 << bit);
- putreg32(regval, IMX_GPIO_DDIR(port));
-}
-
-static inline void imxgpio_dirin(int port, int bit)
-{
- uint32_t regval = getreg32(IMX_GPIO_DDIR(port));
- regval &= ~(1 << bit);
- putreg32(regval, IMX_GPIO_DDIR(port));
-}
-
-/* Select input configuration */
-
-static inline void imxgpio_ocrain(int port, int bit)
-{
- uint32_t regval;
- uint32_t regaddr;
- int shift;
-
- if (bit < 16)
- {
- regaddr = IMX_GPIO_OCR1(port);
- shift = (bit << 1);
- }
- else
- {
- regaddr = IMX_GPIO_OCR2(port);
- shift = ((bit - 16) << 1);
- }
-
- regval = getreg32(regaddr);
- regval &= ~(3 << shift);
- putreg32(regval, regaddr);
-}
-
-static inline void imxgpio_ocrbin(int port, int bit)
-{
- uint32_t regval;
- uint32_t regaddr;
- int shift;
-
- if (bit < 16)
- {
- regaddr = IMX_GPIO_OCR1(port);
- shift = (bit << 1);
- }
- else
- {
- regaddr = IMX_GPIO_OCR2(port);
- shift = ((bit - 16) << 1);
- }
-
- regval = getreg32(regaddr);
- regval &= ~(3 << shift);
- regval |= (1 << shift);
- putreg32(regval, regaddr);
-}
-
-static inline void imxgpio_ocrcin(int port, int bit)
-{
- uint32_t regval;
- uint32_t regaddr;
- int shift;
-
- if (bit < 16)
- {
- regaddr = IMX_GPIO_OCR1(port);
- shift = (bit << 1);
- }
- else
- {
- regaddr = IMX_GPIO_OCR2(port);
- shift = ((bit - 16) << 1);
- }
-
- regval = getreg32(regaddr);
- regval &= ~(3 << shift);
- regval |= (2 << shift);
- putreg32(regval, regaddr);
-}
-
-static inline void imxgpio_ocrodrin(int port, int bit)
-{
- uint32_t regval;
- uint32_t regaddr;
- int shift;
-
- if (bit < 16)
- {
- regaddr = IMX_GPIO_OCR1(port);
- shift = (bit << 1);
- }
- else
- {
- regaddr = IMX_GPIO_OCR2(port);
- shift = ((bit - 16) << 1);
- }
-
- regval = getreg32(regaddr);
- regval |= (3 << shift);
- putreg32(regval, regaddr);
-}
-
-/* Input configuration */
-
-static inline void imxgpio_aoutgpio(int port, int bit)
-{
- uint32_t regval;
- uint32_t regaddr;
- int shift;
-
- if (bit < 16)
- {
- regaddr = IMX_GPIO_ICONFA1(port);
- shift = (bit << 1);
- }
- else
- {
- regaddr = IMX_GPIO_ICONFA2(port);
- shift = ((bit - 16) << 1);
- }
-
- regval = getreg32(regaddr);
- regval &= ~(3 << shift);
- putreg32(regval, regaddr);
-}
-
-static inline void imxgpio_aoutisr(int port, int bit)
-{
- uint32_t regval;
- uint32_t regaddr;
- int shift;
-
- if (bit < 16)
- {
- regaddr = IMX_GPIO_ICONFA1(port);
- shift = (bit << 1);
- }
- else
- {
- regaddr = IMX_GPIO_ICONFA2(port);
- shift = ((bit - 16) << 1);
- }
-
- regval = getreg32(regaddr);
- regval &= ~(3 << shift);
- regval |= (1 << shift);
- putreg32(regval, regaddr);
-}
-
-static inline void imxgpio_aout0(int port, int bit)
-{
- uint32_t regval;
- uint32_t regaddr;
- int shift;
-
- if (bit < 16)
- {
- regaddr = IMX_GPIO_ICONFA1(port);
- shift = (bit << 1);
- }
- else
- {
- regaddr = IMX_GPIO_ICONFA2(port);
- shift = ((bit - 16) << 1);
- }
-
- regval = getreg32(regaddr);
- regval &= ~(3 << shift);
- regval |= (2 << shift);
- putreg32(regval, regaddr);
-}
-
-static inline void imxgpio_aout1(int port, int bit)
-{
- uint32_t regval;
- uint32_t regaddr;
- int shift;
-
- if (bit < 16)
- {
- regaddr = IMX_GPIO_ICONFA1(port);
- shift = (bit << 1);
- }
- else
- {
- regaddr = IMX_GPIO_ICONFA2(port);
- shift = ((bit - 16) << 1);
- }
-
- regval = getreg32(regaddr);
- regval |= (3 << shift);
- putreg32(regval, regaddr);
-}
-
-static inline void imxgpio_boutgpio(int port, int bit)
-{
- uint32_t regval;
- uint32_t regaddr;
- int shift;
-
- if (bit < 16)
- {
- regaddr = IMX_GPIO_ICONFB1(port);
- shift = (bit << 1);
- }
- else
- {
- regaddr = IMX_GPIO_ICONFB2(port);
- shift = ((bit - 16) << 1);
- }
-
- regval = getreg32(regaddr);
- regval &= ~(3 << shift);
- putreg32(regval, regaddr);
-}
-
-static inline void imxgpio_boutisr(int port, int bit)
-{
- uint32_t regval;
- uint32_t regaddr;
- int shift;
-
- if (bit < 16)
- {
- regaddr = IMX_GPIO_ICONFB1(port);
- shift = (bit << 1);
- }
- else
- {
- regaddr = IMX_GPIO_ICONFB2(port);
- shift = ((bit - 16) << 1);
- }
-
- regval = getreg32(regaddr);
- regval &= ~(3 << shift);
- regval |= (1 << shift);
- putreg32(regval, regaddr);
-}
-
-static inline void imxgpio_bout0(int port, int bit)
-{
- uint32_t regval;
- uint32_t regaddr;
- int shift;
-
- if (bit < 16)
- {
- regaddr = IMX_GPIO_ICONFB1(port);
- shift = (bit << 1);
- }
- else
- {
- regaddr = IMX_GPIO_ICONFB2(port);
- shift = ((bit - 16) << 1);
- }
-
- regval = getreg32(regaddr);
- regval &= ~(3 << shift);
- regval |= (2 << shift);
- putreg32(regval, regaddr);
-}
-
-static inline void imxgpio_bout1(int port, int bit)
-{
- uint32_t regval;
- uint32_t regaddr;
- int shift;
-
- if (bit < 16)
- {
- regaddr = IMX_GPIO_ICONFB1(port);
- shift = (bit << 1);
- }
- else
- {
- regaddr = IMX_GPIO_ICONFB2(port);
- shift = ((bit - 16) << 1);
- }
-
- regval = getreg32(regaddr);
- regval |= (3 << shift);
- putreg32(regval, regaddr);
-}
-
-/* Select whether the pin is used for its GPIO function or for
- * its peripheral function. Also select the primary or alternate
- * peripheral function.
- */
-
-static inline void imxgpio_gpiofunc(int port, int bit)
-{
- uint32_t regval = getreg32(IMX_GPIO_GIUS(port));
- regval |= (1 << bit);
- putreg32(regval, IMX_GPIO_GIUS(port));
-}
-
-static inline void imxgpio_peripheralfunc(int port, int bit)
-{
- uint32_t regval = getreg32(IMX_GPIO_GIUS(port));
- regval &= ~(1 << bit);
- putreg32(regval, IMX_GPIO_GIUS(port));
-}
-
-static inline void imxgpio_altperipheralfunc(int port, int bit)
-{
- uint32_t regval = getreg32(IMX_GPIO_GPR(port));
- regval |= (1 << bit);
- putreg32(regval, IMX_GPIO_GPR(port));
-}
-
-static inline void imxgpio_primaryperipheralfunc(int port, int bit)
-{
- uint32_t regval = getreg32(IMX_GPIO_GPR(port));
- regval &= ~(1 << bit);
- putreg32(regval, IMX_GPIO_GPR(port));
-}
-
-/* Enable/disable pullups */
-
-static inline void imxgpio_pullupenable(int port, int bit)
-{
- uint32_t regval = getreg32(IMX_GPIO_PUEN(port));
- regval |= (1 << bit);
- putreg32(regval, IMX_GPIO_PUEN(port));
-}
-
-static inline void imxgpio_pullupdisable(int port, int bit)
-{
- uint32_t regval = getreg32(IMX_GPIO_PUEN(port));
- regval &= ~(1 << bit);
- putreg32(regval, IMX_GPIO_PUEN(port));
-}
-
-static inline void imxgpio_setoutput(int port, int bit)
-{
- uint32_t regval = getreg32(IMX_GPIO_DR(port));
- regval |= (1 << bit);
- putreg32(regval, IMX_GPIO_DR(port));
-}
-
-static inline void imxgpio_clroutput(int port, int bit)
-{
- uint32_t regval = getreg32(IMX_GPIO_DR(port));
- regval &= ~(1 << bit);
- putreg32(regval, IMX_GPIO_DR(port));
-}
-
-/* Useful functions for normal configurations */
-
-extern void imxgpio_configoutput(int port, int bit, int value);
-extern void imxgpio_configinput(int port, int bit);
-
-extern void imxgpio_configpfoutput(int port, int bit);
-extern void imxgpio_configpfinput(int port, int bit);
-
-#endif
-
-#endif /* __ARCH_ARM_IMX_GPIOHELPERS_H */
+/************************************************************************************ + * arch/arm/src/imx/imx_gpio.h + * arch/arm/src/chip/imx_gpio.h + * + * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_IMX_GPIO_H +#define __ARCH_ARM_IMX_GPIO_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#ifndef __ASSEMBLY__ +# include <stdint.h> +#endif +#include "up_arch.h" /* getreg32(), putreg32() */ + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* GPIO Register Offsets ************************************************************/ + +#define GPIO_DDIR_OFFSET 0x0000 /* Data Direction Register */ +#define GPIO_OCR1_OFFSET 0x0004 /* Output Configuration Register 1 */ +#define GPIO_OCR2_OFFSET 0x0008 /* Output Configuration Register 2 */ +#define GPIO_ICONFA1_OFFSET 0x000c /* Input Configuration Register A1 */ +#define GPIO_ICONFA2_OFFSET 0x0010 /* Input Configuration Register A2 */ +#define GPIO_ICONFB1_OFFSET 0x0014 /* Input Configuration Register B1 */ +#define GPIO_ICONFB2_OFFSET 0x0018 /* Input Configuration Register B2 */ +#define GPIO_DR_OFFSET 0x001c /* Data Register */ +#define GPIO_GIUS_OFFSET 0x0020 /* GPIO In Use Register */ +#define GPIO_SSR_OFFSET 0x0024 /* Sample Status Register */ +#define GPIO_ICR1_OFFSET 0x0028 /* Interrupt Configuration Register 1 */ +#define GPIO_ICR2_OFFSET 0x002c /* Interrupt Configuration Register 2 */ +#define GPIO_IMR_OFFSET 0x0030 /* Interrupt Mask Register */ +#define GPIO_ISR_OFFSET 0x0034 /* Interrupt Status Register */ +#define GPIO_GPR_OFFSET 0x0038 /* General Purpose Register */ +#define GPIO_SWR_OFFSET 0x003c /* Software Reset Register */ +#define GPIO_PUEN_OFFSET 0x0040 /* Pull_Up Enable Register */ + +#define GPIO_PTA_OFFSET 0x0000 /* Port A offset */ +#define GPIO_PTB_OFFSET 0x0100 /* Port B offset */ +#define GPIO_PTC_OFFSET 0x0200 /* Port C offset */ +#define GPIO_PTD_OFFSET 0x0300 /* Port D offset */ + +#define GPIOA 0 /* Port A index */ +#define GPIOB 1 /* Port B index */ +#define GPIOC 2 /* Port C index */ +#define GPIOD 3 /* Port D index */ +#define GPIO_PT_OFFSET(n) (GPIO_PTA_OFFSET + (n)*0x0100) + +/* GPIO Register Addresses **********************************************************/ + +#define IMX_PTA_VBASE (IMX_GPIO_VBASE + GPIO_PTA_OFFSET) +#define IMX_PTB_VBASE (IMX_GPIO_VBASE + GPIO_PTB_OFFSET) +#define IMX_PTC_VBASE (IMX_GPIO_VBASE + GPIO_PTC_OFFSET) +#define IMX_PTD_VBASE (IMX_GPIO_VBASE + GPIO_PTD_OFFSET) +#define IMX_PT_VBASE(n) (IMX_GPIO_VBASE + GPIO_PT_OFFSET(n)) + +#define IMX_GPIOA_DDIR (IMX_PTA_VBASE + GPIO_DDIR_OFFSET) +#define IMX_GPIOA_OCR1 (IMX_PTA_VBASE + GPIO_OCR1_OFFSET) +#define IMX_GPIOA_OCR2 (IMX_PTA_VBASE + GPIO_OCR2_OFFSET) +#define IMX_GPIOA_ICONFA1 (IMX_PTA_VBASE + GPIO_ICONFA1_OFFSET) +#define IMX_GPIOA_ICONFA2 (IMX_PTA_VBASE + GPIO_ICONFA2_OFFSET) +#define IMX_GPIOA_ICONFB1 (IMX_PTA_VBASE + GPIO_ICONFB1_OFFSET) +#define IMX_GPIOA_ICONFB2 (IMX_PTA_VBASE + GPIO_ICONFB2_OFFSET) +#define IMX_GPIOA_DR (IMX_PTA_VBASE + GPIO_DR_OFFSET) +#define IMX_GPIOA_GIUS (IMX_PTA_VBASE + GPIO_GIUS_OFFSET) +#define IMX_GPIOA_SSR (IMX_PTA_VBASE + GPIO_SSR_OFFSET) +#define IMX_GPIOA_ICR1 (IMX_PTA_VBASE + GPIO_ICR1_OFFSET) +#define IMX_GPIOA_ICR2 (IMX_PTA_VBASE + GPIO_ICR2_OFFSET) +#define IMX_GPIOA_IMR (IMX_PTA_VBASE + GPIO_IMR_OFFSET) +#define IMX_GPIOA_ISR (IMX_PTA_VBASE + GPIO_ISR_OFFSET) +#define IMX_GPIOA_GPR (IMX_PTA_VBASE + GPIO_GPR_OFFSET) +#define IMX_GPIOA_SWR (IMX_PTA_VBASE + GPIO_SWR_OFFSET) +#define IMX_GPIOA_PUEN (IMX_PTA_VBASE + GPIO_PUEN_OFFSET) + +#define IMX_GPIOB_DDIR (IMX_PTB_VBASE + GPIO_DDIR_OFFSET) +#define IMX_GPIOB_OCR1 (IMX_PTB_VBASE + GPIO_OCR1_OFFSET) +#define IMX_GPIOB_OCR2 (IMX_PTB_VBASE + GPIO_OCR2_OFFSET) +#define IMX_GPIOB_ICONFA1 (IMX_PTB_VBASE + GPIO_ICONFA1_OFFSET) +#define IMX_GPIOB_ICONFA2 (IMX_PTB_VBASE + GPIO_ICONFA2_OFFSET) +#define IMX_GPIOB_ICONFB1 (IMX_PTB_VBASE + GPIO_ICONFB1_OFFSET) +#define IMX_GPIOB_ICONFB2 (IMX_PTB_VBASE + GPIO_ICONFB2_OFFSET) +#define IMX_GPIOB_DR (IMX_PTB_VBASE + GPIO_DR_OFFSET) +#define IMX_GPIOB_GIUS (IMX_PTB_VBASE + GPIO_GIUS_OFFSET) +#define IMX_GPIOB_SSR (IMX_PTB_VBASE + GPIO_SSR_OFFSET) +#define IMX_GPIOB_ICR1 (IMX_PTB_VBASE + GPIO_ICR1_OFFSET) +#define IMX_GPIOB_ICR2 (IMX_PTB_VBASE + GPIO_ICR2_OFFSET) +#define IMX_GPIOB_IMR (IMX_PTB_VBASE + GPIO_IMR_OFFSET) +#define IMX_GPIOB_ISR (IMX_PTB_VBASE + GPIO_ISR_OFFSET) +#define IMX_GPIOB_GPR (IMX_PTB_VBASE + GPIO_GPR_OFFSET) +#define IMX_GPIOB_SWR (IMX_PTB_VBASE + GPIO_SWR_OFFSET) +#define IMX_GPIOB_PUEN (IMX_PTB_VBASE + GPIO_PUEN_OFFSET) + +#define IMX_GPIOC_DDIR (IMX_PTC_VBASE + GPIO_DDIR_OFFSET) +#define IMX_GPIOC_OCR1 (IMX_PTC_VBASE + GPIO_OCR1_OFFSET) +#define IMX_GPIOC_OCR2 (IMX_PTC_VBASE + GPIO_OCR2_OFFSET) +#define IMX_GPIOC_ICONFA1 (IMX_PTC_VBASE + GPIO_ICONFA1_OFFSET) +#define IMX_GPIOC_ICONFA2 (IMX_PTC_VBASE + GPIO_ICONFA2_OFFSET) +#define IMX_GPIOC_ICONFB1 (IMX_PTC_VBASE + GPIO_ICONFB1_OFFSET) +#define IMX_GPIOC_ICONFB2 (IMX_PTC_VBASE + GPIO_ICONFB2_OFFSET) +#define IMX_GPIOC_DR (IMX_PTC_VBASE + GPIO_DR_OFFSET) +#define IMX_GPIOC_GIUS (IMX_PTC_VBASE + GPIO_GIUS_OFFSET) +#define IMX_GPIOC_SSR (IMX_PTC_VBASE + GPIO_SSR_OFFSET) +#define IMX_GPIOC_ICR1 (IMX_PTC_VBASE + GPIO_ICR1_OFFSET) +#define IMX_GPIOC_ICR2 (IMX_PTC_VBASE + GPIO_ICR2_OFFSET) +#define IMX_GPIOC_IMR (IMX_PTC_VBASE + GPIO_IMR_OFFSET) +#define IMX_GPIOC_ISR (IMX_PTC_VBASE + GPIO_ISR_OFFSET) +#define IMX_GPIOC_GPR (IMX_PTC_VBASE + GPIO_GPR_OFFSET) +#define IMX_GPIOC_SWR (IMX_PTC_VBASE + GPIO_SWR_OFFSET) +#define IMX_GPIOC_PUEN (IMX_PTC_VBASE + GPIO_PUEN_OFFSET) + +#define IMX_GPIOD_DDIR (IMX_PTD_VBASE + GPIO_DDIR_OFFSET) +#define IMX_GPIOD_OCR1 (IMX_PTD_VBASE + GPIO_OCR1_OFFSET) +#define IMX_GPIOD_OCR2 (IMX_PTD_VBASE + GPIO_OCR2_OFFSET) +#define IMX_GPIOD_ICONFA1 (IMX_PTD_VBASE + GPIO_ICONFA1_OFFSET) +#define IMX_GPIOD_ICONFA2 (IMX_PTD_VBASE + GPIO_ICONFA2_OFFSET) +#define IMX_GPIOD_ICONFB1 (IMX_PTD_VBASE + GPIO_ICONFB1_OFFSET) +#define IMX_GPIOD_ICONFB2 (IMX_PTD_VBASE + GPIO_ICONFB2_OFFSET) +#define IMX_GPIOD_DR (IMX_PTD_VBASE + GPIO_DR_OFFSET) +#define IMX_GPIOD_GIUS (IMX_PTD_VBASE + GPIO_GIUS_OFFSET) +#define IMX_GPIOD_SSR (IMX_PTD_VBASE + GPIO_SSR_OFFSET) +#define IMX_GPIOD_ICR1 (IMX_PTD_VBASE + GPIO_ICR1_OFFSET) +#define IMX_GPIOD_ICR2 (IMX_PTD_VBASE + GPIO_ICR2_OFFSET) +#define IMX_GPIOD_IMR (IMX_PTD_VBASE + GPIO_IMR_OFFSET) +#define IMX_GPIOD_ISR (IMX_PTD_VBASE + GPIO_ISR_OFFSET) +#define IMX_GPIOD_GPR (IMX_PTD_VBASE + GPIO_GPR_OFFSET) +#define IMX_GPIOD_SWR (IMX_PTD_VBASE + GPIO_SWR_OFFSET) +#define IMX_GPIOD_PUEN (IMX_PTD_VBASE + GPIO_PUEN_OFFSET) + +#define IMX_GPIO_DDIR(n) (IMX_PT_VBASE(n) + GPIO_DDIR_OFFSET) +#define IMX_GPIO_OCR1(n) (IMX_PT_VBASE(n) + GPIO_OCR1_OFFSET) +#define IMX_GPIO_OCR2(n) (IMX_PT_VBASE(n) + GPIO_OCR2_OFFSET) +#define IMX_GPIO_ICONFA1(n) (IMX_PT_VBASE(n) + GPIO_ICONFA1_OFFSET) +#define IMX_GPIO_ICONFA2(n) (IMX_PT_VBASE(n) + GPIO_ICONFA2_OFFSET) +#define IMX_GPIO_ICONFB1(n) (IMX_PT_VBASE(n) + GPIO_ICONFB1_OFFSET) +#define IMX_GPIO_ICONFB2(n) (IMX_PT_VBASE(n) + GPIO_ICONFB2_OFFSET) +#define IMX_GPIO_DR(n) (IMX_PT_VBASE(n) + GPIO_DR_OFFSET) +#define IMX_GPIO_GIUS(n) (IMX_PT_VBASE(n) + GPIO_GIUS_OFFSET) +#define IMX_GPIO_SSR(n) (IMX_PT_VBASE(n) + GPIO_SSR_OFFSET) +#define IMX_GPIO_ICR1(n) (IMX_PT_VBASE(n) + GPIO_ICR1_OFFSET) +#define IMX_GPIO_ICR2(n) (IMX_PT_VBASE(n) + GPIO_ICR2_OFFSET) +#define IMX_GPIO_IMR(n) (IMX_PT_VBASE(n) + GPIO_IMR_OFFSET) +#define IMX_GPIO_ISR(n) (IMX_PT_VBASE(n) + GPIO_ISR_OFFSET) +#define IMX_GPIO_GPR(n) (IMX_PT_VBASE(n) + GPIO_GPR_OFFSET) +#define IMX_GPIO_SWR(n) (IMX_PT_VBASE(n) + GPIO_SWR_OFFSET) +#define IMX_GPIO_PUEN(n) (IMX_PT_VBASE(n) + GPIO_PUEN_OFFSET) + +/* GPIO Register Bit Definitions ****************************************************/ + +/************************************************************************************ + * Inline Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_IMX_GPIO_H */ + +#ifndef __ASSEMBLY__ + +/* Handler circular include... This file includes up_arch.h, but this file is + * included by up_arch.h (via chip.h) BEFORE getreg32 is defined. + */ + +#if !defined(__ARCH_ARM_IMX_GPIOHELPERS_H) && defined(getreg32) +#define __ARCH_ARM_IMX_GPIOHELPERS_H + +/* Select whether the pin is an input or output */ + +static inline void imxgpio_dirout(int port, int bit) +{ + uint32_t regval = getreg32(IMX_GPIO_DDIR(port)); + regval |= (1 << bit); + putreg32(regval, IMX_GPIO_DDIR(port)); +} + +static inline void imxgpio_dirin(int port, int bit) +{ + uint32_t regval = getreg32(IMX_GPIO_DDIR(port)); + regval &= ~(1 << bit); + putreg32(regval, IMX_GPIO_DDIR(port)); +} + +/* Select input configuration */ + +static inline void imxgpio_ocrain(int port, int bit) +{ + uint32_t regval; + uint32_t regaddr; + int shift; + + if (bit < 16) + { + regaddr = IMX_GPIO_OCR1(port); + shift = (bit << 1); + } + else + { + regaddr = IMX_GPIO_OCR2(port); + shift = ((bit - 16) << 1); + } + + regval = getreg32(regaddr); + regval &= ~(3 << shift); + putreg32(regval, regaddr); +} + +static inline void imxgpio_ocrbin(int port, int bit) +{ + uint32_t regval; + uint32_t regaddr; + int shift; + + if (bit < 16) + { + regaddr = IMX_GPIO_OCR1(port); + shift = (bit << 1); + } + else + { + regaddr = IMX_GPIO_OCR2(port); + shift = ((bit - 16) << 1); + } + + regval = getreg32(regaddr); + regval &= ~(3 << shift); + regval |= (1 << shift); + putreg32(regval, regaddr); +} + +static inline void imxgpio_ocrcin(int port, int bit) +{ + uint32_t regval; + uint32_t regaddr; + int shift; + + if (bit < 16) + { + regaddr = IMX_GPIO_OCR1(port); + shift = (bit << 1); + } + else + { + regaddr = IMX_GPIO_OCR2(port); + shift = ((bit - 16) << 1); + } + + regval = getreg32(regaddr); + regval &= ~(3 << shift); + regval |= (2 << shift); + putreg32(regval, regaddr); +} + +static inline void imxgpio_ocrodrin(int port, int bit) +{ + uint32_t regval; + uint32_t regaddr; + int shift; + + if (bit < 16) + { + regaddr = IMX_GPIO_OCR1(port); + shift = (bit << 1); + } + else + { + regaddr = IMX_GPIO_OCR2(port); + shift = ((bit - 16) << 1); + } + + regval = getreg32(regaddr); + regval |= (3 << shift); + putreg32(regval, regaddr); +} + +/* Input configuration */ + +static inline void imxgpio_aoutgpio(int port, int bit) +{ + uint32_t regval; + uint32_t regaddr; + int shift; + + if (bit < 16) + { + regaddr = IMX_GPIO_ICONFA1(port); + shift = (bit << 1); + } + else + { + regaddr = IMX_GPIO_ICONFA2(port); + shift = ((bit - 16) << 1); + } + + regval = getreg32(regaddr); + regval &= ~(3 << shift); + putreg32(regval, regaddr); +} + +static inline void imxgpio_aoutisr(int port, int bit) +{ + uint32_t regval; + uint32_t regaddr; + int shift; + + if (bit < 16) + { + regaddr = IMX_GPIO_ICONFA1(port); + shift = (bit << 1); + } + else + { + regaddr = IMX_GPIO_ICONFA2(port); + shift = ((bit - 16) << 1); + } + + regval = getreg32(regaddr); + regval &= ~(3 << shift); + regval |= (1 << shift); + putreg32(regval, regaddr); +} + +static inline void imxgpio_aout0(int port, int bit) +{ + uint32_t regval; + uint32_t regaddr; + int shift; + + if (bit < 16) + { + regaddr = IMX_GPIO_ICONFA1(port); + shift = (bit << 1); + } + else + { + regaddr = IMX_GPIO_ICONFA2(port); + shift = ((bit - 16) << 1); + } + + regval = getreg32(regaddr); + regval &= ~(3 << shift); + regval |= (2 << shift); + putreg32(regval, regaddr); +} + +static inline void imxgpio_aout1(int port, int bit) +{ + uint32_t regval; + uint32_t regaddr; + int shift; + + if (bit < 16) + { + regaddr = IMX_GPIO_ICONFA1(port); + shift = (bit << 1); + } + else + { + regaddr = IMX_GPIO_ICONFA2(port); + shift = ((bit - 16) << 1); + } + + regval = getreg32(regaddr); + regval |= (3 << shift); + putreg32(regval, regaddr); +} + +static inline void imxgpio_boutgpio(int port, int bit) +{ + uint32_t regval; + uint32_t regaddr; + int shift; + + if (bit < 16) + { + regaddr = IMX_GPIO_ICONFB1(port); + shift = (bit << 1); + } + else + { + regaddr = IMX_GPIO_ICONFB2(port); + shift = ((bit - 16) << 1); + } + + regval = getreg32(regaddr); + regval &= ~(3 << shift); + putreg32(regval, regaddr); +} + +static inline void imxgpio_boutisr(int port, int bit) +{ + uint32_t regval; + uint32_t regaddr; + int shift; + + if (bit < 16) + { + regaddr = IMX_GPIO_ICONFB1(port); + shift = (bit << 1); + } + else + { + regaddr = IMX_GPIO_ICONFB2(port); + shift = ((bit - 16) << 1); + } + + regval = getreg32(regaddr); + regval &= ~(3 << shift); + regval |= (1 << shift); + putreg32(regval, regaddr); +} + +static inline void imxgpio_bout0(int port, int bit) +{ + uint32_t regval; + uint32_t regaddr; + int shift; + + if (bit < 16) + { + regaddr = IMX_GPIO_ICONFB1(port); + shift = (bit << 1); + } + else + { + regaddr = IMX_GPIO_ICONFB2(port); + shift = ((bit - 16) << 1); + } + + regval = getreg32(regaddr); + regval &= ~(3 << shift); + regval |= (2 << shift); + putreg32(regval, regaddr); +} + +static inline void imxgpio_bout1(int port, int bit) +{ + uint32_t regval; + uint32_t regaddr; + int shift; + + if (bit < 16) + { + regaddr = IMX_GPIO_ICONFB1(port); + shift = (bit << 1); + } + else + { + regaddr = IMX_GPIO_ICONFB2(port); + shift = ((bit - 16) << 1); + } + + regval = getreg32(regaddr); + regval |= (3 << shift); + putreg32(regval, regaddr); +} + +/* Select whether the pin is used for its GPIO function or for + * its peripheral function. Also select the primary or alternate + * peripheral function. + */ + +static inline void imxgpio_gpiofunc(int port, int bit) +{ + uint32_t regval = getreg32(IMX_GPIO_GIUS(port)); + regval |= (1 << bit); + putreg32(regval, IMX_GPIO_GIUS(port)); +} + +static inline void imxgpio_peripheralfunc(int port, int bit) +{ + uint32_t regval = getreg32(IMX_GPIO_GIUS(port)); + regval &= ~(1 << bit); + putreg32(regval, IMX_GPIO_GIUS(port)); +} + +static inline void imxgpio_altperipheralfunc(int port, int bit) +{ + uint32_t regval = getreg32(IMX_GPIO_GPR(port)); + regval |= (1 << bit); + putreg32(regval, IMX_GPIO_GPR(port)); +} + +static inline void imxgpio_primaryperipheralfunc(int port, int bit) +{ + uint32_t regval = getreg32(IMX_GPIO_GPR(port)); + regval &= ~(1 << bit); + putreg32(regval, IMX_GPIO_GPR(port)); +} + +/* Enable/disable pullups */ + +static inline void imxgpio_pullupenable(int port, int bit) +{ + uint32_t regval = getreg32(IMX_GPIO_PUEN(port)); + regval |= (1 << bit); + putreg32(regval, IMX_GPIO_PUEN(port)); +} + +static inline void imxgpio_pullupdisable(int port, int bit) +{ + uint32_t regval = getreg32(IMX_GPIO_PUEN(port)); + regval &= ~(1 << bit); + putreg32(regval, IMX_GPIO_PUEN(port)); +} + +static inline void imxgpio_setoutput(int port, int bit) +{ + uint32_t regval = getreg32(IMX_GPIO_DR(port)); + regval |= (1 << bit); + putreg32(regval, IMX_GPIO_DR(port)); +} + +static inline void imxgpio_clroutput(int port, int bit) +{ + uint32_t regval = getreg32(IMX_GPIO_DR(port)); + regval &= ~(1 << bit); + putreg32(regval, IMX_GPIO_DR(port)); +} + +/* Useful functions for normal configurations */ + +extern void imxgpio_configoutput(int port, int bit, int value); +extern void imxgpio_configinput(int port, int bit); + +extern void imxgpio_configpfoutput(int port, int bit); +extern void imxgpio_configpfinput(int port, int bit); + +#endif + +#endif /* __ARCH_ARM_IMX_GPIOHELPERS_H */ diff --git a/nuttx/arch/arm/src/imx/imx_i2c.h b/nuttx/arch/arm/src/imx/imx_i2c.h index b2896b7ee..8b1c065e2 100755 --- a/nuttx/arch/arm/src/imx/imx_i2c.h +++ b/nuttx/arch/arm/src/imx/imx_i2c.h @@ -1,69 +1,69 @@ -/************************************************************************************
- * arch/arm/src/imx/imx_i2c.h
- *
- * Copyright (C) 2009 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_IMX_I2C_H
-#define __ARCH_ARM_IMX_I2C_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-/************************************************************************************
- * Definitions
- ************************************************************************************/
-
-/* I2C Register Offsets *************************************************************/
-
-#define I2C_IADR_OFFSET 0x0000
-#define I2C_IFDR_OFFSET 0x0004
-#define I2C_I2CR_OFFSET 0x0008
-#define I2C_I2SR_OFFSET 0x000c
-#define I2C_I2DR_OFFSET 0x0010
-
-/* I2C Register Addresses ***********************************************************/
-
-#define IMX_I2C_IADR (IMX_I2C_VBASE + I2C_IADR_OFFSET)
-#define IMX_I2C_IFDR (IMX_I2C_VBASE + I2C_IFDR_OFFSET)
-#define IMX_I2C_I2CR (IMX_I2C_VBASE + I2C_I2CR_OFFSET)
-#define IMX_I2C_I2SR (IMX_I2C_VBASE + I2C_I2SR_OFFSET)
-#define IMX_I2C_I2DR (IMX_I2C_VBASE + I2C_I2DR_OFFSET)
-
-/* I2C Register Bit Definitions *****************************************************/
-
-/************************************************************************************
- * Inline Functions
- ************************************************************************************/
-
-#endif /* __ARCH_ARM_IMX_I2C_H */
+/************************************************************************************ + * arch/arm/src/imx/imx_i2c.h + * + * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_IMX_I2C_H +#define __ARCH_ARM_IMX_I2C_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +/************************************************************************************ + * Definitions + ************************************************************************************/ + +/* I2C Register Offsets *************************************************************/ + +#define I2C_IADR_OFFSET 0x0000 +#define I2C_IFDR_OFFSET 0x0004 +#define I2C_I2CR_OFFSET 0x0008 +#define I2C_I2SR_OFFSET 0x000c +#define I2C_I2DR_OFFSET 0x0010 + +/* I2C Register Addresses ***********************************************************/ + +#define IMX_I2C_IADR (IMX_I2C_VBASE + I2C_IADR_OFFSET) +#define IMX_I2C_IFDR (IMX_I2C_VBASE + I2C_IFDR_OFFSET) +#define IMX_I2C_I2CR (IMX_I2C_VBASE + I2C_I2CR_OFFSET) +#define IMX_I2C_I2SR (IMX_I2C_VBASE + I2C_I2SR_OFFSET) +#define IMX_I2C_I2DR (IMX_I2C_VBASE + I2C_I2DR_OFFSET) + +/* I2C Register Bit Definitions *****************************************************/ + +/************************************************************************************ + * Inline Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_IMX_I2C_H */ diff --git a/nuttx/arch/arm/src/imx/imx_irq.c b/nuttx/arch/arm/src/imx/imx_irq.c index 934a60f0b..6715a4ad7 100644 --- a/nuttx/arch/arm/src/imx/imx_irq.c +++ b/nuttx/arch/arm/src/imx/imx_irq.c @@ -3,7 +3,7 @@ * arch/arm/src/chip/imx_irq.c * * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/imx/imx_lowputc.S b/nuttx/arch/arm/src/imx/imx_lowputc.S index c00955622..b0c8163a3 100644 --- a/nuttx/arch/arm/src/imx/imx_lowputc.S +++ b/nuttx/arch/arm/src/imx/imx_lowputc.S @@ -3,7 +3,7 @@ * arch/arm/src/chip/imx_lowputc.S * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/imx/imx_memorymap.h b/nuttx/arch/arm/src/imx/imx_memorymap.h index 7eafc908a..fd23aafc3 100644 --- a/nuttx/arch/arm/src/imx/imx_memorymap.h +++ b/nuttx/arch/arm/src/imx/imx_memorymap.h @@ -2,7 +2,7 @@ * arch/arm/src/imx/imx_memorymap.h * * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/imx/imx_rtc.h b/nuttx/arch/arm/src/imx/imx_rtc.h index 68f684fec..249e7a40d 100755 --- a/nuttx/arch/arm/src/imx/imx_rtc.h +++ b/nuttx/arch/arm/src/imx/imx_rtc.h @@ -1,85 +1,85 @@ -/************************************************************************************
- * arch/arm/src/imx/imx_rtc.h
- *
- * Copyright (C) 2009 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_IMX_RTC_H
-#define __ARCH_ARM_IMX_RTC_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-/************************************************************************************
- * Definitions
- ************************************************************************************/
-
-/* RTC Register Offsets *************************************************************/
-
-#define RTC_HOURMIN_OFFSET 0x0000
-#define RTC_SECOND_OFFSET 0x0004
-#define RTC_ALRM_HM_OFFSET 0x0008
-#define RTC_ALRM_SEC_OFFSET 0x000c
-#define RTC_RTCCTL_OFFSET 0x0010
-#define RTC_RTCISR_OFFSET 0x0014
-#define RTC_RTCIENR_OFFSET 0x0018
-#define RTC_STPWCH_OFFSET 0x001c
-#define RTC_DAYR_OFFSET 0x0020
-#define RTC_DAYALARM_OFFSET 0x0024
-#define RTC_TEST1_OFFSET 0x0028
-#define RTC_TEST2_OFFSET 0x002c
-#define RTC_TEST3_OFFSET 0x0030
-
-/* RTC Register Addresses ***********************************************************/
-
-#define IMX_RTC_HOURMIN (IMX_RTC_VBASE + RTC_HOURMIN_OFFSET)
-#define IMX_RTC_SECOND (IMX_RTC_VBASE + RTC_SECOND_OFFSET)
-#define IMX_RTC_ALRM_HM (IMX_RTC_VBASE + RTC_ALRM_HM_OFFSET)
-#define IMX_RTC_ALRM_SEC (IMX_RTC_VBASE + RTC_ALRM_SEC_OFFSET)
-#define IMX_RTC_RTCCTL (IMX_RTC_VBASE + RTC_RTCCTL_OFFSET)
-#define IMX_RTC_RTCISR (IMX_RTC_VBASE + RTC_RTCISR_OFFSET)
-#define IMX_RTC_RTCIENR (IMX_RTC_VBASE + RTC_RTCIENR_OFFSET)
-#define IMX_RTC_STPWCH (IMX_RTC_VBASE + RTC_STPWCH_OFFSET)
-#define IMX_RTC_DAYR (IMX_RTC_VBASE + RTC_DAYR_OFFSET)
-#define IMX_RTC_DAYALARM (IMX_RTC_VBASE + RTC_DAYALARM_OFFSET)
-#define IMX_RTC_TEST1 (IMX_RTC_VBASE + RTC_TEST1_OFFSET)
-#define IMX_RTC_TEST2 (IMX_RTC_VBASE + RTC_TEST2_OFFSET)
-#define IMX_RTC_TEST3 (IMX_RTC_VBASE + RTC_TEST3_OFFSET)
-
-/* RTC Register Bit Definitions *****************************************************/
-
-/************************************************************************************
- * Inline Functions
- ************************************************************************************/
-
-#endif /* __ARCH_ARM_IMX_RTC_H */
+/************************************************************************************ + * arch/arm/src/imx/imx_rtc.h + * + * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_IMX_RTC_H +#define __ARCH_ARM_IMX_RTC_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +/************************************************************************************ + * Definitions + ************************************************************************************/ + +/* RTC Register Offsets *************************************************************/ + +#define RTC_HOURMIN_OFFSET 0x0000 +#define RTC_SECOND_OFFSET 0x0004 +#define RTC_ALRM_HM_OFFSET 0x0008 +#define RTC_ALRM_SEC_OFFSET 0x000c +#define RTC_RTCCTL_OFFSET 0x0010 +#define RTC_RTCISR_OFFSET 0x0014 +#define RTC_RTCIENR_OFFSET 0x0018 +#define RTC_STPWCH_OFFSET 0x001c +#define RTC_DAYR_OFFSET 0x0020 +#define RTC_DAYALARM_OFFSET 0x0024 +#define RTC_TEST1_OFFSET 0x0028 +#define RTC_TEST2_OFFSET 0x002c +#define RTC_TEST3_OFFSET 0x0030 + +/* RTC Register Addresses ***********************************************************/ + +#define IMX_RTC_HOURMIN (IMX_RTC_VBASE + RTC_HOURMIN_OFFSET) +#define IMX_RTC_SECOND (IMX_RTC_VBASE + RTC_SECOND_OFFSET) +#define IMX_RTC_ALRM_HM (IMX_RTC_VBASE + RTC_ALRM_HM_OFFSET) +#define IMX_RTC_ALRM_SEC (IMX_RTC_VBASE + RTC_ALRM_SEC_OFFSET) +#define IMX_RTC_RTCCTL (IMX_RTC_VBASE + RTC_RTCCTL_OFFSET) +#define IMX_RTC_RTCISR (IMX_RTC_VBASE + RTC_RTCISR_OFFSET) +#define IMX_RTC_RTCIENR (IMX_RTC_VBASE + RTC_RTCIENR_OFFSET) +#define IMX_RTC_STPWCH (IMX_RTC_VBASE + RTC_STPWCH_OFFSET) +#define IMX_RTC_DAYR (IMX_RTC_VBASE + RTC_DAYR_OFFSET) +#define IMX_RTC_DAYALARM (IMX_RTC_VBASE + RTC_DAYALARM_OFFSET) +#define IMX_RTC_TEST1 (IMX_RTC_VBASE + RTC_TEST1_OFFSET) +#define IMX_RTC_TEST2 (IMX_RTC_VBASE + RTC_TEST2_OFFSET) +#define IMX_RTC_TEST3 (IMX_RTC_VBASE + RTC_TEST3_OFFSET) + +/* RTC Register Bit Definitions *****************************************************/ + +/************************************************************************************ + * Inline Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_IMX_RTC_H */ diff --git a/nuttx/arch/arm/src/imx/imx_spi.c b/nuttx/arch/arm/src/imx/imx_spi.c index e07cd5d32..5ee601263 100755 --- a/nuttx/arch/arm/src/imx/imx_spi.c +++ b/nuttx/arch/arm/src/imx/imx_spi.c @@ -2,7 +2,7 @@ * arch/arm/src/imx/imx_spi.c * * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/imx/imx_system.h b/nuttx/arch/arm/src/imx/imx_system.h index a3a4b4c54..ad363f14a 100755 --- a/nuttx/arch/arm/src/imx/imx_system.h +++ b/nuttx/arch/arm/src/imx/imx_system.h @@ -1,187 +1,187 @@ -/************************************************************************************
- * arch/arm/src/imx/imx_system.h
- *
- * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_IMX_SYSTEM_H
-#define __ARCH_ARM_IMX_SYSTEM_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-/************************************************************************************
- * Definitions
- ************************************************************************************/
-
-/* AIPI Register Offsets ************************************************************/
-
-#define AIPI_PSR0_OFFSET 0x0000 /* Peripheral Size Register 0 */
-#define AIPI_PSR1_OFFSET 0x0004 /* Peripheral Size Register 1 */
-#define AIPI_PAR_OFFSET 0x0008 /* Peripheral Access Register */
-
-/* AIPI Register Addresses **********************************************************/
-
-#define IMX_AIPI1_PSR0 (IMX_AIPI1_VBASE + AIPI_PSR0_OFFSET)
-#define IMX_AIPI1_PSR1 (IMX_AIPI1_VBASE + AIPI_PSR1_OFFSET)
-#define IMX_AIPI1_PAR (IMX_AIPI1_VBASE + AIPI_PAR_OFFSET)
-
-#define IMX_AIPI2_PSR0 (IMX_AIP2_VBASE + AIPI_PSR0_OFFSET)
-#define IMX_AIPI2_PSR1 (IMX_AIP2_VBASE + AIPI_PSR1_OFFSET)
-#define IMX_AIPI2_PAR (IMX_AIP2_VBASE + 0xAIPI_PAR_OFFSET)
-
-/* AIPI Register Bit Definitions ****************************************************/
-
-/* PLL Register Offsets *************************************************************/
-
-#define PLL_CSCR_OFFSET 0x0000 /* Clock Source Control Register */
-#define PLL_MPCTL0_OFFSET 0x0004 /* MCU PLL Control Register 0 */
-#define PLL_MPCTL1_OFFSET 0x0008 /* MCU PLL & System Clock Control Register 1 */
-#define PLL_SPCTL0_OFFSET 0x000c /* System PLL Control Register 0 */
-#define PLL_SPCTL1_OFFSET 0x0010 /* System PLL Control Register 1 */
-#define PLL_PCDR_OFFSET 0x0020 /* Peripherial Clock Divider Register */
-
-/* PLL Register Addresses ***********************************************************/
-
-#define IMX_PLL_CSCR (IMX_PLL_VBASE + PLL_CSCR_OFFSET)
-#define IMX_PLL_MPCTL0 (IMX_PLL_VBASE + PLL_MPCTL0_OFFSET)
-#define IMX_PLL_MPCTL1 (IMX_PLL_VBASE + PLL_MPCTL1_OFFSET)
-#define IMX_PLL_SPCTL0 (IMX_PLL_VBASE + PLL_SPCTL0_OFFSET)
-#define IMX_PLL_SPCTL1 (IMX_PLL_VBASE + PLL_SPCTL1_OFFSET)
-#define IMX_PLL_PCDR (IMX_PLL_VBASE + PLL_PCDR_OFFSET)
-
-/* PLL Register Bit Definitions *****************************************************/
-
-#define PLL_CSCR_MPEN (1 << 0) /* Bit 0: 1 = MCU PLL enabled */
-#define PLL_CSCR_SPEN (1 << 1) /* Bit 1: System PLL Enable */
-#define PLL_CSCR_BCLKDIV_SHIFT 10 /* Bits 13–10: BClock Divider */
-#define PLL_CSCR_BCLKDIV_MASK (15 << PLL_CSCR_BCLK_DIV_SHIFT)
-#define PLL_CSCR_PRESC (1 << 15) /* Bit 15: MPU PLL clock prescaler */
-#define PLL_CSCR_SYSTEM_SEL (1 << 16) /* Bit 16: System clock source select */
-#define PLL_CSCR_OSCEN (1 << 17) /* Bit 17: Ext. 16MHz oscillator enable */
-#define PLL_CSCR_CLK16_SEL (1 << 18) /* Bit 18: Select BT ref RFBTCLK16 */
-#define PLL_CSCR_MPLLRESTART (1 << 21) /* Bit 21: MPLL Restart */
-#define PLL_CSCR_SPLLRESTART (1 << 22) /* Bit 22: SPLL Restart */
-#define PLL_CSCR_SDCNT_SHIFT 24 /* Bits 25–24: Shut-Down Control */
-#define PLL_CSCR_SDCNT_MASK (3 << PLL_CSCR_SDCNT_SHIFT)
-#define CSCR_SDCNT_2ndEDGE (1 << PLL_CSCR_SDCNT_SHIFT)
-#define CSCR_SDCNT_3rdEDGE (2 << PLL_CSCR_SDCNT_SHIFT)
-#define CSCR_SDCNT_4thEDGE (3 << PLL_CSCR_SDCNT_SHIFT)
-#define PLL_CSCR_USBDIV_SHIFT 28 /* Bits 28–26: USB Divider */
-#define PLL_CSCR_USBDIV_MASK (7 << PLL_CSCR_USB_DIV_SHIFT)
-#define PLL_CSCR_CLKOSEL_SHIFT 29 /* Bits 31–29: CLKO Select */
-#define PLL_CSCR_CLKOSEL_MASK (7 << PLL_CSCR_CLKOSEL_SHIFT)
-#define CSCR_CLKOSEL_PERCLK1 (0 << PLL_CSCR_CLKOSEL_SHIFT)
-#define CSCR_CLKOSEL_HCLK (1 << PLL_CSCR_CLKOSEL_SHIFT)
-#define CSCR_CLKOSEL_CLK48M (2 << PLL_CSCR_CLKOSEL_SHIFT)
-#define CSCR_CLKOSEL_CLK16M (3 << PLL_CSCR_CLKOSEL_SHIFT)
-#define CSCR_CLKOSEL_PREMCLK (4 << PLL_CSCR_CLKOSEL_SHIFT)
-#define CSCR_CLKOSEL_FCLK (5 << PLL_CSCR_CLKOSEL_SHIFT)
-
-#define PLL_MPCTL0_MFN_SHIFT 0 /* Bits 9–0: Multiplication Factor (Numerator) */
-#define PLL_MPCTL0_MFN_MASK (0x03ff << PLL_MPCTL0_MFN_SHIFT)
-#define PLL_MPCTL0_MFI_SHIFT 10 /* Bits 13–10: Multiplication Factor (Integer) */
-#define PLL_MPCTL0_MFI_MASK (0x0f << PLL_MPCTL0_MFI_SHIFT)
-#define PLL_MPCTL0_MFD_SHIFT 16 /* Bits 25–16: Multiplication Factor (Denominator) */
-#define PLL_MPCTL0_MFD_MASK (0x03ff << PLL_MPCTL0_MFD_SHIFT)
-#define PLL_MPCTL0_PD_SHIFT 26 /* Bits 29–26: Predivider Factor */
-#define PLL_MPCTL0_PD_MASK (0x0f << PLL_MPCTL0_PD_SHIFT
-
-#define PLL_MPCTL1_BRMO (1 << 6) /* Bit 6: Controls the BRM order */
-
-#define PLL_SPCTL0_MFN_SHIFT 0 /* Bits 9–0: Multiplication Factor (Numerator) */
-#define PLL_SPCTL0_MFN_MASK (0x03ff << PLL_SPCTL0_MFN_SHIFT)
-#define PLL_SPCTL0_MFI_SHIFT 10 /* Bits 13–10: Multiplication Factor (Integer) */
-#define PLL_SPCTL0_MFI_MASK (0x0f << PLL_SPCTL0_MFI_SHIFT)
-#define PLL_SPCTL0_MFD_SHIFT 16 /* Bits 25–16: Multiplication Factor (Denominator) */
-#define PLL_SPCTL0_MFD_MASK (0x03ff << PLL_SPCTL0_MFD_SHIFT)
-#define PLL_SPCTL0_PD_SHIFT 26 /* Bits 29–26: Predivider Factor */
-#define PLL_SPCTL0_PD_MASK (0x0f << PLL_SPCTL0_PD_SHIFT)
-
-#define PLL_SPCTL1_BRMO (1 << 6) /* Bit 6: Controls the BRM order */
-#define PLL_SPCTL1_LF (1 << 15) /* Bit 15: Indicates if System PLL is locked */
-
-#define PLL_PCDR_PCLKDIV1_SHIFT 0 /* Bits 3–0: Peripheral Clock Divider 1 */
-#define PLL_PCDR_PCLKDIV1_MASK (0x0f << PLL_PCDR_PCLKDIV1_SHIFT)
-#define PLL_PCDR_PCLKDIV2_SHIFT 4 /* Bits 7–4: Peripheral Clock Divider 2 */
-#define PLL_PCDR_PCLKDIV2_MASK (0x0f << PLL_PCDR_PCLKDIV2_SHIFT)
-#define PLL_PCDR_PCLKDIV3_SHIFT 16 /* Bits 22–16: Peripheral Clock Divider 3 */
-#define PLL_PCDR_PCLKDIV3_MASK (0x7f << PLL_PCDR_PCLKDIV3_SHIFT)
-
-/* PLL Helper Macros ****************************************************************/
-
-/* SC Register Offsets **************************************************************/
-
-#define SC_RSR_OFFSET 0x0000 /* Reset Source Register */
-#define SC_SIDR_OFFSET 0x0004 /* Silicon ID Register */
-#define SC_FMCR_OFFSET 0x0008 /* Function Muxing Control Register */
-#define SC_GPCR_OFFSET 0x000c /* Global Peripheral Control Regiser */
-
-/* SC Register Addresses ************************************************************/
-
-#define IMX_SC_RSR (IMX_SC_VBASE + SC_RSR_OFFSET)
-#define IMX_SC_SIDR (IMX_SC_VBASE + SC_SIDR_OFFSET)
-#define IMX_SC_FMCR (IMX_SC_VBASE + SC_FMCR_OFFSET)
-#define IMX_SC_GPCR (IMX_SC_VBASE + SC_GPCR_OFFSET)
-
-/* SC Register Bit Definitions ******************************************************/
-
-
-#define FMCR_SDCS_SEL (1 << 0) /* Bit 0: 1:CSD0 selected */
-#define FMCR_SDCS1_SEL (1 << 1) /* Bit 1: 1:CSD1 selected */
-#define FMCR_EXT_BREN (1 << 2) /* Bit 2: 1:External bus request enabled */
-#define FMCR_SSI_TXCLKSEL (1 << 3) /* Bit 3: 1:Input from Port B[19] SIM_CLK pin */
-#define FMCR_SSI_TXFSSEL (1 << 4) /* Bit 4: 1:Input from Port B[18] SIM_RST pin */
-#define FMCR_SSI_RXDATSEL (1 << 5) /* Bit 5: 1:Input from Port B[16] SIM_TX pin */
-#define FMCR_SSI_RXCLKSEL (1 << 6) /* Bit 6: 1:Input from Port B[15] SIM_PD pin */
-#define FMCR_SSI_RXFSSEL (1 << 7) /* Bit 7: 1:Input from Port B[14] SIM_SVEN pin */
-#define FMCR_SPI2_RXDSEL (1 << 8) /* Bit 8: 1:Input from SPI2_RXD_1 pin
- * (AOUT of Port D[9]) */
-
-/* SDRAMC Register Offsets **********************************************************/
-
-#define SDRAMC_SDCTL0_OFFSET 0x0000
-#define SDRAMC_SDCTL1_OFFSET 0x0004
-
-/* SDRAMC Register Addresses ********************************************************/
-
-#define IMX_SDRAMC_SDCTL0 (IMX_SDRAMC_VBASE + SDRAMC_SDCTL0_OFFSET)
-#define IMX_SDRAMC_SDCTL1 (IMX_SDRAMC_VBASE + SDRAMC_SDCTL1_OFFSET))
-
-/* SDRAMC Register Bit Definitions **************************************************/
-
-/************************************************************************************
- * Inline Functions
- ************************************************************************************/
-
-#endif /* __ARCH_ARM_IMX_SYSTEM_H */
+/************************************************************************************ + * arch/arm/src/imx/imx_system.h + * + * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_IMX_SYSTEM_H +#define __ARCH_ARM_IMX_SYSTEM_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +/************************************************************************************ + * Definitions + ************************************************************************************/ + +/* AIPI Register Offsets ************************************************************/ + +#define AIPI_PSR0_OFFSET 0x0000 /* Peripheral Size Register 0 */ +#define AIPI_PSR1_OFFSET 0x0004 /* Peripheral Size Register 1 */ +#define AIPI_PAR_OFFSET 0x0008 /* Peripheral Access Register */ + +/* AIPI Register Addresses **********************************************************/ + +#define IMX_AIPI1_PSR0 (IMX_AIPI1_VBASE + AIPI_PSR0_OFFSET) +#define IMX_AIPI1_PSR1 (IMX_AIPI1_VBASE + AIPI_PSR1_OFFSET) +#define IMX_AIPI1_PAR (IMX_AIPI1_VBASE + AIPI_PAR_OFFSET) + +#define IMX_AIPI2_PSR0 (IMX_AIP2_VBASE + AIPI_PSR0_OFFSET) +#define IMX_AIPI2_PSR1 (IMX_AIP2_VBASE + AIPI_PSR1_OFFSET) +#define IMX_AIPI2_PAR (IMX_AIP2_VBASE + 0xAIPI_PAR_OFFSET) + +/* AIPI Register Bit Definitions ****************************************************/ + +/* PLL Register Offsets *************************************************************/ + +#define PLL_CSCR_OFFSET 0x0000 /* Clock Source Control Register */ +#define PLL_MPCTL0_OFFSET 0x0004 /* MCU PLL Control Register 0 */ +#define PLL_MPCTL1_OFFSET 0x0008 /* MCU PLL & System Clock Control Register 1 */ +#define PLL_SPCTL0_OFFSET 0x000c /* System PLL Control Register 0 */ +#define PLL_SPCTL1_OFFSET 0x0010 /* System PLL Control Register 1 */ +#define PLL_PCDR_OFFSET 0x0020 /* Peripherial Clock Divider Register */ + +/* PLL Register Addresses ***********************************************************/ + +#define IMX_PLL_CSCR (IMX_PLL_VBASE + PLL_CSCR_OFFSET) +#define IMX_PLL_MPCTL0 (IMX_PLL_VBASE + PLL_MPCTL0_OFFSET) +#define IMX_PLL_MPCTL1 (IMX_PLL_VBASE + PLL_MPCTL1_OFFSET) +#define IMX_PLL_SPCTL0 (IMX_PLL_VBASE + PLL_SPCTL0_OFFSET) +#define IMX_PLL_SPCTL1 (IMX_PLL_VBASE + PLL_SPCTL1_OFFSET) +#define IMX_PLL_PCDR (IMX_PLL_VBASE + PLL_PCDR_OFFSET) + +/* PLL Register Bit Definitions *****************************************************/ + +#define PLL_CSCR_MPEN (1 << 0) /* Bit 0: 1 = MCU PLL enabled */ +#define PLL_CSCR_SPEN (1 << 1) /* Bit 1: System PLL Enable */ +#define PLL_CSCR_BCLKDIV_SHIFT 10 /* Bits 13–10: BClock Divider */ +#define PLL_CSCR_BCLKDIV_MASK (15 << PLL_CSCR_BCLK_DIV_SHIFT) +#define PLL_CSCR_PRESC (1 << 15) /* Bit 15: MPU PLL clock prescaler */ +#define PLL_CSCR_SYSTEM_SEL (1 << 16) /* Bit 16: System clock source select */ +#define PLL_CSCR_OSCEN (1 << 17) /* Bit 17: Ext. 16MHz oscillator enable */ +#define PLL_CSCR_CLK16_SEL (1 << 18) /* Bit 18: Select BT ref RFBTCLK16 */ +#define PLL_CSCR_MPLLRESTART (1 << 21) /* Bit 21: MPLL Restart */ +#define PLL_CSCR_SPLLRESTART (1 << 22) /* Bit 22: SPLL Restart */ +#define PLL_CSCR_SDCNT_SHIFT 24 /* Bits 25–24: Shut-Down Control */ +#define PLL_CSCR_SDCNT_MASK (3 << PLL_CSCR_SDCNT_SHIFT) +#define CSCR_SDCNT_2ndEDGE (1 << PLL_CSCR_SDCNT_SHIFT) +#define CSCR_SDCNT_3rdEDGE (2 << PLL_CSCR_SDCNT_SHIFT) +#define CSCR_SDCNT_4thEDGE (3 << PLL_CSCR_SDCNT_SHIFT) +#define PLL_CSCR_USBDIV_SHIFT 28 /* Bits 28–26: USB Divider */ +#define PLL_CSCR_USBDIV_MASK (7 << PLL_CSCR_USB_DIV_SHIFT) +#define PLL_CSCR_CLKOSEL_SHIFT 29 /* Bits 31–29: CLKO Select */ +#define PLL_CSCR_CLKOSEL_MASK (7 << PLL_CSCR_CLKOSEL_SHIFT) +#define CSCR_CLKOSEL_PERCLK1 (0 << PLL_CSCR_CLKOSEL_SHIFT) +#define CSCR_CLKOSEL_HCLK (1 << PLL_CSCR_CLKOSEL_SHIFT) +#define CSCR_CLKOSEL_CLK48M (2 << PLL_CSCR_CLKOSEL_SHIFT) +#define CSCR_CLKOSEL_CLK16M (3 << PLL_CSCR_CLKOSEL_SHIFT) +#define CSCR_CLKOSEL_PREMCLK (4 << PLL_CSCR_CLKOSEL_SHIFT) +#define CSCR_CLKOSEL_FCLK (5 << PLL_CSCR_CLKOSEL_SHIFT) + +#define PLL_MPCTL0_MFN_SHIFT 0 /* Bits 9–0: Multiplication Factor (Numerator) */ +#define PLL_MPCTL0_MFN_MASK (0x03ff << PLL_MPCTL0_MFN_SHIFT) +#define PLL_MPCTL0_MFI_SHIFT 10 /* Bits 13–10: Multiplication Factor (Integer) */ +#define PLL_MPCTL0_MFI_MASK (0x0f << PLL_MPCTL0_MFI_SHIFT) +#define PLL_MPCTL0_MFD_SHIFT 16 /* Bits 25–16: Multiplication Factor (Denominator) */ +#define PLL_MPCTL0_MFD_MASK (0x03ff << PLL_MPCTL0_MFD_SHIFT) +#define PLL_MPCTL0_PD_SHIFT 26 /* Bits 29–26: Predivider Factor */ +#define PLL_MPCTL0_PD_MASK (0x0f << PLL_MPCTL0_PD_SHIFT + +#define PLL_MPCTL1_BRMO (1 << 6) /* Bit 6: Controls the BRM order */ + +#define PLL_SPCTL0_MFN_SHIFT 0 /* Bits 9–0: Multiplication Factor (Numerator) */ +#define PLL_SPCTL0_MFN_MASK (0x03ff << PLL_SPCTL0_MFN_SHIFT) +#define PLL_SPCTL0_MFI_SHIFT 10 /* Bits 13–10: Multiplication Factor (Integer) */ +#define PLL_SPCTL0_MFI_MASK (0x0f << PLL_SPCTL0_MFI_SHIFT) +#define PLL_SPCTL0_MFD_SHIFT 16 /* Bits 25–16: Multiplication Factor (Denominator) */ +#define PLL_SPCTL0_MFD_MASK (0x03ff << PLL_SPCTL0_MFD_SHIFT) +#define PLL_SPCTL0_PD_SHIFT 26 /* Bits 29–26: Predivider Factor */ +#define PLL_SPCTL0_PD_MASK (0x0f << PLL_SPCTL0_PD_SHIFT) + +#define PLL_SPCTL1_BRMO (1 << 6) /* Bit 6: Controls the BRM order */ +#define PLL_SPCTL1_LF (1 << 15) /* Bit 15: Indicates if System PLL is locked */ + +#define PLL_PCDR_PCLKDIV1_SHIFT 0 /* Bits 3–0: Peripheral Clock Divider 1 */ +#define PLL_PCDR_PCLKDIV1_MASK (0x0f << PLL_PCDR_PCLKDIV1_SHIFT) +#define PLL_PCDR_PCLKDIV2_SHIFT 4 /* Bits 7–4: Peripheral Clock Divider 2 */ +#define PLL_PCDR_PCLKDIV2_MASK (0x0f << PLL_PCDR_PCLKDIV2_SHIFT) +#define PLL_PCDR_PCLKDIV3_SHIFT 16 /* Bits 22–16: Peripheral Clock Divider 3 */ +#define PLL_PCDR_PCLKDIV3_MASK (0x7f << PLL_PCDR_PCLKDIV3_SHIFT) + +/* PLL Helper Macros ****************************************************************/ + +/* SC Register Offsets **************************************************************/ + +#define SC_RSR_OFFSET 0x0000 /* Reset Source Register */ +#define SC_SIDR_OFFSET 0x0004 /* Silicon ID Register */ +#define SC_FMCR_OFFSET 0x0008 /* Function Muxing Control Register */ +#define SC_GPCR_OFFSET 0x000c /* Global Peripheral Control Regiser */ + +/* SC Register Addresses ************************************************************/ + +#define IMX_SC_RSR (IMX_SC_VBASE + SC_RSR_OFFSET) +#define IMX_SC_SIDR (IMX_SC_VBASE + SC_SIDR_OFFSET) +#define IMX_SC_FMCR (IMX_SC_VBASE + SC_FMCR_OFFSET) +#define IMX_SC_GPCR (IMX_SC_VBASE + SC_GPCR_OFFSET) + +/* SC Register Bit Definitions ******************************************************/ + + +#define FMCR_SDCS_SEL (1 << 0) /* Bit 0: 1:CSD0 selected */ +#define FMCR_SDCS1_SEL (1 << 1) /* Bit 1: 1:CSD1 selected */ +#define FMCR_EXT_BREN (1 << 2) /* Bit 2: 1:External bus request enabled */ +#define FMCR_SSI_TXCLKSEL (1 << 3) /* Bit 3: 1:Input from Port B[19] SIM_CLK pin */ +#define FMCR_SSI_TXFSSEL (1 << 4) /* Bit 4: 1:Input from Port B[18] SIM_RST pin */ +#define FMCR_SSI_RXDATSEL (1 << 5) /* Bit 5: 1:Input from Port B[16] SIM_TX pin */ +#define FMCR_SSI_RXCLKSEL (1 << 6) /* Bit 6: 1:Input from Port B[15] SIM_PD pin */ +#define FMCR_SSI_RXFSSEL (1 << 7) /* Bit 7: 1:Input from Port B[14] SIM_SVEN pin */ +#define FMCR_SPI2_RXDSEL (1 << 8) /* Bit 8: 1:Input from SPI2_RXD_1 pin + * (AOUT of Port D[9]) */ + +/* SDRAMC Register Offsets **********************************************************/ + +#define SDRAMC_SDCTL0_OFFSET 0x0000 +#define SDRAMC_SDCTL1_OFFSET 0x0004 + +/* SDRAMC Register Addresses ********************************************************/ + +#define IMX_SDRAMC_SDCTL0 (IMX_SDRAMC_VBASE + SDRAMC_SDCTL0_OFFSET) +#define IMX_SDRAMC_SDCTL1 (IMX_SDRAMC_VBASE + SDRAMC_SDCTL1_OFFSET)) + +/* SDRAMC Register Bit Definitions **************************************************/ + +/************************************************************************************ + * Inline Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_IMX_SYSTEM_H */ diff --git a/nuttx/arch/arm/src/imx/imx_timer.h b/nuttx/arch/arm/src/imx/imx_timer.h index d923a686d..9d91d3c0d 100644 --- a/nuttx/arch/arm/src/imx/imx_timer.h +++ b/nuttx/arch/arm/src/imx/imx_timer.h @@ -2,7 +2,7 @@ * arch/arm/src/imx/imx_timer.h * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/imx/imx_timerisr.c b/nuttx/arch/arm/src/imx/imx_timerisr.c index 30367e97c..896dc86e5 100644 --- a/nuttx/arch/arm/src/imx/imx_timerisr.c +++ b/nuttx/arch/arm/src/imx/imx_timerisr.c @@ -3,7 +3,7 @@ * arch/arm/src/chip/imx_timerisr.c * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/imx/imx_uart.h b/nuttx/arch/arm/src/imx/imx_uart.h index 89d40f543..5646e83f7 100644 --- a/nuttx/arch/arm/src/imx/imx_uart.h +++ b/nuttx/arch/arm/src/imx/imx_uart.h @@ -2,7 +2,7 @@ * arch/arm/src/imx/imx_uart.h * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/imx/imx_usbd.h b/nuttx/arch/arm/src/imx/imx_usbd.h index be53f2358..8c810cacf 100755 --- a/nuttx/arch/arm/src/imx/imx_usbd.h +++ b/nuttx/arch/arm/src/imx/imx_usbd.h @@ -1,320 +1,320 @@ -/************************************************************************************
- * arch/arm/src/imx/imx_usbd.h
- *
- * Copyright (c) 2009 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_IMX_USBD_H
-#define __ARCH_ARM_IMX_USBD_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-/************************************************************************************
- * Definitions
- ************************************************************************************/
-
-/* USBD Register Offsets ************************************************************/
-
-#define USBD_FRAME_OFFSET 0x0000
-#define USBD_SPEC_OFFSET 0x0004
-#define USBD_STAT_OFFSET 0x0008
-#define USBD_CTRL_OFFSET 0x000c
-#define USBD_DADR_OFFSET 0x0010
-#define USBD_DDAT_OFFSET 0x0014
-#define USBD_INTR_OFFSET 0x0018
-#define USBD_MASK_OFFSET 0x001c
-#define USBD_ENAB_OFFSET 0x0024
-
-#define USBD_EP0_OFFSET 0x0030
-#define USBD_EP1_OFFSET 0x0060
-#define USBD_EP2_OFFSET 0x0090
-#define USBD_EP3_OFFSET 0x00c0
-#define USBD_EP4_OFFSET 0x00f0
-#define USBD_EP5_OFFSET 0x0120
-#define USBD_EP_OFFSET(n) (USBD_EP0_OFFSET + (n)*0x0030)
-
-#define USBD_EP_STAT_OFFSET 0x0000
-#define USBD_EP_INTR_OFFSET 0x0004
-#define USBD_EP_MASK_OFFSET 0x0008
-#define USBD_EP_FDAT_OFFSET 0x000c
-#define USBD_EP_FSTAT_OFFSET 0x0010
-#define USBD_EP_FCTRL_OFFSET 0x0014
-#define USBD_EP_LRFP_OFFSET 0x0018
-#define USBD_EP_LRWP_OFFSET 0x001c
-#define USBD_EP_FALRM_OFFSET 0x0020
-#define USBD_EP_FRDP_OFFSET 0x0024
-#define USBD_EP_FRWP_OFFSET 0x0028
-
-/* USBD Register Addresses **********************************************************/
-
-#define IMX_USBD_FRAME (IMX_USBD_VBASE + USBD_FRAME_OFFSET)
-#define IMX_USBD_SPEC (IMX_USBD_VBASE + USBD_SPEC_OFFSET)
-#define IMX_USBD_STAT (IMX_USBD_VBASE + USBD_STAT_OFFSET)
-#define IMX_USBD_CTRL (IMX_USBD_VBASE + USBD_CTRL_OFFSET)
-#define IMX_USBD_DADR (IMX_USBD_VBASE + USBD_DADR_OFFSET)
-#define IMX_USBD_DDAT (IMX_USBD_VBASE + USBD_DDAT_OFFSET)
-#define IMX_USBD_INTR (IMX_USBD_VBASE + USBD_INTR_OFFSET)
-#define IMX_USBD_MASK (IMX_USBD_VBASE + USBD_MASK_OFFSET)
-#define IMX_USBD_ENAB (IMX_USBD_VBASE + USBD_ENAB_OFFSET)
-
-#define IMX_USBD_EP0_BASE (IMX_USBD_VBASE + USBD_EP0_OFFSET)
-#define IMX_USBD_EP1_BASE (IMX_USBD_VBASE + USBD_EP1_OFFSET)
-#define IMX_USBD_EP2_BASE (IMX_USBD_VBASE + USBD_EP2_OFFSET)
-#define IMX_USBD_EP3_BASE (IMX_USBD_VBASE + USBD_EP3_OFFSET)
-#define IMX_USBD_EP4_BASE (IMX_USBD_VBASE + USBD_EP4_OFFSET)
-#define IMX_USBD_EP5_BASE (IMX_USBD_VBASE + USBD_EP5_OFFSET)
-#define IMX_USBD_EP_BASE(n) (IMX_USBD_VBASE + USBD_EP_OFFSET(n))
-
-#define IMX_USBD_EP0_STAT (IMX_USBD_EP0_BASE + USBD_EP_STAT_OFFSET)
-#define IMX_USBD_EP0_INTR (IMX_USBD_EP0_BASE + USBD_EP_INTR_OFFSET)
-#define IMX_USBD_EP0_MASK (IMX_USBD_EP0_BASE + USBD_EP_MASK_OFFSET)
-#define IMX_USBD_EP0_FDAT (IMX_USBD_EP0_BASE + USBD_EP_FDAT_OFFSET)
-#define IMX_USBD_EP0_FSTAT (IMX_USBD_EP0_BASE + USBD_EP_FSTAT_OFFSET)
-#define IMX_USBD_EP0_FCTRL (IMX_USBD_EP0_BASE + USBD_EP_FCTRL_OFFSET)
-#define IMX_USBD_EP0_LRFP (IMX_USBD_EP0_BASE + USBD_EP_LRFP_OFFSET)
-#define IMX_USBD_EP0_LRWP (IMX_USBD_EP0_BASE + USBD_EP_LRWP_OFFSET)
-#define IMX_USBD_EP0_FALRM (IMX_USBD_EP0_BASE + USBD_EP_FALRM_OFFSET)
-#define IMX_USBD_EP0_FRDP (IMX_USBD_EP0_BASE + USBD_EP_FRDP_OFFSET)
-#define IMX_USBD_EP0_FRWP (IMX_USBD_EP0_BASE + USBD_EP_FRWP_OFFSET)
-
-#define IMX_USBD_EP1_STAT (IMX_USBD_EP1_BASE + USBD_EP_STAT_OFFSET)
-#define IMX_USBD_EP1_INTR (IMX_USBD_EP1_BASE + USBD_EP_INTR_OFFSET)
-#define IMX_USBD_EP1_MASK (IMX_USBD_EP1_BASE + USBD_EP_MASK_OFFSET)
-#define IMX_USBD_EP1_FDAT (IMX_USBD_EP1_BASE + USBD_EP_FDAT_OFFSET)
-#define IMX_USBD_EP1_FSTAT (IMX_USBD_EP1_BASE + USBD_EP_FSTAT_OFFSET)
-#define IMX_USBD_EP1_FCTRL (IMX_USBD_EP1_BASE + USBD_EP_FCTRL_OFFSET)
-#define IMX_USBD_EP1_LRFP (IMX_USBD_EP1_BASE + USBD_EP_LRFP_OFFSET)
-#define IMX_USBD_EP1_LRWP (IMX_USBD_EP1_BASE + USBD_EP_LRWP_OFFSET)
-#define IMX_USBD_EP1_FALRM (IMX_USBD_EP1_BASE + USBD_EP_FALRM_OFFSET)
-#define IMX_USBD_EP1_FRDP (IMX_USBD_EP1_BASE + USBD_EP_FRDP_OFFSET)
-#define IMX_USBD_EP1_FRWP (IMX_USBD_EP1_BASE + USBD_EP_FRWP_OFFSET)
-
-#define IMX_USBD_EP2_STAT (IMX_USBD_EP2_BASE + USBD_EP_STAT_OFFSET)
-#define IMX_USBD_EP2_INTR (IMX_USBD_EP2_BASE + USBD_EP_INTR_OFFSET)
-#define IMX_USBD_EP2_MASK (IMX_USBD_EP2_BASE + USBD_EP_MASK_OFFSET)
-#define IMX_USBD_EP2_FDAT (IMX_USBD_EP2_BASE + USBD_EP_FDAT_OFFSET)
-#define IMX_USBD_EP2_FSTAT (IMX_USBD_EP2_BASE + USBD_EP_FSTAT_OFFSET)
-#define IMX_USBD_EP2_FCTRL (IMX_USBD_EP2_BASE + USBD_EP_FCTRL_OFFSET)
-#define IMX_USBD_EP2_LRFP (IMX_USBD_EP2_BASE + USBD_EP_LRFP_OFFSET)
-#define IMX_USBD_EP2_LRWP (IMX_USBD_EP2_BASE + USBD_EP_LRWP_OFFSET)
-#define IMX_USBD_EP2_FALRM (IMX_USBD_EP2_BASE + USBD_EP_FALRM_OFFSET)
-#define IMX_USBD_EP2_FRDP (IMX_USBD_EP2_BASE + USBD_EP_FRDP_OFFSET)
-#define IMX_USBD_EP2_FRWP (IMX_USBD_EP2_BASE + USBD_EP_FRWP_OFFSET)
-
-#define IMX_USBD_EP3_STAT (IMX_USBD_EP3_BASE + USBD_EP_STAT_OFFSET)
-#define IMX_USBD_EP3_INTR (IMX_USBD_EP3_BASE + USBD_EP_INTR_OFFSET)
-#define IMX_USBD_EP3_MASK (IMX_USBD_EP3_BASE + USBD_EP_MASK_OFFSET)
-#define IMX_USBD_EP3_FDAT (IMX_USBD_EP3_BASE + USBD_EP_FDAT_OFFSET)
-#define IMX_USBD_EP3_FSTAT (IMX_USBD_EP3_BASE + USBD_EP_FSTAT_OFFSET)
-#define IMX_USBD_EP3_FCTRL (IMX_USBD_EP3_BASE + USBD_EP_FCTRL_OFFSET)
-#define IMX_USBD_EP3_LRFP (IMX_USBD_EP3_BASE + USBD_EP_LRFP_OFFSET)
-#define IMX_USBD_EP3_LRWP (IMX_USBD_EP3_BASE + USBD_EP_LRWP_OFFSET)
-#define IMX_USBD_EP3_FALRM (IMX_USBD_EP3_BASE + USBD_EP_FALRM_OFFSET)
-#define IMX_USBD_EP3_FRDP (IMX_USBD_EP3_BASE + USBD_EP_FRDP_OFFSET)
-#define IMX_USBD_EP3_FRWP (IMX_USBD_EP3_BASE + USBD_EP_FRWP_OFFSET)
-
-#define IMX_USBD_EP4_STAT (IMX_USBD_EP4_BASE + USBD_EP_STAT_OFFSET)
-#define IMX_USBD_EP4_INTR (IMX_USBD_EP4_BASE + USBD_EP_INTR_OFFSET)
-#define IMX_USBD_EP4_MASK (IMX_USBD_EP4_BASE + USBD_EP_MASK_OFFSET)
-#define IMX_USBD_EP4_FDAT (IMX_USBD_EP4_BASE + USBD_EP_FDAT_OFFSET)
-#define IMX_USBD_EP4_FSTAT (IMX_USBD_EP4_BASE + USBD_EP_FSTAT_OFFSET)
-#define IMX_USBD_EP4_FCTRL (IMX_USBD_EP4_BASE + USBD_EP_FCTRL_OFFSET)
-#define IMX_USBD_EP4_LRFP (IMX_USBD_EP4_BASE + USBD_EP_LRFP_OFFSET)
-#define IMX_USBD_EP4_LRWP (IMX_USBD_EP4_BASE + USBD_EP_LRWP_OFFSET)
-#define IMX_USBD_EP4_FALRM (IMX_USBD_EP4_BASE + USBD_EP_FALRM_OFFSET)
-#define IMX_USBD_EP4_FRDP (IMX_USBD_EP4_BASE + USBD_EP_FRDP_OFFSET)
-#define IMX_USBD_EP4_FRWP (IMX_USBD_EP4_BASE + USBD_EP_FRWP_OFFSET)
-
-#define IMX_USBD_EP5_STAT (IMX_USBD_EP5_BASE + USBD_EP_STAT_OFFSET)
-#define IMX_USBD_EP5_INTR (IMX_USBD_EP5_BASE + USBD_EP_INTR_OFFSET)
-#define IMX_USBD_EP5_MASK (IMX_USBD_EP5_BASE + USBD_EP_MASK_OFFSET)
-#define IMX_USBD_EP5_FDAT (IMX_USBD_EP5_BASE + USBD_EP_FDAT_OFFSET)
-#define IMX_USBD_EP5_FSTAT (IMX_USBD_EP5_BASE + USBD_EP_FSTAT_OFFSET)
-#define IMX_USBD_EP5_FCTRL (IMX_USBD_EP5_BASE + USBD_EP_FCTRL_OFFSET)
-#define IMX_USBD_EP5_LRFP (IMX_USBD_EP5_BASE + USBD_EP_LRFP_OFFSET)
-#define IMX_USBD_EP5_LRWP (IMX_USBD_EP5_BASE + USBD_EP_LRWP_OFFSET)
-#define IMX_USBD_EP5_FALRM (IMX_USBD_EP5_BASE + USBD_EP_FALRM_OFFSET)
-#define IMX_USBD_EP5_FRDP (IMX_USBD_EP5_BASE + USBD_EP_FRDP_OFFSET)
-#define IMX_USBD_EP5_FRWP (IMX_USBD_EP5_BASE + USBD_EP_FRWP_OFFSET)
-
-#define IMX_USBD_EP_STAT(n) (IMX_USBD_EP_BASE(n) + USBD_EP_STAT_OFFSET)
-#define IMX_USBD_EP_INTR(n) (IMX_USBD_EP_BASE(n) + USBD_EP_INTR_OFFSET)
-#define IMX_USBD_EP_MASK(n) (IMX_USBD_EP_BASE(n) + USBD_EP_MASK_OFFSET)
-#define IMX_USBD_EP_FDAT(n) (IMX_USBD_EP_BASE(n) + USBD_EP_FDAT_OFFSET)
-#define IMX_USBD_EP_FSTAT(n) (IMX_USBD_EP_BASE(n) + USBD_EP_FSTAT_OFFSET)
-#define IMX_USBD_EP_FCTRL(n) (IMX_USBD_EP_BASE(n) + USBD_EP_FCTRL_OFFSET)
-#define IMX_USBD_EP_LRFP(n) (IMX_USBD_EP_BASE(n) + USBD_EP_LRFP_OFFSET)
-#define IMX_USBD_EP_LRWP(n) (IMX_USBD_EP_BASE(n) + USBD_EP_LRWP_OFFSET)
-#define IMX_USBD_EP_FALRM(n) (IMX_USBD_EP_BASE(n) + USBD_EP_FALRM_OFFSET)
-#define IMX_USBD_EP_FRDP(n) (IMX_USBD_EP_BASE(n) + USBD_EP_FRDP_OFFSET)
-#define IMX_USBD_EP_FRWP(n) (IMX_USBD_EP_BASE(n) + USBD_EP_FRWP_OFFSET)
-
-/* USBD Register Bit Definitions ****************************************************/
-
-/* USBD FRAME Register */
-
-#define USBD_FRAME_FRAME_SHIFT 0 /* Bit 0-10: Frame Field */
-#define USBD_FRAME_FRAME_MASK (0x07ff << USBD_FRAME_FRAME_SHIFT)
-#define USBD_FRAME_MATCH_SHIFT 16 /* Bit 16-26: Match Field */
-#define USBD_FRAME_MATCH_MASK (0x07ff << USBD_FRAME_MATCH_SHIFT)
-
-/* USBD STAT Register */
-
-#define USBD_STAT_ALTSET_SHIFT 0 /* Bit 0-2: Alternate Setting */
-#define USBD_STAT_ALTSET_MASK (0x07 << USBD_FRAME_MATCH_SHIFT)
-#define USBD_STAT_INTF_SHIFT 3 /* Bit 3-4: Interface */
-#define USBD_STAT_INTF_MASK (0x03 << USBD_FRAME_MATCH_SHIFT)
-#define USBD_STAT_CFG_SHIFT 5 /* Bit 5-6: Configuration */
-#define USBD_STAT_CFG_MASK (0x03 << USBD_FRAME_MATCH_SHIFT)
-#define USBD_STAT_SUSP (1 << 7) /* Bit 7: Suspend */
-#define USBD_STAT_RST (1 << 8) /* Bit 8: Reset Signaling */
-
-/* USBD CTRL Register */
-
-#define USBD_CTRL_RESUME (1 << 0) /* Bit 0: Resume */
-#define USBD_CTRL_AFEENA (1 << 1) /* Bit 1: Analog Front-End Enable */
-#define USBD_CTRL_UDCRST (1 << 2) /* Bit 2: UDC Reset */
-#define USBD_CTRL_USBENA (1 << 3) /* Bit 3: USB Enable */
-#define USBD_CTRL_USBSPD (1 << 4) /* Bit 4: USB Speed */
-#define USBD_CTRL_CMDERROR (1 << 5) /* Bit 5: Command Error */
-#define USBD_CTRL_CMDOVER (1 << 6) /* Bit 6: Command Over */
-
-/* USBD DADR Register */
-
-#define USBD_DADR_DADR_SHIFT 0 /* Bit 0-8: Desired RAM Address */
-#define USBD_DADR_DADR_MASK (0x1ff << USBD_DADR_DADR_SHIFT)
-#define USBD_DADR_BSY (1 << 30) /* Bit 30: Busy */
-#define USBD_DADR_CFG (1 << 31) /* Bit 31: Configuration */
-
-/* USBD DDAT Register */
-
-#define USBD_DDAT_DDAT_SHIFT 0 /* Bit 0-7: Descriptor Data Buffer */
-#define USBD_DDAT_DDAT_MASK (0xff << USBD_DDAT_DDAT_SHIFT)
-
-/* USBD INTR Register */
-
-#define USBD_INTR_CFGCHG (1 << 0) /* Bit 0: Configuration Change */
-#define USBD_INTR_FRAMEMATCH (1 << 1) /* Bit 1: FRAME_MATCH */
-#define USBD_INTR_SUSP (1 << 2) /* Bit 2: Active to Suspend */
-#define USBD_INTR_RES (1 << 3) /* Bit 3: Suspend to Resume */
-#define USBD_INTR_RESETSTART (1 << 4) /* Bit 4: Restart Signaling Start */
-#define USBD_INTR_RESETSTOP (1 << 5) /* Bit 5: Restart Signaling Stop */
-#define USBD_INTR_SOF (1 << 6) /* Bit 6: Start-of-Frame Interrupt */
-#define USBD_INTR_MSOF (1 << 7) /* Bit 7: Missed Start-of-Frame Interrupt */
-#define USBD_INTR_WAKEUP (1 << 31) /* Bit 31: Wakeup */
-
-/* USBD MASK Register */
-
-#define USBD_MASK_CFGCHG (1 << 0) /* Bit 0: Configuration Change */
-#define USBD_MASK_FRAMEMATCH (1 << 1) /* Bit 1: FRAME_MATCH */
-#define USBD_MASK_SUSP (1 << 2) /* Bit 2: Active to Suspend */
-#define USBD_MASK_RES (1 << 3) /* Bit 3: Suspend to Resume */
-#define USBD_MASK_RESETSTART (1 << 4) /* Bit 4: Restart Signaling Start */
-#define USBD_MASK_RESETSTOP (1 << 5) /* Bit 5: Restart Signaling Stop */
-#define USBD_MASK_SOF (1 << 6) /* Bit 6: Start-of-Frame Interrupt */
-#define USBD_MASK_MSOF (1 << 7) /* Bit 7: Missed Start-of-Frame Interrupt */
-#define USBD_MASK_WAKEUP (1 << 31) /* Bit 31: Wakeup */
-
-/* USBD ENAB Register */
-
-#define USBD_ENAB_PWDMD (1 << 0) /* Bit 0: Power Mode */
-#define USBD_ENAB_ENDIANMODE (1 << 28) /* Bit 28: Endian Mode Select */
-#define USBD_ENAB_SUSPEND (1 << 29) /* Bit 29: Suspend */
-#define USBD_ENAB_ENAB (1 << 30) /* Bit 30: Enable */
-#define USBD_ENAB_RST (1 << 31) /* Bit 31: Reset */
-
-/* USBD EPSTAT Register */
-
-#define USBD_EPSTAT_FORCESTALL (1 << 0) /* Bit 0: Force a Stall Condition */
-#define USBD_EPSTAT_FLUSH (1 << 1) /* Bit 1: Flush */
-#define USBD_EPSTAT_ZLPS (1 << 2) /* Bit 2: Zero Length Packet Send */
-#define USBD_EPSTAT_TYP_SHIFT 3 /* Bit 3-4: Endpoint Type */
-#define USBD_EPSTAT_TYP_MASK (0x03 << USBD_EPSTAT_TYP_SHIFT)
-#define USBD_EPSTAT_MAX_SHIFT 5 /* Bit 5-6: Maximum Packet Size */
-#define USBD_EPSTAT_MAX_MASK (0x03 << USBD_EPSTAT_MAX_SHIFT)
-#define USBD_EPSTAT_DIR (1 << 7) /* Bit 7: Transfer Direction */
-#define USBD_EPSTAT_SIP (1 << 8) /* Bit 8: Setup Packet in Progress */
-#define USBD_EPSTAT_BYTECOUNT_SHIFT 16 /* Bit 16-22: Byte Count */
-#define USBD_EPSTAT_BYTECOUNT_MASK (0x7f << USBD_EPSTAT_BYTECOUNT_SHIFT)
-
-/* USBD EPINTR Register */
-
-#define USBD_EPINTR_EOF (1 << 0) /* Bit 0: End-of-Frame */
-#define USBD_EPINTR_DEVREQ (1 << 1) /* Bit 1: Device Request */
-#define USBD_EPINTR_EOT (1 << 2) /* Bit 2: End of Transfer */
-#define USBD_EPINTR_MDEVREQ (1 << 3) /* Bit 3: Multiple Device Request */
-#define USBD_EPINTR_FIFOLOW (1 << 4) /* Bit 4: FIFO Low */
-#define USBD_EPINTR_FIFOHIGH (1 << 5) /* Bit 5: FIFO High */
-#define USBD_EPINTR_FIFOERROR (1 << 6) /* Bit 6: FIFO Error */
-#define USBD_EPINTR_FIFOEMPTY (1 << 7) /* Bit 7: FIFO Empty */
-#define USBD_EPINTR_FIFOFULL (1 << 8) /* Bit 8: FIFO Full */
-
-/* USBD EPMASK Register */
-
-#define USBD_EPMASK_EOF (1 << 0) /* Bit 0: End-of-Frame */
-#define USBD_EPMASK_DEVREQ (1 << 1) /* Bit 1: Device Request */
-#define USBD_EPMASK_EOT (1 << 2) /* Bit 2: End of Transfer */
-#define USBD_EPMASK_MDEVREQ (1 << 3) /* Bit 3: Multiple Device Request */
-#define USBD_EPMASK_FIFOLOW (1 << 4) /* Bit 4: FIFO Low */
-#define USBD_EPMASK_FIFOHIGH (1 << 5) /* Bit 5: FIFO High */
-#define USBD_EPMASK_FIFOERROR (1 << 6) /* Bit 6: FIFO Error */
-#define USBD_EPMASK_FIFOEMPTY (1 << 7) /* Bit 7: FIFO Empty */
-#define USBD_EPMASK_FIFOFULL (1 << 8) /* Bit 8: FIFO Full */
-
-/* USBD EPFSTAT Register */
-
-#define USBD_EPFSTAT_EMPTY (1 << 16) /* Bit 16: FIFO Empty */
-#define USBD_EPFSTAT_ALARM (1 << 17) /* Bit 17: FIFO Alarm */
-#define USBD_EPFSTAT_FULL (1 << 18) /* Bit 18: FIFO Full */
-#define USBD_EPFSTAT_FR (1 << 19) /* Bit 19: FIFO Ready */
-#define USBD_EPFSTAT_OF (1 << 20) /* Bit 20: FIFO Overflow */
-#define USBD_EPFSTAT_UF (1 << 21) /* Bit 21: FIFO Underflow */
-#define USBD_EPFSTAT_ERROR (1 << 22) /* Bit 22: FIFO Error */
-#define USBD_EPFSTAT_FRAME3 (1 << 24) /* Bit 24: Frame Status Bit 3 */
-#define USBD_EPFSTAT_FRAME2 (1 << 25) /* Bit 25: Frame Status Bit 2 */
-#define USBD_EPFSTAT_FRAME1 (1 << 26) /* Bit 26: Frame Status Bit 1 */
-#define USBD_EPFSTAT_FRAME0 (1 << 27) /* Bit 27: Frame Status Bit 0 */
-
-/* USBD EPFCTRL Register */
-
-#define USBD_EPCTRL_GR_SHIFT 24 /* Bit 24-26: Granularity */
-#define USBD_EPCTRL_GR_MASK (0x07 << USBD_EPCTRL_GR_SHIFT)
-#define USBD_EPCTRL_FRAME (1 << 27) /* Bit 27: Frame Mode */
-#define USBD_EPCTRL_WFR (1 << 28) /* Bit 29: Write Frame End */
-
-/************************************************************************************
- * Inline Functions
- ************************************************************************************/
-
-#endif /* __ARCH_ARM_IMX_USBD_H */
+/************************************************************************************ + * arch/arm/src/imx/imx_usbd.h + * + * Copyright (c) 2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_IMX_USBD_H +#define __ARCH_ARM_IMX_USBD_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +/************************************************************************************ + * Definitions + ************************************************************************************/ + +/* USBD Register Offsets ************************************************************/ + +#define USBD_FRAME_OFFSET 0x0000 +#define USBD_SPEC_OFFSET 0x0004 +#define USBD_STAT_OFFSET 0x0008 +#define USBD_CTRL_OFFSET 0x000c +#define USBD_DADR_OFFSET 0x0010 +#define USBD_DDAT_OFFSET 0x0014 +#define USBD_INTR_OFFSET 0x0018 +#define USBD_MASK_OFFSET 0x001c +#define USBD_ENAB_OFFSET 0x0024 + +#define USBD_EP0_OFFSET 0x0030 +#define USBD_EP1_OFFSET 0x0060 +#define USBD_EP2_OFFSET 0x0090 +#define USBD_EP3_OFFSET 0x00c0 +#define USBD_EP4_OFFSET 0x00f0 +#define USBD_EP5_OFFSET 0x0120 +#define USBD_EP_OFFSET(n) (USBD_EP0_OFFSET + (n)*0x0030) + +#define USBD_EP_STAT_OFFSET 0x0000 +#define USBD_EP_INTR_OFFSET 0x0004 +#define USBD_EP_MASK_OFFSET 0x0008 +#define USBD_EP_FDAT_OFFSET 0x000c +#define USBD_EP_FSTAT_OFFSET 0x0010 +#define USBD_EP_FCTRL_OFFSET 0x0014 +#define USBD_EP_LRFP_OFFSET 0x0018 +#define USBD_EP_LRWP_OFFSET 0x001c +#define USBD_EP_FALRM_OFFSET 0x0020 +#define USBD_EP_FRDP_OFFSET 0x0024 +#define USBD_EP_FRWP_OFFSET 0x0028 + +/* USBD Register Addresses **********************************************************/ + +#define IMX_USBD_FRAME (IMX_USBD_VBASE + USBD_FRAME_OFFSET) +#define IMX_USBD_SPEC (IMX_USBD_VBASE + USBD_SPEC_OFFSET) +#define IMX_USBD_STAT (IMX_USBD_VBASE + USBD_STAT_OFFSET) +#define IMX_USBD_CTRL (IMX_USBD_VBASE + USBD_CTRL_OFFSET) +#define IMX_USBD_DADR (IMX_USBD_VBASE + USBD_DADR_OFFSET) +#define IMX_USBD_DDAT (IMX_USBD_VBASE + USBD_DDAT_OFFSET) +#define IMX_USBD_INTR (IMX_USBD_VBASE + USBD_INTR_OFFSET) +#define IMX_USBD_MASK (IMX_USBD_VBASE + USBD_MASK_OFFSET) +#define IMX_USBD_ENAB (IMX_USBD_VBASE + USBD_ENAB_OFFSET) + +#define IMX_USBD_EP0_BASE (IMX_USBD_VBASE + USBD_EP0_OFFSET) +#define IMX_USBD_EP1_BASE (IMX_USBD_VBASE + USBD_EP1_OFFSET) +#define IMX_USBD_EP2_BASE (IMX_USBD_VBASE + USBD_EP2_OFFSET) +#define IMX_USBD_EP3_BASE (IMX_USBD_VBASE + USBD_EP3_OFFSET) +#define IMX_USBD_EP4_BASE (IMX_USBD_VBASE + USBD_EP4_OFFSET) +#define IMX_USBD_EP5_BASE (IMX_USBD_VBASE + USBD_EP5_OFFSET) +#define IMX_USBD_EP_BASE(n) (IMX_USBD_VBASE + USBD_EP_OFFSET(n)) + +#define IMX_USBD_EP0_STAT (IMX_USBD_EP0_BASE + USBD_EP_STAT_OFFSET) +#define IMX_USBD_EP0_INTR (IMX_USBD_EP0_BASE + USBD_EP_INTR_OFFSET) +#define IMX_USBD_EP0_MASK (IMX_USBD_EP0_BASE + USBD_EP_MASK_OFFSET) +#define IMX_USBD_EP0_FDAT (IMX_USBD_EP0_BASE + USBD_EP_FDAT_OFFSET) +#define IMX_USBD_EP0_FSTAT (IMX_USBD_EP0_BASE + USBD_EP_FSTAT_OFFSET) +#define IMX_USBD_EP0_FCTRL (IMX_USBD_EP0_BASE + USBD_EP_FCTRL_OFFSET) +#define IMX_USBD_EP0_LRFP (IMX_USBD_EP0_BASE + USBD_EP_LRFP_OFFSET) +#define IMX_USBD_EP0_LRWP (IMX_USBD_EP0_BASE + USBD_EP_LRWP_OFFSET) +#define IMX_USBD_EP0_FALRM (IMX_USBD_EP0_BASE + USBD_EP_FALRM_OFFSET) +#define IMX_USBD_EP0_FRDP (IMX_USBD_EP0_BASE + USBD_EP_FRDP_OFFSET) +#define IMX_USBD_EP0_FRWP (IMX_USBD_EP0_BASE + USBD_EP_FRWP_OFFSET) + +#define IMX_USBD_EP1_STAT (IMX_USBD_EP1_BASE + USBD_EP_STAT_OFFSET) +#define IMX_USBD_EP1_INTR (IMX_USBD_EP1_BASE + USBD_EP_INTR_OFFSET) +#define IMX_USBD_EP1_MASK (IMX_USBD_EP1_BASE + USBD_EP_MASK_OFFSET) +#define IMX_USBD_EP1_FDAT (IMX_USBD_EP1_BASE + USBD_EP_FDAT_OFFSET) +#define IMX_USBD_EP1_FSTAT (IMX_USBD_EP1_BASE + USBD_EP_FSTAT_OFFSET) +#define IMX_USBD_EP1_FCTRL (IMX_USBD_EP1_BASE + USBD_EP_FCTRL_OFFSET) +#define IMX_USBD_EP1_LRFP (IMX_USBD_EP1_BASE + USBD_EP_LRFP_OFFSET) +#define IMX_USBD_EP1_LRWP (IMX_USBD_EP1_BASE + USBD_EP_LRWP_OFFSET) +#define IMX_USBD_EP1_FALRM (IMX_USBD_EP1_BASE + USBD_EP_FALRM_OFFSET) +#define IMX_USBD_EP1_FRDP (IMX_USBD_EP1_BASE + USBD_EP_FRDP_OFFSET) +#define IMX_USBD_EP1_FRWP (IMX_USBD_EP1_BASE + USBD_EP_FRWP_OFFSET) + +#define IMX_USBD_EP2_STAT (IMX_USBD_EP2_BASE + USBD_EP_STAT_OFFSET) +#define IMX_USBD_EP2_INTR (IMX_USBD_EP2_BASE + USBD_EP_INTR_OFFSET) +#define IMX_USBD_EP2_MASK (IMX_USBD_EP2_BASE + USBD_EP_MASK_OFFSET) +#define IMX_USBD_EP2_FDAT (IMX_USBD_EP2_BASE + USBD_EP_FDAT_OFFSET) +#define IMX_USBD_EP2_FSTAT (IMX_USBD_EP2_BASE + USBD_EP_FSTAT_OFFSET) +#define IMX_USBD_EP2_FCTRL (IMX_USBD_EP2_BASE + USBD_EP_FCTRL_OFFSET) +#define IMX_USBD_EP2_LRFP (IMX_USBD_EP2_BASE + USBD_EP_LRFP_OFFSET) +#define IMX_USBD_EP2_LRWP (IMX_USBD_EP2_BASE + USBD_EP_LRWP_OFFSET) +#define IMX_USBD_EP2_FALRM (IMX_USBD_EP2_BASE + USBD_EP_FALRM_OFFSET) +#define IMX_USBD_EP2_FRDP (IMX_USBD_EP2_BASE + USBD_EP_FRDP_OFFSET) +#define IMX_USBD_EP2_FRWP (IMX_USBD_EP2_BASE + USBD_EP_FRWP_OFFSET) + +#define IMX_USBD_EP3_STAT (IMX_USBD_EP3_BASE + USBD_EP_STAT_OFFSET) +#define IMX_USBD_EP3_INTR (IMX_USBD_EP3_BASE + USBD_EP_INTR_OFFSET) +#define IMX_USBD_EP3_MASK (IMX_USBD_EP3_BASE + USBD_EP_MASK_OFFSET) +#define IMX_USBD_EP3_FDAT (IMX_USBD_EP3_BASE + USBD_EP_FDAT_OFFSET) +#define IMX_USBD_EP3_FSTAT (IMX_USBD_EP3_BASE + USBD_EP_FSTAT_OFFSET) +#define IMX_USBD_EP3_FCTRL (IMX_USBD_EP3_BASE + USBD_EP_FCTRL_OFFSET) +#define IMX_USBD_EP3_LRFP (IMX_USBD_EP3_BASE + USBD_EP_LRFP_OFFSET) +#define IMX_USBD_EP3_LRWP (IMX_USBD_EP3_BASE + USBD_EP_LRWP_OFFSET) +#define IMX_USBD_EP3_FALRM (IMX_USBD_EP3_BASE + USBD_EP_FALRM_OFFSET) +#define IMX_USBD_EP3_FRDP (IMX_USBD_EP3_BASE + USBD_EP_FRDP_OFFSET) +#define IMX_USBD_EP3_FRWP (IMX_USBD_EP3_BASE + USBD_EP_FRWP_OFFSET) + +#define IMX_USBD_EP4_STAT (IMX_USBD_EP4_BASE + USBD_EP_STAT_OFFSET) +#define IMX_USBD_EP4_INTR (IMX_USBD_EP4_BASE + USBD_EP_INTR_OFFSET) +#define IMX_USBD_EP4_MASK (IMX_USBD_EP4_BASE + USBD_EP_MASK_OFFSET) +#define IMX_USBD_EP4_FDAT (IMX_USBD_EP4_BASE + USBD_EP_FDAT_OFFSET) +#define IMX_USBD_EP4_FSTAT (IMX_USBD_EP4_BASE + USBD_EP_FSTAT_OFFSET) +#define IMX_USBD_EP4_FCTRL (IMX_USBD_EP4_BASE + USBD_EP_FCTRL_OFFSET) +#define IMX_USBD_EP4_LRFP (IMX_USBD_EP4_BASE + USBD_EP_LRFP_OFFSET) +#define IMX_USBD_EP4_LRWP (IMX_USBD_EP4_BASE + USBD_EP_LRWP_OFFSET) +#define IMX_USBD_EP4_FALRM (IMX_USBD_EP4_BASE + USBD_EP_FALRM_OFFSET) +#define IMX_USBD_EP4_FRDP (IMX_USBD_EP4_BASE + USBD_EP_FRDP_OFFSET) +#define IMX_USBD_EP4_FRWP (IMX_USBD_EP4_BASE + USBD_EP_FRWP_OFFSET) + +#define IMX_USBD_EP5_STAT (IMX_USBD_EP5_BASE + USBD_EP_STAT_OFFSET) +#define IMX_USBD_EP5_INTR (IMX_USBD_EP5_BASE + USBD_EP_INTR_OFFSET) +#define IMX_USBD_EP5_MASK (IMX_USBD_EP5_BASE + USBD_EP_MASK_OFFSET) +#define IMX_USBD_EP5_FDAT (IMX_USBD_EP5_BASE + USBD_EP_FDAT_OFFSET) +#define IMX_USBD_EP5_FSTAT (IMX_USBD_EP5_BASE + USBD_EP_FSTAT_OFFSET) +#define IMX_USBD_EP5_FCTRL (IMX_USBD_EP5_BASE + USBD_EP_FCTRL_OFFSET) +#define IMX_USBD_EP5_LRFP (IMX_USBD_EP5_BASE + USBD_EP_LRFP_OFFSET) +#define IMX_USBD_EP5_LRWP (IMX_USBD_EP5_BASE + USBD_EP_LRWP_OFFSET) +#define IMX_USBD_EP5_FALRM (IMX_USBD_EP5_BASE + USBD_EP_FALRM_OFFSET) +#define IMX_USBD_EP5_FRDP (IMX_USBD_EP5_BASE + USBD_EP_FRDP_OFFSET) +#define IMX_USBD_EP5_FRWP (IMX_USBD_EP5_BASE + USBD_EP_FRWP_OFFSET) + +#define IMX_USBD_EP_STAT(n) (IMX_USBD_EP_BASE(n) + USBD_EP_STAT_OFFSET) +#define IMX_USBD_EP_INTR(n) (IMX_USBD_EP_BASE(n) + USBD_EP_INTR_OFFSET) +#define IMX_USBD_EP_MASK(n) (IMX_USBD_EP_BASE(n) + USBD_EP_MASK_OFFSET) +#define IMX_USBD_EP_FDAT(n) (IMX_USBD_EP_BASE(n) + USBD_EP_FDAT_OFFSET) +#define IMX_USBD_EP_FSTAT(n) (IMX_USBD_EP_BASE(n) + USBD_EP_FSTAT_OFFSET) +#define IMX_USBD_EP_FCTRL(n) (IMX_USBD_EP_BASE(n) + USBD_EP_FCTRL_OFFSET) +#define IMX_USBD_EP_LRFP(n) (IMX_USBD_EP_BASE(n) + USBD_EP_LRFP_OFFSET) +#define IMX_USBD_EP_LRWP(n) (IMX_USBD_EP_BASE(n) + USBD_EP_LRWP_OFFSET) +#define IMX_USBD_EP_FALRM(n) (IMX_USBD_EP_BASE(n) + USBD_EP_FALRM_OFFSET) +#define IMX_USBD_EP_FRDP(n) (IMX_USBD_EP_BASE(n) + USBD_EP_FRDP_OFFSET) +#define IMX_USBD_EP_FRWP(n) (IMX_USBD_EP_BASE(n) + USBD_EP_FRWP_OFFSET) + +/* USBD Register Bit Definitions ****************************************************/ + +/* USBD FRAME Register */ + +#define USBD_FRAME_FRAME_SHIFT 0 /* Bit 0-10: Frame Field */ +#define USBD_FRAME_FRAME_MASK (0x07ff << USBD_FRAME_FRAME_SHIFT) +#define USBD_FRAME_MATCH_SHIFT 16 /* Bit 16-26: Match Field */ +#define USBD_FRAME_MATCH_MASK (0x07ff << USBD_FRAME_MATCH_SHIFT) + +/* USBD STAT Register */ + +#define USBD_STAT_ALTSET_SHIFT 0 /* Bit 0-2: Alternate Setting */ +#define USBD_STAT_ALTSET_MASK (0x07 << USBD_FRAME_MATCH_SHIFT) +#define USBD_STAT_INTF_SHIFT 3 /* Bit 3-4: Interface */ +#define USBD_STAT_INTF_MASK (0x03 << USBD_FRAME_MATCH_SHIFT) +#define USBD_STAT_CFG_SHIFT 5 /* Bit 5-6: Configuration */ +#define USBD_STAT_CFG_MASK (0x03 << USBD_FRAME_MATCH_SHIFT) +#define USBD_STAT_SUSP (1 << 7) /* Bit 7: Suspend */ +#define USBD_STAT_RST (1 << 8) /* Bit 8: Reset Signaling */ + +/* USBD CTRL Register */ + +#define USBD_CTRL_RESUME (1 << 0) /* Bit 0: Resume */ +#define USBD_CTRL_AFEENA (1 << 1) /* Bit 1: Analog Front-End Enable */ +#define USBD_CTRL_UDCRST (1 << 2) /* Bit 2: UDC Reset */ +#define USBD_CTRL_USBENA (1 << 3) /* Bit 3: USB Enable */ +#define USBD_CTRL_USBSPD (1 << 4) /* Bit 4: USB Speed */ +#define USBD_CTRL_CMDERROR (1 << 5) /* Bit 5: Command Error */ +#define USBD_CTRL_CMDOVER (1 << 6) /* Bit 6: Command Over */ + +/* USBD DADR Register */ + +#define USBD_DADR_DADR_SHIFT 0 /* Bit 0-8: Desired RAM Address */ +#define USBD_DADR_DADR_MASK (0x1ff << USBD_DADR_DADR_SHIFT) +#define USBD_DADR_BSY (1 << 30) /* Bit 30: Busy */ +#define USBD_DADR_CFG (1 << 31) /* Bit 31: Configuration */ + +/* USBD DDAT Register */ + +#define USBD_DDAT_DDAT_SHIFT 0 /* Bit 0-7: Descriptor Data Buffer */ +#define USBD_DDAT_DDAT_MASK (0xff << USBD_DDAT_DDAT_SHIFT) + +/* USBD INTR Register */ + +#define USBD_INTR_CFGCHG (1 << 0) /* Bit 0: Configuration Change */ +#define USBD_INTR_FRAMEMATCH (1 << 1) /* Bit 1: FRAME_MATCH */ +#define USBD_INTR_SUSP (1 << 2) /* Bit 2: Active to Suspend */ +#define USBD_INTR_RES (1 << 3) /* Bit 3: Suspend to Resume */ +#define USBD_INTR_RESETSTART (1 << 4) /* Bit 4: Restart Signaling Start */ +#define USBD_INTR_RESETSTOP (1 << 5) /* Bit 5: Restart Signaling Stop */ +#define USBD_INTR_SOF (1 << 6) /* Bit 6: Start-of-Frame Interrupt */ +#define USBD_INTR_MSOF (1 << 7) /* Bit 7: Missed Start-of-Frame Interrupt */ +#define USBD_INTR_WAKEUP (1 << 31) /* Bit 31: Wakeup */ + +/* USBD MASK Register */ + +#define USBD_MASK_CFGCHG (1 << 0) /* Bit 0: Configuration Change */ +#define USBD_MASK_FRAMEMATCH (1 << 1) /* Bit 1: FRAME_MATCH */ +#define USBD_MASK_SUSP (1 << 2) /* Bit 2: Active to Suspend */ +#define USBD_MASK_RES (1 << 3) /* Bit 3: Suspend to Resume */ +#define USBD_MASK_RESETSTART (1 << 4) /* Bit 4: Restart Signaling Start */ +#define USBD_MASK_RESETSTOP (1 << 5) /* Bit 5: Restart Signaling Stop */ +#define USBD_MASK_SOF (1 << 6) /* Bit 6: Start-of-Frame Interrupt */ +#define USBD_MASK_MSOF (1 << 7) /* Bit 7: Missed Start-of-Frame Interrupt */ +#define USBD_MASK_WAKEUP (1 << 31) /* Bit 31: Wakeup */ + +/* USBD ENAB Register */ + +#define USBD_ENAB_PWDMD (1 << 0) /* Bit 0: Power Mode */ +#define USBD_ENAB_ENDIANMODE (1 << 28) /* Bit 28: Endian Mode Select */ +#define USBD_ENAB_SUSPEND (1 << 29) /* Bit 29: Suspend */ +#define USBD_ENAB_ENAB (1 << 30) /* Bit 30: Enable */ +#define USBD_ENAB_RST (1 << 31) /* Bit 31: Reset */ + +/* USBD EPSTAT Register */ + +#define USBD_EPSTAT_FORCESTALL (1 << 0) /* Bit 0: Force a Stall Condition */ +#define USBD_EPSTAT_FLUSH (1 << 1) /* Bit 1: Flush */ +#define USBD_EPSTAT_ZLPS (1 << 2) /* Bit 2: Zero Length Packet Send */ +#define USBD_EPSTAT_TYP_SHIFT 3 /* Bit 3-4: Endpoint Type */ +#define USBD_EPSTAT_TYP_MASK (0x03 << USBD_EPSTAT_TYP_SHIFT) +#define USBD_EPSTAT_MAX_SHIFT 5 /* Bit 5-6: Maximum Packet Size */ +#define USBD_EPSTAT_MAX_MASK (0x03 << USBD_EPSTAT_MAX_SHIFT) +#define USBD_EPSTAT_DIR (1 << 7) /* Bit 7: Transfer Direction */ +#define USBD_EPSTAT_SIP (1 << 8) /* Bit 8: Setup Packet in Progress */ +#define USBD_EPSTAT_BYTECOUNT_SHIFT 16 /* Bit 16-22: Byte Count */ +#define USBD_EPSTAT_BYTECOUNT_MASK (0x7f << USBD_EPSTAT_BYTECOUNT_SHIFT) + +/* USBD EPINTR Register */ + +#define USBD_EPINTR_EOF (1 << 0) /* Bit 0: End-of-Frame */ +#define USBD_EPINTR_DEVREQ (1 << 1) /* Bit 1: Device Request */ +#define USBD_EPINTR_EOT (1 << 2) /* Bit 2: End of Transfer */ +#define USBD_EPINTR_MDEVREQ (1 << 3) /* Bit 3: Multiple Device Request */ +#define USBD_EPINTR_FIFOLOW (1 << 4) /* Bit 4: FIFO Low */ +#define USBD_EPINTR_FIFOHIGH (1 << 5) /* Bit 5: FIFO High */ +#define USBD_EPINTR_FIFOERROR (1 << 6) /* Bit 6: FIFO Error */ +#define USBD_EPINTR_FIFOEMPTY (1 << 7) /* Bit 7: FIFO Empty */ +#define USBD_EPINTR_FIFOFULL (1 << 8) /* Bit 8: FIFO Full */ + +/* USBD EPMASK Register */ + +#define USBD_EPMASK_EOF (1 << 0) /* Bit 0: End-of-Frame */ +#define USBD_EPMASK_DEVREQ (1 << 1) /* Bit 1: Device Request */ +#define USBD_EPMASK_EOT (1 << 2) /* Bit 2: End of Transfer */ +#define USBD_EPMASK_MDEVREQ (1 << 3) /* Bit 3: Multiple Device Request */ +#define USBD_EPMASK_FIFOLOW (1 << 4) /* Bit 4: FIFO Low */ +#define USBD_EPMASK_FIFOHIGH (1 << 5) /* Bit 5: FIFO High */ +#define USBD_EPMASK_FIFOERROR (1 << 6) /* Bit 6: FIFO Error */ +#define USBD_EPMASK_FIFOEMPTY (1 << 7) /* Bit 7: FIFO Empty */ +#define USBD_EPMASK_FIFOFULL (1 << 8) /* Bit 8: FIFO Full */ + +/* USBD EPFSTAT Register */ + +#define USBD_EPFSTAT_EMPTY (1 << 16) /* Bit 16: FIFO Empty */ +#define USBD_EPFSTAT_ALARM (1 << 17) /* Bit 17: FIFO Alarm */ +#define USBD_EPFSTAT_FULL (1 << 18) /* Bit 18: FIFO Full */ +#define USBD_EPFSTAT_FR (1 << 19) /* Bit 19: FIFO Ready */ +#define USBD_EPFSTAT_OF (1 << 20) /* Bit 20: FIFO Overflow */ +#define USBD_EPFSTAT_UF (1 << 21) /* Bit 21: FIFO Underflow */ +#define USBD_EPFSTAT_ERROR (1 << 22) /* Bit 22: FIFO Error */ +#define USBD_EPFSTAT_FRAME3 (1 << 24) /* Bit 24: Frame Status Bit 3 */ +#define USBD_EPFSTAT_FRAME2 (1 << 25) /* Bit 25: Frame Status Bit 2 */ +#define USBD_EPFSTAT_FRAME1 (1 << 26) /* Bit 26: Frame Status Bit 1 */ +#define USBD_EPFSTAT_FRAME0 (1 << 27) /* Bit 27: Frame Status Bit 0 */ + +/* USBD EPFCTRL Register */ + +#define USBD_EPCTRL_GR_SHIFT 24 /* Bit 24-26: Granularity */ +#define USBD_EPCTRL_GR_MASK (0x07 << USBD_EPCTRL_GR_SHIFT) +#define USBD_EPCTRL_FRAME (1 << 27) /* Bit 27: Frame Mode */ +#define USBD_EPCTRL_WFR (1 << 28) /* Bit 29: Write Frame End */ + +/************************************************************************************ + * Inline Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_IMX_USBD_H */ diff --git a/nuttx/arch/arm/src/imx/imx_wdog.h b/nuttx/arch/arm/src/imx/imx_wdog.h index 137e67754..4ee6438b3 100755 --- a/nuttx/arch/arm/src/imx/imx_wdog.h +++ b/nuttx/arch/arm/src/imx/imx_wdog.h @@ -1,81 +1,81 @@ -/************************************************************************************
- * arch/arm/src/imx/imx_wdog.h
- *
- * Copyright (C) 2009 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_IMX_WDOG_H
-#define __ARCH_ARM_IMX_WDOG_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-/************************************************************************************
- * Definitions
- ************************************************************************************/
-
-/* WDOG Register Offsets ************************************************************/
-
-#define WDOG_WCR_OFFSET 0x0000 /* Watchdog Control Register */
-#define WDOG_WSR_OFFSET 0x0004 /* Watchdog Service Register */
-#define WDOG_WSTR_OFFSET 0x0008 /* Watchdog Status Register */
-
-/* WDOG Register Addresses **********************************************************/
-
-#define IMX_WDOG_WCR (IMX_WDOG_VBASE + WDOG_WCR_OFFSET)
-#define IMX_WDOG_WSR (IMX_WDOG_VBASE + WDOG_WSR_OFFSET)
-#define IMX_WDOG_WSTRT (IMX_WDOG_VBASE + WDOG_WSTR_OFFSET)
-
-/* WDOG Register Bit Definitions ****************************************************/
-
-/* Watchdog Control Register */
-
-#define WDOG_WCR_WDE (1 << 0) /* Bit 0: Watchdog Enable */
-#define WDOG_WCR_WDEC (1 << 1) /* Bit 1: Watchdog Enable Control */
-#define WDOG_WCR_SWR (1 << 2) /* Bit 2: Software Reset Enable */
-#define WDOG_WCR_TMD (1 << 3) /* Bit 3: Test Mode Enable */
-#define WDOG_WCR_WIE (1 << 4) /* Bit 4: Watchdog Interrupt Enable */
-#define WDOG_WCR_WT_SHIFT 8 /* Bit 8-14: Watchdog Timeout */
-#define WDOG_WCR_WT_MASK (0x7f << WDOG_WCR_WT_SHIFT)
-#define WDOG_WCR_WHALT (1 << 15) /* Bit 15: Watchdog Halt */
-
-/* Watchdog Service Register */
-
-#define WDOG_WSR_SHIFT 0 /* Bit 0-15: Watchdog Service Register */
-#define WDOG_WT_MASK (0xffff << WDOG_WSR_SHIFT)
-
-/************************************************************************************
- * Inline Functions
- ************************************************************************************/
-
-#endif /* __ARCH_ARM_IMX_WDOG_H */
+/************************************************************************************ + * arch/arm/src/imx/imx_wdog.h + * + * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_IMX_WDOG_H +#define __ARCH_ARM_IMX_WDOG_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +/************************************************************************************ + * Definitions + ************************************************************************************/ + +/* WDOG Register Offsets ************************************************************/ + +#define WDOG_WCR_OFFSET 0x0000 /* Watchdog Control Register */ +#define WDOG_WSR_OFFSET 0x0004 /* Watchdog Service Register */ +#define WDOG_WSTR_OFFSET 0x0008 /* Watchdog Status Register */ + +/* WDOG Register Addresses **********************************************************/ + +#define IMX_WDOG_WCR (IMX_WDOG_VBASE + WDOG_WCR_OFFSET) +#define IMX_WDOG_WSR (IMX_WDOG_VBASE + WDOG_WSR_OFFSET) +#define IMX_WDOG_WSTRT (IMX_WDOG_VBASE + WDOG_WSTR_OFFSET) + +/* WDOG Register Bit Definitions ****************************************************/ + +/* Watchdog Control Register */ + +#define WDOG_WCR_WDE (1 << 0) /* Bit 0: Watchdog Enable */ +#define WDOG_WCR_WDEC (1 << 1) /* Bit 1: Watchdog Enable Control */ +#define WDOG_WCR_SWR (1 << 2) /* Bit 2: Software Reset Enable */ +#define WDOG_WCR_TMD (1 << 3) /* Bit 3: Test Mode Enable */ +#define WDOG_WCR_WIE (1 << 4) /* Bit 4: Watchdog Interrupt Enable */ +#define WDOG_WCR_WT_SHIFT 8 /* Bit 8-14: Watchdog Timeout */ +#define WDOG_WCR_WT_MASK (0x7f << WDOG_WCR_WT_SHIFT) +#define WDOG_WCR_WHALT (1 << 15) /* Bit 15: Watchdog Halt */ + +/* Watchdog Service Register */ + +#define WDOG_WSR_SHIFT 0 /* Bit 0-15: Watchdog Service Register */ +#define WDOG_WT_MASK (0xffff << WDOG_WSR_SHIFT) + +/************************************************************************************ + * Inline Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_IMX_WDOG_H */ diff --git a/nuttx/arch/arm/src/kinetis/Make.defs b/nuttx/arch/arm/src/kinetis/Make.defs index 2b978b6b5..22d066828 100644 --- a/nuttx/arch/arm/src/kinetis/Make.defs +++ b/nuttx/arch/arm/src/kinetis/Make.defs @@ -2,7 +2,7 @@ # arch/arm/src/kinetis/Make.defs # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt <spudmonkey@racsa.co.cr> +# Author: Gregory Nutt <gnutt@nuttx.org> # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/kinetis/chip.h b/nuttx/arch/arm/src/kinetis/chip.h index 253562a06..6ad781c20 100644 --- a/nuttx/arch/arm/src/kinetis/chip.h +++ b/nuttx/arch/arm/src/kinetis/chip.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/chip.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/kinetis/kinetis_adc.h b/nuttx/arch/arm/src/kinetis/kinetis_adc.h index 47bbdbd70..a17aa06c7 100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_adc.h +++ b/nuttx/arch/arm/src/kinetis/kinetis_adc.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_adc.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/kinetis/kinetis_aips.h b/nuttx/arch/arm/src/kinetis/kinetis_aips.h index 6e0440147..8f460567f 100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_aips.h +++ b/nuttx/arch/arm/src/kinetis/kinetis_aips.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_aips.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/kinetis/kinetis_axbs.h b/nuttx/arch/arm/src/kinetis/kinetis_axbs.h index 4a5136005..bf8543d4d 100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_axbs.h +++ b/nuttx/arch/arm/src/kinetis/kinetis_axbs.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_axbs.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/kinetis/kinetis_clockconfig.c b/nuttx/arch/arm/src/kinetis/kinetis_clockconfig.c index f167a0328..31ea235d2 100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_clockconfig.c +++ b/nuttx/arch/arm/src/kinetis/kinetis_clockconfig.c @@ -3,7 +3,7 @@ * arch/arm/src/chip/kinetis_clockconfig.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/kinetis/kinetis_clrpend.c b/nuttx/arch/arm/src/kinetis/kinetis_clrpend.c index 98997bf2e..2837d867f 100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_clrpend.c +++ b/nuttx/arch/arm/src/kinetis/kinetis_clrpend.c @@ -3,7 +3,7 @@ * arch/arm/src/chip/kinetis_clrpend.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/kinetis/kinetis_cmp.h b/nuttx/arch/arm/src/kinetis/kinetis_cmp.h index 207d86197..822b7a339 100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_cmp.h +++ b/nuttx/arch/arm/src/kinetis/kinetis_cmp.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_cmp.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/kinetis/kinetis_cmt.h b/nuttx/arch/arm/src/kinetis/kinetis_cmt.h index 34cd12177..c3c47bb67 100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_cmt.h +++ b/nuttx/arch/arm/src/kinetis/kinetis_cmt.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_cmt.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/kinetis/kinetis_config.h b/nuttx/arch/arm/src/kinetis/kinetis_config.h index 025ebc7a8..4faa90ce7 100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_config.h +++ b/nuttx/arch/arm/src/kinetis/kinetis_config.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_config.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/kinetis/kinetis_crc.h b/nuttx/arch/arm/src/kinetis/kinetis_crc.h index 88e20f64c..7b590cf3a 100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_crc.h +++ b/nuttx/arch/arm/src/kinetis/kinetis_crc.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_crc.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/kinetis/kinetis_dac.h b/nuttx/arch/arm/src/kinetis/kinetis_dac.h index fbc2fd697..5c3b5c0c0 100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_dac.h +++ b/nuttx/arch/arm/src/kinetis/kinetis_dac.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_dac.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/kinetis/kinetis_dma.h b/nuttx/arch/arm/src/kinetis/kinetis_dma.h index efe586345..9876a46a0 100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_dma.h +++ b/nuttx/arch/arm/src/kinetis/kinetis_dma.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_dma.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/kinetis/kinetis_dmamux.h b/nuttx/arch/arm/src/kinetis/kinetis_dmamux.h index 0db25305d..b83579180 100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_dmamux.h +++ b/nuttx/arch/arm/src/kinetis/kinetis_dmamux.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_dmamux.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/kinetis/kinetis_dspi.h b/nuttx/arch/arm/src/kinetis/kinetis_dspi.h index a2ead5852..e682ef23e 100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_dspi.h +++ b/nuttx/arch/arm/src/kinetis/kinetis_dspi.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_dspi.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/kinetis/kinetis_enet.h b/nuttx/arch/arm/src/kinetis/kinetis_enet.h index d610f15c3..0a5e78ea9 100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_enet.h +++ b/nuttx/arch/arm/src/kinetis/kinetis_enet.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_enet.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/kinetis/kinetis_ewm.h b/nuttx/arch/arm/src/kinetis/kinetis_ewm.h index 4e6113e81..e259a3cf2 100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_ewm.h +++ b/nuttx/arch/arm/src/kinetis/kinetis_ewm.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_ewm.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/kinetis/kinetis_flexbus.h b/nuttx/arch/arm/src/kinetis/kinetis_flexbus.h index e4936949a..37992320f 100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_flexbus.h +++ b/nuttx/arch/arm/src/kinetis/kinetis_flexbus.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_flexbus.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/kinetis/kinetis_flexcan.h b/nuttx/arch/arm/src/kinetis/kinetis_flexcan.h index f129c9577..db151d540 100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_flexcan.h +++ b/nuttx/arch/arm/src/kinetis/kinetis_flexcan.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_flexcan.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/kinetis/kinetis_fmc.h b/nuttx/arch/arm/src/kinetis/kinetis_fmc.h index 2a318e3de..66f3a3909 100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_fmc.h +++ b/nuttx/arch/arm/src/kinetis/kinetis_fmc.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_fmc.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/kinetis/kinetis_ftfl.h b/nuttx/arch/arm/src/kinetis/kinetis_ftfl.h index 27746ab02..92e53b650 100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_ftfl.h +++ b/nuttx/arch/arm/src/kinetis/kinetis_ftfl.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_ftfl.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/kinetis/kinetis_ftm.h b/nuttx/arch/arm/src/kinetis/kinetis_ftm.h index a318ddfee..52f782855 100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_ftm.h +++ b/nuttx/arch/arm/src/kinetis/kinetis_ftm.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_ftm.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/kinetis/kinetis_gpio.h b/nuttx/arch/arm/src/kinetis/kinetis_gpio.h index 8a87aa72a..1d3d10553 100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_gpio.h +++ b/nuttx/arch/arm/src/kinetis/kinetis_gpio.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_gpio.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/kinetis/kinetis_i2c.h b/nuttx/arch/arm/src/kinetis/kinetis_i2c.h index 353882eff..bee9ef92d 100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_i2c.h +++ b/nuttx/arch/arm/src/kinetis/kinetis_i2c.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_i2c.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/kinetis/kinetis_i2s.h b/nuttx/arch/arm/src/kinetis/kinetis_i2s.h index f69aa8543..11bcc0995 100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_i2s.h +++ b/nuttx/arch/arm/src/kinetis/kinetis_i2s.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_i2s.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/kinetis/kinetis_idle.c b/nuttx/arch/arm/src/kinetis/kinetis_idle.c index 8fc914f3f..bcf8218cb 100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_idle.c +++ b/nuttx/arch/arm/src/kinetis/kinetis_idle.c @@ -1,104 +1,104 @@ -/****************************************************************************
- * arch/arm/src/kinetis/kinetis_idle.c
- *
- * Copyright (C) 2011 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include <arch/board/board.h>
-#include <nuttx/config.h>
-
-#include <nuttx/arch.h>
-#include "up_internal.h"
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/* Does the board support an IDLE LED to indicate that the board is in the
- * IDLE state?
- */
-
-#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE)
-# define BEGIN_IDLE() up_ledon(LED_IDLE)
-# define END_IDLE() up_ledoff(LED_IDLE)
-#else
-# define BEGIN_IDLE()
-# define END_IDLE()
-#endif
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
-
-/****************************************************************************
- * Name: up_idle
- *
- * Description:
- * up_idle() is the logic that will be executed when their is no other
- * ready-to-run task. This is processor idle time and will continue until
- * some interrupt occurs to cause a context switch from the idle task.
- *
- * Processing in this state may be processor-specific. e.g., this is where
- * power management operations might be performed.
- *
- ****************************************************************************/
-
-void up_idle(void)
-{
-#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS)
- /* If the system is idle and there are no timer interrupts, then process
- * "fake" timer interrupts. Hopefully, something will wake up.
- */
-
- sched_process_timer();
-#else
-
- /* Sleep until an interrupt occurs to save power */
-
- BEGIN_IDLE();
- asm("WFI");
- END_IDLE();
-#endif
-}
-
+/**************************************************************************** + * arch/arm/src/kinetis/kinetis_idle.c + * + * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <arch/board/board.h> +#include <nuttx/config.h> + +#include <nuttx/arch.h> +#include "up_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Does the board support an IDLE LED to indicate that the board is in the + * IDLE state? + */ + +#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE) +# define BEGIN_IDLE() up_ledon(LED_IDLE) +# define END_IDLE() up_ledoff(LED_IDLE) +#else +# define BEGIN_IDLE() +# define END_IDLE() +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_idle + * + * Description: + * up_idle() is the logic that will be executed when their is no other + * ready-to-run task. This is processor idle time and will continue until + * some interrupt occurs to cause a context switch from the idle task. + * + * Processing in this state may be processor-specific. e.g., this is where + * power management operations might be performed. + * + ****************************************************************************/ + +void up_idle(void) +{ +#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS) + /* If the system is idle and there are no timer interrupts, then process + * "fake" timer interrupts. Hopefully, something will wake up. + */ + + sched_process_timer(); +#else + + /* Sleep until an interrupt occurs to save power */ + + BEGIN_IDLE(); + asm("WFI"); + END_IDLE(); +#endif +} + diff --git a/nuttx/arch/arm/src/kinetis/kinetis_internal.h b/nuttx/arch/arm/src/kinetis/kinetis_internal.h index c05032678..8d7baaaf1 100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_internal.h +++ b/nuttx/arch/arm/src/kinetis/kinetis_internal.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_internal.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/kinetis/kinetis_irq.c b/nuttx/arch/arm/src/kinetis/kinetis_irq.c index 308afcb97..6fb58c6bf 100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_irq.c +++ b/nuttx/arch/arm/src/kinetis/kinetis_irq.c @@ -3,7 +3,7 @@ * arch/arm/src/chip/kinetis_irq.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/kinetis/kinetis_k40pinmux.h b/nuttx/arch/arm/src/kinetis/kinetis_k40pinmux.h index 13a4da421..9798eda6b 100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_k40pinmux.h +++ b/nuttx/arch/arm/src/kinetis/kinetis_k40pinmux.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_k40pinmux.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/kinetis/kinetis_k60pinmux.h b/nuttx/arch/arm/src/kinetis/kinetis_k60pinmux.h index dee0d15d6..2c77dd4ba 100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_k60pinmux.h +++ b/nuttx/arch/arm/src/kinetis/kinetis_k60pinmux.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_k60pinset.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/kinetis/kinetis_llwu.h b/nuttx/arch/arm/src/kinetis/kinetis_llwu.h index 60fa2fed7..4324a7625 100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_llwu.h +++ b/nuttx/arch/arm/src/kinetis/kinetis_llwu.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_llwu.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/kinetis/kinetis_lowputc.c b/nuttx/arch/arm/src/kinetis/kinetis_lowputc.c index 96d9d6989..f52d3ba35 100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_lowputc.c +++ b/nuttx/arch/arm/src/kinetis/kinetis_lowputc.c @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_lowputc.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/kinetis/kinetis_lptmr.h b/nuttx/arch/arm/src/kinetis/kinetis_lptmr.h index 42e251f30..863b24108 100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_lptmr.h +++ b/nuttx/arch/arm/src/kinetis/kinetis_lptmr.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_lptmr.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/kinetis/kinetis_mcg.h b/nuttx/arch/arm/src/kinetis/kinetis_mcg.h index 6f0ba652c..60f13cd2a 100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_mcg.h +++ b/nuttx/arch/arm/src/kinetis/kinetis_mcg.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_mcg.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/kinetis/kinetis_mcm.h b/nuttx/arch/arm/src/kinetis/kinetis_mcm.h index 8424587aa..d899b7702 100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_mcm.h +++ b/nuttx/arch/arm/src/kinetis/kinetis_mcm.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_mcm.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/kinetis/kinetis_memorymap.h b/nuttx/arch/arm/src/kinetis/kinetis_memorymap.h index be0b22954..7253717bd 100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_memorymap.h +++ b/nuttx/arch/arm/src/kinetis/kinetis_memorymap.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_memorymap.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/kinetis/kinetis_mmcau.h b/nuttx/arch/arm/src/kinetis/kinetis_mmcau.h index f1ba0e769..7468a1d0b 100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_mmcau.h +++ b/nuttx/arch/arm/src/kinetis/kinetis_mmcau.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_mmcau.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/kinetis/kinetis_mpu.h b/nuttx/arch/arm/src/kinetis/kinetis_mpu.h index 9db2570b9..f2b1bf914 100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_mpu.h +++ b/nuttx/arch/arm/src/kinetis/kinetis_mpu.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_mpu.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/kinetis/kinetis_osc.h b/nuttx/arch/arm/src/kinetis/kinetis_osc.h index fef1e0ae7..16efcf328 100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_osc.h +++ b/nuttx/arch/arm/src/kinetis/kinetis_osc.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_osc.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/kinetis/kinetis_pdb.h b/nuttx/arch/arm/src/kinetis/kinetis_pdb.h index 525efc738..9cfab9b99 100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_pdb.h +++ b/nuttx/arch/arm/src/kinetis/kinetis_pdb.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_pdb.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/kinetis/kinetis_pin.c b/nuttx/arch/arm/src/kinetis/kinetis_pin.c index cdd9e19c1..43bfae61e 100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_pin.c +++ b/nuttx/arch/arm/src/kinetis/kinetis_pin.c @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_pin.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/kinetis/kinetis_pindma.c b/nuttx/arch/arm/src/kinetis/kinetis_pindma.c index 00d9a07e6..91132a6a7 100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_pindma.c +++ b/nuttx/arch/arm/src/kinetis/kinetis_pindma.c @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_pindma.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/kinetis/kinetis_pingpio.c b/nuttx/arch/arm/src/kinetis/kinetis_pingpio.c index 23829c6d7..fe25f0df0 100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_pingpio.c +++ b/nuttx/arch/arm/src/kinetis/kinetis_pingpio.c @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_pingpio.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/kinetis/kinetis_pinirq.c b/nuttx/arch/arm/src/kinetis/kinetis_pinirq.c index 1ed9092e2..537e7be9f 100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_pinirq.c +++ b/nuttx/arch/arm/src/kinetis/kinetis_pinirq.c @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_pinirq.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/kinetis/kinetis_pinmux.h b/nuttx/arch/arm/src/kinetis/kinetis_pinmux.h index 04d956e4e..9c791539f 100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_pinmux.h +++ b/nuttx/arch/arm/src/kinetis/kinetis_pinmux.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_pinmux.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/kinetis/kinetis_pit.h b/nuttx/arch/arm/src/kinetis/kinetis_pit.h index 6771f6310..808508f8f 100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_pit.h +++ b/nuttx/arch/arm/src/kinetis/kinetis_pit.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_pit.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/kinetis/kinetis_pmc.h b/nuttx/arch/arm/src/kinetis/kinetis_pmc.h index 2525a936c..065847da3 100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_pmc.h +++ b/nuttx/arch/arm/src/kinetis/kinetis_pmc.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_pmc.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/kinetis/kinetis_port.h b/nuttx/arch/arm/src/kinetis/kinetis_port.h index 2f72f4874..a256fc5c6 100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_port.h +++ b/nuttx/arch/arm/src/kinetis/kinetis_port.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_port.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/kinetis/kinetis_rngb.h b/nuttx/arch/arm/src/kinetis/kinetis_rngb.h index f55b37843..a4f677555 100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_rngb.h +++ b/nuttx/arch/arm/src/kinetis/kinetis_rngb.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_rngb.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/kinetis/kinetis_rtc.h b/nuttx/arch/arm/src/kinetis/kinetis_rtc.h index 2a3c57e59..69c097a7c 100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_rtc.h +++ b/nuttx/arch/arm/src/kinetis/kinetis_rtc.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_rtc.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/kinetis/kinetis_sdhc.h b/nuttx/arch/arm/src/kinetis/kinetis_sdhc.h index cf96faabe..5d122315a 100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_sdhc.h +++ b/nuttx/arch/arm/src/kinetis/kinetis_sdhc.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_sdhc.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/kinetis/kinetis_sim.h b/nuttx/arch/arm/src/kinetis/kinetis_sim.h index bdbf4dc02..aad17e923 100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_sim.h +++ b/nuttx/arch/arm/src/kinetis/kinetis_sim.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_sim.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/kinetis/kinetis_slcd.h b/nuttx/arch/arm/src/kinetis/kinetis_slcd.h index 6849af423..d56ee5c41 100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_slcd.h +++ b/nuttx/arch/arm/src/kinetis/kinetis_slcd.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_slcd.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/kinetis/kinetis_smc.h b/nuttx/arch/arm/src/kinetis/kinetis_smc.h index b596164b0..213ea8077 100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_smc.h +++ b/nuttx/arch/arm/src/kinetis/kinetis_smc.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_smc.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/kinetis/kinetis_timerisr.c b/nuttx/arch/arm/src/kinetis/kinetis_timerisr.c index 62758ee9c..9f9f14ba6 100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_timerisr.c +++ b/nuttx/arch/arm/src/kinetis/kinetis_timerisr.c @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_timerisr.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/kinetis/kinetis_tsi.h b/nuttx/arch/arm/src/kinetis/kinetis_tsi.h index df96a0d8c..5e1dd9976 100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_tsi.h +++ b/nuttx/arch/arm/src/kinetis/kinetis_tsi.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_tsi.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/kinetis/kinetis_uart.h b/nuttx/arch/arm/src/kinetis/kinetis_uart.h index 2983aaf0d..fbdf7a319 100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_uart.h +++ b/nuttx/arch/arm/src/kinetis/kinetis_uart.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_uart.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/kinetis/kinetis_usbdcd.h b/nuttx/arch/arm/src/kinetis/kinetis_usbdcd.h index cfbb28a97..fad76d150 100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_usbdcd.h +++ b/nuttx/arch/arm/src/kinetis/kinetis_usbdcd.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_usbdcd.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/kinetis/kinetis_usbotg.h b/nuttx/arch/arm/src/kinetis/kinetis_usbotg.h index 9219398e7..127c71831 100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_usbotg.h +++ b/nuttx/arch/arm/src/kinetis/kinetis_usbotg.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_usbotg.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/kinetis/kinetis_vectors.S b/nuttx/arch/arm/src/kinetis/kinetis_vectors.S index ff252c91a..faa1ce7a7 100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_vectors.S +++ b/nuttx/arch/arm/src/kinetis/kinetis_vectors.S @@ -3,7 +3,7 @@ * arch/arm/src/chip/kinetis_vectors.S * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/kinetis/kinetis_vrefv1.h b/nuttx/arch/arm/src/kinetis/kinetis_vrefv1.h index 01789e212..ed9a1ff95 100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_vrefv1.h +++ b/nuttx/arch/arm/src/kinetis/kinetis_vrefv1.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_vrefv1.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/kinetis/kinetis_wdog.c b/nuttx/arch/arm/src/kinetis/kinetis_wdog.c index 9ba49306f..19b6b1d59 100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_wdog.c +++ b/nuttx/arch/arm/src/kinetis/kinetis_wdog.c @@ -1,117 +1,117 @@ -/****************************************************************************
- * arch/arm/src/kinetis/kinetis_wdog.c
- * arch/arm/src/chip/kinetis_wdog.c
- *
- * Copyright (C) 2011 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include <nuttx/config.h>
-
-#include <arch/irq.h>
-
-#include "up_arch.h"
-#include "kinetis_internal.h"
-#include "kinetis_wdog.h"
-
-/****************************************************************************
- * Private Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Public Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
-/****************************************************************************
- * Name: kinetis_wdunlock
- *
- * Description:
- * Watchdog timer unlock routine. Writing 0xc520 followed by 0xd928 will
- * unlock the write once registers in the WDOG so they are writable
- * within the WCT period.
- *
- ****************************************************************************/
-
-static void kinetis_wdunlock(void)
-{
- irqstate_t flags;
-
- /* This sequence must execute within 20 clock cycles. Disable interrupts
- * to assure that the following steps are atomic.
- */
-
- flags = irqsave();
-
- /* Write 0xC520 followed by 0xD928 to the unlock register */
-
- putreg16(0xc520, KINETIS_WDOG_UNLOCK);
- putreg16(0xd928, KINETIS_WDOG_UNLOCK);
- irqrestore(flags);
-}
-
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
-
-/****************************************************************************
- * Name: kinetis_wddisable
- *
- * Description:
- * Disable the watchdog timer
- *
- ****************************************************************************/
-
-void kinetis_wddisable(void)
-{
- uint16_t regval;
-
- /* Unlock the watchdog so that we can write to registers */
-
- kinetis_wdunlock();
-
- /* Clear the WDOGEN bit to disable the watchdog */
-
- regval = getreg16(KINETIS_WDOG_STCTRLH);
- regval &= ~WDOG_STCTRLH_WDOGEN;
- putreg16(regval, KINETIS_WDOG_STCTRLH);
-}
+/**************************************************************************** + * arch/arm/src/kinetis/kinetis_wdog.c + * arch/arm/src/chip/kinetis_wdog.c + * + * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include <arch/irq.h> + +#include "up_arch.h" +#include "kinetis_internal.h" +#include "kinetis_wdog.h" + +/**************************************************************************** + * Private Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: kinetis_wdunlock + * + * Description: + * Watchdog timer unlock routine. Writing 0xc520 followed by 0xd928 will + * unlock the write once registers in the WDOG so they are writable + * within the WCT period. + * + ****************************************************************************/ + +static void kinetis_wdunlock(void) +{ + irqstate_t flags; + + /* This sequence must execute within 20 clock cycles. Disable interrupts + * to assure that the following steps are atomic. + */ + + flags = irqsave(); + + /* Write 0xC520 followed by 0xD928 to the unlock register */ + + putreg16(0xc520, KINETIS_WDOG_UNLOCK); + putreg16(0xd928, KINETIS_WDOG_UNLOCK); + irqrestore(flags); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: kinetis_wddisable + * + * Description: + * Disable the watchdog timer + * + ****************************************************************************/ + +void kinetis_wddisable(void) +{ + uint16_t regval; + + /* Unlock the watchdog so that we can write to registers */ + + kinetis_wdunlock(); + + /* Clear the WDOGEN bit to disable the watchdog */ + + regval = getreg16(KINETIS_WDOG_STCTRLH); + regval &= ~WDOG_STCTRLH_WDOGEN; + putreg16(regval, KINETIS_WDOG_STCTRLH); +} diff --git a/nuttx/arch/arm/src/kinetis/kinetis_wdog.h b/nuttx/arch/arm/src/kinetis/kinetis_wdog.h index 0432802b7..326c2cf62 100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_wdog.h +++ b/nuttx/arch/arm/src/kinetis/kinetis_wdog.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_wdog.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/lm3s/Make.defs b/nuttx/arch/arm/src/lm3s/Make.defs index 01fceaaa8..574526f18 100644 --- a/nuttx/arch/arm/src/lm3s/Make.defs +++ b/nuttx/arch/arm/src/lm3s/Make.defs @@ -2,7 +2,7 @@ # arch/arm/src/lm3s/Make.defs # # Copyright (C) 2009-2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt <spudmonkey@racsa.co.cr> +# Author: Gregory Nutt <gnutt@nuttx.org> # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/lm3s/chip.h b/nuttx/arch/arm/src/lm3s/chip.h index 7be4cba51..1e22f6221 100644 --- a/nuttx/arch/arm/src/lm3s/chip.h +++ b/nuttx/arch/arm/src/lm3s/chip.h @@ -2,7 +2,7 @@ * arch/arm/src/lm3s/chip.h * * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/lm3s/lm3s_dumpgpio.c b/nuttx/arch/arm/src/lm3s/lm3s_dumpgpio.c index 631fc7e80..334a3930f 100644 --- a/nuttx/arch/arm/src/lm3s/lm3s_dumpgpio.c +++ b/nuttx/arch/arm/src/lm3s/lm3s_dumpgpio.c @@ -2,7 +2,7 @@ * arch/arm/src/lm3s/lm3s_dumpgpio.c * * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/lm3s/lm3s_ethernet.c b/nuttx/arch/arm/src/lm3s/lm3s_ethernet.c index be38a7b26..f7bbedb20 100644 --- a/nuttx/arch/arm/src/lm3s/lm3s_ethernet.c +++ b/nuttx/arch/arm/src/lm3s/lm3s_ethernet.c @@ -2,7 +2,7 @@ * arch/arm/src/lm3s/lm3s_ethernet.c * * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/lm3s/lm3s_flash.h b/nuttx/arch/arm/src/lm3s/lm3s_flash.h index 53b0e685a..83e388921 100644 --- a/nuttx/arch/arm/src/lm3s/lm3s_flash.h +++ b/nuttx/arch/arm/src/lm3s/lm3s_flash.h @@ -2,7 +2,7 @@ * arch/arm/src/lm3s/lm3s_flash.h * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/lm3s/lm3s_gpio.c b/nuttx/arch/arm/src/lm3s/lm3s_gpio.c index a57b792ab..c345d113c 100644 --- a/nuttx/arch/arm/src/lm3s/lm3s_gpio.c +++ b/nuttx/arch/arm/src/lm3s/lm3s_gpio.c @@ -3,7 +3,7 @@ * arch/arm/src/chip/lm3s_gpio.c * * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/lm3s/lm3s_gpio.h b/nuttx/arch/arm/src/lm3s/lm3s_gpio.h index 4b0456913..066666432 100644 --- a/nuttx/arch/arm/src/lm3s/lm3s_gpio.h +++ b/nuttx/arch/arm/src/lm3s/lm3s_gpio.h @@ -2,7 +2,7 @@ * arch/arm/src/lm3s/lm3s_gpio.h * * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/lm3s/lm3s_i2c.h b/nuttx/arch/arm/src/lm3s/lm3s_i2c.h index f306328e3..a5f0567b9 100644 --- a/nuttx/arch/arm/src/lm3s/lm3s_i2c.h +++ b/nuttx/arch/arm/src/lm3s/lm3s_i2c.h @@ -2,7 +2,7 @@ * arch/arm/src/lm3s/lm3s_i2c.h * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/lm3s/lm3s_internal.h b/nuttx/arch/arm/src/lm3s/lm3s_internal.h index 2ecc9c14a..9bfd67a5e 100644 --- a/nuttx/arch/arm/src/lm3s/lm3s_internal.h +++ b/nuttx/arch/arm/src/lm3s/lm3s_internal.h @@ -2,7 +2,7 @@ * arch/arm/src/lm3s/lm3s_internal.h * * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/lm3s/lm3s_irq.c b/nuttx/arch/arm/src/lm3s/lm3s_irq.c index d129f50cf..aa0ed6c87 100644 --- a/nuttx/arch/arm/src/lm3s/lm3s_irq.c +++ b/nuttx/arch/arm/src/lm3s/lm3s_irq.c @@ -3,7 +3,7 @@ * arch/arm/src/chip/lm3s_irq.c * * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/lm3s/lm3s_lowputc.c b/nuttx/arch/arm/src/lm3s/lm3s_lowputc.c index 81e312cf1..69ac56a9d 100644 --- a/nuttx/arch/arm/src/lm3s/lm3s_lowputc.c +++ b/nuttx/arch/arm/src/lm3s/lm3s_lowputc.c @@ -2,7 +2,7 @@ * arch/arm/src/lm3s/lm3s_lowputc.c * * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/lm3s/lm3s_memorymap.h b/nuttx/arch/arm/src/lm3s/lm3s_memorymap.h index 0bc420ff1..be0d8b58d 100644 --- a/nuttx/arch/arm/src/lm3s/lm3s_memorymap.h +++ b/nuttx/arch/arm/src/lm3s/lm3s_memorymap.h @@ -2,7 +2,7 @@ * arch/arm/src/lm3s/lm3s_memorymap.h * * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/lm3s/lm3s_ssi.c b/nuttx/arch/arm/src/lm3s/lm3s_ssi.c index 3b6abab2c..c756e2b6a 100755 --- a/nuttx/arch/arm/src/lm3s/lm3s_ssi.c +++ b/nuttx/arch/arm/src/lm3s/lm3s_ssi.c @@ -2,7 +2,7 @@ * arch/arm/src/lm32/lm3s_ssi.c * * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/lm3s/lm3s_ssi.h b/nuttx/arch/arm/src/lm3s/lm3s_ssi.h index 10832dda1..482dab326 100644 --- a/nuttx/arch/arm/src/lm3s/lm3s_ssi.h +++ b/nuttx/arch/arm/src/lm3s/lm3s_ssi.h @@ -2,7 +2,7 @@ * arch/arm/src/lm3s/lm3s_ssi.h * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/lm3s/lm3s_syscontrol.c b/nuttx/arch/arm/src/lm3s/lm3s_syscontrol.c index bd67a6ae1..e26789d32 100644 --- a/nuttx/arch/arm/src/lm3s/lm3s_syscontrol.c +++ b/nuttx/arch/arm/src/lm3s/lm3s_syscontrol.c @@ -3,7 +3,7 @@ * arch/arm/src/chip/lm3s_syscontrol.c * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/lm3s/lm3s_syscontrol.h b/nuttx/arch/arm/src/lm3s/lm3s_syscontrol.h index 773d3338f..c59b921c4 100644 --- a/nuttx/arch/arm/src/lm3s/lm3s_syscontrol.h +++ b/nuttx/arch/arm/src/lm3s/lm3s_syscontrol.h @@ -2,7 +2,7 @@ * arch/arm/src/lm3s/lm3s_syscontrol.h * * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/lm3s/lm3s_timerisr.c b/nuttx/arch/arm/src/lm3s/lm3s_timerisr.c index ad5aa279d..4d42af597 100644 --- a/nuttx/arch/arm/src/lm3s/lm3s_timerisr.c +++ b/nuttx/arch/arm/src/lm3s/lm3s_timerisr.c @@ -2,7 +2,7 @@ * arch/arm/src/lm3s/lm3s_timerisr.c * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/lm3s/lm3s_uart.h b/nuttx/arch/arm/src/lm3s/lm3s_uart.h index f807f0a2a..91bfb2266 100644 --- a/nuttx/arch/arm/src/lm3s/lm3s_uart.h +++ b/nuttx/arch/arm/src/lm3s/lm3s_uart.h @@ -2,7 +2,7 @@ * arch/arm/src/lm3s/lm3s_uart.h * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/lm3s/lm3s_vectors.S b/nuttx/arch/arm/src/lm3s/lm3s_vectors.S index 518685f42..71db122a0 100644 --- a/nuttx/arch/arm/src/lm3s/lm3s_vectors.S +++ b/nuttx/arch/arm/src/lm3s/lm3s_vectors.S @@ -3,7 +3,7 @@ * arch/arm/src/chip/lm3s_vectors.S * * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/lpc17xx/chip.h b/nuttx/arch/arm/src/lpc17xx/chip.h index ab671cf6d..982482017 100644 --- a/nuttx/arch/arm/src/lpc17xx/chip.h +++ b/nuttx/arch/arm/src/lpc17xx/chip.h @@ -2,7 +2,7 @@ * arch/arm/src/lpc17xx/chip.h * * Copyright (C) 2010-2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_clockconfig.c b/nuttx/arch/arm/src/lpc17xx/lpc17_clockconfig.c index 7f41371bf..635090e9f 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_clockconfig.c +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_clockconfig.c @@ -3,7 +3,7 @@ * arch/arm/src/chip/lpc17_clockconfig.c * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_clrpend.c b/nuttx/arch/arm/src/lpc17xx/lpc17_clrpend.c index d8f27e4db..242f7ac4f 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_clrpend.c +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_clrpend.c @@ -3,7 +3,7 @@ * arch/arm/src/chip/lpc17_clrpend.c * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_dac.h b/nuttx/arch/arm/src/lpc17xx/lpc17_dac.h index e1e7c1b40..a35e16eae 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_dac.h +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_dac.h @@ -2,7 +2,7 @@ * arch/arm/src/lpc17xx/lpc17_dac.h * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_emacram.h b/nuttx/arch/arm/src/lpc17xx/lpc17_emacram.h index 3561b72ba..700ad7ec3 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_emacram.h +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_emacram.h @@ -1,242 +1,242 @@ -/************************************************************************************
- * arch/arm/src/lpc17xx/lpc17_emacram.h
- *
- * Copyright (C) 2010 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_EMACRAM_H
-#define __ARCH_ARM_SRC_LPC17XX_LPC17_EMACRAM_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-#include "chip.h"
-#include "lpc17_memorymap.h"
-
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-/* Default, no-EMAC Case ************************************************************/
-/* Assume that all of AHB SRAM will be available for heap. If this is not true, then
- * LPC17_BANK0_HEAPSIZE will be undefined and redefined below.
- */
-
-#undef LPC17_BANK0_HEAPBASE
-#undef LPC17_BANK0_HEAPSIZE
-#ifdef LPC17_HAVE_BANK0
-# define LPC17_BANK0_HEAPBASE LPC17_SRAM_BANK0
-# define LPC17_BANK0_HEAPSIZE LPC17_BANK0_SIZE
-#endif
-
-/* Is networking enabled? Is the LPC17xx Ethernet device enabled? Does this chip have
- * and Ethernet controlloer? Yes... then we will replace the above default definitions.
- */
-
-#if defined(CONFIG_NET) && defined(CONFIG_LPC17_ETHERNET) && LPC17_NETHCONTROLLERS > 0
-
-/* EMAC RAM Configuration ***********************************************************/
-/* Is AHB SRAM available? */
-
-#ifndef LPC17_HAVE_BANK0
-# error "AHB SRAM Bank0 is not available for EMAC RAM"
-#endif
-
-/* Number of Tx descriptors */
-
-#ifndef CONFIG_NET_NTXDESC
-# define CONFIG_NET_NTXDESC 18
-#endif
-
-/* Number of Rx descriptors */
-
-#ifndef CONFIG_NET_NRXDESC
-# define CONFIG_NET_NRXDESC 18
-#endif
-
-/* Size of the region at the beginning of AHB SRAM 0 set set aside for the EMAC.
- * This size must fit within AHB SRAM Bank 0 and also be a multiple of 32-bit
- * words.
- */
-
-#ifndef CONFIG_NET_EMACRAM_SIZE
-# define CONFIG_NET_EMACRAM_SIZE LPC17_BANK0_SIZE
-#endif
-
-#if CONFIG_NET_EMACRAM_SIZE > LPC17_BANK0_SIZE
-# error "EMAC RAM size cannot exceed the size of AHB SRAM Bank 0"
-#endif
-
-#if (CONFIG_NET_EMACRAM_SIZE & 3) != 0
-# error "EMAC RAM size must be in multiples of 32-bit words"
-#endif
-
-/* Determine is there is any meaningful space left at the end of AHB Bank 0 that
- * could be added to the heap.
- */
-
-#undef LPC17_BANK0_HEAPBASE
-#undef LPC17_BANK0_HEAPSIZE
-#if CONFIG_NET_EMACRAM_SIZE < (LPC17_BANK0_SIZE-128)
-# define LPC17_BANK0_HEAPBASE (LPC17_SRAM_BANK0 + CONFIG_NET_EMACRAM_SIZE)
-# define LPC17_BANK0_HEAPSIZE (LPC17_BANK0_SIZE - CONFIG_NET_EMACRAM_SIZE)
-#endif
-
-/* Memory at the beginning of AHB SRAM, Bank 0 is set aside for EMAC Tx and Rx
- * descriptors. The position is not controllable, only the size of the region
- * is controllable.
- */
-
-#define LPC17_EMACRAM_BASE LPC17_SRAM_BANK0
-#define LPC17_EMACRAM_SIZE CONFIG_NET_EMACRAM_SIZE
-
-/* Descriptor Memory Layout *********************************************************/
-/* EMAC DMA RAM and descriptor definitions. The configured number of descriptors
- * will determine the organization and the size of the descriptor and status tables.
- * There is a complex interaction between the maximum packet size (CONFIG_NET_BUFSIZE)
- * and the number of Rx and Tx descriptors that can be suppored (CONFIG_NET_NRXDESC
- * and CONFIG_NET_NTXDESC): Small buffers -> more packets. This is something that
- * needs to be tuned for you system.
- *
- * For a 16Kb SRAM region, here is the relationship:
- *
- * 16384 <= ntx * (pktsize + 8 + 4) + nrx * (pktsize + 8 + 8)
- *
- * If ntx == nrx and pktsize == 424, then you could have
- * ntx = nrx = 18.
- *
- * An example with all of the details:
- *
- * NTXDESC=18 NRXDESC=18 CONFIG_NET_EMACRAM_SIZE=16Kb CONFIG_NET_BUFSIZE=420:
- * LPC17_TXDESCTAB_SIZE = 18*8 = 144
- * LPC17_TXSTATTAB_SIZE = 18*4 = 72
- * LPC17_TXTAB_SIZE = 216
- *
- * LPC17_RXDESCTAB_SIZE = 16*8 = 144
- * LPC17_RXSTATTAB_SIZE = 16*8 = 144
- * LPC17_TXTAB_SIZE = 288
- *
- * LPC17_DESCTAB_SIZE = 504
- * LPC17_DESC_BASE = LPC17_SRAM_BANK0 + 0x00004000 - 504
- * = LPC17_SRAM_BANK0 + 0x00003e08
- * LPC17_TXDESC_BASE = LPC17_SRAM_BANK0 + 0x00003e08
- * LPC17_TXSTAT_BASE = LPC17_SRAM_BANK0 + 0x00003e98
- * LPC17_RXDESC_BASE = LPC17_SRAM_BANK0 + 0x00003ee0
- * LPC17_RXSTAT_BASE = LPC17_SRAM_BANK0 + 0x00003f70
- *
- * LPC17_PKTMEM_BASE = LPC17_SRAM_BANK0
- * LPC17_PKTMEM_SIZE = 0x00004000-504 = 0x00003e40
- * LPC17_PKTMEM_END = LPC17_SRAM_BANK0 + 0x00003e08
-
- * LPC17_MAXPACKET_SIZE = ((420 + 3 + 2) & ~3) = 424
- * LPC17_NTXPKTS = 18
- * LPC17_NRXPKTS = 18
-
- * LPC17_TXBUFFER_SIZE = 18 * 424 = 0x00001dd0
- * LPC17_RXBUFFER_SIZE = 18 * 424 = 0x00001dd0
- * LPC17_BUFFER_SIZE = 0x00003ba0
-
- * LPC17_BUFFER_BASE = LPC17_SRAM_BANK0
- * LPC17_TXBUFFER_BASE = LPC17_SRAM_BANK0
- * LPC17_RXBUFFER_BASE = LPC17_SRAM_BANK0 + 0x00001dd0
- * LPC17_BUFFER_END = LPC17_SRAM_BANK0 + 0x00003ba0
- *
- * Then the check LPC17_BUFFER_END < LPC17_PKTMEM_END passes. The amount of
- * unused memory is small: 0x00003e08-0x00003ba0 or about 616 bytes -- not
- * enough for two more packets.
- *
- * [It is also possible, with some effort, to reclaim any unused
- * SRAM for the use in the heap. But that has not yet been pursued.]
- */
-
-#define LPC17_TXDESCTAB_SIZE (CONFIG_NET_NTXDESC*LPC17_TXDESC_SIZE)
-#define LPC17_TXSTATTAB_SIZE (CONFIG_NET_NTXDESC*LPC17_TXSTAT_SIZE)
-#define LPC17_TXTAB_SIZE (LPC17_TXDESCTAB_SIZE+LPC17_TXSTATTAB_SIZE)
-
-#define LPC17_RXDESCTAB_SIZE (CONFIG_NET_NRXDESC*LPC17_RXDESC_SIZE)
-#define LPC17_RXSTATTAB_SIZE (CONFIG_NET_NRXDESC*LPC17_RXSTAT_SIZE)
-#define LPC17_RXTAB_SIZE (LPC17_RXDESCTAB_SIZE+LPC17_RXSTATTAB_SIZE)
-
-#define LPC17_DESCTAB_SIZE (LPC17_TXTAB_SIZE+LPC17_RXTAB_SIZE)
-
-/* Descriptor table memory organization. Descriptor tables are packed at
- * the end of AHB SRAM, Bank 0. The beginning of bank 0 is reserved for
- * packet memory.
- */
-
-#define LPC17_DESC_BASE (LPC17_EMACRAM_BASE+LPC17_EMACRAM_SIZE-LPC17_DESCTAB_SIZE)
-#define LPC17_TXDESC_BASE LPC17_DESC_BASE
-#define LPC17_TXSTAT_BASE (LPC17_TXDESC_BASE+LPC17_TXDESCTAB_SIZE)
-#define LPC17_RXDESC_BASE (LPC17_TXSTAT_BASE+LPC17_TXSTATTAB_SIZE)
-#define LPC17_RXSTAT_BASE (LPC17_RXDESC_BASE + LPC17_RXDESCTAB_SIZE)
-
-/* Now carve up the beginning of SRAM for packet memory. The size of a
- * packet buffer is related to the size of the MTU. We'll round sizes up
- * to multiples of 256 bytes.
- */
-
-#define LPC17_PKTMEM_BASE LPC17_EMACRAM_BASE
-#define LPC17_PKTMEM_SIZE (LPC17_EMACRAM_SIZE-LPC17_DESCTAB_SIZE)
-#define LPC17_PKTMEM_END (LPC17_EMACRAM_BASE+LPC17_PKTMEM_SIZE)
-
-#define LPC17_MAXPACKET_SIZE ((CONFIG_NET_BUFSIZE + CONFIG_NET_GUARDSIZE + 3) & ~3)
-#define LPC17_NTXPKTS CONFIG_NET_NTXDESC
-#define LPC17_NRXPKTS CONFIG_NET_NRXDESC
-
-#define LPC17_TXBUFFER_SIZE (LPC17_NTXPKTS * LPC17_MAXPACKET_SIZE)
-#define LPC17_RXBUFFER_SIZE (LPC17_NRXPKTS * LPC17_MAXPACKET_SIZE)
-#define LPC17_BUFFER_SIZE (LPC17_TXBUFFER_SIZE + LPC17_RXBUFFER_SIZE)
-
-#define LPC17_BUFFER_BASE LPC17_PKTMEM_BASE
-#define LPC17_TXBUFFER_BASE LPC17_BUFFER_BASE
-#define LPC17_RXBUFFER_BASE (LPC17_TXBUFFER_BASE + LPC17_TXBUFFER_SIZE)
-#define LPC17_BUFFER_END (LPC17_BUFFER_BASE + LPC17_BUFFER_SIZE)
-
-#if LPC17_BUFFER_END > LPC17_PKTMEM_END
-# error "Packet memory overlaps descriptor tables"
-#endif
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-/************************************************************************************
- * Public Functions
- ************************************************************************************/
-
-#endif /* CONFIG_NET && CONFIG_LPC17_ETHERNET && LPC17_NETHCONTROLLERS > 0*/
-#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_EMACRAM_H */
+/************************************************************************************ + * arch/arm/src/lpc17xx/lpc17_emacram.h + * + * Copyright (C) 2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_EMACRAM_H +#define __ARCH_ARM_SRC_LPC17XX_LPC17_EMACRAM_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> +#include "chip.h" +#include "lpc17_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ +/* Default, no-EMAC Case ************************************************************/ +/* Assume that all of AHB SRAM will be available for heap. If this is not true, then + * LPC17_BANK0_HEAPSIZE will be undefined and redefined below. + */ + +#undef LPC17_BANK0_HEAPBASE +#undef LPC17_BANK0_HEAPSIZE +#ifdef LPC17_HAVE_BANK0 +# define LPC17_BANK0_HEAPBASE LPC17_SRAM_BANK0 +# define LPC17_BANK0_HEAPSIZE LPC17_BANK0_SIZE +#endif + +/* Is networking enabled? Is the LPC17xx Ethernet device enabled? Does this chip have + * and Ethernet controlloer? Yes... then we will replace the above default definitions. + */ + +#if defined(CONFIG_NET) && defined(CONFIG_LPC17_ETHERNET) && LPC17_NETHCONTROLLERS > 0 + +/* EMAC RAM Configuration ***********************************************************/ +/* Is AHB SRAM available? */ + +#ifndef LPC17_HAVE_BANK0 +# error "AHB SRAM Bank0 is not available for EMAC RAM" +#endif + +/* Number of Tx descriptors */ + +#ifndef CONFIG_NET_NTXDESC +# define CONFIG_NET_NTXDESC 18 +#endif + +/* Number of Rx descriptors */ + +#ifndef CONFIG_NET_NRXDESC +# define CONFIG_NET_NRXDESC 18 +#endif + +/* Size of the region at the beginning of AHB SRAM 0 set set aside for the EMAC. + * This size must fit within AHB SRAM Bank 0 and also be a multiple of 32-bit + * words. + */ + +#ifndef CONFIG_NET_EMACRAM_SIZE +# define CONFIG_NET_EMACRAM_SIZE LPC17_BANK0_SIZE +#endif + +#if CONFIG_NET_EMACRAM_SIZE > LPC17_BANK0_SIZE +# error "EMAC RAM size cannot exceed the size of AHB SRAM Bank 0" +#endif + +#if (CONFIG_NET_EMACRAM_SIZE & 3) != 0 +# error "EMAC RAM size must be in multiples of 32-bit words" +#endif + +/* Determine is there is any meaningful space left at the end of AHB Bank 0 that + * could be added to the heap. + */ + +#undef LPC17_BANK0_HEAPBASE +#undef LPC17_BANK0_HEAPSIZE +#if CONFIG_NET_EMACRAM_SIZE < (LPC17_BANK0_SIZE-128) +# define LPC17_BANK0_HEAPBASE (LPC17_SRAM_BANK0 + CONFIG_NET_EMACRAM_SIZE) +# define LPC17_BANK0_HEAPSIZE (LPC17_BANK0_SIZE - CONFIG_NET_EMACRAM_SIZE) +#endif + +/* Memory at the beginning of AHB SRAM, Bank 0 is set aside for EMAC Tx and Rx + * descriptors. The position is not controllable, only the size of the region + * is controllable. + */ + +#define LPC17_EMACRAM_BASE LPC17_SRAM_BANK0 +#define LPC17_EMACRAM_SIZE CONFIG_NET_EMACRAM_SIZE + +/* Descriptor Memory Layout *********************************************************/ +/* EMAC DMA RAM and descriptor definitions. The configured number of descriptors + * will determine the organization and the size of the descriptor and status tables. + * There is a complex interaction between the maximum packet size (CONFIG_NET_BUFSIZE) + * and the number of Rx and Tx descriptors that can be suppored (CONFIG_NET_NRXDESC + * and CONFIG_NET_NTXDESC): Small buffers -> more packets. This is something that + * needs to be tuned for you system. + * + * For a 16Kb SRAM region, here is the relationship: + * + * 16384 <= ntx * (pktsize + 8 + 4) + nrx * (pktsize + 8 + 8) + * + * If ntx == nrx and pktsize == 424, then you could have + * ntx = nrx = 18. + * + * An example with all of the details: + * + * NTXDESC=18 NRXDESC=18 CONFIG_NET_EMACRAM_SIZE=16Kb CONFIG_NET_BUFSIZE=420: + * LPC17_TXDESCTAB_SIZE = 18*8 = 144 + * LPC17_TXSTATTAB_SIZE = 18*4 = 72 + * LPC17_TXTAB_SIZE = 216 + * + * LPC17_RXDESCTAB_SIZE = 16*8 = 144 + * LPC17_RXSTATTAB_SIZE = 16*8 = 144 + * LPC17_TXTAB_SIZE = 288 + * + * LPC17_DESCTAB_SIZE = 504 + * LPC17_DESC_BASE = LPC17_SRAM_BANK0 + 0x00004000 - 504 + * = LPC17_SRAM_BANK0 + 0x00003e08 + * LPC17_TXDESC_BASE = LPC17_SRAM_BANK0 + 0x00003e08 + * LPC17_TXSTAT_BASE = LPC17_SRAM_BANK0 + 0x00003e98 + * LPC17_RXDESC_BASE = LPC17_SRAM_BANK0 + 0x00003ee0 + * LPC17_RXSTAT_BASE = LPC17_SRAM_BANK0 + 0x00003f70 + * + * LPC17_PKTMEM_BASE = LPC17_SRAM_BANK0 + * LPC17_PKTMEM_SIZE = 0x00004000-504 = 0x00003e40 + * LPC17_PKTMEM_END = LPC17_SRAM_BANK0 + 0x00003e08 + + * LPC17_MAXPACKET_SIZE = ((420 + 3 + 2) & ~3) = 424 + * LPC17_NTXPKTS = 18 + * LPC17_NRXPKTS = 18 + + * LPC17_TXBUFFER_SIZE = 18 * 424 = 0x00001dd0 + * LPC17_RXBUFFER_SIZE = 18 * 424 = 0x00001dd0 + * LPC17_BUFFER_SIZE = 0x00003ba0 + + * LPC17_BUFFER_BASE = LPC17_SRAM_BANK0 + * LPC17_TXBUFFER_BASE = LPC17_SRAM_BANK0 + * LPC17_RXBUFFER_BASE = LPC17_SRAM_BANK0 + 0x00001dd0 + * LPC17_BUFFER_END = LPC17_SRAM_BANK0 + 0x00003ba0 + * + * Then the check LPC17_BUFFER_END < LPC17_PKTMEM_END passes. The amount of + * unused memory is small: 0x00003e08-0x00003ba0 or about 616 bytes -- not + * enough for two more packets. + * + * [It is also possible, with some effort, to reclaim any unused + * SRAM for the use in the heap. But that has not yet been pursued.] + */ + +#define LPC17_TXDESCTAB_SIZE (CONFIG_NET_NTXDESC*LPC17_TXDESC_SIZE) +#define LPC17_TXSTATTAB_SIZE (CONFIG_NET_NTXDESC*LPC17_TXSTAT_SIZE) +#define LPC17_TXTAB_SIZE (LPC17_TXDESCTAB_SIZE+LPC17_TXSTATTAB_SIZE) + +#define LPC17_RXDESCTAB_SIZE (CONFIG_NET_NRXDESC*LPC17_RXDESC_SIZE) +#define LPC17_RXSTATTAB_SIZE (CONFIG_NET_NRXDESC*LPC17_RXSTAT_SIZE) +#define LPC17_RXTAB_SIZE (LPC17_RXDESCTAB_SIZE+LPC17_RXSTATTAB_SIZE) + +#define LPC17_DESCTAB_SIZE (LPC17_TXTAB_SIZE+LPC17_RXTAB_SIZE) + +/* Descriptor table memory organization. Descriptor tables are packed at + * the end of AHB SRAM, Bank 0. The beginning of bank 0 is reserved for + * packet memory. + */ + +#define LPC17_DESC_BASE (LPC17_EMACRAM_BASE+LPC17_EMACRAM_SIZE-LPC17_DESCTAB_SIZE) +#define LPC17_TXDESC_BASE LPC17_DESC_BASE +#define LPC17_TXSTAT_BASE (LPC17_TXDESC_BASE+LPC17_TXDESCTAB_SIZE) +#define LPC17_RXDESC_BASE (LPC17_TXSTAT_BASE+LPC17_TXSTATTAB_SIZE) +#define LPC17_RXSTAT_BASE (LPC17_RXDESC_BASE + LPC17_RXDESCTAB_SIZE) + +/* Now carve up the beginning of SRAM for packet memory. The size of a + * packet buffer is related to the size of the MTU. We'll round sizes up + * to multiples of 256 bytes. + */ + +#define LPC17_PKTMEM_BASE LPC17_EMACRAM_BASE +#define LPC17_PKTMEM_SIZE (LPC17_EMACRAM_SIZE-LPC17_DESCTAB_SIZE) +#define LPC17_PKTMEM_END (LPC17_EMACRAM_BASE+LPC17_PKTMEM_SIZE) + +#define LPC17_MAXPACKET_SIZE ((CONFIG_NET_BUFSIZE + CONFIG_NET_GUARDSIZE + 3) & ~3) +#define LPC17_NTXPKTS CONFIG_NET_NTXDESC +#define LPC17_NRXPKTS CONFIG_NET_NRXDESC + +#define LPC17_TXBUFFER_SIZE (LPC17_NTXPKTS * LPC17_MAXPACKET_SIZE) +#define LPC17_RXBUFFER_SIZE (LPC17_NRXPKTS * LPC17_MAXPACKET_SIZE) +#define LPC17_BUFFER_SIZE (LPC17_TXBUFFER_SIZE + LPC17_RXBUFFER_SIZE) + +#define LPC17_BUFFER_BASE LPC17_PKTMEM_BASE +#define LPC17_TXBUFFER_BASE LPC17_BUFFER_BASE +#define LPC17_RXBUFFER_BASE (LPC17_TXBUFFER_BASE + LPC17_TXBUFFER_SIZE) +#define LPC17_BUFFER_END (LPC17_BUFFER_BASE + LPC17_BUFFER_SIZE) + +#if LPC17_BUFFER_END > LPC17_PKTMEM_END +# error "Packet memory overlaps descriptor tables" +#endif + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* CONFIG_NET && CONFIG_LPC17_ETHERNET && LPC17_NETHCONTROLLERS > 0*/ +#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_EMACRAM_H */ diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_gpdma.c b/nuttx/arch/arm/src/lpc17xx/lpc17_gpdma.c index 1fb27ccc9..f567d52c0 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_gpdma.c +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_gpdma.c @@ -2,7 +2,7 @@ * arch/arm/src/lpc17xx/lpc17_gpdma.c * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_gpdma.h b/nuttx/arch/arm/src/lpc17xx/lpc17_gpdma.h index d4803eba5..c0e70efa5 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_gpdma.h +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_gpdma.h @@ -1,417 +1,417 @@ -/************************************************************************************
- * arch/arm/src/lpc17xx/lpc17_gpdma.h
- *
- * Copyright (C) 2010 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_GPDMA_H
-#define __ARCH_ARM_SRC_LPC17XX_LPC17_GPDMA_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-
-#include "chip.h"
-#include "lpc17_memorymap.h"
-
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-
-/* Register offsets *****************************************************************/
-
-/* General registers (see also LPC17_SYSCON_DMAREQSEL_OFFSET in lpc17_syscon.h) */
-
-#define LPC17_DMA_INTST_OFFSET 0x0000 /* DMA Interrupt Status Register */
-#define LPC17_DMA_INTTCST_OFFSET 0x0004 /* DMA Interrupt Terminal Count Request Status Register */
-#define LPC17_DMA_INTTCCLR_OFFSET 0x0008 /* DMA Interrupt Terminal Count Request Clear Register */
-#define LPC17_DMA_INTERRST_OFFSET 0x000c /* DMA Interrupt Error Status Register */
-#define LPC17_DMA_INTERRCLR_OFFSET 0x0010 /* DMA Interrupt Error Clear Register */
-#define LPC17_DMA_RAWINTTCST_OFFSET 0x0014 /* DMA Raw Interrupt Terminal Count Status Register */
-#define LPC17_DMA_RAWINTERRST_OFFSET 0x0018 /* DMA Raw Error Interrupt Status Register */
-#define LPC17_DMA_ENBLDCHNS_OFFSET 0x001c /* DMA Enabled Channel Register */
-#define LPC17_DMA_SOFTBREQ_OFFSET 0x0020 /* DMA Software Burst Request Register */
-#define LPC17_DMA_SOFTSREQ_OFFSET 0x0024 /* DMA Software Single Request Register */
-#define LPC17_DMA_SOFTLBREQ_OFFSET 0x0028 /* DMA Software Last Burst Request Register */
-#define LPC17_DMA_SOFTLSREQ_OFFSET 0x002c /* DMA Software Last Single Request Register */
-#define LPC17_DMA_CONFIG_OFFSET 0x0030 /* DMA Configuration Register */
-#define LPC17_DMA_SYNC_OFFSET 0x0034 /* DMA Synchronization Register */
-
-/* Channel Registers */
-
-#define LPC17_DMA_CHAN_OFFSET(n) (0x0100 + ((n) << 5)) /* n=0,1,...7 */
-
-#define LPC17_DMACH_SRCADDR_OFFSET 0x0000 /* DMA Channel Source Address Register */
-#define LPC17_DMACH_DESTADDR_OFFSET 0x0004 /* DMA Channel Destination Address Register */
-#define LPC17_DMACH_LLI_OFFSET 0x0008 /* DMA Channel Linked List Item Register */
-#define LPC17_DMACH_CONTROL_OFFSET 0x000c /* DMA Channel Control Register */
-#define LPC17_DMACH_CONFIG_OFFSET 0x0010 /* DMA Channel Configuration Register */
-
-#define LPC17_DMACH0_SRCADDR_OFFSET (0x100+LPC17_DMACH_SRCADDR_OFFSET)
-#define LPC17_DMACH0_DESTADDR_OFFSET (0x100+LPC17_DMACH_DESTADDR_OFFSET)
-#define LPC17_DMACH0_LLI_OFFSET (0x100+LPC17_DMACH_LLI_OFFSET)
-#define LPC17_DMACH0_CONTROL_OFFSET (0x100+LPC17_DMACH_CONTROL_OFFSET)
-#define LPC17_DMACH0_CONFIG_OFFSET (0x100+LPC17_DMACH_CONFIG_OFFSET)
-
-#define LPC17_DMACH1_SRCADDR_OFFSET (0x120+LPC17_DMACH_SRCADDR_OFFSET)
-#define LPC17_DMACH1_DESTADDR_OFFSET (0x120+LPC17_DMACH_DESTADDR_OFFSET)
-#define LPC17_DMACH1_LLI_OFFSET (0x120+LPC17_DMACH_LLI_OFFSET)
-#define LPC17_DMACH1_CONTROL_OFFSET (0x120+LPC17_DMACH_CONTROL_OFFSET)
-#define LPC17_DMACH1_CONFIG_OFFSET (0x120+LPC17_DMACH_CONFIG_OFFSET)
-
-#define LPC17_DMACH2_SRCADDR_OFFSET (0x140+LPC17_DMACH_SRCADDR_OFFSET)
-#define LPC17_DMACH2_DESTADDR_OFFSET (0x140+LPC17_DMACH_DESTADDR_OFFSET)
-#define LPC17_DMACH2_LLI_OFFSET (0x140+LPC17_DMACH_LLI_OFFSET)
-#define LPC17_DMACH2_CONTROL_OFFSET (0x140+LPC17_DMACH_CONTROL_OFFSET)
-#define LPC17_DMACH2_CONFIG_OFFSET (0x140+LPC17_DMACH_CONFIG_OFFSET)
-
-#define LPC17_DMACH3_SRCADDR_OFFSET (0x160+LPC17_DMACH_SRCADDR_OFFSET)
-#define LPC17_DMACH3_DESTADDR_OFFSET (0x160+LPC17_DMACH_DESTADDR_OFFSET)
-#define LPC17_DMACH3_LLI_OFFSET (0x160+LPC17_DMACH_LLI_OFFSET)
-#define LPC17_DMACH3_CONTROL_OFFSET (0x160+LPC17_DMACH_CONTROL_OFFSET)
-#define LPC17_DMACH3_CONFIG_OFFSET (0x160+LPC17_DMACH_CONFIG_OFFSET)
-
-#define LPC17_DMACH4_SRCADDR_OFFSET (0x180+LPC17_DMACH_SRCADDR_OFFSET)
-#define LPC17_DMACH4_DESTADDR_OFFSET (0x180+LPC17_DMACH_DESTADDR_OFFSET)
-#define LPC17_DMACH4_LLI_OFFSET (0x180+LPC17_DMACH_LLI_OFFSET)
-#define LPC17_DMACH4_CONTROL_OFFSET (0x180+LPC17_DMACH_CONTROL_OFFSET)
-#define LPC17_DMACH4_CONFIG_OFFSET (0x180+LPC17_DMACH_CONFIG_OFFSET)
-
-#define LPC17_DMACH5_SRCADDR_OFFSET (0x1a0+LPC17_DMACH_SRCADDR_OFFSET)
-#define LPC17_DMACH5_DESTADDR_OFFSET (0x1a0+LPC17_DMACH_DESTADDR_OFFSET)
-#define LPC17_DMACH5_LLI_OFFSET (0x1a0+LPC17_DMACH_LLI_OFFSET)
-#define LPC17_DMACH5_CONTROL_OFFSET (0x1a0+LPC17_DMACH_CONTROL_OFFSET)
-#define LPC17_DMACH5_CONFIG_OFFSET (0x1a0+LPC17_DMACH_CONFIG_OFFSET)
-
-#define LPC17_DMACH6_SRCADDR_OFFSET (0x1c0+LPC17_DMACH_SRCADDR_OFFSET)
-#define LPC17_DMACH6_DESTADDR_OFFSET (0x1c0+LPC17_DMACH_DESTADDR_OFFSET)
-#define LPC17_DMACH6_LLI_OFFSET (0x1c0+LPC17_DMACH_LLI_OFFSET)
-#define LPC17_DMACH6_CONTROL_OFFSET (0x1c0+LPC17_DMACH_CONTROL_OFFSET)
-#define LPC17_DMACH6_CONFIG_OFFSET (0x1c0+LPC17_DMACH_CONFIG_OFFSET)
-
-#define LPC17_DMACH7_SRCADDR_OFFSET (0x1e0+LPC17_DMACH_SRCADDR_OFFSET)
-#define LPC17_DMACH7_DESTADDR_OFFSET (0x1e0+LPC17_DMACH_DESTADDR_OFFSET)
-#define LPC17_DMACH7_LLI_OFFSET (0x1e0+LPC17_DMACH_LLI_OFFSET)
-#define LPC17_DMACH7_CONTROL_OFFSET (0x1e0+LPC17_DMACH_CONTROL_OFFSET)
-#define LPC17_DMACH7_CONFIG_OFFSET (0x1e0+LPC17_DMACH_CONFIG_OFFSET)
-
-/* Register addresses ***************************************************************/
-/* General registers (see also LPC17_SYSCON_DMAREQSEL in lpc17_syscon.h) */
-
-#define LPC17_DMA_INTST (LPC17_GPDMA_BASE+LPC17_DMA_INTST_OFFSET)
-#define LPC17_DMA_INTTCST (LPC17_GPDMA_BASE+LPC17_DMA_INTTCST_OFFSET)
-#define LPC17_DMA_INTTCCLR (LPC17_GPDMA_BASE+LPC17_DMA_INTTCCLR_OFFSET)
-#define LPC17_DMA_INTERRST (LPC17_GPDMA_BASE+LPC17_DMA_INTERRST_OFFSET)
-#define LPC17_DMA_INTERRCLR (LPC17_GPDMA_BASE+LPC17_DMA_INTERRCLR_OFFSET)
-#define LPC17_DMA_RAWINTTCST (LPC17_GPDMA_BASE+LPC17_DMA_RAWINTTCST_OFFSET)
-#define LPC17_DMA_RAWINTERRST (LPC17_GPDMA_BASE+LPC17_DMA_RAWINTERRST_OFFSET)
-#define LPC17_DMA_ENBLDCHNS (LPC17_GPDMA_BASE+LPC17_DMA_ENBLDCHNS_OFFSET)
-#define LPC17_DMA_SOFTBREQ (LPC17_GPDMA_BASE+LPC17_DMA_SOFTBREQ_OFFSET)
-#define LPC17_DMA_SOFTSREQ (LPC17_GPDMA_BASE+LPC17_DMA_SOFTSREQ_OFFSET)
-#define LPC17_DMA_SOFTLBREQ (LPC17_GPDMA_BASE+LPC17_DMA_SOFTLBREQ_OFFSET)
-#define LPC17_DMA_SOFTLSREQ (LPC17_GPDMA_BASE+LPC17_DMA_SOFTLSREQ_OFFSET)
-#define LPC17_DMA_CONFIG (LPC17_GPDMA_BASE+LPC17_DMA_CONFIG_OFFSET)
-#define LPC17_DMA_SYNC (LPC17_GPDMA_BASE+LPC17_DMA_SYNC_OFFSET)
-
-/* Channel Registers */
-
-#define LPC17_DMACH_BASE(n) (LPC17_GPDMA_BASE+LPC17_DMA_CHAN_OFFSET(n))
-
-#define LPC17_DMACH_SRCADDR(n) (LPC17_DMACH_BASE(n)+LPC17_DMACH_SRCADDR_OFFSET)
-#define LPC17_DMACH_DESTADDR(n) (LPC17_DMACH_BASE(n)+LPC17_DMACH_DESTADDR_OFFSET)
-#define LPC17_DMACH_LLI(n) (LPC17_DMACH_BASE(n)+LPC17_DMACH_LLI_OFFSET)
-#define LPC17_DMACH_CONTROL(n) (LPC17_DMACH_BASE(n)+LPC17_DMACH_CONTROL_OFFSET)
-#define LPC17_DMACH_CONFIG(n) (LPC17_DMACH_BASE(n)+LPC17_DMACH_CONFIG_OFFSET)
-
-#define LPC17_DMACH0_SRCADDR (LPC17_GPDMA_BASE+LPC17_DMACH0_SRCADDR_OFFSET)
-#define LPC17_DMACH0_DESTADDR (LPC17_GPDMA_BASE+LPC17_DMACH0_DESTADDR_OFFSET)
-#define LPC17_DMACH0_LLI (LPC17_GPDMA_BASE+LPC17_DMACH0_LLI_OFFSET)
-#define LPC17_DMACH0_CONTROL (LPC17_GPDMA_BASE+LPC17_DMACH0_CONTROL_OFFSET)
-#define LPC17_DMACH0_CONFIG (LPC17_GPDMA_BASE+LPC17_DMACH0_CONFIG_OFFSET)
-
-#define LPC17_DMACH1_SRCADDR (LPC17_GPDMA_BASE+LPC17_DMACH1_SRCADDR_OFFSET)
-#define LPC17_DMACH1_DESTADDR (LPC17_GPDMA_BASE+LPC17_DMACH1_DESTADDR_OFFSET)
-#define LPC17_DMACH1_LLI (LPC17_GPDMA_BASE+LPC17_DMACH1_LLI_OFFSET)
-#define LPC17_DMACH1_CONTROL (LPC17_GPDMA_BASE+LPC17_DMACH1_CONTROL_OFFSET)
-#define LPC17_DMACH1_CONFIG (LPC17_GPDMA_BASE+LPC17_DMACH1_CONFIG_OFFSET)
-
-#define LPC17_DMACH2_SRCADDR (LPC17_GPDMA_BASE+LPC17_DMACH2_SRCADDR_OFFSET)
-#define LPC17_DMACH2_DESTADDR (LPC17_GPDMA_BASE+LPC17_DMACH2_DESTADDR_OFFSET)
-#define LPC17_DMACH2_LLI (LPC17_GPDMA_BASE+LPC17_DMACH2_LLI_OFFSET)
-#define LPC17_DMACH2_CONTROL (LPC17_GPDMA_BASE+LPC17_DMACH2_CONTROL_OFFSET)
-#define LPC17_DMACH2_CONFIG (LPC17_GPDMA_BASE+LPC17_DMACH2_CONFIG_OFFSET)
-
-#define LPC17_DMACH3_SRCADDR (LPC17_GPDMA_BASE+LPC17_DMACH3_SRCADDR_OFFSET)
-#define LPC17_DMACH3_DESTADDR (LPC17_GPDMA_BASE+LPC17_DMACH3_DESTADDR_OFFSET)
-#define LPC17_DMACH3_LLI (LPC17_GPDMA_BASE+LPC17_DMACH3_LLI_OFFSET)
-#define LPC17_DMACH3_CONTROL (LPC17_GPDMA_BASE+LPC17_DMACH3_CONTROL_OFFSET)
-#define LPC17_DMACH3_CONFIG (LPC17_GPDMA_BASE+LPC17_DMACH3_CONFIG_OFFSET)
-
-#define LPC17_DMACH4_SRCADDR (LPC17_GPDMA_BASE+LPC17_DMACH4_SRCADDR_OFFSET)
-#define LPC17_DMACH4_DESTADDR (LPC17_GPDMA_BASE+LPC17_DMACH4_DESTADDR_OFFSET)
-#define LPC17_DMACH4_LLI (LPC17_GPDMA_BASE+LPC17_DMACH4_LLI_OFFSET)
-#define LPC17_DMACH4_CONTROL (LPC17_GPDMA_BASE+LPC17_DMACH4_CONTROL_OFFSET)
-#define LPC17_DMACH4_CONFIG (LPC17_GPDMA_BASE+LPC17_DMACH4_CONFIG_OFFSET)
-
-#define LPC17_DMACH5_SRCADDR (LPC17_GPDMA_BASE+LPC17_DMACH5_SRCADDR_OFFSET)
-#define LPC17_DMACH5_DESTADDR (LPC17_GPDMA_BASE+LPC17_DMACH5_DESTADDR_OFFSET)
-#define LPC17_DMACH5_LLI (LPC17_GPDMA_BASE+LPC17_DMACH5_LLI_OFFSET)
-#define LPC17_DMACH5_CONTROL (LPC17_GPDMA_BASE+LPC17_DMACH5_CONTROL_OFFSET)
-#define LPC17_DMACH5_CONFIG (LPC17_GPDMA_BASE+LPC17_DMACH5_CONFIG_OFFSET)
-
-#define LPC17_DMACH6_SRCADDR (LPC17_GPDMA_BASE+LPC17_DMACH6_SRCADDR_OFFSET)
-#define LPC17_DMACH6_DESTADDR (LPC17_GPDMA_BASE+LPC17_DMACH6_DESTADDR_OFFSET)
-#define LPC17_DMACH6_LLI (LPC17_GPDMA_BASE+LPC17_DMACH6_LLI_OFFSET)
-#define LPC17_DMACH6_CONTROL (LPC17_GPDMA_BASE+LPC17_DMACH6_CONTROL_OFFSET)
-#define LPC17_DMACH6_CONFIG (LPC17_GPDMA_BASE+LPC17_DMACH6_CONFIG_OFFSET)
-
-#define LPC17_DMACH7_SRCADDR (LPC17_GPDMA_BASE+LPC17_DMACH7_SRCADDR_OFFSET)
-#define LPC17_DMACH7_DESTADDR (LPC17_GPDMA_BASE+LPC17_DMACH7_DESTADDR_OFFSET)
-#define LPC17_DMACH7_LLI (LPC17_GPDMA_BASE+LPC17_DMACH7_LLI_OFFSET)
-#define LPC17_DMACH7_CONTROL (LPC17_GPDMA_BASE+LPC17_DMACH7_CONTROL_OFFSET)
-#define LPC17_DMACH7_CONFIG (LPC17_GPDMA_BASE+LPC17_DMACH7_CONFIG_OFFSET)
-
-/* Register bit definitions *********************************************************/
-/* DMA request connections */
-
-#define DMA_REQ_SSP0TX (0)
-#define DMA_REQ_SSP0RX (1)
-#define DMA_REQ_SSP1TX (2)
-#define DMA_REQ_SSP1RX (3)
-#define DMA_REQ_ADC (4)
-#define DMA_REQ_I2SCH0 (5)
-#define DMA_REQ_I2SCH1 (6)
-#define DMA_REQ_DAC (7)
-
-#define DMA_REQ_UART0TX (8)
-#define DMA_REQ_UART0RX (9)
-#define DMA_REQ_UART1TX (10)
-#define DMA_REQ_UART1RX (11)
-#define DMA_REQ_UART2TX (12)
-#define DMA_REQ_UART2RX (13)
-#define DMA_REQ_UART3TX (14)
-#define DMA_REQ_UART3RX (15)
-
-#define DMA_REQ_MAT0p0 (8)
-#define DMA_REQ_MAT0p1 (9)
-#define DMA_REQ_MAT1p0 (10)
-#define DMA_REQ_MAT1p1 (11)
-#define DMA_REQ_MAT2p0 (12)
-#define DMA_REQ_MAT2p1 (13)
-#define DMA_REQ_MAT3p0 (14)
-#define DMA_REQ_MAT3p1 (15)
-
-/* General registers (see also LPC17_SYSCON_DMAREQSEL in lpc17_syscon.h) */
-/* Fach of the following registers, bits 0-7 controls DMA channels 9-7,
- * respectively. Bits 8-31 are reserved.
- *
- * DMA Interrupt Status Register
- * DMA Interrupt Terminal Count Request Status Register
- * DMA Interrupt Terminal Count Request Clear Register
- * DMA Interrupt Error Status Register
- * DMA Interrupt Error Clear Register
- * DMA Raw Interrupt Terminal Count Status Register
- * DMA Raw Error Interrupt Status Register
- * DMA Enabled Channel Register
- */
-
-#define DMACH(n) (1 << (n)) /* n=0,1,...7 */
-
-/* For each of the following registers, bits 0-15 represent a set of encoded
- * DMA sources. Bits 16-31 are reserved in each case.
- *
- * DMA Software Burst Request Register
- * DMA Software Single Request Register
- * DMA Software Last Burst Request Register
- * DMA Software Last Single Request Register
- * DMA Synchronization Register
- */
-
-#define DMA_REQ_SSP0TX_BIT (1 << DMA_REQ_SSP0TX)
-#define DMA_REQ_SSP0RX_BIT (1 << DMA_REQ_SSP0RX)
-#define DMA_REQ_SSP1TX_BIT (1 << DMA_REQ_SSP1TX)
-#define DMA_REQ_SSP1RX_BIT (1 << DMA_REQ_SSP0RX)
-#define DMA_REQ_ADC_BIT (1 << DMA_REQ_ADC)
-#define DMA_REQ_I2SCH0_BIT (1 << DMA_REQ_I2SCH0)
-#define DMA_REQ_I2SCH1_BIT (1 << DMA_REQ_I2SCH1)
-#define DMA_REQ_DAC_BIT (1 << DMA_REQ_DAC)
-
-#define DMA_REQ_UART0TX_BIT (1 << DMA_REQ_UART0TX)
-#define DMA_REQ_UART0RX_BIT (1 << DMA_REQ_UART0RX)
-#define DMA_REQ_UART1TX_BIT (1 << DMA_REQ_UART1TX)
-#define DMA_REQ_UART1RX_BIT (1 << DMA_REQ_UART1RX)
-#define DMA_REQ_UART2TX_BIT (1 << DMA_REQ_UART2TX)
-#define DMA_REQ_UART2RX_BIT (1 << DMA_REQ_UART2RX)
-#define DMA_REQ_UART3TX_BIT (1 << DMA_REQ_UART3TX)
-#define DMA_REQ_UART3RX_BIT (1 << DMA_REQ_UART3RX)
-
-#define DMA_REQ_MAT0p0_BIT (1 << DMA_REQ_MAT0p0)
-#define DMA_REQ_MAT0p1_BIT (1 << DMA_REQ_MAT0p1)
-#define DMA_REQ_MAT1p0_BIT (1 << DMA_REQ_MAT1p0)
-#define DMA_REQ_MAT1p1_BIT (1 << DMA_REQ_MAT1p1)
-#define DMA_REQ_MAT2p0_BIT (1 << DMA_REQ_MAT2p0)
-#define DMA_REQ_MAT2p1_BIT (1 << DMA_REQ_MAT2p1)
-#define DMA_REQ_MAT3p0_BIT (1 << DMA_REQ_MAT3p0)
-#define DMA_REQ_MAT3p1_BIT (1 << DMA_REQ_MAT3p1)
-
-/* DMA Configuration Register */
-
-#define DMA_CONFIG_E (1 << 0) /* Bit 0: DMA Controller enable */
-#define DMA_CONFIG_M (1 << 1) /* Bit 1: AHB Master endianness configuration */
- /* Bits 2-31: Reserved */
-/* Channel Registers */
-
-/* DMA Channel Source Address Register (Bits 0-31: Source Address) */
-/* DMA Channel Destination Address Register Bits 0-31: Destination Address) */
-/* DMA Channel Linked List Item Register (Bits 0-31: Address of next link list
- * item. Bits 0-1 must be zero.
- */
-
-/* DMA Channel Control Register */
-
-#define DMACH_CONTROL_XFRSIZE_SHIFT (0) /* Bits 0-11: Transfer size */
-#define DMACH_CONTROL_XFRSIZE_MASK (0x0fff << DMACH_CONTROL_XFRSIZE_SHIFT)
-#define DMACH_CONTROL_SBSIZE_SHIFT (12) /* Bits 12-14: Source burst size */
-#define DMACH_CONTROL_SBSIZE_MASK (7 << DMACH_CONTROL_SBSIZE_SHIFT)
-# define DMACH_CONTROL_SBSIZE_1 (0 << DMACH_CONTROL_SBSIZE_SHIFT)
-# define DMACH_CONTROL_SBSIZE_4 (1 << DMACH_CONTROL_SBSIZE_SHIFT)
-# define DMACH_CONTROL_SBSIZE_8 (2 << DMACH_CONTROL_SBSIZE_SHIFT)
-# define DMACH_CONTROL_SBSIZE_16 (3 << DMACH_CONTROL_SBSIZE_SHIFT)
-# define DMACH_CONTROL_SBSIZE_32 (4 << DMACH_CONTROL_SBSIZE_SHIFT)
-# define DMACH_CONTROL_SBSIZE_64 (5 << DMACH_CONTROL_SBSIZE_SHIFT)
-# define DMACH_CONTROL_SBSIZE_128 (6 << DMACH_CONTROL_SBSIZE_SHIFT)
-# define DMACH_CONTROL_SBSIZE_256 (7 << DMACH_CONTROL_SBSIZE_SHIFT)
-#define DMACH_CONTROL_DBSIZE_SHIFT (15) /* Bits 15-17: Destination burst size */
-#define DMACH_CONTROL_DBSIZE_MASK (7 << DMACH_CONTROL_DBSIZE_SHIFT)
-# define DMACH_CONTROL_DBSIZE_1 (0 << DMACH_CONTROL_DBSIZE_SHIFT)
-# define DMACH_CONTROL_DBSIZE_4 (1 << DMACH_CONTROL_DBSIZE_SHIFT)
-# define DMACH_CONTROL_DBSIZE_8 (2 << DMACH_CONTROL_DBSIZE_SHIFT)
-# define DMACH_CONTROL_DBSIZE_16 (3 << DMACH_CONTROL_DBSIZE_SHIFT)
-# define DMACH_CONTROL_DBSIZE_32 (4 << DMACH_CONTROL_DBSIZE_SHIFT)
-# define DMACH_CONTROL_DBSIZE_64 (5 << DMACH_CONTROL_DBSIZE_SHIFT)
-# define DMACH_CONTROL_DBSIZE_128 (6 << DMACH_CONTROL_DBSIZE_SHIFT)
-# define DMACH_CONTROL_DBSIZE_256 (7 << DMACH_CONTROL_DBSIZE_SHIFT)
-#define DMACH_CONTROL_SWIDTH_SHIFT (18) /* Bits 18-20: Source transfer width */
-#define DMACH_CONTROL_SWIDTH_MASK (7 << DMACH_CONTROL_SWIDTH_SHIFT)
-#define DMACH_CONTROL_DWIDTH_SHIFT (21) /* Bits 21-23: Destination transfer width */
-#define DMACH_CONTROL_DWIDTH_MASK (7 << DMACH_CONTROL_DWIDTH_SHIFT)
-#define DMACH_CONTROL_SI (1 << 26) /* Bit 26: Source increment */
-#define DMACH_CONTROL_DI (1 << 27) /* Bit 27: Destination increment */
-#define DMACH_CONTROL_PROT1 (1 << 28) /* Bit 28: User/priviledged mode */
-#define DMACH_CONTROL_PROT2 (1 << 29) /* Bit 29: Bufferable */
-#define DMACH_CONTROL_PROT3 (1 << 30) /* Bit 30: Cacheable */
-#define DMACH_CONTROL_I (1 << 31) /* Bit 31: Terminal count interrupt enable */
-
-/* DMA Channel Configuration Register */
-
-
-#define DMACH_CONFIG_E (1 << 0) /* Bit 0: Channel enable */
-#define DMACH_CONFIG_SRCPER_SHIFT (1) /* Bits 1-5: Source peripheral */
-#define DMACH_CONFIG_SRCPER_MASK (31 << DMACH_CONFIG_SRCPER_SHIFT)
-# define DMACH_CONFIG_SRCPER_SSP0TX (DMA_REQ_SSP0TX << DMACH_CONFIG_SRCPER_SHIFT)
-# define DMACH_CONFIG_SRCPER_SSP0RX (DMA_REQ_SSP0RX << DMACH_CONFIG_SRCPER_SHIFT)
-# define DMACH_CONFIG_SRCPER_SSP1TX (DMA_REQ_SSP1TX << DMACH_CONFIG_SRCPER_SHIFT)
-# define DMACH_CONFIG_SRCPER_SSP1RX (DMA_REQ_SSP0RX << DMACH_CONFIG_SRCPER_SHIFT)
-# define DMACH_CONFIG_SRCPER_ADC (DMA_REQ_ADC << DMACH_CONFIG_SRCPER_SHIFT)
-# define DMACH_CONFIG_SRCPER_I2SCH0 (DMA_REQ_I2SCH0 << DMACH_CONFIG_SRCPER_SHIFT)
-# define DMACH_CONFIG_SRCPER_I2SCH1 (DMA_REQ_I2SCH1 << DMACH_CONFIG_SRCPER_SHIFT)
-# define DMACH_CONFIG_SRCPER_DAC (DMA_REQ_DAC << DMACH_CONFIG_SRCPER_SHIFT)
-# define DMACH_CONFIG_SRCPER_UART0TX (DMA_REQ_UART0TX << DMACH_CONFIG_SRCPER_SHIFT)
-# define DMACH_CONFIG_SRCPER_UART0RX (DMA_REQ_UART0RX << DMACH_CONFIG_SRCPER_SHIFT)
-# define DMACH_CONFIG_SRCPER_UART1TX (DMA_REQ_UART1TX << DMACH_CONFIG_SRCPER_SHIFT)
-# define DMACH_CONFIG_SRCPER_UART1RX (DMA_REQ_UART1RX << DMACH_CONFIG_SRCPER_SHIFT)
-# define DMACH_CONFIG_SRCPER_UART2TX (DMA_REQ_UART2TX << DMACH_CONFIG_SRCPER_SHIFT)
-# define DMACH_CONFIG_SRCPER_UART2RX (DMA_REQ_UART2RX << DMACH_CONFIG_SRCPER_SHIFT)
-# define DMACH_CONFIG_SRCPER_UART3TX (DMA_REQ_UART3TX << DMACH_CONFIG_SRCPER_SHIFT)
-# define DMACH_CONFIG_SRCPER_UART3RX (DMA_REQ_UART3RX << DMACH_CONFIG_SRCPER_SHIFT)
-# define DMACH_CONFIG_SRCPER_MAT0p0 (DMA_REQ_MAT0p0 << DMACH_CONFIG_SRCPER_SHIFT)
-# define DMACH_CONFIG_SRCPER_MAT0p1 (DMA_REQ_MAT0p1 << DMACH_CONFIG_SRCPER_SHIFT)
-# define DMACH_CONFIG_SRCPER_MAT1p0 (DMA_REQ_MAT1p0 << DMACH_CONFIG_SRCPER_SHIFT)
-# define DMACH_CONFIG_SRCPER_MAT1p1 (DMA_REQ_MAT1p1 << DMACH_CONFIG_SRCPER_SHIFT)
-# define DMACH_CONFIG_SRCPER_MAT2p0 (DMA_REQ_MAT2p0 << DMACH_CONFIG_SRCPER_SHIFT)
-# define DMACH_CONFIG_SRCPER_MAT2p1 (DMA_REQ_MAT2p1 << DMACH_CONFIG_SRCPER_SHIFT)
-# define DMACH_CONFIG_SRCPER_MAT3p0 (DMA_REQ_MAT3p0 << DMACH_CONFIG_SRCPER_SHIFT)
-# define DMACH_CONFIG_SRCPER_MAT3p1 (DMA_REQ_MAT3p1 << DMACH_CONFIG_SRCPER_SHIFT)
-#define DMACH_CONFIG_DSTPER_SHIFT (6) /* Bits 6-10: Source peripheral */
-#define DMACH_CONFIG_DSTPER_MASK (31 << DMACH_CONFIG_DSTPER_SHIFT)
-# define DMACH_CONFIG_DSTPER_SSP0TX (DMA_REQ_SSP0TX << DMACH_CONFIG_DSTPER_SHIFT)
-# define DMACH_CONFIG_DSTPER_SSP0RX (DMA_REQ_SSP0RX << DMACH_CONFIG_DSTPER_SHIFT)
-# define DMACH_CONFIG_DSTPER_SSP1TX (DMA_REQ_SSP1TX << DMACH_CONFIG_DSTPER_SHIFT)
-# define DMACH_CONFIG_DSTPER_SSP1RX (DMA_REQ_SSP0RX << DMACH_CONFIG_DSTPER_SHIFT)
-# define DMACH_CONFIG_DSTPER_ADC (DMA_REQ_ADC << DMACH_CONFIG_DSTPER_SHIFT)
-# define DMACH_CONFIG_DSTPER_I2SCH0 (DMA_REQ_I2SCH0 << DMACH_CONFIG_DSTPER_SHIFT)
-# define DMACH_CONFIG_DSTPER_I2SCH1 (DMA_REQ_I2SCH1 << DMACH_CONFIG_DSTPER_SHIFT)
-# define DMACH_CONFIG_DSTPER_DAC (DMA_REQ_DAC << DMACH_CONFIG_DSTPER_SHIFT)
-# define DMACH_CONFIG_DSTPER_UART0TX (DMA_REQ_UART0TX << DMACH_CONFIG_DSTPER_SHIFT)
-# define DMACH_CONFIG_DSTPER_UART0RX (DMA_REQ_UART0RX << DMACH_CONFIG_DSTPER_SHIFT)
-# define DMACH_CONFIG_DSTPER_UART1TX (DMA_REQ_UART1TX << DMACH_CONFIG_DSTPER_SHIFT)
-# define DMACH_CONFIG_DSTPER_UART1RX (DMA_REQ_UART1RX << DMACH_CONFIG_DSTPER_SHIFT)
-# define DMACH_CONFIG_DSTPER_UART2TX (DMA_REQ_UART2TX << DMACH_CONFIG_DSTPER_SHIFT)
-# define DMACH_CONFIG_DSTPER_UART2RX (DMA_REQ_UART2RX << DMACH_CONFIG_DSTPER_SHIFT)
-# define DMACH_CONFIG_DSTPER_UART3TX (DMA_REQ_UART3TX << DMACH_CONFIG_DSTPER_SHIFT)
-# define DMACH_CONFIG_DSTPER_UART3RX (DMA_REQ_UART3RX << DMACH_CONFIG_DSTPER_SHIFT)
-# define DMACH_CONFIG_DSTPER_MAT0p0 (DMA_REQ_MAT0p0 << DMACH_CONFIG_DSTPER_SHIFT)
-# define DMACH_CONFIG_DSTPER_MAT0p1 (DMA_REQ_MAT0p1 << DMACH_CONFIG_DSTPER_SHIFT)
-# define DMACH_CONFIG_DSTPER_MAT1p0 (DMA_REQ_MAT1p0 << DMACH_CONFIG_DSTPER_SHIFT)
-# define DMACH_CONFIG_DSTPER_MAT1p1 (DMA_REQ_MAT1p1 << DMACH_CONFIG_DSTPER_SHIFT)
-# define DMACH_CONFIG_DSTPER_MAT2p0 (DMA_REQ_MAT2p0 << DMACH_CONFIG_DSTPER_SHIFT)
-# define DMACH_CONFIG_DSTPER_MAT2p1 (DMA_REQ_MAT2p1 << DMACH_CONFIG_DSTPER_SHIFT)
-# define DMACH_CONFIG_DSTPER_MAT3p0 (DMA_REQ_MAT3p0 << DMACH_CONFIG_DSTPER_SHIFT)
-# define DMACH_CONFIG_DSTPER_MAT3p1 (DMA_REQ_MAT3p1 << DMACH_CONFIG_DSTPER_SHIFT)
-#define DMACH_CONFIG_XFRTYPE_SHIFT (11) /* Bits 11-13: Type of transfer */
-#define DMACH_CONFIG_XFRTYPE_MASK (7 << DMACH_CONFIG_XFRTYPE_SHIFT)
-# define DMACH_CONFIG_XFRTYPE_M2M (0 << DMACH_CONFIG_XFRTYPE_SHIFT) /* Memory to memory DMA */
-# define DMACH_CONFIG_XFRTYPE_M2P (1 << DMACH_CONFIG_XFRTYPE_SHIFT) /* Memory to peripheral DMA */
-# define DMACH_CONFIG_XFRTYPE_P2M (2 << DMACH_CONFIG_XFRTYPE_SHIFT) /* Peripheral to memory DMA */
-# define DMACH_CONFIG_XFRTYPE_P2P (3 << DMACH_CONFIG_XFRTYPE_SHIFT) /* Peripheral to peripheral DMA */
-#define DMACH_CONFIG_IE (1 << 14) /* Bit 14: Interrupt error mask */
-#define DMACH_CONFIG_ ITC (1 << 15) /* Bit 15: Terminal count interrupt mask */
-#define DMACH_CONFIG_L (1 << 16) /* Bit 16: Lock */
-#define DMACH_CONFIG_A (1 << 17) /* Bit 17: Active */
-#define DMACH_CONFIG_H (1 << 18) /* Bit 18: Halt */
- /* Bits 19-31: Reserved */
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-/************************************************************************************
- * Public Functions
- ************************************************************************************/
-
-#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_GPDMA_H */
+/************************************************************************************ + * arch/arm/src/lpc17xx/lpc17_gpdma.h + * + * Copyright (C) 2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_GPDMA_H +#define __ARCH_ARM_SRC_LPC17XX_LPC17_GPDMA_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +#include "chip.h" +#include "lpc17_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register offsets *****************************************************************/ + +/* General registers (see also LPC17_SYSCON_DMAREQSEL_OFFSET in lpc17_syscon.h) */ + +#define LPC17_DMA_INTST_OFFSET 0x0000 /* DMA Interrupt Status Register */ +#define LPC17_DMA_INTTCST_OFFSET 0x0004 /* DMA Interrupt Terminal Count Request Status Register */ +#define LPC17_DMA_INTTCCLR_OFFSET 0x0008 /* DMA Interrupt Terminal Count Request Clear Register */ +#define LPC17_DMA_INTERRST_OFFSET 0x000c /* DMA Interrupt Error Status Register */ +#define LPC17_DMA_INTERRCLR_OFFSET 0x0010 /* DMA Interrupt Error Clear Register */ +#define LPC17_DMA_RAWINTTCST_OFFSET 0x0014 /* DMA Raw Interrupt Terminal Count Status Register */ +#define LPC17_DMA_RAWINTERRST_OFFSET 0x0018 /* DMA Raw Error Interrupt Status Register */ +#define LPC17_DMA_ENBLDCHNS_OFFSET 0x001c /* DMA Enabled Channel Register */ +#define LPC17_DMA_SOFTBREQ_OFFSET 0x0020 /* DMA Software Burst Request Register */ +#define LPC17_DMA_SOFTSREQ_OFFSET 0x0024 /* DMA Software Single Request Register */ +#define LPC17_DMA_SOFTLBREQ_OFFSET 0x0028 /* DMA Software Last Burst Request Register */ +#define LPC17_DMA_SOFTLSREQ_OFFSET 0x002c /* DMA Software Last Single Request Register */ +#define LPC17_DMA_CONFIG_OFFSET 0x0030 /* DMA Configuration Register */ +#define LPC17_DMA_SYNC_OFFSET 0x0034 /* DMA Synchronization Register */ + +/* Channel Registers */ + +#define LPC17_DMA_CHAN_OFFSET(n) (0x0100 + ((n) << 5)) /* n=0,1,...7 */ + +#define LPC17_DMACH_SRCADDR_OFFSET 0x0000 /* DMA Channel Source Address Register */ +#define LPC17_DMACH_DESTADDR_OFFSET 0x0004 /* DMA Channel Destination Address Register */ +#define LPC17_DMACH_LLI_OFFSET 0x0008 /* DMA Channel Linked List Item Register */ +#define LPC17_DMACH_CONTROL_OFFSET 0x000c /* DMA Channel Control Register */ +#define LPC17_DMACH_CONFIG_OFFSET 0x0010 /* DMA Channel Configuration Register */ + +#define LPC17_DMACH0_SRCADDR_OFFSET (0x100+LPC17_DMACH_SRCADDR_OFFSET) +#define LPC17_DMACH0_DESTADDR_OFFSET (0x100+LPC17_DMACH_DESTADDR_OFFSET) +#define LPC17_DMACH0_LLI_OFFSET (0x100+LPC17_DMACH_LLI_OFFSET) +#define LPC17_DMACH0_CONTROL_OFFSET (0x100+LPC17_DMACH_CONTROL_OFFSET) +#define LPC17_DMACH0_CONFIG_OFFSET (0x100+LPC17_DMACH_CONFIG_OFFSET) + +#define LPC17_DMACH1_SRCADDR_OFFSET (0x120+LPC17_DMACH_SRCADDR_OFFSET) +#define LPC17_DMACH1_DESTADDR_OFFSET (0x120+LPC17_DMACH_DESTADDR_OFFSET) +#define LPC17_DMACH1_LLI_OFFSET (0x120+LPC17_DMACH_LLI_OFFSET) +#define LPC17_DMACH1_CONTROL_OFFSET (0x120+LPC17_DMACH_CONTROL_OFFSET) +#define LPC17_DMACH1_CONFIG_OFFSET (0x120+LPC17_DMACH_CONFIG_OFFSET) + +#define LPC17_DMACH2_SRCADDR_OFFSET (0x140+LPC17_DMACH_SRCADDR_OFFSET) +#define LPC17_DMACH2_DESTADDR_OFFSET (0x140+LPC17_DMACH_DESTADDR_OFFSET) +#define LPC17_DMACH2_LLI_OFFSET (0x140+LPC17_DMACH_LLI_OFFSET) +#define LPC17_DMACH2_CONTROL_OFFSET (0x140+LPC17_DMACH_CONTROL_OFFSET) +#define LPC17_DMACH2_CONFIG_OFFSET (0x140+LPC17_DMACH_CONFIG_OFFSET) + +#define LPC17_DMACH3_SRCADDR_OFFSET (0x160+LPC17_DMACH_SRCADDR_OFFSET) +#define LPC17_DMACH3_DESTADDR_OFFSET (0x160+LPC17_DMACH_DESTADDR_OFFSET) +#define LPC17_DMACH3_LLI_OFFSET (0x160+LPC17_DMACH_LLI_OFFSET) +#define LPC17_DMACH3_CONTROL_OFFSET (0x160+LPC17_DMACH_CONTROL_OFFSET) +#define LPC17_DMACH3_CONFIG_OFFSET (0x160+LPC17_DMACH_CONFIG_OFFSET) + +#define LPC17_DMACH4_SRCADDR_OFFSET (0x180+LPC17_DMACH_SRCADDR_OFFSET) +#define LPC17_DMACH4_DESTADDR_OFFSET (0x180+LPC17_DMACH_DESTADDR_OFFSET) +#define LPC17_DMACH4_LLI_OFFSET (0x180+LPC17_DMACH_LLI_OFFSET) +#define LPC17_DMACH4_CONTROL_OFFSET (0x180+LPC17_DMACH_CONTROL_OFFSET) +#define LPC17_DMACH4_CONFIG_OFFSET (0x180+LPC17_DMACH_CONFIG_OFFSET) + +#define LPC17_DMACH5_SRCADDR_OFFSET (0x1a0+LPC17_DMACH_SRCADDR_OFFSET) +#define LPC17_DMACH5_DESTADDR_OFFSET (0x1a0+LPC17_DMACH_DESTADDR_OFFSET) +#define LPC17_DMACH5_LLI_OFFSET (0x1a0+LPC17_DMACH_LLI_OFFSET) +#define LPC17_DMACH5_CONTROL_OFFSET (0x1a0+LPC17_DMACH_CONTROL_OFFSET) +#define LPC17_DMACH5_CONFIG_OFFSET (0x1a0+LPC17_DMACH_CONFIG_OFFSET) + +#define LPC17_DMACH6_SRCADDR_OFFSET (0x1c0+LPC17_DMACH_SRCADDR_OFFSET) +#define LPC17_DMACH6_DESTADDR_OFFSET (0x1c0+LPC17_DMACH_DESTADDR_OFFSET) +#define LPC17_DMACH6_LLI_OFFSET (0x1c0+LPC17_DMACH_LLI_OFFSET) +#define LPC17_DMACH6_CONTROL_OFFSET (0x1c0+LPC17_DMACH_CONTROL_OFFSET) +#define LPC17_DMACH6_CONFIG_OFFSET (0x1c0+LPC17_DMACH_CONFIG_OFFSET) + +#define LPC17_DMACH7_SRCADDR_OFFSET (0x1e0+LPC17_DMACH_SRCADDR_OFFSET) +#define LPC17_DMACH7_DESTADDR_OFFSET (0x1e0+LPC17_DMACH_DESTADDR_OFFSET) +#define LPC17_DMACH7_LLI_OFFSET (0x1e0+LPC17_DMACH_LLI_OFFSET) +#define LPC17_DMACH7_CONTROL_OFFSET (0x1e0+LPC17_DMACH_CONTROL_OFFSET) +#define LPC17_DMACH7_CONFIG_OFFSET (0x1e0+LPC17_DMACH_CONFIG_OFFSET) + +/* Register addresses ***************************************************************/ +/* General registers (see also LPC17_SYSCON_DMAREQSEL in lpc17_syscon.h) */ + +#define LPC17_DMA_INTST (LPC17_GPDMA_BASE+LPC17_DMA_INTST_OFFSET) +#define LPC17_DMA_INTTCST (LPC17_GPDMA_BASE+LPC17_DMA_INTTCST_OFFSET) +#define LPC17_DMA_INTTCCLR (LPC17_GPDMA_BASE+LPC17_DMA_INTTCCLR_OFFSET) +#define LPC17_DMA_INTERRST (LPC17_GPDMA_BASE+LPC17_DMA_INTERRST_OFFSET) +#define LPC17_DMA_INTERRCLR (LPC17_GPDMA_BASE+LPC17_DMA_INTERRCLR_OFFSET) +#define LPC17_DMA_RAWINTTCST (LPC17_GPDMA_BASE+LPC17_DMA_RAWINTTCST_OFFSET) +#define LPC17_DMA_RAWINTERRST (LPC17_GPDMA_BASE+LPC17_DMA_RAWINTERRST_OFFSET) +#define LPC17_DMA_ENBLDCHNS (LPC17_GPDMA_BASE+LPC17_DMA_ENBLDCHNS_OFFSET) +#define LPC17_DMA_SOFTBREQ (LPC17_GPDMA_BASE+LPC17_DMA_SOFTBREQ_OFFSET) +#define LPC17_DMA_SOFTSREQ (LPC17_GPDMA_BASE+LPC17_DMA_SOFTSREQ_OFFSET) +#define LPC17_DMA_SOFTLBREQ (LPC17_GPDMA_BASE+LPC17_DMA_SOFTLBREQ_OFFSET) +#define LPC17_DMA_SOFTLSREQ (LPC17_GPDMA_BASE+LPC17_DMA_SOFTLSREQ_OFFSET) +#define LPC17_DMA_CONFIG (LPC17_GPDMA_BASE+LPC17_DMA_CONFIG_OFFSET) +#define LPC17_DMA_SYNC (LPC17_GPDMA_BASE+LPC17_DMA_SYNC_OFFSET) + +/* Channel Registers */ + +#define LPC17_DMACH_BASE(n) (LPC17_GPDMA_BASE+LPC17_DMA_CHAN_OFFSET(n)) + +#define LPC17_DMACH_SRCADDR(n) (LPC17_DMACH_BASE(n)+LPC17_DMACH_SRCADDR_OFFSET) +#define LPC17_DMACH_DESTADDR(n) (LPC17_DMACH_BASE(n)+LPC17_DMACH_DESTADDR_OFFSET) +#define LPC17_DMACH_LLI(n) (LPC17_DMACH_BASE(n)+LPC17_DMACH_LLI_OFFSET) +#define LPC17_DMACH_CONTROL(n) (LPC17_DMACH_BASE(n)+LPC17_DMACH_CONTROL_OFFSET) +#define LPC17_DMACH_CONFIG(n) (LPC17_DMACH_BASE(n)+LPC17_DMACH_CONFIG_OFFSET) + +#define LPC17_DMACH0_SRCADDR (LPC17_GPDMA_BASE+LPC17_DMACH0_SRCADDR_OFFSET) +#define LPC17_DMACH0_DESTADDR (LPC17_GPDMA_BASE+LPC17_DMACH0_DESTADDR_OFFSET) +#define LPC17_DMACH0_LLI (LPC17_GPDMA_BASE+LPC17_DMACH0_LLI_OFFSET) +#define LPC17_DMACH0_CONTROL (LPC17_GPDMA_BASE+LPC17_DMACH0_CONTROL_OFFSET) +#define LPC17_DMACH0_CONFIG (LPC17_GPDMA_BASE+LPC17_DMACH0_CONFIG_OFFSET) + +#define LPC17_DMACH1_SRCADDR (LPC17_GPDMA_BASE+LPC17_DMACH1_SRCADDR_OFFSET) +#define LPC17_DMACH1_DESTADDR (LPC17_GPDMA_BASE+LPC17_DMACH1_DESTADDR_OFFSET) +#define LPC17_DMACH1_LLI (LPC17_GPDMA_BASE+LPC17_DMACH1_LLI_OFFSET) +#define LPC17_DMACH1_CONTROL (LPC17_GPDMA_BASE+LPC17_DMACH1_CONTROL_OFFSET) +#define LPC17_DMACH1_CONFIG (LPC17_GPDMA_BASE+LPC17_DMACH1_CONFIG_OFFSET) + +#define LPC17_DMACH2_SRCADDR (LPC17_GPDMA_BASE+LPC17_DMACH2_SRCADDR_OFFSET) +#define LPC17_DMACH2_DESTADDR (LPC17_GPDMA_BASE+LPC17_DMACH2_DESTADDR_OFFSET) +#define LPC17_DMACH2_LLI (LPC17_GPDMA_BASE+LPC17_DMACH2_LLI_OFFSET) +#define LPC17_DMACH2_CONTROL (LPC17_GPDMA_BASE+LPC17_DMACH2_CONTROL_OFFSET) +#define LPC17_DMACH2_CONFIG (LPC17_GPDMA_BASE+LPC17_DMACH2_CONFIG_OFFSET) + +#define LPC17_DMACH3_SRCADDR (LPC17_GPDMA_BASE+LPC17_DMACH3_SRCADDR_OFFSET) +#define LPC17_DMACH3_DESTADDR (LPC17_GPDMA_BASE+LPC17_DMACH3_DESTADDR_OFFSET) +#define LPC17_DMACH3_LLI (LPC17_GPDMA_BASE+LPC17_DMACH3_LLI_OFFSET) +#define LPC17_DMACH3_CONTROL (LPC17_GPDMA_BASE+LPC17_DMACH3_CONTROL_OFFSET) +#define LPC17_DMACH3_CONFIG (LPC17_GPDMA_BASE+LPC17_DMACH3_CONFIG_OFFSET) + +#define LPC17_DMACH4_SRCADDR (LPC17_GPDMA_BASE+LPC17_DMACH4_SRCADDR_OFFSET) +#define LPC17_DMACH4_DESTADDR (LPC17_GPDMA_BASE+LPC17_DMACH4_DESTADDR_OFFSET) +#define LPC17_DMACH4_LLI (LPC17_GPDMA_BASE+LPC17_DMACH4_LLI_OFFSET) +#define LPC17_DMACH4_CONTROL (LPC17_GPDMA_BASE+LPC17_DMACH4_CONTROL_OFFSET) +#define LPC17_DMACH4_CONFIG (LPC17_GPDMA_BASE+LPC17_DMACH4_CONFIG_OFFSET) + +#define LPC17_DMACH5_SRCADDR (LPC17_GPDMA_BASE+LPC17_DMACH5_SRCADDR_OFFSET) +#define LPC17_DMACH5_DESTADDR (LPC17_GPDMA_BASE+LPC17_DMACH5_DESTADDR_OFFSET) +#define LPC17_DMACH5_LLI (LPC17_GPDMA_BASE+LPC17_DMACH5_LLI_OFFSET) +#define LPC17_DMACH5_CONTROL (LPC17_GPDMA_BASE+LPC17_DMACH5_CONTROL_OFFSET) +#define LPC17_DMACH5_CONFIG (LPC17_GPDMA_BASE+LPC17_DMACH5_CONFIG_OFFSET) + +#define LPC17_DMACH6_SRCADDR (LPC17_GPDMA_BASE+LPC17_DMACH6_SRCADDR_OFFSET) +#define LPC17_DMACH6_DESTADDR (LPC17_GPDMA_BASE+LPC17_DMACH6_DESTADDR_OFFSET) +#define LPC17_DMACH6_LLI (LPC17_GPDMA_BASE+LPC17_DMACH6_LLI_OFFSET) +#define LPC17_DMACH6_CONTROL (LPC17_GPDMA_BASE+LPC17_DMACH6_CONTROL_OFFSET) +#define LPC17_DMACH6_CONFIG (LPC17_GPDMA_BASE+LPC17_DMACH6_CONFIG_OFFSET) + +#define LPC17_DMACH7_SRCADDR (LPC17_GPDMA_BASE+LPC17_DMACH7_SRCADDR_OFFSET) +#define LPC17_DMACH7_DESTADDR (LPC17_GPDMA_BASE+LPC17_DMACH7_DESTADDR_OFFSET) +#define LPC17_DMACH7_LLI (LPC17_GPDMA_BASE+LPC17_DMACH7_LLI_OFFSET) +#define LPC17_DMACH7_CONTROL (LPC17_GPDMA_BASE+LPC17_DMACH7_CONTROL_OFFSET) +#define LPC17_DMACH7_CONFIG (LPC17_GPDMA_BASE+LPC17_DMACH7_CONFIG_OFFSET) + +/* Register bit definitions *********************************************************/ +/* DMA request connections */ + +#define DMA_REQ_SSP0TX (0) +#define DMA_REQ_SSP0RX (1) +#define DMA_REQ_SSP1TX (2) +#define DMA_REQ_SSP1RX (3) +#define DMA_REQ_ADC (4) +#define DMA_REQ_I2SCH0 (5) +#define DMA_REQ_I2SCH1 (6) +#define DMA_REQ_DAC (7) + +#define DMA_REQ_UART0TX (8) +#define DMA_REQ_UART0RX (9) +#define DMA_REQ_UART1TX (10) +#define DMA_REQ_UART1RX (11) +#define DMA_REQ_UART2TX (12) +#define DMA_REQ_UART2RX (13) +#define DMA_REQ_UART3TX (14) +#define DMA_REQ_UART3RX (15) + +#define DMA_REQ_MAT0p0 (8) +#define DMA_REQ_MAT0p1 (9) +#define DMA_REQ_MAT1p0 (10) +#define DMA_REQ_MAT1p1 (11) +#define DMA_REQ_MAT2p0 (12) +#define DMA_REQ_MAT2p1 (13) +#define DMA_REQ_MAT3p0 (14) +#define DMA_REQ_MAT3p1 (15) + +/* General registers (see also LPC17_SYSCON_DMAREQSEL in lpc17_syscon.h) */ +/* Fach of the following registers, bits 0-7 controls DMA channels 9-7, + * respectively. Bits 8-31 are reserved. + * + * DMA Interrupt Status Register + * DMA Interrupt Terminal Count Request Status Register + * DMA Interrupt Terminal Count Request Clear Register + * DMA Interrupt Error Status Register + * DMA Interrupt Error Clear Register + * DMA Raw Interrupt Terminal Count Status Register + * DMA Raw Error Interrupt Status Register + * DMA Enabled Channel Register + */ + +#define DMACH(n) (1 << (n)) /* n=0,1,...7 */ + +/* For each of the following registers, bits 0-15 represent a set of encoded + * DMA sources. Bits 16-31 are reserved in each case. + * + * DMA Software Burst Request Register + * DMA Software Single Request Register + * DMA Software Last Burst Request Register + * DMA Software Last Single Request Register + * DMA Synchronization Register + */ + +#define DMA_REQ_SSP0TX_BIT (1 << DMA_REQ_SSP0TX) +#define DMA_REQ_SSP0RX_BIT (1 << DMA_REQ_SSP0RX) +#define DMA_REQ_SSP1TX_BIT (1 << DMA_REQ_SSP1TX) +#define DMA_REQ_SSP1RX_BIT (1 << DMA_REQ_SSP0RX) +#define DMA_REQ_ADC_BIT (1 << DMA_REQ_ADC) +#define DMA_REQ_I2SCH0_BIT (1 << DMA_REQ_I2SCH0) +#define DMA_REQ_I2SCH1_BIT (1 << DMA_REQ_I2SCH1) +#define DMA_REQ_DAC_BIT (1 << DMA_REQ_DAC) + +#define DMA_REQ_UART0TX_BIT (1 << DMA_REQ_UART0TX) +#define DMA_REQ_UART0RX_BIT (1 << DMA_REQ_UART0RX) +#define DMA_REQ_UART1TX_BIT (1 << DMA_REQ_UART1TX) +#define DMA_REQ_UART1RX_BIT (1 << DMA_REQ_UART1RX) +#define DMA_REQ_UART2TX_BIT (1 << DMA_REQ_UART2TX) +#define DMA_REQ_UART2RX_BIT (1 << DMA_REQ_UART2RX) +#define DMA_REQ_UART3TX_BIT (1 << DMA_REQ_UART3TX) +#define DMA_REQ_UART3RX_BIT (1 << DMA_REQ_UART3RX) + +#define DMA_REQ_MAT0p0_BIT (1 << DMA_REQ_MAT0p0) +#define DMA_REQ_MAT0p1_BIT (1 << DMA_REQ_MAT0p1) +#define DMA_REQ_MAT1p0_BIT (1 << DMA_REQ_MAT1p0) +#define DMA_REQ_MAT1p1_BIT (1 << DMA_REQ_MAT1p1) +#define DMA_REQ_MAT2p0_BIT (1 << DMA_REQ_MAT2p0) +#define DMA_REQ_MAT2p1_BIT (1 << DMA_REQ_MAT2p1) +#define DMA_REQ_MAT3p0_BIT (1 << DMA_REQ_MAT3p0) +#define DMA_REQ_MAT3p1_BIT (1 << DMA_REQ_MAT3p1) + +/* DMA Configuration Register */ + +#define DMA_CONFIG_E (1 << 0) /* Bit 0: DMA Controller enable */ +#define DMA_CONFIG_M (1 << 1) /* Bit 1: AHB Master endianness configuration */ + /* Bits 2-31: Reserved */ +/* Channel Registers */ + +/* DMA Channel Source Address Register (Bits 0-31: Source Address) */ +/* DMA Channel Destination Address Register Bits 0-31: Destination Address) */ +/* DMA Channel Linked List Item Register (Bits 0-31: Address of next link list + * item. Bits 0-1 must be zero. + */ + +/* DMA Channel Control Register */ + +#define DMACH_CONTROL_XFRSIZE_SHIFT (0) /* Bits 0-11: Transfer size */ +#define DMACH_CONTROL_XFRSIZE_MASK (0x0fff << DMACH_CONTROL_XFRSIZE_SHIFT) +#define DMACH_CONTROL_SBSIZE_SHIFT (12) /* Bits 12-14: Source burst size */ +#define DMACH_CONTROL_SBSIZE_MASK (7 << DMACH_CONTROL_SBSIZE_SHIFT) +# define DMACH_CONTROL_SBSIZE_1 (0 << DMACH_CONTROL_SBSIZE_SHIFT) +# define DMACH_CONTROL_SBSIZE_4 (1 << DMACH_CONTROL_SBSIZE_SHIFT) +# define DMACH_CONTROL_SBSIZE_8 (2 << DMACH_CONTROL_SBSIZE_SHIFT) +# define DMACH_CONTROL_SBSIZE_16 (3 << DMACH_CONTROL_SBSIZE_SHIFT) +# define DMACH_CONTROL_SBSIZE_32 (4 << DMACH_CONTROL_SBSIZE_SHIFT) +# define DMACH_CONTROL_SBSIZE_64 (5 << DMACH_CONTROL_SBSIZE_SHIFT) +# define DMACH_CONTROL_SBSIZE_128 (6 << DMACH_CONTROL_SBSIZE_SHIFT) +# define DMACH_CONTROL_SBSIZE_256 (7 << DMACH_CONTROL_SBSIZE_SHIFT) +#define DMACH_CONTROL_DBSIZE_SHIFT (15) /* Bits 15-17: Destination burst size */ +#define DMACH_CONTROL_DBSIZE_MASK (7 << DMACH_CONTROL_DBSIZE_SHIFT) +# define DMACH_CONTROL_DBSIZE_1 (0 << DMACH_CONTROL_DBSIZE_SHIFT) +# define DMACH_CONTROL_DBSIZE_4 (1 << DMACH_CONTROL_DBSIZE_SHIFT) +# define DMACH_CONTROL_DBSIZE_8 (2 << DMACH_CONTROL_DBSIZE_SHIFT) +# define DMACH_CONTROL_DBSIZE_16 (3 << DMACH_CONTROL_DBSIZE_SHIFT) +# define DMACH_CONTROL_DBSIZE_32 (4 << DMACH_CONTROL_DBSIZE_SHIFT) +# define DMACH_CONTROL_DBSIZE_64 (5 << DMACH_CONTROL_DBSIZE_SHIFT) +# define DMACH_CONTROL_DBSIZE_128 (6 << DMACH_CONTROL_DBSIZE_SHIFT) +# define DMACH_CONTROL_DBSIZE_256 (7 << DMACH_CONTROL_DBSIZE_SHIFT) +#define DMACH_CONTROL_SWIDTH_SHIFT (18) /* Bits 18-20: Source transfer width */ +#define DMACH_CONTROL_SWIDTH_MASK (7 << DMACH_CONTROL_SWIDTH_SHIFT) +#define DMACH_CONTROL_DWIDTH_SHIFT (21) /* Bits 21-23: Destination transfer width */ +#define DMACH_CONTROL_DWIDTH_MASK (7 << DMACH_CONTROL_DWIDTH_SHIFT) +#define DMACH_CONTROL_SI (1 << 26) /* Bit 26: Source increment */ +#define DMACH_CONTROL_DI (1 << 27) /* Bit 27: Destination increment */ +#define DMACH_CONTROL_PROT1 (1 << 28) /* Bit 28: User/priviledged mode */ +#define DMACH_CONTROL_PROT2 (1 << 29) /* Bit 29: Bufferable */ +#define DMACH_CONTROL_PROT3 (1 << 30) /* Bit 30: Cacheable */ +#define DMACH_CONTROL_I (1 << 31) /* Bit 31: Terminal count interrupt enable */ + +/* DMA Channel Configuration Register */ + + +#define DMACH_CONFIG_E (1 << 0) /* Bit 0: Channel enable */ +#define DMACH_CONFIG_SRCPER_SHIFT (1) /* Bits 1-5: Source peripheral */ +#define DMACH_CONFIG_SRCPER_MASK (31 << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_SSP0TX (DMA_REQ_SSP0TX << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_SSP0RX (DMA_REQ_SSP0RX << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_SSP1TX (DMA_REQ_SSP1TX << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_SSP1RX (DMA_REQ_SSP0RX << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_ADC (DMA_REQ_ADC << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_I2SCH0 (DMA_REQ_I2SCH0 << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_I2SCH1 (DMA_REQ_I2SCH1 << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_DAC (DMA_REQ_DAC << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_UART0TX (DMA_REQ_UART0TX << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_UART0RX (DMA_REQ_UART0RX << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_UART1TX (DMA_REQ_UART1TX << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_UART1RX (DMA_REQ_UART1RX << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_UART2TX (DMA_REQ_UART2TX << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_UART2RX (DMA_REQ_UART2RX << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_UART3TX (DMA_REQ_UART3TX << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_UART3RX (DMA_REQ_UART3RX << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_MAT0p0 (DMA_REQ_MAT0p0 << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_MAT0p1 (DMA_REQ_MAT0p1 << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_MAT1p0 (DMA_REQ_MAT1p0 << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_MAT1p1 (DMA_REQ_MAT1p1 << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_MAT2p0 (DMA_REQ_MAT2p0 << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_MAT2p1 (DMA_REQ_MAT2p1 << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_MAT3p0 (DMA_REQ_MAT3p0 << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_MAT3p1 (DMA_REQ_MAT3p1 << DMACH_CONFIG_SRCPER_SHIFT) +#define DMACH_CONFIG_DSTPER_SHIFT (6) /* Bits 6-10: Source peripheral */ +#define DMACH_CONFIG_DSTPER_MASK (31 << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_SSP0TX (DMA_REQ_SSP0TX << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_SSP0RX (DMA_REQ_SSP0RX << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_SSP1TX (DMA_REQ_SSP1TX << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_SSP1RX (DMA_REQ_SSP0RX << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_ADC (DMA_REQ_ADC << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_I2SCH0 (DMA_REQ_I2SCH0 << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_I2SCH1 (DMA_REQ_I2SCH1 << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_DAC (DMA_REQ_DAC << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_UART0TX (DMA_REQ_UART0TX << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_UART0RX (DMA_REQ_UART0RX << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_UART1TX (DMA_REQ_UART1TX << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_UART1RX (DMA_REQ_UART1RX << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_UART2TX (DMA_REQ_UART2TX << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_UART2RX (DMA_REQ_UART2RX << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_UART3TX (DMA_REQ_UART3TX << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_UART3RX (DMA_REQ_UART3RX << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_MAT0p0 (DMA_REQ_MAT0p0 << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_MAT0p1 (DMA_REQ_MAT0p1 << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_MAT1p0 (DMA_REQ_MAT1p0 << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_MAT1p1 (DMA_REQ_MAT1p1 << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_MAT2p0 (DMA_REQ_MAT2p0 << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_MAT2p1 (DMA_REQ_MAT2p1 << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_MAT3p0 (DMA_REQ_MAT3p0 << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_MAT3p1 (DMA_REQ_MAT3p1 << DMACH_CONFIG_DSTPER_SHIFT) +#define DMACH_CONFIG_XFRTYPE_SHIFT (11) /* Bits 11-13: Type of transfer */ +#define DMACH_CONFIG_XFRTYPE_MASK (7 << DMACH_CONFIG_XFRTYPE_SHIFT) +# define DMACH_CONFIG_XFRTYPE_M2M (0 << DMACH_CONFIG_XFRTYPE_SHIFT) /* Memory to memory DMA */ +# define DMACH_CONFIG_XFRTYPE_M2P (1 << DMACH_CONFIG_XFRTYPE_SHIFT) /* Memory to peripheral DMA */ +# define DMACH_CONFIG_XFRTYPE_P2M (2 << DMACH_CONFIG_XFRTYPE_SHIFT) /* Peripheral to memory DMA */ +# define DMACH_CONFIG_XFRTYPE_P2P (3 << DMACH_CONFIG_XFRTYPE_SHIFT) /* Peripheral to peripheral DMA */ +#define DMACH_CONFIG_IE (1 << 14) /* Bit 14: Interrupt error mask */ +#define DMACH_CONFIG_ ITC (1 << 15) /* Bit 15: Terminal count interrupt mask */ +#define DMACH_CONFIG_L (1 << 16) /* Bit 16: Lock */ +#define DMACH_CONFIG_A (1 << 17) /* Bit 17: Active */ +#define DMACH_CONFIG_H (1 << 18) /* Bit 18: Halt */ + /* Bits 19-31: Reserved */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_GPDMA_H */ diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_gpio.h b/nuttx/arch/arm/src/lpc17xx/lpc17_gpio.h index 39fa161fc..002ef3faf 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_gpio.h +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_gpio.h @@ -1,196 +1,196 @@ -/************************************************************************************
- * arch/arm/src/lpc17xx/lpc17_gpio.h
- *
- * Copyright (C) 2010 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_GPIO_H
-#define __ARCH_ARM_SRC_LPC17XX_LPC17_GPIO_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-
-#include "chip.h"
-#include "lpc17_memorymap.h"
-
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-
-/* Register offsets *****************************************************************/
-/* GPIO block register offsets ******************************************************/
-
-#define LPC17_FIO0_OFFSET 0x0000
-#define LPC17_FIO1_OFFSET 0x0020
-#define LPC17_FIO2_OFFSET 0x0040
-#define LPC17_FIO3_OFFSET 0x0060
-#define LPC17_FIO4_OFFSET 0x0080
-
-#define LPC17_FIO_DIR_OFFSET 0x0000 /* Fast GPIO Port Direction control */
-#define LPC17_FIO_MASK_OFFSET 0x0010 /* Fast Mask register for ports */
-#define LPC17_FIO_PIN_OFFSET 0x0014 /* Fast Port Pin value registers */
-#define LPC17_FIO_SET_OFFSET 0x0018 /* Fast Port Output Set registers */
-#define LPC17_FIO_CLR_OFFSET 0x001c /* Fast Port Output Clear register */
-
-/* GPIO interrupt block register offsets ********************************************/
-
-#define LPC17_GPIOINT_OFFSET(n) (0x10*(n) + 0x80)
-#define LPC17_GPIOINT0_OFFSET 0x0080
-#define LPC17_GPIOINT2_OFFSET 0x00a0
-
-#define LPC17_GPIOINT_IOINTSTATUS_OFFSET 0x0000 /* GPIO overall Interrupt Status */
-#define LPC17_GPIOINT_INTSTATR_OFFSET 0x0004 /* GPIO Interrupt Status Rising edge */
-#define LPC17_GPIOINT_INTSTATF_OFFSET 0x0008 /* GPIO Interrupt Status Falling edge */
-#define LPC17_GPIOINT_INTCLR_OFFSET 0x000c /* GPIO Interrupt Clear */
-#define LPC17_GPIOINT_INTENR_OFFSET 0x0010 /* GPIO Interrupt Enable Rising edge */
-#define LPC17_GPIOINT_INTENF_OFFSET 0x0014 /* GPIO Interrupt Enable Falling edge */
-
-/* Register addresses ***************************************************************/
-/* GPIO block register addresses ****************************************************/
-
-#define LPC17_FIO_BASE(n) (LPC17_GPIO_BASE+LPC17_GPIOINT_OFFSET(n))
-#define LPC17_FIO0_BASE (LPC17_GPIO_BASE+LPC17_FIO0_OFFSET)
-#define LPC17_FIO1_BASE (LPC17_GPIO_BASE+LPC17_FIO1_OFFSET)
-#define LPC17_FIO2_BASE (LPC17_GPIO_BASE+LPC17_FIO2_OFFSET)
-#define LPC17_FIO3_BASE (LPC17_GPIO_BASE+LPC17_FIO3_OFFSET)
-#define LPC17_FIO4_BASE (LPC17_GPIO_BASE+LPC17_FIO4_OFFSET)
-
-#define LPC17_FIO_DIR(n) (LPC17_FIO_BASE(n)+LPC17_FIO_DIR_OFFSET)
-#define LPC17_FIO_MASK(n) (LPC17_FIO_BASE(n)+LPC17_FIO_MASK_OFFSET)
-#define LPC17_FIO_PIN(n) (LPC17_FIO_BASE(n)+LPC17_FIO_PIN_OFFSET)
-#define LPC17_FIO_SET(n) (LPC17_FIO_BASE(n)+LPC17_FIO_SET_OFFSET)
-#define LPC17_FIO_CLR(n) (LPC17_FIO_BASE(n)+LPC17_FIO_CLR_OFFSET)
-
-#define LPC17_FIO0_DIR (LPC17_FIO0_BASE+LPC17_FIO_DIR_OFFSET)
-#define LPC17_FIO0_MASK (LPC17_FIO0_BASE+LPC17_FIO_MASK_OFFSET)
-#define LPC17_FIO0_PIN (LPC17_FIO0_BASE+LPC17_FIO_PIN_OFFSET)
-#define LPC17_FIO0_SET (LPC17_FIO0_BASE+LPC17_FIO_SET_OFFSET)
-#define LPC17_FIO0_CLR (LPC17_FIO0_BASE+LPC17_FIO_CLR_OFFSET)
-
-#define LPC17_FIO1_DIR (LPC17_FIO1_BASE+LPC17_FIO_DIR_OFFSET)
-#define LPC17_FIO1_MASK (LPC17_FIO1_BASE+LPC17_FIO_MASK_OFFSET)
-#define LPC17_FIO1_PIN (LPC17_FIO1_BASE+LPC17_FIO_PIN_OFFSET)
-#define LPC17_FIO1_SET (LPC17_FIO1_BASE+LPC17_FIO_SET_OFFSET)
-#define LPC17_FIO1_CLR (LPC17_FIO1_BASE+LPC17_FIO_CLR_OFFSET)
-
-#define LPC17_FIO2_DIR (LPC17_FIO2_BASE+LPC17_FIO_DIR_OFFSET)
-#define LPC17_FIO2_MASK (LPC17_FIO2_BASE+LPC17_FIO_MASK_OFFSET)
-#define LPC17_FIO2_PIN (LPC17_FIO2_BASE+LPC17_FIO_PIN_OFFSET)
-#define LPC17_FIO2_SET (LPC17_FIO2_BASE+LPC17_FIO_SET_OFFSET)
-#define LPC17_FIO2_CLR (LPC17_FIO2_BASE+LPC17_FIO_CLR_OFFSET)
-
-#define LPC17_FIO3_DIR (LPC17_FIO3_BASE+LPC17_FIO_DIR_OFFSET)
-#define LPC17_FIO3_MASK (LPC17_FIO3_BASE+LPC17_FIO_MASK_OFFSET)
-#define LPC17_FIO3_PIN (LPC17_FIO3_BASE+LPC17_FIO_PIN_OFFSET)
-#define LPC17_FIO3_SET (LPC17_FIO3_BASE+LPC17_FIO_SET_OFFSET)
-#define LPC17_FIO3_CLR (LPC17_FIO3_BASE+LPC17_FIO_CLR_OFFSET)
-
-#define LPC17_FIO4_DIR (LPC17_FIO4_BASE+LPC17_FIO_DIR_OFFSET)
-#define LPC17_FIO4_MASK (LPC17_FIO4_BASE+LPC17_FIO_MASK_OFFSET)
-#define LPC17_FIO4_PIN (LPC17_FIO4_BASE+LPC17_FIO_PIN_OFFSET)
-#define LPC17_FIO4_SET (LPC17_FIO4_BASE+LPC17_FIO_SET_OFFSET)
-#define LPC17_FIO4_CLR (LPC17_FIO4_BASE+LPC17_FIO_CLR_OFFSET)
-
-/* GPIO interrupt block register addresses ******************************************/
-
-#define LPC17_GPIOINTn_BASE(n) (LPC17_GPIOINT_BASE+LPC17_GPIOINT_OFFSET(n))
-#define LPC17_GPIOINT0_BASE (LPC17_GPIOINT_BASE+LPC17_GPIOINT0_OFFSET)
-#define LPC17_GPIOINT2_BASE (LPC17_GPIOINT_BASE+LPC17_GPIOINT2_OFFSET)
-
-#define LPC17_GPIOINT_IOINTSTATUS (LPC17_GPIOINT0_BASE+LPC17_GPIOINT_IOINTSTATUS_OFFSET)
-
-#define LPC17_GPIOINT_INTSTATR(n) (LPC17_GPIOINTn_BASE(n)+LPC17_GPIOINT_INTSTATR_OFFSET)
-#define LPC17_GPIOINT_INTSTATF(n) (LPC17_GPIOINTn_BASE(n)+LPC17_GPIOINT_INTSTATF_OFFSET)
-#define LPC17_GPIOINT_INTCLR(n) (LPC17_GPIOINTn_BASE(n)+LPC17_GPIOINT_INTCLR_OFFSET)
-#define LPC17_GPIOINT_INTENR(n) (LPC17_GPIOINTn_BASE(n)+LPC17_GPIOINT_INTENR_OFFSET)
-#define LPC17_GPIOINT_INTENF(n) (LPC17_GPIOINTn_BASE(n)+LPC17_GPIOINT_INTENF_OFFSET)
-
-/* Pins P0.0-31 (P0.12-14 nad P0.31 are reserved) */
-
-#define LPC17_GPIOINT0_INTSTATR (LPC17_GPIOINT0_BASE+LPC17_GPIOINT_INTSTATR_OFFSET)
-#define LPC17_GPIOINT0_INTSTATF (LPC17_GPIOINT0_BASE+LPC17_GPIOINT_INTSTATF_OFFSET)
-#define LPC17_GPIOINT0_INTCLR (LPC17_GPIOINT0_BASE+LPC17_GPIOINT_INTCLR_OFFSET)
-#define LPC17_GPIOINT0_INTENR (LPC17_GPIOINT0_BASE+LPC17_GPIOINT_INTENR_OFFSET)
-#define LPC17_GPIOINT0_INTENF (LPC17_GPIOINT0_BASE+LPC17_GPIOINT_INTENF_OFFSET)
-
-/* Pins P2.0-13 (P0.14-31 are reserved) */
-
-#define LPC17_GPIOINT2_INTSTATR (LPC17_GPIOINT2_BASE+LPC17_GPIOINT_INTSTATR_OFFSET)
-#define LPC17_GPIOINT2_INTSTATF (LPC17_GPIOINT2_BASE+LPC17_GPIOINT_INTSTATF_OFFSET)
-#define LPC17_GPIOINT2_INTCLR (LPC17_GPIOINT2_BASE+LPC17_GPIOINT_INTCLR_OFFSET)
-#define LPC17_GPIOINT2_INTENR (LPC17_GPIOINT2_BASE+LPC17_GPIOINT_INTENR_OFFSET)
-#define LPC17_GPIOINT2_INTENF (LPC17_GPIOINT2_BASE+LPC17_GPIOINT_INTENF_OFFSET)
-
-/* Register bit definitions *********************************************************/
-/* GPIO block register bit definitions **********************************************/
-
-/* Fast GPIO Port Direction control registers (FIODIR) */
-/* Fast Mask register for ports (FIOMASK) */
-/* Fast Port Pin value registers using FIOMASK (FIOPIN) */
-/* Fast Port Output Set registers using FIOMASK (FIOSET) */
-/* Fast Port Output Clear register using FIOMASK (FIOCLR) */
-
-#define FIO(n) (1 << (n)) /* n=0,1,..31 */
-
-/* GPIO interrupt block register bit definitions ************************************/
-
-/* GPIO overall Interrupt Status (IOINTSTATUS) */
-#define GPIOINT_IOINTSTATUS_P0INT (1 << 0) /* Bit 0: Port 0 GPIO interrupt pending */
- /* Bit 1: Reserved */
-#define GPIOINT_IOINTSTATUS_P2INT (1 << 2) /* Bit 2: Port 2 GPIO interrupt pending */
- /* Bits 3-31: Reserved */
-
-/* GPIO Interrupt Status for Rising edge (INTSTATR)
- * GPIO Interrupt Status for Falling edge (INTSTATF)
- * GPIO Interrupt Clear (INTCLR)
- * GPIO Interrupt Enable for Rising edge (INTENR)
- * GPIO Interrupt Enable for Falling edge (INTENF)
- */
-
-#define GPIOINT(n) (1 << (n)) /* n=0,1,..31 */
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-/************************************************************************************
- * Public Functions
- ************************************************************************************/
-
-#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_GPIO_H */
+/************************************************************************************ + * arch/arm/src/lpc17xx/lpc17_gpio.h + * + * Copyright (C) 2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_GPIO_H +#define __ARCH_ARM_SRC_LPC17XX_LPC17_GPIO_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +#include "chip.h" +#include "lpc17_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register offsets *****************************************************************/ +/* GPIO block register offsets ******************************************************/ + +#define LPC17_FIO0_OFFSET 0x0000 +#define LPC17_FIO1_OFFSET 0x0020 +#define LPC17_FIO2_OFFSET 0x0040 +#define LPC17_FIO3_OFFSET 0x0060 +#define LPC17_FIO4_OFFSET 0x0080 + +#define LPC17_FIO_DIR_OFFSET 0x0000 /* Fast GPIO Port Direction control */ +#define LPC17_FIO_MASK_OFFSET 0x0010 /* Fast Mask register for ports */ +#define LPC17_FIO_PIN_OFFSET 0x0014 /* Fast Port Pin value registers */ +#define LPC17_FIO_SET_OFFSET 0x0018 /* Fast Port Output Set registers */ +#define LPC17_FIO_CLR_OFFSET 0x001c /* Fast Port Output Clear register */ + +/* GPIO interrupt block register offsets ********************************************/ + +#define LPC17_GPIOINT_OFFSET(n) (0x10*(n) + 0x80) +#define LPC17_GPIOINT0_OFFSET 0x0080 +#define LPC17_GPIOINT2_OFFSET 0x00a0 + +#define LPC17_GPIOINT_IOINTSTATUS_OFFSET 0x0000 /* GPIO overall Interrupt Status */ +#define LPC17_GPIOINT_INTSTATR_OFFSET 0x0004 /* GPIO Interrupt Status Rising edge */ +#define LPC17_GPIOINT_INTSTATF_OFFSET 0x0008 /* GPIO Interrupt Status Falling edge */ +#define LPC17_GPIOINT_INTCLR_OFFSET 0x000c /* GPIO Interrupt Clear */ +#define LPC17_GPIOINT_INTENR_OFFSET 0x0010 /* GPIO Interrupt Enable Rising edge */ +#define LPC17_GPIOINT_INTENF_OFFSET 0x0014 /* GPIO Interrupt Enable Falling edge */ + +/* Register addresses ***************************************************************/ +/* GPIO block register addresses ****************************************************/ + +#define LPC17_FIO_BASE(n) (LPC17_GPIO_BASE+LPC17_GPIOINT_OFFSET(n)) +#define LPC17_FIO0_BASE (LPC17_GPIO_BASE+LPC17_FIO0_OFFSET) +#define LPC17_FIO1_BASE (LPC17_GPIO_BASE+LPC17_FIO1_OFFSET) +#define LPC17_FIO2_BASE (LPC17_GPIO_BASE+LPC17_FIO2_OFFSET) +#define LPC17_FIO3_BASE (LPC17_GPIO_BASE+LPC17_FIO3_OFFSET) +#define LPC17_FIO4_BASE (LPC17_GPIO_BASE+LPC17_FIO4_OFFSET) + +#define LPC17_FIO_DIR(n) (LPC17_FIO_BASE(n)+LPC17_FIO_DIR_OFFSET) +#define LPC17_FIO_MASK(n) (LPC17_FIO_BASE(n)+LPC17_FIO_MASK_OFFSET) +#define LPC17_FIO_PIN(n) (LPC17_FIO_BASE(n)+LPC17_FIO_PIN_OFFSET) +#define LPC17_FIO_SET(n) (LPC17_FIO_BASE(n)+LPC17_FIO_SET_OFFSET) +#define LPC17_FIO_CLR(n) (LPC17_FIO_BASE(n)+LPC17_FIO_CLR_OFFSET) + +#define LPC17_FIO0_DIR (LPC17_FIO0_BASE+LPC17_FIO_DIR_OFFSET) +#define LPC17_FIO0_MASK (LPC17_FIO0_BASE+LPC17_FIO_MASK_OFFSET) +#define LPC17_FIO0_PIN (LPC17_FIO0_BASE+LPC17_FIO_PIN_OFFSET) +#define LPC17_FIO0_SET (LPC17_FIO0_BASE+LPC17_FIO_SET_OFFSET) +#define LPC17_FIO0_CLR (LPC17_FIO0_BASE+LPC17_FIO_CLR_OFFSET) + +#define LPC17_FIO1_DIR (LPC17_FIO1_BASE+LPC17_FIO_DIR_OFFSET) +#define LPC17_FIO1_MASK (LPC17_FIO1_BASE+LPC17_FIO_MASK_OFFSET) +#define LPC17_FIO1_PIN (LPC17_FIO1_BASE+LPC17_FIO_PIN_OFFSET) +#define LPC17_FIO1_SET (LPC17_FIO1_BASE+LPC17_FIO_SET_OFFSET) +#define LPC17_FIO1_CLR (LPC17_FIO1_BASE+LPC17_FIO_CLR_OFFSET) + +#define LPC17_FIO2_DIR (LPC17_FIO2_BASE+LPC17_FIO_DIR_OFFSET) +#define LPC17_FIO2_MASK (LPC17_FIO2_BASE+LPC17_FIO_MASK_OFFSET) +#define LPC17_FIO2_PIN (LPC17_FIO2_BASE+LPC17_FIO_PIN_OFFSET) +#define LPC17_FIO2_SET (LPC17_FIO2_BASE+LPC17_FIO_SET_OFFSET) +#define LPC17_FIO2_CLR (LPC17_FIO2_BASE+LPC17_FIO_CLR_OFFSET) + +#define LPC17_FIO3_DIR (LPC17_FIO3_BASE+LPC17_FIO_DIR_OFFSET) +#define LPC17_FIO3_MASK (LPC17_FIO3_BASE+LPC17_FIO_MASK_OFFSET) +#define LPC17_FIO3_PIN (LPC17_FIO3_BASE+LPC17_FIO_PIN_OFFSET) +#define LPC17_FIO3_SET (LPC17_FIO3_BASE+LPC17_FIO_SET_OFFSET) +#define LPC17_FIO3_CLR (LPC17_FIO3_BASE+LPC17_FIO_CLR_OFFSET) + +#define LPC17_FIO4_DIR (LPC17_FIO4_BASE+LPC17_FIO_DIR_OFFSET) +#define LPC17_FIO4_MASK (LPC17_FIO4_BASE+LPC17_FIO_MASK_OFFSET) +#define LPC17_FIO4_PIN (LPC17_FIO4_BASE+LPC17_FIO_PIN_OFFSET) +#define LPC17_FIO4_SET (LPC17_FIO4_BASE+LPC17_FIO_SET_OFFSET) +#define LPC17_FIO4_CLR (LPC17_FIO4_BASE+LPC17_FIO_CLR_OFFSET) + +/* GPIO interrupt block register addresses ******************************************/ + +#define LPC17_GPIOINTn_BASE(n) (LPC17_GPIOINT_BASE+LPC17_GPIOINT_OFFSET(n)) +#define LPC17_GPIOINT0_BASE (LPC17_GPIOINT_BASE+LPC17_GPIOINT0_OFFSET) +#define LPC17_GPIOINT2_BASE (LPC17_GPIOINT_BASE+LPC17_GPIOINT2_OFFSET) + +#define LPC17_GPIOINT_IOINTSTATUS (LPC17_GPIOINT0_BASE+LPC17_GPIOINT_IOINTSTATUS_OFFSET) + +#define LPC17_GPIOINT_INTSTATR(n) (LPC17_GPIOINTn_BASE(n)+LPC17_GPIOINT_INTSTATR_OFFSET) +#define LPC17_GPIOINT_INTSTATF(n) (LPC17_GPIOINTn_BASE(n)+LPC17_GPIOINT_INTSTATF_OFFSET) +#define LPC17_GPIOINT_INTCLR(n) (LPC17_GPIOINTn_BASE(n)+LPC17_GPIOINT_INTCLR_OFFSET) +#define LPC17_GPIOINT_INTENR(n) (LPC17_GPIOINTn_BASE(n)+LPC17_GPIOINT_INTENR_OFFSET) +#define LPC17_GPIOINT_INTENF(n) (LPC17_GPIOINTn_BASE(n)+LPC17_GPIOINT_INTENF_OFFSET) + +/* Pins P0.0-31 (P0.12-14 nad P0.31 are reserved) */ + +#define LPC17_GPIOINT0_INTSTATR (LPC17_GPIOINT0_BASE+LPC17_GPIOINT_INTSTATR_OFFSET) +#define LPC17_GPIOINT0_INTSTATF (LPC17_GPIOINT0_BASE+LPC17_GPIOINT_INTSTATF_OFFSET) +#define LPC17_GPIOINT0_INTCLR (LPC17_GPIOINT0_BASE+LPC17_GPIOINT_INTCLR_OFFSET) +#define LPC17_GPIOINT0_INTENR (LPC17_GPIOINT0_BASE+LPC17_GPIOINT_INTENR_OFFSET) +#define LPC17_GPIOINT0_INTENF (LPC17_GPIOINT0_BASE+LPC17_GPIOINT_INTENF_OFFSET) + +/* Pins P2.0-13 (P0.14-31 are reserved) */ + +#define LPC17_GPIOINT2_INTSTATR (LPC17_GPIOINT2_BASE+LPC17_GPIOINT_INTSTATR_OFFSET) +#define LPC17_GPIOINT2_INTSTATF (LPC17_GPIOINT2_BASE+LPC17_GPIOINT_INTSTATF_OFFSET) +#define LPC17_GPIOINT2_INTCLR (LPC17_GPIOINT2_BASE+LPC17_GPIOINT_INTCLR_OFFSET) +#define LPC17_GPIOINT2_INTENR (LPC17_GPIOINT2_BASE+LPC17_GPIOINT_INTENR_OFFSET) +#define LPC17_GPIOINT2_INTENF (LPC17_GPIOINT2_BASE+LPC17_GPIOINT_INTENF_OFFSET) + +/* Register bit definitions *********************************************************/ +/* GPIO block register bit definitions **********************************************/ + +/* Fast GPIO Port Direction control registers (FIODIR) */ +/* Fast Mask register for ports (FIOMASK) */ +/* Fast Port Pin value registers using FIOMASK (FIOPIN) */ +/* Fast Port Output Set registers using FIOMASK (FIOSET) */ +/* Fast Port Output Clear register using FIOMASK (FIOCLR) */ + +#define FIO(n) (1 << (n)) /* n=0,1,..31 */ + +/* GPIO interrupt block register bit definitions ************************************/ + +/* GPIO overall Interrupt Status (IOINTSTATUS) */ +#define GPIOINT_IOINTSTATUS_P0INT (1 << 0) /* Bit 0: Port 0 GPIO interrupt pending */ + /* Bit 1: Reserved */ +#define GPIOINT_IOINTSTATUS_P2INT (1 << 2) /* Bit 2: Port 2 GPIO interrupt pending */ + /* Bits 3-31: Reserved */ + +/* GPIO Interrupt Status for Rising edge (INTSTATR) + * GPIO Interrupt Status for Falling edge (INTSTATF) + * GPIO Interrupt Clear (INTCLR) + * GPIO Interrupt Enable for Rising edge (INTENR) + * GPIO Interrupt Enable for Falling edge (INTENF) + */ + +#define GPIOINT(n) (1 << (n)) /* n=0,1,..31 */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_GPIO_H */ diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_i2c.c b/nuttx/arch/arm/src/lpc17xx/lpc17_i2c.c index ccff276e5..48d6fefce 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_i2c.c +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_i2c.c @@ -1,545 +1,545 @@ -/*******************************************************************************
- * arch/arm/src/lpc17xx/lpc17_i2c.c
- *
- * Copyright (C) 2011 Li Zhuoyi. All rights reserved.
- * Author: Li Zhuoyi <lzyy.cn@gmail.com>
- * History: 0.1 2011-08-20 initial version
- *
- * Derived from arch/arm/src/lpc31xx/lpc31_i2c.c
- *
- * Author: David Hewson
- *
- * Copyright (C) 2010-2011 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- *******************************************************************************/
-
-/*******************************************************************************
- * Included Files
- *******************************************************************************/
-
-#include <nuttx/config.h>
-
-#include <sys/types.h>
-#include <stdint.h>
-#include <stdbool.h>
-#include <stdlib.h>
-#include <string.h>
-#include <errno.h>
-#include <debug.h>
-
-#include <nuttx/arch.h>
-#include <nuttx/i2c.h>
-
-#include <arch/irq.h>
-#include <arch/board/board.h>
-
-#include "wdog.h"
-#include "chip.h"
-#include "up_arch.h"
-#include "up_internal.h"
-#include "os_internal.h"
-
-
-#include "lpc17_internal.h"
-#include "lpc17_syscon.h"
-#include "lpc17_pinconn.h"
-#include "lpc17_i2c.h"
-
-#if defined(CONFIG_LPC17_I2C0) || defined(CONFIG_LPC17_I2C1) || defined(CONFIG_LPC17_I2C2)
-
-#ifndef GPIO_I2C1_SCL
- #define GPIO_I2C1_SCL GPIO_I2C1_SCL_1
- #define GPIO_I2C1_SDA GPIO_I2C1_SDA_1
-#endif
-#ifndef CONFIG_I2C0_FREQ
- #define CONFIG_I2C0_FREQ 100000
-#endif
-#ifndef CONFIG_I2C1_FREQ
- #define CONFIG_I2C1_FREQ 100000
-#endif
-#ifndef CONFIG_I2C2_FREQ
- #define CONFIG_I2C2_FREQ 100000
-#endif
-
-/*******************************************************************************
- * Definitions
- *******************************************************************************/
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-#define I2C_TIMEOUT ((20 * CLK_TCK) / 1000) /* 20 mS */
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-struct lpc17_i2cdev_s
-{
- struct i2c_dev_s dev; /* Generic I2C device */
- struct i2c_msg_s msg; /* a single message for legacy read/write */
- unsigned int base; /* Base address of registers */
- uint16_t irqid; /* IRQ for this device */
-
- sem_t mutex; /* Only one thread can access at a time */
- sem_t wait; /* Place to wait for state machine completion */
- volatile uint8_t state; /* State of state machine */
- WDOG_ID timeout; /* watchdog to timeout when bus hung */
-
- uint16_t wrcnt; /* number of bytes sent to tx fifo */
- uint16_t rdcnt; /* number of bytes read from rx fifo */
-};
-
-static struct lpc17_i2cdev_s i2cdevices[3];
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-static int i2c_start (struct lpc17_i2cdev_s *priv);
-static void i2c_stop (struct lpc17_i2cdev_s *priv);
-static int i2c_interrupt (int irq, FAR void *context);
-static void i2c_timeout (int argc, uint32_t arg, ...);
-
-/****************************************************************************
- * I2C device operations
- ****************************************************************************/
-
-static uint32_t i2c_setfrequency(FAR struct i2c_dev_s *dev, uint32_t frequency);
-static int i2c_setaddress(FAR struct i2c_dev_s *dev, int addr, int nbits);
-static int i2c_write(FAR struct i2c_dev_s *dev, const uint8_t *buffer, int buflen);
-static int i2c_read(FAR struct i2c_dev_s *dev, uint8_t *buffer, int buflen);
-static int i2c_transfer(FAR struct i2c_dev_s *dev, FAR struct i2c_msg_s *msgs, int count);
-
-struct i2c_ops_s lpc17_i2c_ops =
-{
- .setfrequency = i2c_setfrequency,
- .setaddress = i2c_setaddress,
- .write = i2c_write,
- .read = i2c_read,
-#ifdef CONFIG_I2C_TRANSFER
- .transfer = i2c_transfer
-#endif
-};
-
-/*******************************************************************************
- * Name: lpc17_i2c_setfrequency
- *
- * Description:
- * Set the frequence for the next transfer
- *
- *******************************************************************************/
-
-static uint32_t i2c_setfrequency(FAR struct i2c_dev_s *dev, uint32_t frequency)
-{
- struct lpc17_i2cdev_s *priv = (struct lpc17_i2cdev_s *) dev;
-
- if (frequency > 100000)
- {
- /* asymetric per 400Khz I2C spec */
- putreg32 ( LPC17_CCLK / (83 + 47) * 47 / frequency, priv->base + LPC17_I2C_SCLH_OFFSET);
- putreg32 ( LPC17_CCLK / (83 + 47) * 83 / frequency, priv->base + LPC17_I2C_SCLL_OFFSET);
- }
- else
- {
- /* 50/50 mark space ratio */
- putreg32 (LPC17_CCLK / 100 * 50 / frequency, priv->base + LPC17_I2C_SCLH_OFFSET);
- putreg32 (LPC17_CCLK / 100 * 50 / frequency, priv->base + LPC17_I2C_SCLL_OFFSET);
- }
-
- /* FIXME: This function should return the actual selected frequency */
- return frequency;
-}
-
-/*******************************************************************************
- * Name: lpc17_i2c_setaddress
- *
- * Description:
- * Set the I2C slave address for a subsequent read/write
- *
- *******************************************************************************/
-static int i2c_setaddress(FAR struct i2c_dev_s *dev, int addr, int nbits)
-{
- struct lpc17_i2cdev_s *priv = (struct lpc17_i2cdev_s *) dev;
-
- DEBUGASSERT(dev != NULL);
- DEBUGASSERT(nbits == 7 );
-
- priv->msg.addr = addr<<1;
- priv->msg.flags = 0 ;
-
- return OK;
-}
-
-/*******************************************************************************
- * Name: lpc17_i2c_write
- *
- * Description:
- * Send a block of data on I2C using the previously selected I2C
- * frequency and slave address.
- *
- *******************************************************************************/
-static int i2c_write(FAR struct i2c_dev_s *dev, const uint8_t *buffer, int buflen)
-{
- struct lpc17_i2cdev_s *priv = (struct lpc17_i2cdev_s *) dev;
- int ret;
-
- DEBUGASSERT (dev != NULL);
-
- priv->wrcnt=0;
- priv->rdcnt=0;
- priv->msg.addr &= ~0x01;
- priv->msg.buffer = (uint8_t*)buffer;
- priv->msg.length = buflen;
-
- ret = i2c_start (priv);
-
- return ret >0 ? OK : -ETIMEDOUT;
-}
-
-/*******************************************************************************
- * Name: lpc17_i2c_read
- *
- * Description:
- * Receive a block of data on I2C using the previously selected I2C
- * frequency and slave address.
- *
- *******************************************************************************/
-static int i2c_read(FAR struct i2c_dev_s *dev, uint8_t *buffer, int buflen)
-{
- struct lpc17_i2cdev_s *priv = (struct lpc17_i2cdev_s *) dev;
- int ret;
-
- DEBUGASSERT (dev != NULL);
-
- priv->wrcnt=0;
- priv->rdcnt=0;
- priv->msg.addr |= 0x01;
- priv->msg.buffer = buffer;
- priv->msg.length = buflen;
-
- ret = i2c_start (priv);
-
- return ret >0 ? OK : -ETIMEDOUT;
-}
-
-/*******************************************************************************
- * Name: i2c_start
- *
- * Description:
- * Perform a I2C transfer start
- *
- *******************************************************************************/
-static int i2c_start (struct lpc17_i2cdev_s *priv)
-{
- int ret=-1;
- sem_wait (&priv->mutex);
-
- putreg32(I2C_CONCLR_STAC|I2C_CONCLR_SIC,priv->base+LPC17_I2C_CONCLR_OFFSET);
- putreg32(I2C_CONSET_STA,priv->base+LPC17_I2C_CONSET_OFFSET);
-
- wd_start (priv->timeout, I2C_TIMEOUT, i2c_timeout, 1, (uint32_t)priv);
- sem_wait(&priv->wait);
- wd_cancel (priv->timeout);
- sem_post (&priv->mutex);
-
- if( priv-> state == 0x18 || priv->state == 0x28)
- ret=priv->wrcnt;
- else if( priv-> state == 0x50 || priv->state == 0x58)
- ret=priv->rdcnt;
- return ret;
-}
-
-/*******************************************************************************
- * Name: i2c_stop
- *
- * Description:
- * Perform a I2C transfer stop
- *
- *******************************************************************************/
-static void i2c_stop (struct lpc17_i2cdev_s *priv)
-{
- if(priv->state!=0x38)
- putreg32(I2C_CONSET_STO|I2C_CONSET_AA,priv->base+LPC17_I2C_CONSET_OFFSET);
- sem_post (&priv->wait);
-}
-
-/*******************************************************************************
- * Name: i2c_timeout
- *
- * Description:
- * Watchdog timer for timeout of I2C operation
- *
- *******************************************************************************/
-
-static void i2c_timeout (int argc, uint32_t arg, ...)
-{
- struct lpc17_i2cdev_s *priv = (struct lpc17_i2cdev_s *) arg;
-
- irqstate_t flags = irqsave();
- priv->state = 0xff;
- sem_post (&priv->wait);
- irqrestore (flags);
-}
-
-/*******************************************************************************
- * Name: i2c_interrupt
- *
- * Description:
- * The I2C Interrupt Handler
- *
- *******************************************************************************/
-
-static int i2c_interrupt (int irq, FAR void *context)
-{
- struct lpc17_i2cdev_s *priv;
-#ifdef CONFIG_LPC17_I2C0
- if (irq == LPC17_IRQ_I2C0)
- {
- priv=&i2cdevices[0];
- }
- else
-#endif
-#ifdef CONFIG_LPC17_I2C1
- if (irq == LPC17_IRQ_I2C1)
- {
- priv=&i2cdevices[1];
- }
- else
-#endif
-#ifdef CONFIG_LPC17_I2C2
- if (irq == LPC17_IRQ_I2C2)
- {
- priv=&i2cdevices[2];
- }
- else
-#endif
- {
- PANIC(OSERR_INTERNAL);
- }
-/*
- * refrence UM10360 19.10.5
- */
- uint32_t state = getreg32(priv->base+LPC17_I2C_STAT_OFFSET);
- putreg32(I2C_CONCLR_SIC,priv->base+LPC17_I2C_CONCLR_OFFSET);
- priv->state=state;
- state &=0xf8;
- switch (state)
- {
- case 0x00: //Bus Error
- case 0x20:
- case 0x30:
- case 0x38:
- case 0x48:
- i2c_stop(priv);
- break;
- case 0x08: //START
- case 0x10: //Repeat START
- putreg32(priv->msg.addr,priv->base+LPC17_I2C_DAT_OFFSET);
- putreg32(I2C_CONCLR_STAC,priv->base+LPC17_I2C_CONCLR_OFFSET);
- break;
- case 0x18:
- priv->wrcnt=0;
- putreg32(priv->msg.buffer[0],priv->base+LPC17_I2C_DAT_OFFSET);
- break;
- case 0x28:
- priv->wrcnt++;
- if(priv->wrcnt<priv->msg.length)
- putreg32(priv->msg.buffer[priv->wrcnt],priv->base+LPC17_I2C_DAT_OFFSET);
- else
- i2c_stop(priv);
- break;
- case 0x40:
- priv->rdcnt=-1;
- putreg32(I2C_CONSET_AA,priv->base+LPC17_I2C_CONSET_OFFSET);
- break;
- case 0x50:
- priv->rdcnt++;
- if(priv->rdcnt<priv->msg.length)
- priv->msg.buffer[priv->rdcnt]=getreg32(priv->base+LPC17_I2C_BUFR_OFFSET);
- if(priv->rdcnt>=priv->msg.length-1)
- putreg32(I2C_CONCLR_AAC|I2C_CONCLR_SIC,priv->base+LPC17_I2C_CONCLR_OFFSET);
- break;
- case 0x58:
- i2c_stop(priv);
- break;
- default:
- i2c_stop(priv);
- break;
- }
- return OK;
-}
-
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
-
-
-/*******************************************************************************
- * Name: up_i2cinitialize
- *
- * Description:
- * Initialise an I2C device
- *
- *******************************************************************************/
-
-struct i2c_dev_s *up_i2cinitialize(int port)
-{
- struct lpc17_i2cdev_s *priv;
-
- if (port>2)
- {
- dbg("lpc I2C Only support 0,1,2\n");
- return NULL;
- }
-
- irqstate_t flags;
- uint32_t regval;
-
- flags = irqsave();
-
- priv= &i2cdevices[port];
-#ifdef CONFIG_LPC17_I2C0
- if (port==0)
- {
- priv= (FAR struct lpc17_i2cdev_s *)&i2cdevices[0];
- priv->base = LPC17_I2C0_BASE;
- priv->irqid = LPC17_IRQ_I2C0;
-
- regval = getreg32(LPC17_SYSCON_PCONP);
- regval |= SYSCON_PCONP_PCI2C0;
- putreg32(regval, LPC17_SYSCON_PCONP);
-
- regval = getreg32(LPC17_SYSCON_PCLKSEL0);
- regval &= ~SYSCON_PCLKSEL0_I2C0_MASK;
- regval |= (SYSCON_PCLKSEL_CCLK << SYSCON_PCLKSEL0_I2C0_SHIFT);
- putreg32(regval, LPC17_SYSCON_PCLKSEL0);
-
- lpc17_configgpio(GPIO_I2C0_SCL);
- lpc17_configgpio(GPIO_I2C0_SDA);
-
- putreg32 (LPC17_CCLK/CONFIG_I2C0_FREQ/2, priv->base + LPC17_I2C_SCLH_OFFSET);
- putreg32 (LPC17_CCLK/CONFIG_I2C0_FREQ/2, priv->base + LPC17_I2C_SCLL_OFFSET);
-
- }
- else
-#endif
-#ifdef CONFIG_LPC17_I2C1
- if(port==1)
- {
- priv= (FAR struct lpc17_i2cdev_s *)&i2cdevices[1];
- priv->base = LPC17_I2C1_BASE;
- priv->irqid = LPC17_IRQ_I2C1;
-
- regval = getreg32(LPC17_SYSCON_PCONP);
- regval |= SYSCON_PCONP_PCI2C1;
- putreg32(regval, LPC17_SYSCON_PCONP);
-
- regval = getreg32(LPC17_SYSCON_PCLKSEL1);
- regval &= ~SYSCON_PCLKSEL1_I2C1_MASK;
- regval |= (SYSCON_PCLKSEL_CCLK << SYSCON_PCLKSEL1_I2C1_SHIFT);
- putreg32(regval, LPC17_SYSCON_PCLKSEL1);
-
- lpc17_configgpio(GPIO_I2C1_SCL);
- lpc17_configgpio(GPIO_I2C1_SDA);
-
- putreg32 (LPC17_CCLK/CONFIG_I2C1_FREQ/2, priv->base + LPC17_I2C_SCLH_OFFSET);
- putreg32 (LPC17_CCLK/CONFIG_I2C1_FREQ/2, priv->base + LPC17_I2C_SCLL_OFFSET);
- }
- else
-#endif
-#ifdef CONFIG_LPC17_I2C2
- if(port==2)
- {
- priv= (FAR struct lpc17_i2cdev_s *)&i2cdevices[2];
- priv->base = LPC17_I2C2_BASE;
- priv->irqid = LPC17_IRQ_I2C2;
-
- regval = getreg32(LPC17_SYSCON_PCONP);
- regval |= SYSCON_PCONP_PCI2C2;
- putreg32(regval, LPC17_SYSCON_PCONP);
-
- regval = getreg32(LPC17_SYSCON_PCLKSEL1);
- regval &= ~SYSCON_PCLKSEL1_I2C2_MASK;
- regval |= (SYSCON_PCLKSEL_CCLK << SYSCON_PCLKSEL1_I2C2_SHIFT);
- putreg32(regval, LPC17_SYSCON_PCLKSEL1);
-
- lpc17_configgpio(GPIO_I2C2_SCL);
- lpc17_configgpio(GPIO_I2C2_SDA);
-
- putreg32 (LPC17_CCLK/CONFIG_I2C2_FREQ/2, priv->base + LPC17_I2C_SCLH_OFFSET);
- putreg32 (LPC17_CCLK/CONFIG_I2C2_FREQ/2, priv->base + LPC17_I2C_SCLL_OFFSET);
- }
- else
-#endif
- {
- return NULL;
- }
- putreg32(I2C_CONSET_I2EN,priv->base+LPC17_I2C_CONSET_OFFSET);
-
- sem_init (&priv->mutex, 0, 1);
- sem_init (&priv->wait, 0, 0);
-
- /* Allocate a watchdog timer */
- priv->timeout = wd_create();
-
- DEBUGASSERT(priv->timeout != 0);
-
- /* Attach Interrupt Handler */
- irq_attach (priv->irqid, i2c_interrupt);
-
- /* Enable Interrupt Handler */
- up_enable_irq(priv->irqid);
-
- /* Install our operations */
- priv->dev.ops = &lpc17_i2c_ops;
-
- return &priv->dev;
-}
-
-/*******************************************************************************
- * Name: up_i2cuninitalize
- *
- * Description:
- * Uninitialise an I2C device
- *
- *******************************************************************************/
-
-int up_i2cuninitialize(FAR struct i2c_dev_s * dev)
-{
- struct lpc17_i2cdev_s *priv = (struct lpc17_i2cdev_s *) dev;
-
- putreg32(I2C_CONCLRT_I2ENC,priv->base+LPC17_I2C_CONCLR_OFFSET);
- up_disable_irq(priv->irqid);
- irq_detach (priv->irqid);
- return OK;
-}
-
-#endif
+/******************************************************************************* + * arch/arm/src/lpc17xx/lpc17_i2c.c + * + * Copyright (C) 2011 Li Zhuoyi. All rights reserved. + * Author: Li Zhuoyi <lzyy.cn@gmail.com> + * History: 0.1 2011-08-20 initial version + * + * Derived from arch/arm/src/lpc31xx/lpc31_i2c.c + * + * Author: David Hewson + * + * Copyright (C) 2010-2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + *******************************************************************************/ + +/******************************************************************************* + * Included Files + *******************************************************************************/ + +#include <nuttx/config.h> + +#include <sys/types.h> +#include <stdint.h> +#include <stdbool.h> +#include <stdlib.h> +#include <string.h> +#include <errno.h> +#include <debug.h> + +#include <nuttx/arch.h> +#include <nuttx/i2c.h> + +#include <arch/irq.h> +#include <arch/board/board.h> + +#include "wdog.h" +#include "chip.h" +#include "up_arch.h" +#include "up_internal.h" +#include "os_internal.h" + + +#include "lpc17_internal.h" +#include "lpc17_syscon.h" +#include "lpc17_pinconn.h" +#include "lpc17_i2c.h" + +#if defined(CONFIG_LPC17_I2C0) || defined(CONFIG_LPC17_I2C1) || defined(CONFIG_LPC17_I2C2) + +#ifndef GPIO_I2C1_SCL + #define GPIO_I2C1_SCL GPIO_I2C1_SCL_1 + #define GPIO_I2C1_SDA GPIO_I2C1_SDA_1 +#endif +#ifndef CONFIG_I2C0_FREQ + #define CONFIG_I2C0_FREQ 100000 +#endif +#ifndef CONFIG_I2C1_FREQ + #define CONFIG_I2C1_FREQ 100000 +#endif +#ifndef CONFIG_I2C2_FREQ + #define CONFIG_I2C2_FREQ 100000 +#endif + +/******************************************************************************* + * Definitions + *******************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define I2C_TIMEOUT ((20 * CLK_TCK) / 1000) /* 20 mS */ + +/**************************************************************************** + * Private Data + ****************************************************************************/ +struct lpc17_i2cdev_s +{ + struct i2c_dev_s dev; /* Generic I2C device */ + struct i2c_msg_s msg; /* a single message for legacy read/write */ + unsigned int base; /* Base address of registers */ + uint16_t irqid; /* IRQ for this device */ + + sem_t mutex; /* Only one thread can access at a time */ + sem_t wait; /* Place to wait for state machine completion */ + volatile uint8_t state; /* State of state machine */ + WDOG_ID timeout; /* watchdog to timeout when bus hung */ + + uint16_t wrcnt; /* number of bytes sent to tx fifo */ + uint16_t rdcnt; /* number of bytes read from rx fifo */ +}; + +static struct lpc17_i2cdev_s i2cdevices[3]; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ +static int i2c_start (struct lpc17_i2cdev_s *priv); +static void i2c_stop (struct lpc17_i2cdev_s *priv); +static int i2c_interrupt (int irq, FAR void *context); +static void i2c_timeout (int argc, uint32_t arg, ...); + +/**************************************************************************** + * I2C device operations + ****************************************************************************/ + +static uint32_t i2c_setfrequency(FAR struct i2c_dev_s *dev, uint32_t frequency); +static int i2c_setaddress(FAR struct i2c_dev_s *dev, int addr, int nbits); +static int i2c_write(FAR struct i2c_dev_s *dev, const uint8_t *buffer, int buflen); +static int i2c_read(FAR struct i2c_dev_s *dev, uint8_t *buffer, int buflen); +static int i2c_transfer(FAR struct i2c_dev_s *dev, FAR struct i2c_msg_s *msgs, int count); + +struct i2c_ops_s lpc17_i2c_ops = +{ + .setfrequency = i2c_setfrequency, + .setaddress = i2c_setaddress, + .write = i2c_write, + .read = i2c_read, +#ifdef CONFIG_I2C_TRANSFER + .transfer = i2c_transfer +#endif +}; + +/******************************************************************************* + * Name: lpc17_i2c_setfrequency + * + * Description: + * Set the frequence for the next transfer + * + *******************************************************************************/ + +static uint32_t i2c_setfrequency(FAR struct i2c_dev_s *dev, uint32_t frequency) +{ + struct lpc17_i2cdev_s *priv = (struct lpc17_i2cdev_s *) dev; + + if (frequency > 100000) + { + /* asymetric per 400Khz I2C spec */ + putreg32 ( LPC17_CCLK / (83 + 47) * 47 / frequency, priv->base + LPC17_I2C_SCLH_OFFSET); + putreg32 ( LPC17_CCLK / (83 + 47) * 83 / frequency, priv->base + LPC17_I2C_SCLL_OFFSET); + } + else + { + /* 50/50 mark space ratio */ + putreg32 (LPC17_CCLK / 100 * 50 / frequency, priv->base + LPC17_I2C_SCLH_OFFSET); + putreg32 (LPC17_CCLK / 100 * 50 / frequency, priv->base + LPC17_I2C_SCLL_OFFSET); + } + + /* FIXME: This function should return the actual selected frequency */ + return frequency; +} + +/******************************************************************************* + * Name: lpc17_i2c_setaddress + * + * Description: + * Set the I2C slave address for a subsequent read/write + * + *******************************************************************************/ +static int i2c_setaddress(FAR struct i2c_dev_s *dev, int addr, int nbits) +{ + struct lpc17_i2cdev_s *priv = (struct lpc17_i2cdev_s *) dev; + + DEBUGASSERT(dev != NULL); + DEBUGASSERT(nbits == 7 ); + + priv->msg.addr = addr<<1; + priv->msg.flags = 0 ; + + return OK; +} + +/******************************************************************************* + * Name: lpc17_i2c_write + * + * Description: + * Send a block of data on I2C using the previously selected I2C + * frequency and slave address. + * + *******************************************************************************/ +static int i2c_write(FAR struct i2c_dev_s *dev, const uint8_t *buffer, int buflen) +{ + struct lpc17_i2cdev_s *priv = (struct lpc17_i2cdev_s *) dev; + int ret; + + DEBUGASSERT (dev != NULL); + + priv->wrcnt=0; + priv->rdcnt=0; + priv->msg.addr &= ~0x01; + priv->msg.buffer = (uint8_t*)buffer; + priv->msg.length = buflen; + + ret = i2c_start (priv); + + return ret >0 ? OK : -ETIMEDOUT; +} + +/******************************************************************************* + * Name: lpc17_i2c_read + * + * Description: + * Receive a block of data on I2C using the previously selected I2C + * frequency and slave address. + * + *******************************************************************************/ +static int i2c_read(FAR struct i2c_dev_s *dev, uint8_t *buffer, int buflen) +{ + struct lpc17_i2cdev_s *priv = (struct lpc17_i2cdev_s *) dev; + int ret; + + DEBUGASSERT (dev != NULL); + + priv->wrcnt=0; + priv->rdcnt=0; + priv->msg.addr |= 0x01; + priv->msg.buffer = buffer; + priv->msg.length = buflen; + + ret = i2c_start (priv); + + return ret >0 ? OK : -ETIMEDOUT; +} + +/******************************************************************************* + * Name: i2c_start + * + * Description: + * Perform a I2C transfer start + * + *******************************************************************************/ +static int i2c_start (struct lpc17_i2cdev_s *priv) +{ + int ret=-1; + sem_wait (&priv->mutex); + + putreg32(I2C_CONCLR_STAC|I2C_CONCLR_SIC,priv->base+LPC17_I2C_CONCLR_OFFSET); + putreg32(I2C_CONSET_STA,priv->base+LPC17_I2C_CONSET_OFFSET); + + wd_start (priv->timeout, I2C_TIMEOUT, i2c_timeout, 1, (uint32_t)priv); + sem_wait(&priv->wait); + wd_cancel (priv->timeout); + sem_post (&priv->mutex); + + if( priv-> state == 0x18 || priv->state == 0x28) + ret=priv->wrcnt; + else if( priv-> state == 0x50 || priv->state == 0x58) + ret=priv->rdcnt; + return ret; +} + +/******************************************************************************* + * Name: i2c_stop + * + * Description: + * Perform a I2C transfer stop + * + *******************************************************************************/ +static void i2c_stop (struct lpc17_i2cdev_s *priv) +{ + if(priv->state!=0x38) + putreg32(I2C_CONSET_STO|I2C_CONSET_AA,priv->base+LPC17_I2C_CONSET_OFFSET); + sem_post (&priv->wait); +} + +/******************************************************************************* + * Name: i2c_timeout + * + * Description: + * Watchdog timer for timeout of I2C operation + * + *******************************************************************************/ + +static void i2c_timeout (int argc, uint32_t arg, ...) +{ + struct lpc17_i2cdev_s *priv = (struct lpc17_i2cdev_s *) arg; + + irqstate_t flags = irqsave(); + priv->state = 0xff; + sem_post (&priv->wait); + irqrestore (flags); +} + +/******************************************************************************* + * Name: i2c_interrupt + * + * Description: + * The I2C Interrupt Handler + * + *******************************************************************************/ + +static int i2c_interrupt (int irq, FAR void *context) +{ + struct lpc17_i2cdev_s *priv; +#ifdef CONFIG_LPC17_I2C0 + if (irq == LPC17_IRQ_I2C0) + { + priv=&i2cdevices[0]; + } + else +#endif +#ifdef CONFIG_LPC17_I2C1 + if (irq == LPC17_IRQ_I2C1) + { + priv=&i2cdevices[1]; + } + else +#endif +#ifdef CONFIG_LPC17_I2C2 + if (irq == LPC17_IRQ_I2C2) + { + priv=&i2cdevices[2]; + } + else +#endif + { + PANIC(OSERR_INTERNAL); + } +/* + * refrence UM10360 19.10.5 + */ + uint32_t state = getreg32(priv->base+LPC17_I2C_STAT_OFFSET); + putreg32(I2C_CONCLR_SIC,priv->base+LPC17_I2C_CONCLR_OFFSET); + priv->state=state; + state &=0xf8; + switch (state) + { + case 0x00: //Bus Error + case 0x20: + case 0x30: + case 0x38: + case 0x48: + i2c_stop(priv); + break; + case 0x08: //START + case 0x10: //Repeat START + putreg32(priv->msg.addr,priv->base+LPC17_I2C_DAT_OFFSET); + putreg32(I2C_CONCLR_STAC,priv->base+LPC17_I2C_CONCLR_OFFSET); + break; + case 0x18: + priv->wrcnt=0; + putreg32(priv->msg.buffer[0],priv->base+LPC17_I2C_DAT_OFFSET); + break; + case 0x28: + priv->wrcnt++; + if(priv->wrcnt<priv->msg.length) + putreg32(priv->msg.buffer[priv->wrcnt],priv->base+LPC17_I2C_DAT_OFFSET); + else + i2c_stop(priv); + break; + case 0x40: + priv->rdcnt=-1; + putreg32(I2C_CONSET_AA,priv->base+LPC17_I2C_CONSET_OFFSET); + break; + case 0x50: + priv->rdcnt++; + if(priv->rdcnt<priv->msg.length) + priv->msg.buffer[priv->rdcnt]=getreg32(priv->base+LPC17_I2C_BUFR_OFFSET); + if(priv->rdcnt>=priv->msg.length-1) + putreg32(I2C_CONCLR_AAC|I2C_CONCLR_SIC,priv->base+LPC17_I2C_CONCLR_OFFSET); + break; + case 0x58: + i2c_stop(priv); + break; + default: + i2c_stop(priv); + break; + } + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + + +/******************************************************************************* + * Name: up_i2cinitialize + * + * Description: + * Initialise an I2C device + * + *******************************************************************************/ + +struct i2c_dev_s *up_i2cinitialize(int port) +{ + struct lpc17_i2cdev_s *priv; + + if (port>2) + { + dbg("lpc I2C Only support 0,1,2\n"); + return NULL; + } + + irqstate_t flags; + uint32_t regval; + + flags = irqsave(); + + priv= &i2cdevices[port]; +#ifdef CONFIG_LPC17_I2C0 + if (port==0) + { + priv= (FAR struct lpc17_i2cdev_s *)&i2cdevices[0]; + priv->base = LPC17_I2C0_BASE; + priv->irqid = LPC17_IRQ_I2C0; + + regval = getreg32(LPC17_SYSCON_PCONP); + regval |= SYSCON_PCONP_PCI2C0; + putreg32(regval, LPC17_SYSCON_PCONP); + + regval = getreg32(LPC17_SYSCON_PCLKSEL0); + regval &= ~SYSCON_PCLKSEL0_I2C0_MASK; + regval |= (SYSCON_PCLKSEL_CCLK << SYSCON_PCLKSEL0_I2C0_SHIFT); + putreg32(regval, LPC17_SYSCON_PCLKSEL0); + + lpc17_configgpio(GPIO_I2C0_SCL); + lpc17_configgpio(GPIO_I2C0_SDA); + + putreg32 (LPC17_CCLK/CONFIG_I2C0_FREQ/2, priv->base + LPC17_I2C_SCLH_OFFSET); + putreg32 (LPC17_CCLK/CONFIG_I2C0_FREQ/2, priv->base + LPC17_I2C_SCLL_OFFSET); + + } + else +#endif +#ifdef CONFIG_LPC17_I2C1 + if(port==1) + { + priv= (FAR struct lpc17_i2cdev_s *)&i2cdevices[1]; + priv->base = LPC17_I2C1_BASE; + priv->irqid = LPC17_IRQ_I2C1; + + regval = getreg32(LPC17_SYSCON_PCONP); + regval |= SYSCON_PCONP_PCI2C1; + putreg32(regval, LPC17_SYSCON_PCONP); + + regval = getreg32(LPC17_SYSCON_PCLKSEL1); + regval &= ~SYSCON_PCLKSEL1_I2C1_MASK; + regval |= (SYSCON_PCLKSEL_CCLK << SYSCON_PCLKSEL1_I2C1_SHIFT); + putreg32(regval, LPC17_SYSCON_PCLKSEL1); + + lpc17_configgpio(GPIO_I2C1_SCL); + lpc17_configgpio(GPIO_I2C1_SDA); + + putreg32 (LPC17_CCLK/CONFIG_I2C1_FREQ/2, priv->base + LPC17_I2C_SCLH_OFFSET); + putreg32 (LPC17_CCLK/CONFIG_I2C1_FREQ/2, priv->base + LPC17_I2C_SCLL_OFFSET); + } + else +#endif +#ifdef CONFIG_LPC17_I2C2 + if(port==2) + { + priv= (FAR struct lpc17_i2cdev_s *)&i2cdevices[2]; + priv->base = LPC17_I2C2_BASE; + priv->irqid = LPC17_IRQ_I2C2; + + regval = getreg32(LPC17_SYSCON_PCONP); + regval |= SYSCON_PCONP_PCI2C2; + putreg32(regval, LPC17_SYSCON_PCONP); + + regval = getreg32(LPC17_SYSCON_PCLKSEL1); + regval &= ~SYSCON_PCLKSEL1_I2C2_MASK; + regval |= (SYSCON_PCLKSEL_CCLK << SYSCON_PCLKSEL1_I2C2_SHIFT); + putreg32(regval, LPC17_SYSCON_PCLKSEL1); + + lpc17_configgpio(GPIO_I2C2_SCL); + lpc17_configgpio(GPIO_I2C2_SDA); + + putreg32 (LPC17_CCLK/CONFIG_I2C2_FREQ/2, priv->base + LPC17_I2C_SCLH_OFFSET); + putreg32 (LPC17_CCLK/CONFIG_I2C2_FREQ/2, priv->base + LPC17_I2C_SCLL_OFFSET); + } + else +#endif + { + return NULL; + } + putreg32(I2C_CONSET_I2EN,priv->base+LPC17_I2C_CONSET_OFFSET); + + sem_init (&priv->mutex, 0, 1); + sem_init (&priv->wait, 0, 0); + + /* Allocate a watchdog timer */ + priv->timeout = wd_create(); + + DEBUGASSERT(priv->timeout != 0); + + /* Attach Interrupt Handler */ + irq_attach (priv->irqid, i2c_interrupt); + + /* Enable Interrupt Handler */ + up_enable_irq(priv->irqid); + + /* Install our operations */ + priv->dev.ops = &lpc17_i2c_ops; + + return &priv->dev; +} + +/******************************************************************************* + * Name: up_i2cuninitalize + * + * Description: + * Uninitialise an I2C device + * + *******************************************************************************/ + +int up_i2cuninitialize(FAR struct i2c_dev_s * dev) +{ + struct lpc17_i2cdev_s *priv = (struct lpc17_i2cdev_s *) dev; + + putreg32(I2C_CONCLRT_I2ENC,priv->base+LPC17_I2C_CONCLR_OFFSET); + up_disable_irq(priv->irqid); + irq_detach (priv->irqid); + return OK; +} + +#endif diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_i2c.h b/nuttx/arch/arm/src/lpc17xx/lpc17_i2c.h index f8e098959..10e1fbeac 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_i2c.h +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_i2c.h @@ -1,208 +1,208 @@ -/************************************************************************************
- * arch/arm/src/lpc17xx/lpc17_i2c.h
- *
- * Copyright (C) 2010 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_I2C_H
-#define __ARCH_ARM_SRC_LPC17XX_LPC17_I2C_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-
-#include "chip.h"
-#include "lpc17_memorymap.h"
-
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-
-/* Register offsets *****************************************************************/
-
-#define LPC17_I2C_CONSET_OFFSET 0x0000 /* I2C Control Set Register */
-#define LPC17_I2C_STAT_OFFSET 0x0004 /* I2C Status Register */
-#define LPC17_I2C_DAT_OFFSET 0x0008 /* I2C Data Register */
-#define LPC17_I2C_ADR0_OFFSET 0x000c /* I2C Slave Address Register 0 */
-#define LPC17_I2C_SCLH_OFFSET 0x0010 /* SCH Duty Cycle Register High Half Word */
-#define LPC17_I2C_SCLL_OFFSET 0x0014 /* SCL Duty Cycle Register Low Half Word */
-#define LPC17_I2C_CONCLR_OFFSET 0x0018 /* I2C Control Clear Register */
-#define LPC17_I2C_MMCTRL_OFFSET 0x001c /* Monitor mode control register */
-#define LPC17_I2C_ADR1_OFFSET 0x0020 /* I2C Slave Address Register 1 */
-#define LPC17_I2C_ADR2_OFFSET 0x0024 /* I2C Slave Address Register 2 */
-#define LPC17_I2C_ADR3_OFFSET 0x0028 /* I2C Slave Address Register 3 */
-#define LPC17_I2C_BUFR_OFFSET 0x002c /* Data buffer register */
-#define LPC17_I2C_MASK0_OFFSET 0x0030 /* I2C Slave address mask register 0 */
-#define LPC17_I2C_MASK1_OFFSET 0x0034 /* I2C Slave address mask register 1 */
-#define LPC17_I2C_MASK2_OFFSET 0x0038 /* I2C Slave address mask register 2 */
-#define LPC17_I2C_MASK3_OFFSET 0x003c /* I2C Slave address mask register */
-
-/* Register addresses ***************************************************************/
-
-#define LPC17_I2C0_CONSET (LPC17_I2C0_BASE+LPC17_I2C_CONSET_OFFSET)
-#define LPC17_I2C0_STAT (LPC17_I2C0_BASE+LPC17_I2C_STAT_OFFSET)
-#define LPC17_I2C0_DAT (LPC17_I2C0_BASE+LPC17_I2C_DAT_OFFSET)
-#define LPC17_I2C0_ADR0 (LPC17_I2C0_BASE+LPC17_I2C_ADR0_OFFSET)
-#define LPC17_I2C0_SCLH (LPC17_I2C0_BASE+LPC17_I2C_SCLH_OFFSET)
-#define LPC17_I2C0_SCLL (LPC17_I2C0_BASE+LPC17_I2C_SCLL_OFFSET)
-#define LPC17_I2C0_CONCLR (LPC17_I2C0_BASE+LPC17_I2C_CONCLR_OFFSET)
-#define LPC17_I2C0_MMCTRL (LPC17_I2C0_BASE+LPC17_I2C_MMCTRL_OFFSET)
-#define LPC17_I2C0_ADR1 (LPC17_I2C0_BASE+LPC17_I2C_ADR1_OFFSET)
-#define LPC17_I2C0_ADR2 (LPC17_I2C0_BASE+LPC17_I2C_ADR2_OFFSET)
-#define LPC17_I2C0_ADR3 (LPC17_I2C0_BASE+LPC17_I2C_ADR3_OFFSET)
-#define LPC17_I2C0_BUFR (LPC17_I2C0_BASE+LPC17_I2C_BUFR_OFFSET)
-#define LPC17_I2C0_MASK0 (LPC17_I2C0_BASE+LPC17_I2C_MASK0_OFFSET)
-#define LPC17_I2C0_MASK1 (LPC17_I2C0_BASE+LPC17_I2C_MASK1_OFFSET)
-#define LPC17_I2C0_MASK2 (LPC17_I2C0_BASE+LPC17_I2C_MASK2_OFFSET)
-#define LPC17_I2C0_MASK3 (LPC17_I2C0_BASE+LPC17_I2C_MASK3_OFFSET)
-
-#define LPC17_I2C1_CONSET (LPC17_I2C1_BASE+LPC17_I2C_CONSET_OFFSET)
-#define LPC17_I2C1_STAT (LPC17_I2C1_BASE+LPC17_I2C_STAT_OFFSET)
-#define LPC17_I2C1_DAT (LPC17_I2C1_BASE+LPC17_I2C_DAT_OFFSET)
-#define LPC17_I2C1_ADR0 (LPC17_I2C1_BASE+LPC17_I2C_ADR0_OFFSET)
-#define LPC17_I2C1_SCLH (LPC17_I2C1_BASE+LPC17_I2C_SCLH_OFFSET)
-#define LPC17_I2C1_SCLL (LPC17_I2C1_BASE+LPC17_I2C_SCLL_OFFSET)
-#define LPC17_I2C1_CONCLR (LPC17_I2C1_BASE+LPC17_I2C_CONCLR_OFFSET)
-#define LPC17_I2C1_MMCTRL (LPC17_I2C1_BASE+LPC17_I2C_MMCTRL_OFFSET)
-#define LPC17_I2C1_ADR1 (LPC17_I2C1_BASE+LPC17_I2C_ADR1_OFFSET)
-#define LPC17_I2C1_ADR2 (LPC17_I2C1_BASE+LPC17_I2C_ADR2_OFFSET)
-#define LPC17_I2C1_ADR3 (LPC17_I2C1_BASE+LPC17_I2C_ADR3_OFFSET)
-#define LPC17_I2C1_BUFR (LPC17_I2C1_BASE+LPC17_I2C_BUFR_OFFSET)
-#define LPC17_I2C1_MASK0 (LPC17_I2C1_BASE+LPC17_I2C_MASK0_OFFSET)
-#define LPC17_I2C1_MASK1 (LPC17_I2C1_BASE+LPC17_I2C_MASK1_OFFSET)
-#define LPC17_I2C1_MASK2 (LPC17_I2C1_BASE+LPC17_I2C_MASK2_OFFSET)
-#define LPC17_I2C1_MASK3 (LPC17_I2C1_BASE+LPC17_I2C_MASK3_OFFSET)
-
-#define LPC17_I2C2_CONSET (LPC17_I2C2_BASE+LPC17_I2C_CONSET_OFFSET)
-#define LPC17_I2C2_STAT (LPC17_I2C2_BASE+LPC17_I2C_STAT_OFFSET)
-#define LPC17_I2C2_DAT (LPC17_I2C2_BASE+LPC17_I2C_DAT_OFFSET)
-#define LPC17_I2C2_ADR0 (LPC17_I2C2_BASE+LPC17_I2C_ADR0_OFFSET)
-#define LPC17_I2C2_SCLH (LPC17_I2C2_BASE+LPC17_I2C_SCLH_OFFSET)
-#define LPC17_I2C2_SCLL (LPC17_I2C2_BASE+LPC17_I2C_SCLL_OFFSET)
-#define LPC17_I2C2_CONCLR (LPC17_I2C2_BASE+LPC17_I2C_CONCLR_OFFSET)
-#define LPC17_I2C2_MMCTRL (LPC17_I2C2_BASE+LPC17_I2C_MMCTRL_OFFSET)
-#define LPC17_I2C2_ADR1 (LPC17_I2C2_BASE+LPC17_I2C_ADR1_OFFSET)
-#define LPC17_I2C2_ADR2 (LPC17_I2C2_BASE+LPC17_I2C_ADR2_OFFSET)
-#define LPC17_I2C2_ADR3 (LPC17_I2C2_BASE+LPC17_I2C_ADR3_OFFSET)
-#define LPC17_I2C2_BUFR (LPC17_I2C2_BASE+LPC17_I2C_BUFR_OFFSET)
-#define LPC17_I2C2_MASK0 (LPC17_I2C2_BASE+LPC17_I2C_MASK0_OFFSET)
-#define LPC17_I2C2_MASK1 (LPC17_I2C2_BASE+LPC17_I2C_MASK1_OFFSET)
-#define LPC17_I2C2_MASK2 (LPC17_I2C2_BASE+LPC17_I2C_MASK2_OFFSET)
-#define LPC17_I2C2_MASK3 (LPC17_I2C2_BASE+LPC17_I2C_MASK3_OFFSET)
-
-/* Register bit definitions *********************************************************/
-/* I2C Control Set Register */
- /* Bits 0-1: Reserved */
-#define I2C_CONSET_AA (1 << 2) /* Bit 2: Assert acknowledge flag */
-#define I2C_CONSET_SI (1 << 3) /* Bit 3: I2C interrupt flag */
-#define I2C_CONSET_STO (1 << 4) /* Bit 4: STOP flag */
-#define I2C_CONSET_STA (1 << 5) /* Bit 5: START flag */
-#define I2C_CONSET_I2EN (1 << 6) /* Bit 6: I2C interface enable */
- /* Bits 7-31: Reserved */
-/* I2C Control Clear Register */
- /* Bits 0-1: Reserved */
-#define I2C_CONCLR_AAC (1 << 2) /* Bit 2: Assert acknowledge Clear bit */
-#define I2C_CONCLR_SIC (1 << 3) /* Bit 3: I2C interrupt Clear bit */
- /* Bit 4: Reserved */
-#define I2C_CONCLR_STAC (1 << 5) /* Bit 5: START flag Clear bit */
-#define I2C_CONCLRT_I2ENC (1 << 6) /* Bit 6: I2C interface Disable bit */
- /* Bits 7-31: Reserved */
-/* I2C Status Register
- *
- * See tables 399-402 in the "LPC17xx User Manual" (UM10360), Rev. 01, 4 January
- * 2010, NXP for definitions of status codes.
- */
-
-#define I2C_STAT_MASK (0xff) /* Bits 0-7: I2C interface status
- * Bits 0-1 always zero */
- /* Bits 8-31: Reserved */
-/* I2C Data Register */
-
-#define I2C_DAT_MASK (0xff) /* Bits 0-7: I2C data */
- /* Bits 8-31: Reserved */
-/* Monitor mode control register */
-
-#define I2C_MMCTRL_MMENA (1 << 0) /* Bit 0: Monitor mode enable */
-#define I2C_MMCTRL_ENASCL (1 << 1) /* Bit 1: SCL output enable */
-#define I2C_MMCTRL_MATCHALL (1 << 2) /* Bit 2: Select interrupt register match */
- /* Bits 3-31: Reserved */
-/* Data buffer register */
-
-#define I2C_BUFR_MASK (0xff) /* Bits 0-7: 8 MSBs of the I2DAT shift register */
- /* Bits 8-31: Reserved */
-/* I2C Slave address registers:
- *
- * I2C Slave Address Register 0
- * I2C Slave Address Register 1
- * I2C Slave Address Register 2
- * I2C Slave Address Register 3
- */
-
-#define I2C_ADR_GC (1 << 0) /* Bit 0: GC General Call enable bit */
-#define I2C_ADR_ADDR_SHIFT (1) /* Bits 1-7: I2C slave address */
-#define I2C_ADR_ADDR_MASK (0x7f << I2C_ADR_ADDR_SHIFT)
- /* Bits 8-31: Reserved */
-/* I2C Slave address mask registers:
- *
- * I2C Slave address mask register 0
- * I2C Slave address mask register 1
- * I2C Slave address mask register 2
- * I2C Slave address mask register 3
- */
- /* Bit 0: Reserved */
-#define I2C_MASK_SHIFT (1) /* Bits 1-7: I2C mask bits */
-#define I2C_MASK_MASK (0x7f << I2C_ADR_ADDR_SHIFT)
- /* Bits 8-31: Reserved */
-/* SCH Duty Cycle Register High Half Word */
-
-#define I2C_SCLH_MASK (0xffff) /* Bit 0-15: Count for SCL HIGH time period selection */
- /* Bits 16-31: Reserved */
-/* SCL Duty Cycle Register Low Half Word */
-
-#define I2C_SCLL_MASK (0xffff) /* Bit 0-15: Count for SCL LOW time period selection */
- /* Bits 16-31: Reserved */
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-/************************************************************************************
- * Public Functions
- ************************************************************************************/
-
-#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_I2C_H */
+/************************************************************************************ + * arch/arm/src/lpc17xx/lpc17_i2c.h + * + * Copyright (C) 2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_I2C_H +#define __ARCH_ARM_SRC_LPC17XX_LPC17_I2C_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +#include "chip.h" +#include "lpc17_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register offsets *****************************************************************/ + +#define LPC17_I2C_CONSET_OFFSET 0x0000 /* I2C Control Set Register */ +#define LPC17_I2C_STAT_OFFSET 0x0004 /* I2C Status Register */ +#define LPC17_I2C_DAT_OFFSET 0x0008 /* I2C Data Register */ +#define LPC17_I2C_ADR0_OFFSET 0x000c /* I2C Slave Address Register 0 */ +#define LPC17_I2C_SCLH_OFFSET 0x0010 /* SCH Duty Cycle Register High Half Word */ +#define LPC17_I2C_SCLL_OFFSET 0x0014 /* SCL Duty Cycle Register Low Half Word */ +#define LPC17_I2C_CONCLR_OFFSET 0x0018 /* I2C Control Clear Register */ +#define LPC17_I2C_MMCTRL_OFFSET 0x001c /* Monitor mode control register */ +#define LPC17_I2C_ADR1_OFFSET 0x0020 /* I2C Slave Address Register 1 */ +#define LPC17_I2C_ADR2_OFFSET 0x0024 /* I2C Slave Address Register 2 */ +#define LPC17_I2C_ADR3_OFFSET 0x0028 /* I2C Slave Address Register 3 */ +#define LPC17_I2C_BUFR_OFFSET 0x002c /* Data buffer register */ +#define LPC17_I2C_MASK0_OFFSET 0x0030 /* I2C Slave address mask register 0 */ +#define LPC17_I2C_MASK1_OFFSET 0x0034 /* I2C Slave address mask register 1 */ +#define LPC17_I2C_MASK2_OFFSET 0x0038 /* I2C Slave address mask register 2 */ +#define LPC17_I2C_MASK3_OFFSET 0x003c /* I2C Slave address mask register */ + +/* Register addresses ***************************************************************/ + +#define LPC17_I2C0_CONSET (LPC17_I2C0_BASE+LPC17_I2C_CONSET_OFFSET) +#define LPC17_I2C0_STAT (LPC17_I2C0_BASE+LPC17_I2C_STAT_OFFSET) +#define LPC17_I2C0_DAT (LPC17_I2C0_BASE+LPC17_I2C_DAT_OFFSET) +#define LPC17_I2C0_ADR0 (LPC17_I2C0_BASE+LPC17_I2C_ADR0_OFFSET) +#define LPC17_I2C0_SCLH (LPC17_I2C0_BASE+LPC17_I2C_SCLH_OFFSET) +#define LPC17_I2C0_SCLL (LPC17_I2C0_BASE+LPC17_I2C_SCLL_OFFSET) +#define LPC17_I2C0_CONCLR (LPC17_I2C0_BASE+LPC17_I2C_CONCLR_OFFSET) +#define LPC17_I2C0_MMCTRL (LPC17_I2C0_BASE+LPC17_I2C_MMCTRL_OFFSET) +#define LPC17_I2C0_ADR1 (LPC17_I2C0_BASE+LPC17_I2C_ADR1_OFFSET) +#define LPC17_I2C0_ADR2 (LPC17_I2C0_BASE+LPC17_I2C_ADR2_OFFSET) +#define LPC17_I2C0_ADR3 (LPC17_I2C0_BASE+LPC17_I2C_ADR3_OFFSET) +#define LPC17_I2C0_BUFR (LPC17_I2C0_BASE+LPC17_I2C_BUFR_OFFSET) +#define LPC17_I2C0_MASK0 (LPC17_I2C0_BASE+LPC17_I2C_MASK0_OFFSET) +#define LPC17_I2C0_MASK1 (LPC17_I2C0_BASE+LPC17_I2C_MASK1_OFFSET) +#define LPC17_I2C0_MASK2 (LPC17_I2C0_BASE+LPC17_I2C_MASK2_OFFSET) +#define LPC17_I2C0_MASK3 (LPC17_I2C0_BASE+LPC17_I2C_MASK3_OFFSET) + +#define LPC17_I2C1_CONSET (LPC17_I2C1_BASE+LPC17_I2C_CONSET_OFFSET) +#define LPC17_I2C1_STAT (LPC17_I2C1_BASE+LPC17_I2C_STAT_OFFSET) +#define LPC17_I2C1_DAT (LPC17_I2C1_BASE+LPC17_I2C_DAT_OFFSET) +#define LPC17_I2C1_ADR0 (LPC17_I2C1_BASE+LPC17_I2C_ADR0_OFFSET) +#define LPC17_I2C1_SCLH (LPC17_I2C1_BASE+LPC17_I2C_SCLH_OFFSET) +#define LPC17_I2C1_SCLL (LPC17_I2C1_BASE+LPC17_I2C_SCLL_OFFSET) +#define LPC17_I2C1_CONCLR (LPC17_I2C1_BASE+LPC17_I2C_CONCLR_OFFSET) +#define LPC17_I2C1_MMCTRL (LPC17_I2C1_BASE+LPC17_I2C_MMCTRL_OFFSET) +#define LPC17_I2C1_ADR1 (LPC17_I2C1_BASE+LPC17_I2C_ADR1_OFFSET) +#define LPC17_I2C1_ADR2 (LPC17_I2C1_BASE+LPC17_I2C_ADR2_OFFSET) +#define LPC17_I2C1_ADR3 (LPC17_I2C1_BASE+LPC17_I2C_ADR3_OFFSET) +#define LPC17_I2C1_BUFR (LPC17_I2C1_BASE+LPC17_I2C_BUFR_OFFSET) +#define LPC17_I2C1_MASK0 (LPC17_I2C1_BASE+LPC17_I2C_MASK0_OFFSET) +#define LPC17_I2C1_MASK1 (LPC17_I2C1_BASE+LPC17_I2C_MASK1_OFFSET) +#define LPC17_I2C1_MASK2 (LPC17_I2C1_BASE+LPC17_I2C_MASK2_OFFSET) +#define LPC17_I2C1_MASK3 (LPC17_I2C1_BASE+LPC17_I2C_MASK3_OFFSET) + +#define LPC17_I2C2_CONSET (LPC17_I2C2_BASE+LPC17_I2C_CONSET_OFFSET) +#define LPC17_I2C2_STAT (LPC17_I2C2_BASE+LPC17_I2C_STAT_OFFSET) +#define LPC17_I2C2_DAT (LPC17_I2C2_BASE+LPC17_I2C_DAT_OFFSET) +#define LPC17_I2C2_ADR0 (LPC17_I2C2_BASE+LPC17_I2C_ADR0_OFFSET) +#define LPC17_I2C2_SCLH (LPC17_I2C2_BASE+LPC17_I2C_SCLH_OFFSET) +#define LPC17_I2C2_SCLL (LPC17_I2C2_BASE+LPC17_I2C_SCLL_OFFSET) +#define LPC17_I2C2_CONCLR (LPC17_I2C2_BASE+LPC17_I2C_CONCLR_OFFSET) +#define LPC17_I2C2_MMCTRL (LPC17_I2C2_BASE+LPC17_I2C_MMCTRL_OFFSET) +#define LPC17_I2C2_ADR1 (LPC17_I2C2_BASE+LPC17_I2C_ADR1_OFFSET) +#define LPC17_I2C2_ADR2 (LPC17_I2C2_BASE+LPC17_I2C_ADR2_OFFSET) +#define LPC17_I2C2_ADR3 (LPC17_I2C2_BASE+LPC17_I2C_ADR3_OFFSET) +#define LPC17_I2C2_BUFR (LPC17_I2C2_BASE+LPC17_I2C_BUFR_OFFSET) +#define LPC17_I2C2_MASK0 (LPC17_I2C2_BASE+LPC17_I2C_MASK0_OFFSET) +#define LPC17_I2C2_MASK1 (LPC17_I2C2_BASE+LPC17_I2C_MASK1_OFFSET) +#define LPC17_I2C2_MASK2 (LPC17_I2C2_BASE+LPC17_I2C_MASK2_OFFSET) +#define LPC17_I2C2_MASK3 (LPC17_I2C2_BASE+LPC17_I2C_MASK3_OFFSET) + +/* Register bit definitions *********************************************************/ +/* I2C Control Set Register */ + /* Bits 0-1: Reserved */ +#define I2C_CONSET_AA (1 << 2) /* Bit 2: Assert acknowledge flag */ +#define I2C_CONSET_SI (1 << 3) /* Bit 3: I2C interrupt flag */ +#define I2C_CONSET_STO (1 << 4) /* Bit 4: STOP flag */ +#define I2C_CONSET_STA (1 << 5) /* Bit 5: START flag */ +#define I2C_CONSET_I2EN (1 << 6) /* Bit 6: I2C interface enable */ + /* Bits 7-31: Reserved */ +/* I2C Control Clear Register */ + /* Bits 0-1: Reserved */ +#define I2C_CONCLR_AAC (1 << 2) /* Bit 2: Assert acknowledge Clear bit */ +#define I2C_CONCLR_SIC (1 << 3) /* Bit 3: I2C interrupt Clear bit */ + /* Bit 4: Reserved */ +#define I2C_CONCLR_STAC (1 << 5) /* Bit 5: START flag Clear bit */ +#define I2C_CONCLRT_I2ENC (1 << 6) /* Bit 6: I2C interface Disable bit */ + /* Bits 7-31: Reserved */ +/* I2C Status Register + * + * See tables 399-402 in the "LPC17xx User Manual" (UM10360), Rev. 01, 4 January + * 2010, NXP for definitions of status codes. + */ + +#define I2C_STAT_MASK (0xff) /* Bits 0-7: I2C interface status + * Bits 0-1 always zero */ + /* Bits 8-31: Reserved */ +/* I2C Data Register */ + +#define I2C_DAT_MASK (0xff) /* Bits 0-7: I2C data */ + /* Bits 8-31: Reserved */ +/* Monitor mode control register */ + +#define I2C_MMCTRL_MMENA (1 << 0) /* Bit 0: Monitor mode enable */ +#define I2C_MMCTRL_ENASCL (1 << 1) /* Bit 1: SCL output enable */ +#define I2C_MMCTRL_MATCHALL (1 << 2) /* Bit 2: Select interrupt register match */ + /* Bits 3-31: Reserved */ +/* Data buffer register */ + +#define I2C_BUFR_MASK (0xff) /* Bits 0-7: 8 MSBs of the I2DAT shift register */ + /* Bits 8-31: Reserved */ +/* I2C Slave address registers: + * + * I2C Slave Address Register 0 + * I2C Slave Address Register 1 + * I2C Slave Address Register 2 + * I2C Slave Address Register 3 + */ + +#define I2C_ADR_GC (1 << 0) /* Bit 0: GC General Call enable bit */ +#define I2C_ADR_ADDR_SHIFT (1) /* Bits 1-7: I2C slave address */ +#define I2C_ADR_ADDR_MASK (0x7f << I2C_ADR_ADDR_SHIFT) + /* Bits 8-31: Reserved */ +/* I2C Slave address mask registers: + * + * I2C Slave address mask register 0 + * I2C Slave address mask register 1 + * I2C Slave address mask register 2 + * I2C Slave address mask register 3 + */ + /* Bit 0: Reserved */ +#define I2C_MASK_SHIFT (1) /* Bits 1-7: I2C mask bits */ +#define I2C_MASK_MASK (0x7f << I2C_ADR_ADDR_SHIFT) + /* Bits 8-31: Reserved */ +/* SCH Duty Cycle Register High Half Word */ + +#define I2C_SCLH_MASK (0xffff) /* Bit 0-15: Count for SCL HIGH time period selection */ + /* Bits 16-31: Reserved */ +/* SCL Duty Cycle Register Low Half Word */ + +#define I2C_SCLL_MASK (0xffff) /* Bit 0-15: Count for SCL LOW time period selection */ + /* Bits 16-31: Reserved */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_I2C_H */ diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_mcpwm.h b/nuttx/arch/arm/src/lpc17xx/lpc17_mcpwm.h index 0d562854f..370aa42de 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_mcpwm.h +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_mcpwm.h @@ -1,280 +1,280 @@ -/************************************************************************************
- * arch/arm/src/lpc17xx/lpc17_mcpwm.h
- *
- * Copyright (C) 2010 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_MCPWM_H
-#define __ARCH_ARM_SRC_LPC17XX_LPC17_MCPWM_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-
-#include "chip.h"
-#include "lpc17_memorymap.h"
-
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-
-/* Register offsets *****************************************************************/
-
-#define LPC17_MCPWM_CON_OFFSET 0x0000 /* PWM Control read address */
-#define LPC17_MCPWM_CONSET_OFFSET 0x0004 /* PWM Control set address */
-#define LPC17_MCPWM_CONCLR_OFFSET 0x0008 /* PWM Control clear address */
-#define LPC17_MCPWM_CAPCON_OFFSET 0x000c /* Capture Control read address */
-#define LPC17_MCPWM_CAPCONSET_OFFSET 0x0010 /* Capture Control set address */
-#define LPC17_MCPWM_CAPCONCLR_OFFSET 0x0014 /* Event Control clear address */
-#define LPC17_MCPWM_TC0_OFFSET 0x0018 /* Timer Counter register, channel 0 */
-#define LPC17_MCPWM_TC1_OFFSET 0x001c /* Timer Counter register, channel 1 */
-#define LPC17_MCPWM_TC2_OFFSET 0x0020 /* Timer Counter register, channel 2 */
-#define LPC17_MCPWM_LIM0_OFFSET 0x0024 /* Limit register, channel 0 */
-#define LPC17_MCPWM_LIM1_OFFSET 0x0028 /* Limit register, channel 1 */
-#define LPC17_MCPWM_LIM2_OFFSET 0x002c /* Limit register, channel 2 */
-#define LPC17_MCPWM_MAT0_OFFSET 0x0030 /* Match register, channel 0 */
-#define LPC17_MCPWM_MAT1_OFFSET 0x0034 /* Match register, channel 1 */
-#define LPC17_MCPWM_MAT2_OFFSET 0x0038 /* Match register, channel 2 */
-#define LPC17_MCPWM_DT_OFFSET 0x003c /* Dead time register */
-#define LPC17_MCPWM_CP_OFFSET 0x0040 /* Commutation Pattern register */
-#define LPC17_MCPWM_CAP0_OFFSET 0x0044 /* Capture register, channel 0 */
-#define LPC17_MCPWM_CAP1_OFFSET 0x0048 /* Capture register, channel 1 */
-#define LPC17_MCPWM_CAP2_OFFSET 0x004c /* Capture register, channel 2 */
-#define LPC17_MCPWM_INTEN_OFFSET 0x0050 /* Interrupt Enable read address */
-#define LPC17_MCPWM_INTENSET_OFFSET 0x0054 /* Interrupt Enable set address */
-#define LPC17_MCPWM_INTENCLR_OFFSET 0x0058 /* Interrupt Enable clear address */
-#define LPC17_MCPWM_CNTCON_OFFSET 0x005c /* Count Control read address */
-#define LPC17_MCPWM_CNTCONSET_OFFSET 0x0060 /* Count Control set address */
-#define LPC17_MCPWM_CNTCONCLR_OFFSET 0x0064 /* Count Control clear address */
-#define LPC17_MCPWM_INTF_OFFSET 0x0068 /* Interrupt flags read address */
-#define LPC17_MCPWM_INTFSET_OFFSET 0x006c /* Interrupt flags set address */
-#define LPC17_MCPWM_INTFCLR_OFFSET 0x0070 /* Interrupt flags clear address */
-#define LPC17_MCPWM_CAPCLR_OFFSET 0x0074 /* Capture clear address */
-
-/* Register addresses ***************************************************************/
-
-#define LPC17_MCPWM_CON (LPC17_MCPWM_BASE+LPC17_MCPWM_CON_OFFSET)
-#define LPC17_MCPWM_CONSET (LPC17_MCPWM_BASE+LPC17_MCPWM_CONSET_OFFSET)
-#define LPC17_MCPWM_CONCLR (LPC17_MCPWM_BASE+LPC17_MCPWM_CONCLR_OFFSET)
-#define LPC17_MCPWM_CAPCON (LPC17_MCPWM_BASE+LPC17_MCPWM_CAPCON_OFFSET)
-#define LPC17_MCPWM_CAPCONSET (LPC17_MCPWM_BASE+LPC17_MCPWM_CAPCONSET_OFFSET)
-#define LPC17_MCPWM_CAPCONCLR (LPC17_MCPWM_BASE+LPC17_MCPWM_CAPCONCLR_OFFSET)
-#define LPC17_MCPWM_TC0 (LPC17_MCPWM_BASE+LPC17_MCPWM_TC0_OFFSET)
-#define LPC17_MCPWM_TC1 (LPC17_MCPWM_BASE+LPC17_MCPWM_TC1_OFFSET)
-#define LPC17_MCPWM_TC2 (LPC17_MCPWM_BASE+LPC17_MCPWM_TC2_OFFSET)
-#define LPC17_MCPWM_LIM0 (LPC17_MCPWM_BASE+LPC17_MCPWM_LIM0_OFFSET)
-#define LPC17_MCPWM_LIM1 (LPC17_MCPWM_BASE+LPC17_MCPWM_LIM1_OFFSET)
-#define LPC17_MCPWM_LIM2 (LPC17_MCPWM_BASE+LPC17_MCPWM_LIM2_OFFSET)
-#define LPC17_MCPWM_MAT0 (LPC17_MCPWM_BASE+LPC17_MCPWM_MAT0_OFFSET)
-#define LPC17_MCPWM_MAT1 (LPC17_MCPWM_BASE+LPC17_MCPWM_MAT1_OFFSET)
-#define LPC17_MCPWM_MAT2 (LPC17_MCPWM_BASE+LPC17_MCPWM_MAT2_OFFSET)
-#define LPC17_MCPWM_DT (LPC17_MCPWM_BASE+LPC17_MCPWM_DT_OFFSET)
-#define LPC17_MCPWM_CP (LPC17_MCPWM_BASE+LPC17_MCPWM_CP_OFFSET)
-#define LPC17_MCPWM_CAP0 (LPC17_MCPWM_BASE+LPC17_MCPWM_CAP0_OFFSET)
-#define LPC17_MCPWM_CAP1 (LPC17_MCPWM_BASE+LPC17_MCPWM_CAP1_OFFSET)
-#define LPC17_MCPWM_CAP2 (LPC17_MCPWM_BASE+LPC17_MCPWM_CAP2_OFFSET)
-#define LPC17_MCPWM_INTEN (LPC17_MCPWM_BASE+LPC17_MCPWM_INTEN_OFFSET)
-#define LPC17_MCPWM_INTENSET (LPC17_MCPWM_BASE+LPC17_MCPWM_INTENSET_OFFSET)
-#define LPC17_MCPWM_INTENCLR (LPC17_MCPWM_BASE+LPC17_MCPWM_INTENCLR_OFFSET)
-#define LPC17_MCPWM_CNTCON (LPC17_MCPWM_BASE+LPC17_MCPWM_CNTCON_OFFSET)
-#define LPC17_MCPWM_CNTCONSET (LPC17_MCPWM_BASE+LPC17_MCPWM_CNTCONSET_OFFSET)
-#define LPC17_MCPWM_CNTCONCLR (LPC17_MCPWM_BASE+LPC17_MCPWM_CNTCONCLR_OFFSET)
-#define LPC17_MCPWM_INTF (LPC17_MCPWM_BASE+LPC17_MCPWM_INTF_OFFSET)
-#define LPC17_MCPWM_INTFSET (LPC17_MCPWM_BASE+LPC17_MCPWM_INTFSET_OFFSET)
-#define LPC17_MCPWM_INTFCLR (LPC17_MCPWM_BASE+LPC17_MCPWM_INTFCLR_OFFSET)
-#define LPC17_MCPWM_CAPCLR (LPC17_MCPWM_BASE+LPC17_MCPWM_CAPCLR_OFFSET)
-
-/* Register bit definitions *********************************************************/
-/* There are no bit field definitions for the following registers because they support
- * 32-bit values:
- *
- * - Timer Counter register, channel 0 (TC0), Timer Counter register, channel 1 (TC1),
- * and Timer Counter register, channel 2 (TC2): 32-bit Timer/Counter values for
- * channels 0, 1, 2 (no bit field definitions)
- *
- * - Limit register, channel 0 (LIM0), Limit register, channel 1 (LIM1), and Limit
- * register, channel 2 (LIM2): 32-bit Limit values for TC0, 1, 2 (no bit field
- * definitions)
- *
- * - Match register, channel 0 MAT0), Match register, channel 1 (MAT1), and Match
- * register, channel 2 (MAT2): 32-bit Match values for TC0, 1, 2 (no bit field
- * definitions).
- *
- * - Capture register, channel 0 (CAP0), Capture register, channel 1 (CAP1), and
- * Capture register, channel 2 (CAP2): 32-bit TC value at a capture event for
- * channels 0, 1, 2 (no bit field definitions)
- */
-
-/* PWM Control read address (CON), PWM Control set address (CONSET), and PWM Control
- * clear address (CONCLR) common regiser bit definitions.
- */
-
-#define MCPWM_CON_RUN0 (1 << 0) /* Bit 0: Stops/starts timer channel 0 */
-#define MCPWM_CON_CENTER0 (1 << 1) /* Bit 1: Chan 0 edge/center aligned operation */
-#define MCPWM_CON_POLA0 (1 << 2) /* Bit 2: Polarity of MCOA0 and MCOB0 */
-#define MCPWM_CON_DTE0 (1 << 3) /* Bit 3: Dead time feature control */
-#define MCPWM_CON_DISUP0 (1 << 4) /* Bit 4: Enable/disable register updates */
- /* Bits 5-7: Reserved */
-#define MCPWM_CON_RUN1 (1 << 8) /* Bit 8: Stops/starts timer channel 1 */
-#define MCPWM_CON_CENTER1 (1 << 9) /* Bit 9: Chan 1 edge/center aligned operation */
-#define MCPWM_CON_POLA1 (1 << 10) /* Bit 10: Polarity of MCOA1 and MCOB1 */
-#define MCPWM_CON_DTE1 (1 << 11) /* Bit 11: Dead time feature control */
-#define MCPWM_CON_DISUP1 (1 << 12) /* Bit 12: Enable/disable register updates */
- /* Bits 13-15: Reserved */
-#define MCPWM_CON_RUN2 (1 << 16) /* Bit 16: Stops/starts timer channel 2 */
-#define MCPWM_CON_CENTER2 (1 << 17) /* Bit 17: Chan 2 edge/center aligned operation */
-#define MCPWM_CON_POLA2 (1 << 18) /* Bit 18: Polarity of MCOA1 and MCOB1 */
-#define MCPWM_CON_DTE2 (1 << 19) /* Bit 19: Dead time feature control */
-#define MCPWM_CON_DISUP2 (1 << 20) /* Bit 20: Enable/disable register updates */
- /* Bits 21-28: Reserved */
-#define MCPWM_CON_INVBDC (1 << 29) /* Bit 29: Polarity of MCOB outputs (all channels) */
-#define MCPWM_CON_ACMODE (1 << 30) /* Bit 30: 3-phase AC mode select */
-#define MCPWM_CON_DCMODE (1 << 31) /* Bit 31: 3-phase DC mode select */
-
-/* Capture Control read address (CAPCON), Capture Control set address (CAPCONSET),
- * and Event Control clear address (CAPCONCLR) common register bit defintions
- */
-
-#define MCPWM_CAPCON_CAP0MCI0RE (1 << 0) /* Bit 0: Enable chan0 rising edge capture MCI0 */
-#define MCPWM_CAPCON_CAP0MCI0FE (1 << 1) /* Bit 1: Enable chan 0 falling edge capture MCI0 */
-#define MCPWM_CAPCON_CAP0MCI1RE (1 << 2) /* Bit 2: Enable chan 0 rising edge capture MCI1 */
-#define MCPWM_CAPCON_CAP0MCI1FE (1 << 3) /* Bit 3: Enable chan 0 falling edge capture MCI1 */
-#define MCPWM_CAPCON_CAP0MCI2RE (1 << 4) /* Bit 4: Enable chan 0 rising edge capture MCI2 */
-#define MCPWM_CAPCON_CAP0MCI2FE (1 << 5) /* Bit 5: Enable chan 0 falling edge capture MCI2 */
-#define MCPWM_CAPCON_CAP1MCI0RE (1 << 6) /* Bit 6: Enable chan 1 rising edge capture MCI0 */
-#define MCPWM_CAPCON_CAP1MCI0FE (1 << 7) /* Bit 7: Enable chan 1 falling edge capture MCI0 */
-#define MCPWM_CAPCON_CAP1MCI1RE (1 << 8) /* Bit 8: Enable chan 1 rising edge capture MCI1 */
-#define MCPWM_CAPCON_CAP1MCI1FE (1 << 9) /* Bit 9: Enable chan 1 falling edge capture MCI1 */
-#define MCPWM_CAPCON_CAP1MCI2RE (1 << 10) /* Bit 10: Enable chan 1 rising edge capture MCI2 */
-#define MCPWM_CAPCON_CAP1MCI2FE (1 << 11) /* Bit 11: Enable chan 1 falling edge capture MCI2 */
-#define MCPWM_CAPCON_CAP2MCI0RE (1 << 12) /* Bit 12: Enable chan 2 rising edge capture MCI0 */
-#define MCPWM_CAPCON_CAP2MCI0FE (1 << 13) /* Bit 13: Enable chan 2 falling edge capture MCI0 */
-#define MCPWM_CAPCON_CAP2MCI1RE (1 << 14) /* Bit 14: Enable chan 2 rising edge capture MCI1 */
-#define MCPWM_CAPCON_CAP2MCI1FE (1 << 15) /* Bit 15: Enable chan 2 falling edge capture MCI1 */
-#define MCPWM_CAPCON_CAP2MCI2RE (1 << 16) /* Bit 16: Enable chan 2 rising edge capture MCI2 */
-#define MCPWM_CAPCON_CAP2MCI2FE (1 << 17) /* Bit 17: Enable chan 2 falling edge capture MCI2 */
-#define MCPWM_CAPCON_RT0 (1 << 18) /* Bit 18: TC0 reset by chan 0 capture event */
-#define MCPWM_CAPCON_RT1 (1 << 19) /* Bit 19: TC1 reset by chan 1 capture event */
-#define MCPWM_CAPCON_RT2 (1 << 20) /* Bit 20: TC2 reset by chan 2 capture event */
-#define MCPWM_CAPCON_HNFCAP0 (1 << 21) /* Bit 21: Hardware noise filter */
-#define MCPWM_CAPCON_HNFCAP1 (1 << 22) /* Bit 22: Hardware noise filter */
-#define MCPWM_CAPCON_HNFCAP2 (1 << 23) /* Bit 23: Hardware noise filter */
- /* Bits 24-31: Reserved
-/* Dead time register */
-
-#define MCPWM_DT_DT0_SHIFT (0) /* Bits 0-9: Dead time for channel 0 */
-#define MCPWM_DT_DT0_MASK (0x03ff << MCPWM_DT_DT0_SHIFT)
-#define MCPWM_DT_DT1_SHIFT (10) /* Bits 10-19: Dead time for channel 1 */
-#define MCPWM_DT_DT1_MASK (0x03ff << MCPWM_DT_DT1_SHIFT)
-#define MCPWM_DT_DT2_SHIFT (20) /* Bits 20-29: Dead time for channel 2 */
-#define MCPWM_DT_DT2_MASK (0x03ff << MCPWM_DT_DT2_SHIFT)
- /* Bits 30-31: reserved */
-/* Commutation Pattern register */
-
-#define MCPWM_CP_CCPA0 (1 << 0) /* Bit 0: Iinternal MCOA0 */
-#define MCPWM_CP_CCPB0 (1 << 1) /* Bit 1: MCOB0 tracks internal MCOA0 */
-#define MCPWM_CP_CCPA1 (1 << 2) /* Bit 2: MCOA1 tracks internal MCOA0 */
-#define MCPWM_CP_CCPB1 (1 << 3) /* Bit 3: MCOB1 tracks internal MCOA0 */
-#define MCPWM_CP_CCPA2 (1 << 4) /* Bit 4: MCOA2 tracks internal MCOA0 */
-#define MCPWM_CP_CCPB2 (1 << 5) /* Bit 5: MCOB2 tracks internal MCOA0 */
- /* Bits 6-31: reserved */
-
-/* Interrupt Enable read address (INTEN), Interrupt Enable set address (INTENSET),
- * Interrupt Enable clear address (INTENCLR), Interrupt flags read address (INTF),
- * Interrupt flags set address (INTFSET), and Interrupt flags clear address (INTFCLR)
- * common bit field definitions
- */
-
-#define MCPWM_INT_ILIM0 (1 << 0) /* Bit 0: Limit interrupts for channel 0 */
-#define MCPWM_INT_IMAT0 (1 << 1) /* Bit 1: Match interrupts for channel 0 */
-#define MCPWM_INT_ICAP0 (1 << 2) /* Bit 2: Capture interrupts for channel 0 */
- /* Bit 3: Reserved */
-#define MCPWM_INT_ILIM1 (1 << 4) /* Bit 4: Limit interrupts for channel 1 */
-#define MCPWM_INT_IMAT1 (1 << 5) /* Bit 5: Match interrupts for channel 1 */
-#define MCPWM_INT_ICAP1 (1 << 6) /* Bit 6: Capture interrupts for channel 1 */
- /* Bit 7: Reserved */
-#define MCPWM_INT_ILIM2 (1 << 8) /* Bit 8: Limit interrupts for channel 2 */
-#define MCPWM_INT_IMAT2 (1 << 9) /* Bit 9: Match interrupts for channel 2 */
-#define MCPWM_INT_ICAP2 (1 << 10) /* Bit 10: Capture interrupts for channel 2 */
- /* Bits 11-14: Reserved */
-#define MCPWM_INT_ABORT (1 << 15) /* Bit 15: Fast abort interrupt */
- /* Bits 16-31: Reserved */
-
-/* Count Control read address (CNTCON), Count Control set address (CNTCONSET), and
- * Count Control clear address (CNTCONCLR) common register bit definitions.
- */
-
-#define MCPWM_CNTCON_TC0MCI0RE (1 << 0) /* Bit 0: Counter 0 incr on rising edge MCI0 */
-#define MCPWM_CNTCON_TC0MCI0FE (1 << 1) /* Bit 1: Counter 0 incr onfalling edge MCI0 */
-#define MCPWM_CNTCON_TC0MCI1RE (1 << 2) /* Bit 2: Counter 0 incr onrising edge MCI1 */
-#define MCPWM_CNTCON_TC0MCI1FE (1 << 3) /* Bit 3: Counter 0 incr onfalling edge MCI1 */
-#define MCPWM_CNTCON_TC0MCI2RE (1 << 4) /* Bit 4: Counter 0 incr onrising edge MCI2 */
-#define MCPWM_CNTCON_TC0MCI2FE (1 << 5) /* Bit 5: Counter 0 incr onfalling edge MCI2 */
-#define MCPWM_CNTCON_TC1MCI0RE (1 << 6) /* Bit 6: Counter 1 incr onrising edge MCI0 */
-#define MCPWM_CNTCON_TC1MCI0FE (1 << 7) /* Bit 7: Counter 1 incr onfalling edge MCI0 */
-#define MCPWM_CNTCON_TC1MCI1RE (1 << 8) /* Bit 8: Counter 1 incr onrising edge MCI1 */
-#define MCPWM_CNTCON_TC1MCI1FE (1 << 9) /* Bit 9: Counter 1 incr onfalling edge MCI1 */
-#define MCPWM_CNTCON_TC1MCI2RE (1 << 10) /* Bit 10: Counter 1 incr onrising edge MCI2 */
-#define MCPWM_CNTCON_TC1MCI2FE (1 << 11) /* Bit 11: Counter 1 incr onfalling edge MCI2 */
-#define MCPWM_CNTCON_TC2MCI0RE (1 << 12) /* Bit 12: Counter 2 incr onrising edge MCI0 */
-#define MCPWM_CNTCON_TC2MCI0FE (1 << 13) /* Bit 13: Counter 2 incr onfalling edge MCI0 */
-#define MCPWM_CNTCON_TC2MCI1RE (1 << 14) /* Bit 14: Counter 2 incr onrising edge MCI1 */
-#define MCPWM_CNTCON_TC2MCI1FE (1 << 15) /* Bit 15: Counter 2 incr onfalling edge MCI1 */
-#define MCPWM_CNTCON_TC2MCI2RE (1 << 16) /* Bit 16: Counter 2 incr onrising edge MCI2 */
-#define MCPWM_CNTCON_TC2MCI2FE (1 << 17) /* Bit 17: Counter 2 incr onfalling edge MCI2 */
- /* Bits 28-28: Reserved */
-#define MCPWM_CNTCON_CNTR0 (1 << 29) /* Bit 29: Channel 0 counter mode */
-#define MCPWM_CNTCON_CNTR1 (1 << 30) /* Bit 30: Channel 1 counter mode */
-#define MCPWM_CNTCON_CNTR2 (1 << 31) /* Bit 31: Channel 2 counter mode */
-
-/* Capture clear address */
-
-#define MCPWM_CAPCLR_MCCLR0 (1 << 0) /* Bit 0: Clear MCCAP0 register */
-#define MCPWM_CAPCLR_MCCLR1 (1 << 1) /* Bit 1: Clear MCCAP1 register */
-#define MCPWM_CAPCLR_MCCLR2 (1 << 2) /* Bit 2: Clear MCCAP2 register */
- /* Bits 2-31: Reserved */
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-/************************************************************************************
- * Public Functions
- ************************************************************************************/
-
-#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_MCPWM_H */
+/************************************************************************************ + * arch/arm/src/lpc17xx/lpc17_mcpwm.h + * + * Copyright (C) 2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_MCPWM_H +#define __ARCH_ARM_SRC_LPC17XX_LPC17_MCPWM_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +#include "chip.h" +#include "lpc17_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register offsets *****************************************************************/ + +#define LPC17_MCPWM_CON_OFFSET 0x0000 /* PWM Control read address */ +#define LPC17_MCPWM_CONSET_OFFSET 0x0004 /* PWM Control set address */ +#define LPC17_MCPWM_CONCLR_OFFSET 0x0008 /* PWM Control clear address */ +#define LPC17_MCPWM_CAPCON_OFFSET 0x000c /* Capture Control read address */ +#define LPC17_MCPWM_CAPCONSET_OFFSET 0x0010 /* Capture Control set address */ +#define LPC17_MCPWM_CAPCONCLR_OFFSET 0x0014 /* Event Control clear address */ +#define LPC17_MCPWM_TC0_OFFSET 0x0018 /* Timer Counter register, channel 0 */ +#define LPC17_MCPWM_TC1_OFFSET 0x001c /* Timer Counter register, channel 1 */ +#define LPC17_MCPWM_TC2_OFFSET 0x0020 /* Timer Counter register, channel 2 */ +#define LPC17_MCPWM_LIM0_OFFSET 0x0024 /* Limit register, channel 0 */ +#define LPC17_MCPWM_LIM1_OFFSET 0x0028 /* Limit register, channel 1 */ +#define LPC17_MCPWM_LIM2_OFFSET 0x002c /* Limit register, channel 2 */ +#define LPC17_MCPWM_MAT0_OFFSET 0x0030 /* Match register, channel 0 */ +#define LPC17_MCPWM_MAT1_OFFSET 0x0034 /* Match register, channel 1 */ +#define LPC17_MCPWM_MAT2_OFFSET 0x0038 /* Match register, channel 2 */ +#define LPC17_MCPWM_DT_OFFSET 0x003c /* Dead time register */ +#define LPC17_MCPWM_CP_OFFSET 0x0040 /* Commutation Pattern register */ +#define LPC17_MCPWM_CAP0_OFFSET 0x0044 /* Capture register, channel 0 */ +#define LPC17_MCPWM_CAP1_OFFSET 0x0048 /* Capture register, channel 1 */ +#define LPC17_MCPWM_CAP2_OFFSET 0x004c /* Capture register, channel 2 */ +#define LPC17_MCPWM_INTEN_OFFSET 0x0050 /* Interrupt Enable read address */ +#define LPC17_MCPWM_INTENSET_OFFSET 0x0054 /* Interrupt Enable set address */ +#define LPC17_MCPWM_INTENCLR_OFFSET 0x0058 /* Interrupt Enable clear address */ +#define LPC17_MCPWM_CNTCON_OFFSET 0x005c /* Count Control read address */ +#define LPC17_MCPWM_CNTCONSET_OFFSET 0x0060 /* Count Control set address */ +#define LPC17_MCPWM_CNTCONCLR_OFFSET 0x0064 /* Count Control clear address */ +#define LPC17_MCPWM_INTF_OFFSET 0x0068 /* Interrupt flags read address */ +#define LPC17_MCPWM_INTFSET_OFFSET 0x006c /* Interrupt flags set address */ +#define LPC17_MCPWM_INTFCLR_OFFSET 0x0070 /* Interrupt flags clear address */ +#define LPC17_MCPWM_CAPCLR_OFFSET 0x0074 /* Capture clear address */ + +/* Register addresses ***************************************************************/ + +#define LPC17_MCPWM_CON (LPC17_MCPWM_BASE+LPC17_MCPWM_CON_OFFSET) +#define LPC17_MCPWM_CONSET (LPC17_MCPWM_BASE+LPC17_MCPWM_CONSET_OFFSET) +#define LPC17_MCPWM_CONCLR (LPC17_MCPWM_BASE+LPC17_MCPWM_CONCLR_OFFSET) +#define LPC17_MCPWM_CAPCON (LPC17_MCPWM_BASE+LPC17_MCPWM_CAPCON_OFFSET) +#define LPC17_MCPWM_CAPCONSET (LPC17_MCPWM_BASE+LPC17_MCPWM_CAPCONSET_OFFSET) +#define LPC17_MCPWM_CAPCONCLR (LPC17_MCPWM_BASE+LPC17_MCPWM_CAPCONCLR_OFFSET) +#define LPC17_MCPWM_TC0 (LPC17_MCPWM_BASE+LPC17_MCPWM_TC0_OFFSET) +#define LPC17_MCPWM_TC1 (LPC17_MCPWM_BASE+LPC17_MCPWM_TC1_OFFSET) +#define LPC17_MCPWM_TC2 (LPC17_MCPWM_BASE+LPC17_MCPWM_TC2_OFFSET) +#define LPC17_MCPWM_LIM0 (LPC17_MCPWM_BASE+LPC17_MCPWM_LIM0_OFFSET) +#define LPC17_MCPWM_LIM1 (LPC17_MCPWM_BASE+LPC17_MCPWM_LIM1_OFFSET) +#define LPC17_MCPWM_LIM2 (LPC17_MCPWM_BASE+LPC17_MCPWM_LIM2_OFFSET) +#define LPC17_MCPWM_MAT0 (LPC17_MCPWM_BASE+LPC17_MCPWM_MAT0_OFFSET) +#define LPC17_MCPWM_MAT1 (LPC17_MCPWM_BASE+LPC17_MCPWM_MAT1_OFFSET) +#define LPC17_MCPWM_MAT2 (LPC17_MCPWM_BASE+LPC17_MCPWM_MAT2_OFFSET) +#define LPC17_MCPWM_DT (LPC17_MCPWM_BASE+LPC17_MCPWM_DT_OFFSET) +#define LPC17_MCPWM_CP (LPC17_MCPWM_BASE+LPC17_MCPWM_CP_OFFSET) +#define LPC17_MCPWM_CAP0 (LPC17_MCPWM_BASE+LPC17_MCPWM_CAP0_OFFSET) +#define LPC17_MCPWM_CAP1 (LPC17_MCPWM_BASE+LPC17_MCPWM_CAP1_OFFSET) +#define LPC17_MCPWM_CAP2 (LPC17_MCPWM_BASE+LPC17_MCPWM_CAP2_OFFSET) +#define LPC17_MCPWM_INTEN (LPC17_MCPWM_BASE+LPC17_MCPWM_INTEN_OFFSET) +#define LPC17_MCPWM_INTENSET (LPC17_MCPWM_BASE+LPC17_MCPWM_INTENSET_OFFSET) +#define LPC17_MCPWM_INTENCLR (LPC17_MCPWM_BASE+LPC17_MCPWM_INTENCLR_OFFSET) +#define LPC17_MCPWM_CNTCON (LPC17_MCPWM_BASE+LPC17_MCPWM_CNTCON_OFFSET) +#define LPC17_MCPWM_CNTCONSET (LPC17_MCPWM_BASE+LPC17_MCPWM_CNTCONSET_OFFSET) +#define LPC17_MCPWM_CNTCONCLR (LPC17_MCPWM_BASE+LPC17_MCPWM_CNTCONCLR_OFFSET) +#define LPC17_MCPWM_INTF (LPC17_MCPWM_BASE+LPC17_MCPWM_INTF_OFFSET) +#define LPC17_MCPWM_INTFSET (LPC17_MCPWM_BASE+LPC17_MCPWM_INTFSET_OFFSET) +#define LPC17_MCPWM_INTFCLR (LPC17_MCPWM_BASE+LPC17_MCPWM_INTFCLR_OFFSET) +#define LPC17_MCPWM_CAPCLR (LPC17_MCPWM_BASE+LPC17_MCPWM_CAPCLR_OFFSET) + +/* Register bit definitions *********************************************************/ +/* There are no bit field definitions for the following registers because they support + * 32-bit values: + * + * - Timer Counter register, channel 0 (TC0), Timer Counter register, channel 1 (TC1), + * and Timer Counter register, channel 2 (TC2): 32-bit Timer/Counter values for + * channels 0, 1, 2 (no bit field definitions) + * + * - Limit register, channel 0 (LIM0), Limit register, channel 1 (LIM1), and Limit + * register, channel 2 (LIM2): 32-bit Limit values for TC0, 1, 2 (no bit field + * definitions) + * + * - Match register, channel 0 MAT0), Match register, channel 1 (MAT1), and Match + * register, channel 2 (MAT2): 32-bit Match values for TC0, 1, 2 (no bit field + * definitions). + * + * - Capture register, channel 0 (CAP0), Capture register, channel 1 (CAP1), and + * Capture register, channel 2 (CAP2): 32-bit TC value at a capture event for + * channels 0, 1, 2 (no bit field definitions) + */ + +/* PWM Control read address (CON), PWM Control set address (CONSET), and PWM Control + * clear address (CONCLR) common regiser bit definitions. + */ + +#define MCPWM_CON_RUN0 (1 << 0) /* Bit 0: Stops/starts timer channel 0 */ +#define MCPWM_CON_CENTER0 (1 << 1) /* Bit 1: Chan 0 edge/center aligned operation */ +#define MCPWM_CON_POLA0 (1 << 2) /* Bit 2: Polarity of MCOA0 and MCOB0 */ +#define MCPWM_CON_DTE0 (1 << 3) /* Bit 3: Dead time feature control */ +#define MCPWM_CON_DISUP0 (1 << 4) /* Bit 4: Enable/disable register updates */ + /* Bits 5-7: Reserved */ +#define MCPWM_CON_RUN1 (1 << 8) /* Bit 8: Stops/starts timer channel 1 */ +#define MCPWM_CON_CENTER1 (1 << 9) /* Bit 9: Chan 1 edge/center aligned operation */ +#define MCPWM_CON_POLA1 (1 << 10) /* Bit 10: Polarity of MCOA1 and MCOB1 */ +#define MCPWM_CON_DTE1 (1 << 11) /* Bit 11: Dead time feature control */ +#define MCPWM_CON_DISUP1 (1 << 12) /* Bit 12: Enable/disable register updates */ + /* Bits 13-15: Reserved */ +#define MCPWM_CON_RUN2 (1 << 16) /* Bit 16: Stops/starts timer channel 2 */ +#define MCPWM_CON_CENTER2 (1 << 17) /* Bit 17: Chan 2 edge/center aligned operation */ +#define MCPWM_CON_POLA2 (1 << 18) /* Bit 18: Polarity of MCOA1 and MCOB1 */ +#define MCPWM_CON_DTE2 (1 << 19) /* Bit 19: Dead time feature control */ +#define MCPWM_CON_DISUP2 (1 << 20) /* Bit 20: Enable/disable register updates */ + /* Bits 21-28: Reserved */ +#define MCPWM_CON_INVBDC (1 << 29) /* Bit 29: Polarity of MCOB outputs (all channels) */ +#define MCPWM_CON_ACMODE (1 << 30) /* Bit 30: 3-phase AC mode select */ +#define MCPWM_CON_DCMODE (1 << 31) /* Bit 31: 3-phase DC mode select */ + +/* Capture Control read address (CAPCON), Capture Control set address (CAPCONSET), + * and Event Control clear address (CAPCONCLR) common register bit defintions + */ + +#define MCPWM_CAPCON_CAP0MCI0RE (1 << 0) /* Bit 0: Enable chan0 rising edge capture MCI0 */ +#define MCPWM_CAPCON_CAP0MCI0FE (1 << 1) /* Bit 1: Enable chan 0 falling edge capture MCI0 */ +#define MCPWM_CAPCON_CAP0MCI1RE (1 << 2) /* Bit 2: Enable chan 0 rising edge capture MCI1 */ +#define MCPWM_CAPCON_CAP0MCI1FE (1 << 3) /* Bit 3: Enable chan 0 falling edge capture MCI1 */ +#define MCPWM_CAPCON_CAP0MCI2RE (1 << 4) /* Bit 4: Enable chan 0 rising edge capture MCI2 */ +#define MCPWM_CAPCON_CAP0MCI2FE (1 << 5) /* Bit 5: Enable chan 0 falling edge capture MCI2 */ +#define MCPWM_CAPCON_CAP1MCI0RE (1 << 6) /* Bit 6: Enable chan 1 rising edge capture MCI0 */ +#define MCPWM_CAPCON_CAP1MCI0FE (1 << 7) /* Bit 7: Enable chan 1 falling edge capture MCI0 */ +#define MCPWM_CAPCON_CAP1MCI1RE (1 << 8) /* Bit 8: Enable chan 1 rising edge capture MCI1 */ +#define MCPWM_CAPCON_CAP1MCI1FE (1 << 9) /* Bit 9: Enable chan 1 falling edge capture MCI1 */ +#define MCPWM_CAPCON_CAP1MCI2RE (1 << 10) /* Bit 10: Enable chan 1 rising edge capture MCI2 */ +#define MCPWM_CAPCON_CAP1MCI2FE (1 << 11) /* Bit 11: Enable chan 1 falling edge capture MCI2 */ +#define MCPWM_CAPCON_CAP2MCI0RE (1 << 12) /* Bit 12: Enable chan 2 rising edge capture MCI0 */ +#define MCPWM_CAPCON_CAP2MCI0FE (1 << 13) /* Bit 13: Enable chan 2 falling edge capture MCI0 */ +#define MCPWM_CAPCON_CAP2MCI1RE (1 << 14) /* Bit 14: Enable chan 2 rising edge capture MCI1 */ +#define MCPWM_CAPCON_CAP2MCI1FE (1 << 15) /* Bit 15: Enable chan 2 falling edge capture MCI1 */ +#define MCPWM_CAPCON_CAP2MCI2RE (1 << 16) /* Bit 16: Enable chan 2 rising edge capture MCI2 */ +#define MCPWM_CAPCON_CAP2MCI2FE (1 << 17) /* Bit 17: Enable chan 2 falling edge capture MCI2 */ +#define MCPWM_CAPCON_RT0 (1 << 18) /* Bit 18: TC0 reset by chan 0 capture event */ +#define MCPWM_CAPCON_RT1 (1 << 19) /* Bit 19: TC1 reset by chan 1 capture event */ +#define MCPWM_CAPCON_RT2 (1 << 20) /* Bit 20: TC2 reset by chan 2 capture event */ +#define MCPWM_CAPCON_HNFCAP0 (1 << 21) /* Bit 21: Hardware noise filter */ +#define MCPWM_CAPCON_HNFCAP1 (1 << 22) /* Bit 22: Hardware noise filter */ +#define MCPWM_CAPCON_HNFCAP2 (1 << 23) /* Bit 23: Hardware noise filter */ + /* Bits 24-31: Reserved +/* Dead time register */ + +#define MCPWM_DT_DT0_SHIFT (0) /* Bits 0-9: Dead time for channel 0 */ +#define MCPWM_DT_DT0_MASK (0x03ff << MCPWM_DT_DT0_SHIFT) +#define MCPWM_DT_DT1_SHIFT (10) /* Bits 10-19: Dead time for channel 1 */ +#define MCPWM_DT_DT1_MASK (0x03ff << MCPWM_DT_DT1_SHIFT) +#define MCPWM_DT_DT2_SHIFT (20) /* Bits 20-29: Dead time for channel 2 */ +#define MCPWM_DT_DT2_MASK (0x03ff << MCPWM_DT_DT2_SHIFT) + /* Bits 30-31: reserved */ +/* Commutation Pattern register */ + +#define MCPWM_CP_CCPA0 (1 << 0) /* Bit 0: Iinternal MCOA0 */ +#define MCPWM_CP_CCPB0 (1 << 1) /* Bit 1: MCOB0 tracks internal MCOA0 */ +#define MCPWM_CP_CCPA1 (1 << 2) /* Bit 2: MCOA1 tracks internal MCOA0 */ +#define MCPWM_CP_CCPB1 (1 << 3) /* Bit 3: MCOB1 tracks internal MCOA0 */ +#define MCPWM_CP_CCPA2 (1 << 4) /* Bit 4: MCOA2 tracks internal MCOA0 */ +#define MCPWM_CP_CCPB2 (1 << 5) /* Bit 5: MCOB2 tracks internal MCOA0 */ + /* Bits 6-31: reserved */ + +/* Interrupt Enable read address (INTEN), Interrupt Enable set address (INTENSET), + * Interrupt Enable clear address (INTENCLR), Interrupt flags read address (INTF), + * Interrupt flags set address (INTFSET), and Interrupt flags clear address (INTFCLR) + * common bit field definitions + */ + +#define MCPWM_INT_ILIM0 (1 << 0) /* Bit 0: Limit interrupts for channel 0 */ +#define MCPWM_INT_IMAT0 (1 << 1) /* Bit 1: Match interrupts for channel 0 */ +#define MCPWM_INT_ICAP0 (1 << 2) /* Bit 2: Capture interrupts for channel 0 */ + /* Bit 3: Reserved */ +#define MCPWM_INT_ILIM1 (1 << 4) /* Bit 4: Limit interrupts for channel 1 */ +#define MCPWM_INT_IMAT1 (1 << 5) /* Bit 5: Match interrupts for channel 1 */ +#define MCPWM_INT_ICAP1 (1 << 6) /* Bit 6: Capture interrupts for channel 1 */ + /* Bit 7: Reserved */ +#define MCPWM_INT_ILIM2 (1 << 8) /* Bit 8: Limit interrupts for channel 2 */ +#define MCPWM_INT_IMAT2 (1 << 9) /* Bit 9: Match interrupts for channel 2 */ +#define MCPWM_INT_ICAP2 (1 << 10) /* Bit 10: Capture interrupts for channel 2 */ + /* Bits 11-14: Reserved */ +#define MCPWM_INT_ABORT (1 << 15) /* Bit 15: Fast abort interrupt */ + /* Bits 16-31: Reserved */ + +/* Count Control read address (CNTCON), Count Control set address (CNTCONSET), and + * Count Control clear address (CNTCONCLR) common register bit definitions. + */ + +#define MCPWM_CNTCON_TC0MCI0RE (1 << 0) /* Bit 0: Counter 0 incr on rising edge MCI0 */ +#define MCPWM_CNTCON_TC0MCI0FE (1 << 1) /* Bit 1: Counter 0 incr onfalling edge MCI0 */ +#define MCPWM_CNTCON_TC0MCI1RE (1 << 2) /* Bit 2: Counter 0 incr onrising edge MCI1 */ +#define MCPWM_CNTCON_TC0MCI1FE (1 << 3) /* Bit 3: Counter 0 incr onfalling edge MCI1 */ +#define MCPWM_CNTCON_TC0MCI2RE (1 << 4) /* Bit 4: Counter 0 incr onrising edge MCI2 */ +#define MCPWM_CNTCON_TC0MCI2FE (1 << 5) /* Bit 5: Counter 0 incr onfalling edge MCI2 */ +#define MCPWM_CNTCON_TC1MCI0RE (1 << 6) /* Bit 6: Counter 1 incr onrising edge MCI0 */ +#define MCPWM_CNTCON_TC1MCI0FE (1 << 7) /* Bit 7: Counter 1 incr onfalling edge MCI0 */ +#define MCPWM_CNTCON_TC1MCI1RE (1 << 8) /* Bit 8: Counter 1 incr onrising edge MCI1 */ +#define MCPWM_CNTCON_TC1MCI1FE (1 << 9) /* Bit 9: Counter 1 incr onfalling edge MCI1 */ +#define MCPWM_CNTCON_TC1MCI2RE (1 << 10) /* Bit 10: Counter 1 incr onrising edge MCI2 */ +#define MCPWM_CNTCON_TC1MCI2FE (1 << 11) /* Bit 11: Counter 1 incr onfalling edge MCI2 */ +#define MCPWM_CNTCON_TC2MCI0RE (1 << 12) /* Bit 12: Counter 2 incr onrising edge MCI0 */ +#define MCPWM_CNTCON_TC2MCI0FE (1 << 13) /* Bit 13: Counter 2 incr onfalling edge MCI0 */ +#define MCPWM_CNTCON_TC2MCI1RE (1 << 14) /* Bit 14: Counter 2 incr onrising edge MCI1 */ +#define MCPWM_CNTCON_TC2MCI1FE (1 << 15) /* Bit 15: Counter 2 incr onfalling edge MCI1 */ +#define MCPWM_CNTCON_TC2MCI2RE (1 << 16) /* Bit 16: Counter 2 incr onrising edge MCI2 */ +#define MCPWM_CNTCON_TC2MCI2FE (1 << 17) /* Bit 17: Counter 2 incr onfalling edge MCI2 */ + /* Bits 28-28: Reserved */ +#define MCPWM_CNTCON_CNTR0 (1 << 29) /* Bit 29: Channel 0 counter mode */ +#define MCPWM_CNTCON_CNTR1 (1 << 30) /* Bit 30: Channel 1 counter mode */ +#define MCPWM_CNTCON_CNTR2 (1 << 31) /* Bit 31: Channel 2 counter mode */ + +/* Capture clear address */ + +#define MCPWM_CAPCLR_MCCLR0 (1 << 0) /* Bit 0: Clear MCCAP0 register */ +#define MCPWM_CAPCLR_MCCLR1 (1 << 1) /* Bit 1: Clear MCCAP1 register */ +#define MCPWM_CAPCLR_MCCLR2 (1 << 2) /* Bit 2: Clear MCCAP2 register */ + /* Bits 2-31: Reserved */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_MCPWM_H */ diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_memorymap.h b/nuttx/arch/arm/src/lpc17xx/lpc17_memorymap.h index da69f1481..ae66b684c 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_memorymap.h +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_memorymap.h @@ -1,136 +1,136 @@ -/************************************************************************************
- * arch/arm/src/lpc17xx/lpc17_memorymap.h
- *
- * Copyright (C) 2010 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_MEMORYMAP_H
-#define __ARCH_ARM_SRC_LPC17XX_LPC17_MEMORYMAP_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-
-#include "chip.h"
-
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-
-/* Memory Map ***********************************************************************/
-
-#define LPC17_FLASH_BASE 0x00000000 /* -0x1fffffff: On-chip non-volatile memory */
-#define LPC17_SRAM_BASE 0x10000000 /* -0x10007fff: On-chip SRAM (devices <=32Kb) */
-#define LPC17_ROM_BASE 0x1fff0000 /* -0x1fffffff: 8Kb Boot ROM with flash services */
-#define LPC17_AHBSRAM_BASE 0x20000000 /* -0x3fffffff: On-chip AHB SRAM (devices >32Kb) */
-# define LPC17_SRAM_BANK0 0x2007c000 /* -0x2007ffff: On-chip AHB SRAM Bank0 (devices >=32Kb) */
-# define LPC17_SRAM_BANK1 0x20080000 /* -0x2008ffff: On-chip AHB SRAM Bank1 (devices 64Kb) */
-#define LPC17_GPIO_BASE 0x2009c000 /* -0x2009ffff: GPIO */
-#define LPC17_APB_BASE 0x40000000 /* -0x5fffffff: APB Peripherals */
-# define LPC17_APB0_BASE 0x40000000 /* -0x4007ffff: APB0 Peripherals */
-# define LPC17_APB1_BASE 0x40080000 /* -0x400fffff: APB1 Peripherals */
-# define LPC17_AHB_BASE 0x50000000 /* -0x501fffff: DMA Controller, Ethernet, and USB */
-#define LPC17_CORTEXM3_BASE 0xe0000000 /* -0xe00fffff: (see armv7-m/nvic.h) */
-#define LPC17_SCS_BASE 0xe000e000
-#define LPC17_DEBUGMCU_BASE 0xe0042000
-
-/* AHB SRAM Bank sizes **************************************************************/
-
-#define LPC17_BANK0_SIZE (16*1024) /* Size of AHB SRAM Bank0 (if present) */
-#define LPC17_BANK1_SIZE (16*1024) /* Size of AHB SRAM Bank1 (if present) */
-
-/* APB0 Peripherals *****************************************************************/
-
-#define LPC17_WDT_BASE 0x40000000 /* -0x40003fff: Watchdog timer */
-#define LPC17_TMR0_BASE 0x40004000 /* -0x40007fff: Timer 0 */
-#define LPC17_TMR1_BASE 0x40008000 /* -0x4000bfff: Timer 1 */
-#define LPC17_UART0_BASE 0x4000c000 /* -0x4000ffff: UART 0 */
-#define LPC17_UART1_BASE 0x40010000 /* -0x40013fff: UART 1 */
- /* -0x40017fff: Reserved */
-#define LPC17_PWM1_BASE 0x40018000 /* -0x4001bfff: PWM 1 */
-#define LPC17_I2C0_BASE 0x4001c000 /* -0x4001ffff: I2C 0 */
-#define LPC17_SPI_BASE 0x40020000 /* -0x40023fff: SPI */
-#define LPC17_RTC_BASE 0x40024000 /* -0x40027fff: RTC + backup registers */
-#define LPC17_GPIOINT_BASE 0x40028000 /* -0x4002bfff: GPIO interrupts */
-#define LPC17_PINCONN_BASE 0x4002c000 /* -0x4002ffff: Pin connect block */
-#define LPC17_SSP1_BASE 0x40030000 /* -0x40033fff: SSP 1 */
-#define LPC17_ADC_BASE 0x40034000 /* -0x40037fff: ADC */
-#define LPC17_CANAFRAM_BASE 0x40038000 /* -0x4003bfff: CAN acceptance filter (AF) RAM */
-#define LPC17_CANAF_BASE 0x4003c000 /* -0x4003ffff: CAN acceptance filter (AF) registers */
-#define LPC17_CAN_BASE 0x40040000 /* -0x40043fff: CAN common registers */
-#define LPC17_CAN1_BASE 0x40044000 /* -0x40047fff: CAN controller l */
-#define LPC17_CAN2_BASE 0x40048000 /* -0x4004bfff: CAN controller 2 */
- /* -0x4005bfff: Reserved */
-#define LPC17_I2C1_BASE 0x4005c000 /* -0x4005ffff: I2C 1 */
- /* -0x4007ffff: Reserved */
-
-/* APB1 Peripherals *****************************************************************/
-
- /* -0x40087fff: Reserved */
-#define LPC17_SSP0_BASE 0x40088000 /* -0x4008bfff: SSP 0 */
-#define LPC17_DAC_BASE 0x4008c000 /* -0x4008ffff: DAC */
-#define LPC17_TMR2_BASE 0x40090000 /* -0x40093fff: Timer 2 */
-#define LPC17_TMR3_BASE 0x40094000 /* -0x40097fff: Timer 3 */
-#define LPC17_UART2_BASE 0x40098000 /* -0x4009bfff: UART 2 */
-#define LPC17_UART3_BASE 0x4009c000 /* -0x4009ffff: UART 3 */
-#define LPC17_I2C2_BASE 0x400a0000 /* -0x400a3fff: I2C 2 */
- /* -0x400a7fff: Reserved */
-#define LPC17_I2S_BASE 0x400a8000 /* -0x400abfff: I2S */
- /* -0x400affff: Reserved */
-#define LPC17_RIT_BASE 0x400b0000 /* -0x400b3fff: Repetitive interrupt timer */
- /* -0x400b7fff: Reserved */
-#define LPC17_MCPWM_BASE 0x400b8000 /* -0x400bbfff: Motor control PWM */
-#define LPC17_QEI_BASE 0x400bc000 /* -0x400bffff: Quadrature encoder interface */
- /* -0x400fbfff: Reserved */
-#define LPC17_SYSCON_BASE 0x400fc000 /* -0x400fffff: System control */
-
-/* AHB Peripherals ******************************************************************/
-
-#define LPC17_ETH_BASE 0x50000000 /* -0x50003fff: Ethernet controller */
-#define LPC17_GPDMA_BASE 0x50004000 /* -0x50007fff: GPDMA controller */
-#define LPC17_USB_BASE 0x5000c000 /* -0x5000cfff: USB controller */
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-/************************************************************************************
- * Public Functions
- ************************************************************************************/
-
-#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_MEMORYMAP_H */
+/************************************************************************************ + * arch/arm/src/lpc17xx/lpc17_memorymap.h + * + * Copyright (C) 2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_MEMORYMAP_H +#define __ARCH_ARM_SRC_LPC17XX_LPC17_MEMORYMAP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +#include "chip.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Memory Map ***********************************************************************/ + +#define LPC17_FLASH_BASE 0x00000000 /* -0x1fffffff: On-chip non-volatile memory */ +#define LPC17_SRAM_BASE 0x10000000 /* -0x10007fff: On-chip SRAM (devices <=32Kb) */ +#define LPC17_ROM_BASE 0x1fff0000 /* -0x1fffffff: 8Kb Boot ROM with flash services */ +#define LPC17_AHBSRAM_BASE 0x20000000 /* -0x3fffffff: On-chip AHB SRAM (devices >32Kb) */ +# define LPC17_SRAM_BANK0 0x2007c000 /* -0x2007ffff: On-chip AHB SRAM Bank0 (devices >=32Kb) */ +# define LPC17_SRAM_BANK1 0x20080000 /* -0x2008ffff: On-chip AHB SRAM Bank1 (devices 64Kb) */ +#define LPC17_GPIO_BASE 0x2009c000 /* -0x2009ffff: GPIO */ +#define LPC17_APB_BASE 0x40000000 /* -0x5fffffff: APB Peripherals */ +# define LPC17_APB0_BASE 0x40000000 /* -0x4007ffff: APB0 Peripherals */ +# define LPC17_APB1_BASE 0x40080000 /* -0x400fffff: APB1 Peripherals */ +# define LPC17_AHB_BASE 0x50000000 /* -0x501fffff: DMA Controller, Ethernet, and USB */ +#define LPC17_CORTEXM3_BASE 0xe0000000 /* -0xe00fffff: (see armv7-m/nvic.h) */ +#define LPC17_SCS_BASE 0xe000e000 +#define LPC17_DEBUGMCU_BASE 0xe0042000 + +/* AHB SRAM Bank sizes **************************************************************/ + +#define LPC17_BANK0_SIZE (16*1024) /* Size of AHB SRAM Bank0 (if present) */ +#define LPC17_BANK1_SIZE (16*1024) /* Size of AHB SRAM Bank1 (if present) */ + +/* APB0 Peripherals *****************************************************************/ + +#define LPC17_WDT_BASE 0x40000000 /* -0x40003fff: Watchdog timer */ +#define LPC17_TMR0_BASE 0x40004000 /* -0x40007fff: Timer 0 */ +#define LPC17_TMR1_BASE 0x40008000 /* -0x4000bfff: Timer 1 */ +#define LPC17_UART0_BASE 0x4000c000 /* -0x4000ffff: UART 0 */ +#define LPC17_UART1_BASE 0x40010000 /* -0x40013fff: UART 1 */ + /* -0x40017fff: Reserved */ +#define LPC17_PWM1_BASE 0x40018000 /* -0x4001bfff: PWM 1 */ +#define LPC17_I2C0_BASE 0x4001c000 /* -0x4001ffff: I2C 0 */ +#define LPC17_SPI_BASE 0x40020000 /* -0x40023fff: SPI */ +#define LPC17_RTC_BASE 0x40024000 /* -0x40027fff: RTC + backup registers */ +#define LPC17_GPIOINT_BASE 0x40028000 /* -0x4002bfff: GPIO interrupts */ +#define LPC17_PINCONN_BASE 0x4002c000 /* -0x4002ffff: Pin connect block */ +#define LPC17_SSP1_BASE 0x40030000 /* -0x40033fff: SSP 1 */ +#define LPC17_ADC_BASE 0x40034000 /* -0x40037fff: ADC */ +#define LPC17_CANAFRAM_BASE 0x40038000 /* -0x4003bfff: CAN acceptance filter (AF) RAM */ +#define LPC17_CANAF_BASE 0x4003c000 /* -0x4003ffff: CAN acceptance filter (AF) registers */ +#define LPC17_CAN_BASE 0x40040000 /* -0x40043fff: CAN common registers */ +#define LPC17_CAN1_BASE 0x40044000 /* -0x40047fff: CAN controller l */ +#define LPC17_CAN2_BASE 0x40048000 /* -0x4004bfff: CAN controller 2 */ + /* -0x4005bfff: Reserved */ +#define LPC17_I2C1_BASE 0x4005c000 /* -0x4005ffff: I2C 1 */ + /* -0x4007ffff: Reserved */ + +/* APB1 Peripherals *****************************************************************/ + + /* -0x40087fff: Reserved */ +#define LPC17_SSP0_BASE 0x40088000 /* -0x4008bfff: SSP 0 */ +#define LPC17_DAC_BASE 0x4008c000 /* -0x4008ffff: DAC */ +#define LPC17_TMR2_BASE 0x40090000 /* -0x40093fff: Timer 2 */ +#define LPC17_TMR3_BASE 0x40094000 /* -0x40097fff: Timer 3 */ +#define LPC17_UART2_BASE 0x40098000 /* -0x4009bfff: UART 2 */ +#define LPC17_UART3_BASE 0x4009c000 /* -0x4009ffff: UART 3 */ +#define LPC17_I2C2_BASE 0x400a0000 /* -0x400a3fff: I2C 2 */ + /* -0x400a7fff: Reserved */ +#define LPC17_I2S_BASE 0x400a8000 /* -0x400abfff: I2S */ + /* -0x400affff: Reserved */ +#define LPC17_RIT_BASE 0x400b0000 /* -0x400b3fff: Repetitive interrupt timer */ + /* -0x400b7fff: Reserved */ +#define LPC17_MCPWM_BASE 0x400b8000 /* -0x400bbfff: Motor control PWM */ +#define LPC17_QEI_BASE 0x400bc000 /* -0x400bffff: Quadrature encoder interface */ + /* -0x400fbfff: Reserved */ +#define LPC17_SYSCON_BASE 0x400fc000 /* -0x400fffff: System control */ + +/* AHB Peripherals ******************************************************************/ + +#define LPC17_ETH_BASE 0x50000000 /* -0x50003fff: Ethernet controller */ +#define LPC17_GPDMA_BASE 0x50004000 /* -0x50007fff: GPDMA controller */ +#define LPC17_USB_BASE 0x5000c000 /* -0x5000cfff: USB controller */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_MEMORYMAP_H */ diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_ohciram.h b/nuttx/arch/arm/src/lpc17xx/lpc17_ohciram.h index 7601fefca..1e0564a87 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_ohciram.h +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_ohciram.h @@ -1,263 +1,263 @@ -/************************************************************************************
- * arch/arm/src/lpc17xx/lpc17_ohciram.h
- *
- * Copyright (C) 2010-2011 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_OHCIRAM_H
-#define __ARCH_ARM_SRC_LPC17XX_LPC17_OHCIRAM_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-#include "chip.h"
-#include "lpc17_memorymap.h"
-
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-/* Default, no-OHCI Case ************************************************************/
-/* Assume that all of AHB SRAM will be available for heap. If this is not true, then
- * LPC17_BANK1_HEAPSIZE will be undefined but redefined below.
- */
-
-#undef LPC17_BANK1_HEAPBASE
-#undef LPC17_BANK1_HEAPSIZE
-#ifdef LPC17_HAVE_BANK1
-# define LPC17_BANK1_HEAPBASE LPC17_SRAM_BANK1
-# define LPC17_BANK1_HEAPSIZE LPC17_BANK1_SIZE
-#endif
-
-/* Is networking enabled? Is the LPC17xx Ethernet device enabled? Does this chip have
- * and Ethernet controlloer? Yes... then we will replace the above default definitions.
- */
-
-#if defined(CONFIG_USBHOST) && defined(CONFIG_LPC17_USBHOST) && LPC17_NUSBHOST > 0
-
-/* OHCI RAM Configuration ***********************************************************/
-/* Is AHB SRAM available? */
-
-#ifndef LPC17_HAVE_BANK1
-# error "AHB SRAM Bank1 is not available for OHCI RAM"
-#endif
-
-/* OHCI/Heap Memory Allocation ******************************************************/
-/* Configured Size of the region at the end of AHB SRAM BANK1 set set aside for the
- * OHCI. This size must fit within AHB SRAM Bank 1 and also be a multiple of 256
- * bytes.
- */
-
-#ifndef CONFIG_USBHOST_OHCIRAM_SIZE
-# define CONFIG_USBHOST_OHCIRAM_SIZE LPC17_BANK1_SIZE
-#endif
-
-#if CONFIG_USBHOST_OHCIRAM_SIZE > LPC17_BANK1_SIZE
-# error "OHCI RAM size cannot exceed the size of AHB SRAM Bank 1"
-#endif
-
-#if (CONFIG_USBHOST_OHCIRAM_SIZE & 0xff) != 0
-# error "OHCI RAM size must be in multiples of 256 bytes"
-#endif
-
-/* Then position the OHCI RAM at the end of AHB SRAM Bank 1 */
-
-#define LPC17_OHCIRAM_END (LPC17_SRAM_BANK1 + LPC17_BANK1_SIZE)
-#define LPC17_OHCIRAM_BASE (LPC17_OHCIRAM_END - CONFIG_USBHOST_OHCIRAM_SIZE)
-#define LPC17_OHCIRAM_SIZE CONFIG_USBHOST_OHCIRAM_SIZE
-
-/* Determine is there is any meaningful space left at the beginning of AHB Bank 1
- * that could be added to the heap.
- */
-
-#undef LPC17_BANK1_HEAPBASE
-#undef LPC17_BANK1_HEAPSIZE
-#if LPC17_OHCIRAM_SIZE < (LPC17_BANK1_SIZE-128)
-# define LPC17_BANK1_HEAPBASE LPC17_SRAM_BANK1
-# define LPC17_BANK1_HEAPSIZE (LPC17_BANK1_SIZE - LPC17_OHCIRAM_SIZE)
-#endif
-
-/* Numbers and Sizes of Things ******************************************************/
-/* Fixed size of the OHCI control area */
-
-#define LPC17_HCCA_SIZE 256
-
-/* Fixed endpoint descriptor size. The actual size required by the hardware is only
- * 16 bytes, however, we set aside an additional 16 bytes for for internal use by
- * the OHCI host driver. 16-bytes is set aside because the EDs must still be
- * aligned to 16-byte boundaries.
- */
-
-#define LPC17_ED_SIZE 32
-
-/* Configurable number of user endpoint descriptors (EDs). This number excludes
- * the control endpoint that is always allocated.
- */
-
-#ifndef CONFIG_USBHOST_NEDS
-# define CONFIG_USBHOST_NEDS 2
-#endif
-
-/* Derived size of user endpoint descriptor (ED) memory. */
-
-#define LPC17_EDFREE_SIZE (CONFIG_USBHOST_NEDS * LPC17_ED_SIZE)
-
-/* Fixed transfer descriptor size. The actual size required by the hardware is only
- * 16 bytes, however, we set aside an additional 16 bytes for for internal use by
- * the OHCI host driver. 16-bytes is set aside because the TDs must still be
- * aligned to 16-byte boundaries.
- */
-
-#define LPC17_TD_SIZE 32
-
-/* Configurable number of user transfer descriptors (TDs). */
-
-#ifndef CONFIG_USBHOST_NTDS
-# define CONFIG_USBHOST_NTDS 3
-#endif
-
-#if CONFIG_USBHOST_NTDS < 2
-# error "Insufficent TDs"
-#endif
-
-/* Derived size of user trasnfer descriptor (TD) memory. */
-
-#define LPC17_TDFREE_SIZE (CONFIG_USBHOST_NTDS * LPC17_TD_SIZE)
-
-/* Configurable number of request/descriptor buffers (TDBUFFER) */
-
-#ifndef CONFIG_USBHOST_TDBUFFERS
-# define CONFIG_USBHOST_TDBUFFERS 2
-#endif
-
-#if CONFIG_USBHOST_TDBUFFERS < 2
-# error "At least two TD buffers are required"
-#endif
-
-/* Configurable size of a TD buffer */
-
-#if CONFIG_USBHOST_TDBUFFERS > 0 && !defined(CONFIG_USBHOST_TDBUFSIZE)
-# define CONFIG_USBHOST_TDBUFSIZE 128
-#endif
-
-#if (CONFIG_USBHOST_TDBUFSIZE & 3) != 0
-# error "TD buffer size must be an even number of 32-bit words"
-#endif
-
-#define LPC17_TBFREE_SIZE (CONFIG_USBHOST_TDBUFFERS * CONFIG_USBHOST_TDBUFSIZE)
-
-/* Configurable size of an IO buffer. The number of IO buffers will be determined
- * by what is left at the end of the BANK1 memory setup aside of OHCI RAM.
- */
-
-#ifndef CONFIG_USBHOST_IOBUFSIZE
-# define CONFIG_USBHOST_IOBUFSIZE 512
-#endif
-
-#if (CONFIG_USBHOST_IOBUFSIZE & 3) != 0
-# error "IO buffer size must be an even number of 32-bit words"
-#endif
-
-/* OHCI Memory Layout ***************************************************************/
-/* Example:
- * Hardware:
- * LPC17_SRAM_BANK1 0x20008000
- * LPC17_BANK1_SIZE 16384
- *
- * Configuration:
- * CONFIG_USBHOST_OHCIRAM_SIZE 1536
- * CONFIG_USBHOST_NEDS 2
- * CONFIG_USBHOST_NTDS 3
- * CONFIG_USBHOST_TDBUFFERS 3
- * CONFIG_USBHOST_TDBUFSIZE 128
- * CONFIG_USBHOST_IOBUFSIZE 512
- *
- * Sizes of things
- * LPC17_EDFREE_SIZE 64 0x00000040
- * LPC17_TDFREE_SIZE 96 0x00000060
- * LPC17_TBFREE_SIZE 384 0x00000100
- * LPC17_IOFREE_SIZE 512 0x00000200
- *
- * Memory Layout
- * LPC17_OHCIRAM_END (0x20008000 + 16384) = 0x20084000
- * LPC17_OHCIRAM_BASE (0x2000c000 - 1536) = 0x2000ba00
- * LPC17_OHCIRAM_SIZE 1280
- * LPC17_BANK1_HEAPBASE 0x20008000
- * LPC17_BANK1_HEAPSIZE (16384 - 1280) = 15104
- *
- * LPC17_HCCA_BASE 0x20083a00 -- Communications area
- * LPC17_TDTAIL_ADDR 0x20083b00 -- Common. pre-allocated tail TD
- * LPC17_EDCTRL_ADDR 0x20083b20 -- Pre-allocated ED for EP0
- * LPC17_EDFREE_BASE 0x20083b40 -- Free EDs
- * LPC17_TDFREE_BASE 0x20083b80 -- Free TDs
- * LPC17_TBFREE_BASE 0x20083be0 -- Free request/descriptor buffers
- * LPC17_IOFREE_BASE 0x20083d60 -- Free large I/O buffers
- * LPC17_IOBUFFERS (0x20084000 - 0x20083d60) / 512 = 672/512 = 1
- *
- * Wasted memory: 672-512 = 160 bytes
- */
-
-#define LPC17_HCCA_BASE (LPC17_OHCIRAM_BASE)
-#define LPC17_TDTAIL_ADDR (LPC17_HCCA_BASE + LPC17_HCCA_SIZE)
-#define LPC17_EDCTRL_ADDR (LPC17_TDTAIL_ADDR + LPC17_TD_SIZE)
-#define LPC17_EDFREE_BASE (LPC17_EDCTRL_ADDR + LPC17_ED_SIZE)
-#define LPC17_TDFREE_BASE (LPC17_EDFREE_BASE + LPC17_EDFREE_SIZE)
-#define LPC17_TBFREE_BASE (LPC17_TDFREE_BASE + LPC17_TDFREE_SIZE)
-#define LPC17_IOFREE_BASE (LPC17_TBFREE_BASE + LPC17_TBFREE_SIZE)
-
-#if LPC17_IOFREE_BASE > LPC17_OHCIRAM_END
-# error "Insufficient OHCI RAM allocated"
-#endif
-
-/* Finally, use the remainder of the allocated OHCI for IO buffers */
-
-#if CONFIG_USBHOST_IOBUFSIZE > 0
-# define LPC17_IOBUFFERS ((LPC17_OHCIRAM_END - LPC17_IOFREE_BASE) / CONFIG_USBHOST_IOBUFSIZE)
-#else
-# define LPC17_IOBUFFERS 0
-#endif
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-/************************************************************************************
- * Public Functions
- ************************************************************************************/
-
-#endif /* CONFIG_USBHOST && CONFIG_LPC17_USBHOST && LPC17_NUSBHOST > 0*/
-#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_OHCIRAM_H */
+/************************************************************************************ + * arch/arm/src/lpc17xx/lpc17_ohciram.h + * + * Copyright (C) 2010-2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_OHCIRAM_H +#define __ARCH_ARM_SRC_LPC17XX_LPC17_OHCIRAM_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> +#include "chip.h" +#include "lpc17_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ +/* Default, no-OHCI Case ************************************************************/ +/* Assume that all of AHB SRAM will be available for heap. If this is not true, then + * LPC17_BANK1_HEAPSIZE will be undefined but redefined below. + */ + +#undef LPC17_BANK1_HEAPBASE +#undef LPC17_BANK1_HEAPSIZE +#ifdef LPC17_HAVE_BANK1 +# define LPC17_BANK1_HEAPBASE LPC17_SRAM_BANK1 +# define LPC17_BANK1_HEAPSIZE LPC17_BANK1_SIZE +#endif + +/* Is networking enabled? Is the LPC17xx Ethernet device enabled? Does this chip have + * and Ethernet controlloer? Yes... then we will replace the above default definitions. + */ + +#if defined(CONFIG_USBHOST) && defined(CONFIG_LPC17_USBHOST) && LPC17_NUSBHOST > 0 + +/* OHCI RAM Configuration ***********************************************************/ +/* Is AHB SRAM available? */ + +#ifndef LPC17_HAVE_BANK1 +# error "AHB SRAM Bank1 is not available for OHCI RAM" +#endif + +/* OHCI/Heap Memory Allocation ******************************************************/ +/* Configured Size of the region at the end of AHB SRAM BANK1 set set aside for the + * OHCI. This size must fit within AHB SRAM Bank 1 and also be a multiple of 256 + * bytes. + */ + +#ifndef CONFIG_USBHOST_OHCIRAM_SIZE +# define CONFIG_USBHOST_OHCIRAM_SIZE LPC17_BANK1_SIZE +#endif + +#if CONFIG_USBHOST_OHCIRAM_SIZE > LPC17_BANK1_SIZE +# error "OHCI RAM size cannot exceed the size of AHB SRAM Bank 1" +#endif + +#if (CONFIG_USBHOST_OHCIRAM_SIZE & 0xff) != 0 +# error "OHCI RAM size must be in multiples of 256 bytes" +#endif + +/* Then position the OHCI RAM at the end of AHB SRAM Bank 1 */ + +#define LPC17_OHCIRAM_END (LPC17_SRAM_BANK1 + LPC17_BANK1_SIZE) +#define LPC17_OHCIRAM_BASE (LPC17_OHCIRAM_END - CONFIG_USBHOST_OHCIRAM_SIZE) +#define LPC17_OHCIRAM_SIZE CONFIG_USBHOST_OHCIRAM_SIZE + +/* Determine is there is any meaningful space left at the beginning of AHB Bank 1 + * that could be added to the heap. + */ + +#undef LPC17_BANK1_HEAPBASE +#undef LPC17_BANK1_HEAPSIZE +#if LPC17_OHCIRAM_SIZE < (LPC17_BANK1_SIZE-128) +# define LPC17_BANK1_HEAPBASE LPC17_SRAM_BANK1 +# define LPC17_BANK1_HEAPSIZE (LPC17_BANK1_SIZE - LPC17_OHCIRAM_SIZE) +#endif + +/* Numbers and Sizes of Things ******************************************************/ +/* Fixed size of the OHCI control area */ + +#define LPC17_HCCA_SIZE 256 + +/* Fixed endpoint descriptor size. The actual size required by the hardware is only + * 16 bytes, however, we set aside an additional 16 bytes for for internal use by + * the OHCI host driver. 16-bytes is set aside because the EDs must still be + * aligned to 16-byte boundaries. + */ + +#define LPC17_ED_SIZE 32 + +/* Configurable number of user endpoint descriptors (EDs). This number excludes + * the control endpoint that is always allocated. + */ + +#ifndef CONFIG_USBHOST_NEDS +# define CONFIG_USBHOST_NEDS 2 +#endif + +/* Derived size of user endpoint descriptor (ED) memory. */ + +#define LPC17_EDFREE_SIZE (CONFIG_USBHOST_NEDS * LPC17_ED_SIZE) + +/* Fixed transfer descriptor size. The actual size required by the hardware is only + * 16 bytes, however, we set aside an additional 16 bytes for for internal use by + * the OHCI host driver. 16-bytes is set aside because the TDs must still be + * aligned to 16-byte boundaries. + */ + +#define LPC17_TD_SIZE 32 + +/* Configurable number of user transfer descriptors (TDs). */ + +#ifndef CONFIG_USBHOST_NTDS +# define CONFIG_USBHOST_NTDS 3 +#endif + +#if CONFIG_USBHOST_NTDS < 2 +# error "Insufficent TDs" +#endif + +/* Derived size of user trasnfer descriptor (TD) memory. */ + +#define LPC17_TDFREE_SIZE (CONFIG_USBHOST_NTDS * LPC17_TD_SIZE) + +/* Configurable number of request/descriptor buffers (TDBUFFER) */ + +#ifndef CONFIG_USBHOST_TDBUFFERS +# define CONFIG_USBHOST_TDBUFFERS 2 +#endif + +#if CONFIG_USBHOST_TDBUFFERS < 2 +# error "At least two TD buffers are required" +#endif + +/* Configurable size of a TD buffer */ + +#if CONFIG_USBHOST_TDBUFFERS > 0 && !defined(CONFIG_USBHOST_TDBUFSIZE) +# define CONFIG_USBHOST_TDBUFSIZE 128 +#endif + +#if (CONFIG_USBHOST_TDBUFSIZE & 3) != 0 +# error "TD buffer size must be an even number of 32-bit words" +#endif + +#define LPC17_TBFREE_SIZE (CONFIG_USBHOST_TDBUFFERS * CONFIG_USBHOST_TDBUFSIZE) + +/* Configurable size of an IO buffer. The number of IO buffers will be determined + * by what is left at the end of the BANK1 memory setup aside of OHCI RAM. + */ + +#ifndef CONFIG_USBHOST_IOBUFSIZE +# define CONFIG_USBHOST_IOBUFSIZE 512 +#endif + +#if (CONFIG_USBHOST_IOBUFSIZE & 3) != 0 +# error "IO buffer size must be an even number of 32-bit words" +#endif + +/* OHCI Memory Layout ***************************************************************/ +/* Example: + * Hardware: + * LPC17_SRAM_BANK1 0x20008000 + * LPC17_BANK1_SIZE 16384 + * + * Configuration: + * CONFIG_USBHOST_OHCIRAM_SIZE 1536 + * CONFIG_USBHOST_NEDS 2 + * CONFIG_USBHOST_NTDS 3 + * CONFIG_USBHOST_TDBUFFERS 3 + * CONFIG_USBHOST_TDBUFSIZE 128 + * CONFIG_USBHOST_IOBUFSIZE 512 + * + * Sizes of things + * LPC17_EDFREE_SIZE 64 0x00000040 + * LPC17_TDFREE_SIZE 96 0x00000060 + * LPC17_TBFREE_SIZE 384 0x00000100 + * LPC17_IOFREE_SIZE 512 0x00000200 + * + * Memory Layout + * LPC17_OHCIRAM_END (0x20008000 + 16384) = 0x20084000 + * LPC17_OHCIRAM_BASE (0x2000c000 - 1536) = 0x2000ba00 + * LPC17_OHCIRAM_SIZE 1280 + * LPC17_BANK1_HEAPBASE 0x20008000 + * LPC17_BANK1_HEAPSIZE (16384 - 1280) = 15104 + * + * LPC17_HCCA_BASE 0x20083a00 -- Communications area + * LPC17_TDTAIL_ADDR 0x20083b00 -- Common. pre-allocated tail TD + * LPC17_EDCTRL_ADDR 0x20083b20 -- Pre-allocated ED for EP0 + * LPC17_EDFREE_BASE 0x20083b40 -- Free EDs + * LPC17_TDFREE_BASE 0x20083b80 -- Free TDs + * LPC17_TBFREE_BASE 0x20083be0 -- Free request/descriptor buffers + * LPC17_IOFREE_BASE 0x20083d60 -- Free large I/O buffers + * LPC17_IOBUFFERS (0x20084000 - 0x20083d60) / 512 = 672/512 = 1 + * + * Wasted memory: 672-512 = 160 bytes + */ + +#define LPC17_HCCA_BASE (LPC17_OHCIRAM_BASE) +#define LPC17_TDTAIL_ADDR (LPC17_HCCA_BASE + LPC17_HCCA_SIZE) +#define LPC17_EDCTRL_ADDR (LPC17_TDTAIL_ADDR + LPC17_TD_SIZE) +#define LPC17_EDFREE_BASE (LPC17_EDCTRL_ADDR + LPC17_ED_SIZE) +#define LPC17_TDFREE_BASE (LPC17_EDFREE_BASE + LPC17_EDFREE_SIZE) +#define LPC17_TBFREE_BASE (LPC17_TDFREE_BASE + LPC17_TDFREE_SIZE) +#define LPC17_IOFREE_BASE (LPC17_TBFREE_BASE + LPC17_TBFREE_SIZE) + +#if LPC17_IOFREE_BASE > LPC17_OHCIRAM_END +# error "Insufficient OHCI RAM allocated" +#endif + +/* Finally, use the remainder of the allocated OHCI for IO buffers */ + +#if CONFIG_USBHOST_IOBUFSIZE > 0 +# define LPC17_IOBUFFERS ((LPC17_OHCIRAM_END - LPC17_IOFREE_BASE) / CONFIG_USBHOST_IOBUFSIZE) +#else +# define LPC17_IOBUFFERS 0 +#endif + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* CONFIG_USBHOST && CONFIG_LPC17_USBHOST && LPC17_NUSBHOST > 0*/ +#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_OHCIRAM_H */ diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_pinconn.h b/nuttx/arch/arm/src/lpc17xx/lpc17_pinconn.h index e41bdb8de..c0e0ec916 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_pinconn.h +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_pinconn.h @@ -1,635 +1,635 @@ -/************************************************************************************
- * arch/arm/src/lpc17xx/lpc17_pinconn.h
- *
- * Copyright (C) 2010 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_PINCONN_H
-#define __ARCH_ARM_SRC_LPC17XX_LPC17_PINCONN_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-
-#include "chip.h"
-#include "lpc17_memorymap.h"
-
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-
-/* Register offsets *****************************************************************/
-
-#define LPC17_PINCONN_PINSEL0_OFFSET 0x0000 /* Pin function select register 0 */
-#define LPC17_PINCONN_PINSEL1_OFFSET 0x0004 /* Pin function select register 1 */
-#define LPC17_PINCONN_PINSEL2_OFFSET 0x0008 /* Pin function select register 2 */
-#define LPC17_PINCONN_PINSEL3_OFFSET 0x000c /* Pin function select register 3 */
-#define LPC17_PINCONN_PINSEL4_OFFSET 0x0010 /* Pin function select register 4 */
-#define LPC17_PINCONN_PINSEL7_OFFSET 0x001c /* Pin function select register 7 */
-#define LPC17_PINCONN_PINSEL8_OFFSET 0x0020 /* Pin function select register 8 */
-#define LPC17_PINCONN_PINSEL9_OFFSET 0x0024 /* Pin function select register 9 */
-#define LPC17_PINCONN_PINSEL10_OFFSET 0x0028 /* Pin function select register 10 */
-#define LPC17_PINCONN_PINMODE0_OFFSET 0x0040 /* Pin mode select register 0 */
-#define LPC17_PINCONN_PINMODE1_OFFSET 0x0044 /* Pin mode select register 1 */
-#define LPC17_PINCONN_PINMODE2_OFFSET 0x0048 /* Pin mode select register 2 */
-#define LPC17_PINCONN_PINMODE3_OFFSET 0x004c /* Pin mode select register 3 */
-#define LPC17_PINCONN_PINMODE4_OFFSET 0x0050 /* Pin mode select register 4 */
-#define LPC17_PINCONN_PINMODE5_OFFSET 0x0054 /* Pin mode select register 5 */
-#define LPC17_PINCONN_PINMODE6_OFFSET 0x0058 /* Pin mode select register 6 */
-#define LPC17_PINCONN_PINMODE7_OFFSET 0x005c /* Pin mode select register 7 */
-#define LPC17_PINCONN_PINMODE9_OFFSET 0x0064 /* Pin mode select register 9 */
-#define LPC17_PINCONN_ODMODE0_OFFSET 0x0068 /* Open drain mode control register 0 */
-#define LPC17_PINCONN_ODMODE1_OFFSET 0x006c /* Open drain mode control register 1 */
-#define LPC17_PINCONN_ODMODE2_OFFSET 0x0070 /* Open drain mode control register 2 */
-#define LPC17_PINCONN_ODMODE3_OFFSET 0x0074 /* Open drain mode control register 3 */
-#define LPC17_PINCONN_ODMODE4_OFFSET 0x0078 /* Open drain mode control register 4 */
-#define LPC17_PINCONN_I2CPADCFG_OFFSET 0x007c /* I2C Pin Configuration register */
-
-/* Register addresses ***************************************************************/
-
-#define LPC17_PINCONN_PINSEL0 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINSEL0_OFFSET)
-#define LPC17_PINCONN_PINSEL1 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINSEL1_OFFSET)
-#define LPC17_PINCONN_PINSEL2 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINSEL2_OFFSET)
-#define LPC17_PINCONN_PINSEL3 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINSEL3_OFFSET)
-#define LPC17_PINCONN_PINSEL4 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINSEL4_OFFSET)
-#define LPC17_PINCONN_PINSEL7 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINSEL7_OFFSET)
-#define LPC17_PINCONN_PINSEL8 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINSEL8_OFFSET)
-#define LPC17_PINCONN_PINSEL9 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINSEL9_OFFSET)
-#define LPC17_PINCONN_PINSEL10 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINSEL10_OFFSET)
-#define LPC17_PINCONN_PINMODE0 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINMODE0_OFFSET)
-#define LPC17_PINCONN_PINMODE1 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINMODE1_OFFSET)
-#define LPC17_PINCONN_PINMODE2 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINMODE2_OFFSET)
-#define LPC17_PINCONN_PINMODE3 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINMODE3_OFFSET)
-#define LPC17_PINCONN_PINMODE4 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINMODE4_OFFSET)
-#define LPC17_PINCONN_PINMODE5 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINMODE5_OFFSET)
-#define LPC17_PINCONN_PINMODE6 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINMODE6_OFFSET)
-#define LPC17_PINCONN_PINMODE7 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINMODE7_OFFSET)
-#define LPC17_PINCONN_PINMODE9 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINMODE9_OFFSET)
-#define LPC17_PINCONN_ODMODE0 (LPC17_PINCONN_BASE+LPC17_PINCONN_ODMODE0_OFFSET)
-#define LPC17_PINCONN_ODMODE1 (LPC17_PINCONN_BASE+LPC17_PINCONN_ODMODE1_OFFSET)
-#define LPC17_PINCONN_ODMODE2 (LPC17_PINCONN_BASE+LPC17_PINCONN_ODMODE2_OFFSET)
-#define LPC17_PINCONN_ODMODE3 (LPC17_PINCONN_BASE+LPC17_PINCONN_ODMODE3_OFFSET)
-#define LPC17_PINCONN_ODMODE4 (LPC17_PINCONN_BASE+LPC17_PINCONN_ODMODE4_OFFSET)
-#define LPC17_PINCONN_I2CPADCFG (LPC17_PINCONN_BASE+LPC17_PINCONN_I2CPADCFG_OFFSET)
-
-/* Register bit definitions *********************************************************/
-/* Pin Function Select register 0 (PINSEL0: 0x4002c000) */
-
-#define PINCONN_PINSEL_GPIO (0)
-#define PINCONN_PINSEL_ALT1 (1)
-#define PINCONN_PINSEL_ALT2 (2)
-#define PINCONN_PINSEL_ALT3 (3)
-#define PINCONN_PINSEL_MASK (3)
-
-#define PINCONN_PINSELL_SHIFT(n) ((n) << 1) /* n=0,1,..,15 */
-#define PINCONN_PINSELL_MASK(n) (3 << PINCONN_PINSELL_SHIFT(n))
-#define PINCONN_PINSELH_SHIFT(n) (((n)-16) << 1) /* n=16,17,..31 */
-#define PINCONN_PINSELH_MASK(n) (3 << PINCONN_PINSELH_SHIFT(n))
-
-#define PINCONN_PINSEL0_P0_SHIFT(n) PINCONN_PINSELL_SHIFT(n) /* n=0,1,..,15 */
-#define PINCONN_PINSEL0_P0_MASK(n) PINCONN_PINSELL_MASK(n) /* n=0,1,..,15 */
-
-#define PINCONN_PINSEL0_P0p0_SHIFT (0) /* Bits 0-1: P0.0 00=GPIO 01=RD1 10=TXD3 11=SDA1 */
-#define PINCONN_PINSEL0_P0p0_MASK (3 << PINCONN_PINSEL0_P0p0_SHIFT)
-#define PINCONN_PINSEL0_P0p1_SHIFT (2) /* Bits 2-3: P0.1 00=GPIO 01=TD1 10=RXD3 11=SCL1 */
-#define PINCONN_PINSEL0_P0p1_MASK (3 << PINCONN_PINSEL0_P0p1_SHIFT)
-#define PINCONN_PINSEL0_P0p2_SHIFT (4) /* Bits 4-5: P0.2 00=GPIO 01=TXD0 10=AD0.7 11=Reserved */
-#define PINCONN_PINSEL0_P0p2_MASK (3 << PINCONN_PINSEL0_P0p2_SHIFT)
-#define PINCONN_PINSEL0_P0p3_SHIFT (6) /* Bits 6-7: P0.3 00=GPIO 01=RXD0 10=AD0.6 11=Reserved */
-#define PINCONN_PINSEL0_P0p3_MASK (3 << PINCONN_PINSEL0_P0p3_SHIFT)
-#define PINCONN_PINSEL0_P0p4_SHIFT (8) /* Bits 8-9: P0.4 00=GPIO 01=I2SRX_CLK 10=RD2 11=CAP2.0 */
-#define PINCONN_PINSEL0_P0p4_MASK (3 << PINCONN_PINSEL0_P0p4_SHIFT)
-#define PINCONN_PINSEL0_P0p5_SHIFT (10) /* Bits 10-11: P0.5 00=GPIO 01=I2SRX_WS 10=TD2 11=CAP2.1 */
-#define PINCONN_PINSEL0_P0p5_MASK (3 << PINCONN_PINSEL0_P0p5_SHIFT)
-#define PINCONN_PINSEL0_P0p6_SHIFT (12) /* Bits 12-13: P0.6 00=GPIO 01=I2SRX_SDA 10=SSEL1 11=MAT2.0 */
-#define PINCONN_PINSEL0_P0p6_MASK (3 << PINCONN_PINSEL0_P0p6_SHIFT)
-#define PINCONN_PINSEL0_P0p7_SHIFT (14) /* Bits 14-15: P0.7 00=GPIO 01=I2STX_CLK 10=SCK1 11=MAT2.1 */
-#define PINCONN_PINSEL0_P0p7_MASK (3 << PINCONN_PINSEL0_P0p7_SHIFT)
-#define PINCONN_PINSEL0_P0p8_SHIFT (16) /* Bits 16-17: P0.8 00=GPIO 01=I2STX_WS 10=MISO1 11=MAT2.2 */
-#define PINCONN_PINSEL0_P0p8_MASK (3 << PINCONN_PINSEL0_P0p8_SHIFT)
-#define PINCONN_PINSEL0_P0p9_SHIFT (18) /* Bits 18-19: P0.9 00=GPIO 01=I2STX_SDA 10=MOSI1 11=MAT2.3 */
-#define PINCONN_PINSEL0_P0p9_MASK (3 << PINCONN_PINSEL0_P0p9_SHIFT)
-#define PINCONN_PINSEL0_P0p10_SHIFT (20) /* Bits 20-21: P0.10 00=GPIO 01=TXD2 10=SDA2 11=MAT3.0 */
-#define PINCONN_PINSEL0_P0p10_MASK (3 << PINCONN_PINSEL0_P0p10_SHIFT)
-#define PINCONN_PINSEL0_P0p11_SHIFT (22) /* Bits 22-23: P0.11 00=GPIO 01=RXD2 10=SCL2 11=MAT3.1 */
-#define PINCONN_PINSEL0_P0p11_MASK (3 << PINCONN_PINSEL0_P0p11_SHIFT)
- /* Bits 24-29: Reserved */
-#define PINCONN_PINSEL0_P0p15_SHIFT (30) /* Bits 30-31: P0.15 00=GPIO 01=TXD1 10=SCK0 11=SCK */
-#define PINCONN_PINSEL0_P0p15_MASK (3 << PINCONN_PINSEL0_P0p15_SHIFT)
-
-/* Pin Function Select Register 1 (PINSEL1: 0x4002c004) */
-
-#define PINCONN_PINSEL1_P0_SHIFT(n) PINCONN_PINSELH_SHIFT(n) /* n=16,17,..31 */
-#define PINCONN_PINSEL1_P0_MASK(n) PINCONN_PINSELH_MASK(n) /* n=16,17,..31 */
-
-#define PINCONN_PINSEL1_P0p16_SHIFT (0) /* Bits 0-1: P0.16 00=GPIO 01=RXD1 10=SSEL0 11=SSEL */
-#define PINCONN_PINSEL1_P0p16_MASK (3 << PINCONN_PINSEL1_P0p16_SHIFT)
-#define PINCONN_PINSEL1_P0p17_SHIFT (2) /* Bits 2-3: P0.17 00=GPIO 01=CTS1 10=MISO0 11=MISO */
-#define PINCONN_PINSEL1_P0p17_MASK (3 << PINCONN_PINSEL1_P0p17_SHIFT)
-#define PINCONN_PINSEL1_P0p18_SHIFT (4) /* Bits 4-5: P0.18 00=GPIO 01=DCD1 10=MOSI0 11=MOSI */
-#define PINCONN_PINSEL1_P0p18_MASK (3 << PINCONN_PINSEL1_P0p18_SHIFT)
-#define PINCONN_PINSEL1_P0p19_SHIFT (6) /* Bits 6-7: P0.19 00=GPIO 01=DSR1 10=Reserved 11=SDA1 */
-#define PINCONN_PINSEL1_P0p19_MASK (3 << PINCONN_PINSEL1_P0p19_SHIFT)
-#define PINCONN_PINSEL1_P0p20_SHIFT (8) /* Bits 8-9: P0.20 00=GPIO 01=DTR1 10=Reserved 11=SCL1 */
-#define PINCONN_PINSEL1_P0p20_MASK (3 << PINCONN_PINSEL1_P0p20_SHIFT)
-#define PINCONN_PINSEL1_P0p21_SHIFT (10) /* Bits 10-11: P0.21 00=GPIO 01=RI1 10=Reserved 11=RD1 */
-#define PINCONN_PINSEL1_P0p21_MASK (3 << PINCONN_PINSEL1_P0p21_SHIFT)
-#define PINCONN_PINSEL1_P0p22_SHIFT (12) /* Bits 12-13: P0.22 00=GPIO 01=RTS1 10=Reserved 11=TD1 */
-#define PINCONN_PINSEL1_P0p22_MASK (3 << PINCONN_PINSEL1_P0p22_SHIFT)
-#define PINCONN_PINSEL1_P0p23_SHIFT (14) /* Bits 14-15: P0.23 00=GPIO 01=AD0.0 10=I2SRX_CLK 11=CAP3.0 */
-#define PINCONN_PINSEL1_P0p23_MASK (3 << PINCONN_PINSEL1_P0p23_SHIFT)
-#define PINCONN_PINSEL1_P0p24_SHIFT (16) /* Bits 16-17: P0.24 00=GPIO 01=AD0.1 10=I2SRX_WS 11=CAP3.1 */
-#define PINCONN_PINSEL1_P0p24_MASK (3 << PINCONN_PINSEL1_P0p24_SHIFT)
-#define PINCONN_PINSEL1_P0p25_SHIFT (18) /* Bits 18-19: P0.25 00=GPIO 01=AD0.2 10=I2SRX_SDA 11=TXD3 */
-#define PINCONN_PINSEL1_P0p25_MASK (3 << PINCONN_PINSEL1_P0p25_SHIFT)
-#define PINCONN_PINSEL1_P0p26_SHIFT (20) /* Bits 20-21: P0.26 00=GPIO 01=AD0.3 10=AOUT 11=RXD3 */
-#define PINCONN_PINSEL1_P0p26_MASK (3 << PINCONN_PINSEL1_P0p26_SHIFT)
-#define PINCONN_PINSEL1_P0p27_SHIFT (22) /* Bits 22-23: P0.27 00=GPIO 01=SDA0 10=USB_SDA 11=Reserved */
-#define PINCONN_PINSEL1_P0p27_MASK (3 << PINCONN_PINSEL1_P0p27_SHIFT)
-#define PINCONN_PINSEL1_P0p28_SHIFT (24) /* Bits 24-25: P0.28 00=GPIO 01=SCL0 10=USB_SCL 11=Reserved */
-#define PINCONN_PINSEL1_P0p28_MASK (3 << PINCONN_PINSEL1_P0p28_SHIFT)
-#define PINCONN_PINSEL1_P0p29_SHIFT (26) /* Bits 26-27: P0.29 00=GPIO 01=USB_D+ 10=Reserved 11=Reserved */
-#define PINCONN_PINSEL1_P0p29_MASK (3 << PINCONN_PINSEL1_P0p29_SHIFT)
-#define PINCONN_PINSEL1_P0p30_SHIFT (28) /* Bits 28-29: P0.30 00=GPIO 01=USB_D- 10=Reserved 11=Reserved */
-#define PINCONN_PINSEL1_P0p30_MASK (3 << PINCONN_PINSEL1_P0p30_SHIFT)
- /* Bits 30-31: Reserved */
-/* Pin Function Select register 2 (PINSEL2: 0x4002c008) */
-
-#define PINCONN_PINSEL2_P1_SHIFT(n) PINCONN_PINSELL_SHIFT(n) /* n=0,1,..,15 */
-#define PINCONN_PINSEL2_P1_MASK(n) PINCONN_PINSELL_MASK(n) /* n=0,1,..,15 */
-
-#define PINCONN_PINSEL2_P1p0_SHIFT (0) /* Bits 0-1: P1.0 00=GPIO 01=ENET_TXD0 10=Reserved 11=Reserved */
-#define PINCONN_PINSEL2_P1p0_MASK (3 << PINCONN_PINSEL2_P1p0_SHIFT)
-#define PINCONN_PINSEL2_P1p1_SHIFT (2) /* Bits 2-3: P1.1 00=GPIO 01=ENET_TXD1 10=Reserved 11=Reserved */
-#define PINCONN_PINSEL2_P1p1_MASK (3 << PINCONN_PINSEL2_P1p1_SHIFT)
- /* Bits 4-7: Reserved */
-#define PINCONN_PINSEL2_P1p4_SHIFT (8) /* Bits 8-9: P1.4 00=GPIO 01=ENET_TX_EN 10=Reserved 11=Reserved */
-#define PINCONN_PINSEL2_P1p4_MASK (3 << PINCONN_PINSEL2_P1p4_SHIFT)
- /* Bits 10-15: Reserved */
-#define PINCONN_PINSEL2_P1p8_SHIFT (16) /* Bits 16-17: P1.8 00=GPIO 01=ENET_CRS 10=Reserved 11=Reserved */
-#define PINCONN_PINSEL2_P1p8_MASK (3 << PINCONN_PINSEL2_P1p8_SHIFT)
-#define PINCONN_PINSEL2_P1p9_SHIFT (18) /* Bits 18-19: P1.9 00=GPIO 01=ENET_RXD0 10=Reserved 11=Reserved */
-#define PINCONN_PINSEL2_P1p9_MASK (3 << PINCONN_PINSEL2_P1p9_SHIFT)
-#define PINCONN_PINSEL2_P1p10_SHIFT (20) /* Bits 20-21: P1.10 00=GPIO 01=ENET_RXD1 10=Reserved 11=Reserved */
-#define PINCONN_PINSEL2_P1p10_MASK (3 << PINCONN_PINSEL2_P1p10_SHIFT)
- /* Bits 22-27: Reserved */
-#define PINCONN_PINSEL2_P1p14_SHIFT (28) /* Bits 28-29: P1.14 00=GPIO 01=ENET_RX_ER 10=Reserved 11=Reserved */
-#define PINCONN_PINSEL2_P1p14_MASK (3 << PINCONN_PINSEL2_P1p14_SHIFT)
-#define PINCONN_PINSEL2_P1p15_SHIFT (30) /* Bits 30-31: P1.15 00=GPIO 01=ENET_REF_CLK 10=Reserved 11=Reserved */
-#define PINCONN_PINSEL2_P1p15_MASK (3 << PINCONN_PINSEL2_P1p15_SHIFT)
-
-/* Pin Function Select Register 3 (PINSEL3: 0x4002c00c) */
-
-#define PINCONN_PINSEL3_P1_SHIFT(n) PINCONN_PINSELH_SHIFT(n) /* n=16,17,..31 */
-#define PINCONN_PINSEL3_P1_MASK(n) PINCONN_PINSELH_MASK(n) /* n=16,17,..31 */
-
-#define PINCONN_PINSEL3_P1p16_SHIFT (0) /* Bits 0-1: P1.16 00=GPIO 01=ENET_MDC 10=Reserved 11=Reserved */
-#define PINCONN_PINSEL3_P1p16_MASK (3 << PINCONN_PINSEL3_P1p16_SHIFT)
-#define PINCONN_PINSEL3_P1p17_SHIFT (2) /* Bits 2-3: P1.17 00=GPIO 01=ENET_MDIO 10=Reserved 11=Reserved */
-#define PINCONN_PINSEL3_P1p17_MASK (3 << PINCONN_PINSEL3_P1p17_SHIFT)
-#define PINCONN_PINSEL3_P1p18_SHIFT (4) /* Bits 4-5: P1.18 00=GPIO 01=USB_UP_LED 10=PWM1.1 11=CAP1.0 */
-#define PINCONN_PINSEL3_P1p18_MASK (3 << PINCONN_PINSEL3_P1p18_SHIFT)
-#define PINCONN_PINSEL3_P1p19_SHIFT (6) /* Bits 6-7: P1.19 00=GPIO 01=MCOA0 10=USB_PPWR 11=CAP1.1 */
-#define PINCONN_PINSEL3_P1p19_MASK (3 << PINCONN_PINSEL3_P1p19_SHIFT)
-#define PINCONN_PINSEL3_P1p20_SHIFT (8) /* Bits 8-9: P1.20 00=GPIO 01=MCI0 10=PWM1.2 11=SCK0 */
-#define PINCONN_PINSEL3_P1p20_MASK (3 << PINCONN_PINSEL3_P1p20_SHIFT)
-#define PINCONN_PINSEL3_P1p21_SHIFT (10) /* Bits 10-11: P1.21 00=GPIO 01=MCABORT 10=PWM1.3 11=SSEL0 */
-#define PINCONN_PINSEL3_P1p21_MASK (3 << PINCONN_PINSEL3_P1p21_SHIFT)
-#define PINCONN_PINSEL3_P1p22_SHIFT (12) /* Bits 12-13: P1.22 00=GPIO 01=MCOB0 10=USB_PWRD 11=MAT1.0 */
-#define PINCONN_PINSEL3_P1p22_MASK (3 << PINCONN_PINSEL3_P1p22_SHIFT)
-#define PINCONN_PINSEL3_P1p23_SHIFT (14) /* Bits 14-15: P1.23 00=GPIO 01=MCI1 10=PWM1.4 11=MISO0 */
-#define PINCONN_PINSEL3_P1p23_MASK (3 << PINCONN_PINSEL3_P1p23_SHIFT)
-#define PINCONN_PINSEL3_P1p24_SHIFT (16) /* Bits 16-17: P1.24 00=GPIO 01=MCI2 10=PWM1.5 11=MOSI0 */
-#define PINCONN_PINSEL3_P1p24_MASK (3 << PINCONN_PINSEL3_P1p24_SHIFT)
-#define PINCONN_PINSEL3_P1p25_SHIFT (18) /* Bits 18-19: P1.25 00=GPIO 01=MCOA1 10=Reserved 11=MAT1.1 */
-#define PINCONN_PINSEL3_P1p25_MASK (3 << PINCONN_PINSEL3_P1p25_SHIFT)
-#define PINCONN_PINSEL3_P1p26_SHIFT (20) /* Bits 20-21: P1.26 00=GPIO 01=MCOB1 10=PWM1.6 11=CAP0.0 */
-#define PINCONN_PINSEL3_P1p26_MASK (3 << PINCONN_PINSEL3_P1p26_SHIFT)
-#define PINCONN_PINSEL3_P1p27_SHIFT (22) /* Bits 22-23: P1.27 00=GPIO 01=CLKOUT 10=USB_OVRCR 11=CAP0.1 */
-#define PINCONN_PINSEL3_P1p27_MASK (3 << PINCONN_PINSEL3_P1p27_SHIFT)
-#define PINCONN_PINSEL3_P1p28_SHIFT (24) /* Bits 24-25: P1.28 00=GPIO 01=MCOA2 10=PCAP1.0 11=MAT0.0 */
-#define PINCONN_PINSEL3_P1p28_MASK (3 << PINCONN_PINSEL3_P1p28_SHIFT)
-#define PINCONN_PINSEL3_P1p29_SHIFT (26) /* Bits 26-27: P1.29 00=GPIO 01=MCOB2 10=PCAP1.1 11=MAT0.1 */
-#define PINCONN_PINSEL3_P1p29_MASK (3 << PINCONN_PINSEL3_P1p29_SHIFT)
-#define PINCONN_PINSEL3_P1p30_SHIFT (28) /* Bits 28-29: P1.30 00=GPIO 01=Reserved 10=VBUS 11=AD0.4 */
-#define PINCONN_PINSEL3_P1p30_MASK (3 << PINCONN_PINSEL3_P1p30_SHIFT)
-#define PINCONN_PINSEL3_P1p31_SHIFT (30) /* Bits 30-31: P1.31 00=GPIO 01=Reserved 10=SCK1 11=AD0.5 */
-#define PINCONN_PINSEL3_P1p31_MASK (3 << PINCONN_PINSEL3_P1p31_SHIFT)
-
-/* Pin Function Select Register 4 (PINSEL4: 0x4002c010) */
-
-#define PINCONN_PINSEL4_P2_SHIFT(n) PINCONN_PINSELL_SHIFT(n) /* n=0,1,..,15 */
-#define PINCONN_PINSEL4_P2_MASK(n) PINCONN_PINSELL_MASK(n) /* n=0,1,..,15 */
-
-#define PINCONN_PINSEL4_P2p0_SHIFT (0) /* Bits 0-1: P2.0 00=GPIO 01=PWM1.1 10=TXD1 11=Reserved */
-#define PINCONN_PINSEL4_P2p0_MASK (3 << PINCONN_PINSEL4_P2p0_SHIFT)
-#define PINCONN_PINSEL4_P2p1_SHIFT (2) /* Bits 2-3: P2.1 00=GPIO 01=PWM1.2 10=RXD1 11=Reserved */
-#define PINCONN_PINSEL4_P2p1_MASK (3 << PINCONN_PINSEL4_P2p1_SHIFT)
-#define PINCONN_PINSEL4_P2p2_SHIFT (4) /* Bits 4-5: P2.2 00=GPIO 01=PWM1.3 10=CTS1 11=Reserved */
-#define PINCONN_PINSEL4_P2p2_MASK (3 << PINCONN_PINSEL4_P2p2_SHIFT)
-#define PINCONN_PINSEL4_P2p3_SHIFT (6) /* Bits 6-7: P2.3 00=GPIO 01=PWM1.4 10=DCD1 11=Reserved */
-#define PINCONN_PINSEL4_P2p3_MASK (3 << PINCONN_PINSEL4_P2p3_SHIFT)
-#define PINCONN_PINSEL4_P2p4_SHIFT (8) /* Bits 8-9: P2.4 00=GPIO 01=PWM1.5 10=DSR1 11=Reserved */
-#define PINCONN_PINSEL4_P2p4_MASK (3 << PINCONN_PINSEL4_P2p4_SHIFT)
-#define PINCONN_PINSEL4_P2p5_SHIFT (10) /* Bits 10-11: P2.5 00=GPIO 01=PWM1.6 10=DTR1 11=Reserved */
-#define PINCONN_PINSEL4_P2p5_MASK (3 << PINCONN_PINSEL4_P2p5_SHIFT)
-#define PINCONN_PINSEL4_P2p6_SHIFT (12) /* Bits 12-13: P2.6 00=GPIO 01=PCAP1.0 10=RI1 11=Reserved */
-#define PINCONN_PINSEL4_P2p6_MASK (3 << PINCONN_PINSEL4_P2p6_SHIFT)
-#define PINCONN_PINSEL4_P2p7_SHIFT (14) /* Bits 14-15: P2.7 00=GPIO 01=RD2 10=RTS1 11=Reserved */
-#define PINCONN_PINSEL4_P2p7_MASK (3 << PINCONN_PINSEL4_P2p7_SHIFT)
-#define PINCONN_PINSEL4_P2p8_SHIFT (16) /* Bits 16-17: P2.8 00=GPIO 01=TD2 10=TXD2 11=ENET_MDC */
-#define PINCONN_PINSEL4_P2p8_MASK (3 << PINCONN_PINSEL4_P2p8_SHIFT)
-#define PINCONN_PINSEL4_P2p9_SHIFT (18) /* Bits 18-19: P2.9 00=GPIO 01=USB_CONNECT 10=RXD2 11=ENET_MDIO */
-#define PINCONN_PINSEL4_P2p9_MASK (3 << PINCONN_PINSEL4_P2p9_SHIFT)
-#define PINCONN_PINSEL4_P2p10_SHIFT (20) /* Bits 20-21: P2.10 00=GPIO 01=EINT0 10=NMI 11=Reserved */
-#define PINCONN_PINSEL4_P2p10_MASK (3 << PINCONN_PINSEL4_P2p10_SHIFT)
-#define PINCONN_PINSEL4_P2p11_SHIFT (22) /* Bits 22-23: P2.11 00=GPIO 01=EINT1 10=Reserved 11=I2STX_CLK */
-#define PINCONN_PINSEL4_P2p11_MASK (3 << PINCONN_PINSEL4_P2p11_SHIFT)
-#define PINCONN_PINSEL4_P2p12_SHIFT (24) /* Bits 24-25: P2.12 00=GPIO 01=PEINT2 10=Reserved 11=I2STX_WS */
-#define PINCONN_PINSEL4_P2p12_MASK (3 << PINCONN_PINSEL4_P2p12_SHIFT)
-#define PINCONN_PINSEL4_P2p13_SHIFT (26) /* Bits 26-27: P2.13 00=GPIO 01=EINT3 10=Reserved 11=I2STX_SDA */
-#define PINCONN_PINSEL4_P2p13_MASK (3 << PINCONN_PINSEL4_P2p13_SHIFT)
- /* Bits 28-31: Reserved */
-/* Pin Function Select Register 7 (PINSEL7: 0x4002c01c) */
-
-#define PINCONN_PINSEL7_P3_SHIFT(n) PINCONN_PINSELH_SHIFT(n) /* n=16,17,..31 */
-#define PINCONN_PINSEL7_P3_MASK(n) PINCONN_PINSELH_MASK(n) /* n=16,17,..31 */
-
- /* Bits 0-17: Reserved */
-#define PINCONN_PINSEL7_P3p25_SHIFT (18) /* Bits 18-19: P3.25 00=GPIO 01=Reserved 10=MAT0.0 11=PWM1.2 */
-#define PINCONN_PINSEL7_P3p25_MASK (3 << PINCONN_PINSEL7_P3p25_SHIFT)
-#define PINCONN_PINSEL7_P3p26_SHIFT (20) /* Bits 20-21: P3.26 00=GPIO 01=STCLK 10=MAT0.1 11=PWM1.3 */
-#define PINCONN_PINSEL7_P3p26_MASK (3 << PINCONN_PINSEL7_P3p26_SHIFT)
- /* Bits 22-31: Reserved */
-
-/* Pin Function Select Register 8 (PINSEL8: 0x4002c020) */
-/* No description of bits -- Does this register exist? */
-
-/* Pin Function Select Register 9 (PINSEL9: 0x4002c024) */
-
-#define PINCONN_PINSEL9_P4_SHIFT(n) PINCONN_PINSELH_SHIFT(n) /* n=16,17,..31 */
-#define PINCONN_PINSEL9_P4_MASK(n) PINCONN_PINSELH_MASK(n) /* n=16,17,..31 */
-
- /* Bits 0-23: Reserved */
-#define PINCONN_PINSEL9_P4p28_SHIFT (24) /* Bits 24-25: P4.28 00=GPIO 01=RX_MCLK 10=MAT2.0 11=TXD3 */
-#define PINCONN_PINSEL9_P4p28_MASK (3 << PINCONN_PINSEL9_P4p28_SHIFT)
-#define PINCONN_PINSEL9_P4p29_SHIFT (26) /* Bits 26-27: P4.29 00=GPIO 01=TX_MCLK 10=MAT2.1 11=RXD3 */
-#define PINCONN_PINSEL9_P4p29_MASK (3 << PINCONN_PINSEL9_P4p29_SHIFT)
- /* Bits 28-31: Reserved */
-/* Pin Function Select Register 10 (PINSEL10: 0x4002c028) */
- /* Bits 0-2: Reserved */
-#define PINCONN_PINSEL10_TPIU (1 << 3) /* Bit 3: 0=TPIU interface disabled; 1=TPIU interface enabled */
- /* Bits 4-31: Reserved */
-/* Pin Mode select register 0 (PINMODE0: 0x4002c040) */
-
-#define PINCONN_PINMODE_PU (0) /* 00: pin has a pull-up resistor enabled */
-#define PINCONN_PINMODE_RM (1) /* 01: pin has repeater mode enabled */
-#define PINCONN_PINMODE_FLOAT (2) /* 10: pin has neither pull-up nor pull-down */
-#define PINCONN_PINMODE_PD (3) /* 11: pin has a pull-down resistor enabled */
-#define PINCONN_PINMODE_MASK (3)
-
-#define PINCONN_PINMODEL_SHIFT(n) ((n) << 1) /* n=0,1,..,15 */
-#define PINCONN_PINMODEL_MASK(n) (3 << PINCONN_PINMODEL_SHIFT(n))
-#define PINCONN_PINMODEH_SHIFT(n) (((n)-16) << 1) /* n=16,17,..31 */
-#define PINCONN_PINMODEH_MASK(n) (3 << PINCONN_PINMODEH_SHIFT(n))
-
-#define PINCONN_PINMODE0_P0_SHIFT(n) PINCONN_PINMODEL_SHIFT(n) /* n=0,1,..,15 */
-#define PINCONN_PINMODE0_P0_MASK(n) PINCONN_PINMODEL_MASK(n) /* n=0,1,..,15 */
-
-#define PINCONN_PINMODE0_P0p0_SHIFT (0) /* Bits 0-1: P0.0 mode control */
-#define PINCONN_PINMODE0_P0p0_MASK (3 << PINCONN_PINMODE0_P0p0_SHIFT)
-#define PINCONN_PINMODE0_P0p1_SHIFT (2) /* Bits 2-3: P0.1 mode control */
-#define PINCONN_PINMODE0_P0p1_MASK (3 << PINCONN_PINMODE0_P0p1_SHIFT)
-#define PINCONN_PINMODE0_P0p2_SHIFT (4) /* Bits 4-5: P0.2 mode control */
-#define PINCONN_PINMODE0_P0p2_MASK (3 << PINCONN_PINMODE0_P0p2_SHIFT)
-#define PINCONN_PINMODE0_P0p3_SHIFT (6) /* Bits 6-7: P0.3 mode control */
-#define PINCONN_PINMODE0_P0p3_MASK (3 << PINCONN_PINMODE0_P0p3_SHIFT)
-#define PINCONN_PINMODE0_P0p4_SHIFT (8) /* Bits 8-9: P0.4 mode control */
-#define PINCONN_PINMODE0_P0p4_MASK (3 << PINCONN_PINMODE0_P0p4_SHIFT)
-#define PINCONN_PINMODE0_P0p5_SHIFT (10) /* Bits 10-11: P0.5 mode control */
-#define PINCONN_PINMODE0_P0p5_MASK (3 << PINCONN_PINMODE0_P0p5_SHIFT)
-#define PINCONN_PINMODE0_P0p6_SHIFT (12) /* Bits 12-13: P0.6 mode control */
-#define PINCONN_PINMODE0_P0p6_MASK (3 << PINCONN_PINMODE0_P0p6_SHIFT)
-#define PINCONN_PINMODE0_P0p7_SHIFT (14) /* Bits 14-15: P0.7 mode control */
-#define PINCONN_PINMODE0_P0p7_MASK (3 << PINCONN_PINMODE0_P0p7_SHIFT)
-#define PINCONN_PINMODE0_P0p8_SHIFT (16) /* Bits 16-17: P0.8 mode control */
-#define PINCONN_PINMODE0_P0p8_MASK (3 << PINCONN_PINMODE0_P0p8_SHIFT)
-#define PINCONN_PINMODE0_P0p9_SHIFT (18) /* Bits 18-19: P0.9 mode control */
-#define PINCONN_PINMODE0_P0p9_MASK (3 << PINCONN_PINMODE0_P0p9_SHIFT)
-#define PINCONN_PINMODE0_P0p10_SHIFT (20) /* Bits 20-21: P0.10 mode control */
-#define PINCONN_PINMODE0_P0p10_MASK (3 << PINCONN_PINMODE0_P0p10_SHIFT)
-#define PINCONN_PINMODE0_P0p11_SHIFT (22) /* Bits 22-23: P0.11 mode control */
-#define PINCONN_PINMODE0_P0p11_MASK (3 << PINCONN_PINMODE0_P0p11_SHIFT)
- /* Bits 24-29: Reserved */
-#define PINCONN_PINMODE0_P0p15_SHIFT (30) /* Bits 30-31: P0.15 mode control */
-#define PINCONN_PINMODE0_P0p15_MASK (3 << PINCONN_PINMODE0_P0p15_SHIFT)
-
-/* Pin Mode select register 1 (PINMODE1: 0x4002c044) */
-
-#define PINCONN_PINMODE1_P0_SHIFT(n) PINCONN_PINMODEH_SHIFT(n) /* n=16,17,..31 */
-#define PINCONN_PINMODE1_P0_MASK(n) PINCONN_PINMODEH_MASK(n) /* n=16,17,..31 */
-
-#define PINCONN_PINMODE1_P0p16_SHIFT (0) /* Bits 0-1: P0.16 mode control */
-#define PINCONN_PINMODE1_P0p16_MASK (3 << PINCONN_PINMODE1_P0p16_SHIFT)
-#define PINCONN_PINMODE1_P0p17_SHIFT (2) /* Bits 2-3: P0.17 mode control */
-#define PINCONN_PINMODE1_P0p17_MASK (3 << PINCONN_PINMODE1_P0p17_SHIFT)
-#define PINCONN_PINMODE1_P0p18_SHIFT (4) /* Bits 4-5: P0.18 mode control */
-#define PINCONN_PINMODE1_P0p18_MASK (3 << PINCONN_PINMODE1_P0p18_SHIFT)
-#define PINCONN_PINMODE1_P0p19_SHIFT (6) /* Bits 6-7: P0.19 mode control */
-#define PINCONN_PINMODE1_P0p19_MASK (3 << PINCONN_PINMODE1_P0p19_SHIFT)
-#define PINCONN_PINMODE1_P0p20_SHIFT (8) /* Bits 8-9: P0.20 mode control */
-#define PINCONN_PINMODE1_P0p20_MASK (3 << PINCONN_PINMODE1_P0p20_SHIFT)
-#define PINCONN_PINMODE1_P0p21_SHIFT (10) /* Bits 10-11: P0.21 mode control */
-#define PINCONN_PINMODE1_P0p21_MASK (3 << PINCONN_PINMODE1_P0p21_SHIFT)
-#define PINCONN_PINMODE1_P0p22_SHIFT (12) /* Bits 12-13: P0.22 mode control */
-#define PINCONN_PINMODE1_P0p22_MASK (3 << PINCONN_PINMODE1_P0p22_SHIFT)
-#define PINCONN_PINMODE1_P0p23_SHIFT (14) /* Bits 14-15: P0.23 mode control */
-#define PINCONN_PINMODE1_P0p23_MASK (3 << PINCONN_PINMODE1_P0p23_SHIFT)
-#define PINCONN_PINMODE1_P0p24_SHIFT (16) /* Bits 16-17: P0.24 mode control */
-#define PINCONN_PINMODE1_P0p24_MASK (3 << PINCONN_PINMODE1_P0p24_SHIFT)
-#define PINCONN_PINMODE1_P0p25_SHIFT (18) /* Bits 18-19: P0.25 mode control */
-#define PINCONN_PINMODE1_P0p25_MASK (3 << PINCONN_PINMODE1_P0p25_SHIFT)
-#define PINCONN_PINMODE1_P0p26_SHIFT (20) /* Bits 20-21: P0.26 mode control */
-#define PINCONN_PINMODE1_P0p26_MASK (3 << PINCONN_PINMODE1_P0p26_SHIFT)
- /* Bits 22-31: Reserved */
-
-/* Pin Mode select register 2 (PINMODE2: 0x4002c048) */
-
-#define PINCONN_PINMODE2_P1_SHIFT(n) PINCONN_PINMODEL_SHIFT(n) /* n=0,1,..,15 */
-#define PINCONN_PINMODE2_P1_MASK(n) PINCONN_PINMODEL_MASK(n) /* n=0,1,..,15 */
-
-#define PINCONN_PINMODE2_P1p0_SHIFT (0) /* Bits 2-1: P1.0 mode control */
-#define PINCONN_PINMODE2_P1p0_MASK (3 << PINCONN_PINMODE2_P1p0_SHIFT)
-#define PINCONN_PINMODE2_P1p1_SHIFT (2) /* Bits 2-3: P1.1 mode control */
-#define PINCONN_PINMODE2_P1p1_MASK (3 << PINCONN_PINMODE2_P1p1_SHIFT)
- /* Bits 4-7: Reserved */
-#define PINCONN_PINMODE2_P1p4_SHIFT (8) /* Bits 8-9: P1.4 mode control */
-#define PINCONN_PINMODE2_P1p4_MASK (3 << PINCONN_PINMODE2_P1p4_SHIFT)
- /* Bits 10-15: Reserved */
-#define PINCONN_PINMODE2_P1p8_SHIFT (16) /* Bits 16-17: P1.8 mode control */
-#define PINCONN_PINMODE2_P1p8_MASK (3 << PINCONN_PINMODE2_P1p8_SHIFT)
-#define PINCONN_PINMODE2_P1p9_SHIFT (18) /* Bits 18-19: P1.9 mode control */
-#define PINCONN_PINMODE2_P1p9_MASK (3 << PINCONN_PINMODE2_P1p9_SHIFT)
-#define PINCONN_PINMODE2_P1p10_SHIFT (20) /* Bits 20-21: P1.10 mode control */
-#define PINCONN_PINMODE2_P1p10_MASK (3 << PINCONN_PINMODE2_P1p10_SHIFT)
- /* Bits 22-27: Reserved */
-#define PINCONN_PINMODE2_P1p14_SHIFT (28) /* Bits 28-29: P1.14 mode control */
-#define PINCONN_PINMODE2_P1p14_MASK (3 << PINCONN_PINMODE2_P1p14_SHIFT)
-#define PINCONN_PINMODE2_P1p15_SHIFT (30) /* Bits 30-31: P1.15 mode control */
-#define PINCONN_PINMODE2_P1p15_MASK (3 << PINCONN_PINMODE2_P1p15_SHIFT)
-
-/* Pin Mode select register 3 (PINMODE3: 0x4002c04c) */
-
-#define PINCONN_PINMODE3_P1_SHIFT(n) PINCONN_PINMODEH_SHIFT(n) /* n=16,17,..31 */
-#define PINCONN_PINMODE3_P1_MASK(n) PINCONN_PINMODEH_MASK(n) /* n=16,17,..31 */
-
-#define PINCONN_PINMODE3_P1p16_SHIFT (0) /* Bits 0-1: P1.16 mode control */
-#define PINCONN_PINMODE3_P1p16_MASK (3 << PINCONN_PINMODE3_P1p16_SHIFT)
-#define PINCONN_PINMODE3_P1p17_SHIFT (2) /* Bits 2-3: P1.17 mode control */
-#define PINCONN_PINMODE3_P1p17_MASK (3 << PINCONN_PINMODE3_P1p17_SHIFT)
-#define PINCONN_PINMODE3_P1p18_SHIFT (4) /* Bits 4-5: P1.18 mode control */
-#define PINCONN_PINMODE3_P1p18_MASK (3 << PINCONN_PINMODE3_P1p18_SHIFT)
-#define PINCONN_PINMODE3_P1p19_SHIFT (6) /* Bits 6-7: P1.19 mode control */
-#define PINCONN_PINMODE3_P1p19_MASK (3 << PINCONN_PINMODE3_P1p19_SHIFT)
-#define PINCONN_PINMODE3_P1p20_SHIFT (8) /* Bits 8-9: P1.20 mode control */
-#define PINCONN_PINMODE3_P1p20_MASK (3 << PINCONN_PINMODE3_P1p20_SHIFT)
-#define PINCONN_PINMODE3_P1p21_SHIFT (10) /* Bits 10-11: P1.21 mode control */
-#define PINCONN_PINMODE3_P1p21_MASK (3 << PINCONN_PINMODE3_P1p21_SHIFT)
-#define PINCONN_PINMODE3_P1p22_SHIFT (12) /* Bits 12-13: P1.22 mode control */
-#define PINCONN_PINMODE3_P1p22_MASK (3 << PINCONN_PINMODE3_P1p22_SHIFT)
-#define PINCONN_PINMODE3_P1p23_SHIFT (14) /* Bits 14-15: P1.23 mode control */
-#define PINCONN_PINMODE3_P1p23_MASK (3 << PINCONN_PINMODE3_P1p23_SHIFT)
-#define PINCONN_PINMODE3_P1p24_SHIFT (16) /* Bits 16-17: P1.24 mode control */
-#define PINCONN_PINMODE3_P1p24_MASK (3 << PINCONN_PINMODE3_P1p24_SHIFT)
-#define PINCONN_PINMODE3_P1p25_SHIFT (18) /* Bits 18-19: P1.25 mode control */
-#define PINCONN_PINMODE3_P1p25_MASK (3 << PINCONN_PINMODE3_P1p25_SHIFT)
-#define PINCONN_PINMODE3_P1p26_SHIFT (20) /* Bits 20-21: P1.26 mode control */
-#define PINCONN_PINMODE3_P1p26_MASK (3 << PINCONN_PINMODE3_P1p26_SHIFT)
-#define PINCONN_PINMODE3_P1p27_SHIFT (22) /* Bits 22-23: P1.27 mode control */
-#define PINCONN_PINMODE3_P1p27_MASK (3 << PINCONN_PINMODE3_P1p27_SHIFT)
-#define PINCONN_PINMODE3_P1p28_SHIFT (24) /* Bits 24-25: P1.28 mode control */
-#define PINCONN_PINMODE3_P1p28_MASK (3 << PINCONN_PINMODE3_P1p28_SHIFT)
-#define PINCONN_PINMODE3_P1p29_SHIFT (26) /* Bits 26-27: P1.29 mode control */
-#define PINCONN_PINMODE3_P1p29_MASK (3 << PINCONN_PINMODE3_P1p29_SHIFT)
-#define PINCONN_PINMODE3_P1p30_SHIFT (28) /* Bits 28-29: P1.30 mode control */
-#define PINCONN_PINMODE3_P1p30_MASK (3 << PINCONN_PINMODE3_P1p30_SHIFT)
-#define PINCONN_PINMODE3_P1p31_SHIFT (30) /* Bits 30-31: P1.31 mode control */
-#define PINCONN_PINMODE3_P1p31_MASK (3 << PINCONN_PINMODE3_P1p31_SHIFT)
-
-/* Pin Mode select register 4 (PINMODE4: 0x4002c050) */
-
-#define PINCONN_PINMODE4_P2_SHIFT(n) PINCONN_PINMODEL_SHIFT(n) /* n=0,1,..,15 */
-#define PINCONN_PINMODE4_P2_MASK(n) PINCONN_PINMODEL_MASK(n) /* n=0,1,..,15 */
-
-#define PINCONN_PINMODE4_P2p0_SHIFT (0) /* Bits 0-1: P2.0 mode control */
-#define PINCONN_PINMODE4_P2p0_MASK (3 << PINCONN_PINMODE4_P2p0_SHIFT)
-#define PINCONN_PINMODE4_P2p1_SHIFT (2) /* Bits 2-3: P2.1 mode control */
-#define PINCONN_PINMODE4_P2p1_MASK (3 << PINCONN_PINMODE4_P2p1_SHIFT)
-#define PINCONN_PINMODE4_P2p2_SHIFT (4) /* Bits 4-5: P2.2 mode control */
-#define PINCONN_PINMODE4_P2p2_MASK (3 << PINCONN_PINMODE4_P2p2_SHIFT)
-#define PINCONN_PINMODE4_P2p3_SHIFT (6) /* Bits 6-7: P2.3 mode control */
-#define PINCONN_PINMODE4_P2p3_MASK (3 << PINCONN_PINMODE4_P2p3_SHIFT)
-#define PINCONN_PINMODE4_P2p4_SHIFT (8) /* Bits 8-9: P2.4 mode control */
-#define PINCONN_PINMODE4_P2p4_MASK (3 << PINCONN_PINMODE4_P2p4_SHIFT)
-#define PINCONN_PINMODE4_P2p5_SHIFT (10) /* Bits 10-11: P2.5 mode control */
-#define PINCONN_PINMODE4_P2p5_MASK (3 << PINCONN_PINMODE4_P2p5_SHIFT)
-#define PINCONN_PINMODE4_P2p6_SHIFT (12) /* Bits 12-13: P2.6 mode control */
-#define PINCONN_PINMODE4_P2p6_MASK (3 << PINCONN_PINMODE4_P2p6_SHIFT)
-#define PINCONN_PINMODE4_P2p7_SHIFT (14) /* Bits 14-15: P2.7 mode control */
-#define PINCONN_PINMODE4_P2p7_MASK (3 << PINCONN_PINMODE4_P2p7_SHIFT)
-#define PINCONN_PINMODE4_P2p8_SHIFT (16) /* Bits 16-17: P2.8 mode control */
-#define PINCONN_PINMODE4_P2p8_MASK (3 << PINCONN_PINMODE4_P2p8_SHIFT)
-#define PINCONN_PINMODE4_P2p9_SHIFT (18) /* Bits 18-19: P2.9 mode control */
-#define PINCONN_PINMODE4_P2p9_MASK (3 << PINCONN_PINMODE4_P2p9_SHIFT)
-#define PINCONN_PINMODE4_P2p10_SHIFT (20) /* Bits 20-21: P2.10 mode control */
-#define PINCONN_PINMODE4_P2p10_MASK (3 << PINCONN_PINMODE4_P2p10_SHIFT)
-#define PINCONN_PINMODE4_P2p11_SHIFT (22) /* Bits 22-23: P2.11 mode control */
-#define PINCONN_PINMODE4_P2p11_MASK (3 << PINCONN_PINMODE4_P2p11_SHIFT)
-#define PINCONN_PINMODE4_P2p12_SHIFT (24) /* Bits 24-25: P2.12 mode control */
-#define PINCONN_PINMODE4_P2p12_MASK (3 << PINCONN_PINMODE4_P2p12_SHIFT)
-#define PINCONN_PINMODE4_P2p13_SHIFT (26) /* Bits 26-27: P2.13 mode control */
-#define PINCONN_PINMODE4_P2p13_MASK (3 << PINCONN_PINMODE4_P2p13_SHIFT)
- /* Bits 28-31: Reserved */
-/* Pin Mode select register 5 (PINMODE5: 0x4002c054)
- * Pin Mode select register 6 (PINMODE6: 0x4002c058)
- * No bit definitions -- do these registers exist?
- */
-
-#define PINCONN_PINMODE5_P2_SHIFT(n) PINCONN_PINMODEH_SHIFT(n) /* n=16,17,..31 */
-#define PINCONN_PINMODE5_P2_MASK(n) PINCONN_PINMODEH_MASK(n) /* n=16,17,..31 */
-
-#define PINCONN_PINMODE6_P3_SHIFT(n) PINCONN_PINMODEL_SHIFT(n) /* n=0,1,..,15 */
-#define PINCONN_PINMODE6_P3_MASK(n) PINCONN_PINMODEL_MASK(n) /* n=0,1,..,15 */
-
-/* Pin Mode select register 7 (PINMODE7: 0x4002c05c) */
-
-#define PINCONN_PINMODE7_P3_SHIFT(n) PINCONN_PINMODEH_SHIFT(n) /* n=16,17,..31 */
-#define PINCONN_PINMODE7_P3_MASK(n) PINCONN_PINMODEH_MASK(n) /* n=16,17,..31 */
- /* Bits 0-17: Reserved */
-#define PINCONN_PINMODE7_P3p25_SHIFT (18) /* Bits 18-19: P3.25 mode control */
-#define PINCONN_PINMODE7_P3p25_MASK (3 << PINCONN_PINMODE7_P3p25_SHIFT)
-#define PINCONN_PINMODE7_P3p26_SHIFT (20) /* Bits 20-21: P3.26 mode control */
-#define PINCONN_PINMODE7_P3p26_MASK (3 << PINCONN_PINMODE7_P3p26_SHIFT)
- /* Bits 22-31: Reserved */
-/* Pin Mode select register 9 (PINMODE9: 0x4002c064) */
-
-#define PINCONN_PINMODE9_P4_SHIFT(n) PINCONN_PINMODEH_SHIFT(n) /* n=16,17,..31 */
-#define PINCONN_PINMODE9_P4_MASK(n) PINCONN_PINMODEH_MASK(n) /* n=16,17,..31 */
- /* Bits 0-23: Reserved */
-#define PINCONN_PINMODE9_P4p28_SHIFT (24) /* Bits 24-25: P4.28 mode control */
-#define PINCONN_PINMODE9_P4p28_MASK (3 << PINCONN_PINMODE9_P4p28_SHIFT)
-#define PINCONN_PINMODE9_P4p29_SHIFT (26) /* Bits 26-27: P4.29 mode control */
-#define PINCONN_PINMODE9_P4p29_MASK (3 << PINCONN_PINMODE9_P4p29_SHIFT)
- /* Bits 28-31: Reserved */
-/* Open Drain Pin Mode select register 0 (PINMODE_OD0: 0x4002c068) */
-
-#define PINCONN_ODMODE0_P0(n) (1 << (n))
-
-#define PINCONN_ODMODE0_P0p0 (1 << 0) /* Bit 0: P0.0 open drain mode */
-#define PINCONN_ODMODE0_P0p1 (1 << 1) /* Bit 1: P0.1 open drain mode */
-#define PINCONN_ODMODE0_P0p2 (1 << 2) /* Bit 2: P0.2 open drain mode */
-#define PINCONN_ODMODE0_P0p3 (1 << 3) /* Bit 3: P0.3 open drain mode */
-#define PINCONN_ODMODE0_P0p4 (1 << 4) /* Bit 4: P0.4 open drain mode */
-#define PINCONN_ODMODE0_P0p5 (1 << 5) /* Bit 5: P0.5 open drain mode */
-#define PINCONN_ODMODE0_P0p6 (1 << 6) /* Bit 6: P0.6 open drain mode */
-#define PINCONN_ODMODE0_P0p7 (1 << 7) /* Bit 7: P0.7 open drain mode */
-#define PINCONN_ODMODE0_P0p8 (1 << 8) /* Bit 8: P0.8 open drain mode */
-#define PINCONN_ODMODE0_P0p9 (1 << 9) /* Bit 9: P0.9 open drain mode */
-#define PINCONN_ODMODE0_P0p10 (1 << 10) /* Bit 10: P0.10 open drain mode */
-#define PINCONN_ODMODE0_P0p11 (1 << 11) /* Bit 11: P0.11 open drain mode */
- /* Bits 12-14: Reserved */
-#define PINCONN_ODMODE0_P0p15 (1 << 15) /* Bit 15: P0.15 open drain mode */
-#define PINCONN_ODMODE0_P0p16 (1 << 16) /* Bit 16: P0.16 open drain mode */
-#define PINCONN_ODMODE0_P0p17 (1 << 17) /* Bit 17: P0.17 open drain mode */
-#define PINCONN_ODMODE0_P0p18 (1 << 18) /* Bit 18: P0.18 open drain mode */
-#define PINCONN_ODMODE0_P0p19 (1 << 19) /* Bit 19: P0.19 open drain mode */
-#define PINCONN_ODMODE0_P0p20 (1 << 20) /* Bit 20: P0.20 open drain mode */
-#define PINCONN_ODMODE0_P0p21 (1 << 21) /* Bit 21: P0.21 open drain mode */
-#define PINCONN_ODMODE0_P0p22 (1 << 22) /* Bit 22: P0.22 open drain mode */
-#define PINCONN_ODMODE0_P0p23 (1 << 23) /* Bit 23: P0.23 open drain mode */
-#define PINCONN_ODMODE0_P0p24 (1 << 24) /* Bit 24: P0.24 open drain mode */
-#define PINCONN_ODMODE0_P0p25 (1 << 25) /* Bit 25: P0.25 open drain mode */
-#define PINCONN_ODMODE0_P0p26 (1 << 25) /* Bit 26: P0.26 open drain mode */
- /* Bits 27-28: Reserved */
-#define PINCONN_ODMODE0_P0p29 (1 << 29) /* Bit 29: P0.29 open drain mode */
-#define PINCONN_ODMODE0_P0p30 (1 << 30) /* Bit 30: P0.30 open drain mode */
- /* Bit 31: Reserved */
-/* Open Drain Pin Mode select register 1 (PINMODE_OD1: 0x4002c06c) */
-
-#define PINCONN_ODMODE1_P1(n) (1 << (n))
-
-#define PINCONN_ODMODE1_P1p0 (1 << 0) /* Bit 0: P1.0 open drain mode */
-#define PINCONN_ODMODE1_P1p1 (1 << 1) /* Bit 1: P1.1 open drain mode */
- /* Bits 2-3: Reserved */
-#define PINCONN_ODMODE1_P1p4 (1 << 4) /* Bit 4: P1.4 open drain mode */
- /* Bits 5-7: Reserved */
-#define PINCONN_ODMODE1_P1p8 (1 << 8) /* Bit 8: P1.8 open drain mode */
-#define PINCONN_ODMODE1_P1p9 (1 << 9) /* Bit 9: P1.9 open drain mode */
-#define PINCONN_ODMODE1_P1p10 (1 << 10) /* Bit 10: P1.10 open drain mode */
- /* Bits 11-13: Reserved */
-#define PINCONN_ODMODE1_P1p14 (1 << 14) /* Bit 14: P1.14 open drain mode */
-#define PINCONN_ODMODE1_P1p15 (1 << 15) /* Bit 15: P1.15 open drain mode */
-#define PINCONN_ODMODE1_P1p16 (1 << 16) /* Bit 16: P1.16 open drain mode */
-#define PINCONN_ODMODE1_P1p17 (1 << 17) /* Bit 17: P1.17 open drain mode */
-#define PINCONN_ODMODE1_P1p18 (1 << 18) /* Bit 18: P1.18 open drain mode */
-#define PINCONN_ODMODE1_P1p19 (1 << 19) /* Bit 19: P1.19 open drain mode */
-#define PINCONN_ODMODE1_P1p20 (1 << 20) /* Bit 20: P1.20 open drain mode */
-#define PINCONN_ODMODE1_P1p21 (1 << 21) /* Bit 21: P1.21 open drain mode */
-#define PINCONN_ODMODE1_P1p22 (1 << 22) /* Bit 22: P1.22 open drain mode */
-#define PINCONN_ODMODE1_P1p23 (1 << 23) /* Bit 23: P1.23 open drain mode */
-#define PINCONN_ODMODE1_P1p24 (1 << 24) /* Bit 24: P1.24 open drain mode */
-#define PINCONN_ODMODE1_P1p25 (1 << 25) /* Bit 25: P1.25 open drain mode */
-#define PINCONN_ODMODE1_P1p26 (1 << 25) /* Bit 26: P1.26 open drain mode */
-#define PINCONN_ODMODE1_P1p27 (1 << 27) /* Bit 27: P1.27 open drain mode */
-#define PINCONN_ODMODE1_P1p28 (1 << 28) /* Bit 28: P1.28 open drain mode */
-#define PINCONN_ODMODE1_P1p29 (1 << 29) /* Bit 29: P1.29 open drain mode */
-#define PINCONN_ODMODE1_P1p30 (1 << 30) /* Bit 30: P1.30 open drain mode */
-#define PINCONN_ODMODE1_P1p31 (1 << 31) /* Bit 31: P1.31 open drain mode */
-
-/* Open Drain Pin Mode select register 2 (PINMODE_OD2: 0x4002c070) */
-
-#define PINCONN_ODMODE2_P2(n) (1 << (n))
-
-#define PINCONN_ODMODE2_P2p0 (1 << 0) /* Bit 0: P2.0 open drain mode */
-#define PINCONN_ODMODE2_P2p1 (1 << 1) /* Bit 1: P2.1 open drain mode */
-#define PINCONN_ODMODE2_P2p2 (1 << 2) /* Bit 2: P2.2 open drain mode */
-#define PINCONN_ODMODE2_P2p3 (1 << 3) /* Bit 3: P2.3 open drain mode */
-#define PINCONN_ODMODE2_P2p4 (1 << 4) /* Bit 4: P2.4 open drain mode */
-#define PINCONN_ODMODE2_P2p5 (1 << 5) /* Bit 5: P2.5 open drain mode */
-#define PINCONN_ODMODE2_P2p6 (1 << 6) /* Bit 6: P2.6 open drain mode */
-#define PINCONN_ODMODE2_P2p7 (1 << 7) /* Bit 7: P2.7 open drain mode */
-#define PINCONN_ODMODE2_P2p8 (1 << 8) /* Bit 8: P2.8 open drain mode */
-#define PINCONN_ODMODE2_P2p9 (1 << 9) /* Bit 9: P2.9 open drain mode */
-#define PINCONN_ODMODE2_P2p10 (1 << 10) /* Bit 10: P2.10 open drain mode */
-#define PINCONN_ODMODE2_P2p11 (1 << 11) /* Bit 11: P2.11 open drain mode */
-#define PINCONN_ODMODE2_P2p12 (1 << 12) /* Bit 12: P2.12 open drain mode */
-#define PINCONN_ODMODE2_P2p13 (1 << 13) /* Bit 13: P2.13 open drain mode */
- /* Bits 14-31: Reserved */
-/* Open Drain Pin Mode select register 3 (PINMODE_OD3: 0x4002c074) */
-
-#define PINCONN_ODMODE3_P3(n) (1 << (n))
- /* Bits 0-24: Reserved */
-#define PINCONN_ODMODE3_P3p25 (1 << 25) /* Bit 25: P3.25 open drain mode */
-#define PINCONN_ODMODE3_P3p26 (1 << 25) /* Bit 26: P3.26 open drain mode */
- /* Bits 17-31: Reserved */
-/* Open Drain Pin Mode select register 4 (PINMODE_OD4: 0x4002c078) */
-
-#define PINCONN_ODMODE4_P4(n) (1 << (n))
- /* Bits 0-27: Reserved */
-#define PINCONN_ODMODE4_P4p28 (1 << 28) /* Bit 28: P4.28 open drain mode */
-#define PINCONN_ODMODE4_P4p29 (1 << 29) /* Bit 29: P4.29 open drain mode */
- /* Bits 30-31: Reserved */
-/* I2C Pin Configuration register (I2CPADCFG: 0x4002c07c) */
-
-#define PINCONN_I2CPADCFG_SDADRV0 (1 << 0) /* Bit 0: SDA0 pin, P0.27 in Fast Mode Plus */
-#define PINCONN_I2CPADCFG_SDAI2C0 (1 << 1) /* Bit 1: SDA0 pin, P0.27 I2C glitch
- * filtering/slew rate control */
-#define PINCONN_I2CPADCFG_SCLDRV0 (1 << 2) /* Bit 2: SCL0 pin, P0.28 in Fast Mode Plus */
-#define PINCONN_I2CPADCFG_SCLI2C0 (1 << 3) /* Bit 3: SCL0 pin, P0.28 I2C glitch
- * filtering/slew rate control */
- /* Bits 4-31: Reserved */
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-/************************************************************************************
- * Public Functions
- ************************************************************************************/
-
-#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_PINCONN_H */
+/************************************************************************************ + * arch/arm/src/lpc17xx/lpc17_pinconn.h + * + * Copyright (C) 2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_PINCONN_H +#define __ARCH_ARM_SRC_LPC17XX_LPC17_PINCONN_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +#include "chip.h" +#include "lpc17_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register offsets *****************************************************************/ + +#define LPC17_PINCONN_PINSEL0_OFFSET 0x0000 /* Pin function select register 0 */ +#define LPC17_PINCONN_PINSEL1_OFFSET 0x0004 /* Pin function select register 1 */ +#define LPC17_PINCONN_PINSEL2_OFFSET 0x0008 /* Pin function select register 2 */ +#define LPC17_PINCONN_PINSEL3_OFFSET 0x000c /* Pin function select register 3 */ +#define LPC17_PINCONN_PINSEL4_OFFSET 0x0010 /* Pin function select register 4 */ +#define LPC17_PINCONN_PINSEL7_OFFSET 0x001c /* Pin function select register 7 */ +#define LPC17_PINCONN_PINSEL8_OFFSET 0x0020 /* Pin function select register 8 */ +#define LPC17_PINCONN_PINSEL9_OFFSET 0x0024 /* Pin function select register 9 */ +#define LPC17_PINCONN_PINSEL10_OFFSET 0x0028 /* Pin function select register 10 */ +#define LPC17_PINCONN_PINMODE0_OFFSET 0x0040 /* Pin mode select register 0 */ +#define LPC17_PINCONN_PINMODE1_OFFSET 0x0044 /* Pin mode select register 1 */ +#define LPC17_PINCONN_PINMODE2_OFFSET 0x0048 /* Pin mode select register 2 */ +#define LPC17_PINCONN_PINMODE3_OFFSET 0x004c /* Pin mode select register 3 */ +#define LPC17_PINCONN_PINMODE4_OFFSET 0x0050 /* Pin mode select register 4 */ +#define LPC17_PINCONN_PINMODE5_OFFSET 0x0054 /* Pin mode select register 5 */ +#define LPC17_PINCONN_PINMODE6_OFFSET 0x0058 /* Pin mode select register 6 */ +#define LPC17_PINCONN_PINMODE7_OFFSET 0x005c /* Pin mode select register 7 */ +#define LPC17_PINCONN_PINMODE9_OFFSET 0x0064 /* Pin mode select register 9 */ +#define LPC17_PINCONN_ODMODE0_OFFSET 0x0068 /* Open drain mode control register 0 */ +#define LPC17_PINCONN_ODMODE1_OFFSET 0x006c /* Open drain mode control register 1 */ +#define LPC17_PINCONN_ODMODE2_OFFSET 0x0070 /* Open drain mode control register 2 */ +#define LPC17_PINCONN_ODMODE3_OFFSET 0x0074 /* Open drain mode control register 3 */ +#define LPC17_PINCONN_ODMODE4_OFFSET 0x0078 /* Open drain mode control register 4 */ +#define LPC17_PINCONN_I2CPADCFG_OFFSET 0x007c /* I2C Pin Configuration register */ + +/* Register addresses ***************************************************************/ + +#define LPC17_PINCONN_PINSEL0 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINSEL0_OFFSET) +#define LPC17_PINCONN_PINSEL1 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINSEL1_OFFSET) +#define LPC17_PINCONN_PINSEL2 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINSEL2_OFFSET) +#define LPC17_PINCONN_PINSEL3 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINSEL3_OFFSET) +#define LPC17_PINCONN_PINSEL4 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINSEL4_OFFSET) +#define LPC17_PINCONN_PINSEL7 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINSEL7_OFFSET) +#define LPC17_PINCONN_PINSEL8 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINSEL8_OFFSET) +#define LPC17_PINCONN_PINSEL9 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINSEL9_OFFSET) +#define LPC17_PINCONN_PINSEL10 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINSEL10_OFFSET) +#define LPC17_PINCONN_PINMODE0 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINMODE0_OFFSET) +#define LPC17_PINCONN_PINMODE1 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINMODE1_OFFSET) +#define LPC17_PINCONN_PINMODE2 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINMODE2_OFFSET) +#define LPC17_PINCONN_PINMODE3 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINMODE3_OFFSET) +#define LPC17_PINCONN_PINMODE4 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINMODE4_OFFSET) +#define LPC17_PINCONN_PINMODE5 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINMODE5_OFFSET) +#define LPC17_PINCONN_PINMODE6 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINMODE6_OFFSET) +#define LPC17_PINCONN_PINMODE7 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINMODE7_OFFSET) +#define LPC17_PINCONN_PINMODE9 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINMODE9_OFFSET) +#define LPC17_PINCONN_ODMODE0 (LPC17_PINCONN_BASE+LPC17_PINCONN_ODMODE0_OFFSET) +#define LPC17_PINCONN_ODMODE1 (LPC17_PINCONN_BASE+LPC17_PINCONN_ODMODE1_OFFSET) +#define LPC17_PINCONN_ODMODE2 (LPC17_PINCONN_BASE+LPC17_PINCONN_ODMODE2_OFFSET) +#define LPC17_PINCONN_ODMODE3 (LPC17_PINCONN_BASE+LPC17_PINCONN_ODMODE3_OFFSET) +#define LPC17_PINCONN_ODMODE4 (LPC17_PINCONN_BASE+LPC17_PINCONN_ODMODE4_OFFSET) +#define LPC17_PINCONN_I2CPADCFG (LPC17_PINCONN_BASE+LPC17_PINCONN_I2CPADCFG_OFFSET) + +/* Register bit definitions *********************************************************/ +/* Pin Function Select register 0 (PINSEL0: 0x4002c000) */ + +#define PINCONN_PINSEL_GPIO (0) +#define PINCONN_PINSEL_ALT1 (1) +#define PINCONN_PINSEL_ALT2 (2) +#define PINCONN_PINSEL_ALT3 (3) +#define PINCONN_PINSEL_MASK (3) + +#define PINCONN_PINSELL_SHIFT(n) ((n) << 1) /* n=0,1,..,15 */ +#define PINCONN_PINSELL_MASK(n) (3 << PINCONN_PINSELL_SHIFT(n)) +#define PINCONN_PINSELH_SHIFT(n) (((n)-16) << 1) /* n=16,17,..31 */ +#define PINCONN_PINSELH_MASK(n) (3 << PINCONN_PINSELH_SHIFT(n)) + +#define PINCONN_PINSEL0_P0_SHIFT(n) PINCONN_PINSELL_SHIFT(n) /* n=0,1,..,15 */ +#define PINCONN_PINSEL0_P0_MASK(n) PINCONN_PINSELL_MASK(n) /* n=0,1,..,15 */ + +#define PINCONN_PINSEL0_P0p0_SHIFT (0) /* Bits 0-1: P0.0 00=GPIO 01=RD1 10=TXD3 11=SDA1 */ +#define PINCONN_PINSEL0_P0p0_MASK (3 << PINCONN_PINSEL0_P0p0_SHIFT) +#define PINCONN_PINSEL0_P0p1_SHIFT (2) /* Bits 2-3: P0.1 00=GPIO 01=TD1 10=RXD3 11=SCL1 */ +#define PINCONN_PINSEL0_P0p1_MASK (3 << PINCONN_PINSEL0_P0p1_SHIFT) +#define PINCONN_PINSEL0_P0p2_SHIFT (4) /* Bits 4-5: P0.2 00=GPIO 01=TXD0 10=AD0.7 11=Reserved */ +#define PINCONN_PINSEL0_P0p2_MASK (3 << PINCONN_PINSEL0_P0p2_SHIFT) +#define PINCONN_PINSEL0_P0p3_SHIFT (6) /* Bits 6-7: P0.3 00=GPIO 01=RXD0 10=AD0.6 11=Reserved */ +#define PINCONN_PINSEL0_P0p3_MASK (3 << PINCONN_PINSEL0_P0p3_SHIFT) +#define PINCONN_PINSEL0_P0p4_SHIFT (8) /* Bits 8-9: P0.4 00=GPIO 01=I2SRX_CLK 10=RD2 11=CAP2.0 */ +#define PINCONN_PINSEL0_P0p4_MASK (3 << PINCONN_PINSEL0_P0p4_SHIFT) +#define PINCONN_PINSEL0_P0p5_SHIFT (10) /* Bits 10-11: P0.5 00=GPIO 01=I2SRX_WS 10=TD2 11=CAP2.1 */ +#define PINCONN_PINSEL0_P0p5_MASK (3 << PINCONN_PINSEL0_P0p5_SHIFT) +#define PINCONN_PINSEL0_P0p6_SHIFT (12) /* Bits 12-13: P0.6 00=GPIO 01=I2SRX_SDA 10=SSEL1 11=MAT2.0 */ +#define PINCONN_PINSEL0_P0p6_MASK (3 << PINCONN_PINSEL0_P0p6_SHIFT) +#define PINCONN_PINSEL0_P0p7_SHIFT (14) /* Bits 14-15: P0.7 00=GPIO 01=I2STX_CLK 10=SCK1 11=MAT2.1 */ +#define PINCONN_PINSEL0_P0p7_MASK (3 << PINCONN_PINSEL0_P0p7_SHIFT) +#define PINCONN_PINSEL0_P0p8_SHIFT (16) /* Bits 16-17: P0.8 00=GPIO 01=I2STX_WS 10=MISO1 11=MAT2.2 */ +#define PINCONN_PINSEL0_P0p8_MASK (3 << PINCONN_PINSEL0_P0p8_SHIFT) +#define PINCONN_PINSEL0_P0p9_SHIFT (18) /* Bits 18-19: P0.9 00=GPIO 01=I2STX_SDA 10=MOSI1 11=MAT2.3 */ +#define PINCONN_PINSEL0_P0p9_MASK (3 << PINCONN_PINSEL0_P0p9_SHIFT) +#define PINCONN_PINSEL0_P0p10_SHIFT (20) /* Bits 20-21: P0.10 00=GPIO 01=TXD2 10=SDA2 11=MAT3.0 */ +#define PINCONN_PINSEL0_P0p10_MASK (3 << PINCONN_PINSEL0_P0p10_SHIFT) +#define PINCONN_PINSEL0_P0p11_SHIFT (22) /* Bits 22-23: P0.11 00=GPIO 01=RXD2 10=SCL2 11=MAT3.1 */ +#define PINCONN_PINSEL0_P0p11_MASK (3 << PINCONN_PINSEL0_P0p11_SHIFT) + /* Bits 24-29: Reserved */ +#define PINCONN_PINSEL0_P0p15_SHIFT (30) /* Bits 30-31: P0.15 00=GPIO 01=TXD1 10=SCK0 11=SCK */ +#define PINCONN_PINSEL0_P0p15_MASK (3 << PINCONN_PINSEL0_P0p15_SHIFT) + +/* Pin Function Select Register 1 (PINSEL1: 0x4002c004) */ + +#define PINCONN_PINSEL1_P0_SHIFT(n) PINCONN_PINSELH_SHIFT(n) /* n=16,17,..31 */ +#define PINCONN_PINSEL1_P0_MASK(n) PINCONN_PINSELH_MASK(n) /* n=16,17,..31 */ + +#define PINCONN_PINSEL1_P0p16_SHIFT (0) /* Bits 0-1: P0.16 00=GPIO 01=RXD1 10=SSEL0 11=SSEL */ +#define PINCONN_PINSEL1_P0p16_MASK (3 << PINCONN_PINSEL1_P0p16_SHIFT) +#define PINCONN_PINSEL1_P0p17_SHIFT (2) /* Bits 2-3: P0.17 00=GPIO 01=CTS1 10=MISO0 11=MISO */ +#define PINCONN_PINSEL1_P0p17_MASK (3 << PINCONN_PINSEL1_P0p17_SHIFT) +#define PINCONN_PINSEL1_P0p18_SHIFT (4) /* Bits 4-5: P0.18 00=GPIO 01=DCD1 10=MOSI0 11=MOSI */ +#define PINCONN_PINSEL1_P0p18_MASK (3 << PINCONN_PINSEL1_P0p18_SHIFT) +#define PINCONN_PINSEL1_P0p19_SHIFT (6) /* Bits 6-7: P0.19 00=GPIO 01=DSR1 10=Reserved 11=SDA1 */ +#define PINCONN_PINSEL1_P0p19_MASK (3 << PINCONN_PINSEL1_P0p19_SHIFT) +#define PINCONN_PINSEL1_P0p20_SHIFT (8) /* Bits 8-9: P0.20 00=GPIO 01=DTR1 10=Reserved 11=SCL1 */ +#define PINCONN_PINSEL1_P0p20_MASK (3 << PINCONN_PINSEL1_P0p20_SHIFT) +#define PINCONN_PINSEL1_P0p21_SHIFT (10) /* Bits 10-11: P0.21 00=GPIO 01=RI1 10=Reserved 11=RD1 */ +#define PINCONN_PINSEL1_P0p21_MASK (3 << PINCONN_PINSEL1_P0p21_SHIFT) +#define PINCONN_PINSEL1_P0p22_SHIFT (12) /* Bits 12-13: P0.22 00=GPIO 01=RTS1 10=Reserved 11=TD1 */ +#define PINCONN_PINSEL1_P0p22_MASK (3 << PINCONN_PINSEL1_P0p22_SHIFT) +#define PINCONN_PINSEL1_P0p23_SHIFT (14) /* Bits 14-15: P0.23 00=GPIO 01=AD0.0 10=I2SRX_CLK 11=CAP3.0 */ +#define PINCONN_PINSEL1_P0p23_MASK (3 << PINCONN_PINSEL1_P0p23_SHIFT) +#define PINCONN_PINSEL1_P0p24_SHIFT (16) /* Bits 16-17: P0.24 00=GPIO 01=AD0.1 10=I2SRX_WS 11=CAP3.1 */ +#define PINCONN_PINSEL1_P0p24_MASK (3 << PINCONN_PINSEL1_P0p24_SHIFT) +#define PINCONN_PINSEL1_P0p25_SHIFT (18) /* Bits 18-19: P0.25 00=GPIO 01=AD0.2 10=I2SRX_SDA 11=TXD3 */ +#define PINCONN_PINSEL1_P0p25_MASK (3 << PINCONN_PINSEL1_P0p25_SHIFT) +#define PINCONN_PINSEL1_P0p26_SHIFT (20) /* Bits 20-21: P0.26 00=GPIO 01=AD0.3 10=AOUT 11=RXD3 */ +#define PINCONN_PINSEL1_P0p26_MASK (3 << PINCONN_PINSEL1_P0p26_SHIFT) +#define PINCONN_PINSEL1_P0p27_SHIFT (22) /* Bits 22-23: P0.27 00=GPIO 01=SDA0 10=USB_SDA 11=Reserved */ +#define PINCONN_PINSEL1_P0p27_MASK (3 << PINCONN_PINSEL1_P0p27_SHIFT) +#define PINCONN_PINSEL1_P0p28_SHIFT (24) /* Bits 24-25: P0.28 00=GPIO 01=SCL0 10=USB_SCL 11=Reserved */ +#define PINCONN_PINSEL1_P0p28_MASK (3 << PINCONN_PINSEL1_P0p28_SHIFT) +#define PINCONN_PINSEL1_P0p29_SHIFT (26) /* Bits 26-27: P0.29 00=GPIO 01=USB_D+ 10=Reserved 11=Reserved */ +#define PINCONN_PINSEL1_P0p29_MASK (3 << PINCONN_PINSEL1_P0p29_SHIFT) +#define PINCONN_PINSEL1_P0p30_SHIFT (28) /* Bits 28-29: P0.30 00=GPIO 01=USB_D- 10=Reserved 11=Reserved */ +#define PINCONN_PINSEL1_P0p30_MASK (3 << PINCONN_PINSEL1_P0p30_SHIFT) + /* Bits 30-31: Reserved */ +/* Pin Function Select register 2 (PINSEL2: 0x4002c008) */ + +#define PINCONN_PINSEL2_P1_SHIFT(n) PINCONN_PINSELL_SHIFT(n) /* n=0,1,..,15 */ +#define PINCONN_PINSEL2_P1_MASK(n) PINCONN_PINSELL_MASK(n) /* n=0,1,..,15 */ + +#define PINCONN_PINSEL2_P1p0_SHIFT (0) /* Bits 0-1: P1.0 00=GPIO 01=ENET_TXD0 10=Reserved 11=Reserved */ +#define PINCONN_PINSEL2_P1p0_MASK (3 << PINCONN_PINSEL2_P1p0_SHIFT) +#define PINCONN_PINSEL2_P1p1_SHIFT (2) /* Bits 2-3: P1.1 00=GPIO 01=ENET_TXD1 10=Reserved 11=Reserved */ +#define PINCONN_PINSEL2_P1p1_MASK (3 << PINCONN_PINSEL2_P1p1_SHIFT) + /* Bits 4-7: Reserved */ +#define PINCONN_PINSEL2_P1p4_SHIFT (8) /* Bits 8-9: P1.4 00=GPIO 01=ENET_TX_EN 10=Reserved 11=Reserved */ +#define PINCONN_PINSEL2_P1p4_MASK (3 << PINCONN_PINSEL2_P1p4_SHIFT) + /* Bits 10-15: Reserved */ +#define PINCONN_PINSEL2_P1p8_SHIFT (16) /* Bits 16-17: P1.8 00=GPIO 01=ENET_CRS 10=Reserved 11=Reserved */ +#define PINCONN_PINSEL2_P1p8_MASK (3 << PINCONN_PINSEL2_P1p8_SHIFT) +#define PINCONN_PINSEL2_P1p9_SHIFT (18) /* Bits 18-19: P1.9 00=GPIO 01=ENET_RXD0 10=Reserved 11=Reserved */ +#define PINCONN_PINSEL2_P1p9_MASK (3 << PINCONN_PINSEL2_P1p9_SHIFT) +#define PINCONN_PINSEL2_P1p10_SHIFT (20) /* Bits 20-21: P1.10 00=GPIO 01=ENET_RXD1 10=Reserved 11=Reserved */ +#define PINCONN_PINSEL2_P1p10_MASK (3 << PINCONN_PINSEL2_P1p10_SHIFT) + /* Bits 22-27: Reserved */ +#define PINCONN_PINSEL2_P1p14_SHIFT (28) /* Bits 28-29: P1.14 00=GPIO 01=ENET_RX_ER 10=Reserved 11=Reserved */ +#define PINCONN_PINSEL2_P1p14_MASK (3 << PINCONN_PINSEL2_P1p14_SHIFT) +#define PINCONN_PINSEL2_P1p15_SHIFT (30) /* Bits 30-31: P1.15 00=GPIO 01=ENET_REF_CLK 10=Reserved 11=Reserved */ +#define PINCONN_PINSEL2_P1p15_MASK (3 << PINCONN_PINSEL2_P1p15_SHIFT) + +/* Pin Function Select Register 3 (PINSEL3: 0x4002c00c) */ + +#define PINCONN_PINSEL3_P1_SHIFT(n) PINCONN_PINSELH_SHIFT(n) /* n=16,17,..31 */ +#define PINCONN_PINSEL3_P1_MASK(n) PINCONN_PINSELH_MASK(n) /* n=16,17,..31 */ + +#define PINCONN_PINSEL3_P1p16_SHIFT (0) /* Bits 0-1: P1.16 00=GPIO 01=ENET_MDC 10=Reserved 11=Reserved */ +#define PINCONN_PINSEL3_P1p16_MASK (3 << PINCONN_PINSEL3_P1p16_SHIFT) +#define PINCONN_PINSEL3_P1p17_SHIFT (2) /* Bits 2-3: P1.17 00=GPIO 01=ENET_MDIO 10=Reserved 11=Reserved */ +#define PINCONN_PINSEL3_P1p17_MASK (3 << PINCONN_PINSEL3_P1p17_SHIFT) +#define PINCONN_PINSEL3_P1p18_SHIFT (4) /* Bits 4-5: P1.18 00=GPIO 01=USB_UP_LED 10=PWM1.1 11=CAP1.0 */ +#define PINCONN_PINSEL3_P1p18_MASK (3 << PINCONN_PINSEL3_P1p18_SHIFT) +#define PINCONN_PINSEL3_P1p19_SHIFT (6) /* Bits 6-7: P1.19 00=GPIO 01=MCOA0 10=USB_PPWR 11=CAP1.1 */ +#define PINCONN_PINSEL3_P1p19_MASK (3 << PINCONN_PINSEL3_P1p19_SHIFT) +#define PINCONN_PINSEL3_P1p20_SHIFT (8) /* Bits 8-9: P1.20 00=GPIO 01=MCI0 10=PWM1.2 11=SCK0 */ +#define PINCONN_PINSEL3_P1p20_MASK (3 << PINCONN_PINSEL3_P1p20_SHIFT) +#define PINCONN_PINSEL3_P1p21_SHIFT (10) /* Bits 10-11: P1.21 00=GPIO 01=MCABORT 10=PWM1.3 11=SSEL0 */ +#define PINCONN_PINSEL3_P1p21_MASK (3 << PINCONN_PINSEL3_P1p21_SHIFT) +#define PINCONN_PINSEL3_P1p22_SHIFT (12) /* Bits 12-13: P1.22 00=GPIO 01=MCOB0 10=USB_PWRD 11=MAT1.0 */ +#define PINCONN_PINSEL3_P1p22_MASK (3 << PINCONN_PINSEL3_P1p22_SHIFT) +#define PINCONN_PINSEL3_P1p23_SHIFT (14) /* Bits 14-15: P1.23 00=GPIO 01=MCI1 10=PWM1.4 11=MISO0 */ +#define PINCONN_PINSEL3_P1p23_MASK (3 << PINCONN_PINSEL3_P1p23_SHIFT) +#define PINCONN_PINSEL3_P1p24_SHIFT (16) /* Bits 16-17: P1.24 00=GPIO 01=MCI2 10=PWM1.5 11=MOSI0 */ +#define PINCONN_PINSEL3_P1p24_MASK (3 << PINCONN_PINSEL3_P1p24_SHIFT) +#define PINCONN_PINSEL3_P1p25_SHIFT (18) /* Bits 18-19: P1.25 00=GPIO 01=MCOA1 10=Reserved 11=MAT1.1 */ +#define PINCONN_PINSEL3_P1p25_MASK (3 << PINCONN_PINSEL3_P1p25_SHIFT) +#define PINCONN_PINSEL3_P1p26_SHIFT (20) /* Bits 20-21: P1.26 00=GPIO 01=MCOB1 10=PWM1.6 11=CAP0.0 */ +#define PINCONN_PINSEL3_P1p26_MASK (3 << PINCONN_PINSEL3_P1p26_SHIFT) +#define PINCONN_PINSEL3_P1p27_SHIFT (22) /* Bits 22-23: P1.27 00=GPIO 01=CLKOUT 10=USB_OVRCR 11=CAP0.1 */ +#define PINCONN_PINSEL3_P1p27_MASK (3 << PINCONN_PINSEL3_P1p27_SHIFT) +#define PINCONN_PINSEL3_P1p28_SHIFT (24) /* Bits 24-25: P1.28 00=GPIO 01=MCOA2 10=PCAP1.0 11=MAT0.0 */ +#define PINCONN_PINSEL3_P1p28_MASK (3 << PINCONN_PINSEL3_P1p28_SHIFT) +#define PINCONN_PINSEL3_P1p29_SHIFT (26) /* Bits 26-27: P1.29 00=GPIO 01=MCOB2 10=PCAP1.1 11=MAT0.1 */ +#define PINCONN_PINSEL3_P1p29_MASK (3 << PINCONN_PINSEL3_P1p29_SHIFT) +#define PINCONN_PINSEL3_P1p30_SHIFT (28) /* Bits 28-29: P1.30 00=GPIO 01=Reserved 10=VBUS 11=AD0.4 */ +#define PINCONN_PINSEL3_P1p30_MASK (3 << PINCONN_PINSEL3_P1p30_SHIFT) +#define PINCONN_PINSEL3_P1p31_SHIFT (30) /* Bits 30-31: P1.31 00=GPIO 01=Reserved 10=SCK1 11=AD0.5 */ +#define PINCONN_PINSEL3_P1p31_MASK (3 << PINCONN_PINSEL3_P1p31_SHIFT) + +/* Pin Function Select Register 4 (PINSEL4: 0x4002c010) */ + +#define PINCONN_PINSEL4_P2_SHIFT(n) PINCONN_PINSELL_SHIFT(n) /* n=0,1,..,15 */ +#define PINCONN_PINSEL4_P2_MASK(n) PINCONN_PINSELL_MASK(n) /* n=0,1,..,15 */ + +#define PINCONN_PINSEL4_P2p0_SHIFT (0) /* Bits 0-1: P2.0 00=GPIO 01=PWM1.1 10=TXD1 11=Reserved */ +#define PINCONN_PINSEL4_P2p0_MASK (3 << PINCONN_PINSEL4_P2p0_SHIFT) +#define PINCONN_PINSEL4_P2p1_SHIFT (2) /* Bits 2-3: P2.1 00=GPIO 01=PWM1.2 10=RXD1 11=Reserved */ +#define PINCONN_PINSEL4_P2p1_MASK (3 << PINCONN_PINSEL4_P2p1_SHIFT) +#define PINCONN_PINSEL4_P2p2_SHIFT (4) /* Bits 4-5: P2.2 00=GPIO 01=PWM1.3 10=CTS1 11=Reserved */ +#define PINCONN_PINSEL4_P2p2_MASK (3 << PINCONN_PINSEL4_P2p2_SHIFT) +#define PINCONN_PINSEL4_P2p3_SHIFT (6) /* Bits 6-7: P2.3 00=GPIO 01=PWM1.4 10=DCD1 11=Reserved */ +#define PINCONN_PINSEL4_P2p3_MASK (3 << PINCONN_PINSEL4_P2p3_SHIFT) +#define PINCONN_PINSEL4_P2p4_SHIFT (8) /* Bits 8-9: P2.4 00=GPIO 01=PWM1.5 10=DSR1 11=Reserved */ +#define PINCONN_PINSEL4_P2p4_MASK (3 << PINCONN_PINSEL4_P2p4_SHIFT) +#define PINCONN_PINSEL4_P2p5_SHIFT (10) /* Bits 10-11: P2.5 00=GPIO 01=PWM1.6 10=DTR1 11=Reserved */ +#define PINCONN_PINSEL4_P2p5_MASK (3 << PINCONN_PINSEL4_P2p5_SHIFT) +#define PINCONN_PINSEL4_P2p6_SHIFT (12) /* Bits 12-13: P2.6 00=GPIO 01=PCAP1.0 10=RI1 11=Reserved */ +#define PINCONN_PINSEL4_P2p6_MASK (3 << PINCONN_PINSEL4_P2p6_SHIFT) +#define PINCONN_PINSEL4_P2p7_SHIFT (14) /* Bits 14-15: P2.7 00=GPIO 01=RD2 10=RTS1 11=Reserved */ +#define PINCONN_PINSEL4_P2p7_MASK (3 << PINCONN_PINSEL4_P2p7_SHIFT) +#define PINCONN_PINSEL4_P2p8_SHIFT (16) /* Bits 16-17: P2.8 00=GPIO 01=TD2 10=TXD2 11=ENET_MDC */ +#define PINCONN_PINSEL4_P2p8_MASK (3 << PINCONN_PINSEL4_P2p8_SHIFT) +#define PINCONN_PINSEL4_P2p9_SHIFT (18) /* Bits 18-19: P2.9 00=GPIO 01=USB_CONNECT 10=RXD2 11=ENET_MDIO */ +#define PINCONN_PINSEL4_P2p9_MASK (3 << PINCONN_PINSEL4_P2p9_SHIFT) +#define PINCONN_PINSEL4_P2p10_SHIFT (20) /* Bits 20-21: P2.10 00=GPIO 01=EINT0 10=NMI 11=Reserved */ +#define PINCONN_PINSEL4_P2p10_MASK (3 << PINCONN_PINSEL4_P2p10_SHIFT) +#define PINCONN_PINSEL4_P2p11_SHIFT (22) /* Bits 22-23: P2.11 00=GPIO 01=EINT1 10=Reserved 11=I2STX_CLK */ +#define PINCONN_PINSEL4_P2p11_MASK (3 << PINCONN_PINSEL4_P2p11_SHIFT) +#define PINCONN_PINSEL4_P2p12_SHIFT (24) /* Bits 24-25: P2.12 00=GPIO 01=PEINT2 10=Reserved 11=I2STX_WS */ +#define PINCONN_PINSEL4_P2p12_MASK (3 << PINCONN_PINSEL4_P2p12_SHIFT) +#define PINCONN_PINSEL4_P2p13_SHIFT (26) /* Bits 26-27: P2.13 00=GPIO 01=EINT3 10=Reserved 11=I2STX_SDA */ +#define PINCONN_PINSEL4_P2p13_MASK (3 << PINCONN_PINSEL4_P2p13_SHIFT) + /* Bits 28-31: Reserved */ +/* Pin Function Select Register 7 (PINSEL7: 0x4002c01c) */ + +#define PINCONN_PINSEL7_P3_SHIFT(n) PINCONN_PINSELH_SHIFT(n) /* n=16,17,..31 */ +#define PINCONN_PINSEL7_P3_MASK(n) PINCONN_PINSELH_MASK(n) /* n=16,17,..31 */ + + /* Bits 0-17: Reserved */ +#define PINCONN_PINSEL7_P3p25_SHIFT (18) /* Bits 18-19: P3.25 00=GPIO 01=Reserved 10=MAT0.0 11=PWM1.2 */ +#define PINCONN_PINSEL7_P3p25_MASK (3 << PINCONN_PINSEL7_P3p25_SHIFT) +#define PINCONN_PINSEL7_P3p26_SHIFT (20) /* Bits 20-21: P3.26 00=GPIO 01=STCLK 10=MAT0.1 11=PWM1.3 */ +#define PINCONN_PINSEL7_P3p26_MASK (3 << PINCONN_PINSEL7_P3p26_SHIFT) + /* Bits 22-31: Reserved */ + +/* Pin Function Select Register 8 (PINSEL8: 0x4002c020) */ +/* No description of bits -- Does this register exist? */ + +/* Pin Function Select Register 9 (PINSEL9: 0x4002c024) */ + +#define PINCONN_PINSEL9_P4_SHIFT(n) PINCONN_PINSELH_SHIFT(n) /* n=16,17,..31 */ +#define PINCONN_PINSEL9_P4_MASK(n) PINCONN_PINSELH_MASK(n) /* n=16,17,..31 */ + + /* Bits 0-23: Reserved */ +#define PINCONN_PINSEL9_P4p28_SHIFT (24) /* Bits 24-25: P4.28 00=GPIO 01=RX_MCLK 10=MAT2.0 11=TXD3 */ +#define PINCONN_PINSEL9_P4p28_MASK (3 << PINCONN_PINSEL9_P4p28_SHIFT) +#define PINCONN_PINSEL9_P4p29_SHIFT (26) /* Bits 26-27: P4.29 00=GPIO 01=TX_MCLK 10=MAT2.1 11=RXD3 */ +#define PINCONN_PINSEL9_P4p29_MASK (3 << PINCONN_PINSEL9_P4p29_SHIFT) + /* Bits 28-31: Reserved */ +/* Pin Function Select Register 10 (PINSEL10: 0x4002c028) */ + /* Bits 0-2: Reserved */ +#define PINCONN_PINSEL10_TPIU (1 << 3) /* Bit 3: 0=TPIU interface disabled; 1=TPIU interface enabled */ + /* Bits 4-31: Reserved */ +/* Pin Mode select register 0 (PINMODE0: 0x4002c040) */ + +#define PINCONN_PINMODE_PU (0) /* 00: pin has a pull-up resistor enabled */ +#define PINCONN_PINMODE_RM (1) /* 01: pin has repeater mode enabled */ +#define PINCONN_PINMODE_FLOAT (2) /* 10: pin has neither pull-up nor pull-down */ +#define PINCONN_PINMODE_PD (3) /* 11: pin has a pull-down resistor enabled */ +#define PINCONN_PINMODE_MASK (3) + +#define PINCONN_PINMODEL_SHIFT(n) ((n) << 1) /* n=0,1,..,15 */ +#define PINCONN_PINMODEL_MASK(n) (3 << PINCONN_PINMODEL_SHIFT(n)) +#define PINCONN_PINMODEH_SHIFT(n) (((n)-16) << 1) /* n=16,17,..31 */ +#define PINCONN_PINMODEH_MASK(n) (3 << PINCONN_PINMODEH_SHIFT(n)) + +#define PINCONN_PINMODE0_P0_SHIFT(n) PINCONN_PINMODEL_SHIFT(n) /* n=0,1,..,15 */ +#define PINCONN_PINMODE0_P0_MASK(n) PINCONN_PINMODEL_MASK(n) /* n=0,1,..,15 */ + +#define PINCONN_PINMODE0_P0p0_SHIFT (0) /* Bits 0-1: P0.0 mode control */ +#define PINCONN_PINMODE0_P0p0_MASK (3 << PINCONN_PINMODE0_P0p0_SHIFT) +#define PINCONN_PINMODE0_P0p1_SHIFT (2) /* Bits 2-3: P0.1 mode control */ +#define PINCONN_PINMODE0_P0p1_MASK (3 << PINCONN_PINMODE0_P0p1_SHIFT) +#define PINCONN_PINMODE0_P0p2_SHIFT (4) /* Bits 4-5: P0.2 mode control */ +#define PINCONN_PINMODE0_P0p2_MASK (3 << PINCONN_PINMODE0_P0p2_SHIFT) +#define PINCONN_PINMODE0_P0p3_SHIFT (6) /* Bits 6-7: P0.3 mode control */ +#define PINCONN_PINMODE0_P0p3_MASK (3 << PINCONN_PINMODE0_P0p3_SHIFT) +#define PINCONN_PINMODE0_P0p4_SHIFT (8) /* Bits 8-9: P0.4 mode control */ +#define PINCONN_PINMODE0_P0p4_MASK (3 << PINCONN_PINMODE0_P0p4_SHIFT) +#define PINCONN_PINMODE0_P0p5_SHIFT (10) /* Bits 10-11: P0.5 mode control */ +#define PINCONN_PINMODE0_P0p5_MASK (3 << PINCONN_PINMODE0_P0p5_SHIFT) +#define PINCONN_PINMODE0_P0p6_SHIFT (12) /* Bits 12-13: P0.6 mode control */ +#define PINCONN_PINMODE0_P0p6_MASK (3 << PINCONN_PINMODE0_P0p6_SHIFT) +#define PINCONN_PINMODE0_P0p7_SHIFT (14) /* Bits 14-15: P0.7 mode control */ +#define PINCONN_PINMODE0_P0p7_MASK (3 << PINCONN_PINMODE0_P0p7_SHIFT) +#define PINCONN_PINMODE0_P0p8_SHIFT (16) /* Bits 16-17: P0.8 mode control */ +#define PINCONN_PINMODE0_P0p8_MASK (3 << PINCONN_PINMODE0_P0p8_SHIFT) +#define PINCONN_PINMODE0_P0p9_SHIFT (18) /* Bits 18-19: P0.9 mode control */ +#define PINCONN_PINMODE0_P0p9_MASK (3 << PINCONN_PINMODE0_P0p9_SHIFT) +#define PINCONN_PINMODE0_P0p10_SHIFT (20) /* Bits 20-21: P0.10 mode control */ +#define PINCONN_PINMODE0_P0p10_MASK (3 << PINCONN_PINMODE0_P0p10_SHIFT) +#define PINCONN_PINMODE0_P0p11_SHIFT (22) /* Bits 22-23: P0.11 mode control */ +#define PINCONN_PINMODE0_P0p11_MASK (3 << PINCONN_PINMODE0_P0p11_SHIFT) + /* Bits 24-29: Reserved */ +#define PINCONN_PINMODE0_P0p15_SHIFT (30) /* Bits 30-31: P0.15 mode control */ +#define PINCONN_PINMODE0_P0p15_MASK (3 << PINCONN_PINMODE0_P0p15_SHIFT) + +/* Pin Mode select register 1 (PINMODE1: 0x4002c044) */ + +#define PINCONN_PINMODE1_P0_SHIFT(n) PINCONN_PINMODEH_SHIFT(n) /* n=16,17,..31 */ +#define PINCONN_PINMODE1_P0_MASK(n) PINCONN_PINMODEH_MASK(n) /* n=16,17,..31 */ + +#define PINCONN_PINMODE1_P0p16_SHIFT (0) /* Bits 0-1: P0.16 mode control */ +#define PINCONN_PINMODE1_P0p16_MASK (3 << PINCONN_PINMODE1_P0p16_SHIFT) +#define PINCONN_PINMODE1_P0p17_SHIFT (2) /* Bits 2-3: P0.17 mode control */ +#define PINCONN_PINMODE1_P0p17_MASK (3 << PINCONN_PINMODE1_P0p17_SHIFT) +#define PINCONN_PINMODE1_P0p18_SHIFT (4) /* Bits 4-5: P0.18 mode control */ +#define PINCONN_PINMODE1_P0p18_MASK (3 << PINCONN_PINMODE1_P0p18_SHIFT) +#define PINCONN_PINMODE1_P0p19_SHIFT (6) /* Bits 6-7: P0.19 mode control */ +#define PINCONN_PINMODE1_P0p19_MASK (3 << PINCONN_PINMODE1_P0p19_SHIFT) +#define PINCONN_PINMODE1_P0p20_SHIFT (8) /* Bits 8-9: P0.20 mode control */ +#define PINCONN_PINMODE1_P0p20_MASK (3 << PINCONN_PINMODE1_P0p20_SHIFT) +#define PINCONN_PINMODE1_P0p21_SHIFT (10) /* Bits 10-11: P0.21 mode control */ +#define PINCONN_PINMODE1_P0p21_MASK (3 << PINCONN_PINMODE1_P0p21_SHIFT) +#define PINCONN_PINMODE1_P0p22_SHIFT (12) /* Bits 12-13: P0.22 mode control */ +#define PINCONN_PINMODE1_P0p22_MASK (3 << PINCONN_PINMODE1_P0p22_SHIFT) +#define PINCONN_PINMODE1_P0p23_SHIFT (14) /* Bits 14-15: P0.23 mode control */ +#define PINCONN_PINMODE1_P0p23_MASK (3 << PINCONN_PINMODE1_P0p23_SHIFT) +#define PINCONN_PINMODE1_P0p24_SHIFT (16) /* Bits 16-17: P0.24 mode control */ +#define PINCONN_PINMODE1_P0p24_MASK (3 << PINCONN_PINMODE1_P0p24_SHIFT) +#define PINCONN_PINMODE1_P0p25_SHIFT (18) /* Bits 18-19: P0.25 mode control */ +#define PINCONN_PINMODE1_P0p25_MASK (3 << PINCONN_PINMODE1_P0p25_SHIFT) +#define PINCONN_PINMODE1_P0p26_SHIFT (20) /* Bits 20-21: P0.26 mode control */ +#define PINCONN_PINMODE1_P0p26_MASK (3 << PINCONN_PINMODE1_P0p26_SHIFT) + /* Bits 22-31: Reserved */ + +/* Pin Mode select register 2 (PINMODE2: 0x4002c048) */ + +#define PINCONN_PINMODE2_P1_SHIFT(n) PINCONN_PINMODEL_SHIFT(n) /* n=0,1,..,15 */ +#define PINCONN_PINMODE2_P1_MASK(n) PINCONN_PINMODEL_MASK(n) /* n=0,1,..,15 */ + +#define PINCONN_PINMODE2_P1p0_SHIFT (0) /* Bits 2-1: P1.0 mode control */ +#define PINCONN_PINMODE2_P1p0_MASK (3 << PINCONN_PINMODE2_P1p0_SHIFT) +#define PINCONN_PINMODE2_P1p1_SHIFT (2) /* Bits 2-3: P1.1 mode control */ +#define PINCONN_PINMODE2_P1p1_MASK (3 << PINCONN_PINMODE2_P1p1_SHIFT) + /* Bits 4-7: Reserved */ +#define PINCONN_PINMODE2_P1p4_SHIFT (8) /* Bits 8-9: P1.4 mode control */ +#define PINCONN_PINMODE2_P1p4_MASK (3 << PINCONN_PINMODE2_P1p4_SHIFT) + /* Bits 10-15: Reserved */ +#define PINCONN_PINMODE2_P1p8_SHIFT (16) /* Bits 16-17: P1.8 mode control */ +#define PINCONN_PINMODE2_P1p8_MASK (3 << PINCONN_PINMODE2_P1p8_SHIFT) +#define PINCONN_PINMODE2_P1p9_SHIFT (18) /* Bits 18-19: P1.9 mode control */ +#define PINCONN_PINMODE2_P1p9_MASK (3 << PINCONN_PINMODE2_P1p9_SHIFT) +#define PINCONN_PINMODE2_P1p10_SHIFT (20) /* Bits 20-21: P1.10 mode control */ +#define PINCONN_PINMODE2_P1p10_MASK (3 << PINCONN_PINMODE2_P1p10_SHIFT) + /* Bits 22-27: Reserved */ +#define PINCONN_PINMODE2_P1p14_SHIFT (28) /* Bits 28-29: P1.14 mode control */ +#define PINCONN_PINMODE2_P1p14_MASK (3 << PINCONN_PINMODE2_P1p14_SHIFT) +#define PINCONN_PINMODE2_P1p15_SHIFT (30) /* Bits 30-31: P1.15 mode control */ +#define PINCONN_PINMODE2_P1p15_MASK (3 << PINCONN_PINMODE2_P1p15_SHIFT) + +/* Pin Mode select register 3 (PINMODE3: 0x4002c04c) */ + +#define PINCONN_PINMODE3_P1_SHIFT(n) PINCONN_PINMODEH_SHIFT(n) /* n=16,17,..31 */ +#define PINCONN_PINMODE3_P1_MASK(n) PINCONN_PINMODEH_MASK(n) /* n=16,17,..31 */ + +#define PINCONN_PINMODE3_P1p16_SHIFT (0) /* Bits 0-1: P1.16 mode control */ +#define PINCONN_PINMODE3_P1p16_MASK (3 << PINCONN_PINMODE3_P1p16_SHIFT) +#define PINCONN_PINMODE3_P1p17_SHIFT (2) /* Bits 2-3: P1.17 mode control */ +#define PINCONN_PINMODE3_P1p17_MASK (3 << PINCONN_PINMODE3_P1p17_SHIFT) +#define PINCONN_PINMODE3_P1p18_SHIFT (4) /* Bits 4-5: P1.18 mode control */ +#define PINCONN_PINMODE3_P1p18_MASK (3 << PINCONN_PINMODE3_P1p18_SHIFT) +#define PINCONN_PINMODE3_P1p19_SHIFT (6) /* Bits 6-7: P1.19 mode control */ +#define PINCONN_PINMODE3_P1p19_MASK (3 << PINCONN_PINMODE3_P1p19_SHIFT) +#define PINCONN_PINMODE3_P1p20_SHIFT (8) /* Bits 8-9: P1.20 mode control */ +#define PINCONN_PINMODE3_P1p20_MASK (3 << PINCONN_PINMODE3_P1p20_SHIFT) +#define PINCONN_PINMODE3_P1p21_SHIFT (10) /* Bits 10-11: P1.21 mode control */ +#define PINCONN_PINMODE3_P1p21_MASK (3 << PINCONN_PINMODE3_P1p21_SHIFT) +#define PINCONN_PINMODE3_P1p22_SHIFT (12) /* Bits 12-13: P1.22 mode control */ +#define PINCONN_PINMODE3_P1p22_MASK (3 << PINCONN_PINMODE3_P1p22_SHIFT) +#define PINCONN_PINMODE3_P1p23_SHIFT (14) /* Bits 14-15: P1.23 mode control */ +#define PINCONN_PINMODE3_P1p23_MASK (3 << PINCONN_PINMODE3_P1p23_SHIFT) +#define PINCONN_PINMODE3_P1p24_SHIFT (16) /* Bits 16-17: P1.24 mode control */ +#define PINCONN_PINMODE3_P1p24_MASK (3 << PINCONN_PINMODE3_P1p24_SHIFT) +#define PINCONN_PINMODE3_P1p25_SHIFT (18) /* Bits 18-19: P1.25 mode control */ +#define PINCONN_PINMODE3_P1p25_MASK (3 << PINCONN_PINMODE3_P1p25_SHIFT) +#define PINCONN_PINMODE3_P1p26_SHIFT (20) /* Bits 20-21: P1.26 mode control */ +#define PINCONN_PINMODE3_P1p26_MASK (3 << PINCONN_PINMODE3_P1p26_SHIFT) +#define PINCONN_PINMODE3_P1p27_SHIFT (22) /* Bits 22-23: P1.27 mode control */ +#define PINCONN_PINMODE3_P1p27_MASK (3 << PINCONN_PINMODE3_P1p27_SHIFT) +#define PINCONN_PINMODE3_P1p28_SHIFT (24) /* Bits 24-25: P1.28 mode control */ +#define PINCONN_PINMODE3_P1p28_MASK (3 << PINCONN_PINMODE3_P1p28_SHIFT) +#define PINCONN_PINMODE3_P1p29_SHIFT (26) /* Bits 26-27: P1.29 mode control */ +#define PINCONN_PINMODE3_P1p29_MASK (3 << PINCONN_PINMODE3_P1p29_SHIFT) +#define PINCONN_PINMODE3_P1p30_SHIFT (28) /* Bits 28-29: P1.30 mode control */ +#define PINCONN_PINMODE3_P1p30_MASK (3 << PINCONN_PINMODE3_P1p30_SHIFT) +#define PINCONN_PINMODE3_P1p31_SHIFT (30) /* Bits 30-31: P1.31 mode control */ +#define PINCONN_PINMODE3_P1p31_MASK (3 << PINCONN_PINMODE3_P1p31_SHIFT) + +/* Pin Mode select register 4 (PINMODE4: 0x4002c050) */ + +#define PINCONN_PINMODE4_P2_SHIFT(n) PINCONN_PINMODEL_SHIFT(n) /* n=0,1,..,15 */ +#define PINCONN_PINMODE4_P2_MASK(n) PINCONN_PINMODEL_MASK(n) /* n=0,1,..,15 */ + +#define PINCONN_PINMODE4_P2p0_SHIFT (0) /* Bits 0-1: P2.0 mode control */ +#define PINCONN_PINMODE4_P2p0_MASK (3 << PINCONN_PINMODE4_P2p0_SHIFT) +#define PINCONN_PINMODE4_P2p1_SHIFT (2) /* Bits 2-3: P2.1 mode control */ +#define PINCONN_PINMODE4_P2p1_MASK (3 << PINCONN_PINMODE4_P2p1_SHIFT) +#define PINCONN_PINMODE4_P2p2_SHIFT (4) /* Bits 4-5: P2.2 mode control */ +#define PINCONN_PINMODE4_P2p2_MASK (3 << PINCONN_PINMODE4_P2p2_SHIFT) +#define PINCONN_PINMODE4_P2p3_SHIFT (6) /* Bits 6-7: P2.3 mode control */ +#define PINCONN_PINMODE4_P2p3_MASK (3 << PINCONN_PINMODE4_P2p3_SHIFT) +#define PINCONN_PINMODE4_P2p4_SHIFT (8) /* Bits 8-9: P2.4 mode control */ +#define PINCONN_PINMODE4_P2p4_MASK (3 << PINCONN_PINMODE4_P2p4_SHIFT) +#define PINCONN_PINMODE4_P2p5_SHIFT (10) /* Bits 10-11: P2.5 mode control */ +#define PINCONN_PINMODE4_P2p5_MASK (3 << PINCONN_PINMODE4_P2p5_SHIFT) +#define PINCONN_PINMODE4_P2p6_SHIFT (12) /* Bits 12-13: P2.6 mode control */ +#define PINCONN_PINMODE4_P2p6_MASK (3 << PINCONN_PINMODE4_P2p6_SHIFT) +#define PINCONN_PINMODE4_P2p7_SHIFT (14) /* Bits 14-15: P2.7 mode control */ +#define PINCONN_PINMODE4_P2p7_MASK (3 << PINCONN_PINMODE4_P2p7_SHIFT) +#define PINCONN_PINMODE4_P2p8_SHIFT (16) /* Bits 16-17: P2.8 mode control */ +#define PINCONN_PINMODE4_P2p8_MASK (3 << PINCONN_PINMODE4_P2p8_SHIFT) +#define PINCONN_PINMODE4_P2p9_SHIFT (18) /* Bits 18-19: P2.9 mode control */ +#define PINCONN_PINMODE4_P2p9_MASK (3 << PINCONN_PINMODE4_P2p9_SHIFT) +#define PINCONN_PINMODE4_P2p10_SHIFT (20) /* Bits 20-21: P2.10 mode control */ +#define PINCONN_PINMODE4_P2p10_MASK (3 << PINCONN_PINMODE4_P2p10_SHIFT) +#define PINCONN_PINMODE4_P2p11_SHIFT (22) /* Bits 22-23: P2.11 mode control */ +#define PINCONN_PINMODE4_P2p11_MASK (3 << PINCONN_PINMODE4_P2p11_SHIFT) +#define PINCONN_PINMODE4_P2p12_SHIFT (24) /* Bits 24-25: P2.12 mode control */ +#define PINCONN_PINMODE4_P2p12_MASK (3 << PINCONN_PINMODE4_P2p12_SHIFT) +#define PINCONN_PINMODE4_P2p13_SHIFT (26) /* Bits 26-27: P2.13 mode control */ +#define PINCONN_PINMODE4_P2p13_MASK (3 << PINCONN_PINMODE4_P2p13_SHIFT) + /* Bits 28-31: Reserved */ +/* Pin Mode select register 5 (PINMODE5: 0x4002c054) + * Pin Mode select register 6 (PINMODE6: 0x4002c058) + * No bit definitions -- do these registers exist? + */ + +#define PINCONN_PINMODE5_P2_SHIFT(n) PINCONN_PINMODEH_SHIFT(n) /* n=16,17,..31 */ +#define PINCONN_PINMODE5_P2_MASK(n) PINCONN_PINMODEH_MASK(n) /* n=16,17,..31 */ + +#define PINCONN_PINMODE6_P3_SHIFT(n) PINCONN_PINMODEL_SHIFT(n) /* n=0,1,..,15 */ +#define PINCONN_PINMODE6_P3_MASK(n) PINCONN_PINMODEL_MASK(n) /* n=0,1,..,15 */ + +/* Pin Mode select register 7 (PINMODE7: 0x4002c05c) */ + +#define PINCONN_PINMODE7_P3_SHIFT(n) PINCONN_PINMODEH_SHIFT(n) /* n=16,17,..31 */ +#define PINCONN_PINMODE7_P3_MASK(n) PINCONN_PINMODEH_MASK(n) /* n=16,17,..31 */ + /* Bits 0-17: Reserved */ +#define PINCONN_PINMODE7_P3p25_SHIFT (18) /* Bits 18-19: P3.25 mode control */ +#define PINCONN_PINMODE7_P3p25_MASK (3 << PINCONN_PINMODE7_P3p25_SHIFT) +#define PINCONN_PINMODE7_P3p26_SHIFT (20) /* Bits 20-21: P3.26 mode control */ +#define PINCONN_PINMODE7_P3p26_MASK (3 << PINCONN_PINMODE7_P3p26_SHIFT) + /* Bits 22-31: Reserved */ +/* Pin Mode select register 9 (PINMODE9: 0x4002c064) */ + +#define PINCONN_PINMODE9_P4_SHIFT(n) PINCONN_PINMODEH_SHIFT(n) /* n=16,17,..31 */ +#define PINCONN_PINMODE9_P4_MASK(n) PINCONN_PINMODEH_MASK(n) /* n=16,17,..31 */ + /* Bits 0-23: Reserved */ +#define PINCONN_PINMODE9_P4p28_SHIFT (24) /* Bits 24-25: P4.28 mode control */ +#define PINCONN_PINMODE9_P4p28_MASK (3 << PINCONN_PINMODE9_P4p28_SHIFT) +#define PINCONN_PINMODE9_P4p29_SHIFT (26) /* Bits 26-27: P4.29 mode control */ +#define PINCONN_PINMODE9_P4p29_MASK (3 << PINCONN_PINMODE9_P4p29_SHIFT) + /* Bits 28-31: Reserved */ +/* Open Drain Pin Mode select register 0 (PINMODE_OD0: 0x4002c068) */ + +#define PINCONN_ODMODE0_P0(n) (1 << (n)) + +#define PINCONN_ODMODE0_P0p0 (1 << 0) /* Bit 0: P0.0 open drain mode */ +#define PINCONN_ODMODE0_P0p1 (1 << 1) /* Bit 1: P0.1 open drain mode */ +#define PINCONN_ODMODE0_P0p2 (1 << 2) /* Bit 2: P0.2 open drain mode */ +#define PINCONN_ODMODE0_P0p3 (1 << 3) /* Bit 3: P0.3 open drain mode */ +#define PINCONN_ODMODE0_P0p4 (1 << 4) /* Bit 4: P0.4 open drain mode */ +#define PINCONN_ODMODE0_P0p5 (1 << 5) /* Bit 5: P0.5 open drain mode */ +#define PINCONN_ODMODE0_P0p6 (1 << 6) /* Bit 6: P0.6 open drain mode */ +#define PINCONN_ODMODE0_P0p7 (1 << 7) /* Bit 7: P0.7 open drain mode */ +#define PINCONN_ODMODE0_P0p8 (1 << 8) /* Bit 8: P0.8 open drain mode */ +#define PINCONN_ODMODE0_P0p9 (1 << 9) /* Bit 9: P0.9 open drain mode */ +#define PINCONN_ODMODE0_P0p10 (1 << 10) /* Bit 10: P0.10 open drain mode */ +#define PINCONN_ODMODE0_P0p11 (1 << 11) /* Bit 11: P0.11 open drain mode */ + /* Bits 12-14: Reserved */ +#define PINCONN_ODMODE0_P0p15 (1 << 15) /* Bit 15: P0.15 open drain mode */ +#define PINCONN_ODMODE0_P0p16 (1 << 16) /* Bit 16: P0.16 open drain mode */ +#define PINCONN_ODMODE0_P0p17 (1 << 17) /* Bit 17: P0.17 open drain mode */ +#define PINCONN_ODMODE0_P0p18 (1 << 18) /* Bit 18: P0.18 open drain mode */ +#define PINCONN_ODMODE0_P0p19 (1 << 19) /* Bit 19: P0.19 open drain mode */ +#define PINCONN_ODMODE0_P0p20 (1 << 20) /* Bit 20: P0.20 open drain mode */ +#define PINCONN_ODMODE0_P0p21 (1 << 21) /* Bit 21: P0.21 open drain mode */ +#define PINCONN_ODMODE0_P0p22 (1 << 22) /* Bit 22: P0.22 open drain mode */ +#define PINCONN_ODMODE0_P0p23 (1 << 23) /* Bit 23: P0.23 open drain mode */ +#define PINCONN_ODMODE0_P0p24 (1 << 24) /* Bit 24: P0.24 open drain mode */ +#define PINCONN_ODMODE0_P0p25 (1 << 25) /* Bit 25: P0.25 open drain mode */ +#define PINCONN_ODMODE0_P0p26 (1 << 25) /* Bit 26: P0.26 open drain mode */ + /* Bits 27-28: Reserved */ +#define PINCONN_ODMODE0_P0p29 (1 << 29) /* Bit 29: P0.29 open drain mode */ +#define PINCONN_ODMODE0_P0p30 (1 << 30) /* Bit 30: P0.30 open drain mode */ + /* Bit 31: Reserved */ +/* Open Drain Pin Mode select register 1 (PINMODE_OD1: 0x4002c06c) */ + +#define PINCONN_ODMODE1_P1(n) (1 << (n)) + +#define PINCONN_ODMODE1_P1p0 (1 << 0) /* Bit 0: P1.0 open drain mode */ +#define PINCONN_ODMODE1_P1p1 (1 << 1) /* Bit 1: P1.1 open drain mode */ + /* Bits 2-3: Reserved */ +#define PINCONN_ODMODE1_P1p4 (1 << 4) /* Bit 4: P1.4 open drain mode */ + /* Bits 5-7: Reserved */ +#define PINCONN_ODMODE1_P1p8 (1 << 8) /* Bit 8: P1.8 open drain mode */ +#define PINCONN_ODMODE1_P1p9 (1 << 9) /* Bit 9: P1.9 open drain mode */ +#define PINCONN_ODMODE1_P1p10 (1 << 10) /* Bit 10: P1.10 open drain mode */ + /* Bits 11-13: Reserved */ +#define PINCONN_ODMODE1_P1p14 (1 << 14) /* Bit 14: P1.14 open drain mode */ +#define PINCONN_ODMODE1_P1p15 (1 << 15) /* Bit 15: P1.15 open drain mode */ +#define PINCONN_ODMODE1_P1p16 (1 << 16) /* Bit 16: P1.16 open drain mode */ +#define PINCONN_ODMODE1_P1p17 (1 << 17) /* Bit 17: P1.17 open drain mode */ +#define PINCONN_ODMODE1_P1p18 (1 << 18) /* Bit 18: P1.18 open drain mode */ +#define PINCONN_ODMODE1_P1p19 (1 << 19) /* Bit 19: P1.19 open drain mode */ +#define PINCONN_ODMODE1_P1p20 (1 << 20) /* Bit 20: P1.20 open drain mode */ +#define PINCONN_ODMODE1_P1p21 (1 << 21) /* Bit 21: P1.21 open drain mode */ +#define PINCONN_ODMODE1_P1p22 (1 << 22) /* Bit 22: P1.22 open drain mode */ +#define PINCONN_ODMODE1_P1p23 (1 << 23) /* Bit 23: P1.23 open drain mode */ +#define PINCONN_ODMODE1_P1p24 (1 << 24) /* Bit 24: P1.24 open drain mode */ +#define PINCONN_ODMODE1_P1p25 (1 << 25) /* Bit 25: P1.25 open drain mode */ +#define PINCONN_ODMODE1_P1p26 (1 << 25) /* Bit 26: P1.26 open drain mode */ +#define PINCONN_ODMODE1_P1p27 (1 << 27) /* Bit 27: P1.27 open drain mode */ +#define PINCONN_ODMODE1_P1p28 (1 << 28) /* Bit 28: P1.28 open drain mode */ +#define PINCONN_ODMODE1_P1p29 (1 << 29) /* Bit 29: P1.29 open drain mode */ +#define PINCONN_ODMODE1_P1p30 (1 << 30) /* Bit 30: P1.30 open drain mode */ +#define PINCONN_ODMODE1_P1p31 (1 << 31) /* Bit 31: P1.31 open drain mode */ + +/* Open Drain Pin Mode select register 2 (PINMODE_OD2: 0x4002c070) */ + +#define PINCONN_ODMODE2_P2(n) (1 << (n)) + +#define PINCONN_ODMODE2_P2p0 (1 << 0) /* Bit 0: P2.0 open drain mode */ +#define PINCONN_ODMODE2_P2p1 (1 << 1) /* Bit 1: P2.1 open drain mode */ +#define PINCONN_ODMODE2_P2p2 (1 << 2) /* Bit 2: P2.2 open drain mode */ +#define PINCONN_ODMODE2_P2p3 (1 << 3) /* Bit 3: P2.3 open drain mode */ +#define PINCONN_ODMODE2_P2p4 (1 << 4) /* Bit 4: P2.4 open drain mode */ +#define PINCONN_ODMODE2_P2p5 (1 << 5) /* Bit 5: P2.5 open drain mode */ +#define PINCONN_ODMODE2_P2p6 (1 << 6) /* Bit 6: P2.6 open drain mode */ +#define PINCONN_ODMODE2_P2p7 (1 << 7) /* Bit 7: P2.7 open drain mode */ +#define PINCONN_ODMODE2_P2p8 (1 << 8) /* Bit 8: P2.8 open drain mode */ +#define PINCONN_ODMODE2_P2p9 (1 << 9) /* Bit 9: P2.9 open drain mode */ +#define PINCONN_ODMODE2_P2p10 (1 << 10) /* Bit 10: P2.10 open drain mode */ +#define PINCONN_ODMODE2_P2p11 (1 << 11) /* Bit 11: P2.11 open drain mode */ +#define PINCONN_ODMODE2_P2p12 (1 << 12) /* Bit 12: P2.12 open drain mode */ +#define PINCONN_ODMODE2_P2p13 (1 << 13) /* Bit 13: P2.13 open drain mode */ + /* Bits 14-31: Reserved */ +/* Open Drain Pin Mode select register 3 (PINMODE_OD3: 0x4002c074) */ + +#define PINCONN_ODMODE3_P3(n) (1 << (n)) + /* Bits 0-24: Reserved */ +#define PINCONN_ODMODE3_P3p25 (1 << 25) /* Bit 25: P3.25 open drain mode */ +#define PINCONN_ODMODE3_P3p26 (1 << 25) /* Bit 26: P3.26 open drain mode */ + /* Bits 17-31: Reserved */ +/* Open Drain Pin Mode select register 4 (PINMODE_OD4: 0x4002c078) */ + +#define PINCONN_ODMODE4_P4(n) (1 << (n)) + /* Bits 0-27: Reserved */ +#define PINCONN_ODMODE4_P4p28 (1 << 28) /* Bit 28: P4.28 open drain mode */ +#define PINCONN_ODMODE4_P4p29 (1 << 29) /* Bit 29: P4.29 open drain mode */ + /* Bits 30-31: Reserved */ +/* I2C Pin Configuration register (I2CPADCFG: 0x4002c07c) */ + +#define PINCONN_I2CPADCFG_SDADRV0 (1 << 0) /* Bit 0: SDA0 pin, P0.27 in Fast Mode Plus */ +#define PINCONN_I2CPADCFG_SDAI2C0 (1 << 1) /* Bit 1: SDA0 pin, P0.27 I2C glitch + * filtering/slew rate control */ +#define PINCONN_I2CPADCFG_SCLDRV0 (1 << 2) /* Bit 2: SCL0 pin, P0.28 in Fast Mode Plus */ +#define PINCONN_I2CPADCFG_SCLI2C0 (1 << 3) /* Bit 3: SCL0 pin, P0.28 I2C glitch + * filtering/slew rate control */ + /* Bits 4-31: Reserved */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_PINCONN_H */ diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_pwm.h b/nuttx/arch/arm/src/lpc17xx/lpc17_pwm.h index 6db271a47..6555ce616 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_pwm.h +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_pwm.h @@ -1,223 +1,223 @@ -/************************************************************************************
- * arch/arm/src/lpc17xx/lpc17_pwm.h
- *
- * Copyright (C) 2010 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_PWM_H
-#define __ARCH_ARM_SRC_LPC17XX_LPC17_PWM_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-
-#include "chip.h"
-#include "lpc17_memorymap.h"
-
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-
-/* Register offsets *****************************************************************/
-
-#define LPC17_PWM_IR_OFFSET 0x0000 /* Interrupt Register */
-#define LPC17_PWM_TCR_OFFSET 0x0004 /* Timer Control Register */
-#define LPC17_PWM_TC_OFFSET 0x0008 /* Timer Counter */
-#define LPC17_PWM_PR_OFFSET 0x000c /* Prescale Register */
-#define LPC17_PWM_PC_OFFSET 0x0010 /* Prescale Counter */
-#define LPC17_PWM_MCR_OFFSET 0x0014 /* Match Control Register */
-#define LPC17_PWM_MR0_OFFSET 0x0018 /* Match Register 0 */
-#define LPC17_PWM_MR1_OFFSET 0x001c /* Match Register 1 */
-#define LPC17_PWM_MR2_OFFSET 0x0020 /* Match Register 2 */
-#define LPC17_PWM_MR3_OFFSET 0x0024 /* Match Register 3 */
-#define LPC17_PWM_CCR_OFFSET 0x0028 /* Capture Control Register */
-#define LPC17_PWM_CR0_OFFSET 0x002c /* Capture Register 0 */
-#define LPC17_PWM_CR1_OFFSET 0x0030 /* Capture Register 1 */
-#define LPC17_PWM_CR2_OFFSET 0x0034 /* Capture Register 2 */
-#define LPC17_PWM_CR3_OFFSET 0x0038 /* Capture Register 3 */
-#define LPC17_PWM_MR4_OFFSET 0x0040 /* Match Register 4 */
-#define LPC17_PWM_MR5_OFFSET 0x0044 /* Match Register 5 */
-#define LPC17_PWM_MR6_OFFSET 0x0048 /* Match Register 6 */
-#define LPC17_PWM_PCR_OFFSET 0x004c /* PWM Control Register */
-#define LPC17_PWM_LER_OFFSET 0x0050 /* Load Enable Register */
-#define LPC17_PWM_CTCR_OFFSET 0x0070 /* Counter/Timer Control Register */
-
-/* Register addresses ***************************************************************/
-
-#define LPC17_PWM1_IR (LPC17_PWM1_BASE+LPC17_PWM_IR_OFFSET)
-#define LPC17_PWM1_TCR (LPC17_PWM1_BASE+LPC17_PWM_TCR_OFFSET)
-#define LPC17_PWM1_TC (LPC17_PWM1_BASE+LPC17_PWM_TC_OFFSET)
-#define LPC17_PWM1_PR (LPC17_PWM1_BASE+LPC17_PWM_PR_OFFSET)
-#define LPC17_PWM1_PC (LPC17_PWM1_BASE+LPC17_PWM_PC_OFFSET)
-#define LPC17_PWM1_MCR (LPC17_PWM1_BASE+LPC17_PWM_MCR_OFFSET)
-#define LPC17_PWM1_MR0 (LPC17_PWM1_BASE+LPC17_PWM_MR0_OFFSET)
-#define LPC17_PWM1_MR1 (LPC17_PWM1_BASE+LPC17_PWM_MR1_OFFSET)
-#define LPC17_PWM1_MR2 (LPC17_PWM1_BASE+LPC17_PWM_MR2_OFFSET)
-#define LPC17_PWM1_MR3 (LPC17_PWM1_BASE+LPC17_PWM_MR3_OFFSET)
-#define LPC17_PWM1_MR4 (LPC17_PWM1_BASE+LPC17_PWM_MR4_OFFSET)
-#define LPC17_PWM1_MR5 (LPC17_PWM1_BASE+LPC17_PWM_MR5_OFFSET)
-#define LPC17_PWM1_MR6 (LPC17_PWM1_BASE+LPC17_PWM_MR6_OFFSET)
-#define LPC17_PWM1_CCR (LPC17_PWM1_BASE+LPC17_PWM_CCR_OFFSET)
-#define LPC17_PWM1_CR0 (LPC17_PWM1_BASE+LPC17_PWM_CR0_OFFSET)
-#define LPC17_PWM1_CR1 (LPC17_PWM1_BASE+LPC17_PWM_CR1_OFFSET)
-#define LPC17_PWM1_CR2 (LPC17_PWM1_BASE+LPC17_PWM_CR2_OFFSET)
-#define LPC17_PWM1_CR3 (LPC17_PWM1_BASE+LPC17_PWM_CR3_OFFSET)
-#define LPC17_PWM1_PCR (LPC17_PWM1_BASE+LPC17_PWM_PCR_OFFSET)
-#define LPC17_PWM1_LER (LPC17_PWM1_BASE+LPC17_PWM_LER_OFFSET)
-#define LPC17_PWM1_CTCR (LPC17_PWM1_BASE+LPC17_PWM_CTCR_OFFSET)
-
-/* Register bit definitions *********************************************************/
-/* Registers holding 32-bit numeric values (no bit field definitions):
- *
- * Timer Counter (TC)
- * Prescale Register (PR)
- * Prescale Counter (PC)
- * Match Register 0 (MR0)
- * Match Register 1 (MR1)
- * Match Register 2 (MR2)
- * Match Register 3 (MR3)
- * Match Register 4 (MR3)
- * Match Register 5 (MR3)
- * Match Register 6 (MR3)
- * Capture Register 0 (CR0)
- * Capture Register 1 (CR1)
- * Capture Register 1 (CR2)
- * Capture Register 1 (CR3)
- */
-
-/* Interrupt Register */
-
-#define PWM_IR_MR0 (1 << 0) /* Bit 0: PWM match channel 0 interrrupt */
-#define PWM_IR_MR1 (1 << 1) /* Bit 1: PWM match channel 1 interrrupt */
-#define PWM_IR_MR2 (1 << 2) /* Bit 2: PWM match channel 2 interrrupt */
-#define PWM_IR_MR3 (1 << 3) /* Bit 3: PWM match channel 3 interrrupt */
-#define PWM_IR_CAP0 (1 << 4) /* Bit 4: Capture input 0 interrrupt */
-#define PWM_IR_CAP1 (1 << 5) /* Bit 5: Capture input 1 interrrupt */
- /* Bits 6-7: Reserved */
-#define PWM_IR_MR4 (1 << 8) /* Bit 8: PWM match channel 4 interrrupt */
-#define PWM_IR_MR5 (1 << 9) /* Bit 9: PWM match channel 5 interrrupt */
-#define PWM_IR_MR6 (1 << 10) /* Bit 10: PWM match channel 6 interrrupt */
- /* Bits 11-31: Reserved */
-/* Timer Control Register */
-
-#define PWM_TCR_CNTREN (1 << 0) /* Bit 0: Counter Enable */
-#define PWM_TCR_CNTRRST (1 << 1) /* Bit 1: Counter Reset */
- /* Bit 2: Reserved */
-#define PWM_TCR_PWMEN (1 << 3) /* Bit 3: PWM Enable */
- /* Bits 4-31: Reserved */
-/* Match Control Register */
-
-#define PWM_MCR_MR0I (1 << 0) /* Bit 0: Interrupt on MR0 */
-#define PWM_MCR_MR0R (1 << 1) /* Bit 1: Reset on MR0 */
-#define PWM_MCR_MR0S (1 << 2) /* Bit 2: Stop on MR0 */
-#define PWM_MCR_MR1I (1 << 3) /* Bit 3: Interrupt on MR1 */
-#define PWM_MCR_MR1R (1 << 4) /* Bit 4: Reset on MR1 */
-#define PWM_MCR_MR1S (1 << 5) /* Bit 5: Stop on MR1 */
-#define PWM_MCR_MR2I (1 << 6) /* Bit 6: Interrupt on MR2 */
-#define PWM_MCR_MR2R (1 << 7) /* Bit 7: Reset on MR2 */
-#define PWM_MCR_MR2S (1 << 8) /* Bit 8: Stop on MR2 */
-#define PWM_MCR_MR3I (1 << 9) /* Bit 9: Interrupt on MR3 */
-#define PWM_MCR_MR3R (1 << 10) /* Bit 10: Reset on MR3 */
-#define PWM_MCR_MR3S (1 << 11) /* Bit 11: Stop on MR3 */
-#define PWM_MCR_MR4I (1 << 12) /* Bit 12: Interrupt on MR4 */
-#define PWM_MCR_MR4R (1 << 13) /* Bit 13: Reset on MR4 */
-#define PWM_MCR_MR4S (1 << 14) /* Bit 14: Stop on MR4 */
-#define PWM_MCR_MR5I (1 << 15) /* Bit 15: Interrupt on MR5 */
-#define PWM_MCR_MR5R (1 << 16) /* Bit 16: Reset on MR5*/
-#define PWM_MCR_MR5S (1 << 17) /* Bit 17: Stop on MR5 */
-#define PWM_MCR_MR6I (1 << 18) /* Bit 18: Interrupt on MR6 */
-#define PWM_MCR_MR6R (1 << 19) /* Bit 19: Reset on MR6 */
-#define PWM_MCR_MR6S (1 << 20) /* Bit 20: Stop on MR6 */
- /* Bits 21-31: Reserved */
-/* Capture Control Register (Where are CAP2 and 3?) */
-
-#define PWM_CCR_CAP0RE (1 << 0) /* Bit 0: Capture on CAPn.0 rising edge */
-#define PWM_CCR_CAP0FE (1 << 1) /* Bit 1: Capture on CAPn.0 falling edg */
-#define PWM_CCR_CAP0I (1 << 2) /* Bit 2: Interrupt on CAPn.0 */
-#define PWM_CCR_CAP1RE (1 << 3) /* Bit 3: Capture on CAPn.1 rising edge */
-#define PWM_CCR_CAP1FE (1 << 4) /* Bit 4: Capture on CAPn.1 falling edg */
-#define PWM_CCR_CAP1I (1 << 5) /* Bit 5: Interrupt on CAPn.1 */
- /* Bits 6-31: Reserved */
-/* PWM Control Register */
- /* Bits 0-1: Reserved */
-#define PWM_PCR_SEL2 (1 << 2) /* Bit 2: PWM2 single edge controlled mode */
-#define PWM_PCR_SEL3 (1 << 3) /* Bit 3: PWM3 single edge controlled mode */
-#define PWM_PCR_SEL4 (1 << 4) /* Bit 4: PWM4 single edge controlled mode */
-#define PWM_PCR_SEL5 (1 << 5) /* Bit 5: PWM5 single edge controlled mode */
-#define PWM_PCR_SEL6 (1 << 6) /* Bit 6: PWM6 single edge controlled mode */
- /* Bits 7-8: Reserved */
-#define PWM_PCR_ENA1 (1 << 9) /* Bit 9: Enable PWM1 output */
-#define PWM_PCR_ENA2 (1 << 10) /* Bit 10: Enable PWM2 output */
-#define PWM_PCR_ENA3 (1 << 11) /* Bit 11: Enable PWM3 output */
-#define PWM_PCR_ENA4 (1 << 12) /* Bit 12: Enable PWM4 output */
-#define PWM_PCR_ENA5 (1 << 13) /* Bit 13: Enable PWM5 output */
-#define PWM_PCR_ENA6 (1 << 14) /* Bit 14: Enable PWM6 output */
- /* Bits 15-31: Reserved */
-/* Load Enable Register */
-
-#define PWM_LER_M0EN (1 << 0) /* Bit 0: Enable PWM Match 0 Latch */
-#define PWM_LER_M1EN (1 << 1) /* Bit 1: Enable PWM Match 1 Latch */
-#define PWM_LER_M2EN (1 << 2) /* Bit 2: Enable PWM Match 2 Latch */
-#define PWM_LER_M3EN (1 << 3) /* Bit 3: Enable PWM Match 3 Latch */
-#define PWM_LER_M4EN (1 << 4) /* Bit 4: Enable PWM Match 4 Latch */
-#define PWM_LER_M5EN (1 << 5) /* Bit 5: Enable PWM Match 5 Latch */
-#define PWM_LER_M6EN (1 << 6) /* Bit 6: Enable PWM Match 6 Latch */
- /* Bits 7-31: Reserved */
-/* Counter/Timer Control Register */
-
-#define PWM_CTCR_MODE_SHIFT (0) /* Bits 0-1: Counter/Timer Mode */
-#define PWM_CTCR_MODE_MASK (3 << PWM_CTCR_MODE_SHIFT)
-# define PWM_CTCR_MODE_TIMER (0 << PWM_CTCR_MODE_SHIFT) /* Timer Mode, prescal match */
-# define PWM_CTCR_MODE_CNTRRE (1 << PWM_CTCR_MODE_SHIFT) /* Counter Mode, CAP rising edge */
-# define PWM_CTCR_MODE_CNTRFE (2 << PWM_CTCR_MODE_SHIFT) /* Counter Mode, CAP falling edge */
-# define PWM_CTCR_MODE_CNTRBE (3 << PWM_CTCR_MODE_SHIFT) /* Counter Mode, CAP both edges */
-#define PWM_CTCR_INPSEL_SHIFT (2) /* Bits 2-3: Count Input Select */
-#define PWM_CTCR_INPSEL_MASK (3 << PWM_CTCR_INPSEL_SHIFT)
-# define PWM_CTCR_INPSEL_CAPNp0 (0 << PWM_CTCR_INPSEL_SHIFT) /* CAPn.0 for TIMERn */
-# define PWM_CTCR_INPSEL_CAPNp1 (1 << PWM_CTCR_INPSEL_SHIFT) /* CAPn.0 for TIMERn */
- /* Bits 4-31: Reserved */
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-/************************************************************************************
- * Public Functions
- ************************************************************************************/
-
-#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_PWM_H */
+/************************************************************************************ + * arch/arm/src/lpc17xx/lpc17_pwm.h + * + * Copyright (C) 2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_PWM_H +#define __ARCH_ARM_SRC_LPC17XX_LPC17_PWM_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +#include "chip.h" +#include "lpc17_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register offsets *****************************************************************/ + +#define LPC17_PWM_IR_OFFSET 0x0000 /* Interrupt Register */ +#define LPC17_PWM_TCR_OFFSET 0x0004 /* Timer Control Register */ +#define LPC17_PWM_TC_OFFSET 0x0008 /* Timer Counter */ +#define LPC17_PWM_PR_OFFSET 0x000c /* Prescale Register */ +#define LPC17_PWM_PC_OFFSET 0x0010 /* Prescale Counter */ +#define LPC17_PWM_MCR_OFFSET 0x0014 /* Match Control Register */ +#define LPC17_PWM_MR0_OFFSET 0x0018 /* Match Register 0 */ +#define LPC17_PWM_MR1_OFFSET 0x001c /* Match Register 1 */ +#define LPC17_PWM_MR2_OFFSET 0x0020 /* Match Register 2 */ +#define LPC17_PWM_MR3_OFFSET 0x0024 /* Match Register 3 */ +#define LPC17_PWM_CCR_OFFSET 0x0028 /* Capture Control Register */ +#define LPC17_PWM_CR0_OFFSET 0x002c /* Capture Register 0 */ +#define LPC17_PWM_CR1_OFFSET 0x0030 /* Capture Register 1 */ +#define LPC17_PWM_CR2_OFFSET 0x0034 /* Capture Register 2 */ +#define LPC17_PWM_CR3_OFFSET 0x0038 /* Capture Register 3 */ +#define LPC17_PWM_MR4_OFFSET 0x0040 /* Match Register 4 */ +#define LPC17_PWM_MR5_OFFSET 0x0044 /* Match Register 5 */ +#define LPC17_PWM_MR6_OFFSET 0x0048 /* Match Register 6 */ +#define LPC17_PWM_PCR_OFFSET 0x004c /* PWM Control Register */ +#define LPC17_PWM_LER_OFFSET 0x0050 /* Load Enable Register */ +#define LPC17_PWM_CTCR_OFFSET 0x0070 /* Counter/Timer Control Register */ + +/* Register addresses ***************************************************************/ + +#define LPC17_PWM1_IR (LPC17_PWM1_BASE+LPC17_PWM_IR_OFFSET) +#define LPC17_PWM1_TCR (LPC17_PWM1_BASE+LPC17_PWM_TCR_OFFSET) +#define LPC17_PWM1_TC (LPC17_PWM1_BASE+LPC17_PWM_TC_OFFSET) +#define LPC17_PWM1_PR (LPC17_PWM1_BASE+LPC17_PWM_PR_OFFSET) +#define LPC17_PWM1_PC (LPC17_PWM1_BASE+LPC17_PWM_PC_OFFSET) +#define LPC17_PWM1_MCR (LPC17_PWM1_BASE+LPC17_PWM_MCR_OFFSET) +#define LPC17_PWM1_MR0 (LPC17_PWM1_BASE+LPC17_PWM_MR0_OFFSET) +#define LPC17_PWM1_MR1 (LPC17_PWM1_BASE+LPC17_PWM_MR1_OFFSET) +#define LPC17_PWM1_MR2 (LPC17_PWM1_BASE+LPC17_PWM_MR2_OFFSET) +#define LPC17_PWM1_MR3 (LPC17_PWM1_BASE+LPC17_PWM_MR3_OFFSET) +#define LPC17_PWM1_MR4 (LPC17_PWM1_BASE+LPC17_PWM_MR4_OFFSET) +#define LPC17_PWM1_MR5 (LPC17_PWM1_BASE+LPC17_PWM_MR5_OFFSET) +#define LPC17_PWM1_MR6 (LPC17_PWM1_BASE+LPC17_PWM_MR6_OFFSET) +#define LPC17_PWM1_CCR (LPC17_PWM1_BASE+LPC17_PWM_CCR_OFFSET) +#define LPC17_PWM1_CR0 (LPC17_PWM1_BASE+LPC17_PWM_CR0_OFFSET) +#define LPC17_PWM1_CR1 (LPC17_PWM1_BASE+LPC17_PWM_CR1_OFFSET) +#define LPC17_PWM1_CR2 (LPC17_PWM1_BASE+LPC17_PWM_CR2_OFFSET) +#define LPC17_PWM1_CR3 (LPC17_PWM1_BASE+LPC17_PWM_CR3_OFFSET) +#define LPC17_PWM1_PCR (LPC17_PWM1_BASE+LPC17_PWM_PCR_OFFSET) +#define LPC17_PWM1_LER (LPC17_PWM1_BASE+LPC17_PWM_LER_OFFSET) +#define LPC17_PWM1_CTCR (LPC17_PWM1_BASE+LPC17_PWM_CTCR_OFFSET) + +/* Register bit definitions *********************************************************/ +/* Registers holding 32-bit numeric values (no bit field definitions): + * + * Timer Counter (TC) + * Prescale Register (PR) + * Prescale Counter (PC) + * Match Register 0 (MR0) + * Match Register 1 (MR1) + * Match Register 2 (MR2) + * Match Register 3 (MR3) + * Match Register 4 (MR3) + * Match Register 5 (MR3) + * Match Register 6 (MR3) + * Capture Register 0 (CR0) + * Capture Register 1 (CR1) + * Capture Register 1 (CR2) + * Capture Register 1 (CR3) + */ + +/* Interrupt Register */ + +#define PWM_IR_MR0 (1 << 0) /* Bit 0: PWM match channel 0 interrrupt */ +#define PWM_IR_MR1 (1 << 1) /* Bit 1: PWM match channel 1 interrrupt */ +#define PWM_IR_MR2 (1 << 2) /* Bit 2: PWM match channel 2 interrrupt */ +#define PWM_IR_MR3 (1 << 3) /* Bit 3: PWM match channel 3 interrrupt */ +#define PWM_IR_CAP0 (1 << 4) /* Bit 4: Capture input 0 interrrupt */ +#define PWM_IR_CAP1 (1 << 5) /* Bit 5: Capture input 1 interrrupt */ + /* Bits 6-7: Reserved */ +#define PWM_IR_MR4 (1 << 8) /* Bit 8: PWM match channel 4 interrrupt */ +#define PWM_IR_MR5 (1 << 9) /* Bit 9: PWM match channel 5 interrrupt */ +#define PWM_IR_MR6 (1 << 10) /* Bit 10: PWM match channel 6 interrrupt */ + /* Bits 11-31: Reserved */ +/* Timer Control Register */ + +#define PWM_TCR_CNTREN (1 << 0) /* Bit 0: Counter Enable */ +#define PWM_TCR_CNTRRST (1 << 1) /* Bit 1: Counter Reset */ + /* Bit 2: Reserved */ +#define PWM_TCR_PWMEN (1 << 3) /* Bit 3: PWM Enable */ + /* Bits 4-31: Reserved */ +/* Match Control Register */ + +#define PWM_MCR_MR0I (1 << 0) /* Bit 0: Interrupt on MR0 */ +#define PWM_MCR_MR0R (1 << 1) /* Bit 1: Reset on MR0 */ +#define PWM_MCR_MR0S (1 << 2) /* Bit 2: Stop on MR0 */ +#define PWM_MCR_MR1I (1 << 3) /* Bit 3: Interrupt on MR1 */ +#define PWM_MCR_MR1R (1 << 4) /* Bit 4: Reset on MR1 */ +#define PWM_MCR_MR1S (1 << 5) /* Bit 5: Stop on MR1 */ +#define PWM_MCR_MR2I (1 << 6) /* Bit 6: Interrupt on MR2 */ +#define PWM_MCR_MR2R (1 << 7) /* Bit 7: Reset on MR2 */ +#define PWM_MCR_MR2S (1 << 8) /* Bit 8: Stop on MR2 */ +#define PWM_MCR_MR3I (1 << 9) /* Bit 9: Interrupt on MR3 */ +#define PWM_MCR_MR3R (1 << 10) /* Bit 10: Reset on MR3 */ +#define PWM_MCR_MR3S (1 << 11) /* Bit 11: Stop on MR3 */ +#define PWM_MCR_MR4I (1 << 12) /* Bit 12: Interrupt on MR4 */ +#define PWM_MCR_MR4R (1 << 13) /* Bit 13: Reset on MR4 */ +#define PWM_MCR_MR4S (1 << 14) /* Bit 14: Stop on MR4 */ +#define PWM_MCR_MR5I (1 << 15) /* Bit 15: Interrupt on MR5 */ +#define PWM_MCR_MR5R (1 << 16) /* Bit 16: Reset on MR5*/ +#define PWM_MCR_MR5S (1 << 17) /* Bit 17: Stop on MR5 */ +#define PWM_MCR_MR6I (1 << 18) /* Bit 18: Interrupt on MR6 */ +#define PWM_MCR_MR6R (1 << 19) /* Bit 19: Reset on MR6 */ +#define PWM_MCR_MR6S (1 << 20) /* Bit 20: Stop on MR6 */ + /* Bits 21-31: Reserved */ +/* Capture Control Register (Where are CAP2 and 3?) */ + +#define PWM_CCR_CAP0RE (1 << 0) /* Bit 0: Capture on CAPn.0 rising edge */ +#define PWM_CCR_CAP0FE (1 << 1) /* Bit 1: Capture on CAPn.0 falling edg */ +#define PWM_CCR_CAP0I (1 << 2) /* Bit 2: Interrupt on CAPn.0 */ +#define PWM_CCR_CAP1RE (1 << 3) /* Bit 3: Capture on CAPn.1 rising edge */ +#define PWM_CCR_CAP1FE (1 << 4) /* Bit 4: Capture on CAPn.1 falling edg */ +#define PWM_CCR_CAP1I (1 << 5) /* Bit 5: Interrupt on CAPn.1 */ + /* Bits 6-31: Reserved */ +/* PWM Control Register */ + /* Bits 0-1: Reserved */ +#define PWM_PCR_SEL2 (1 << 2) /* Bit 2: PWM2 single edge controlled mode */ +#define PWM_PCR_SEL3 (1 << 3) /* Bit 3: PWM3 single edge controlled mode */ +#define PWM_PCR_SEL4 (1 << 4) /* Bit 4: PWM4 single edge controlled mode */ +#define PWM_PCR_SEL5 (1 << 5) /* Bit 5: PWM5 single edge controlled mode */ +#define PWM_PCR_SEL6 (1 << 6) /* Bit 6: PWM6 single edge controlled mode */ + /* Bits 7-8: Reserved */ +#define PWM_PCR_ENA1 (1 << 9) /* Bit 9: Enable PWM1 output */ +#define PWM_PCR_ENA2 (1 << 10) /* Bit 10: Enable PWM2 output */ +#define PWM_PCR_ENA3 (1 << 11) /* Bit 11: Enable PWM3 output */ +#define PWM_PCR_ENA4 (1 << 12) /* Bit 12: Enable PWM4 output */ +#define PWM_PCR_ENA5 (1 << 13) /* Bit 13: Enable PWM5 output */ +#define PWM_PCR_ENA6 (1 << 14) /* Bit 14: Enable PWM6 output */ + /* Bits 15-31: Reserved */ +/* Load Enable Register */ + +#define PWM_LER_M0EN (1 << 0) /* Bit 0: Enable PWM Match 0 Latch */ +#define PWM_LER_M1EN (1 << 1) /* Bit 1: Enable PWM Match 1 Latch */ +#define PWM_LER_M2EN (1 << 2) /* Bit 2: Enable PWM Match 2 Latch */ +#define PWM_LER_M3EN (1 << 3) /* Bit 3: Enable PWM Match 3 Latch */ +#define PWM_LER_M4EN (1 << 4) /* Bit 4: Enable PWM Match 4 Latch */ +#define PWM_LER_M5EN (1 << 5) /* Bit 5: Enable PWM Match 5 Latch */ +#define PWM_LER_M6EN (1 << 6) /* Bit 6: Enable PWM Match 6 Latch */ + /* Bits 7-31: Reserved */ +/* Counter/Timer Control Register */ + +#define PWM_CTCR_MODE_SHIFT (0) /* Bits 0-1: Counter/Timer Mode */ +#define PWM_CTCR_MODE_MASK (3 << PWM_CTCR_MODE_SHIFT) +# define PWM_CTCR_MODE_TIMER (0 << PWM_CTCR_MODE_SHIFT) /* Timer Mode, prescal match */ +# define PWM_CTCR_MODE_CNTRRE (1 << PWM_CTCR_MODE_SHIFT) /* Counter Mode, CAP rising edge */ +# define PWM_CTCR_MODE_CNTRFE (2 << PWM_CTCR_MODE_SHIFT) /* Counter Mode, CAP falling edge */ +# define PWM_CTCR_MODE_CNTRBE (3 << PWM_CTCR_MODE_SHIFT) /* Counter Mode, CAP both edges */ +#define PWM_CTCR_INPSEL_SHIFT (2) /* Bits 2-3: Count Input Select */ +#define PWM_CTCR_INPSEL_MASK (3 << PWM_CTCR_INPSEL_SHIFT) +# define PWM_CTCR_INPSEL_CAPNp0 (0 << PWM_CTCR_INPSEL_SHIFT) /* CAPn.0 for TIMERn */ +# define PWM_CTCR_INPSEL_CAPNp1 (1 << PWM_CTCR_INPSEL_SHIFT) /* CAPn.0 for TIMERn */ + /* Bits 4-31: Reserved */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_PWM_H */ diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_qei.h b/nuttx/arch/arm/src/lpc17xx/lpc17_qei.h index 2c37051b1..d1637f943 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_qei.h +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_qei.h @@ -1,190 +1,190 @@ -/************************************************************************************
- * arch/arm/src/lpc17xx/lpc17_qei.h
- *
- * Copyright (C) 2010 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_QEI_H
-#define __ARCH_ARM_SRC_LPC17XX_LPC17_QEI_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-
-#include "chip.h"
-#include "lpc17_memorymap.h"
-
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-
-/* Register offsets *****************************************************************/
-/* Control registers */
-
-#define LPC17_QEI_CON_OFFSET 0x0000 /* Control register */
-#define LPC17_QEI_STAT_OFFSET 0x0004 /* Encoder status register */
-#define LPC17_QEI_CONF_OFFSET 0x0008 /* Configuration register */
-
-/* Position, index, and timer registers */
-
-#define LPC17_QEI_POS_OFFSET 0x000c /* Position register */
-#define LPC17_QEI_MAXPOS_OFFSET 0x0010 /* Maximum position register */
-#define LPC17_QEI_CMPOS0_OFFSET 0x0014 /* Position compare register */
-#define LPC17_QEI_CMPOS1_OFFSET 0x0018 /* Position compare register */
-#define LPC17_QEI_CMPOS2_OFFSET 0x001c /* Position compare register */
-#define LPC17_QEI_INXCNT_OFFSET 0x0020 /* Index count register */
-#define LPC17_QEI_INXCMP_OFFSET 0x0024 /* Index compare register */
-#define LPC17_QEI_LOAD_OFFSET 0x0028 /* Velocity timer reload register */
-#define LPC17_QEI_TIME_OFFSET 0x002c /* Velocity timer register */
-#define LPC17_QEI_VEL_OFFSET 0x0030 /* Velocity counter register */
-#define LPC17_QEI_CAP_OFFSET 0x0034 /* Velocity capture register */
-#define LPC17_QEI_VELCOMP_OFFSET 0x0038 /* Velocity compare register */
-#define LPC17_QEI_FILTER_OFFSET 0x003c /* Digital filter register */
-
-/* Interrupt registers */
-
-#define LPC17_QEI_IEC_OFFSET 0x0fd8 /* Interrupt enable clear register */
-#define LPC17_QEI_IES_OFFSET 0x0fdc /* Interrupt enable set register */
-#define LPC17_QEI_INTSTAT_OFFSET 0x0fe0 /* Interrupt status register */
-#define LPC17_QEI_IE_OFFSET 0x0fe4 /* Interrupt enable register */
-#define LPC17_QEI_CLR_OFFSET 0x0fe8 /* Interrupt status clear register */
-#define LPC17_QEI_SET_OFFSET 0x0fec /* Interrupt status set register */
-
-/* Register addresses ***************************************************************/
-/* Control registers */
-
-#define LPC17_QEI_CON (LPC17_QEI_BASE+LPC17_QEI_CON_OFFSET)
-#define LPC17_QEI_STAT (LPC17_QEI_BASE+LPC17_QEI_STAT_OFFSET)
-#define LPC17_QEI_CONF (LPC17_QEI_BASE+LPC17_QEI_CONF_OFFSET)
-
-/* Position, index, and timer registers */
-
-#define LPC17_QEI_POS (LPC17_QEI_BASE+LPC17_QEI_POS_OFFSET)
-#define LPC17_QEI_MAXPOS (LPC17_QEI_BASE+LPC17_QEI_MAXPOS_OFFSET)
-#define LPC17_QEI_CMPOS0 (LPC17_QEI_BASE+LPC17_QEI_CMPOS0_OFFSET)
-#define LPC17_QEI_CMPOS1 (LPC17_QEI_BASE+LPC17_QEI_CMPOS1_OFFSET)
-#define LPC17_QEI_CMPOS2 (LPC17_QEI_BASE+LPC17_QEI_CMPOS2_OFFSET)
-#define LPC17_QEI_INXCNT (LPC17_QEI_BASE+LPC17_QEI_INXCNT_OFFSET)
-#define LPC17_QEI_INXCMP (LPC17_QEI_BASE+LPC17_QEI_INXCMP_OFFSET)
-#define LPC17_QEI_LOAD (LPC17_QEI_BASE+LPC17_QEI_LOAD_OFFSET)
-#define LPC17_QEI_TIME (LPC17_QEI_BASE+LPC17_QEI_TIME_OFFSET)
-#define LPC17_QEI_VEL (LPC17_QEI_BASE+LPC17_QEI_VEL_OFFSET)
-#define LPC17_QEI_CAP (LPC17_QEI_BASE+LPC17_QEI_CAP_OFFSET)
-#define LPC17_QEI_VELCOMP (LPC17_QEI_BASE+LPC17_QEI_VELCOMP_OFFSET)
-#define LPC17_QEI_FILTER (LPC17_QEI_BASE+LPC17_QEI_FILTER_OFFSET)
-
-/* Interrupt registers */
-
-#define LPC17_QEI_IEC (LPC17_QEI_BASE+LPC17_QEI_IEC_OFFSET)
-#define LPC17_QEI_IES (LPC17_QEI_BASE+LPC17_QEI_IES_OFFSET)
-#define LPC17_QEI_INTSTAT (LPC17_QEI_BASE+LPC17_QEI_INTSTAT_OFFSET)
-#define LPC17_QEI_IE (LPC17_QEI_BASE+LPC17_QEI_IE_OFFSET)
-#define LPC17_QEI_CLR (LPC17_QEI_BASE+LPC17_QEI_CLR_OFFSET)
-#define LPC17_QEI_SET (LPC17_QEI_BASE+LPC17_QEI_SET_OFFSET)
-
-/* Register bit definitions *********************************************************/
-/* The following registers hold 32-bit integer values and have no bit fields defined
- * in this section:
- *
- * Position register (POS)
- * Maximum position register (MAXPOS)
- * Position compare register 0 (CMPOS0)
- * Position compare register 1 (CMPOS)
- * Position compare register 2 (CMPOS2)
- * Index count register (INXCNT)
- * Index compare register (INXCMP)
- * Velocity timer reload register (LOAD)
- * Velocity timer register (TIME)
- * Velocity counter register (VEL)
- * Velocity capture register (CAP)
- * Velocity compare register (VELCOMP)
- * Digital filter register (FILTER)
- */
-
-/* Control registers */
-/* Control register */
-
-#define QEI_CON_RESP (1 << 0) /* Bit 0: Reset position counter */
-#define QEI_CON_RESPI (1 << 1) /* Bit 1: Reset position counter on index */
-#define QEI_CON_RESV (1 << 2) /* Bit 2: Reset velocity */
-#define QEI_CON_RESI (1 << 3) /* Bit 3: Reset index counter */
- /* Bits 4-31: reserved */
-/* Encoder status register */
-
-#define QEI_STAT_DIR (1 << 0) /* Bit 0: Direction bit */
- /* Bits 1-31: reserved */
-/* Configuration register */
-
-#define QEI_CONF_DIRINV (1 << 0) /* Bit 0: Direction invert */
-#define QEI_CONF_SIGMODE (1 << 1) /* Bit 1: Signal Mode */
-#define QEI_CONF_CAPMODE (1 << 2) /* Bit 2: Capture Mode */
-#define QEI_CONF_INVINX (1 << 3) /* Bit 3: Invert Index */
- /* Bits 4-31: reserved */
-/* Position, index, and timer registers (all 32-bit integer values with not bit fields */
-
-/* Interrupt registers */
-/* Interrupt enable clear register (IEC), Interrupt enable set register (IES),
- * Interrupt status register (INTSTAT), Interrupt enable register (IE), Interrupt
- * status clear register (CLR), and Interrupt status set register (SET) common
- * bit definitions.
- */
-
-#define QEI_INT_INX (1 << 0) /* Bit 0: Index pulse detected */
-#define QEI_INT_TIM (1 << 1) /* Bit 1: Velocity timer overflow occurred */
-#define QEI_INT_VELC (1 << 2) /* Bit 2: Captured velocity less than compare velocity */
-#define QEI_INT_DIR (1 << 3) /* Bit 3: Change of direction detected */
-#define QEI_INT_ERR (1 << 4) /* Bit 4: Encoder phase error detected */
-#define QEI_INT_ENCLK (1 << 5) /* Bit 5: Eencoder clock pulse detected */
-#define QEI_INT_POS0 (1 << 6) /* Bit 6: Position 0 compare equal to current position */
-#define QEI_INT_POS1 (1 << 7) /* Bit 7: Position 1 compare equal to current position */
-#define QEI_INT_POS2 (1 << 8) /* Bit 8: Position 2 compare equal to current position */
-#define QEI_INT_REV (1 << 9) /* Bit 9: Index compare value equal to current index count */
-#define QEI_INT_POS0REV (1 << 10) /* Bit 10: Combined position 0 and revolution count interrupt */
-#define QEI_INT_POS1REV (1 << 11) /* Bit 11: Position 1 and revolution count interrupt */
-#define QEI_INT_POS2REV (1 << 12) /* Bit 12: Position 2 and revolution count interrupt */
- /* Bits 13-31: reserved */
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-/************************************************************************************
- * Public Functions
- ************************************************************************************/
-
-#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_QEI_H */
+/************************************************************************************ + * arch/arm/src/lpc17xx/lpc17_qei.h + * + * Copyright (C) 2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_QEI_H +#define __ARCH_ARM_SRC_LPC17XX_LPC17_QEI_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +#include "chip.h" +#include "lpc17_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register offsets *****************************************************************/ +/* Control registers */ + +#define LPC17_QEI_CON_OFFSET 0x0000 /* Control register */ +#define LPC17_QEI_STAT_OFFSET 0x0004 /* Encoder status register */ +#define LPC17_QEI_CONF_OFFSET 0x0008 /* Configuration register */ + +/* Position, index, and timer registers */ + +#define LPC17_QEI_POS_OFFSET 0x000c /* Position register */ +#define LPC17_QEI_MAXPOS_OFFSET 0x0010 /* Maximum position register */ +#define LPC17_QEI_CMPOS0_OFFSET 0x0014 /* Position compare register */ +#define LPC17_QEI_CMPOS1_OFFSET 0x0018 /* Position compare register */ +#define LPC17_QEI_CMPOS2_OFFSET 0x001c /* Position compare register */ +#define LPC17_QEI_INXCNT_OFFSET 0x0020 /* Index count register */ +#define LPC17_QEI_INXCMP_OFFSET 0x0024 /* Index compare register */ +#define LPC17_QEI_LOAD_OFFSET 0x0028 /* Velocity timer reload register */ +#define LPC17_QEI_TIME_OFFSET 0x002c /* Velocity timer register */ +#define LPC17_QEI_VEL_OFFSET 0x0030 /* Velocity counter register */ +#define LPC17_QEI_CAP_OFFSET 0x0034 /* Velocity capture register */ +#define LPC17_QEI_VELCOMP_OFFSET 0x0038 /* Velocity compare register */ +#define LPC17_QEI_FILTER_OFFSET 0x003c /* Digital filter register */ + +/* Interrupt registers */ + +#define LPC17_QEI_IEC_OFFSET 0x0fd8 /* Interrupt enable clear register */ +#define LPC17_QEI_IES_OFFSET 0x0fdc /* Interrupt enable set register */ +#define LPC17_QEI_INTSTAT_OFFSET 0x0fe0 /* Interrupt status register */ +#define LPC17_QEI_IE_OFFSET 0x0fe4 /* Interrupt enable register */ +#define LPC17_QEI_CLR_OFFSET 0x0fe8 /* Interrupt status clear register */ +#define LPC17_QEI_SET_OFFSET 0x0fec /* Interrupt status set register */ + +/* Register addresses ***************************************************************/ +/* Control registers */ + +#define LPC17_QEI_CON (LPC17_QEI_BASE+LPC17_QEI_CON_OFFSET) +#define LPC17_QEI_STAT (LPC17_QEI_BASE+LPC17_QEI_STAT_OFFSET) +#define LPC17_QEI_CONF (LPC17_QEI_BASE+LPC17_QEI_CONF_OFFSET) + +/* Position, index, and timer registers */ + +#define LPC17_QEI_POS (LPC17_QEI_BASE+LPC17_QEI_POS_OFFSET) +#define LPC17_QEI_MAXPOS (LPC17_QEI_BASE+LPC17_QEI_MAXPOS_OFFSET) +#define LPC17_QEI_CMPOS0 (LPC17_QEI_BASE+LPC17_QEI_CMPOS0_OFFSET) +#define LPC17_QEI_CMPOS1 (LPC17_QEI_BASE+LPC17_QEI_CMPOS1_OFFSET) +#define LPC17_QEI_CMPOS2 (LPC17_QEI_BASE+LPC17_QEI_CMPOS2_OFFSET) +#define LPC17_QEI_INXCNT (LPC17_QEI_BASE+LPC17_QEI_INXCNT_OFFSET) +#define LPC17_QEI_INXCMP (LPC17_QEI_BASE+LPC17_QEI_INXCMP_OFFSET) +#define LPC17_QEI_LOAD (LPC17_QEI_BASE+LPC17_QEI_LOAD_OFFSET) +#define LPC17_QEI_TIME (LPC17_QEI_BASE+LPC17_QEI_TIME_OFFSET) +#define LPC17_QEI_VEL (LPC17_QEI_BASE+LPC17_QEI_VEL_OFFSET) +#define LPC17_QEI_CAP (LPC17_QEI_BASE+LPC17_QEI_CAP_OFFSET) +#define LPC17_QEI_VELCOMP (LPC17_QEI_BASE+LPC17_QEI_VELCOMP_OFFSET) +#define LPC17_QEI_FILTER (LPC17_QEI_BASE+LPC17_QEI_FILTER_OFFSET) + +/* Interrupt registers */ + +#define LPC17_QEI_IEC (LPC17_QEI_BASE+LPC17_QEI_IEC_OFFSET) +#define LPC17_QEI_IES (LPC17_QEI_BASE+LPC17_QEI_IES_OFFSET) +#define LPC17_QEI_INTSTAT (LPC17_QEI_BASE+LPC17_QEI_INTSTAT_OFFSET) +#define LPC17_QEI_IE (LPC17_QEI_BASE+LPC17_QEI_IE_OFFSET) +#define LPC17_QEI_CLR (LPC17_QEI_BASE+LPC17_QEI_CLR_OFFSET) +#define LPC17_QEI_SET (LPC17_QEI_BASE+LPC17_QEI_SET_OFFSET) + +/* Register bit definitions *********************************************************/ +/* The following registers hold 32-bit integer values and have no bit fields defined + * in this section: + * + * Position register (POS) + * Maximum position register (MAXPOS) + * Position compare register 0 (CMPOS0) + * Position compare register 1 (CMPOS) + * Position compare register 2 (CMPOS2) + * Index count register (INXCNT) + * Index compare register (INXCMP) + * Velocity timer reload register (LOAD) + * Velocity timer register (TIME) + * Velocity counter register (VEL) + * Velocity capture register (CAP) + * Velocity compare register (VELCOMP) + * Digital filter register (FILTER) + */ + +/* Control registers */ +/* Control register */ + +#define QEI_CON_RESP (1 << 0) /* Bit 0: Reset position counter */ +#define QEI_CON_RESPI (1 << 1) /* Bit 1: Reset position counter on index */ +#define QEI_CON_RESV (1 << 2) /* Bit 2: Reset velocity */ +#define QEI_CON_RESI (1 << 3) /* Bit 3: Reset index counter */ + /* Bits 4-31: reserved */ +/* Encoder status register */ + +#define QEI_STAT_DIR (1 << 0) /* Bit 0: Direction bit */ + /* Bits 1-31: reserved */ +/* Configuration register */ + +#define QEI_CONF_DIRINV (1 << 0) /* Bit 0: Direction invert */ +#define QEI_CONF_SIGMODE (1 << 1) /* Bit 1: Signal Mode */ +#define QEI_CONF_CAPMODE (1 << 2) /* Bit 2: Capture Mode */ +#define QEI_CONF_INVINX (1 << 3) /* Bit 3: Invert Index */ + /* Bits 4-31: reserved */ +/* Position, index, and timer registers (all 32-bit integer values with not bit fields */ + +/* Interrupt registers */ +/* Interrupt enable clear register (IEC), Interrupt enable set register (IES), + * Interrupt status register (INTSTAT), Interrupt enable register (IE), Interrupt + * status clear register (CLR), and Interrupt status set register (SET) common + * bit definitions. + */ + +#define QEI_INT_INX (1 << 0) /* Bit 0: Index pulse detected */ +#define QEI_INT_TIM (1 << 1) /* Bit 1: Velocity timer overflow occurred */ +#define QEI_INT_VELC (1 << 2) /* Bit 2: Captured velocity less than compare velocity */ +#define QEI_INT_DIR (1 << 3) /* Bit 3: Change of direction detected */ +#define QEI_INT_ERR (1 << 4) /* Bit 4: Encoder phase error detected */ +#define QEI_INT_ENCLK (1 << 5) /* Bit 5: Eencoder clock pulse detected */ +#define QEI_INT_POS0 (1 << 6) /* Bit 6: Position 0 compare equal to current position */ +#define QEI_INT_POS1 (1 << 7) /* Bit 7: Position 1 compare equal to current position */ +#define QEI_INT_POS2 (1 << 8) /* Bit 8: Position 2 compare equal to current position */ +#define QEI_INT_REV (1 << 9) /* Bit 9: Index compare value equal to current index count */ +#define QEI_INT_POS0REV (1 << 10) /* Bit 10: Combined position 0 and revolution count interrupt */ +#define QEI_INT_POS1REV (1 << 11) /* Bit 11: Position 1 and revolution count interrupt */ +#define QEI_INT_POS2REV (1 << 12) /* Bit 12: Position 2 and revolution count interrupt */ + /* Bits 13-31: reserved */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_QEI_H */ diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_rit.h b/nuttx/arch/arm/src/lpc17xx/lpc17_rit.h index 57d89de95..2da0164bd 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_rit.h +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_rit.h @@ -1,92 +1,92 @@ -/************************************************************************************
- * arch/arm/src/lpc17xx/lpc17_rit.h
- *
- * Copyright (C) 2010 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_RIT_H
-#define __ARCH_ARM_SRC_LPC17XX_LPC17_RIT_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-
-#include "chip.h"
-#include "lpc17_memorymap.h"
-
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-
-/* Register offsets *****************************************************************/
-
-#define LPC17_RIT_COMPVAL_OFFSET 0x0000 /* Compare register */
-#define LPC17_RIT_MASK_OFFSET 0x0004 /* Mask register */
-#define LPC17_RIT_CTRL_OFFSET 0x0008 /* Control register */
-#define LPC17_RIT_COUNTER_OFFSET 0x000c /* 32-bit counter */
-
-/* Register addresses ***************************************************************/
-
-#define LPC17_RIT_COMPVAL (LPC17_RIT_BASE+LPC17_RIT_COMPVAL_OFFSET)
-#define LPC17_RIT_MASK (LPC17_RIT_BASE+LPC17_RIT_MASK_OFFSET)
-#define LPC17_RIT_CTRL (LPC17_RIT_BASE+LPC17_RIT_CTRL_OFFSET)
-#define LPC17_RIT_COUNTER (LPC17_RIT_BASE+LPC17_RIT_COUNTER_OFFSET)
-
-/* Register bit definitions *********************************************************/
-/* Compare register (Bits 0-31: value compared to the counter) */
-
-/* Mask register (Bits 0-31: 32-bit mask value) */
-
-/* Control register */
-
-#define RIT_CTRL_INT (1 << 0) /* Bit 0: Interrupt flag */
-#define RIT_CTRL_ENCLR (1 << 1) /* Bit 1: Timer enable clear */
-#define RIT_CTRL_ENBR (1 << 2) /* Bit 2: Timer enable for debug */
-#define RIT_CTRL_EN (1 << 3) /* Bit 3: Timer enable */
- /* Bits 4-31: Reserved */
-/* 32-bit counter (Bits 0-31: 32-bit up counter) */
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-/************************************************************************************
- * Public Functions
- ************************************************************************************/
-
-#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_RIT_H */
+/************************************************************************************ + * arch/arm/src/lpc17xx/lpc17_rit.h + * + * Copyright (C) 2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_RIT_H +#define __ARCH_ARM_SRC_LPC17XX_LPC17_RIT_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +#include "chip.h" +#include "lpc17_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register offsets *****************************************************************/ + +#define LPC17_RIT_COMPVAL_OFFSET 0x0000 /* Compare register */ +#define LPC17_RIT_MASK_OFFSET 0x0004 /* Mask register */ +#define LPC17_RIT_CTRL_OFFSET 0x0008 /* Control register */ +#define LPC17_RIT_COUNTER_OFFSET 0x000c /* 32-bit counter */ + +/* Register addresses ***************************************************************/ + +#define LPC17_RIT_COMPVAL (LPC17_RIT_BASE+LPC17_RIT_COMPVAL_OFFSET) +#define LPC17_RIT_MASK (LPC17_RIT_BASE+LPC17_RIT_MASK_OFFSET) +#define LPC17_RIT_CTRL (LPC17_RIT_BASE+LPC17_RIT_CTRL_OFFSET) +#define LPC17_RIT_COUNTER (LPC17_RIT_BASE+LPC17_RIT_COUNTER_OFFSET) + +/* Register bit definitions *********************************************************/ +/* Compare register (Bits 0-31: value compared to the counter) */ + +/* Mask register (Bits 0-31: 32-bit mask value) */ + +/* Control register */ + +#define RIT_CTRL_INT (1 << 0) /* Bit 0: Interrupt flag */ +#define RIT_CTRL_ENCLR (1 << 1) /* Bit 1: Timer enable clear */ +#define RIT_CTRL_ENBR (1 << 2) /* Bit 2: Timer enable for debug */ +#define RIT_CTRL_EN (1 << 3) /* Bit 3: Timer enable */ + /* Bits 4-31: Reserved */ +/* 32-bit counter (Bits 0-31: 32-bit up counter) */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_RIT_H */ diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_serial.h b/nuttx/arch/arm/src/lpc17xx/lpc17_serial.h index 9fca96219..27d7da9d1 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_serial.h +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_serial.h @@ -1,127 +1,127 @@ -/************************************************************************************
- * arch/arm/src/lpc17xx/lpc17_serial.h
- *
- * Copyright (C) 2010 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_SERIAL_H
-#define __ARCH_ARM_SRC_LPC17XX_LPC17_SERIAL_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-#include <arch/board/board.h>
-
-#include "lpc17_uart.h"
-#include "lpc17_syscon.h"
-
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-
-/* Configuration *********************************************************************/
-
-/* Are any UARTs enabled? */
-
-#undef HAVE_UART
-#if defined(CONFIG_LPC17_UART0) || defined(CONFIG_LPC17_UART1) || \
- defined(CONFIG_LPC17_UART2) || defined(CONFIG_LPC17_UART3)
-# define HAVE_UART 1
-#endif
-
-/* Is there a serial console? There should be at most one defined. It could be on
- * any UARTn, n=0,1,2,3
- */
-
-#if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_LPC17_UART0)
-# undef CONFIG_UART1_SERIAL_CONSOLE
-# undef CONFIG_UART2_SERIAL_CONSOLE
-# undef CONFIG_UART3_SERIAL_CONSOLE
-# define HAVE_CONSOLE 1
-#elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_LPC17_UART1)
-# undef CONFIG_UART0_SERIAL_CONSOLE
-# undef CONFIG_UART2_SERIAL_CONSOLE
-# undef CONFIG_UART3_SERIAL_CONSOLE
-# define HAVE_CONSOLE 1
-#elif defined(CONFIG_UART2_SERIAL_CONSOLE) && defined(CONFIG_LPC17_UART2)
-# undef CONFIG_UART0_SERIAL_CONSOLE
-# undef CONFIG_UART1_SERIAL_CONSOLE
-# undef CONFIG_UART3_SERIAL_CONSOLE
-# define HAVE_CONSOLE 1
-#elif defined(CONFIG_UART3_SERIAL_CONSOLE) && defined(CONFIG_LPC17_UART3)
-# undef CONFIG_UART0_SERIAL_CONSOLE
-# undef CONFIG_UART1_SERIAL_CONSOLE
-# undef CONFIG_UART2_SERIAL_CONSOLE
-# define HAVE_CONSOLE 1
-#else
-# undef CONFIG_UART0_SERIAL_CONSOLE
-# undef CONFIG_UART1_SERIAL_CONSOLE
-# undef CONFIG_UART2_SERIAL_CONSOLE
-# undef CONFIG_UART3_SERIAL_CONSOLE
-# undef HAVE_CONSOLE
-#endif
-
-/* Check UART flow control (Only supported by UART1) */
-
-# undef CONFIG_UART0_FLOWCONTROL
-# undef CONFIG_UART2_FLOWCONTROL
-# undef CONFIG_UART3_FLOWCONTROL
-#ifndef CONFIG_LPC17_UART1
-# undef CONFIG_UART1_FLOWCONTROL
-#endif
-
-/* We cannot allow the DLM/DLL divisor to become to small or will will lose too
- * much accuracy. This following is a "fudge factor" that represents the minimum
- * value of the divisor that we will permit.
- */
-
-#define UART_MINDL 32
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-/************************************************************************************
- * Inline Functions
- ************************************************************************************/
-
-/************************************************************************************
- * Public Functions
- ************************************************************************************/
-
-#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_SERIAL_H */
+/************************************************************************************ + * arch/arm/src/lpc17xx/lpc17_serial.h + * + * Copyright (C) 2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_SERIAL_H +#define __ARCH_ARM_SRC_LPC17XX_LPC17_SERIAL_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> +#include <arch/board/board.h> + +#include "lpc17_uart.h" +#include "lpc17_syscon.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Configuration *********************************************************************/ + +/* Are any UARTs enabled? */ + +#undef HAVE_UART +#if defined(CONFIG_LPC17_UART0) || defined(CONFIG_LPC17_UART1) || \ + defined(CONFIG_LPC17_UART2) || defined(CONFIG_LPC17_UART3) +# define HAVE_UART 1 +#endif + +/* Is there a serial console? There should be at most one defined. It could be on + * any UARTn, n=0,1,2,3 + */ + +#if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_LPC17_UART0) +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# define HAVE_CONSOLE 1 +#elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_LPC17_UART1) +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# define HAVE_CONSOLE 1 +#elif defined(CONFIG_UART2_SERIAL_CONSOLE) && defined(CONFIG_LPC17_UART2) +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# define HAVE_CONSOLE 1 +#elif defined(CONFIG_UART3_SERIAL_CONSOLE) && defined(CONFIG_LPC17_UART3) +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# define HAVE_CONSOLE 1 +#else +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# undef HAVE_CONSOLE +#endif + +/* Check UART flow control (Only supported by UART1) */ + +# undef CONFIG_UART0_FLOWCONTROL +# undef CONFIG_UART2_FLOWCONTROL +# undef CONFIG_UART3_FLOWCONTROL +#ifndef CONFIG_LPC17_UART1 +# undef CONFIG_UART1_FLOWCONTROL +#endif + +/* We cannot allow the DLM/DLL divisor to become to small or will will lose too + * much accuracy. This following is a "fudge factor" that represents the minimum + * value of the divisor that we will permit. + */ + +#define UART_MINDL 32 + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Inline Functions + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_SERIAL_H */ diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_spi.c b/nuttx/arch/arm/src/lpc17xx/lpc17_spi.c index f0a2b1264..a7bb15931 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_spi.c +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_spi.c @@ -2,7 +2,7 @@ * arch/arm/src/lpc17xx/lpc17_spi.c * * Copyright (C) 2010, 2012 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_spi.h b/nuttx/arch/arm/src/lpc17xx/lpc17_spi.h index ca7699c15..880966eb1 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_spi.h +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_spi.h @@ -1,141 +1,141 @@ -/************************************************************************************
- * arch/arm/src/lpc17xx/lpc17_spi.h
- *
- * Copyright (C) 2010 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_SPI_H
-#define __ARCH_ARM_SRC_LPC17XX_LPC17_SPI_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-
-#include "chip.h"
-#include "lpc17_memorymap.h"
-
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-
-/* Register offsets *****************************************************************/
-
-#define LPC17_SPI_CR_OFFSET 0x0000 /* Control Register */
-#define LPC17_SPI_SR_OFFSET 0x0004 /* SPI Status Register */
-#define LPC17_SPI_DR_OFFSET 0x0008 /* SPI Data Register */
-#define LPC17_SPI_CCR_OFFSET 0x000c /* SPI Clock Counter Register */
-#define LPC17_SPI_TCR_OFFSET 0x0010 /* SPI Test Control Register */
-#define LPC17_SPI_TSR_OFFSET 0x0014 /* SPI Test Status Register */
-#define LPC17_SPI_INT_OFFSET 0x001c /* SPI Interrupt Register */
-
-/* Register addresses ***************************************************************/
-
-#define LPC17_SPI_CR (LPC17_SPI_BASE+LPC17_SPI_CR_OFFSET)
-#define LPC17_SPI_SR (LPC17_SPI_BASE+LPC17_SPI_SR_OFFSET)
-#define LPC17_SPI_DR (LPC17_SPI_BASE+LPC17_SPI_DR_OFFSET)
-#define LPC17_SPI_CCR (LPC17_SPI_BASE+LPC17_SPI_CCR_OFFSET)
-#define LPC17_TCR_CCR (LPC17_SPI_BASE+LPC17_SPI_TCR_OFFSET)
-#define LPC17_TSR_CCR (LPC17_SPI_BASE+LPC17_SPI_TSR_OFFSET)
-#define LPC17_SPI_INT (LPC17_SPI_BASE+LPC17_SPI_INT_OFFSET)
-
-/* Register bit definitions *********************************************************/
-
-/* Control Register */
- /* Bits 0-1: Reserved */
-#define SPI_CR_BITENABLE (1 << 2) /* Bit 2: Enable word size selected by BITS */
-#define SPI_CR_CPHA (1 << 3) /* Bit 3: Clock phase control */
-#define SPI_CR_CPOL (1 << 4) /* Bit 4: Clock polarity control */
-#define SPI_CR_MSTR (1 << 5) /* Bit 5: Master mode select */
-#define SPI_CR_LSBF (1 << 6) /* Bit 6: SPI data is transferred LSB first */
-#define SPI_CR_SPIE (1 << 7) /* Bit 7: Serial peripheral interrupt enable */
-#define SPI_CR_BITS_SHIFT (8) /* Bits 8-11: Number of bits per word (BITENABLE==1) */
-#define SPI_CR_BITS_MASK (15 << SPI_CR_BITS_SHIFT)
-# define SPI_CR_BITS_8BITS (8 << SPI_CR_BITS_SHIFT) /* 8 bits per transfer */
-# define SPI_CR_BITS_9BITS (9 << SPI_CR_BITS_SHIFT) /* 9 bits per transfer */
-# define SPI_CR_BITS_10BITS (10 << SPI_CR_BITS_SHIFT) /* 10 bits per transfer */
-# define SPI_CR_BITS_11BITS (11 << SPI_CR_BITS_SHIFT) /* 11 bits per transfer */
-# define SPI_CR_BITS_12BITS (12 << SPI_CR_BITS_SHIFT) /* 12 bits per transfer */
-# define SPI_CR_BITS_13BITS (13 << SPI_CR_BITS_SHIFT) /* 13 bits per transfer */
-# define SPI_CR_BITS_14BITS (14 << SPI_CR_BITS_SHIFT) /* 14 bits per transfer */
-# define SPI_CR_BITS_15BITS (15 << SPI_CR_BITS_SHIFT) /* 15 bits per transfer */
-# define SPI_CR_BITS_16BITS (0 << SPI_CR_BITS_SHIFT) /* 16 bits per transfer */
- /* Bits 12-31: Reserved */
-/* SPI Status Register */
- /* Bits 0-2: Reserved */
-#define SPI_SR_ABRT (1 << 3) /* Bit 3: Slave abort */
-#define SPI_SR_MODF (1 << 4) /* Bit 4: Mode fault */
-#define SPI_SR_ROVR (1 << 5) /* Bit 5: Read overrun */
-#define SPI_SR_WCOL (1 << 6) /* Bit 6: Write collision */
-#define SPI_SR_SPIF (1 << 7) /* Bit 7: SPI transfer complete */
- /* Bits 8-31: Reserved */
-/* SPI Data Register */
-
-#define SPI_DR_MASK (0xff) /* Bits 0-15: SPI Bi-directional data port */
-#define SPI_DR_MASKWIDE (0xffff) /* Bits 0-15: If SPI_CR_BITENABLE != 0 */
- /* Bits 8-31: Reserved */
-/* SPI Clock Counter Register */
-
-#define SPI_CCR_MASK (0xff) /* Bits 0-7: SPI Clock counter setting */
- /* Bits 8-31: Reserved */
-/* SPI Test Control Register */
- /* Bit 0: Reserved */
-#define SPI_TCR_TEST_SHIFT (1) /* Bits 1-7: SPI test mode */
-#define SPI_TCR_TEST_MASK (0x7f << SPI_TCR_TEST_SHIFT)
- /* Bits 8-31: Reserved */
-/* SPI Test Status Register */
- /* Bits 0-2: Reserved */
-#define SPI_TSR_ABRT (1 << 3) /* Bit 3: Slave abort */
-#define SPI_TSR_MODF (1 << 4) /* Bit 4: Mode fault */
-#define SPI_TSR_ROVR (1 << 5) /* Bit 5: Read overrun */
-#define SPI_TSR_WCOL (1 << 6) /* Bit 6: Write collision */
-#define SPI_TSR_SPIF (1 << 7) /* Bit 7: SPI transfer complete */
- /* Bits 8-31: Reserved */
-/* SPI Interrupt Register */
-
-#define SPI_INT_SPIF (1 << 0) /* SPI interrupt */
- /* Bits 1-31: Reserved */
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-/************************************************************************************
- * Public Functions
- ************************************************************************************/
-
-#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_SPI_H */
+/************************************************************************************ + * arch/arm/src/lpc17xx/lpc17_spi.h + * + * Copyright (C) 2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_SPI_H +#define __ARCH_ARM_SRC_LPC17XX_LPC17_SPI_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +#include "chip.h" +#include "lpc17_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register offsets *****************************************************************/ + +#define LPC17_SPI_CR_OFFSET 0x0000 /* Control Register */ +#define LPC17_SPI_SR_OFFSET 0x0004 /* SPI Status Register */ +#define LPC17_SPI_DR_OFFSET 0x0008 /* SPI Data Register */ +#define LPC17_SPI_CCR_OFFSET 0x000c /* SPI Clock Counter Register */ +#define LPC17_SPI_TCR_OFFSET 0x0010 /* SPI Test Control Register */ +#define LPC17_SPI_TSR_OFFSET 0x0014 /* SPI Test Status Register */ +#define LPC17_SPI_INT_OFFSET 0x001c /* SPI Interrupt Register */ + +/* Register addresses ***************************************************************/ + +#define LPC17_SPI_CR (LPC17_SPI_BASE+LPC17_SPI_CR_OFFSET) +#define LPC17_SPI_SR (LPC17_SPI_BASE+LPC17_SPI_SR_OFFSET) +#define LPC17_SPI_DR (LPC17_SPI_BASE+LPC17_SPI_DR_OFFSET) +#define LPC17_SPI_CCR (LPC17_SPI_BASE+LPC17_SPI_CCR_OFFSET) +#define LPC17_TCR_CCR (LPC17_SPI_BASE+LPC17_SPI_TCR_OFFSET) +#define LPC17_TSR_CCR (LPC17_SPI_BASE+LPC17_SPI_TSR_OFFSET) +#define LPC17_SPI_INT (LPC17_SPI_BASE+LPC17_SPI_INT_OFFSET) + +/* Register bit definitions *********************************************************/ + +/* Control Register */ + /* Bits 0-1: Reserved */ +#define SPI_CR_BITENABLE (1 << 2) /* Bit 2: Enable word size selected by BITS */ +#define SPI_CR_CPHA (1 << 3) /* Bit 3: Clock phase control */ +#define SPI_CR_CPOL (1 << 4) /* Bit 4: Clock polarity control */ +#define SPI_CR_MSTR (1 << 5) /* Bit 5: Master mode select */ +#define SPI_CR_LSBF (1 << 6) /* Bit 6: SPI data is transferred LSB first */ +#define SPI_CR_SPIE (1 << 7) /* Bit 7: Serial peripheral interrupt enable */ +#define SPI_CR_BITS_SHIFT (8) /* Bits 8-11: Number of bits per word (BITENABLE==1) */ +#define SPI_CR_BITS_MASK (15 << SPI_CR_BITS_SHIFT) +# define SPI_CR_BITS_8BITS (8 << SPI_CR_BITS_SHIFT) /* 8 bits per transfer */ +# define SPI_CR_BITS_9BITS (9 << SPI_CR_BITS_SHIFT) /* 9 bits per transfer */ +# define SPI_CR_BITS_10BITS (10 << SPI_CR_BITS_SHIFT) /* 10 bits per transfer */ +# define SPI_CR_BITS_11BITS (11 << SPI_CR_BITS_SHIFT) /* 11 bits per transfer */ +# define SPI_CR_BITS_12BITS (12 << SPI_CR_BITS_SHIFT) /* 12 bits per transfer */ +# define SPI_CR_BITS_13BITS (13 << SPI_CR_BITS_SHIFT) /* 13 bits per transfer */ +# define SPI_CR_BITS_14BITS (14 << SPI_CR_BITS_SHIFT) /* 14 bits per transfer */ +# define SPI_CR_BITS_15BITS (15 << SPI_CR_BITS_SHIFT) /* 15 bits per transfer */ +# define SPI_CR_BITS_16BITS (0 << SPI_CR_BITS_SHIFT) /* 16 bits per transfer */ + /* Bits 12-31: Reserved */ +/* SPI Status Register */ + /* Bits 0-2: Reserved */ +#define SPI_SR_ABRT (1 << 3) /* Bit 3: Slave abort */ +#define SPI_SR_MODF (1 << 4) /* Bit 4: Mode fault */ +#define SPI_SR_ROVR (1 << 5) /* Bit 5: Read overrun */ +#define SPI_SR_WCOL (1 << 6) /* Bit 6: Write collision */ +#define SPI_SR_SPIF (1 << 7) /* Bit 7: SPI transfer complete */ + /* Bits 8-31: Reserved */ +/* SPI Data Register */ + +#define SPI_DR_MASK (0xff) /* Bits 0-15: SPI Bi-directional data port */ +#define SPI_DR_MASKWIDE (0xffff) /* Bits 0-15: If SPI_CR_BITENABLE != 0 */ + /* Bits 8-31: Reserved */ +/* SPI Clock Counter Register */ + +#define SPI_CCR_MASK (0xff) /* Bits 0-7: SPI Clock counter setting */ + /* Bits 8-31: Reserved */ +/* SPI Test Control Register */ + /* Bit 0: Reserved */ +#define SPI_TCR_TEST_SHIFT (1) /* Bits 1-7: SPI test mode */ +#define SPI_TCR_TEST_MASK (0x7f << SPI_TCR_TEST_SHIFT) + /* Bits 8-31: Reserved */ +/* SPI Test Status Register */ + /* Bits 0-2: Reserved */ +#define SPI_TSR_ABRT (1 << 3) /* Bit 3: Slave abort */ +#define SPI_TSR_MODF (1 << 4) /* Bit 4: Mode fault */ +#define SPI_TSR_ROVR (1 << 5) /* Bit 5: Read overrun */ +#define SPI_TSR_WCOL (1 << 6) /* Bit 6: Write collision */ +#define SPI_TSR_SPIF (1 << 7) /* Bit 7: SPI transfer complete */ + /* Bits 8-31: Reserved */ +/* SPI Interrupt Register */ + +#define SPI_INT_SPIF (1 << 0) /* SPI interrupt */ + /* Bits 1-31: Reserved */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_SPI_H */ diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_syscon.h b/nuttx/arch/arm/src/lpc17xx/lpc17_syscon.h index c9a2dbb54..ce8654645 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_syscon.h +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_syscon.h @@ -2,7 +2,7 @@ * arch/arm/src/lpc17xx/lpc17_syscon.h * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_timerisr.c b/nuttx/arch/arm/src/lpc17xx/lpc17_timerisr.c index aa113463a..918c153a4 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_timerisr.c +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_timerisr.c @@ -2,7 +2,7 @@ * arch/arm/src/lpc17xx/lpc17_timerisr.c * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_usb.h b/nuttx/arch/arm/src/lpc17xx/lpc17_usb.h index 40c491811..8fd599584 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_usb.h +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_usb.h @@ -1,778 +1,778 @@ -/************************************************************************************
- * arch/arm/src/lpc17xx/lpc17_usb.h
- *
- * Copyright (C) 2010 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_USB_H
-#define __ARCH_ARM_SRC_LPC17XX_LPC17_USB_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-#include <nuttx/usb/ohci.h>
-
-#include "chip.h"
-#include "lpc17_memorymap.h"
-
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-
-/* Register offsets *****************************************************************/
-/* USB Host Controller (OHCI) *******************************************************/
-/* See include/nuttx/usb/ohci.h */
-
-#define LPC17_USBHOST_MODID_OFFSET 0x00fc /* Module ID/Revision ID */
-
-/* USB OTG Controller ***************************************************************/
-/* OTG registers */
-
-#define LPC17_USBOTG_INTST_OFFSET 0x0100 /* OTG Interrupt Status */
-#define LPC17_USBOTG_INTEN_OFFSET 0x0104 /* OTG Interrupt Enable */
-#define LPC17_USBOTG_INTSET_OFFSET 0x0108 /* OTG Interrupt Set */
-#define LPC17_USBOTG_INTCLR_OFFSET 0x010c /* OTG Interrupt Clear */
-#define LPC17_USBOTG_STCTRL_OFFSET 0x0110 /* OTG Status and Control */
-#define LPC17_USBOTG_TMR_OFFSET 0x0114 /* OTG Timer */
-
-/* USB Device Controller ************************************************************/
-/* Device interrupt registers. See also SYSCON_USBINTST in lpc17_syscon.h */
-
-#define LPC17_USBDEV_INTST_OFFSET 0x0200 /* USB Device Interrupt Status */
-#define LPC17_USBDEV_INTEN_OFFSET 0x0204 /* USB Device Interrupt Enable */
-#define LPC17_USBDEV_INTCLR_OFFSET 0x0208 /* USB Device Interrupt Clear */
-#define LPC17_USBDEV_INTSET_OFFSET 0x020c /* USB Device Interrupt Set */
-
-/* SIE Command registers */
-
-#define LPC17_USBDEV_CMDCODE_OFFSET 0x0210 /* USB Command Code */
-#define LPC17_USBDEV_CMDDATA_OFFSET 0x0214 /* USB Command Data */
-
-/* USB transfer registers */
-
-#define LPC17_USBDEV_RXDATA_OFFSET 0x0218 /* USB Receive Data */
-#define LPC17_USBDEV_RXPLEN_OFFSET 0x0220 /* USB Receive Packet Length */
-#define LPC17_USBDEV_TXDATA_OFFSET 0x021c /* USB Transmit Data */
-#define LPC17_USBDEV_TXPLEN_OFFSET 0x0224 /* USB Transmit Packet Length */
-#define LPC17_USBDEV_CTRL_OFFSET 0x0228 /* USB Control */
-
-/* More Device interrupt registers */
-
-#define LPC17_USBDEV_INTPRI_OFFSET 0x022c /* USB Device Interrupt Priority */
-
-/* Endpoint interrupt registers */
-
-#define LPC17_USBDEV_EPINTST_OFFSET 0x0230 /* USB Endpoint Interrupt Status */
-#define LPC17_USBDEV_EPINTEN_OFFSET 0x0234 /* USB Endpoint Interrupt Enable */
-#define LPC17_USBDEV_EPINTCLR_OFFSET 0x0238 /* USB Endpoint Interrupt Clear */
-#define LPC17_USBDEV_EPINTSET_OFFSET 0x023c /* USB Endpoint Interrupt Set */
-#define LPC17_USBDEV_EPINTPRI_OFFSET 0x0240 /* USB Endpoint Priority */
-
-/* Endpoint realization registers */
-
-#define LPC17_USBDEV_REEP_OFFSET 0x0244 /* USB Realize Endpoint */
-#define LPC17_USBDEV_EPIND_OFFSET 0x0248 /* USB Endpoint Index */
-#define LPC17_USBDEV_MAXPSIZE_OFFSET 0x024c /* USB MaxPacketSize */
-
-/* DMA registers */
-
-#define LPC17_USBDEV_DMARST_OFFSET 0x0250 /* USB DMA Request Status */
-#define LPC17_USBDEV_DMARCLR_OFFSET 0x0254 /* USB DMA Request Clear */
-#define LPC17_USBDEV_DMARSET_OFFSET 0x0258 /* USB DMA Request Set */
-#define LPC17_USBDEV_UDCAH_OFFSET 0x0280 /* USB UDCA Head */
-#define LPC17_USBDEV_EPDMAST_OFFSET 0x0284 /* USB Endpoint DMA Status */
-#define LPC17_USBDEV_EPDMAEN_OFFSET 0x0288 /* USB Endpoint DMA Enable */
-#define LPC17_USBDEV_EPDMADIS_OFFSET 0x028c /* USB Endpoint DMA Disable */
-#define LPC17_USBDEV_DMAINTST_OFFSET 0x0290 /* USB DMA Interrupt Status */
-#define LPC17_USBDEV_DMAINTEN_OFFSET 0x0294 /* USB DMA Interrupt Enable */
-#define LPC17_USBDEV_EOTINTST_OFFSET 0x02a0 /* USB End of Transfer Interrupt Status */
-#define LPC17_USBDEV_EOTINTCLR_OFFSET 0x02a4 /* USB End of Transfer Interrupt Clear */
-#define LPC17_USBDEV_EOTINTSET_OFFSET 0x02a8 /* USB End of Transfer Interrupt Set */
-#define LPC17_USBDEV_NDDRINTST_OFFSET 0x02ac /* USB New DD Request Interrupt Status */
-#define LPC17_USBDEV_NDDRINTCLR_OFFSET 0x02b0 /* USB New DD Request Interrupt Clear */
-#define LPC17_USBDEV_NDDRINTSET_OFFSET 0x02b4 /* USB New DD Request Interrupt Set */
-#define LPC17_USBDEV_SYSERRINTST_OFFSET 0x02b8 /* USB System Error Interrupt Status */
-#define LPC17_USBDEV_SYSERRINTCLR_OFFSET 0x02bc /* USB System Error Interrupt Clear */
-#define LPC17_USBDEV_SYSERRINTSET_OFFSET 0x02c0 /* USB System Error Interrupt Set */
-
-/* OTG I2C registers ****************************************************************/
-
-#define LPC17_OTGI2C_RX_OFFSET 0x0300 /* I2C Receive */
-#define LPC17_OTGI2C_TX_OFFSET 0x0300 /* I2C Transmit */
-#define LPC17_OTGI2C_STS_OFFSET 0x0304 /* I2C Status */
-#define LPC17_OTGI2C_CTL_OFFSET 0x0308 /* I2C Control */
-#define LPC17_OTGI2C_CLKHI_OFFSET 0x030c /* I2C Clock High */
-#define LPC17_OTGI2C_CLKLO_OFFSET 0x0310 /* I2C Clock Low */
-
-/* Clock control registers ***********************************************************/
-
-#define LPC17_USBOTG_CLKCTRL_OFFSET 0x0ff4 /* OTG clock controller */
-#define LPC17_USBOTG_CLKST_OFFSET 0x0ff8 /* OTG clock status */
-
-#define LPC17_USBDEV_CLKCTRL_OFFSET 0x0ff4 /* USB Clock Control */
-#define LPC17_USBDEV_CLKST_OFFSET 0x0ff8 /* USB Clock Status */
-
-/* Register addresses ***************************************************************/
-/* USB Host Controller (OHCI) *******************************************************/
-/* Control and status registers (section 7.1) */
-
-#define LPC17_USBHOST_HCIREV (LPC17_USB_BASE+OHCI_HCIREV_OFFSET)
-#define LPC17_USBHOST_CTRL (LPC17_USB_BASE+OHCI_CTRL_OFFSET)
-#define LPC17_USBHOST_CMDST (LPC17_USB_BASE+OHCI_CMDST_OFFSET)
-#define LPC17_USBHOST_INTST (LPC17_USB_BASE+OHCI_INTST_OFFSET)
-#define LPC17_USBHOST_INTEN (LPC17_USB_BASE+OHCI_INTEN_OFFSET)
-#define LPC17_USBHOST_INTDIS (LPC17_USB_BASE+OHCI_INTDIS_OFFSET)
-
-/* Memory pointers (section 7.2) */
-
-#define LPC17_USBHOST_HCCA (LPC17_USB_BASE+OHCI_HCCA_OFFSET)
-#define LPC17_USBHOST_PERED (LPC17_USB_BASE+OHCI_PERED_OFFSET)
-#define LPC17_USBHOST_CTRLHEADED (LPC17_USB_BASE+OHCI_CTRLHEADED_OFFSET)
-#define LPC17_USBHOST_CTRLED (LPC17_USB_BASE+OHCI_CTRLED_OFFSET)
-#define LPC17_USBHOST_BULKHEADED (LPC17_USB_BASE+OHCI_BULKHEADED_OFFSET)
-#define LPC17_USBHOST_BULKED (LPC17_USB_BASE+OHCI_BULKED_OFFSET)
-#define LPC17_USBHOST_DONEHEAD (LPC17_USB_BASE+OHCI_DONEHEAD_OFFSET)
-
-/* Frame counters (section 7.3) */
-
-#define LPC17_USBHOST_FMINT (LPC17_USB_BASE+OHCI_FMINT_OFFSET)
-#define LPC17_USBHOST_FMREM (LPC17_USB_BASE+OHCI_FMREM_OFFSET)
-#define LPC17_USBHOST_FMNO (LPC17_USB_BASE+OHCI_FMNO_OFFSET)
-#define LPC17_USBHOST_PERSTART (LPC17_USB_BASE+OHCI_PERSTART_OFFSET)
-
-/* Root hub ports (section 7.4) */
-
-#define LPC17_USBHOST_LSTHRES (LPC17_USB_BASE+OHCI_LSTHRES_OFFSET)
-#define LPC17_USBHOST_RHDESCA (LPC17_USB_BASE+OHCI_RHDESCA_OFFSET)
-#define LPC17_USBHOST_RHDESCB (LPC17_USB_BASE+OHCI_RHDESCB_OFFSET)
-#define LPC17_USBHOST_RHSTATUS (LPC17_USB_BASE+OHCI_RHSTATUS_OFFSET)
-#define LPC17_USBHOST_RHPORTST1 (LPC17_USB_BASE+OHCI_RHPORTST1_OFFSET)
-#define LPC17_USBHOST_RHPORTST2 (LPC17_USB_BASE+OHCI_RHPORTST2_OFFSET)
-#define LPC17_USBHOST_MODID (LPC17_USB_BASE+LPC17_USBHOST_MODID_OFFSET)
-
-/* USB OTG Controller ***************************************************************/
-/* OTG registers */
-
-#define LPC17_USBOTG_INTST (LPC17_USB_BASE+LPC17_USBOTG_INTST_OFFSET)
-#define LPC17_USBOTG_INTEN (LPC17_USB_BASE+LPC17_USBOTG_INTEN_OFFSET)
-#define LPC17_USBOTG_INTSET (LPC17_USB_BASE+LPC17_USBOTG_INTSET_OFFSET)
-#define LPC17_USBOTG_INTCLR (LPC17_USB_BASE+LPC17_USBOTG_INTCLR_OFFSET)
-#define LPC17_USBOTG_STCTRL (LPC17_USB_BASE+LPC17_USBOTG_STCTRL_OFFSET)
-#define LPC17_USBOTG_TMR (LPC17_USB_BASE+LPC17_USBOTG_TMR_OFFSET)
-
-/* USB Device Controller ************************************************************/
-/* Device interrupt registers. See also SYSCON_USBINTST in lpc17_syscon.h */
-
-#define LPC17_USBDEV_INTST (LPC17_USB_BASE+LPC17_USBDEV_INTST_OFFSET)
-#define LPC17_USBDEV_INTEN (LPC17_USB_BASE+LPC17_USBDEV_INTEN_OFFSET)
-#define LPC17_USBDEV_INTCLR (LPC17_USB_BASE+LPC17_USBDEV_INTCLR_OFFSET)
-#define LPC17_USBDEV_INTSET (LPC17_USB_BASE+LPC17_USBDEV_INTSET_OFFSET)
-
-/* SIE Command registers */
-
-#define LPC17_USBDEV_CMDCODE (LPC17_USB_BASE+LPC17_USBDEV_CMDCODE_OFFSET)
-#define LPC17_USBDEV_CMDDATA (LPC17_USB_BASE+LPC17_USBDEV_CMDDATA_OFFSET)
-
-/* USB transfer registers */
-
-#define LPC17_USBDEV_RXDATA (LPC17_USB_BASE+LPC17_USBDEV_RXDATA_OFFSET)
-#define LPC17_USBDEV_RXPLEN (LPC17_USB_BASE+LPC17_USBDEV_RXPLEN_OFFSET)
-#define LPC17_USBDEV_TXDATA (LPC17_USB_BASE+LPC17_USBDEV_TXDATA_OFFSET)
-#define LPC17_USBDEV_TXPLEN (LPC17_USB_BASE+LPC17_USBDEV_TXPLEN_OFFSET)
-#define LPC17_USBDEV_CTRL (LPC17_USB_BASE+LPC17_USBDEV_CTRL_OFFSET)
-
-/* More Device interrupt registers */
-
-#define LPC17_USBDEV_INTPRI (LPC17_USB_BASE+LPC17_USBDEV_INTPRI_OFFSET)
-
-/* Endpoint interrupt registers */
-
-#define LPC17_USBDEV_EPINTST (LPC17_USB_BASE+LPC17_USBDEV_EPINTST_OFFSET)
-#define LPC17_USBDEV_EPINTEN (LPC17_USB_BASE+LPC17_USBDEV_EPINTEN_OFFSET)
-#define LPC17_USBDEV_EPINTCLR (LPC17_USB_BASE+LPC17_USBDEV_EPINTCLR_OFFSET)
-#define LPC17_USBDEV_EPINTSET (LPC17_USB_BASE+LPC17_USBDEV_EPINTSET_OFFSET)
-#define LPC17_USBDEV_EPINTPRI (LPC17_USB_BASE+LPC17_USBDEV_EPINTPRI_OFFSET)
-
-/* Endpoint realization registers */
-
-#define LPC17_USBDEV_REEP (LPC17_USB_BASE+LPC17_USBDEV_REEP_OFFSET)
-#define LPC17_USBDEV_EPIND (LPC17_USB_BASE+LPC17_USBDEV_EPIND_OFFSET)
-#define LPC17_USBDEV_MAXPSIZE (LPC17_USB_BASE+LPC17_USBDEV_MAXPSIZE_OFFSET)
-
-/* DMA registers */
-
-#define LPC17_USBDEV_DMARST (LPC17_USB_BASE+LPC17_USBDEV_DMARST_OFFSET)
-#define LPC17_USBDEV_DMARCLR (LPC17_USB_BASE+LPC17_USBDEV_DMARCLR_OFFSET)
-#define LPC17_USBDEV_DMARSET (LPC17_USB_BASE+LPC17_USBDEV_DMARSET_OFFSET)
-#define LPC17_USBDEV_UDCAH (LPC17_USB_BASE+LPC17_USBDEV_UDCAH_OFFSET)
-#define LPC17_USBDEV_EPDMAST (LPC17_USB_BASE+LPC17_USBDEV_EPDMAST_OFFSET)
-#define LPC17_USBDEV_EPDMAEN (LPC17_USB_BASE+LPC17_USBDEV_EPDMAEN_OFFSET)
-#define LPC17_USBDEV_EPDMADIS (LPC17_USB_BASE+LPC17_USBDEV_EPDMADIS_OFFSET)
-#define LPC17_USBDEV_DMAINTST (LPC17_USB_BASE+LPC17_USBDEV_DMAINTST_OFFSET)
-#define LPC17_USBDEV_DMAINTEN (LPC17_USB_BASE+LPC17_USBDEV_DMAINTEN_OFFSET)
-#define LPC17_USBDEV_EOTINTST (LPC17_USB_BASE+LPC17_USBDEV_EOTINTST_OFFSET)
-#define LPC17_USBDEV_EOTINTCLR (LPC17_USB_BASE+LPC17_USBDEV_EOTINTCLR_OFFSET)
-#define LPC17_USBDEV_EOTINTSET (LPC17_USB_BASE+LPC17_USBDEV_EOTINTSET_OFFSET)
-#define LPC17_USBDEV_NDDRINTST (LPC17_USB_BASE+LPC17_USBDEV_NDDRINTST_OFFSET)
-#define LPC17_USBDEV_NDDRINTCLR (LPC17_USB_BASE+LPC17_USBDEV_NDDRINTCLR_OFFSET)
-#define LPC17_USBDEV_NDDRINTSET (LPC17_USB_BASE+LPC17_USBDEV_NDDRINTSET_OFFSET)
-#define LPC17_USBDEV_SYSERRINTST (LPC17_USB_BASE+LPC17_USBDEV_SYSERRINTST_OFFSET)
-#define LPC17_USBDEV_SYSERRINTCLR (LPC17_USB_BASE+LPC17_USBDEV_SYSERRINTCLR_OFFSET)
-#define LPC17_USBDEV_SYSERRINTSET (LPC17_USB_BASE+LPC17_USBDEV_SYSERRINTSET_OFFSET)
-
-/* OTG I2C registers ****************************************************************/
-
-#define LPC17_OTGI2C_RX (LPC17_USB_BASE+LPC17_OTGI2C_RX_OFFSET)
-#define LPC17_OTGI2C_TX (LPC17_USB_BASE+LPC17_OTGI2C_TX_OFFSET)
-#define LPC17_OTGI2C_STS (LPC17_USB_BASE+LPC17_OTGI2C_STS_OFFSET)
-#define LPC17_OTGI2C_CTL (LPC17_USB_BASE+LPC17_OTGI2C_CTL_OFFSET)
-#define LPC17_OTGI2C_CLKHI (LPC17_USB_BASE+LPC17_OTGI2C_CLKHI_OFFSET)
-#define LPC17_OTGI2C_CLKLO (LPC17_USB_BASE+LPC17_OTGI2C_CLKLO_OFFSET)
-
-/* Clock control registers ***********************************************************/
-
-#define LPC17_USBOTG_CLKCTRL (LPC17_USB_BASE+LPC17_USBOTG_CLKCTRL_OFFSET)
-#define LPC17_USBOTG_CLKST (LPC17_USB_BASE+LPC17_USBOTG_CLKST_OFFSET)
-
-#define LPC17_USBDEV_CLKCTRL (LPC17_USB_BASE+LPC17_USBDEV_CLKCTRL_OFFSET)
-#define LPC17_USBDEV_CLKST (LPC17_USB_BASE+LPC17_USBDEV_CLKST_OFFSET)
-
-/* Register bit definitions *********************************************************/
-/* USB Host Controller (OHCI) *******************************************************/
-/* See include/nuttx/usb/ohci.h */
-
-/* Module ID/Revision ID */
-
-#define USBHOST_MODID_VER_SHIFT (0) /* Bits 0-7: Unique version number */
-#define USBHOST_MODID_VER_MASK (0xff << USBHOST_MODID_VER_SHIFT)
-#define USBHOST_MODID_REV_SHIFT (8) /* Bits 9-15: Unique revision number */
-#define USBHOST_MODID_REV_MASK (0xff << USBHOST_MODID_REV_SHIFT)
-#define USBHOST_MODID_3505_SHIFT (16) /* Bits 16-31: 0x3505 */
-#define USBHOST_MODID_3505_MASK (0xffff << USBHOST_MODID_3505_SHIFT)
-# define USBHOST_MODID_3505 (0x3505 << USBHOST_MODID_3505_SHIFT)
-
-/* USB OTG Controller ***************************************************************/
-/* OTG registers:
- *
- * OTG Interrupt Status, OTG Interrupt Enable, OTG Interrupt Set, AND OTG Interrupt
- * Clear
- */
-
-#define USBOTG_INT_TMR (1 << 0) /* Bit 0: Timer time-out */
-#define USBOTG_INT_REMOVE_PU (1 << 1) /* Bit 1: Remove pull-up */
-#define USBOTG_INT_HNP_FAILURE (1 << 2) /* Bit 2: HNP failed */
-#define USBOTG_INT_HNP_SUCCESS (1 << 3) /* Bit 3: HNP succeeded */
- /* Bits 4-31: Reserved */
-/* OTG Status and Control */
-
-#define USBOTG_STCTRL_PORTFUNC_SHIFT (0) /* Bits 0-1: Controls port function */
-#define USBOTG_STCTRL_PORTFUNC_MASK (3 << USBOTG_STCTRL_PORTFUNC_SHIFT)
-# define USBOTG_STCTRL_PORTFUNC_HNPOK (1 << USBOTG_STCTRL_PORTFUNC_SHIFT) /* HNP suceeded */
-#define USBOTG_STCTRL_TMRSCALE_SHIFT (2) /* Bits 2-3: Timer scale selection */
-#define USBOTG_STCTRL_TMRSCALE_MASK (3 << USBOTG_STCTRL_TMR_SCALE_SHIFT)
-# define USBOTG_STCTRL_TMRSCALE_10US (0 << USBOTG_STCTRL_TMR_SCALE_SHIFT) /* 10uS (100 KHz) */
-# define USBOTG_STCTRL_TMRSCALE_100US (1 << USBOTG_STCTRL_TMR_SCALE_SHIFT) /* 100uS (10 KHz) */
-# define USBOTG_STCTRL_TMRSCALE_1000US (2 << USBOTG_STCTRL_TMR_SCALE_SHIFT) /* 1000uS (1 KHz) */
-#define USBOTG_STCTRL_TMRMODE (1 << 4) /* Bit 4: Timer mode selection */
-#define USBOTG_STCTRL_TMREN (1 << 5) /* Bit 5: Timer enable */
-#define USBOTG_STCTRL_TMRRST (1 << 6) /* Bit 6: TTimer reset */
- /* Bit 7: Reserved */
-#define USBOTG_STCTRL_BHNPTRACK (1 << 8) /* Bit 8: Enable HNP tracking for B-device (peripheral) */
-#define USBOTG_STCTRL_AHNPTRACK (1 << 9) /* Bit 9: Enable HNP tracking for A-device (host) */
-#define USBOTG_STCTRL_PUREMOVED (1 << 10) /* Bit 10: Set when D+ pull-up removed */
- /* Bits 11-15: Reserved */
-#define USBOTG_STCTRL_TMRCNT_SHIFT (0) /* Bits 16-313: Timer scale selection */
-#define USBOTG_STCTRL_TMRCNT_MASK (0ffff << USBOTG_STCTRL_TMR_CNT_SHIFT)
-
-/* OTG Timer */
-
-#define USBOTG_TMR_TIMEOUTCNT_SHIFT (0) /* Bits 0-15: Interrupt when CNT matches this */
-#define USBOTG_TMR_TIMEOUTCNT_MASK (0xffff << USBOTG_TMR_TIMEOUTCNT_SHIFT)
- /* Bits 16-31: Reserved */
-
-/* USB Device Controller ************************************************************/
-/* Device interrupt registers. See also SYSCON_USBINTST in lpc17_syscon.h */
-/* USB Device Interrupt Status, USB Device Interrupt Enable, USB Device Interrupt
- * Clear, USB Device Interrupt Set, and USB Device Interrupt Priority
- */
-
-#define USBDEV_INT_FRAME (1 << 0) /* Bit 0: frame interrupt (every 1 ms) */
-#define USBDEV_INT_EPFAST (1 << 1) /* Bit 1: Fast endpoint interrupt */
-#define USBDEV_INT_EPSLOW (1 << 2) /* Bit 2: Slow endpoints interrupt */
-#define USBDEV_INT_DEVSTAT (1 << 3) /* Bit 3: Bus reset, suspend change or connect change */
-#define USBDEV_INT_CCEMPTY (1 << 4) /* Bit 4: Command code register empty */
-#define USBDEV_INT_CDFULL (1 << 5) /* Bit 5: Command data register full */
-#define USBDEV_INT_RXENDPKT (1 << 6) /* Bit 6: RX endpoint data transferred */
-#define USBDEV_INT_TXENDPKT (1 << 7) /* Bit 7: TX endpoint data tansferred */
-#define USBDEV_INT_EPRLZED (1 << 8) /* Bit 8: Endpoints realized */
-#define USBDEV_INT_ERRINT (1 << 9) /* Bit 9: Error Interrupt */
- /* Bits 10-31: Reserved */
-/* SIE Command registers:
- *
- * USB Command Code
- */
- /* Bits 0-7: Reserved */
-#define USBDEV_CMDCODE_PHASE_SHIFT (8) /* Bits 8-15: Command phase */
-#define USBDEV_CMDCODE_PHASE_MASK (0xff << USBDEV_CMDCODE_PHASE_SHIFT)
-# define USBDEV_CMDCODE_PHASE_READ (1 << USBDEV_CMDCODE_PHASE_SHIFT)
-# define USBDEV_CMDCODE_PHASE_WRITE (2 << USBDEV_CMDCODE_PHASE_SHIFT)
-# define USBDEV_CMDCODE_PHASE_COMMAND (5 << USBDEV_CMDCODE_PHASE_SHIFT)
-#define USBDEV_CMDCODE_CMD_SHIFT (16) /* Bits 15-23: Command (READ/COMMAND phases) */
-#define USBDEV_CMDCODE_CMD_MASK (0xff << USBDEV_CMDCODE_CMD_SHIFT)
-#define USBDEV_CMDCODE_WDATA_SHIFT (16) /* Bits 15-23: Write dagta (WRITE phase) */
-#define USBDEV_CMDCODE_WDATA_MASK (0xff << USBDEV_CMDCODE_CMD_SHIFT)
- /* Bits 24-31: Reserved */
-/* USB Command Data */
-
-#define USBDEV_CMDDATA_SHIFT (0) /* Bits 0-7: Command read data */
-#define USBDEV_CMDDATA_MASK (0xff << USBDEV_CMDDATA_SHIFT)
- /* Bits 8-31: Reserved */
-/* USB transfer registers:
- *
- * USB Receive Data (Bits 0-31: Received data)
- */
-
-/* USB Receive Packet Length */
-
-#define USBDEV_RXPLEN_SHIFT (0) /* Bits 0-9: Bytes remaining to be read */
-#define USBDEV_RXPLEN_MASK (0x3ff << USBDEV_RXPLEN_SHIFT)
-#define USBDEV_RXPLEN_DV (1 << 10) /* Bit 10: DV Data valid */
-#define USBDEV_RXPLEN_PKTRDY (1 << 11) /* Bit 11: Packet ready for reading */
- /* Bits 12-31: Reserved */
-/* USB Transmit Data (Bits 0-31: Transmit data) */
-
-/* USB Transmit Packet Length */
-
-#define USBDEV_TXPLEN_SHIFT (0) /* Bits 0-9: Bytes remaining to be written */
-#define USBDEV_TXPLEN_MASK (0x3ff << USBDEV_TXPLEN_SHIFT)
- /* Bits 10-31: Reserved */
-/* USB Control */
-
-#define USBDEV_CTRL_RDEN (1 << 0) /* Bit 0: Read mode control */
-#define USBDEV_CTRL_WREN (1 << 1) /* Bit 1: Write mode control */
-#define USBDEV_CTRL_LOGEP_SHIFT (2) /* Bits 2-5: Logical Endpoint number */
-#define USBDEV_CTRL_LOGEP_MASK (15 << USBDEV_CTRL_LOGEP_SHIFT)
- /* Bits 6-31: Reserved */
-/* Endpoint interrupt registers:
- *
- * USB Endpoint Interrupt Status, USB Endpoint Interrupt Enable, USB Endpoint Interrupt
- * Clear, USB Endpoint Interrupt Set, and USB Endpoint Priority. Bits correspond
- * to on RX or TX value for any of 15 logical endpoints).
- */
-
-#define USBDEV_LOGEPRX(n) (1 << ((n) << 1))
-#define USBDEV_LOGEPTX(n) ((1 << ((n) << 1)) + 1)
-#define USBDEV_LOGEPRX0 (1 << 0)
-#define USBDEV_LOGEPTX0 (1 << 1)
-#define USBDEV_LOGEPRX1 (1 << 2)
-#define USBDEV_LOGEPTX1 (1 << 3)
-#define USBDEV_LOGEPRX2 (1 << 4)
-#define USBDEV_LOGEPTX2 (1 << 5)
-#define USBDEV_LOGEPRX3 (1 << 6)
-#define USBDEV_LOGEPTX3 (1 << 7)
-#define USBDEV_LOGEPRX4 (1 << 8)
-#define USBDEV_LOGEPTX4 (1 << 9)
-#define USBDEV_LOGEPRX5 (1 << 10)
-#define USBDEV_LOGEPTX5 (1 << 11)
-#define USBDEV_LOGEPRX6 (1 << 12)
-#define USBDEV_LOGEPTX6 (1 << 13)
-#define USBDEV_LOGEPRX7 (1 << 14)
-#define USBDEV_LOGEPTX7 (1 << 15)
-#define USBDEV_LOGEPRX8 (1 << 16)
-#define USBDEV_LOGEPTX8 (1 << 17)
-#define USBDEV_LOGEPRX9 (1 << 18)
-#define USBDEV_LOGEPTX9 (1 << 19)
-#define USBDEV_LOGEPRX10 (1 << 20)
-#define USBDEV_LOGEPTX10 (1 << 21)
-#define USBDEV_LOGEPRX11 (1 << 22)
-#define USBDEV_LOGEPTX11 (1 << 23)
-#define USBDEV_LOGEPRX12 (1 << 24)
-#define USBDEV_LOGEPTX12 (1 << 25)
-#define USBDEV_LOGEPRX13 (1 << 26)
-#define USBDEV_LOGEPTX13 (1 << 27)
-#define USBDEV_LOGEPRX14 (1 << 28)
-#define USBDEV_LOGEPTX14 (1 << 29)
-#define USBDEV_LOGEPRX15 (1 << 30)
-#define USBDEV_LOGEPTX15 (1 << 31)
-
-/* Endpoint realization registers:
- *
- * USB Realize Endpoint (Bits correspond to 1 of 32 physical endpoints)
- */
-
-#define USBDEV_PHYEP(n) (1 << (n))
-#define USBDEV_PHYEP0 (1 << 0)
-#define USBDEV_PHYEP1 (1 << 1)
-#define USBDEV_PHYEP2 (1 << 2)
-#define USBDEV_PHYEP3 (1 << 3)
-#define USBDEV_PHYEP4 (1 << 4)
-#define USBDEV_PHYEP5 (1 << 5)
-#define USBDEV_PHYEP6 (1 << 6)
-#define USBDEV_PHYEP7 (1 << 7)
-#define USBDEV_PHYEP8 (1 << 8)
-#define USBDEV_PHYEP9 (1 << 9)
-#define USBDEV_PHYEP10 (1 << 10)
-#define USBDEV_PHYEP11 (1 << 11)
-#define USBDEV_PHYEP12 (1 << 12)
-#define USBDEV_PHYEP13 (1 << 13)
-#define USBDEV_PHYEP14 (1 << 14)
-#define USBDEV_PHYEP15 (1 << 15)
-#define USBDEV_PHYEP16 (1 << 16)
-#define USBDEV_PHYEP17 (1 << 17)
-#define USBDEV_PHYEP18 (1 << 18)
-#define USBDEV_PHYEP19 (1 << 19)
-#define USBDEV_PHYEP20 (1 << 20)
-#define USBDEV_PHYEP21 (1 << 21)
-#define USBDEV_PHYEP22 (1 << 22)
-#define USBDEV_PHYEP23 (1 << 23)
-#define USBDEV_PHYEP24 (1 << 24)
-#define USBDEV_PHYEP25 (1 << 25)
-#define USBDEV_PHYEP26 (1 << 26)
-#define USBDEV_PHYEP27 (1 << 27)
-#define USBDEV_PHYEP28 (1 << 28)
-#define USBDEV_PHYEP29 (1 << 29)
-#define USBDEV_PHYEP30 (1 << 30)
-#define USBDEV_PHYEP31 (1 << 31)
-
-/* USB Endpoint Index */
-
-#define USBDEV_EPIND_SHIFT (0) /* Bits 0-4: Physical endpoint number (0-31) */
-#define USBDEV_EPIND_MASK (31 << USBDEV_EPIND_SHIFT)
- /* Bits 5-31: Reserved */
-/* USB MaxPacketSize */
-
-#define USBDEV_MAXPSIZE_SHIFT (0) /* Bits 0-9: Maximum packet size value */
-#define USBDEV_MAXPSIZE_MASK (0x3ff << USBDEV_MAXPSIZE_SHIFT)
- /* Bits 10-31: Reserved */
-/* DMA registers:
- *
- * USB DMA Request Status, USB DMA Request Clear, and USB DMA Request Set. Registers
- * contain bits for each of 32 physical endpoints. Use the USBDEV_PHYEP* definitions
- * above. PHYEP0-1 (bits 0-1) must be zero.
- */
-
-/* USB UDCA Head */
- /* Bits 0-6: Reserved */
-#define USBDEV_UDCAH_SHIFT (7) /* Bits 7-31: UDCA start address */
-#define USBDEV_UDCAH_MASK (0x01ffffff << USBDEV_UDCAH_SHIFT)
-
-/* USB Endpoint DMA Status, USB Endpoint DMA Enable, and USB Endpoint DMA Disable.
- * Registers contain bits for physical endpoints 2-31. Use the USBDEV_PHYEP*
- * definitions above. PHYEP0-1 (bits 0-1) must be zero.
- */
-
-/* USB DMA Interrupt Status and USB DMA Interrupt Enable */
-
-#define USBDEV_DMAINT_EOT (1 << 0) /* Bit 0: End of Transfer Interrupt */
-#define USBDEV_DMAINT_NDDR (1 << 1) /* Bit 1: New DD Request Interrupt */
-#define USBDEV_DMAINT_ERR (1 << 2) /* Bit 2: System Error Interrupt */
- /* Bits 3-31: Reserved */
-/* USB End of Transfer Interrupt Status, USB End of Transfer Interrupt Clear, and USB
- * End of Transfer Interrupt Set. Registers contain bits for physical endpoints 2-31.
- * Use the USBDEV_PHYEP* definitions above. PHYEP0-1 (bits 0-1) must be zero.
- */
-
-/* USB New DD Request Interrupt Status, USB New DD Request Interrupt Clear, and USB
- * New DD Request Interrupt Set. Registers contain bits for physical endpoints 2-31.
- * Use the USBDEV_PHYEP* definitions above. PHYEP0-1 (bits 0-1) must be zero.
- */
-
-/* USB System Error Interrupt Status, USB System Error Interrupt Clear, USB System
- * Error Interrupt Set. Registers contain bits for physical endpoints 2-31. Use
- * the USBDEV_PHYEP* definitions above. PHYEP0-1 (bits 0-1) must be zero.
- */
-
-/* OTG I2C registers ****************************************************************/
-
-/* I2C Receive */
-
-#define OTGI2C_RX_DATA_SHIFT (0) /* Bits 0-7: RX data */
-#define OTGI2C_RX_DATA_MASK (0xff << OTGI2C_RX_SHIFT)
- /* Bits 8-31: Reserved */
-/* I2C Transmit */
-
-#define OTGI2C_TX_DATA_SHIFT (0) /* Bits 0-7: TX data */
-#define OTGI2C_TX_DATA_MASK (0xff << OTGI2C_TX_DATA_SHIFT)
-#define OTGI2C_TX_DATA_START (1 << 8) /* Bit 8: Issue START before transmit */
-#define OTGI2C_TX_DATA_STOP (1 << 9) /* Bit 9: Issue STOP before transmit */
- /* Bits 3-31: Reserved */
-/* I2C Status */
-
-#define OTGI2C_STS_TDI (1 << 0) /* Bit 0: Transaction Done Interrupt */
-#define OTGI2C_STS_AFI (1 << 1) /* Bit 1: Arbitration Failure Interrupt */
-#define OTGI2C_STS_NAI (1 << 2) /* Bit 2: No Acknowledge Interrupt */
-#define OTGI2C_STS_DRMI (1 << 3) /* Bit 3: Master Data Request Interrupt */
-#define OTGI2C_STS_DRSI (1 << 4) /* Bit 4: Slave Data Request Interrupt */
-#define OTGI2C_STS_ACTIVE (1 << 5) /* Bit 5: Indicates whether the bus is busy */
-#define OTGI2C_STS_SCL (1 << 6) /* Bit 6: The current value of the SCL signal */
-#define OTGI2C_STS_SDA (1 << 7) /* Bit 7: The current value of the SDA signal */
-#define OTGI2C_STS_RFF (1 << 8) /* Bit 8: Receive FIFO Full (RFF) */
-#define OTGI2C_STS_RFE (1 << 9) /* Bit 9: Receive FIFO Empty */
-#define OTGI2C_STS_TFF (1 << 10) /* Bit 10: Transmit FIFO Full */
-#define OTGI2C_STS_TFE (1 << 11) /* Bit 11: Transmit FIFO Empty */
- /* Bits 12-31: Reserved */
-/* I2C Control */
-
-#define OTGI2C_CTL_TDIE (1 << 0) /* Bit 0: Transmit Done Interrupt Enable */
-#define OTGI2C_CTL_AFIE (1 << 1) /* Bit 1: Transmitter Arbitration Failure Interrupt Enable */
-#define OTGI2C_CTL_NAIE (1 << 2) /* Bit 2: Transmitter No Acknowledge Interrupt Enable */
-#define OTGI2C_CTL_DRMIE (1 << 3) /* Bit 3: Master Transmitter Data Request Interrupt Enable */
-#define OTGI2C_CTL_DRSIE (1 << 4) /* Bit 4: Slave Transmitter Data Request Interrupt Enable */
-#define OTGI2C_CTL_REFIE (1 << 5) /* Bit 5: Receive FIFO Full Interrupt Enable */
-#define OTGI2C_CTL_RFDAIE (1 << 6) /* Bit 6: Receive Data Available Interrupt Enable */
-#define OTGI2C_CTL_TFFIE (1 << 7) /* Bit 7: Transmit FIFO Not Full Interrupt Enable */
-#define OTGI2C_CTL_SRST (1 << 8) /* Bit 8: Soft reset */
- /* Bits 9-31: Reserved */
-/* I2C Clock High */
-
-#define OTGI2C_CLKHI_SHIFT (0) /* Bits 0-7: Clock divisor high */
-#define OTGI2C_CLKHI_MASK (0xff << OTGI2C_CLKHI_SHIFT)
- /* Bits 8-31: Reserved */
-/* I2C Clock Low */
-
-#define OTGI2C_CLKLO_SHIFT (0) /* Bits 0-7: Clock divisor high */
-#define OTGI2C_CLLO_MASK (0xff << OTGI2C_CLKLO_SHIFT)
- /* Bits 8-31: Reserved */
-/* Clock control registers ***********************************************************/
-
-/* USB Clock Control (OTG clock controller) and USB Clock Status (OTG clock status) */
-
-#define USBDEV_CLK_HOSTCLK (1 << 0) /* Bit 1: Host clock (OTG only) */
-#define USBDEV_CLK_DEVCLK (1 << 1) /* Bit 1: Device clock */
-#define USBDEV_CLK_I2CCLK (1 << 2) /* Bit 2: I2C clock (OTG only) */
-#define USBDEV_CLK_PORTSELCLK (1 << 3) /* Bit 3: Port select register clock (device only) */
-#define USBDEV_CLK_OTGCLK (1 << 3) /* Bit 3: OTG clock (OTG only) */
-#define USBDEV_CLK_AHBCLK (1 << 4) /* Bit 4: AHB clock */
- /* Bits 5-31: Reserved */
-/* Alternate naming */
-
-#define USBOTG_CLK_HOSTCLK USBDEV_CLK_HOSTCLK
-#define USBOTG_CLK_DEVCLK USBDEV_CLK_DEVCLK
-#define USBOTG_CLK_I2CCLK USBDEV_CLK_I2CCLK
-#define USBOTG_CLK_PORTSELCLK USBDEV_CLK_PORTSELCLK
-#define USBOTG_CLK_OTGCLK USBDEV_CLK_OTGCLK
-#define USBOTG_CLK_AHBCLK USBDEV_CLK_AHBCLK
-
-/* Endpoints *************************************************************************/
-
-#define LPC17_EP0_OUT 0
-#define LPC17_EP0_IN 1
-#define LPC17_CTRLEP_OUT LPC17_EP0_OUT
-#define LPC17_CTRLEP_IN LPC17_EP0_IN
-#define LPC17_EP1_OUT 2
-#define LPC17_EP1_IN 3
-#define LPC17_EP2_OUT 4
-#define LPC17_EP2_IN 5
-#define LPC17_EP3_OUT 6
-#define LPC17_EP3_IN 7
-#define LPC17_EP4_OUT 8
-#define LPC17_EP4_IN 9
-#define LPC17_EP5_OUT 10
-#define LPC17_EP5_IN 11
-#define LPC17_EP6_OUT 12
-#define LPC17_EP6_IN 13
-#define LPC17_EP7_OUT 14
-#define LPC17_EP7_IN 15
-#define LPC17_EP8_OUT 16
-#define LPC17_EP8_IN 17
-#define LPC17_EP9_OUT 18
-#define LPC17_EP9_IN 19
-#define LPC17_EP10_OUT 20
-#define LPC17_EP10_IN 21
-#define LPC17_EP11_OUT 22
-#define LPC17_EP11_IN 23
-#define LPC17_EP12_OUT 24
-#define LPC17_EP12_IN 25
-#define LPC17_EP13_OUT 26
-#define LPC17_EP13_IN 27
-#define LPC17_EP14_OUT 28
-#define LPC17_EP14_IN 29
-#define LPC17_EP15_OUT 30
-#define LPC17_EP15_IN 31
-#define LPC17_NUMEPS 32
-
-/* Commands *************************************************************************/
-
-/* USB Command Code Register */
-
-#define CMD_USBDEV_PHASESHIFT (8) /* Bits 8-15: Command phase value */
-#define CMD_USBDEV_PHASEMASK (0xff << CMD_USBDEV_PHASESHIFT)
-# define CMD_USBDEV_DATAWR (1 << CMD_USBDEV_PHASESHIFT)
-# define CMD_USBDEV_DATARD (2 << CMD_USBDEV_PHASESHIFT)
-# define CMD_USBDEV_CMDWR (5 << CMD_USBDEV_PHASESHIFT)
-#define CMD_USBDEV_CMDSHIFT (16) /* Bits 16-23: Device command/WDATA */
-#define CMD_USBDEV_CMDMASK (0xff << CMD_USBDEV_CMDSHIFT)
-#define CMD_USBDEV_WDATASHIFT CMD_USBDEV_CMDSHIFT
-#define CMD_USBDEV_WDATAMASK CMD_USBDEV_CMDMASK
-
-/* Device Commands */
-
-#define CMD_USBDEV_SETADDRESS (0x00d0)
-#define CMD_USBDEV_CONFIG (0x00d8)
-#define CMD_USBDEV_SETMODE (0x00f3)
-#define CMD_USBDEV_READFRAMENO (0x00f5)
-#define CMD_USBDEV_READTESTREG (0x00fd)
-#define CMD_USBDEV_SETSTATUS (0x01fe) /* Bit 8 set to distingish get from set */
-#define CMD_USBDEV_GETSTATUS (0x00fe)
-#define CMD_USBDEV_GETERRORCODE (0x00ff)
-#define CMD_USBDEV_READERRORSTATUS (0x00fb)
-
-/* Endpoint Commands */
-
-#define CMD_USBDEV_EPSELECT (0x0000)
-#define CMD_USBDEV_EPSELECTCLEAR (0x0040)
-#define CMD_USBDEV_EPSETSTATUS (0x0140) /* Bit 8 set to distingish get from selectclear */
-#define CMD_USBDEV_EPCLRBUFFER (0x00f2)
-#define CMD_USBDEV_EPVALIDATEBUFFER (0x00fa)
-
-/* Command/response bit definitions ********************************************/
-/* SETADDRESS (0xd0) command definitions */
-
-#define CMD_USBDEV_SETADDRESS_MASK (0x7f) /* Bits 0-6: Device address */
-#define CMD_USBDEV_SETADDRESS_DEVEN (1 << 7) /* Bit 7: Device enable */
-
-/* SETSTATUS (0xfe) and GETSTATUS (0xfe) response: */
-
-#define CMD_STATUS_CONNECT (1 << 0) /* Bit 0: Connected */
-#define CMD_STATUS_CONNCHG (1 << 1) /* Bit 1: Connect change */
-#define CMD_STATUS_SUSPEND (1 << 2) /* Bit 2: Suspend */
-#define CMD_STATUS_SUSPCHG (1 << 3) /* Bit 3: Suspend change */
-#define CMD_STATUS_RESET (1 << 4) /* Bit 4: Bus reset bit */
-
-/* EPSELECT (0x00) endpoint status response */
-
-#define CMD_EPSELECT_FE (1 << 0) /* Bit 0: IN empty or OUT full */
-#define CMD_EPSELECT_ST (1 << 1) /* Bit 1: Endpoint is stalled */
-#define CMD_EPSELECT_STP (1 << 2) /* Bit 2: Last packet was setup */
-#define CMD_EPSELECT_PO (1 << 3) /* Bit 3: Previous packet was overwritten */
-#define CMD_EPSELECT_EPN (1 << 4) /* Bit 4: NAK sent */
-#define CMD_EPSELECT_B1FULL (1 << 5) /* Bit 5: Buffer 1 full */
-#define CMD_EPSELECT_B2FULL (1 << 6) /* Bit 6: Buffer 2 full */
- /* Bit 7: Reserved */
-/* EPSETSTATUS (0x40) command */
-
-#define CMD_SETSTAUS_ST (1 << 0) /* Bit 0: Stalled endpoint bit */
- /* Bits 1-4: Reserved */
-#define CMD_SETSTAUS_DA (1 << 5) /* Bit 5: Disabled endpoint bit */
-#define CMD_SETSTAUS_RFMO (1 << 6) /* Bit 6: Rate feedback mode */
-#define CMD_SETSTAUS_CNDST (1 << 7) /* Bit 7: Conditional stall bit */
-
-/* EPCLRBUFFER (0xf2) response */
-
-#define CMD_USBDEV_CLRBUFFER_PO (0x00000001)
-
-/* SETMODE(0xf3) command */
-
-#define CMD_SETMODE_APCLK (1 << 0) /* Bit 0: Always PLL Clock */
-#define CMD_SETMODE_INAKCI (1 << 1) /* Bit 1: Interrupt on NAK for Control IN endpoint */
-#define CMD_SETMODE_INAKCO (1 << 2) /* Bit 2: Interrupt on NAK for Control OUT endpoint */
-#define CMD_SETMODE_INAKII (1 << 3) /* Bit 3: Interrupt on NAK for Interrupt IN endpoint */
-#define CMD_SETMODE_INAKIO (1 << 4) /* Bit 4: Interrupt on NAK for Interrupt OUT endpoints */
-#define CMD_SETMODE_INAKBI (1 << 5) /* Bit 5: Interrupt on NAK for Bulk IN endpoints */
-#define CMD_SETMODE_INAKBO (1 << 6) /* Bit 6: Interrupt on NAK for Bulk OUT endpoints */
-
-/* READERRORSTATUS (0xFb) command */
-
-#define CMD_READERRORSTATUS_PIDERR (1 << 0) /* Bit 0: PID encoding/unknown or Token CRC */
-#define CMD_READERRORSTATUS_UEPKT (1 << 1) /* Bit 1: Unexpected Packet */
-#define CMD_READERRORSTATUS_DCRC (1 << 2) /* Bit 2: Data CRC error */
-#define CMD_READERRORSTATUS_TIMEOUT (1 << 3) /* Bit 3: Time out error */
-#define CMD_READERRORSTATUS_EOP (1 << 4) /* Bit 4: End of packet error */
-#define CMD_READERRORSTATUS_BOVRN (1 << 5) /* Bit 5: Buffer Overrun */
-#define CMD_READERRORSTATUS_BTSTF (1 << 6) /* Bit 6: Bit stuff error */
-#define CMD_READERRORSTATUS_TGLERR (1 << 7) /* Bit 7: Wrong toggle in data PID */
-#define CMD_READERRORSTATUS_ALLERRS (0xff)
-
-/* DMA ******************************************************************************/
-/* The DMA descriptor */
-
-#define USB_DMADESC_NEXTDDPTR 0 /* Offset 0: Next USB descriptor in RAM */
-#define USB_DMADESC_CONFIG 1 /* Offset 1: DMA configuration info. */
-#define USB_DMADESC_STARTADDR 2 /* Offset 2: DMA start address */
-#define USB_DMADESC_STATUS 3 /* Offset 3: DMA status info (read only) */
-#define USB_DMADESC_ISOCSIZEADDR 4 /* Offset 4: Isoc. packet size address */
-
-/* Bit settings for CONFIG (offset 1 )*/
-
-#define USB_DMADESC_MODE_SHIFT (0) /* Bits 0-1: DMA mode */
-#define USB_DMADESC_MODE_MASK (3 << USB_DMADESC_MODE_SHIFT)
-# define USB_DMADESC_MODENORMAL (0 << USB_DMADESC_MODE_SHIFT) /* Mode normal */
-# define USB_DMADESC_MODEATLE (1 << USB_DMADESC_MODE_SHIFT) /* ATLE normal */
-#define USB_DMADESC_NEXTDDVALID (1 << 2) /* Bit 2: Next descriptor valid */
- /* Bit 3: Reserved */
-#define USB_DMADESC_ISCOEP (1 << 4) /* Bit 4: ISOC endpoint */
-#define USB_DMADESC_PKTSIZE_SHIFT (5) /* Bits 5-15: Max packet size */
-#define USB_DMADESC_PKTSIZE_MASK (0x7ff << USB_DMADESC_PKTSIZE_SHIFT)
-#define USB_DMADESC_BUFLEN_SHIFT (16) /* Bits 16-31: DMA buffer length */
-#define USB_DMADESC_BUFLEN_MASK (0xffff << USB_DMADESC_BUFLEN_SHIFT
-
-/* Bit settings for STATUS (offset 3). All must be initialized to zero. */
-
-#define USB_DMADESC_STATUS_SHIFT (1) /* Bits 1-4: DMA status */
-#define USB_DMADESC_STATUS_MASK (15 << USB_DMADESC_STATUS_SHIFT)
-# define USB_DMADESC_NOTSERVICED (0 << USB_DMADESC_STATUS_SHIFT)
-# define USB_DMADESC_BEINGSERVICED (1 << USB_DMADESC_STATUS_SHIFT)
-# define USB_DMADESC_NORMALCOMPLETION (2 << USB_DMADESC_STATUS_SHIFT)
-# define USB_DMADESC_DATAUNDERRUN (3 << USB_DMADESC_STATUS_SHIFT)
-# define USB_DMADESC_DATAOVERRUN (8 << USB_DMADESC_STATUS_SHIFT)
-# define USB_DMADESC_SYSTEMERROR (9 << USB_DMADESC_STATUS_SHIFT)
-#define USB_DMADESC_PKTVALID (1 << 5) /* Bit 5: Packet valid */
-#define USB_DMADESC_LSBEXTRACTED (1 << 6) /* Bit 6: LS byte extracted */
-#define USB_DMADESC_MSBEXTRACTED (1 << 7) /* Bit 7: MS byte extracted */
-#define USB_DMADESC_MSGLENPOS_SHIFT (8) /* Bits 8-13: Message length position */
-#define USB_DMADESC_MSGLENPOS_MASK (0x3f << USB_DMADESC_MSGLENPOS_SHIFT)
-#define USB_DMADESC_DMACOUNT_SHIFT (16) /* Bits 16-31: DMA count */
-#define USB_DMADESC_DMACOUNT_MASK (0xffff << USB_DMADESC_DMACOUNT_SHIFT)
-
-/* DMA packet size format */
-
-#define USB_DMAPKTSIZE_PKTLEN_SHIFT (0) /* Bits 0-15: Packet length */
-#define USB_DMAPKTSIZE_PKTLEN_MASK (0xffff << USB_DMAPKTSIZE_PKTLEN_SHIFT)
-#define USB_DMAPKTSIZE_PKTVALID (1 << 16) /* Bit 16: Packet valid */
-#define USB_DMAPKTSIZE_FRAMENO_SHIFT (17) /* Bit 17-31: Frame number */
-#define USB_DMAPKTSIZE_FRAMENO_MASK (0x7fff << USB_DMAPKTSIZE_FRAMENO_SHIFT)
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-/************************************************************************************
- * Public Functions
- ************************************************************************************/
-
-#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_USB_H */
+/************************************************************************************ + * arch/arm/src/lpc17xx/lpc17_usb.h + * + * Copyright (C) 2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_USB_H +#define __ARCH_ARM_SRC_LPC17XX_LPC17_USB_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> +#include <nuttx/usb/ohci.h> + +#include "chip.h" +#include "lpc17_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register offsets *****************************************************************/ +/* USB Host Controller (OHCI) *******************************************************/ +/* See include/nuttx/usb/ohci.h */ + +#define LPC17_USBHOST_MODID_OFFSET 0x00fc /* Module ID/Revision ID */ + +/* USB OTG Controller ***************************************************************/ +/* OTG registers */ + +#define LPC17_USBOTG_INTST_OFFSET 0x0100 /* OTG Interrupt Status */ +#define LPC17_USBOTG_INTEN_OFFSET 0x0104 /* OTG Interrupt Enable */ +#define LPC17_USBOTG_INTSET_OFFSET 0x0108 /* OTG Interrupt Set */ +#define LPC17_USBOTG_INTCLR_OFFSET 0x010c /* OTG Interrupt Clear */ +#define LPC17_USBOTG_STCTRL_OFFSET 0x0110 /* OTG Status and Control */ +#define LPC17_USBOTG_TMR_OFFSET 0x0114 /* OTG Timer */ + +/* USB Device Controller ************************************************************/ +/* Device interrupt registers. See also SYSCON_USBINTST in lpc17_syscon.h */ + +#define LPC17_USBDEV_INTST_OFFSET 0x0200 /* USB Device Interrupt Status */ +#define LPC17_USBDEV_INTEN_OFFSET 0x0204 /* USB Device Interrupt Enable */ +#define LPC17_USBDEV_INTCLR_OFFSET 0x0208 /* USB Device Interrupt Clear */ +#define LPC17_USBDEV_INTSET_OFFSET 0x020c /* USB Device Interrupt Set */ + +/* SIE Command registers */ + +#define LPC17_USBDEV_CMDCODE_OFFSET 0x0210 /* USB Command Code */ +#define LPC17_USBDEV_CMDDATA_OFFSET 0x0214 /* USB Command Data */ + +/* USB transfer registers */ + +#define LPC17_USBDEV_RXDATA_OFFSET 0x0218 /* USB Receive Data */ +#define LPC17_USBDEV_RXPLEN_OFFSET 0x0220 /* USB Receive Packet Length */ +#define LPC17_USBDEV_TXDATA_OFFSET 0x021c /* USB Transmit Data */ +#define LPC17_USBDEV_TXPLEN_OFFSET 0x0224 /* USB Transmit Packet Length */ +#define LPC17_USBDEV_CTRL_OFFSET 0x0228 /* USB Control */ + +/* More Device interrupt registers */ + +#define LPC17_USBDEV_INTPRI_OFFSET 0x022c /* USB Device Interrupt Priority */ + +/* Endpoint interrupt registers */ + +#define LPC17_USBDEV_EPINTST_OFFSET 0x0230 /* USB Endpoint Interrupt Status */ +#define LPC17_USBDEV_EPINTEN_OFFSET 0x0234 /* USB Endpoint Interrupt Enable */ +#define LPC17_USBDEV_EPINTCLR_OFFSET 0x0238 /* USB Endpoint Interrupt Clear */ +#define LPC17_USBDEV_EPINTSET_OFFSET 0x023c /* USB Endpoint Interrupt Set */ +#define LPC17_USBDEV_EPINTPRI_OFFSET 0x0240 /* USB Endpoint Priority */ + +/* Endpoint realization registers */ + +#define LPC17_USBDEV_REEP_OFFSET 0x0244 /* USB Realize Endpoint */ +#define LPC17_USBDEV_EPIND_OFFSET 0x0248 /* USB Endpoint Index */ +#define LPC17_USBDEV_MAXPSIZE_OFFSET 0x024c /* USB MaxPacketSize */ + +/* DMA registers */ + +#define LPC17_USBDEV_DMARST_OFFSET 0x0250 /* USB DMA Request Status */ +#define LPC17_USBDEV_DMARCLR_OFFSET 0x0254 /* USB DMA Request Clear */ +#define LPC17_USBDEV_DMARSET_OFFSET 0x0258 /* USB DMA Request Set */ +#define LPC17_USBDEV_UDCAH_OFFSET 0x0280 /* USB UDCA Head */ +#define LPC17_USBDEV_EPDMAST_OFFSET 0x0284 /* USB Endpoint DMA Status */ +#define LPC17_USBDEV_EPDMAEN_OFFSET 0x0288 /* USB Endpoint DMA Enable */ +#define LPC17_USBDEV_EPDMADIS_OFFSET 0x028c /* USB Endpoint DMA Disable */ +#define LPC17_USBDEV_DMAINTST_OFFSET 0x0290 /* USB DMA Interrupt Status */ +#define LPC17_USBDEV_DMAINTEN_OFFSET 0x0294 /* USB DMA Interrupt Enable */ +#define LPC17_USBDEV_EOTINTST_OFFSET 0x02a0 /* USB End of Transfer Interrupt Status */ +#define LPC17_USBDEV_EOTINTCLR_OFFSET 0x02a4 /* USB End of Transfer Interrupt Clear */ +#define LPC17_USBDEV_EOTINTSET_OFFSET 0x02a8 /* USB End of Transfer Interrupt Set */ +#define LPC17_USBDEV_NDDRINTST_OFFSET 0x02ac /* USB New DD Request Interrupt Status */ +#define LPC17_USBDEV_NDDRINTCLR_OFFSET 0x02b0 /* USB New DD Request Interrupt Clear */ +#define LPC17_USBDEV_NDDRINTSET_OFFSET 0x02b4 /* USB New DD Request Interrupt Set */ +#define LPC17_USBDEV_SYSERRINTST_OFFSET 0x02b8 /* USB System Error Interrupt Status */ +#define LPC17_USBDEV_SYSERRINTCLR_OFFSET 0x02bc /* USB System Error Interrupt Clear */ +#define LPC17_USBDEV_SYSERRINTSET_OFFSET 0x02c0 /* USB System Error Interrupt Set */ + +/* OTG I2C registers ****************************************************************/ + +#define LPC17_OTGI2C_RX_OFFSET 0x0300 /* I2C Receive */ +#define LPC17_OTGI2C_TX_OFFSET 0x0300 /* I2C Transmit */ +#define LPC17_OTGI2C_STS_OFFSET 0x0304 /* I2C Status */ +#define LPC17_OTGI2C_CTL_OFFSET 0x0308 /* I2C Control */ +#define LPC17_OTGI2C_CLKHI_OFFSET 0x030c /* I2C Clock High */ +#define LPC17_OTGI2C_CLKLO_OFFSET 0x0310 /* I2C Clock Low */ + +/* Clock control registers ***********************************************************/ + +#define LPC17_USBOTG_CLKCTRL_OFFSET 0x0ff4 /* OTG clock controller */ +#define LPC17_USBOTG_CLKST_OFFSET 0x0ff8 /* OTG clock status */ + +#define LPC17_USBDEV_CLKCTRL_OFFSET 0x0ff4 /* USB Clock Control */ +#define LPC17_USBDEV_CLKST_OFFSET 0x0ff8 /* USB Clock Status */ + +/* Register addresses ***************************************************************/ +/* USB Host Controller (OHCI) *******************************************************/ +/* Control and status registers (section 7.1) */ + +#define LPC17_USBHOST_HCIREV (LPC17_USB_BASE+OHCI_HCIREV_OFFSET) +#define LPC17_USBHOST_CTRL (LPC17_USB_BASE+OHCI_CTRL_OFFSET) +#define LPC17_USBHOST_CMDST (LPC17_USB_BASE+OHCI_CMDST_OFFSET) +#define LPC17_USBHOST_INTST (LPC17_USB_BASE+OHCI_INTST_OFFSET) +#define LPC17_USBHOST_INTEN (LPC17_USB_BASE+OHCI_INTEN_OFFSET) +#define LPC17_USBHOST_INTDIS (LPC17_USB_BASE+OHCI_INTDIS_OFFSET) + +/* Memory pointers (section 7.2) */ + +#define LPC17_USBHOST_HCCA (LPC17_USB_BASE+OHCI_HCCA_OFFSET) +#define LPC17_USBHOST_PERED (LPC17_USB_BASE+OHCI_PERED_OFFSET) +#define LPC17_USBHOST_CTRLHEADED (LPC17_USB_BASE+OHCI_CTRLHEADED_OFFSET) +#define LPC17_USBHOST_CTRLED (LPC17_USB_BASE+OHCI_CTRLED_OFFSET) +#define LPC17_USBHOST_BULKHEADED (LPC17_USB_BASE+OHCI_BULKHEADED_OFFSET) +#define LPC17_USBHOST_BULKED (LPC17_USB_BASE+OHCI_BULKED_OFFSET) +#define LPC17_USBHOST_DONEHEAD (LPC17_USB_BASE+OHCI_DONEHEAD_OFFSET) + +/* Frame counters (section 7.3) */ + +#define LPC17_USBHOST_FMINT (LPC17_USB_BASE+OHCI_FMINT_OFFSET) +#define LPC17_USBHOST_FMREM (LPC17_USB_BASE+OHCI_FMREM_OFFSET) +#define LPC17_USBHOST_FMNO (LPC17_USB_BASE+OHCI_FMNO_OFFSET) +#define LPC17_USBHOST_PERSTART (LPC17_USB_BASE+OHCI_PERSTART_OFFSET) + +/* Root hub ports (section 7.4) */ + +#define LPC17_USBHOST_LSTHRES (LPC17_USB_BASE+OHCI_LSTHRES_OFFSET) +#define LPC17_USBHOST_RHDESCA (LPC17_USB_BASE+OHCI_RHDESCA_OFFSET) +#define LPC17_USBHOST_RHDESCB (LPC17_USB_BASE+OHCI_RHDESCB_OFFSET) +#define LPC17_USBHOST_RHSTATUS (LPC17_USB_BASE+OHCI_RHSTATUS_OFFSET) +#define LPC17_USBHOST_RHPORTST1 (LPC17_USB_BASE+OHCI_RHPORTST1_OFFSET) +#define LPC17_USBHOST_RHPORTST2 (LPC17_USB_BASE+OHCI_RHPORTST2_OFFSET) +#define LPC17_USBHOST_MODID (LPC17_USB_BASE+LPC17_USBHOST_MODID_OFFSET) + +/* USB OTG Controller ***************************************************************/ +/* OTG registers */ + +#define LPC17_USBOTG_INTST (LPC17_USB_BASE+LPC17_USBOTG_INTST_OFFSET) +#define LPC17_USBOTG_INTEN (LPC17_USB_BASE+LPC17_USBOTG_INTEN_OFFSET) +#define LPC17_USBOTG_INTSET (LPC17_USB_BASE+LPC17_USBOTG_INTSET_OFFSET) +#define LPC17_USBOTG_INTCLR (LPC17_USB_BASE+LPC17_USBOTG_INTCLR_OFFSET) +#define LPC17_USBOTG_STCTRL (LPC17_USB_BASE+LPC17_USBOTG_STCTRL_OFFSET) +#define LPC17_USBOTG_TMR (LPC17_USB_BASE+LPC17_USBOTG_TMR_OFFSET) + +/* USB Device Controller ************************************************************/ +/* Device interrupt registers. See also SYSCON_USBINTST in lpc17_syscon.h */ + +#define LPC17_USBDEV_INTST (LPC17_USB_BASE+LPC17_USBDEV_INTST_OFFSET) +#define LPC17_USBDEV_INTEN (LPC17_USB_BASE+LPC17_USBDEV_INTEN_OFFSET) +#define LPC17_USBDEV_INTCLR (LPC17_USB_BASE+LPC17_USBDEV_INTCLR_OFFSET) +#define LPC17_USBDEV_INTSET (LPC17_USB_BASE+LPC17_USBDEV_INTSET_OFFSET) + +/* SIE Command registers */ + +#define LPC17_USBDEV_CMDCODE (LPC17_USB_BASE+LPC17_USBDEV_CMDCODE_OFFSET) +#define LPC17_USBDEV_CMDDATA (LPC17_USB_BASE+LPC17_USBDEV_CMDDATA_OFFSET) + +/* USB transfer registers */ + +#define LPC17_USBDEV_RXDATA (LPC17_USB_BASE+LPC17_USBDEV_RXDATA_OFFSET) +#define LPC17_USBDEV_RXPLEN (LPC17_USB_BASE+LPC17_USBDEV_RXPLEN_OFFSET) +#define LPC17_USBDEV_TXDATA (LPC17_USB_BASE+LPC17_USBDEV_TXDATA_OFFSET) +#define LPC17_USBDEV_TXPLEN (LPC17_USB_BASE+LPC17_USBDEV_TXPLEN_OFFSET) +#define LPC17_USBDEV_CTRL (LPC17_USB_BASE+LPC17_USBDEV_CTRL_OFFSET) + +/* More Device interrupt registers */ + +#define LPC17_USBDEV_INTPRI (LPC17_USB_BASE+LPC17_USBDEV_INTPRI_OFFSET) + +/* Endpoint interrupt registers */ + +#define LPC17_USBDEV_EPINTST (LPC17_USB_BASE+LPC17_USBDEV_EPINTST_OFFSET) +#define LPC17_USBDEV_EPINTEN (LPC17_USB_BASE+LPC17_USBDEV_EPINTEN_OFFSET) +#define LPC17_USBDEV_EPINTCLR (LPC17_USB_BASE+LPC17_USBDEV_EPINTCLR_OFFSET) +#define LPC17_USBDEV_EPINTSET (LPC17_USB_BASE+LPC17_USBDEV_EPINTSET_OFFSET) +#define LPC17_USBDEV_EPINTPRI (LPC17_USB_BASE+LPC17_USBDEV_EPINTPRI_OFFSET) + +/* Endpoint realization registers */ + +#define LPC17_USBDEV_REEP (LPC17_USB_BASE+LPC17_USBDEV_REEP_OFFSET) +#define LPC17_USBDEV_EPIND (LPC17_USB_BASE+LPC17_USBDEV_EPIND_OFFSET) +#define LPC17_USBDEV_MAXPSIZE (LPC17_USB_BASE+LPC17_USBDEV_MAXPSIZE_OFFSET) + +/* DMA registers */ + +#define LPC17_USBDEV_DMARST (LPC17_USB_BASE+LPC17_USBDEV_DMARST_OFFSET) +#define LPC17_USBDEV_DMARCLR (LPC17_USB_BASE+LPC17_USBDEV_DMARCLR_OFFSET) +#define LPC17_USBDEV_DMARSET (LPC17_USB_BASE+LPC17_USBDEV_DMARSET_OFFSET) +#define LPC17_USBDEV_UDCAH (LPC17_USB_BASE+LPC17_USBDEV_UDCAH_OFFSET) +#define LPC17_USBDEV_EPDMAST (LPC17_USB_BASE+LPC17_USBDEV_EPDMAST_OFFSET) +#define LPC17_USBDEV_EPDMAEN (LPC17_USB_BASE+LPC17_USBDEV_EPDMAEN_OFFSET) +#define LPC17_USBDEV_EPDMADIS (LPC17_USB_BASE+LPC17_USBDEV_EPDMADIS_OFFSET) +#define LPC17_USBDEV_DMAINTST (LPC17_USB_BASE+LPC17_USBDEV_DMAINTST_OFFSET) +#define LPC17_USBDEV_DMAINTEN (LPC17_USB_BASE+LPC17_USBDEV_DMAINTEN_OFFSET) +#define LPC17_USBDEV_EOTINTST (LPC17_USB_BASE+LPC17_USBDEV_EOTINTST_OFFSET) +#define LPC17_USBDEV_EOTINTCLR (LPC17_USB_BASE+LPC17_USBDEV_EOTINTCLR_OFFSET) +#define LPC17_USBDEV_EOTINTSET (LPC17_USB_BASE+LPC17_USBDEV_EOTINTSET_OFFSET) +#define LPC17_USBDEV_NDDRINTST (LPC17_USB_BASE+LPC17_USBDEV_NDDRINTST_OFFSET) +#define LPC17_USBDEV_NDDRINTCLR (LPC17_USB_BASE+LPC17_USBDEV_NDDRINTCLR_OFFSET) +#define LPC17_USBDEV_NDDRINTSET (LPC17_USB_BASE+LPC17_USBDEV_NDDRINTSET_OFFSET) +#define LPC17_USBDEV_SYSERRINTST (LPC17_USB_BASE+LPC17_USBDEV_SYSERRINTST_OFFSET) +#define LPC17_USBDEV_SYSERRINTCLR (LPC17_USB_BASE+LPC17_USBDEV_SYSERRINTCLR_OFFSET) +#define LPC17_USBDEV_SYSERRINTSET (LPC17_USB_BASE+LPC17_USBDEV_SYSERRINTSET_OFFSET) + +/* OTG I2C registers ****************************************************************/ + +#define LPC17_OTGI2C_RX (LPC17_USB_BASE+LPC17_OTGI2C_RX_OFFSET) +#define LPC17_OTGI2C_TX (LPC17_USB_BASE+LPC17_OTGI2C_TX_OFFSET) +#define LPC17_OTGI2C_STS (LPC17_USB_BASE+LPC17_OTGI2C_STS_OFFSET) +#define LPC17_OTGI2C_CTL (LPC17_USB_BASE+LPC17_OTGI2C_CTL_OFFSET) +#define LPC17_OTGI2C_CLKHI (LPC17_USB_BASE+LPC17_OTGI2C_CLKHI_OFFSET) +#define LPC17_OTGI2C_CLKLO (LPC17_USB_BASE+LPC17_OTGI2C_CLKLO_OFFSET) + +/* Clock control registers ***********************************************************/ + +#define LPC17_USBOTG_CLKCTRL (LPC17_USB_BASE+LPC17_USBOTG_CLKCTRL_OFFSET) +#define LPC17_USBOTG_CLKST (LPC17_USB_BASE+LPC17_USBOTG_CLKST_OFFSET) + +#define LPC17_USBDEV_CLKCTRL (LPC17_USB_BASE+LPC17_USBDEV_CLKCTRL_OFFSET) +#define LPC17_USBDEV_CLKST (LPC17_USB_BASE+LPC17_USBDEV_CLKST_OFFSET) + +/* Register bit definitions *********************************************************/ +/* USB Host Controller (OHCI) *******************************************************/ +/* See include/nuttx/usb/ohci.h */ + +/* Module ID/Revision ID */ + +#define USBHOST_MODID_VER_SHIFT (0) /* Bits 0-7: Unique version number */ +#define USBHOST_MODID_VER_MASK (0xff << USBHOST_MODID_VER_SHIFT) +#define USBHOST_MODID_REV_SHIFT (8) /* Bits 9-15: Unique revision number */ +#define USBHOST_MODID_REV_MASK (0xff << USBHOST_MODID_REV_SHIFT) +#define USBHOST_MODID_3505_SHIFT (16) /* Bits 16-31: 0x3505 */ +#define USBHOST_MODID_3505_MASK (0xffff << USBHOST_MODID_3505_SHIFT) +# define USBHOST_MODID_3505 (0x3505 << USBHOST_MODID_3505_SHIFT) + +/* USB OTG Controller ***************************************************************/ +/* OTG registers: + * + * OTG Interrupt Status, OTG Interrupt Enable, OTG Interrupt Set, AND OTG Interrupt + * Clear + */ + +#define USBOTG_INT_TMR (1 << 0) /* Bit 0: Timer time-out */ +#define USBOTG_INT_REMOVE_PU (1 << 1) /* Bit 1: Remove pull-up */ +#define USBOTG_INT_HNP_FAILURE (1 << 2) /* Bit 2: HNP failed */ +#define USBOTG_INT_HNP_SUCCESS (1 << 3) /* Bit 3: HNP succeeded */ + /* Bits 4-31: Reserved */ +/* OTG Status and Control */ + +#define USBOTG_STCTRL_PORTFUNC_SHIFT (0) /* Bits 0-1: Controls port function */ +#define USBOTG_STCTRL_PORTFUNC_MASK (3 << USBOTG_STCTRL_PORTFUNC_SHIFT) +# define USBOTG_STCTRL_PORTFUNC_HNPOK (1 << USBOTG_STCTRL_PORTFUNC_SHIFT) /* HNP suceeded */ +#define USBOTG_STCTRL_TMRSCALE_SHIFT (2) /* Bits 2-3: Timer scale selection */ +#define USBOTG_STCTRL_TMRSCALE_MASK (3 << USBOTG_STCTRL_TMR_SCALE_SHIFT) +# define USBOTG_STCTRL_TMRSCALE_10US (0 << USBOTG_STCTRL_TMR_SCALE_SHIFT) /* 10uS (100 KHz) */ +# define USBOTG_STCTRL_TMRSCALE_100US (1 << USBOTG_STCTRL_TMR_SCALE_SHIFT) /* 100uS (10 KHz) */ +# define USBOTG_STCTRL_TMRSCALE_1000US (2 << USBOTG_STCTRL_TMR_SCALE_SHIFT) /* 1000uS (1 KHz) */ +#define USBOTG_STCTRL_TMRMODE (1 << 4) /* Bit 4: Timer mode selection */ +#define USBOTG_STCTRL_TMREN (1 << 5) /* Bit 5: Timer enable */ +#define USBOTG_STCTRL_TMRRST (1 << 6) /* Bit 6: TTimer reset */ + /* Bit 7: Reserved */ +#define USBOTG_STCTRL_BHNPTRACK (1 << 8) /* Bit 8: Enable HNP tracking for B-device (peripheral) */ +#define USBOTG_STCTRL_AHNPTRACK (1 << 9) /* Bit 9: Enable HNP tracking for A-device (host) */ +#define USBOTG_STCTRL_PUREMOVED (1 << 10) /* Bit 10: Set when D+ pull-up removed */ + /* Bits 11-15: Reserved */ +#define USBOTG_STCTRL_TMRCNT_SHIFT (0) /* Bits 16-313: Timer scale selection */ +#define USBOTG_STCTRL_TMRCNT_MASK (0ffff << USBOTG_STCTRL_TMR_CNT_SHIFT) + +/* OTG Timer */ + +#define USBOTG_TMR_TIMEOUTCNT_SHIFT (0) /* Bits 0-15: Interrupt when CNT matches this */ +#define USBOTG_TMR_TIMEOUTCNT_MASK (0xffff << USBOTG_TMR_TIMEOUTCNT_SHIFT) + /* Bits 16-31: Reserved */ + +/* USB Device Controller ************************************************************/ +/* Device interrupt registers. See also SYSCON_USBINTST in lpc17_syscon.h */ +/* USB Device Interrupt Status, USB Device Interrupt Enable, USB Device Interrupt + * Clear, USB Device Interrupt Set, and USB Device Interrupt Priority + */ + +#define USBDEV_INT_FRAME (1 << 0) /* Bit 0: frame interrupt (every 1 ms) */ +#define USBDEV_INT_EPFAST (1 << 1) /* Bit 1: Fast endpoint interrupt */ +#define USBDEV_INT_EPSLOW (1 << 2) /* Bit 2: Slow endpoints interrupt */ +#define USBDEV_INT_DEVSTAT (1 << 3) /* Bit 3: Bus reset, suspend change or connect change */ +#define USBDEV_INT_CCEMPTY (1 << 4) /* Bit 4: Command code register empty */ +#define USBDEV_INT_CDFULL (1 << 5) /* Bit 5: Command data register full */ +#define USBDEV_INT_RXENDPKT (1 << 6) /* Bit 6: RX endpoint data transferred */ +#define USBDEV_INT_TXENDPKT (1 << 7) /* Bit 7: TX endpoint data tansferred */ +#define USBDEV_INT_EPRLZED (1 << 8) /* Bit 8: Endpoints realized */ +#define USBDEV_INT_ERRINT (1 << 9) /* Bit 9: Error Interrupt */ + /* Bits 10-31: Reserved */ +/* SIE Command registers: + * + * USB Command Code + */ + /* Bits 0-7: Reserved */ +#define USBDEV_CMDCODE_PHASE_SHIFT (8) /* Bits 8-15: Command phase */ +#define USBDEV_CMDCODE_PHASE_MASK (0xff << USBDEV_CMDCODE_PHASE_SHIFT) +# define USBDEV_CMDCODE_PHASE_READ (1 << USBDEV_CMDCODE_PHASE_SHIFT) +# define USBDEV_CMDCODE_PHASE_WRITE (2 << USBDEV_CMDCODE_PHASE_SHIFT) +# define USBDEV_CMDCODE_PHASE_COMMAND (5 << USBDEV_CMDCODE_PHASE_SHIFT) +#define USBDEV_CMDCODE_CMD_SHIFT (16) /* Bits 15-23: Command (READ/COMMAND phases) */ +#define USBDEV_CMDCODE_CMD_MASK (0xff << USBDEV_CMDCODE_CMD_SHIFT) +#define USBDEV_CMDCODE_WDATA_SHIFT (16) /* Bits 15-23: Write dagta (WRITE phase) */ +#define USBDEV_CMDCODE_WDATA_MASK (0xff << USBDEV_CMDCODE_CMD_SHIFT) + /* Bits 24-31: Reserved */ +/* USB Command Data */ + +#define USBDEV_CMDDATA_SHIFT (0) /* Bits 0-7: Command read data */ +#define USBDEV_CMDDATA_MASK (0xff << USBDEV_CMDDATA_SHIFT) + /* Bits 8-31: Reserved */ +/* USB transfer registers: + * + * USB Receive Data (Bits 0-31: Received data) + */ + +/* USB Receive Packet Length */ + +#define USBDEV_RXPLEN_SHIFT (0) /* Bits 0-9: Bytes remaining to be read */ +#define USBDEV_RXPLEN_MASK (0x3ff << USBDEV_RXPLEN_SHIFT) +#define USBDEV_RXPLEN_DV (1 << 10) /* Bit 10: DV Data valid */ +#define USBDEV_RXPLEN_PKTRDY (1 << 11) /* Bit 11: Packet ready for reading */ + /* Bits 12-31: Reserved */ +/* USB Transmit Data (Bits 0-31: Transmit data) */ + +/* USB Transmit Packet Length */ + +#define USBDEV_TXPLEN_SHIFT (0) /* Bits 0-9: Bytes remaining to be written */ +#define USBDEV_TXPLEN_MASK (0x3ff << USBDEV_TXPLEN_SHIFT) + /* Bits 10-31: Reserved */ +/* USB Control */ + +#define USBDEV_CTRL_RDEN (1 << 0) /* Bit 0: Read mode control */ +#define USBDEV_CTRL_WREN (1 << 1) /* Bit 1: Write mode control */ +#define USBDEV_CTRL_LOGEP_SHIFT (2) /* Bits 2-5: Logical Endpoint number */ +#define USBDEV_CTRL_LOGEP_MASK (15 << USBDEV_CTRL_LOGEP_SHIFT) + /* Bits 6-31: Reserved */ +/* Endpoint interrupt registers: + * + * USB Endpoint Interrupt Status, USB Endpoint Interrupt Enable, USB Endpoint Interrupt + * Clear, USB Endpoint Interrupt Set, and USB Endpoint Priority. Bits correspond + * to on RX or TX value for any of 15 logical endpoints). + */ + +#define USBDEV_LOGEPRX(n) (1 << ((n) << 1)) +#define USBDEV_LOGEPTX(n) ((1 << ((n) << 1)) + 1) +#define USBDEV_LOGEPRX0 (1 << 0) +#define USBDEV_LOGEPTX0 (1 << 1) +#define USBDEV_LOGEPRX1 (1 << 2) +#define USBDEV_LOGEPTX1 (1 << 3) +#define USBDEV_LOGEPRX2 (1 << 4) +#define USBDEV_LOGEPTX2 (1 << 5) +#define USBDEV_LOGEPRX3 (1 << 6) +#define USBDEV_LOGEPTX3 (1 << 7) +#define USBDEV_LOGEPRX4 (1 << 8) +#define USBDEV_LOGEPTX4 (1 << 9) +#define USBDEV_LOGEPRX5 (1 << 10) +#define USBDEV_LOGEPTX5 (1 << 11) +#define USBDEV_LOGEPRX6 (1 << 12) +#define USBDEV_LOGEPTX6 (1 << 13) +#define USBDEV_LOGEPRX7 (1 << 14) +#define USBDEV_LOGEPTX7 (1 << 15) +#define USBDEV_LOGEPRX8 (1 << 16) +#define USBDEV_LOGEPTX8 (1 << 17) +#define USBDEV_LOGEPRX9 (1 << 18) +#define USBDEV_LOGEPTX9 (1 << 19) +#define USBDEV_LOGEPRX10 (1 << 20) +#define USBDEV_LOGEPTX10 (1 << 21) +#define USBDEV_LOGEPRX11 (1 << 22) +#define USBDEV_LOGEPTX11 (1 << 23) +#define USBDEV_LOGEPRX12 (1 << 24) +#define USBDEV_LOGEPTX12 (1 << 25) +#define USBDEV_LOGEPRX13 (1 << 26) +#define USBDEV_LOGEPTX13 (1 << 27) +#define USBDEV_LOGEPRX14 (1 << 28) +#define USBDEV_LOGEPTX14 (1 << 29) +#define USBDEV_LOGEPRX15 (1 << 30) +#define USBDEV_LOGEPTX15 (1 << 31) + +/* Endpoint realization registers: + * + * USB Realize Endpoint (Bits correspond to 1 of 32 physical endpoints) + */ + +#define USBDEV_PHYEP(n) (1 << (n)) +#define USBDEV_PHYEP0 (1 << 0) +#define USBDEV_PHYEP1 (1 << 1) +#define USBDEV_PHYEP2 (1 << 2) +#define USBDEV_PHYEP3 (1 << 3) +#define USBDEV_PHYEP4 (1 << 4) +#define USBDEV_PHYEP5 (1 << 5) +#define USBDEV_PHYEP6 (1 << 6) +#define USBDEV_PHYEP7 (1 << 7) +#define USBDEV_PHYEP8 (1 << 8) +#define USBDEV_PHYEP9 (1 << 9) +#define USBDEV_PHYEP10 (1 << 10) +#define USBDEV_PHYEP11 (1 << 11) +#define USBDEV_PHYEP12 (1 << 12) +#define USBDEV_PHYEP13 (1 << 13) +#define USBDEV_PHYEP14 (1 << 14) +#define USBDEV_PHYEP15 (1 << 15) +#define USBDEV_PHYEP16 (1 << 16) +#define USBDEV_PHYEP17 (1 << 17) +#define USBDEV_PHYEP18 (1 << 18) +#define USBDEV_PHYEP19 (1 << 19) +#define USBDEV_PHYEP20 (1 << 20) +#define USBDEV_PHYEP21 (1 << 21) +#define USBDEV_PHYEP22 (1 << 22) +#define USBDEV_PHYEP23 (1 << 23) +#define USBDEV_PHYEP24 (1 << 24) +#define USBDEV_PHYEP25 (1 << 25) +#define USBDEV_PHYEP26 (1 << 26) +#define USBDEV_PHYEP27 (1 << 27) +#define USBDEV_PHYEP28 (1 << 28) +#define USBDEV_PHYEP29 (1 << 29) +#define USBDEV_PHYEP30 (1 << 30) +#define USBDEV_PHYEP31 (1 << 31) + +/* USB Endpoint Index */ + +#define USBDEV_EPIND_SHIFT (0) /* Bits 0-4: Physical endpoint number (0-31) */ +#define USBDEV_EPIND_MASK (31 << USBDEV_EPIND_SHIFT) + /* Bits 5-31: Reserved */ +/* USB MaxPacketSize */ + +#define USBDEV_MAXPSIZE_SHIFT (0) /* Bits 0-9: Maximum packet size value */ +#define USBDEV_MAXPSIZE_MASK (0x3ff << USBDEV_MAXPSIZE_SHIFT) + /* Bits 10-31: Reserved */ +/* DMA registers: + * + * USB DMA Request Status, USB DMA Request Clear, and USB DMA Request Set. Registers + * contain bits for each of 32 physical endpoints. Use the USBDEV_PHYEP* definitions + * above. PHYEP0-1 (bits 0-1) must be zero. + */ + +/* USB UDCA Head */ + /* Bits 0-6: Reserved */ +#define USBDEV_UDCAH_SHIFT (7) /* Bits 7-31: UDCA start address */ +#define USBDEV_UDCAH_MASK (0x01ffffff << USBDEV_UDCAH_SHIFT) + +/* USB Endpoint DMA Status, USB Endpoint DMA Enable, and USB Endpoint DMA Disable. + * Registers contain bits for physical endpoints 2-31. Use the USBDEV_PHYEP* + * definitions above. PHYEP0-1 (bits 0-1) must be zero. + */ + +/* USB DMA Interrupt Status and USB DMA Interrupt Enable */ + +#define USBDEV_DMAINT_EOT (1 << 0) /* Bit 0: End of Transfer Interrupt */ +#define USBDEV_DMAINT_NDDR (1 << 1) /* Bit 1: New DD Request Interrupt */ +#define USBDEV_DMAINT_ERR (1 << 2) /* Bit 2: System Error Interrupt */ + /* Bits 3-31: Reserved */ +/* USB End of Transfer Interrupt Status, USB End of Transfer Interrupt Clear, and USB + * End of Transfer Interrupt Set. Registers contain bits for physical endpoints 2-31. + * Use the USBDEV_PHYEP* definitions above. PHYEP0-1 (bits 0-1) must be zero. + */ + +/* USB New DD Request Interrupt Status, USB New DD Request Interrupt Clear, and USB + * New DD Request Interrupt Set. Registers contain bits for physical endpoints 2-31. + * Use the USBDEV_PHYEP* definitions above. PHYEP0-1 (bits 0-1) must be zero. + */ + +/* USB System Error Interrupt Status, USB System Error Interrupt Clear, USB System + * Error Interrupt Set. Registers contain bits for physical endpoints 2-31. Use + * the USBDEV_PHYEP* definitions above. PHYEP0-1 (bits 0-1) must be zero. + */ + +/* OTG I2C registers ****************************************************************/ + +/* I2C Receive */ + +#define OTGI2C_RX_DATA_SHIFT (0) /* Bits 0-7: RX data */ +#define OTGI2C_RX_DATA_MASK (0xff << OTGI2C_RX_SHIFT) + /* Bits 8-31: Reserved */ +/* I2C Transmit */ + +#define OTGI2C_TX_DATA_SHIFT (0) /* Bits 0-7: TX data */ +#define OTGI2C_TX_DATA_MASK (0xff << OTGI2C_TX_DATA_SHIFT) +#define OTGI2C_TX_DATA_START (1 << 8) /* Bit 8: Issue START before transmit */ +#define OTGI2C_TX_DATA_STOP (1 << 9) /* Bit 9: Issue STOP before transmit */ + /* Bits 3-31: Reserved */ +/* I2C Status */ + +#define OTGI2C_STS_TDI (1 << 0) /* Bit 0: Transaction Done Interrupt */ +#define OTGI2C_STS_AFI (1 << 1) /* Bit 1: Arbitration Failure Interrupt */ +#define OTGI2C_STS_NAI (1 << 2) /* Bit 2: No Acknowledge Interrupt */ +#define OTGI2C_STS_DRMI (1 << 3) /* Bit 3: Master Data Request Interrupt */ +#define OTGI2C_STS_DRSI (1 << 4) /* Bit 4: Slave Data Request Interrupt */ +#define OTGI2C_STS_ACTIVE (1 << 5) /* Bit 5: Indicates whether the bus is busy */ +#define OTGI2C_STS_SCL (1 << 6) /* Bit 6: The current value of the SCL signal */ +#define OTGI2C_STS_SDA (1 << 7) /* Bit 7: The current value of the SDA signal */ +#define OTGI2C_STS_RFF (1 << 8) /* Bit 8: Receive FIFO Full (RFF) */ +#define OTGI2C_STS_RFE (1 << 9) /* Bit 9: Receive FIFO Empty */ +#define OTGI2C_STS_TFF (1 << 10) /* Bit 10: Transmit FIFO Full */ +#define OTGI2C_STS_TFE (1 << 11) /* Bit 11: Transmit FIFO Empty */ + /* Bits 12-31: Reserved */ +/* I2C Control */ + +#define OTGI2C_CTL_TDIE (1 << 0) /* Bit 0: Transmit Done Interrupt Enable */ +#define OTGI2C_CTL_AFIE (1 << 1) /* Bit 1: Transmitter Arbitration Failure Interrupt Enable */ +#define OTGI2C_CTL_NAIE (1 << 2) /* Bit 2: Transmitter No Acknowledge Interrupt Enable */ +#define OTGI2C_CTL_DRMIE (1 << 3) /* Bit 3: Master Transmitter Data Request Interrupt Enable */ +#define OTGI2C_CTL_DRSIE (1 << 4) /* Bit 4: Slave Transmitter Data Request Interrupt Enable */ +#define OTGI2C_CTL_REFIE (1 << 5) /* Bit 5: Receive FIFO Full Interrupt Enable */ +#define OTGI2C_CTL_RFDAIE (1 << 6) /* Bit 6: Receive Data Available Interrupt Enable */ +#define OTGI2C_CTL_TFFIE (1 << 7) /* Bit 7: Transmit FIFO Not Full Interrupt Enable */ +#define OTGI2C_CTL_SRST (1 << 8) /* Bit 8: Soft reset */ + /* Bits 9-31: Reserved */ +/* I2C Clock High */ + +#define OTGI2C_CLKHI_SHIFT (0) /* Bits 0-7: Clock divisor high */ +#define OTGI2C_CLKHI_MASK (0xff << OTGI2C_CLKHI_SHIFT) + /* Bits 8-31: Reserved */ +/* I2C Clock Low */ + +#define OTGI2C_CLKLO_SHIFT (0) /* Bits 0-7: Clock divisor high */ +#define OTGI2C_CLLO_MASK (0xff << OTGI2C_CLKLO_SHIFT) + /* Bits 8-31: Reserved */ +/* Clock control registers ***********************************************************/ + +/* USB Clock Control (OTG clock controller) and USB Clock Status (OTG clock status) */ + +#define USBDEV_CLK_HOSTCLK (1 << 0) /* Bit 1: Host clock (OTG only) */ +#define USBDEV_CLK_DEVCLK (1 << 1) /* Bit 1: Device clock */ +#define USBDEV_CLK_I2CCLK (1 << 2) /* Bit 2: I2C clock (OTG only) */ +#define USBDEV_CLK_PORTSELCLK (1 << 3) /* Bit 3: Port select register clock (device only) */ +#define USBDEV_CLK_OTGCLK (1 << 3) /* Bit 3: OTG clock (OTG only) */ +#define USBDEV_CLK_AHBCLK (1 << 4) /* Bit 4: AHB clock */ + /* Bits 5-31: Reserved */ +/* Alternate naming */ + +#define USBOTG_CLK_HOSTCLK USBDEV_CLK_HOSTCLK +#define USBOTG_CLK_DEVCLK USBDEV_CLK_DEVCLK +#define USBOTG_CLK_I2CCLK USBDEV_CLK_I2CCLK +#define USBOTG_CLK_PORTSELCLK USBDEV_CLK_PORTSELCLK +#define USBOTG_CLK_OTGCLK USBDEV_CLK_OTGCLK +#define USBOTG_CLK_AHBCLK USBDEV_CLK_AHBCLK + +/* Endpoints *************************************************************************/ + +#define LPC17_EP0_OUT 0 +#define LPC17_EP0_IN 1 +#define LPC17_CTRLEP_OUT LPC17_EP0_OUT +#define LPC17_CTRLEP_IN LPC17_EP0_IN +#define LPC17_EP1_OUT 2 +#define LPC17_EP1_IN 3 +#define LPC17_EP2_OUT 4 +#define LPC17_EP2_IN 5 +#define LPC17_EP3_OUT 6 +#define LPC17_EP3_IN 7 +#define LPC17_EP4_OUT 8 +#define LPC17_EP4_IN 9 +#define LPC17_EP5_OUT 10 +#define LPC17_EP5_IN 11 +#define LPC17_EP6_OUT 12 +#define LPC17_EP6_IN 13 +#define LPC17_EP7_OUT 14 +#define LPC17_EP7_IN 15 +#define LPC17_EP8_OUT 16 +#define LPC17_EP8_IN 17 +#define LPC17_EP9_OUT 18 +#define LPC17_EP9_IN 19 +#define LPC17_EP10_OUT 20 +#define LPC17_EP10_IN 21 +#define LPC17_EP11_OUT 22 +#define LPC17_EP11_IN 23 +#define LPC17_EP12_OUT 24 +#define LPC17_EP12_IN 25 +#define LPC17_EP13_OUT 26 +#define LPC17_EP13_IN 27 +#define LPC17_EP14_OUT 28 +#define LPC17_EP14_IN 29 +#define LPC17_EP15_OUT 30 +#define LPC17_EP15_IN 31 +#define LPC17_NUMEPS 32 + +/* Commands *************************************************************************/ + +/* USB Command Code Register */ + +#define CMD_USBDEV_PHASESHIFT (8) /* Bits 8-15: Command phase value */ +#define CMD_USBDEV_PHASEMASK (0xff << CMD_USBDEV_PHASESHIFT) +# define CMD_USBDEV_DATAWR (1 << CMD_USBDEV_PHASESHIFT) +# define CMD_USBDEV_DATARD (2 << CMD_USBDEV_PHASESHIFT) +# define CMD_USBDEV_CMDWR (5 << CMD_USBDEV_PHASESHIFT) +#define CMD_USBDEV_CMDSHIFT (16) /* Bits 16-23: Device command/WDATA */ +#define CMD_USBDEV_CMDMASK (0xff << CMD_USBDEV_CMDSHIFT) +#define CMD_USBDEV_WDATASHIFT CMD_USBDEV_CMDSHIFT +#define CMD_USBDEV_WDATAMASK CMD_USBDEV_CMDMASK + +/* Device Commands */ + +#define CMD_USBDEV_SETADDRESS (0x00d0) +#define CMD_USBDEV_CONFIG (0x00d8) +#define CMD_USBDEV_SETMODE (0x00f3) +#define CMD_USBDEV_READFRAMENO (0x00f5) +#define CMD_USBDEV_READTESTREG (0x00fd) +#define CMD_USBDEV_SETSTATUS (0x01fe) /* Bit 8 set to distingish get from set */ +#define CMD_USBDEV_GETSTATUS (0x00fe) +#define CMD_USBDEV_GETERRORCODE (0x00ff) +#define CMD_USBDEV_READERRORSTATUS (0x00fb) + +/* Endpoint Commands */ + +#define CMD_USBDEV_EPSELECT (0x0000) +#define CMD_USBDEV_EPSELECTCLEAR (0x0040) +#define CMD_USBDEV_EPSETSTATUS (0x0140) /* Bit 8 set to distingish get from selectclear */ +#define CMD_USBDEV_EPCLRBUFFER (0x00f2) +#define CMD_USBDEV_EPVALIDATEBUFFER (0x00fa) + +/* Command/response bit definitions ********************************************/ +/* SETADDRESS (0xd0) command definitions */ + +#define CMD_USBDEV_SETADDRESS_MASK (0x7f) /* Bits 0-6: Device address */ +#define CMD_USBDEV_SETADDRESS_DEVEN (1 << 7) /* Bit 7: Device enable */ + +/* SETSTATUS (0xfe) and GETSTATUS (0xfe) response: */ + +#define CMD_STATUS_CONNECT (1 << 0) /* Bit 0: Connected */ +#define CMD_STATUS_CONNCHG (1 << 1) /* Bit 1: Connect change */ +#define CMD_STATUS_SUSPEND (1 << 2) /* Bit 2: Suspend */ +#define CMD_STATUS_SUSPCHG (1 << 3) /* Bit 3: Suspend change */ +#define CMD_STATUS_RESET (1 << 4) /* Bit 4: Bus reset bit */ + +/* EPSELECT (0x00) endpoint status response */ + +#define CMD_EPSELECT_FE (1 << 0) /* Bit 0: IN empty or OUT full */ +#define CMD_EPSELECT_ST (1 << 1) /* Bit 1: Endpoint is stalled */ +#define CMD_EPSELECT_STP (1 << 2) /* Bit 2: Last packet was setup */ +#define CMD_EPSELECT_PO (1 << 3) /* Bit 3: Previous packet was overwritten */ +#define CMD_EPSELECT_EPN (1 << 4) /* Bit 4: NAK sent */ +#define CMD_EPSELECT_B1FULL (1 << 5) /* Bit 5: Buffer 1 full */ +#define CMD_EPSELECT_B2FULL (1 << 6) /* Bit 6: Buffer 2 full */ + /* Bit 7: Reserved */ +/* EPSETSTATUS (0x40) command */ + +#define CMD_SETSTAUS_ST (1 << 0) /* Bit 0: Stalled endpoint bit */ + /* Bits 1-4: Reserved */ +#define CMD_SETSTAUS_DA (1 << 5) /* Bit 5: Disabled endpoint bit */ +#define CMD_SETSTAUS_RFMO (1 << 6) /* Bit 6: Rate feedback mode */ +#define CMD_SETSTAUS_CNDST (1 << 7) /* Bit 7: Conditional stall bit */ + +/* EPCLRBUFFER (0xf2) response */ + +#define CMD_USBDEV_CLRBUFFER_PO (0x00000001) + +/* SETMODE(0xf3) command */ + +#define CMD_SETMODE_APCLK (1 << 0) /* Bit 0: Always PLL Clock */ +#define CMD_SETMODE_INAKCI (1 << 1) /* Bit 1: Interrupt on NAK for Control IN endpoint */ +#define CMD_SETMODE_INAKCO (1 << 2) /* Bit 2: Interrupt on NAK for Control OUT endpoint */ +#define CMD_SETMODE_INAKII (1 << 3) /* Bit 3: Interrupt on NAK for Interrupt IN endpoint */ +#define CMD_SETMODE_INAKIO (1 << 4) /* Bit 4: Interrupt on NAK for Interrupt OUT endpoints */ +#define CMD_SETMODE_INAKBI (1 << 5) /* Bit 5: Interrupt on NAK for Bulk IN endpoints */ +#define CMD_SETMODE_INAKBO (1 << 6) /* Bit 6: Interrupt on NAK for Bulk OUT endpoints */ + +/* READERRORSTATUS (0xFb) command */ + +#define CMD_READERRORSTATUS_PIDERR (1 << 0) /* Bit 0: PID encoding/unknown or Token CRC */ +#define CMD_READERRORSTATUS_UEPKT (1 << 1) /* Bit 1: Unexpected Packet */ +#define CMD_READERRORSTATUS_DCRC (1 << 2) /* Bit 2: Data CRC error */ +#define CMD_READERRORSTATUS_TIMEOUT (1 << 3) /* Bit 3: Time out error */ +#define CMD_READERRORSTATUS_EOP (1 << 4) /* Bit 4: End of packet error */ +#define CMD_READERRORSTATUS_BOVRN (1 << 5) /* Bit 5: Buffer Overrun */ +#define CMD_READERRORSTATUS_BTSTF (1 << 6) /* Bit 6: Bit stuff error */ +#define CMD_READERRORSTATUS_TGLERR (1 << 7) /* Bit 7: Wrong toggle in data PID */ +#define CMD_READERRORSTATUS_ALLERRS (0xff) + +/* DMA ******************************************************************************/ +/* The DMA descriptor */ + +#define USB_DMADESC_NEXTDDPTR 0 /* Offset 0: Next USB descriptor in RAM */ +#define USB_DMADESC_CONFIG 1 /* Offset 1: DMA configuration info. */ +#define USB_DMADESC_STARTADDR 2 /* Offset 2: DMA start address */ +#define USB_DMADESC_STATUS 3 /* Offset 3: DMA status info (read only) */ +#define USB_DMADESC_ISOCSIZEADDR 4 /* Offset 4: Isoc. packet size address */ + +/* Bit settings for CONFIG (offset 1 )*/ + +#define USB_DMADESC_MODE_SHIFT (0) /* Bits 0-1: DMA mode */ +#define USB_DMADESC_MODE_MASK (3 << USB_DMADESC_MODE_SHIFT) +# define USB_DMADESC_MODENORMAL (0 << USB_DMADESC_MODE_SHIFT) /* Mode normal */ +# define USB_DMADESC_MODEATLE (1 << USB_DMADESC_MODE_SHIFT) /* ATLE normal */ +#define USB_DMADESC_NEXTDDVALID (1 << 2) /* Bit 2: Next descriptor valid */ + /* Bit 3: Reserved */ +#define USB_DMADESC_ISCOEP (1 << 4) /* Bit 4: ISOC endpoint */ +#define USB_DMADESC_PKTSIZE_SHIFT (5) /* Bits 5-15: Max packet size */ +#define USB_DMADESC_PKTSIZE_MASK (0x7ff << USB_DMADESC_PKTSIZE_SHIFT) +#define USB_DMADESC_BUFLEN_SHIFT (16) /* Bits 16-31: DMA buffer length */ +#define USB_DMADESC_BUFLEN_MASK (0xffff << USB_DMADESC_BUFLEN_SHIFT + +/* Bit settings for STATUS (offset 3). All must be initialized to zero. */ + +#define USB_DMADESC_STATUS_SHIFT (1) /* Bits 1-4: DMA status */ +#define USB_DMADESC_STATUS_MASK (15 << USB_DMADESC_STATUS_SHIFT) +# define USB_DMADESC_NOTSERVICED (0 << USB_DMADESC_STATUS_SHIFT) +# define USB_DMADESC_BEINGSERVICED (1 << USB_DMADESC_STATUS_SHIFT) +# define USB_DMADESC_NORMALCOMPLETION (2 << USB_DMADESC_STATUS_SHIFT) +# define USB_DMADESC_DATAUNDERRUN (3 << USB_DMADESC_STATUS_SHIFT) +# define USB_DMADESC_DATAOVERRUN (8 << USB_DMADESC_STATUS_SHIFT) +# define USB_DMADESC_SYSTEMERROR (9 << USB_DMADESC_STATUS_SHIFT) +#define USB_DMADESC_PKTVALID (1 << 5) /* Bit 5: Packet valid */ +#define USB_DMADESC_LSBEXTRACTED (1 << 6) /* Bit 6: LS byte extracted */ +#define USB_DMADESC_MSBEXTRACTED (1 << 7) /* Bit 7: MS byte extracted */ +#define USB_DMADESC_MSGLENPOS_SHIFT (8) /* Bits 8-13: Message length position */ +#define USB_DMADESC_MSGLENPOS_MASK (0x3f << USB_DMADESC_MSGLENPOS_SHIFT) +#define USB_DMADESC_DMACOUNT_SHIFT (16) /* Bits 16-31: DMA count */ +#define USB_DMADESC_DMACOUNT_MASK (0xffff << USB_DMADESC_DMACOUNT_SHIFT) + +/* DMA packet size format */ + +#define USB_DMAPKTSIZE_PKTLEN_SHIFT (0) /* Bits 0-15: Packet length */ +#define USB_DMAPKTSIZE_PKTLEN_MASK (0xffff << USB_DMAPKTSIZE_PKTLEN_SHIFT) +#define USB_DMAPKTSIZE_PKTVALID (1 << 16) /* Bit 16: Packet valid */ +#define USB_DMAPKTSIZE_FRAMENO_SHIFT (17) /* Bit 17-31: Frame number */ +#define USB_DMAPKTSIZE_FRAMENO_MASK (0x7fff << USB_DMAPKTSIZE_FRAMENO_SHIFT) + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_USB_H */ diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_vectors.S b/nuttx/arch/arm/src/lpc17xx/lpc17_vectors.S index 75eb71f17..cdb4bef66 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_vectors.S +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_vectors.S @@ -3,7 +3,7 @@ * arch/arm/src/chip/lpc17_vectors.S * * Copyright (C) 2010-2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_wdt.h b/nuttx/arch/arm/src/lpc17xx/lpc17_wdt.h index dc02b2e1d..bd7790a6e 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_wdt.h +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_wdt.h @@ -1,108 +1,108 @@ -/************************************************************************************
- * arch/arm/src/lpc17xx/lpc17_wdt.h
- *
- * Copyright (C) 2010 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_WDT_H
-#define __ARCH_ARM_SRC_LPC17XX_LPC17_WDT_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-
-#include "chip.h"
-#include "lpc17_memorymap.h"
-
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-
-/* Register offsets *****************************************************************/
-
-#define LPC17_WDT_WDMOD_OFFSET 0x0000 /* Watchdog mode register */
-#define LPC17_WDT_WDTC_OFFSET 0x0004 /* Watchdog timer constant register */
-#define LPC17_WDT_WDFEED_OFFSET 0x0008 /* Watchdog feed sequence register */
-#define LPC17_WDT_WDTV_OFFSET 0x000c /* Watchdog timer value register */
-#define LPC17_WDT_WDCLKSEL_OFFSET 0x0010 /* Watchdog clock source selection register */
-
-/* Register addresses ***************************************************************/
-
-#define LPC17_WDT_WDMOD (LPC17_WDT_BASE+LPC17_WDT_WDMOD_OFFSET)
-#define LPC17_WDT_WDTC (LPC17_WDT_BASE+LPC17_WDT_WDTC_OFFSET)
-#define LPC17_WDT_WDFEED (LPC17_WDT_BASE+LPC17_WDT_WDFEED_OFFSET)
-#define LPC17_WDT_WDTV (LPC17_WDT_BASE+LPC17_WDT_WDTV_OFFSET)
-#define LPC17_WDT_WDCLKSEL (LPC17_WDT_BASE+LPC17_WDT_WDCLKSEL_OFFSET)
-
-/* Register bit definitions *********************************************************/
-
-/* Watchdog mode register */
-
-#define WDT_WDMOD_WDEN (1 << 0) /* Bit 0: Watchdog enable */
-#define WDT_WDMOD_WDRESET (1 << 1) /* Bit 1: Watchdog reset enable */
-#define WDT_WDMOD_WDTOF (1 << 2) /* Bit 2: Watchdog time-out */
-#define WDT_WDMOD_WDINT (1 << 3) /* Bit 3: Watchdog interrupt */
- /* Bits 14-31: Reserved */
-
-/* Watchdog timer constant register (Bits 0-31: Watchdog time-out interval) */
-
-/* Watchdog feed sequence register */
-
-#define WDT_WDFEED_MASK (0xff) /* Bits 0-7: Feed value should be 0xaa followed by 0x55 */
- /* Bits 14-31: Reserved */
-/* Watchdog timer value register (Bits 0-31: Counter timer value) */
-
-/* Watchdog clock source selection register */
-
-#define WDT_WDCLKSEL_WDSEL_SHIFT (0) /* Bits 0-1: Clock source for the Watchdog timer */
-#define WDT_WDCLKSEL_WDSEL_MASK (3 << WDT_WDCLKSEL_WDSEL_SHIFT)
-# define WDT_WDCLKSEL_WDSEL_INTRC (0 << WDT_WDCLKSEL_WDSEL_SHIFT) /* Internal RC osc */
-# define WDT_WDCLKSEL_WDSEL_APB (1 << WDT_WDCLKSEL_WDSEL_SHIFT) /* APB peripheral clock (watchdog pclk) */
-# define WDT_WDCLKSEL_WDSEL_RTC (2 << WDT_WDCLKSEL_WDSEL_SHIFT) /* RTC oscillator (rtc_clk) */
- /* Bits 2-30: Reserved */
-#define WDT_WDCLKSEL_WDLOCK (1 << 31) /* Bit 31: Lock WDT register bits if set */
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-/************************************************************************************
- * Public Functions
- ************************************************************************************/
-
-#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_WDT_H */
+/************************************************************************************ + * arch/arm/src/lpc17xx/lpc17_wdt.h + * + * Copyright (C) 2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_WDT_H +#define __ARCH_ARM_SRC_LPC17XX_LPC17_WDT_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +#include "chip.h" +#include "lpc17_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register offsets *****************************************************************/ + +#define LPC17_WDT_WDMOD_OFFSET 0x0000 /* Watchdog mode register */ +#define LPC17_WDT_WDTC_OFFSET 0x0004 /* Watchdog timer constant register */ +#define LPC17_WDT_WDFEED_OFFSET 0x0008 /* Watchdog feed sequence register */ +#define LPC17_WDT_WDTV_OFFSET 0x000c /* Watchdog timer value register */ +#define LPC17_WDT_WDCLKSEL_OFFSET 0x0010 /* Watchdog clock source selection register */ + +/* Register addresses ***************************************************************/ + +#define LPC17_WDT_WDMOD (LPC17_WDT_BASE+LPC17_WDT_WDMOD_OFFSET) +#define LPC17_WDT_WDTC (LPC17_WDT_BASE+LPC17_WDT_WDTC_OFFSET) +#define LPC17_WDT_WDFEED (LPC17_WDT_BASE+LPC17_WDT_WDFEED_OFFSET) +#define LPC17_WDT_WDTV (LPC17_WDT_BASE+LPC17_WDT_WDTV_OFFSET) +#define LPC17_WDT_WDCLKSEL (LPC17_WDT_BASE+LPC17_WDT_WDCLKSEL_OFFSET) + +/* Register bit definitions *********************************************************/ + +/* Watchdog mode register */ + +#define WDT_WDMOD_WDEN (1 << 0) /* Bit 0: Watchdog enable */ +#define WDT_WDMOD_WDRESET (1 << 1) /* Bit 1: Watchdog reset enable */ +#define WDT_WDMOD_WDTOF (1 << 2) /* Bit 2: Watchdog time-out */ +#define WDT_WDMOD_WDINT (1 << 3) /* Bit 3: Watchdog interrupt */ + /* Bits 14-31: Reserved */ + +/* Watchdog timer constant register (Bits 0-31: Watchdog time-out interval) */ + +/* Watchdog feed sequence register */ + +#define WDT_WDFEED_MASK (0xff) /* Bits 0-7: Feed value should be 0xaa followed by 0x55 */ + /* Bits 14-31: Reserved */ +/* Watchdog timer value register (Bits 0-31: Counter timer value) */ + +/* Watchdog clock source selection register */ + +#define WDT_WDCLKSEL_WDSEL_SHIFT (0) /* Bits 0-1: Clock source for the Watchdog timer */ +#define WDT_WDCLKSEL_WDSEL_MASK (3 << WDT_WDCLKSEL_WDSEL_SHIFT) +# define WDT_WDCLKSEL_WDSEL_INTRC (0 << WDT_WDCLKSEL_WDSEL_SHIFT) /* Internal RC osc */ +# define WDT_WDCLKSEL_WDSEL_APB (1 << WDT_WDCLKSEL_WDSEL_SHIFT) /* APB peripheral clock (watchdog pclk) */ +# define WDT_WDCLKSEL_WDSEL_RTC (2 << WDT_WDCLKSEL_WDSEL_SHIFT) /* RTC oscillator (rtc_clk) */ + /* Bits 2-30: Reserved */ +#define WDT_WDCLKSEL_WDLOCK (1 << 31) /* Bit 31: Lock WDT register bits if set */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_WDT_H */ diff --git a/nuttx/arch/arm/src/lpc214x/Make.defs b/nuttx/arch/arm/src/lpc214x/Make.defs index 1f199a6ba..41dc0911c 100644 --- a/nuttx/arch/arm/src/lpc214x/Make.defs +++ b/nuttx/arch/arm/src/lpc214x/Make.defs @@ -2,7 +2,7 @@ # lpc214x/Make.defs # # Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt <spudmonkey@racsa.co.cr> +# Author: Gregory Nutt <gnutt@nuttx.org> # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/lpc214x/chip.h b/nuttx/arch/arm/src/lpc214x/chip.h index 9d7d963b1..d469aae8b 100644 --- a/nuttx/arch/arm/src/lpc214x/chip.h +++ b/nuttx/arch/arm/src/lpc214x/chip.h @@ -2,7 +2,7 @@ * arch/arm/src/lpc214x/chip.h * * Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/lpc214x/lpc214x_apb.h b/nuttx/arch/arm/src/lpc214x/lpc214x_apb.h index 996983778..2d41ab106 100644 --- a/nuttx/arch/arm/src/lpc214x/lpc214x_apb.h +++ b/nuttx/arch/arm/src/lpc214x/lpc214x_apb.h @@ -2,7 +2,7 @@ * arch/arm/src/lpc214x/lpc214x_apb.h * * Copyright (C) 2008 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/lpc214x/lpc214x_decodeirq.c b/nuttx/arch/arm/src/lpc214x/lpc214x_decodeirq.c index 6317066c3..652fe4d61 100644 --- a/nuttx/arch/arm/src/lpc214x/lpc214x_decodeirq.c +++ b/nuttx/arch/arm/src/lpc214x/lpc214x_decodeirq.c @@ -2,7 +2,7 @@ * arch/arm/src/lpc214x/lpc214x_decodeirq.c * * Copyright (C) 2007-2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/lpc214x/lpc214x_i2c.h b/nuttx/arch/arm/src/lpc214x/lpc214x_i2c.h index 804dc0a11..a66399968 100644 --- a/nuttx/arch/arm/src/lpc214x/lpc214x_i2c.h +++ b/nuttx/arch/arm/src/lpc214x/lpc214x_i2c.h @@ -2,7 +2,7 @@ * arch/arm/src/lpc214x/lpc214x_i2c.h * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/lpc214x/lpc214x_irq.c b/nuttx/arch/arm/src/lpc214x/lpc214x_irq.c index a8b91037c..cb0f6e12f 100644 --- a/nuttx/arch/arm/src/lpc214x/lpc214x_irq.c +++ b/nuttx/arch/arm/src/lpc214x/lpc214x_irq.c @@ -2,7 +2,7 @@ * arch/arm/src/lpc214x/lpc214x_irq.c * * Copyright (C) 2007-2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/lpc214x/lpc214x_lowputc.S b/nuttx/arch/arm/src/lpc214x/lpc214x_lowputc.S index e36b1d83f..b53e7aa78 100644 --- a/nuttx/arch/arm/src/lpc214x/lpc214x_lowputc.S +++ b/nuttx/arch/arm/src/lpc214x/lpc214x_lowputc.S @@ -2,7 +2,7 @@ * arch/arm/src/lpc214x/lpc214X_lowputc.S * * Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/lpc214x/lpc214x_pinsel.h b/nuttx/arch/arm/src/lpc214x/lpc214x_pinsel.h index e3f793f09..b34eb86b6 100644 --- a/nuttx/arch/arm/src/lpc214x/lpc214x_pinsel.h +++ b/nuttx/arch/arm/src/lpc214x/lpc214x_pinsel.h @@ -2,7 +2,7 @@ * arch/arm/src/lpc214x/lpc214x_pinsl.h * * Copyright (C) 2008 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/lpc214x/lpc214x_pll.h b/nuttx/arch/arm/src/lpc214x/lpc214x_pll.h index 386f3a765..bea923e43 100644 --- a/nuttx/arch/arm/src/lpc214x/lpc214x_pll.h +++ b/nuttx/arch/arm/src/lpc214x/lpc214x_pll.h @@ -2,7 +2,7 @@ * arch/arm/src/lpc214x/lpc214x_pll.h * * Copyright (C) 2008 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/lpc214x/lpc214x_power.h b/nuttx/arch/arm/src/lpc214x/lpc214x_power.h index cd493dac6..7eb253160 100644 --- a/nuttx/arch/arm/src/lpc214x/lpc214x_power.h +++ b/nuttx/arch/arm/src/lpc214x/lpc214x_power.h @@ -2,7 +2,7 @@ * arch/arm/src/lpc214x/lpc214x_power.h * * Copyright (C) 2008 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/lpc214x/lpc214x_spi.h b/nuttx/arch/arm/src/lpc214x/lpc214x_spi.h index 202b9e250..ce6a03db9 100644 --- a/nuttx/arch/arm/src/lpc214x/lpc214x_spi.h +++ b/nuttx/arch/arm/src/lpc214x/lpc214x_spi.h @@ -2,7 +2,7 @@ * arch/arm/src/lpc214x/lpc214x_spi.h * * Copyright (C) 2008 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/lpc214x/lpc214x_timer.h b/nuttx/arch/arm/src/lpc214x/lpc214x_timer.h index 47adf9796..6c239f10c 100644 --- a/nuttx/arch/arm/src/lpc214x/lpc214x_timer.h +++ b/nuttx/arch/arm/src/lpc214x/lpc214x_timer.h @@ -2,7 +2,7 @@ * arch/arm/src/lpc214x/lpc214x_timer.h * * Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/lpc214x/lpc214x_timerisr.c b/nuttx/arch/arm/src/lpc214x/lpc214x_timerisr.c index 65e9adb57..99d1d118f 100644 --- a/nuttx/arch/arm/src/lpc214x/lpc214x_timerisr.c +++ b/nuttx/arch/arm/src/lpc214x/lpc214x_timerisr.c @@ -2,7 +2,7 @@ * arch/arm/src/lpc214x/lpc214x_timerisr.c * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/lpc214x/lpc214x_uart.h b/nuttx/arch/arm/src/lpc214x/lpc214x_uart.h index 2752d17ae..fd634a816 100755 --- a/nuttx/arch/arm/src/lpc214x/lpc214x_uart.h +++ b/nuttx/arch/arm/src/lpc214x/lpc214x_uart.h @@ -1,142 +1,142 @@ -/************************************************************************************
- * arch/arm/src/lpc214x/uart.h
- *
- * Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __LPC214X_UART_H
-#define __LPC214X_UART_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <arch/board/board.h> /* For clock settings */
-
-/************************************************************************************
- * Definitions
- ************************************************************************************/
-
-/* PINSEL0 bit definitions for UART0/1 */
-
-#define LPC214X_UART0_PINSEL 0x00000005 /* PINSEL0 value for UART0 */
-#define LPC214X_UART0_PINMASK 0x0000000f /* PINSEL0 mask for UART0 */
-
-#define LPC214X_UART1_PINSEL 0x00050000 /* PINSEL0 value for UART1 */
-#define LPC214X_UART1_PINMASK 0x000f0000 /* PINSEL0 mask for UART1 */
-
-/* Derive baud divisor setting from clock settings (see board.h) */
-
-#define UART_BAUD(baud) ((LPC214X_FOSC * LPC214X_PLL_M) / (baud * 16))
-
-/* Interrupt Enable Register (IER) bit definitions */
-
-#define LPC214X_IER_ERBFI (1 << 0) /* Enable receive data available int */
-#define LPC214X_IER_ETBEI (1 << 1) /* Enable THR empty Interrupt */
-#define LPC214X_IER_ELSI (1 << 2) /* Enable receive line status int */
-#define LPC214X_IER_EDSSI (1 << 3) /* Enable MODEM atatus interrupt (2146/6/8 UART1 Only) */
-#define LPC214X_IER_ALLIE 0x0f /* All interrupts */
-
-/* Interrupt ID Register(IIR) bit definitions */
-
-#define LPC214X_IIR_NO_INT (1 << 0) /* No interrupts pending */
-#define LPC214X_IIR_MS_INT (0 << 1) /* MODEM Status (UART1 only) */
-#define LPC214X_IIR_THRE_INT (1 << 1) /* Transmit Holding Register Empty */
-#define LPC214X_IIR_RDA_INT (2 << 1) /* Receive Data Available */
-#define LPC214X_IIR_RLS_INT (3 << 1) /* Receive Line Status */
-#define LPC214X_IIR_CTI_INT (6 << 1) /* Character Timeout Indicator */
-#define LPC214X_IIR_MASK 0x0e
-
-/* FIFO Control Register (FCR) bit definitions */
-
-#define LPC214X_FCR_FIFO_ENABLE (1 << 0) /* FIFO enable */
-#define LPC214X_FCR_RX_FIFO_RESET (1 << 1) /* Reset receive FIFO */
-#define LPC214X_FCR_TX_FIFO_RESET (1 << 2) /* Reset transmit FIFO */
-#define LPC214X_FCR_FIFO_TRIG1 (0 << 6) /* Trigger @1 character in FIFO */
-#define LPC214X_FCR_FIFO_TRIG4 (1 << 6) /* Trigger @4 characters in FIFO */
-#define LPC214X_FCR_FIFO_TRIG8 (2 << 6) /* Trigger @8 characters in FIFO */
-#define LPC214X_FCR_FIFO_TRIG14 (3 << 6) /* Trigger @14 characters in FIFO */
-
-/* Line Control Register (LCR) bit definitions */
-
-#define LPC214X_LCR_CHAR_5 (0 << 0) /* 5-bit character length */
-#define LPC214X_LCR_CHAR_6 (1 << 0) /* 6-bit character length */
-#define LPC214X_LCR_CHAR_7 (2 << 0) /* 7-bit character length */
-#define LPC214X_LCR_CHAR_8 (3 << 0) /* 8-bit character length */
-#define LPC214X_LCR_STOP_1 (0 << 2) /* 1 stop bit */
-#define LPC214X_LCR_STOP_2 (1 << 2) /* 2 stop bits */
-#define LPC214X_LCR_PAR_NONE (0 << 3) /* No parity */
-#define LPC214X_LCR_PAR_ODD (1 << 3) /* Odd parity */
-#define LPC214X_LCR_PAR_EVEN (3 << 3) /* Even parity */
-#define LPC214X_LCR_PAR_MARK (5 << 3) /* Mark "1" parity */
-#define LPC214X_LCR_PAR_SPACE (7 << 3) /* Space "0" parity */
-#define LPC214X_LCR_BREAK_ENABLE (1 << 6) /* Output BREAK */
-#define LPC214X_LCR_DLAB_ENABLE (1 << 7) /* Enable divisor latch access */
-
-/* Modem Control Register (MCR) bit definitions */
-
-#define LPC214X_MCR_DTR (1 << 0) /* Data terminal ready */
-#define LPC214X_MCR_RTS (1 << 1) /* Request to send */
-#define LPC214X_MCR_LB (1 << 4) /* Loopback */
-
-/* Line Status Register (LSR) bit definitions */
-
-#define LPC214X_LSR_RDR (1 << 0) /* Receive data ready */
-#define LPC214X_LSR_OE (1 << 1) /* Overrun error */
-#define LPC214X_LSR_PE (1 << 2) /* Parity error */
-#define LPC214X_LSR_FE (1 << 3) /* Framing error */
-#define LPC214X_LSR_BI (1 << 4) /* Break interrupt */
-#define LPC214X_LSR_THRE (1 << 5) /* THR empty */
-#define LPC214X_LSR_TEMT (1 << 6) /* Transmitter empty */
-#define LPC214X_LSR_RXFE (1 << 7) /* Error in receive FIFO */
-#define LPC214X_LSR_ERR_MASK 0x1e
-
-/* Modem Status Register (MSR) bit definitions */
-
-#define LPC214X_MSR_DCTS (1 << 0) /* Delta clear to send */
-#define LPC214X_MSR_DDSR (1 << 1) /* Delta data set ready */
-#define LPC214X_MSR_TERI (1 << 2) /* Trailing edge ring indicator */
-#define LPC214X_MSR_DDCD (1 << 3) /* Delta data carrier detect */
-#define LPC214X_MSR_CTS (1 << 4) /* Clear to send */
-#define LPC214X_MSR_DSR (1 << 5) /* Data set ready */
-#define LPC214X_MSR_RI (1 << 6) /* Ring indicator */
-#define LPC214X_MSR_DCD (1 << 7) /* Data carrier detect */
-
-/************************************************************************************
- * Inline Functions
- ************************************************************************************/
-
-/************************************************************************************
- * Global Function Prototypes
- ************************************************************************************/
-
-#endif /* __LPC214X_UART_H */
+/************************************************************************************ + * arch/arm/src/lpc214x/uart.h + * + * Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __LPC214X_UART_H +#define __LPC214X_UART_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <arch/board/board.h> /* For clock settings */ + +/************************************************************************************ + * Definitions + ************************************************************************************/ + +/* PINSEL0 bit definitions for UART0/1 */ + +#define LPC214X_UART0_PINSEL 0x00000005 /* PINSEL0 value for UART0 */ +#define LPC214X_UART0_PINMASK 0x0000000f /* PINSEL0 mask for UART0 */ + +#define LPC214X_UART1_PINSEL 0x00050000 /* PINSEL0 value for UART1 */ +#define LPC214X_UART1_PINMASK 0x000f0000 /* PINSEL0 mask for UART1 */ + +/* Derive baud divisor setting from clock settings (see board.h) */ + +#define UART_BAUD(baud) ((LPC214X_FOSC * LPC214X_PLL_M) / (baud * 16)) + +/* Interrupt Enable Register (IER) bit definitions */ + +#define LPC214X_IER_ERBFI (1 << 0) /* Enable receive data available int */ +#define LPC214X_IER_ETBEI (1 << 1) /* Enable THR empty Interrupt */ +#define LPC214X_IER_ELSI (1 << 2) /* Enable receive line status int */ +#define LPC214X_IER_EDSSI (1 << 3) /* Enable MODEM atatus interrupt (2146/6/8 UART1 Only) */ +#define LPC214X_IER_ALLIE 0x0f /* All interrupts */ + +/* Interrupt ID Register(IIR) bit definitions */ + +#define LPC214X_IIR_NO_INT (1 << 0) /* No interrupts pending */ +#define LPC214X_IIR_MS_INT (0 << 1) /* MODEM Status (UART1 only) */ +#define LPC214X_IIR_THRE_INT (1 << 1) /* Transmit Holding Register Empty */ +#define LPC214X_IIR_RDA_INT (2 << 1) /* Receive Data Available */ +#define LPC214X_IIR_RLS_INT (3 << 1) /* Receive Line Status */ +#define LPC214X_IIR_CTI_INT (6 << 1) /* Character Timeout Indicator */ +#define LPC214X_IIR_MASK 0x0e + +/* FIFO Control Register (FCR) bit definitions */ + +#define LPC214X_FCR_FIFO_ENABLE (1 << 0) /* FIFO enable */ +#define LPC214X_FCR_RX_FIFO_RESET (1 << 1) /* Reset receive FIFO */ +#define LPC214X_FCR_TX_FIFO_RESET (1 << 2) /* Reset transmit FIFO */ +#define LPC214X_FCR_FIFO_TRIG1 (0 << 6) /* Trigger @1 character in FIFO */ +#define LPC214X_FCR_FIFO_TRIG4 (1 << 6) /* Trigger @4 characters in FIFO */ +#define LPC214X_FCR_FIFO_TRIG8 (2 << 6) /* Trigger @8 characters in FIFO */ +#define LPC214X_FCR_FIFO_TRIG14 (3 << 6) /* Trigger @14 characters in FIFO */ + +/* Line Control Register (LCR) bit definitions */ + +#define LPC214X_LCR_CHAR_5 (0 << 0) /* 5-bit character length */ +#define LPC214X_LCR_CHAR_6 (1 << 0) /* 6-bit character length */ +#define LPC214X_LCR_CHAR_7 (2 << 0) /* 7-bit character length */ +#define LPC214X_LCR_CHAR_8 (3 << 0) /* 8-bit character length */ +#define LPC214X_LCR_STOP_1 (0 << 2) /* 1 stop bit */ +#define LPC214X_LCR_STOP_2 (1 << 2) /* 2 stop bits */ +#define LPC214X_LCR_PAR_NONE (0 << 3) /* No parity */ +#define LPC214X_LCR_PAR_ODD (1 << 3) /* Odd parity */ +#define LPC214X_LCR_PAR_EVEN (3 << 3) /* Even parity */ +#define LPC214X_LCR_PAR_MARK (5 << 3) /* Mark "1" parity */ +#define LPC214X_LCR_PAR_SPACE (7 << 3) /* Space "0" parity */ +#define LPC214X_LCR_BREAK_ENABLE (1 << 6) /* Output BREAK */ +#define LPC214X_LCR_DLAB_ENABLE (1 << 7) /* Enable divisor latch access */ + +/* Modem Control Register (MCR) bit definitions */ + +#define LPC214X_MCR_DTR (1 << 0) /* Data terminal ready */ +#define LPC214X_MCR_RTS (1 << 1) /* Request to send */ +#define LPC214X_MCR_LB (1 << 4) /* Loopback */ + +/* Line Status Register (LSR) bit definitions */ + +#define LPC214X_LSR_RDR (1 << 0) /* Receive data ready */ +#define LPC214X_LSR_OE (1 << 1) /* Overrun error */ +#define LPC214X_LSR_PE (1 << 2) /* Parity error */ +#define LPC214X_LSR_FE (1 << 3) /* Framing error */ +#define LPC214X_LSR_BI (1 << 4) /* Break interrupt */ +#define LPC214X_LSR_THRE (1 << 5) /* THR empty */ +#define LPC214X_LSR_TEMT (1 << 6) /* Transmitter empty */ +#define LPC214X_LSR_RXFE (1 << 7) /* Error in receive FIFO */ +#define LPC214X_LSR_ERR_MASK 0x1e + +/* Modem Status Register (MSR) bit definitions */ + +#define LPC214X_MSR_DCTS (1 << 0) /* Delta clear to send */ +#define LPC214X_MSR_DDSR (1 << 1) /* Delta data set ready */ +#define LPC214X_MSR_TERI (1 << 2) /* Trailing edge ring indicator */ +#define LPC214X_MSR_DDCD (1 << 3) /* Delta data carrier detect */ +#define LPC214X_MSR_CTS (1 << 4) /* Clear to send */ +#define LPC214X_MSR_DSR (1 << 5) /* Data set ready */ +#define LPC214X_MSR_RI (1 << 6) /* Ring indicator */ +#define LPC214X_MSR_DCD (1 << 7) /* Data carrier detect */ + +/************************************************************************************ + * Inline Functions + ************************************************************************************/ + +/************************************************************************************ + * Global Function Prototypes + ************************************************************************************/ + +#endif /* __LPC214X_UART_H */ diff --git a/nuttx/arch/arm/src/lpc214x/lpc214x_usbdev.h b/nuttx/arch/arm/src/lpc214x/lpc214x_usbdev.h index 67774f1fb..814622ef5 100644 --- a/nuttx/arch/arm/src/lpc214x/lpc214x_usbdev.h +++ b/nuttx/arch/arm/src/lpc214x/lpc214x_usbdev.h @@ -2,7 +2,7 @@ * arch/arm/src/lpc214x/lpc214x_usbdev.h * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/lpc214x/lpc214x_vic.h b/nuttx/arch/arm/src/lpc214x/lpc214x_vic.h index 912019e28..520c6037a 100755 --- a/nuttx/arch/arm/src/lpc214x/lpc214x_vic.h +++ b/nuttx/arch/arm/src/lpc214x/lpc214x_vic.h @@ -2,7 +2,7 @@ * arch/arm/src/lpc214x/lpc214x_vic.h * * Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/lpc2378/Make.defs b/nuttx/arch/arm/src/lpc2378/Make.defs index 2b444d317..9126fa2a1 100755 --- a/nuttx/arch/arm/src/lpc2378/Make.defs +++ b/nuttx/arch/arm/src/lpc2378/Make.defs @@ -7,7 +7,7 @@ # This file is part of the NuttX RTOS and based on the lpc2148 port: # # Copyright (C) 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt <spudmonkey@racsa.co.cr> +# Author: Gregory Nutt <gnutt@nuttx.org> # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/lpc2378/chip.h b/nuttx/arch/arm/src/lpc2378/chip.h index d371c12f0..6113f21e8 100755 --- a/nuttx/arch/arm/src/lpc2378/chip.h +++ b/nuttx/arch/arm/src/lpc2378/chip.h @@ -7,7 +7,7 @@ * This file is part of the NuttX RTOS and based on the lpc2148 port: * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/lpc2378/internal.h b/nuttx/arch/arm/src/lpc2378/internal.h index 7abd98700..5a0e63b62 100755 --- a/nuttx/arch/arm/src/lpc2378/internal.h +++ b/nuttx/arch/arm/src/lpc2378/internal.h @@ -7,7 +7,7 @@ * This file is part of the NuttX RTOS and based on the lpc2148 port: * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/lpc2378/lpc23xx_decodeirq.c b/nuttx/arch/arm/src/lpc2378/lpc23xx_decodeirq.c index 100502a22..a55ed339d 100755 --- a/nuttx/arch/arm/src/lpc2378/lpc23xx_decodeirq.c +++ b/nuttx/arch/arm/src/lpc2378/lpc23xx_decodeirq.c @@ -7,7 +7,7 @@ * This file is part of the NuttX RTOS and based on the lpc2148 port: * * Copyright (C) 2010, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/lpc2378/lpc23xx_gpio.h b/nuttx/arch/arm/src/lpc2378/lpc23xx_gpio.h index ecf629d84..f18bd685a 100755 --- a/nuttx/arch/arm/src/lpc2378/lpc23xx_gpio.h +++ b/nuttx/arch/arm/src/lpc2378/lpc23xx_gpio.h @@ -7,7 +7,7 @@ * This file is part of the NuttX RTOS and based on the lpc2148 port: * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/lpc2378/lpc23xx_irq.c b/nuttx/arch/arm/src/lpc2378/lpc23xx_irq.c index 10f188cba..96e94c454 100755 --- a/nuttx/arch/arm/src/lpc2378/lpc23xx_irq.c +++ b/nuttx/arch/arm/src/lpc2378/lpc23xx_irq.c @@ -7,7 +7,7 @@ * This file is part of the NuttX RTOS and based on the lpc2148 port: * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/lpc2378/lpc23xx_lowputc.S b/nuttx/arch/arm/src/lpc2378/lpc23xx_lowputc.S index 1d88b77fb..cc332a961 100755 --- a/nuttx/arch/arm/src/lpc2378/lpc23xx_lowputc.S +++ b/nuttx/arch/arm/src/lpc2378/lpc23xx_lowputc.S @@ -7,7 +7,7 @@ * This file is part of the NuttX RTOS and based on the lpc2148 port: * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/lpc2378/lpc23xx_pinsel.h b/nuttx/arch/arm/src/lpc2378/lpc23xx_pinsel.h index 04c6507b1..10a97c7f1 100755 --- a/nuttx/arch/arm/src/lpc2378/lpc23xx_pinsel.h +++ b/nuttx/arch/arm/src/lpc2378/lpc23xx_pinsel.h @@ -7,7 +7,7 @@ * This file is part of the NuttX RTOS and based on the lpc2148 port: * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/lpc2378/lpc23xx_scb.h b/nuttx/arch/arm/src/lpc2378/lpc23xx_scb.h index e80f8e23e..d876ef6ec 100755 --- a/nuttx/arch/arm/src/lpc2378/lpc23xx_scb.h +++ b/nuttx/arch/arm/src/lpc2378/lpc23xx_scb.h @@ -7,7 +7,7 @@ * This file is part of the NuttX RTOS and based on the lpc2148 port: * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/lpc2378/lpc23xx_timer.h b/nuttx/arch/arm/src/lpc2378/lpc23xx_timer.h index 28439e220..4de1b3fff 100755 --- a/nuttx/arch/arm/src/lpc2378/lpc23xx_timer.h +++ b/nuttx/arch/arm/src/lpc2378/lpc23xx_timer.h @@ -7,7 +7,7 @@ * This file is part of the NuttX RTOS and based on the lpc2148 port: * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/lpc2378/lpc23xx_timerisr.c b/nuttx/arch/arm/src/lpc2378/lpc23xx_timerisr.c index 5e8d5696d..d9e63d6d6 100755 --- a/nuttx/arch/arm/src/lpc2378/lpc23xx_timerisr.c +++ b/nuttx/arch/arm/src/lpc2378/lpc23xx_timerisr.c @@ -7,7 +7,7 @@ * This file is part of the NuttX RTOS and based on the lpc2148 port: * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/lpc2378/lpc23xx_uart.h b/nuttx/arch/arm/src/lpc2378/lpc23xx_uart.h index e493a0abd..2c8999bfa 100755 --- a/nuttx/arch/arm/src/lpc2378/lpc23xx_uart.h +++ b/nuttx/arch/arm/src/lpc2378/lpc23xx_uart.h @@ -1,231 +1,231 @@ -/************************************************************************************
- * arch/arm/src/lpc2378/lpc2378/uart.h
- *
- * Copyright (C) 2010 Rommel Marcelo. All rights reserved.
- * Author: Rommel Marcelo
- *
- * This file is part of the NuttX RTOS and based on the lpc2148 port:
- *
- * Copyright (C) 2010 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_LPC2378_LPC23XX_UART_H
-#define __ARCH_ARM_SRC_LPC2378_LPC23XX_UART_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <arch/board/board.h> /* For clock settings */
-
-/************************************************************************************
- * Definitions
- ************************************************************************************/
-/* Derive baud divisor setting from clock settings (see board.h) */
-//--F_in = 57 600 000 Hz U0DLM=0, U0DLL=25, DIVADDVAL=3, MULVAL=12, baudrate=115200, err = 0.000000 %
-//--F_in = 57 600 000 Hz U0DLM=1, U0DLL=119, DIVADDVAL=0, MULVAL=1, baudrate=9600, err = 0.000000 %
-/* Used only if CONFIG_UART_MULVAL is not defined */
-#define DIVADDVAL 0
-#define MULVAL 1
-#define DLMVAL 1
-#define DLLVAL 119
-
-/* UARTx PCLK divider valid values are 1,2,4 */
-#define U0_PCLKDIV 1
-//~ #define U1_PCLKDIV 1
-#define U2_PCLKDIV 1
-//~ #define U3_PCLKDIV 1
-
-
-#define U0_PCLK (CCLK / U0_PCLKDIV)
-//~ #define U1_PCLK (CCLK / U1_PCLKDIV)
-#define U2_PCLK (CCLK / U2_PCLKDIV)
-//~ #define U3_PCLK (CCLK / U3_PCLKDIV)
-
-#define U0_PCLKSEL_MASK (0x000000C0)
-#define U2_PCLKSEL_MASK (0x00030000)
-
-/* PCKLSEL0 bits 7:6, 00=CCLK/4, 01=CCLK/1 , 10=CCLK/2 */
-#ifdef U0_PCLKDIV
-# if U0_PCLKDIV == 1
-# define U0_PCLKSEL (0x00000040)
-# elif U0_PCLKDIV == 2
-# define U0_PCLKSEL (0x00000080)
-# elif U0_PCLKDIV == 4
-# define U0_PCLKSEL (0x00000000)
-# endif
-#else
-# error "UART0 PCLK divider not set"
-#endif
-
-/* PCKLSEL1 bits 17:16, 00=CCLK/4, 01=CCLK/1 , 10=CCLK/2 */
-#ifdef U2_PCLKDIV
-# if U2_PCLKDIV == 1
-# define U2_PCLKSEL (0x00010000)
-# elif U2_PCLKDIV == 2
-# define U2_PCLKSEL (0x00020000)
-# elif U2_PCLKDIV == 4
-# define U2_PCLKSEL (0x00000000)
-# endif
-#else
-# error "UART2 PCLK divider not set"
-#endif
-
-
-
-
-/* Universal Asynchronous Receiver Transmitter Base Addresses */
-#define UART0_BASE_ADDR 0xE000C000
-#define UART1_BASE_ADDR 0xE0010000
-#define UART2_BASE_ADDR 0xE0078000
-#define UART3_BASE_ADDR 0xE007C000
-
-/* UART 0/1/2/3 Register Offsets */
-#define UART_RBR_OFFSET 0x00 /* R: Receive Buffer Register (DLAB=0) */
-#define UART_THR_OFFSET 0x00 /* W: Transmit Holding Register (DLAB=0) */
-#define UART_DLL_OFFSET 0x00 /* W: Divisor Latch Register (LSB, DLAB=1) */
-#define UART_IER_OFFSET 0x04 /* W: Interrupt Enable Register (DLAB=0) */
-#define UART_DLM_OFFSET 0x04 /* RW: Divisor Latch Register (MSB, DLAB=1) */
-#define UART_IIR_OFFSET 0x08 /* R: Interrupt ID Register */
-#define UART_FCR_OFFSET 0x08 /* W: FIFO Control Register */
-#define UART_LCR_OFFSET 0x0c /* RW: Line Control Register */
-#define UART_MCR_OFFSET 0x10 /* RW: Modem Control REgister (2146/6/8 UART1 Only) */
-#define UART_LSR_OFFSET 0x14 /* R: Scratch Pad Register */
-#define UART_MSR_OFFSET 0x18 /* RW: MODEM Status Register (2146/6/8 UART1 Only) */
-#define UART_SCR_OFFSET 0x1c /* RW: Line Status Register */
-#define UART_ACR_OFFSET 0x20 /* RW: Autobaud Control Register */
-#define UART_FDR_OFFSET 0x28 /* RW: Fractional Divider Register */
-#define UART_TER_OFFSET 0x30 /* RW: Transmit Enable Register */
-
-/* PINSEL0 bit definitions for UART0/2 */
-
-#define UART0_PINSEL 0x00000050 /* PINSEL0 value for UART0 */
-#define UART0_PINMASK 0x000000F0 /* PINSEL0 mask for UART0 */
-
-#define UART1_TX_PINSEL 0x40000000 /* PINSEL0 value for UART1 Tx */
-#define UART1_TXPINMASK 0xC0000000 /* PINSEL0 mask for UART1 Tx */
-#define UART1_RX_PINSEL 0x00000001 /* PINSEL1 value for UART1 Rx */
-#define UART1_RX_PINMASK 0x00000003 /* PINSEL1 mask for UART1 Rx */
-#define UART1_MODEM_PINSEL 0x00001555 /* PINSEL1 mask for UART1 Modem Interface */
-#define UART1_CTS_PINMASK 0x00003FFF /* PINSEL1 mask for UART1 Modem Interface */
-//~ #define UART1_CTS_PINSEL 0x00000004 /* PINSEL1 mask for UART1 CTS */
-//~ #define UART1_CTS_PINMASK 0x0000000C /* PINSEL1 mask for UART1 CTS */
-//~ #define UART1_CTS_PINSEL 0x00000010 /* PINSEL1 mask for UART1 Rx */
-//~ #define UART1_CTS_PINMASK 0x00000030 /* PINSEL1 mask for UART1 Rx */
-#define UART2_PINSEL 0x00500000 /* PINSEL0 value for UART2 */
-#define UART2_PINMASK 0x00F00000 /* PINSEL0 mask for UART2 */
-
-#define UART3_PINSEL 0x0F000000 /* PINSEL9 value for UART3 */
-#define UART3_PINMASK 0x0F000000 /* PINSEL9 mask for UART3 */
-
-/* Interrupt Enable Register (IER) bit definitions */
-
-#define IER_ERBFI (1 << 0) /* Enable receive data available int */
-#define IER_ETBEI (1 << 1) /* Enable THR empty Interrupt */
-#define IER_ELSI (1 << 2) /* Enable receive line status int */
-#define IER_EDSSI (1 << 3) /* Enable MODEM atatus interrupt (2146/6/8 UART1 Only) */
-#define IER_ALLIE 0x0f /* All interrupts */
-
-/* Interrupt ID Register(IIR) bit definitions */
-
-#define IIR_NO_INT (1 << 0) /* No interrupts pending */
-#define IIR_MS_INT (0 << 1) /* MODEM Status (UART1 only) */
-#define IIR_THRE_INT (1 << 1) /* Transmit Holding Register Empty */
-#define IIR_RDA_INT (2 << 1) /* Receive Data Available */
-#define IIR_RLS_INT (3 << 1) /* Receive Line Status */
-#define IIR_CTI_INT (6 << 1) /* Character Timeout Indicator */
-#define IIR_MASK 0x0e
-
-/* FIFO Control Register (FCR) bit definitions */
-
-#define FCR_FIFO_ENABLE (1 << 0) /* FIFO enable */
-#define FCR_RX_FIFO_RESET (1 << 1) /* Reset receive FIFO */
-#define FCR_TX_FIFO_RESET (1 << 2) /* Reset transmit FIFO */
-#define FCR_FIFO_TRIG1 (0 << 6) /* Trigger @1 character in FIFO */
-#define FCR_FIFO_TRIG4 (1 << 6) /* Trigger @4 characters in FIFO */
-#define FCR_FIFO_TRIG8 (2 << 6) /* Trigger @8 characters in FIFO */
-#define FCR_FIFO_TRIG14 (3 << 6) /* Trigger @14 characters in FIFO */
-
-/* Line Control Register (LCR) bit definitions */
-
-#define LCR_CHAR_5 (0 << 0) /* 5-bit character length */
-#define LCR_CHAR_6 (1 << 0) /* 6-bit character length */
-#define LCR_CHAR_7 (2 << 0) /* 7-bit character length */
-#define LCR_CHAR_8 (3 << 0) /* 8-bit character length */
-#define LCR_STOP_1 (0 << 2) /* 1 stop bit */
-#define LCR_STOP_2 (1 << 2) /* 2 stop bits */
-#define LCR_PAR_NONE (0 << 3) /* No parity */
-#define LCR_PAR_ODD (1 << 3) /* Odd parity */
-#define LCR_PAR_EVEN (3 << 3) /* Even parity */
-#define LCR_PAR_MARK (5 << 3) /* Mark "1" parity */
-#define LCR_PAR_SPACE (7 << 3) /* Space "0" parity */
-#define LCR_BREAK_ENABLE (1 << 6) /* Output BREAK */
-#define LCR_DLAB_ENABLE (1 << 7) /* Enable divisor latch access */
-
-/* Modem Control Register (MCR) bit definitions */
-
-#define MCR_DTR (1 << 0) /* Data terminal ready */
-#define MCR_RTS (1 << 1) /* Request to send */
-#define MCR_LB (1 << 4) /* Loopback */
-
-/* Line Status Register (LSR) bit definitions */
-
-#define LSR_RDR (1 << 0) /* Receive data ready */
-#define LSR_OE (1 << 1) /* Overrun error */
-#define LSR_PE (1 << 2) /* Parity error */
-#define LSR_FE (1 << 3) /* Framing error */
-#define LSR_BI (1 << 4) /* Break interrupt */
-#define LSR_THRE (1 << 5) /* THR empty */
-#define LSR_TEMT (1 << 6) /* Transmitter empty */
-#define LSR_RXFE (1 << 7) /* Error in receive FIFO */
-#define LSR_ERR_MASK 0x1e
-
-/* Modem Status Register (MSR) bit definitions */
-
-#define MSR_DCTS (1 << 0) /* Delta clear to send */
-#define MSR_DDSR (1 << 1) /* Delta data set ready */
-#define MSR_TERI (1 << 2) /* Trailing edge ring indicator */
-#define MSR_DDCD (1 << 3) /* Delta data carrier detect */
-#define MSR_CTS (1 << 4) /* Clear to send */
-#define MSR_DSR (1 << 5) /* Data set ready */
-#define MSR_RI (1 << 6) /* Ring indicator */
-#define MSR_DCD (1 << 7) /* Data carrier detect */
-
-/************************************************************************************
- * Inline Functions
- ************************************************************************************/
-
-/************************************************************************************
- * Global Function Prototypes
- ************************************************************************************/
-
-#endif /* __ARCH_ARM_SRC_LPC2378_LPC23XX_UART_H */
+/************************************************************************************ + * arch/arm/src/lpc2378/lpc2378/uart.h + * + * Copyright (C) 2010 Rommel Marcelo. All rights reserved. + * Author: Rommel Marcelo + * + * This file is part of the NuttX RTOS and based on the lpc2148 port: + * + * Copyright (C) 2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC2378_LPC23XX_UART_H +#define __ARCH_ARM_SRC_LPC2378_LPC23XX_UART_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <arch/board/board.h> /* For clock settings */ + +/************************************************************************************ + * Definitions + ************************************************************************************/ +/* Derive baud divisor setting from clock settings (see board.h) */ +//--F_in = 57 600 000 Hz U0DLM=0, U0DLL=25, DIVADDVAL=3, MULVAL=12, baudrate=115200, err = 0.000000 % +//--F_in = 57 600 000 Hz U0DLM=1, U0DLL=119, DIVADDVAL=0, MULVAL=1, baudrate=9600, err = 0.000000 % +/* Used only if CONFIG_UART_MULVAL is not defined */ +#define DIVADDVAL 0 +#define MULVAL 1 +#define DLMVAL 1 +#define DLLVAL 119 + +/* UARTx PCLK divider valid values are 1,2,4 */ +#define U0_PCLKDIV 1 +//~ #define U1_PCLKDIV 1 +#define U2_PCLKDIV 1 +//~ #define U3_PCLKDIV 1 + + +#define U0_PCLK (CCLK / U0_PCLKDIV) +//~ #define U1_PCLK (CCLK / U1_PCLKDIV) +#define U2_PCLK (CCLK / U2_PCLKDIV) +//~ #define U3_PCLK (CCLK / U3_PCLKDIV) + +#define U0_PCLKSEL_MASK (0x000000C0) +#define U2_PCLKSEL_MASK (0x00030000) + +/* PCKLSEL0 bits 7:6, 00=CCLK/4, 01=CCLK/1 , 10=CCLK/2 */ +#ifdef U0_PCLKDIV +# if U0_PCLKDIV == 1 +# define U0_PCLKSEL (0x00000040) +# elif U0_PCLKDIV == 2 +# define U0_PCLKSEL (0x00000080) +# elif U0_PCLKDIV == 4 +# define U0_PCLKSEL (0x00000000) +# endif +#else +# error "UART0 PCLK divider not set" +#endif + +/* PCKLSEL1 bits 17:16, 00=CCLK/4, 01=CCLK/1 , 10=CCLK/2 */ +#ifdef U2_PCLKDIV +# if U2_PCLKDIV == 1 +# define U2_PCLKSEL (0x00010000) +# elif U2_PCLKDIV == 2 +# define U2_PCLKSEL (0x00020000) +# elif U2_PCLKDIV == 4 +# define U2_PCLKSEL (0x00000000) +# endif +#else +# error "UART2 PCLK divider not set" +#endif + + + + +/* Universal Asynchronous Receiver Transmitter Base Addresses */ +#define UART0_BASE_ADDR 0xE000C000 +#define UART1_BASE_ADDR 0xE0010000 +#define UART2_BASE_ADDR 0xE0078000 +#define UART3_BASE_ADDR 0xE007C000 + +/* UART 0/1/2/3 Register Offsets */ +#define UART_RBR_OFFSET 0x00 /* R: Receive Buffer Register (DLAB=0) */ +#define UART_THR_OFFSET 0x00 /* W: Transmit Holding Register (DLAB=0) */ +#define UART_DLL_OFFSET 0x00 /* W: Divisor Latch Register (LSB, DLAB=1) */ +#define UART_IER_OFFSET 0x04 /* W: Interrupt Enable Register (DLAB=0) */ +#define UART_DLM_OFFSET 0x04 /* RW: Divisor Latch Register (MSB, DLAB=1) */ +#define UART_IIR_OFFSET 0x08 /* R: Interrupt ID Register */ +#define UART_FCR_OFFSET 0x08 /* W: FIFO Control Register */ +#define UART_LCR_OFFSET 0x0c /* RW: Line Control Register */ +#define UART_MCR_OFFSET 0x10 /* RW: Modem Control REgister (2146/6/8 UART1 Only) */ +#define UART_LSR_OFFSET 0x14 /* R: Scratch Pad Register */ +#define UART_MSR_OFFSET 0x18 /* RW: MODEM Status Register (2146/6/8 UART1 Only) */ +#define UART_SCR_OFFSET 0x1c /* RW: Line Status Register */ +#define UART_ACR_OFFSET 0x20 /* RW: Autobaud Control Register */ +#define UART_FDR_OFFSET 0x28 /* RW: Fractional Divider Register */ +#define UART_TER_OFFSET 0x30 /* RW: Transmit Enable Register */ + +/* PINSEL0 bit definitions for UART0/2 */ + +#define UART0_PINSEL 0x00000050 /* PINSEL0 value for UART0 */ +#define UART0_PINMASK 0x000000F0 /* PINSEL0 mask for UART0 */ + +#define UART1_TX_PINSEL 0x40000000 /* PINSEL0 value for UART1 Tx */ +#define UART1_TXPINMASK 0xC0000000 /* PINSEL0 mask for UART1 Tx */ +#define UART1_RX_PINSEL 0x00000001 /* PINSEL1 value for UART1 Rx */ +#define UART1_RX_PINMASK 0x00000003 /* PINSEL1 mask for UART1 Rx */ +#define UART1_MODEM_PINSEL 0x00001555 /* PINSEL1 mask for UART1 Modem Interface */ +#define UART1_CTS_PINMASK 0x00003FFF /* PINSEL1 mask for UART1 Modem Interface */ +//~ #define UART1_CTS_PINSEL 0x00000004 /* PINSEL1 mask for UART1 CTS */ +//~ #define UART1_CTS_PINMASK 0x0000000C /* PINSEL1 mask for UART1 CTS */ +//~ #define UART1_CTS_PINSEL 0x00000010 /* PINSEL1 mask for UART1 Rx */ +//~ #define UART1_CTS_PINMASK 0x00000030 /* PINSEL1 mask for UART1 Rx */ +#define UART2_PINSEL 0x00500000 /* PINSEL0 value for UART2 */ +#define UART2_PINMASK 0x00F00000 /* PINSEL0 mask for UART2 */ + +#define UART3_PINSEL 0x0F000000 /* PINSEL9 value for UART3 */ +#define UART3_PINMASK 0x0F000000 /* PINSEL9 mask for UART3 */ + +/* Interrupt Enable Register (IER) bit definitions */ + +#define IER_ERBFI (1 << 0) /* Enable receive data available int */ +#define IER_ETBEI (1 << 1) /* Enable THR empty Interrupt */ +#define IER_ELSI (1 << 2) /* Enable receive line status int */ +#define IER_EDSSI (1 << 3) /* Enable MODEM atatus interrupt (2146/6/8 UART1 Only) */ +#define IER_ALLIE 0x0f /* All interrupts */ + +/* Interrupt ID Register(IIR) bit definitions */ + +#define IIR_NO_INT (1 << 0) /* No interrupts pending */ +#define IIR_MS_INT (0 << 1) /* MODEM Status (UART1 only) */ +#define IIR_THRE_INT (1 << 1) /* Transmit Holding Register Empty */ +#define IIR_RDA_INT (2 << 1) /* Receive Data Available */ +#define IIR_RLS_INT (3 << 1) /* Receive Line Status */ +#define IIR_CTI_INT (6 << 1) /* Character Timeout Indicator */ +#define IIR_MASK 0x0e + +/* FIFO Control Register (FCR) bit definitions */ + +#define FCR_FIFO_ENABLE (1 << 0) /* FIFO enable */ +#define FCR_RX_FIFO_RESET (1 << 1) /* Reset receive FIFO */ +#define FCR_TX_FIFO_RESET (1 << 2) /* Reset transmit FIFO */ +#define FCR_FIFO_TRIG1 (0 << 6) /* Trigger @1 character in FIFO */ +#define FCR_FIFO_TRIG4 (1 << 6) /* Trigger @4 characters in FIFO */ +#define FCR_FIFO_TRIG8 (2 << 6) /* Trigger @8 characters in FIFO */ +#define FCR_FIFO_TRIG14 (3 << 6) /* Trigger @14 characters in FIFO */ + +/* Line Control Register (LCR) bit definitions */ + +#define LCR_CHAR_5 (0 << 0) /* 5-bit character length */ +#define LCR_CHAR_6 (1 << 0) /* 6-bit character length */ +#define LCR_CHAR_7 (2 << 0) /* 7-bit character length */ +#define LCR_CHAR_8 (3 << 0) /* 8-bit character length */ +#define LCR_STOP_1 (0 << 2) /* 1 stop bit */ +#define LCR_STOP_2 (1 << 2) /* 2 stop bits */ +#define LCR_PAR_NONE (0 << 3) /* No parity */ +#define LCR_PAR_ODD (1 << 3) /* Odd parity */ +#define LCR_PAR_EVEN (3 << 3) /* Even parity */ +#define LCR_PAR_MARK (5 << 3) /* Mark "1" parity */ +#define LCR_PAR_SPACE (7 << 3) /* Space "0" parity */ +#define LCR_BREAK_ENABLE (1 << 6) /* Output BREAK */ +#define LCR_DLAB_ENABLE (1 << 7) /* Enable divisor latch access */ + +/* Modem Control Register (MCR) bit definitions */ + +#define MCR_DTR (1 << 0) /* Data terminal ready */ +#define MCR_RTS (1 << 1) /* Request to send */ +#define MCR_LB (1 << 4) /* Loopback */ + +/* Line Status Register (LSR) bit definitions */ + +#define LSR_RDR (1 << 0) /* Receive data ready */ +#define LSR_OE (1 << 1) /* Overrun error */ +#define LSR_PE (1 << 2) /* Parity error */ +#define LSR_FE (1 << 3) /* Framing error */ +#define LSR_BI (1 << 4) /* Break interrupt */ +#define LSR_THRE (1 << 5) /* THR empty */ +#define LSR_TEMT (1 << 6) /* Transmitter empty */ +#define LSR_RXFE (1 << 7) /* Error in receive FIFO */ +#define LSR_ERR_MASK 0x1e + +/* Modem Status Register (MSR) bit definitions */ + +#define MSR_DCTS (1 << 0) /* Delta clear to send */ +#define MSR_DDSR (1 << 1) /* Delta data set ready */ +#define MSR_TERI (1 << 2) /* Trailing edge ring indicator */ +#define MSR_DDCD (1 << 3) /* Delta data carrier detect */ +#define MSR_CTS (1 << 4) /* Clear to send */ +#define MSR_DSR (1 << 5) /* Data set ready */ +#define MSR_RI (1 << 6) /* Ring indicator */ +#define MSR_DCD (1 << 7) /* Data carrier detect */ + +/************************************************************************************ + * Inline Functions + ************************************************************************************/ + +/************************************************************************************ + * Global Function Prototypes + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC2378_LPC23XX_UART_H */ diff --git a/nuttx/arch/arm/src/lpc2378/lpc23xx_vic.h b/nuttx/arch/arm/src/lpc2378/lpc23xx_vic.h index 964c93ed9..c8b9871a1 100755 --- a/nuttx/arch/arm/src/lpc2378/lpc23xx_vic.h +++ b/nuttx/arch/arm/src/lpc2378/lpc23xx_vic.h @@ -7,7 +7,7 @@ * This file is part of the NuttX RTOS and based on the lpc2148 port: * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_qei.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_qei.h index 5e110ce15..9994c4e9e 100644 --- a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_qei.h +++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_qei.h @@ -2,7 +2,7 @@ * arch/arm/src/lpc43xx/lpc43_qei.h * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_usb0dev.c b/nuttx/arch/arm/src/lpc43xx/lpc43_usb0dev.c index b4ca55420..a40d6492d 100644 --- a/nuttx/arch/arm/src/lpc43xx/lpc43_usb0dev.c +++ b/nuttx/arch/arm/src/lpc43xx/lpc43_usb0dev.c @@ -7,7 +7,7 @@ * Part of the NuttX OS and based, in part, on the LPC31xx USB driver: * * Authors: David Hewson - * Gregory Nutt <spudmonkey@racsa.co.cr> + * Gregory Nutt <gnutt@nuttx.org> * * Which, in turn, was based on the LPC2148 USB driver: * diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_usb0dev.h b/nuttx/arch/arm/src/lpc43xx/lpc43_usb0dev.h index 94a2a64ea..fae22d323 100644 --- a/nuttx/arch/arm/src/lpc43xx/lpc43_usb0dev.h +++ b/nuttx/arch/arm/src/lpc43xx/lpc43_usb0dev.h @@ -2,7 +2,7 @@ * arch/arm/src/lpc43xx/lpc43_usbdev.h * * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/sam3u/chip.h b/nuttx/arch/arm/src/sam3u/chip.h index 7e18e45c9..865cad5ea 100644 --- a/nuttx/arch/arm/src/sam3u/chip.h +++ b/nuttx/arch/arm/src/sam3u/chip.h @@ -2,7 +2,7 @@ * arch/arm/src/sam3u/chip.h * * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/sam3u/sam3u_adc.h b/nuttx/arch/arm/src/sam3u/sam3u_adc.h index 6b1f9552e..4701c0c48 100644 --- a/nuttx/arch/arm/src/sam3u/sam3u_adc.h +++ b/nuttx/arch/arm/src/sam3u/sam3u_adc.h @@ -1,236 +1,236 @@ -/****************************************************************************************
- * arch/arm/src/sam3u/sam3u_adc.h
- *
- * Copyright (C) 2009 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_ADC_H
-#define __ARCH_ARM_SRC_SAM3U_SAM3U_ADC_H
-
-/****************************************************************************************
- * Included Files
- ****************************************************************************************/
-
-#include <nuttx/config.h>
-
-#include "chip.h"
-#include "sam3u_memorymap.h"
-
-/****************************************************************************************
- * Pre-processor Definitions
- ****************************************************************************************/
-
-/* ADC register offsets ****************************************************************/
-
-#define SAM3U_ADC_CR_OFFSET 0x00 /* Control Register (Both) */
-#define SAM3U_ADC_MR_OFFSET 0x04 /* Mode Register (Both) */
- /* 0x08: Reserved */
- /* 0x0c: Reserved */
-#define SAM3U_ADC_CHER_OFFSET 0x10 /* Channel Enable Register (Both) */
-#define SAM3U_ADC_CHDR_OFFSET 0x14 /* Channel Disable Register (Both) */
-#define SAM3U_ADC_CHSR_OFFSET 0x18 /* Channel Status Register (Both) */
-#define SAM3U_ADC_SR_OFFSET 0x1c /* Status Register (Both) */
-#define SAM3U_ADC_LCDR_OFFSET 0x20 /* Last Converted Data Register (Both) */
-#define SAM3U_ADC_IER_OFFSET 0x24 /* Interrupt Enable Register (Both) */
-#define SAM3U_ADC_IDR_OFFSET 0x28 /* Interrupt Disable Register (Both) */
-#define SAM3U_ADC_IMR_OFFSET 0x2c /* Interrupt Mask Register (Both) */
-#define SAM3U_ADC_CDR_OFFSET(n) (0x30+((n)<<2))
-#define SAM3U_ADC_CDR0_OFFSET 0x30 /* Channel Data Register 0 (Both) */
-#define SAM3U_ADC_CDR1_OFFSET 0x34 /* Channel Data Register 1 (Both) */
-#define SAM3U_ADC_CDR2_OFFSET 0x38 /* Channel Data Register 2 (Both) */
-#define SAM3U_ADC_CDR3_OFFSET 0x3c /* Channel Data Register 3 (Both) */
-#define SAM3U_ADC_CDR4_OFFSET 0x40 /* Channel Data Register 4 (Both) */
-#define SAM3U_ADC_CDR5_OFFSET 0x44 /* Channel Data Register 5 (Both) */
-#define SAM3U_ADC_CDR6_OFFSET 0x48 /* Channel Data Register 6 (Both) */
-#define SAM3U_ADC_CDR7_OFFSET 0x4c /* Channel Data Register 7 (Both) */
-#define SAM3U_ADC12B_ACR_OFFSET 0x64 /* Analog Control Register (ADC12B only) */
-#define SAM3U_ADC12B_EMR_OFFSET 0x68 /* Extended Mode Register (ADC12B only) */
-
-/* ADC register adresses ***************************************************************/
-
-#define SAM3U_ADC12B_CR (SAM3U_ADC12B_BASE+SAM3U_ADC_CR_OFFSET)
-#define SAM3U_ADC12B_MR (SAM3U_ADC12B_BASE+SAM3U_ADC_MR_OFFSET)
-#define SAM3U_ADC12B_CHER (SAM3U_ADC12B_BASE+SAM3U_ADC_CHER_OFFSET)
-#define SAM3U_ADC12B_CHDR (SAM3U_ADC12B_BASE+SAM3U_ADC_CHDR_OFFSET)
-#define SAM3U_ADC12B_CHSR (SAM3U_ADC12B_BASE+SAM3U_ADC_CHSR_OFFSET)
-#define SAM3U_ADC12B_SR (SAM3U_ADC12B_BASE+SAM3U_ADC_SR_OFFSET)
-#define SAM3U_ADC12B_LCDR_ (SAM3U_ADC12B_BASE+SAM3U_ADC_LCDR_OFFSET)
-#define SAM3U_ADC12B_IER (SAM3U_ADC12B_BASE+SAM3U_ADC_IER_OFFSET)
-#define SAM3U_ADC12B_IDR (SAM3U_ADC12B_BASE+SAM3U_ADC_IDR_OFFSET)
-#define SAM3U_ADC12B_IMR (SAM3U_ADC12B_BASE+SAM3U_ADC_IMR_OFFSET)
-#define SAM3U_ADC12B_CDR(n)) (SAM3U_ADC12B_BASE+SAM3U_ADC_CDR_OFFSET(n))
-#define SAM3U_ADC12B_CDR0 (SAM3U_ADC12B_BASE+SAM3U_ADC_CDR0_OFFSET)
-#define SAM3U_ADC12B_CDR1 (SAM3U_ADC12B_BASE+SAM3U_ADC_CDR1_OFFSET)
-#define SAM3U_ADC12B_CDR2 (SAM3U_ADC12B_BASE+SAM3U_ADC_CDR2_OFFSET)
-#define SAM3U_ADC12B_CDR3 (SAM3U_ADC12B_BASE+SAM3U_ADC_CDR3_OFFSET)
-#define SAM3U_ADC12B_CDR4 (SAM3U_ADC12B_BASE+SAM3U_ADC_CDR4_OFFSET)
-#define SAM3U_ADC12B_CDR5 (SAM3U_ADC12B_BASE+SAM3U_ADC_CDR5_OFFSET)
-#define SAM3U_ADC12B_CDR6 (SAM3U_ADC12B_BASE+SAM3U_ADC_CDR6_OFFSET)
-#define SAM3U_ADC12B_CDR7 (SAM3U_ADC12B_BASE+SAM3U_ADC_CDR7_OFFSET)
-#define SAM3U_ADC12B_ACR (SAM3U_ADC12B_BASE+SAM3U_ADC12B_ACR_OFFSET)
-#define SAM3U_ADC12B_EMR (SAM3U_ADC12B_BASE+SAM3U_ADC12B_EMR_OFFSET)
-
-#define SAM3U_ADC_CR (SAM3U_ADC_BASE+SAM3U_ADC_CR_OFFSET)
-#define SAM3U_ADC_MR (SAM3U_ADC_BASE+SAM3U_ADC_MR_OFFSET)
-#define SAM3U_ADC_CHER (SAM3U_ADC_BASE+SAM3U_ADC_CHER_OFFSET)
-#define SAM3U_ADC_CHDR (SAM3U_ADC_BASE+SAM3U_ADC_CHDR_OFFSET)
-#define SAM3U_ADC_CHSR (SAM3U_ADC_BASE+SAM3U_ADC_CHSR_OFFSET)
-#define SAM3U_ADC_SR (SAM3U_ADC_BASE+SAM3U_ADC_SR_OFFSET)
-#define SAM3U_ADC_LCDR (SAM3U_ADC_BASE+SAM3U_ADC_LCDR_OFFSET)
-#define SAM3U_ADC_IER (SAM3U_ADC_BASE+SAM3U_ADC_IER_OFFSET)
-#define SAM3U_ADC_IDR (SAM3U_ADC_BASE+SAM3U_ADC_IDR_OFFSET)
-#define SAM3U_ADC_IMR (SAM3U_ADC_BASE+SAM3U_ADC_IMR_OFFSET)
-#define SAM3U_ADC_CDR(n)) (SAM3U_ADC_BASE+SAM3U_ADC_CDR_OFFSET(n))
-#define SAM3U_ADC_CDR0 (SAM3U_ADC_BASE+SAM3U_ADC_CDR0_OFFSET)
-#define SAM3U_ADC_CDR1 (SAM3U_ADC_BASE+SAM3U_ADC_CDR1_OFFSET)
-#define SAM3U_ADC_CDR2 (SAM3U_ADC_BASE+SAM3U_ADC_CDR2_OFFSET)
-#define SAM3U_ADC_CDR3 (SAM3U_ADC_BASE+SAM3U_ADC_CDR3_OFFSET)
-#define SAM3U_ADC_CDR4 (SAM3U_ADC_BASE+SAM3U_ADC_CDR4_OFFSET)
-#define SAM3U_ADC_CDR5 (SAM3U_ADC_BASE+SAM3U_ADC_CDR5_OFFSET)
-#define SAM3U_ADC_CDR6 (SAM3U_ADC_BASE+SAM3U_ADC_CDR6_OFFSET)
-#define SAM3U_ADC_CDR7 (SAM3U_ADC_BASE+SAM3U_ADC_CDR7_OFFSET)
-
-/* ADC register bit definitions ********************************************************/
-
-/* ADC12B Control Register and ADC(10B) Control Register common bit-field definitions */
-
-#define ADC_CR_SWRST (1 << 0) /* Bit 0: Software Reset */
-#define ADC_CR_START (1 << 1) /* Bit 1: Start Conversion */
-
-/* ADC12B Mode Register and ADC(10B) Mode Register common bit-field definitions */
-
-#define ADC_MR_TRGEN (1 << 0) /* Bit 0: Trigger Enable */
-#define ADC_MR_TRGSEL_SHIFT (1) /* Bits 1-3: Trigger Selection */
-#define ADC_MR_TRGSEL_MASK (7 << ADC_MR_TRGSEL_SHIFT)
-#define ADC_MR_LOWRES (1 << 4) /* Bit 4: Resolution */
-#define ADC_MR_SLEEP (1 << 5) /* Bit 5: Sleep Mode */
-#define ADC_MR_PRESCAL_SHIFT (8) /* Bits 8-15: Prescaler Rate Selection */
-#define ADC_MR_PRESCAL_MASK (0xff << ADC_MR_PRESCAL_SHIFT)
-#define ADB12B_MRSTARTUP_SHIFT (16) /* Bits 16-23: Start Up Time (ADC12B) */
-#define ADB12B_MRSTARTUP_MASK (0xff << ADB12B_MRSTARTUP_SHIFT
-#define ADB10B_MRSTARTUP_SHIFT (16) /* Bits 16-22: Start Up Time (ADC10B) */
-#define ADB10B_MRSTARTUP_MASK (0x7f << ADB10B_MRSTARTUP_SHIFT)
-#define ADC_MR_SHTIM_SHIFT (24) /* Bits 24-27: Sample & Hold Time */
-#define ADC_MR_SHTIM_MASK (15 << ADC_MR_SHTIM_SHIFT)
-
-/* ADC12B Channel Enable Register, ADC12B Channel Disable Register, ADC12B Channel
- * Status Register, ADC(10B) Channel Enable Register, ADC(10B) Channel Disable Register,
- * and ADC(10B) Channel Status Register common bit-field definitions
- */
-
-#define ADC_CH(n) (1 << (n))
-#define ADC_CH0 (1 << 0) /* Bit 0: Channel x Enable */
-#define ADC_CH1 (1 << 1) /* Bit 1: Channel x Enable */
-#define ADC_CH2 (1 << 2) /* Bit 2: Channel x Enable */
-#define ADC_CH3 (1 << 3) /* Bit 3: Channel x Enable */
-#define ADC_CH4 (1 << 4) /* Bit 4: Channel x Enable */
-#define ADC_CH5 (1 << 5) /* Bit 5: Channel x Enable */
-#define ADC_CH6 (1 << 6) /* Bit 6: Channel x Enable */
-#define ADC_CH7 (1 << 7) /* Bit 7: Channel x Enable */
-
-/* ADC12B Analog Control Register (ADC12B only) */
-
-#define ADC12B_ACR_GAIN_SHIFT (0) /* Bits 0-1: Input Gain */
-#define ADC12B_ACR_GAIN_MASK (3 << ADC12B_ACR_GAIN_SHIFT)
-#define ADC12B_ACR_IBCTL_SHIFT (8) /* Bits 8-9: Bias Current Control */
-#define ADC12B_ACR_IBCTL_MASK (3 << ADC12B_ACR_IBCTL_SHIFT)
-#define ADC12B_ACR_DIFF (1 << 16) /* Bit 16: Differential Mode */
-#define ADC12B_ACR_OFFSET (1 << 17) /* Bit 17: Input OFFSET */
-
-/* ADC12B Extended Mode Register (ADC12B only) */
-
-#define ADC12B_EMR_OFFMODES (1 << 0) /* Bit 0: Off Mode if Sleep Bit (ADC12B_MR) = 1 */
-#define ADC12B_EMR_OFFMSTIME_SHIFT (16) /* Bits 16-23: Startup Time */
-#define ADC12B_EMR_OFFMSTIME_MASK (0xff << ADC12B_EMR_OFFMSTIME_SHIFT)
-
-/* ADC12B Status Register , ADC12B Interrupt Enable Register, ADC12B Interrupt
- * Disable Register, ADC12B Interrupt Mask Register, ADC(10B) Status Register,
- * ADC(10B) Interrupt Enable Register, ADC(10B) Interrupt Disable Register, and
- * ADC(10B) Interrupt Mask Register common bit-field definitions
- */
-
-#define ADC_INT_EOC(n) (1<<(n))
-#define ADC_INT_EOC0 (1 << 0) /* Bit 0: End of Conversion 0 */
-#define ADC_INT_EOC1 (1 << 1) /* Bit 1: End of Conversion 1 */
-#define ADC_INT_EOC2 (1 << 2) /* Bit 2: End of Conversion 2 */
-#define ADC_INT_EOC3 (1 << 3) /* Bit 3: End of Conversion 3 */
-#define ADC_INT_EOC4 (1 << 4) /* Bit 4: End of Conversion 4 */
-#define ADC_INT_EOC5 (1 << 5) /* Bit 5: End of Conversion 5 */
-#define ADC_INT_EOC6 (1 << 6) /* Bit 6: End of Conversion 6 */
-#define ADC_INT_EOC7 (1 << 7) /* Bit 0: End of Conversion 7 */
-#define ADC_INT_OVRE(n) (1<<((n)+8))
-#define ADC_INT_OVRE0 (1 << 8) /* Bit 8: Overrun Error 0 */
-#define ADC_INT_OVRE1 (1 << 9) /* Bit 9: Overrun Error 1 */
-#define ADC_INT_OVRE2 (1 << 10) /* Bit 10: Overrun Error 2 */
-#define ADC_INT_OVRE3 (1 << 11) /* Bit 11: Overrun Error 3 */
-#define ADC_INT_OVRE4 (1 << 12) /* Bit 12: Overrun Error 4 */
-#define ADC_INT_OVRE5 (1 << 13) /* Bit 13: Overrun Error 5 */
-#define ADC_INT_OVRE6 (1 << 14) /* Bit 14: Overrun Error 6 */
-#define ADC_INT_OVRE7 (1 << 15) /* Bit 15: Overrun Error 7 */
-#define ADC_INT_DRDY (1 << 16) /* Bit 16: Data Ready */
-#define ADC_INT_GOVRE (1 << 17) /* Bit 17: General Overrun Error */
-#define ADC_INT_ENDRX (1 << 18) /* Bit 18: End of RX Buffer */
-#define ADC_INT_RXBUFF (1 << 19) /* Bit 19: RX Buffer Full */
-
-/* ADC12B Last Converted Data Register */
-
-#define ADC12B_LCDR_DATA_SHIFT (0) /* Bits 0-11: Last Data Converted */
-#define ADC12B_LCDR_DATA_MASK (0xfff << ADC12B_LCDR_DATA_SHIFT)
-
-/* ADC(10B) Last Converted Data Register */
-
-#define ADC10B_LCDR_DATA_SHIFT (0) /* Bits 0-9: Last Data Converted */
-#define ADC10B_LCDR_DATA_MASK (0x1ff << ADC10B_LCDR_DATA_SHIFT)
-
-/* ADC12B Channel Data Register */
-
-#define ADC12B_CDR_DATA_SHIFT (0) /* Bits 0-11: Converted Data */
-#define ADC12B_CDR_DATA_MASK (0xfff << ADC12B_CDR_DATA_SHIFT)
-
-/* ADC(10B) Channel Data Register */
-
-#define ADC10B_CDR_DATA_SHIFT (0) /* Bits 0-9: Converted Data */
-#define ADC10B_CDR_DATA_MASK (0x1ff << ADC10B_CDR_DATA_SHIFT)
-
-/****************************************************************************************
- * Public Types
- ****************************************************************************************/
-
-/****************************************************************************************
- * Public Data
- ****************************************************************************************/
-
-/****************************************************************************************
- * Public Functions
- ****************************************************************************************/
-
-#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_ADC_H */
+/**************************************************************************************** + * arch/arm/src/sam3u/sam3u_adc.h + * + * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_ADC_H +#define __ARCH_ARM_SRC_SAM3U_SAM3U_ADC_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +#include <nuttx/config.h> + +#include "chip.h" +#include "sam3u_memorymap.h" + +/**************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************/ + +/* ADC register offsets ****************************************************************/ + +#define SAM3U_ADC_CR_OFFSET 0x00 /* Control Register (Both) */ +#define SAM3U_ADC_MR_OFFSET 0x04 /* Mode Register (Both) */ + /* 0x08: Reserved */ + /* 0x0c: Reserved */ +#define SAM3U_ADC_CHER_OFFSET 0x10 /* Channel Enable Register (Both) */ +#define SAM3U_ADC_CHDR_OFFSET 0x14 /* Channel Disable Register (Both) */ +#define SAM3U_ADC_CHSR_OFFSET 0x18 /* Channel Status Register (Both) */ +#define SAM3U_ADC_SR_OFFSET 0x1c /* Status Register (Both) */ +#define SAM3U_ADC_LCDR_OFFSET 0x20 /* Last Converted Data Register (Both) */ +#define SAM3U_ADC_IER_OFFSET 0x24 /* Interrupt Enable Register (Both) */ +#define SAM3U_ADC_IDR_OFFSET 0x28 /* Interrupt Disable Register (Both) */ +#define SAM3U_ADC_IMR_OFFSET 0x2c /* Interrupt Mask Register (Both) */ +#define SAM3U_ADC_CDR_OFFSET(n) (0x30+((n)<<2)) +#define SAM3U_ADC_CDR0_OFFSET 0x30 /* Channel Data Register 0 (Both) */ +#define SAM3U_ADC_CDR1_OFFSET 0x34 /* Channel Data Register 1 (Both) */ +#define SAM3U_ADC_CDR2_OFFSET 0x38 /* Channel Data Register 2 (Both) */ +#define SAM3U_ADC_CDR3_OFFSET 0x3c /* Channel Data Register 3 (Both) */ +#define SAM3U_ADC_CDR4_OFFSET 0x40 /* Channel Data Register 4 (Both) */ +#define SAM3U_ADC_CDR5_OFFSET 0x44 /* Channel Data Register 5 (Both) */ +#define SAM3U_ADC_CDR6_OFFSET 0x48 /* Channel Data Register 6 (Both) */ +#define SAM3U_ADC_CDR7_OFFSET 0x4c /* Channel Data Register 7 (Both) */ +#define SAM3U_ADC12B_ACR_OFFSET 0x64 /* Analog Control Register (ADC12B only) */ +#define SAM3U_ADC12B_EMR_OFFSET 0x68 /* Extended Mode Register (ADC12B only) */ + +/* ADC register adresses ***************************************************************/ + +#define SAM3U_ADC12B_CR (SAM3U_ADC12B_BASE+SAM3U_ADC_CR_OFFSET) +#define SAM3U_ADC12B_MR (SAM3U_ADC12B_BASE+SAM3U_ADC_MR_OFFSET) +#define SAM3U_ADC12B_CHER (SAM3U_ADC12B_BASE+SAM3U_ADC_CHER_OFFSET) +#define SAM3U_ADC12B_CHDR (SAM3U_ADC12B_BASE+SAM3U_ADC_CHDR_OFFSET) +#define SAM3U_ADC12B_CHSR (SAM3U_ADC12B_BASE+SAM3U_ADC_CHSR_OFFSET) +#define SAM3U_ADC12B_SR (SAM3U_ADC12B_BASE+SAM3U_ADC_SR_OFFSET) +#define SAM3U_ADC12B_LCDR_ (SAM3U_ADC12B_BASE+SAM3U_ADC_LCDR_OFFSET) +#define SAM3U_ADC12B_IER (SAM3U_ADC12B_BASE+SAM3U_ADC_IER_OFFSET) +#define SAM3U_ADC12B_IDR (SAM3U_ADC12B_BASE+SAM3U_ADC_IDR_OFFSET) +#define SAM3U_ADC12B_IMR (SAM3U_ADC12B_BASE+SAM3U_ADC_IMR_OFFSET) +#define SAM3U_ADC12B_CDR(n)) (SAM3U_ADC12B_BASE+SAM3U_ADC_CDR_OFFSET(n)) +#define SAM3U_ADC12B_CDR0 (SAM3U_ADC12B_BASE+SAM3U_ADC_CDR0_OFFSET) +#define SAM3U_ADC12B_CDR1 (SAM3U_ADC12B_BASE+SAM3U_ADC_CDR1_OFFSET) +#define SAM3U_ADC12B_CDR2 (SAM3U_ADC12B_BASE+SAM3U_ADC_CDR2_OFFSET) +#define SAM3U_ADC12B_CDR3 (SAM3U_ADC12B_BASE+SAM3U_ADC_CDR3_OFFSET) +#define SAM3U_ADC12B_CDR4 (SAM3U_ADC12B_BASE+SAM3U_ADC_CDR4_OFFSET) +#define SAM3U_ADC12B_CDR5 (SAM3U_ADC12B_BASE+SAM3U_ADC_CDR5_OFFSET) +#define SAM3U_ADC12B_CDR6 (SAM3U_ADC12B_BASE+SAM3U_ADC_CDR6_OFFSET) +#define SAM3U_ADC12B_CDR7 (SAM3U_ADC12B_BASE+SAM3U_ADC_CDR7_OFFSET) +#define SAM3U_ADC12B_ACR (SAM3U_ADC12B_BASE+SAM3U_ADC12B_ACR_OFFSET) +#define SAM3U_ADC12B_EMR (SAM3U_ADC12B_BASE+SAM3U_ADC12B_EMR_OFFSET) + +#define SAM3U_ADC_CR (SAM3U_ADC_BASE+SAM3U_ADC_CR_OFFSET) +#define SAM3U_ADC_MR (SAM3U_ADC_BASE+SAM3U_ADC_MR_OFFSET) +#define SAM3U_ADC_CHER (SAM3U_ADC_BASE+SAM3U_ADC_CHER_OFFSET) +#define SAM3U_ADC_CHDR (SAM3U_ADC_BASE+SAM3U_ADC_CHDR_OFFSET) +#define SAM3U_ADC_CHSR (SAM3U_ADC_BASE+SAM3U_ADC_CHSR_OFFSET) +#define SAM3U_ADC_SR (SAM3U_ADC_BASE+SAM3U_ADC_SR_OFFSET) +#define SAM3U_ADC_LCDR (SAM3U_ADC_BASE+SAM3U_ADC_LCDR_OFFSET) +#define SAM3U_ADC_IER (SAM3U_ADC_BASE+SAM3U_ADC_IER_OFFSET) +#define SAM3U_ADC_IDR (SAM3U_ADC_BASE+SAM3U_ADC_IDR_OFFSET) +#define SAM3U_ADC_IMR (SAM3U_ADC_BASE+SAM3U_ADC_IMR_OFFSET) +#define SAM3U_ADC_CDR(n)) (SAM3U_ADC_BASE+SAM3U_ADC_CDR_OFFSET(n)) +#define SAM3U_ADC_CDR0 (SAM3U_ADC_BASE+SAM3U_ADC_CDR0_OFFSET) +#define SAM3U_ADC_CDR1 (SAM3U_ADC_BASE+SAM3U_ADC_CDR1_OFFSET) +#define SAM3U_ADC_CDR2 (SAM3U_ADC_BASE+SAM3U_ADC_CDR2_OFFSET) +#define SAM3U_ADC_CDR3 (SAM3U_ADC_BASE+SAM3U_ADC_CDR3_OFFSET) +#define SAM3U_ADC_CDR4 (SAM3U_ADC_BASE+SAM3U_ADC_CDR4_OFFSET) +#define SAM3U_ADC_CDR5 (SAM3U_ADC_BASE+SAM3U_ADC_CDR5_OFFSET) +#define SAM3U_ADC_CDR6 (SAM3U_ADC_BASE+SAM3U_ADC_CDR6_OFFSET) +#define SAM3U_ADC_CDR7 (SAM3U_ADC_BASE+SAM3U_ADC_CDR7_OFFSET) + +/* ADC register bit definitions ********************************************************/ + +/* ADC12B Control Register and ADC(10B) Control Register common bit-field definitions */ + +#define ADC_CR_SWRST (1 << 0) /* Bit 0: Software Reset */ +#define ADC_CR_START (1 << 1) /* Bit 1: Start Conversion */ + +/* ADC12B Mode Register and ADC(10B) Mode Register common bit-field definitions */ + +#define ADC_MR_TRGEN (1 << 0) /* Bit 0: Trigger Enable */ +#define ADC_MR_TRGSEL_SHIFT (1) /* Bits 1-3: Trigger Selection */ +#define ADC_MR_TRGSEL_MASK (7 << ADC_MR_TRGSEL_SHIFT) +#define ADC_MR_LOWRES (1 << 4) /* Bit 4: Resolution */ +#define ADC_MR_SLEEP (1 << 5) /* Bit 5: Sleep Mode */ +#define ADC_MR_PRESCAL_SHIFT (8) /* Bits 8-15: Prescaler Rate Selection */ +#define ADC_MR_PRESCAL_MASK (0xff << ADC_MR_PRESCAL_SHIFT) +#define ADB12B_MRSTARTUP_SHIFT (16) /* Bits 16-23: Start Up Time (ADC12B) */ +#define ADB12B_MRSTARTUP_MASK (0xff << ADB12B_MRSTARTUP_SHIFT +#define ADB10B_MRSTARTUP_SHIFT (16) /* Bits 16-22: Start Up Time (ADC10B) */ +#define ADB10B_MRSTARTUP_MASK (0x7f << ADB10B_MRSTARTUP_SHIFT) +#define ADC_MR_SHTIM_SHIFT (24) /* Bits 24-27: Sample & Hold Time */ +#define ADC_MR_SHTIM_MASK (15 << ADC_MR_SHTIM_SHIFT) + +/* ADC12B Channel Enable Register, ADC12B Channel Disable Register, ADC12B Channel + * Status Register, ADC(10B) Channel Enable Register, ADC(10B) Channel Disable Register, + * and ADC(10B) Channel Status Register common bit-field definitions + */ + +#define ADC_CH(n) (1 << (n)) +#define ADC_CH0 (1 << 0) /* Bit 0: Channel x Enable */ +#define ADC_CH1 (1 << 1) /* Bit 1: Channel x Enable */ +#define ADC_CH2 (1 << 2) /* Bit 2: Channel x Enable */ +#define ADC_CH3 (1 << 3) /* Bit 3: Channel x Enable */ +#define ADC_CH4 (1 << 4) /* Bit 4: Channel x Enable */ +#define ADC_CH5 (1 << 5) /* Bit 5: Channel x Enable */ +#define ADC_CH6 (1 << 6) /* Bit 6: Channel x Enable */ +#define ADC_CH7 (1 << 7) /* Bit 7: Channel x Enable */ + +/* ADC12B Analog Control Register (ADC12B only) */ + +#define ADC12B_ACR_GAIN_SHIFT (0) /* Bits 0-1: Input Gain */ +#define ADC12B_ACR_GAIN_MASK (3 << ADC12B_ACR_GAIN_SHIFT) +#define ADC12B_ACR_IBCTL_SHIFT (8) /* Bits 8-9: Bias Current Control */ +#define ADC12B_ACR_IBCTL_MASK (3 << ADC12B_ACR_IBCTL_SHIFT) +#define ADC12B_ACR_DIFF (1 << 16) /* Bit 16: Differential Mode */ +#define ADC12B_ACR_OFFSET (1 << 17) /* Bit 17: Input OFFSET */ + +/* ADC12B Extended Mode Register (ADC12B only) */ + +#define ADC12B_EMR_OFFMODES (1 << 0) /* Bit 0: Off Mode if Sleep Bit (ADC12B_MR) = 1 */ +#define ADC12B_EMR_OFFMSTIME_SHIFT (16) /* Bits 16-23: Startup Time */ +#define ADC12B_EMR_OFFMSTIME_MASK (0xff << ADC12B_EMR_OFFMSTIME_SHIFT) + +/* ADC12B Status Register , ADC12B Interrupt Enable Register, ADC12B Interrupt + * Disable Register, ADC12B Interrupt Mask Register, ADC(10B) Status Register, + * ADC(10B) Interrupt Enable Register, ADC(10B) Interrupt Disable Register, and + * ADC(10B) Interrupt Mask Register common bit-field definitions + */ + +#define ADC_INT_EOC(n) (1<<(n)) +#define ADC_INT_EOC0 (1 << 0) /* Bit 0: End of Conversion 0 */ +#define ADC_INT_EOC1 (1 << 1) /* Bit 1: End of Conversion 1 */ +#define ADC_INT_EOC2 (1 << 2) /* Bit 2: End of Conversion 2 */ +#define ADC_INT_EOC3 (1 << 3) /* Bit 3: End of Conversion 3 */ +#define ADC_INT_EOC4 (1 << 4) /* Bit 4: End of Conversion 4 */ +#define ADC_INT_EOC5 (1 << 5) /* Bit 5: End of Conversion 5 */ +#define ADC_INT_EOC6 (1 << 6) /* Bit 6: End of Conversion 6 */ +#define ADC_INT_EOC7 (1 << 7) /* Bit 0: End of Conversion 7 */ +#define ADC_INT_OVRE(n) (1<<((n)+8)) +#define ADC_INT_OVRE0 (1 << 8) /* Bit 8: Overrun Error 0 */ +#define ADC_INT_OVRE1 (1 << 9) /* Bit 9: Overrun Error 1 */ +#define ADC_INT_OVRE2 (1 << 10) /* Bit 10: Overrun Error 2 */ +#define ADC_INT_OVRE3 (1 << 11) /* Bit 11: Overrun Error 3 */ +#define ADC_INT_OVRE4 (1 << 12) /* Bit 12: Overrun Error 4 */ +#define ADC_INT_OVRE5 (1 << 13) /* Bit 13: Overrun Error 5 */ +#define ADC_INT_OVRE6 (1 << 14) /* Bit 14: Overrun Error 6 */ +#define ADC_INT_OVRE7 (1 << 15) /* Bit 15: Overrun Error 7 */ +#define ADC_INT_DRDY (1 << 16) /* Bit 16: Data Ready */ +#define ADC_INT_GOVRE (1 << 17) /* Bit 17: General Overrun Error */ +#define ADC_INT_ENDRX (1 << 18) /* Bit 18: End of RX Buffer */ +#define ADC_INT_RXBUFF (1 << 19) /* Bit 19: RX Buffer Full */ + +/* ADC12B Last Converted Data Register */ + +#define ADC12B_LCDR_DATA_SHIFT (0) /* Bits 0-11: Last Data Converted */ +#define ADC12B_LCDR_DATA_MASK (0xfff << ADC12B_LCDR_DATA_SHIFT) + +/* ADC(10B) Last Converted Data Register */ + +#define ADC10B_LCDR_DATA_SHIFT (0) /* Bits 0-9: Last Data Converted */ +#define ADC10B_LCDR_DATA_MASK (0x1ff << ADC10B_LCDR_DATA_SHIFT) + +/* ADC12B Channel Data Register */ + +#define ADC12B_CDR_DATA_SHIFT (0) /* Bits 0-11: Converted Data */ +#define ADC12B_CDR_DATA_MASK (0xfff << ADC12B_CDR_DATA_SHIFT) + +/* ADC(10B) Channel Data Register */ + +#define ADC10B_CDR_DATA_SHIFT (0) /* Bits 0-9: Converted Data */ +#define ADC10B_CDR_DATA_MASK (0x1ff << ADC10B_CDR_DATA_SHIFT) + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +/**************************************************************************************** + * Public Data + ****************************************************************************************/ + +/**************************************************************************************** + * Public Functions + ****************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_ADC_H */ diff --git a/nuttx/arch/arm/src/sam3u/sam3u_allocateheap.c b/nuttx/arch/arm/src/sam3u/sam3u_allocateheap.c index f266fd754..1f4b5fdd2 100644 --- a/nuttx/arch/arm/src/sam3u/sam3u_allocateheap.c +++ b/nuttx/arch/arm/src/sam3u/sam3u_allocateheap.c @@ -2,7 +2,7 @@ * arch/arm/src/common/sam3u_allocateheap.c * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/sam3u/sam3u_chipid.h b/nuttx/arch/arm/src/sam3u/sam3u_chipid.h index 9ef007d27..03071d77a 100644 --- a/nuttx/arch/arm/src/sam3u/sam3u_chipid.h +++ b/nuttx/arch/arm/src/sam3u/sam3u_chipid.h @@ -1,167 +1,167 @@ -/****************************************************************************************
- * arch/arm/src/sam3u/sam3u_chipid.h
- *
- * Copyright (C) 2009 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_CHIPID_H
-#define __ARCH_ARM_SRC_SAM3U_SAM3U_CHIPID_H
-
-/****************************************************************************************
- * Included Files
- ****************************************************************************************/
-
-#include <nuttx/config.h>
-
-#include "chip.h"
-#include "sam3u_memorymap.h"
-
-/****************************************************************************************
- * Pre-processor Definitions
- ****************************************************************************************/
-
-/* CHIPID register offsets **************************************************************/
-
-#define SAM3U_CHIPID_CIDR 0x00 /* Chip ID Register */
-#define SAM3U_CHIPID_EXID 0x04 /* Chip ID Extension Register */
-
-/* CHIPID register adresses *************************************************************/
-
-#define SAM3U_CHIPID_CIDR (SAM3U_CHIPID_BASE+SAM3U_CHIPID_CIDR)
-#define SAM3U_CHIPID_EXID (SAM3U_CHIPID_BASE+SAM3U_CHIPID_EXID)
-
-/* CHIPID register bit definitions ******************************************************/
-
-#define CHIPID_CIDR_VERSION_SHIFT (0) /* Bits 0-4: Version of the Device */
-#define CHIPID_CIDR_VERSION_MASK (0x1f << CHIPID_CIDR_VERSION_SHIFT)
-#define CHIPID_CIDR_EPROC_SHIFT (5) /* Bits 5-7: Embedded Processor */
-#define CHIPID_CIDR_EPROC_MASK (7 << CHIPID_CIDR_EPROC_SHIFT)
-# define CHIPID_CIDR_EPROC_ARM946ES (1 << CHIPID_CIDR_EPROC_SHIFT) /* ARM946E-S */
-# define CHIPID_CIDR_EPROC_ARM7TDMI (2 << CHIPID_CIDR_EPROC_SHIFT) /* ARM7TDMI */
-# define CHIPID_CIDR_EPROC_CORTEXM3 (3 << CHIPID_CIDR_EPROC_SHIFT) /* Cortex-M3 */
-# define CHIPID_CIDR_EPROC_ARM920T (4 << CHIPID_CIDR_EPROC_SHIFT) /* ARM920T */
-# define CHIPID_CIDR_EPROC_ARM926EJS (5 << CHIPID_CIDR_EPROC_SHIFT) /* ARM926EJ-S */
-#define CHIPID_CIDR_NVPSIZ_SHIFT (8) /* Bits 8-11: Nonvolatile Program Memory Size */
-#define CHIPID_CIDR_NVPSIZ_MASK (15 << CHIPID_CIDR_NVPSIZ_SHIFT)
-# define CHIPID_CIDR_NVPSIZ_NONE (0 << CHIPID_CIDR_NVPSIZ_SHIFT) /* None */
-# define CHIPID_CIDR_NVPSIZ_8KB (1 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 8K bytes */
-# define CHIPID_CIDR_NVPSIZ_16KB (2 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 16K bytes */
-# define CHIPID_CIDR_NVPSIZ_32KB (3 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 32K bytes */
-# define CHIPID_CIDR_NVPSIZ_64KB (5 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 64K bytes */
-# define CHIPID_CIDR_NVPSIZ_128KB (7 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 128K bytes */
-# define CHIPID_CIDR_NVPSIZ_256KB (9 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 256K bytes */
-# define CHIPID_CIDR_NVPSIZ_512KB (10 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 512K bytes */
-# define CHIPID_CIDR_NVPSIZ_1MB (12 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 1024K bytes */
-# define CHIPID_CIDR_NVPSIZ_2MB (14 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 2048K bytes */
-#define CHIPID_CIDR_NVPSIZ2_SHIFT (12) /* Bits 12-15: Nonvolatile Program Memory Size */
-#define CHIPID_CIDR_NVPSIZ2_MASK (15 << CHIPID_CIDR_NVPSIZ_SHIFT)
-# define CHIPID_CIDR_NVPSIZ2_NONE (0 << CHIPID_CIDR_NVPSIZ_SHIFT) /* None */
-# define CHIPID_CIDR_NVPSIZ2_8KB (1 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 8K bytes */
-# define CHIPID_CIDR_NVPSIZ2_16KB (2 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 16K bytes */
-# define CHIPID_CIDR_NVPSIZ2_32KB (3 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 32K bytes */
-# define CHIPID_CIDR_NVPSIZ2_64KB (5 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 64K bytes */
-# define CHIPID_CIDR_NVPSIZ2_128KB (7 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 128K bytes */
-# define CHIPID_CIDR_NVPSIZ2_256KB (9 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 256K bytes */
-# define CHIPID_CIDR_NVPSIZ2_512KB (10 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 512K bytes */
-# define CHIPID_CIDR_NVPSIZ2_1MB (12 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 1024K bytes */
-# define CHIPID_CIDR_NVPSIZ2_2MB (14 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 2048K bytes */
-#define CHIPID_CIDR_SRAMSIZ_SHIFT (16) /* Bits 16-19: Internal SRAM Size */
-#define CHIPID_CIDR_SRAMSIZ_MASK (15 << CHIPID_CIDR_SRAMSIZ_SHIFT)
-# define CHIPID_CIDR_SRAMSIZ_48KB (0 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 48K bytes */
-# define CHIPID_CIDR_SRAMSIZ_1KB (1 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 1K bytes */
-# define CHIPID_CIDR_SRAMSIZ_2KB (2 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 2K bytes */
-# define CHIPID_CIDR_SRAMSIZ_6KB (3 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 6K bytes */
-# define CHIPID_CIDR_SRAMSIZ_112KB (4 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 112K bytes */
-# define CHIPID_CIDR_SRAMSIZ_4KB (5 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 4K bytes */
-# define CHIPID_CIDR_SRAMSIZ_80KB (6 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 80K bytes */
-# define CHIPID_CIDR_SRAMSIZ_160KB (7 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 160K bytes */
-# define CHIPID_CIDR_SRAMSIZ_8KB (8 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 8K bytes */
-# define CHIPID_CIDR_SRAMSIZ_16KB (9 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 16K bytes */
-# define CHIPID_CIDR_SRAMSIZ_32KB (10 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 32K bytes */
-# define CHIPID_CIDR_SRAMSIZ_64KB (11 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 64K bytes */
-# define CHIPID_CIDR_SRAMSIZ_128KB (12 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 128K bytes */
-# define CHIPID_CIDR_SRAMSIZ_256KB (13 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 256K bytes */
-# define CHIPID_CIDR_SRAMSIZ_96KB (14 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 96K bytes */
-# define CHIPID_CIDR_SRAMSIZ_512KB (15 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 512K bytes */
-#define CHIPID_CIDR_ARCH_SHIFT (20) /* Bits 20-27: Architecture Identifier */
-#define CHIPID_CIDR_ARCH_MASK (0xff << CHIPID_CIDR_ARCH_SHIFT)
-# define CHIPID_CIDR_ARCH_AT91SAM9XX (0x19 << CHIPID_CIDR_ARCH_SHIFT) /* AT91SAM9xx Series */
-# define CHIPID_CIDR_ARCH_AT91SAM9XEXX (0x29 << CHIPID_CIDR_ARCH_SHIFT) /* AT91SAM9XExx Series */
-# define CHIPID_CIDR_ARCH_AT91X34 (0x34 << CHIPID_CIDR_ARCH_SHIFT) /* AT91x34 Series */
-# define CHIPID_CIDR_ARCH_CAP7 (0x37 << CHIPID_CIDR_ARCH_SHIFT) /* CAP7 Series */
-# define CHIPID_CIDR_ARCH_CAP9 (0x39 << CHIPID_CIDR_ARCH_SHIFT) /* CAP9 Series */
-# define CHIPID_CIDR_ARCH_CAP11 (0x3b << CHIPID_CIDR_ARCH_SHIFT) /* CAP11 Series */
-# define CHIPID_CIDR_ARCH_AT91X40 (0x40 << CHIPID_CIDR_ARCH_SHIFT) /* AT91x40 Series */
-# define CHIPID_CIDR_ARCH_AT91X42 (0x42 << CHIPID_CIDR_ARCH_SHIFT) /* AT91x42 Series */
-# define CHIPID_CIDR_ARCH_AT91X55 (0x55 << CHIPID_CIDR_ARCH_SHIFT) /* AT91x55 Series */
-# define CHIPID_CIDR_ARCH_AT91SAM7AXX (0x60 << CHIPID_CIDR_ARCH_SHIFT) /* AT91SAM7Axx Series */
-# define CHIPID_CIDR_ARCH_AT91SAM7AQXX (0x61 << CHIPID_CIDR_ARCH_SHIFT) /* AT91SAM7AQxx Series */
-# define CHIPID_CIDR_ARCH_AT91X63 (0x63 << CHIPID_CIDR_ARCH_SHIFT) /* AT91x63 Series */
-# define CHIPID_CIDR_ARCH_AT91SAM7SXX (0x70 << CHIPID_CIDR_ARCH_SHIFT) /* AT91SAM7Sxx Series */
-# define CHIPID_CIDR_ARCH_AT91SAM7XCXX (0x71 << CHIPID_CIDR_ARCH_SHIFT) /* AT91SAM7XCxx Series */
-# define CHIPID_CIDR_ARCH_AT91SAM7SEXX (0x72 << CHIPID_CIDR_ARCH_SHIFT) /* AT91SAM7SExx Series */
-# define CHIPID_CIDR_ARCH_AT91SAM7LXX (0x73 << CHIPID_CIDR_ARCH_SHIFT) /* AT91SAM7Lxx Series */
-# define CHIPID_CIDR_ARCH_AT91SAM7XXX (0x75 << CHIPID_CIDR_ARCH_SHIFT) /* AT91SAM7Xxx Series */
-# define CHIPID_CIDR_ARCH_AT91SAM7SLXX (0x76 << CHIPID_CIDR_ARCH_SHIFT) /* AT91SAM7SLxx Series */
-# define CHIPID_CIDR_ARCH_SAM3UXC (0x80 << CHIPID_CIDR_ARCH_SHIFT) /* SAM3UxC Series (100-pin version) */
-# define CHIPID_CIDR_ARCH_SAM3UXE (0x81 << CHIPID_CIDR_ARCH_SHIFT) /* SAM3UxE Series (144-pin version) */
-# define CHIPID_CIDR_ARCH_SAM3AXC (0x83 << CHIPID_CIDR_ARCH_SHIFT) /* SAM3AxC Series (100-pin version) */
-# define CHIPID_CIDR_ARCH_SAM3XXC (0x84 << CHIPID_CIDR_ARCH_SHIFT) /* SAM3XxC Series (100-pin version) */
-# define CHIPID_CIDR_ARCH_SAM3XXE (0x85 << CHIPID_CIDR_ARCH_SHIFT) /* SAM3XxE Series (144-pin version) */
-# define CHIPID_CIDR_ARCH_SAM3XXG (0x86 << CHIPID_CIDR_ARCH_SHIFT) /* SAM3XxG Series (208/217-pin version) */
-# define CHIPID_CIDR_ARCH_SAM3SXA (0x88 << CHIPID_CIDR_ARCH_SHIFT) /* SAM3SxA Series (48-pin version) */
-# define CHIPID_CIDR_ARCH_SAM3SXB (0x89 << CHIPID_CIDR_ARCH_SHIFT) /* SAM3SxB Series (64-pin version) */
-# define CHIPID_CIDR_ARCH_SAM3SXC (0x8a << CHIPID_CIDR_ARCH_SHIFT) /* SAM3SxC Series (100-pin version) */
-# define CHIPID_CIDR_ARCH_AT91X92 (0x92 << CHIPID_CIDR_ARCH_SHIFT) /* AT91x92 Series */
-# define CHIPID_CIDR_ARCH_AT75CXX (0xf0 << CHIPID_CIDR_ARCH_SHIFT) /* AT75Cxx Series */
-#define CHIPID_CIDR_NVPTYP_SHIFT (28) /* Bits 28-30: Nonvolatile Program Memory Type */
-#define CHIPID_CIDR_NVPTYP_MASK (7 << CHIPID_CIDR_NVPTYP_SHIFT)
-# define CHIPID_CIDR_NVPTYP ROM (0 << CHIPID_CIDR_NVPTYP_SHIFT) /* ROM */
-# define CHIPID_CIDR_NVPTYP FLASH (1 << CHIPID_CIDR_NVPTYP_SHIFT) /* ROMless or on-chip Flash */
-# define CHIPID_CIDR_NVPTYP SRAM (4 << CHIPID_CIDR_NVPTYP_SHIFT) /* SRAM emulating ROM */
-# define CHIPID_CIDR_NVPTYP EFLASH (2 << CHIPID_CIDR_NVPTYP_SHIFT) /* Embedded Flash Memory */
-# define CHIPID_CIDR_NVPTYP REFLASH (3 << CHIPID_CIDR_NVPTYP_SHIFT) /* ROM and Embedded Flash Memory */
-#define CHIPID_CIDR_EXT (1 << 31) /* Bit 31: Extension Flag */
-
-/****************************************************************************************
- * Public Types
- ****************************************************************************************/
-
-/****************************************************************************************
- * Public Data
- ****************************************************************************************/
-
-/****************************************************************************************
- * Public Functions
- ****************************************************************************************/
-
-#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_CHIPID_H */
+/**************************************************************************************** + * arch/arm/src/sam3u/sam3u_chipid.h + * + * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_CHIPID_H +#define __ARCH_ARM_SRC_SAM3U_SAM3U_CHIPID_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +#include <nuttx/config.h> + +#include "chip.h" +#include "sam3u_memorymap.h" + +/**************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************/ + +/* CHIPID register offsets **************************************************************/ + +#define SAM3U_CHIPID_CIDR 0x00 /* Chip ID Register */ +#define SAM3U_CHIPID_EXID 0x04 /* Chip ID Extension Register */ + +/* CHIPID register adresses *************************************************************/ + +#define SAM3U_CHIPID_CIDR (SAM3U_CHIPID_BASE+SAM3U_CHIPID_CIDR) +#define SAM3U_CHIPID_EXID (SAM3U_CHIPID_BASE+SAM3U_CHIPID_EXID) + +/* CHIPID register bit definitions ******************************************************/ + +#define CHIPID_CIDR_VERSION_SHIFT (0) /* Bits 0-4: Version of the Device */ +#define CHIPID_CIDR_VERSION_MASK (0x1f << CHIPID_CIDR_VERSION_SHIFT) +#define CHIPID_CIDR_EPROC_SHIFT (5) /* Bits 5-7: Embedded Processor */ +#define CHIPID_CIDR_EPROC_MASK (7 << CHIPID_CIDR_EPROC_SHIFT) +# define CHIPID_CIDR_EPROC_ARM946ES (1 << CHIPID_CIDR_EPROC_SHIFT) /* ARM946E-S */ +# define CHIPID_CIDR_EPROC_ARM7TDMI (2 << CHIPID_CIDR_EPROC_SHIFT) /* ARM7TDMI */ +# define CHIPID_CIDR_EPROC_CORTEXM3 (3 << CHIPID_CIDR_EPROC_SHIFT) /* Cortex-M3 */ +# define CHIPID_CIDR_EPROC_ARM920T (4 << CHIPID_CIDR_EPROC_SHIFT) /* ARM920T */ +# define CHIPID_CIDR_EPROC_ARM926EJS (5 << CHIPID_CIDR_EPROC_SHIFT) /* ARM926EJ-S */ +#define CHIPID_CIDR_NVPSIZ_SHIFT (8) /* Bits 8-11: Nonvolatile Program Memory Size */ +#define CHIPID_CIDR_NVPSIZ_MASK (15 << CHIPID_CIDR_NVPSIZ_SHIFT) +# define CHIPID_CIDR_NVPSIZ_NONE (0 << CHIPID_CIDR_NVPSIZ_SHIFT) /* None */ +# define CHIPID_CIDR_NVPSIZ_8KB (1 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 8K bytes */ +# define CHIPID_CIDR_NVPSIZ_16KB (2 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 16K bytes */ +# define CHIPID_CIDR_NVPSIZ_32KB (3 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 32K bytes */ +# define CHIPID_CIDR_NVPSIZ_64KB (5 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 64K bytes */ +# define CHIPID_CIDR_NVPSIZ_128KB (7 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 128K bytes */ +# define CHIPID_CIDR_NVPSIZ_256KB (9 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 256K bytes */ +# define CHIPID_CIDR_NVPSIZ_512KB (10 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 512K bytes */ +# define CHIPID_CIDR_NVPSIZ_1MB (12 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 1024K bytes */ +# define CHIPID_CIDR_NVPSIZ_2MB (14 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 2048K bytes */ +#define CHIPID_CIDR_NVPSIZ2_SHIFT (12) /* Bits 12-15: Nonvolatile Program Memory Size */ +#define CHIPID_CIDR_NVPSIZ2_MASK (15 << CHIPID_CIDR_NVPSIZ_SHIFT) +# define CHIPID_CIDR_NVPSIZ2_NONE (0 << CHIPID_CIDR_NVPSIZ_SHIFT) /* None */ +# define CHIPID_CIDR_NVPSIZ2_8KB (1 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 8K bytes */ +# define CHIPID_CIDR_NVPSIZ2_16KB (2 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 16K bytes */ +# define CHIPID_CIDR_NVPSIZ2_32KB (3 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 32K bytes */ +# define CHIPID_CIDR_NVPSIZ2_64KB (5 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 64K bytes */ +# define CHIPID_CIDR_NVPSIZ2_128KB (7 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 128K bytes */ +# define CHIPID_CIDR_NVPSIZ2_256KB (9 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 256K bytes */ +# define CHIPID_CIDR_NVPSIZ2_512KB (10 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 512K bytes */ +# define CHIPID_CIDR_NVPSIZ2_1MB (12 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 1024K bytes */ +# define CHIPID_CIDR_NVPSIZ2_2MB (14 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 2048K bytes */ +#define CHIPID_CIDR_SRAMSIZ_SHIFT (16) /* Bits 16-19: Internal SRAM Size */ +#define CHIPID_CIDR_SRAMSIZ_MASK (15 << CHIPID_CIDR_SRAMSIZ_SHIFT) +# define CHIPID_CIDR_SRAMSIZ_48KB (0 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 48K bytes */ +# define CHIPID_CIDR_SRAMSIZ_1KB (1 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 1K bytes */ +# define CHIPID_CIDR_SRAMSIZ_2KB (2 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 2K bytes */ +# define CHIPID_CIDR_SRAMSIZ_6KB (3 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 6K bytes */ +# define CHIPID_CIDR_SRAMSIZ_112KB (4 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 112K bytes */ +# define CHIPID_CIDR_SRAMSIZ_4KB (5 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 4K bytes */ +# define CHIPID_CIDR_SRAMSIZ_80KB (6 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 80K bytes */ +# define CHIPID_CIDR_SRAMSIZ_160KB (7 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 160K bytes */ +# define CHIPID_CIDR_SRAMSIZ_8KB (8 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 8K bytes */ +# define CHIPID_CIDR_SRAMSIZ_16KB (9 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 16K bytes */ +# define CHIPID_CIDR_SRAMSIZ_32KB (10 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 32K bytes */ +# define CHIPID_CIDR_SRAMSIZ_64KB (11 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 64K bytes */ +# define CHIPID_CIDR_SRAMSIZ_128KB (12 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 128K bytes */ +# define CHIPID_CIDR_SRAMSIZ_256KB (13 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 256K bytes */ +# define CHIPID_CIDR_SRAMSIZ_96KB (14 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 96K bytes */ +# define CHIPID_CIDR_SRAMSIZ_512KB (15 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 512K bytes */ +#define CHIPID_CIDR_ARCH_SHIFT (20) /* Bits 20-27: Architecture Identifier */ +#define CHIPID_CIDR_ARCH_MASK (0xff << CHIPID_CIDR_ARCH_SHIFT) +# define CHIPID_CIDR_ARCH_AT91SAM9XX (0x19 << CHIPID_CIDR_ARCH_SHIFT) /* AT91SAM9xx Series */ +# define CHIPID_CIDR_ARCH_AT91SAM9XEXX (0x29 << CHIPID_CIDR_ARCH_SHIFT) /* AT91SAM9XExx Series */ +# define CHIPID_CIDR_ARCH_AT91X34 (0x34 << CHIPID_CIDR_ARCH_SHIFT) /* AT91x34 Series */ +# define CHIPID_CIDR_ARCH_CAP7 (0x37 << CHIPID_CIDR_ARCH_SHIFT) /* CAP7 Series */ +# define CHIPID_CIDR_ARCH_CAP9 (0x39 << CHIPID_CIDR_ARCH_SHIFT) /* CAP9 Series */ +# define CHIPID_CIDR_ARCH_CAP11 (0x3b << CHIPID_CIDR_ARCH_SHIFT) /* CAP11 Series */ +# define CHIPID_CIDR_ARCH_AT91X40 (0x40 << CHIPID_CIDR_ARCH_SHIFT) /* AT91x40 Series */ +# define CHIPID_CIDR_ARCH_AT91X42 (0x42 << CHIPID_CIDR_ARCH_SHIFT) /* AT91x42 Series */ +# define CHIPID_CIDR_ARCH_AT91X55 (0x55 << CHIPID_CIDR_ARCH_SHIFT) /* AT91x55 Series */ +# define CHIPID_CIDR_ARCH_AT91SAM7AXX (0x60 << CHIPID_CIDR_ARCH_SHIFT) /* AT91SAM7Axx Series */ +# define CHIPID_CIDR_ARCH_AT91SAM7AQXX (0x61 << CHIPID_CIDR_ARCH_SHIFT) /* AT91SAM7AQxx Series */ +# define CHIPID_CIDR_ARCH_AT91X63 (0x63 << CHIPID_CIDR_ARCH_SHIFT) /* AT91x63 Series */ +# define CHIPID_CIDR_ARCH_AT91SAM7SXX (0x70 << CHIPID_CIDR_ARCH_SHIFT) /* AT91SAM7Sxx Series */ +# define CHIPID_CIDR_ARCH_AT91SAM7XCXX (0x71 << CHIPID_CIDR_ARCH_SHIFT) /* AT91SAM7XCxx Series */ +# define CHIPID_CIDR_ARCH_AT91SAM7SEXX (0x72 << CHIPID_CIDR_ARCH_SHIFT) /* AT91SAM7SExx Series */ +# define CHIPID_CIDR_ARCH_AT91SAM7LXX (0x73 << CHIPID_CIDR_ARCH_SHIFT) /* AT91SAM7Lxx Series */ +# define CHIPID_CIDR_ARCH_AT91SAM7XXX (0x75 << CHIPID_CIDR_ARCH_SHIFT) /* AT91SAM7Xxx Series */ +# define CHIPID_CIDR_ARCH_AT91SAM7SLXX (0x76 << CHIPID_CIDR_ARCH_SHIFT) /* AT91SAM7SLxx Series */ +# define CHIPID_CIDR_ARCH_SAM3UXC (0x80 << CHIPID_CIDR_ARCH_SHIFT) /* SAM3UxC Series (100-pin version) */ +# define CHIPID_CIDR_ARCH_SAM3UXE (0x81 << CHIPID_CIDR_ARCH_SHIFT) /* SAM3UxE Series (144-pin version) */ +# define CHIPID_CIDR_ARCH_SAM3AXC (0x83 << CHIPID_CIDR_ARCH_SHIFT) /* SAM3AxC Series (100-pin version) */ +# define CHIPID_CIDR_ARCH_SAM3XXC (0x84 << CHIPID_CIDR_ARCH_SHIFT) /* SAM3XxC Series (100-pin version) */ +# define CHIPID_CIDR_ARCH_SAM3XXE (0x85 << CHIPID_CIDR_ARCH_SHIFT) /* SAM3XxE Series (144-pin version) */ +# define CHIPID_CIDR_ARCH_SAM3XXG (0x86 << CHIPID_CIDR_ARCH_SHIFT) /* SAM3XxG Series (208/217-pin version) */ +# define CHIPID_CIDR_ARCH_SAM3SXA (0x88 << CHIPID_CIDR_ARCH_SHIFT) /* SAM3SxA Series (48-pin version) */ +# define CHIPID_CIDR_ARCH_SAM3SXB (0x89 << CHIPID_CIDR_ARCH_SHIFT) /* SAM3SxB Series (64-pin version) */ +# define CHIPID_CIDR_ARCH_SAM3SXC (0x8a << CHIPID_CIDR_ARCH_SHIFT) /* SAM3SxC Series (100-pin version) */ +# define CHIPID_CIDR_ARCH_AT91X92 (0x92 << CHIPID_CIDR_ARCH_SHIFT) /* AT91x92 Series */ +# define CHIPID_CIDR_ARCH_AT75CXX (0xf0 << CHIPID_CIDR_ARCH_SHIFT) /* AT75Cxx Series */ +#define CHIPID_CIDR_NVPTYP_SHIFT (28) /* Bits 28-30: Nonvolatile Program Memory Type */ +#define CHIPID_CIDR_NVPTYP_MASK (7 << CHIPID_CIDR_NVPTYP_SHIFT) +# define CHIPID_CIDR_NVPTYP ROM (0 << CHIPID_CIDR_NVPTYP_SHIFT) /* ROM */ +# define CHIPID_CIDR_NVPTYP FLASH (1 << CHIPID_CIDR_NVPTYP_SHIFT) /* ROMless or on-chip Flash */ +# define CHIPID_CIDR_NVPTYP SRAM (4 << CHIPID_CIDR_NVPTYP_SHIFT) /* SRAM emulating ROM */ +# define CHIPID_CIDR_NVPTYP EFLASH (2 << CHIPID_CIDR_NVPTYP_SHIFT) /* Embedded Flash Memory */ +# define CHIPID_CIDR_NVPTYP REFLASH (3 << CHIPID_CIDR_NVPTYP_SHIFT) /* ROM and Embedded Flash Memory */ +#define CHIPID_CIDR_EXT (1 << 31) /* Bit 31: Extension Flag */ + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +/**************************************************************************************** + * Public Data + ****************************************************************************************/ + +/**************************************************************************************** + * Public Functions + ****************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_CHIPID_H */ diff --git a/nuttx/arch/arm/src/sam3u/sam3u_clockconfig.c b/nuttx/arch/arm/src/sam3u/sam3u_clockconfig.c index 0093368e9..c9ddba964 100644 --- a/nuttx/arch/arm/src/sam3u/sam3u_clockconfig.c +++ b/nuttx/arch/arm/src/sam3u/sam3u_clockconfig.c @@ -3,7 +3,7 @@ * arch/arm/src/chip/sam3u_clockconfig.c * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/sam3u/sam3u_dmac.c b/nuttx/arch/arm/src/sam3u/sam3u_dmac.c index 8bb186e91..e3958af74 100644 --- a/nuttx/arch/arm/src/sam3u/sam3u_dmac.c +++ b/nuttx/arch/arm/src/sam3u/sam3u_dmac.c @@ -2,7 +2,7 @@ * arch/arm/src/sam3u-ek/sam3u_dmac.c * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/sam3u/sam3u_dmac.h b/nuttx/arch/arm/src/sam3u/sam3u_dmac.h index 523eaf686..9edf61df7 100644 --- a/nuttx/arch/arm/src/sam3u/sam3u_dmac.h +++ b/nuttx/arch/arm/src/sam3u/sam3u_dmac.h @@ -1,441 +1,441 @@ -/****************************************************************************************
- * arch/arm/src/sam3u/sam3u_dmac.h
- *
- * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_DMAC_H
-#define __ARCH_ARM_SRC_SAM3U_SAM3U_DMAC_H
-
-/****************************************************************************************
- * Included Files
- ****************************************************************************************/
-
-#include <nuttx/config.h>
-
-#include "chip.h"
-#include "sam3u_memorymap.h"
-
-/****************************************************************************************
- * Pre-processor Definitions
- ****************************************************************************************/
-
-/* DMAC register offsets ****************************************************************/
-
-/* Global Registers */
-
-#define SAM3U_DMAC_GCFG_OFFSET 0x00 /* DMAC Global Configuration Register */
-#define SAM3U_DMAC_EN_OFFSET 0x04 /* DMAC Enable Register */
-#define SAM3U_DMAC_SREQ_OFFSET 0x08 /* DMAC Software Single Request Register */
-#define SAM3U_DMAC_CREQ_OFFSET 0x0c /* DMAC Software Chunk Transfer Request Register */
-#define SAM3U_DMAC_LAST_OFFSET 0x10 /* DMAC Software Last Transfer Flag Register */
- /* 0x014-0x18: Reserved */
-#define SAM3U_DMAC_EBCIER_OFFSET 0x18 /* DMAC Error Enable */
-#define SAM3U_DMAC_EBCIDR_OFFSET 0x1C /* DMAC Error Disable */
-#define SAM3U_DMAC_EBCIMR_OFFSET 0x20 /* DMAC Error Mask */
-#define SAM3U_DMAC_EBCISR_OFFSET 0x24 /* DMAC Error Status */
-#define SAM3U_DMAC_CHER_OFFSET 0x28 /* DMAC Channel Handler Enable Register */
-#define SAM3U_DMAC_CHDR_OFFSET 0x2c /* DMAC Channel Handler Disable Register */
-#define SAM3U_DMAC_CHSR_OFFSET 0x30 /* DMAC Channel Handler Status Register */
- /* 0x034-0x38: Reserved */
-/* DMA channel registers */
-
-#define SAM3U_DMACHAN_OFFSET(n) (0x3c+((n)*0x28))
-#define SAM3U_DMACHAN0_OFFSET 0x3c /* 0x3c-0x60: Channel 0 */
-#define SAM3U_DMACHAN1_OFFSET 0x64 /* 0x64-0x88: Channel 1 */
-#define SAM3U_DMACHAN2_OFFSET 0x8c /* 0x8c-0xb0: Channel 2 */
-#define SAM3U_DMACHAN3_OFFSET 0xb4 /* 0xb4-0xd8: Channel 3 */
-
-#define SAM3U_DMACHAN_SADDR_OFFSET 0x00 /* DMAC Channel Source Address Register */
-#define SAM3U_DMACHAN_DADDR_OFFSET 0x04 /* DMAC Channel Destination Address Register */
-#define SAM3U_DMACHAN_DSCR_OFFSET 0x08 /* DMAC Channel Descriptor Address Register */
-#define SAM3U_DMACHAN_CTRLA_OFFSET 0x0c /* DMAC Channel Control A Register */
-#define SAM3U_DMACHAN_CTRLB_OFFSET 0x10 /* DMAC Channel Control B Register */
-#define SAM3U_DMACHAN_CFG_OFFSET 0x14 /* DMAC Channel Configuration Register */
- /* 0x18-0x24: Reserved */
-
- /* 0x017c-0x1fc: Reserved */
-
-/* DMAC register adresses ***************************************************************/
-
-/* Global Registers */
-
-#define SAM3U_DMAC_GCFG (SAM3U_DMAC_BASE+SAM3U_DMAC_GCFG_OFFSET)
-#define SAM3U_DMAC_EN (SAM3U_DMAC_BASE+SAM3U_DMAC_EN_OFFSET)
-#define SAM3U_DMAC_SREQ (SAM3U_DMAC_BASE+SAM3U_DMAC_SREQ_OFFSET)
-#define SAM3U_DMAC_CREQ (SAM3U_DMAC_BASE+SAM3U_DMAC_CREQ_OFFSET)
-#define SAM3U_DMAC_LAST (SAM3U_DMAC_BASE+SAM3U_DMAC_LAST_OFFSET)
-#define SAM3U_DMAC_EBCIER (SAM3U_DMAC_BASE+SAM3U_DMAC_EBCIER_OFFSET)
-#define SAM3U_DMAC_EBCIDR (SAM3U_DMAC_BASE+SAM3U_DMAC_EBCIDR_OFFSET)
-#define SAM3U_DMAC_EBCIMR (SAM3U_DMAC_BASE+SAM3U_DMAC_EBCIMR_OFFSET)
-#define SAM3U_DMAC_EBCISR (SAM3U_DMAC_BASE+SAM3U_DMAC_EBCISR_OFFSET)
-#define SAM3U_DMAC_CHER (SAM3U_DMAC_BASE+SAM3U_DMAC_CHER_OFFSET)
-#define SAM3U_DMAC_CHDR (SAM3U_DMAC_BASE+SAM3U_DMAC_CHDR_OFFSET)
-#define SAM3U_DMAC_CHSR (SAM3U_DMAC_BASE+SAM3U_DMAC_CHSR_OFFSET)
-
-/* DMA channel registers */
-
-#define SAM3U_DMACHAN_BASE(n) (SAM3U_DMAC_BASE+SAM3U_DMACHAN_OFFSET(n))
-#define SAM3U_DMACHAN0_BASE (SAM3U_DMAC_BASE+SAM3U_DMACHAN0_OFFSET)
-#define SAM3U_DMACHAN1_BASE (SAM3U_DMAC_BASE+SAM3U_DMACHAN1_OFFSET)
-#define SAM3U_DMACHAN2_BASE (SAM3U_DMAC_BASE+SAM3U_DMACHAN2_OFFSET)
-#define SAM3U_DMACHAN3_BASE (SAM3U_DMAC_BASE+SAM3U_DMACHAN3_OFFSET)
-
-#define SAM3U_DMACHAN_SADDR(n) (SAM3U_DMACHAN_BASE(n)+SAM3U_DMACHAN_SADDR_OFFSET)
-#define SAM3U_DMACHAN_DADDR(n) (SAM3U_DMACHAN_BASE(n)+SAM3U_DMACHAN_DADDR_OFFSET)
-#define SAM3U_DMACHAN_DSCR(n) (SAM3U_DMACHAN_BASE(n)+SAM3U_DMACHAN_DSCR_OFFSET)
-#define SAM3U_DMACHAN_CTRLA(n) (SAM3U_DMACHAN_BASE(n)+SAM3U_DMACHAN_CTRLA_OFFSET)
-#define SAM3U_DMACHAN_CTRLB(n) (SAM3U_DMACHAN_BASE(n)+SAM3U_DMACHAN_CTRLB_OFFSET)
-#define SAM3U_DMACHAN_CFG(n) (SAM3U_DMACHAN_BASE(n)+SAM3U_DMACHAN_CFG_OFFSET)
-
-#define SAM3U_DMACHAN0_SADDR (SAM3U_DMACHAN0_BASE+SAM3U_DMACHAN_SADDR_OFFSET)
-#define SAM3U_DMACHAN0_DADDR (SAM3U_DMACHAN0_BASE+SAM3U_DMACHAN_DADDR_OFFSET)
-#define SAM3U_DMACHAN0_DSCR (SAM3U_DMACHAN0_BASE+SAM3U_DMACHAN_DSCR_OFFSET)
-#define SAM3U_DMACHAN0_CTRLA (SAM3U_DMACHAN0_BASE+SAM3U_DMACHAN_CTRLA_OFFSET)
-#define SAM3U_DMACHAN0_CTRLB (SAM3U_DMACHAN0_BASE+SAM3U_DMACHAN_CTRLB_OFFSET)
-#define SAM3U_DMACHAN0_CFG (SAM3U_DMACHAN0_BASE+SAM3U_DMACHAN_CFG_OFFSET)
-
-#define SAM3U_DMACHAN1_SADDR (SAM3U_DMACHAN1_BASE+SAM3U_DMACHAN_SADDR_OFFSET)
-#define SAM3U_DMACHAN1_DADDR (SAM3U_DMACHAN1_BASE+SAM3U_DMACHAN_DADDR_OFFSET)
-#define SAM3U_DMACHAN1_DSCR (SAM3U_DMACHAN1_BASE+SAM3U_DMACHAN_DSCR_OFFSET)
-#define SAM3U_DMACHAN1_CTRLA (SAM3U_DMACHAN1_BASE+SAM3U_DMACHAN_CTRLA_OFFSET)
-#define SAM3U_DMACHAN1_CTRLB (SAM3U_DMACHAN1_BASE+SAM3U_DMACHAN_CTRLB_OFFSET)
-#define SAM3U_DMACHAN1_CFG (SAM3U_DMACHAN1_BASE+SAM3U_DMACHAN_CFG_OFFSET)
-
-#define SAM3U_DMACHAN2_SADDR (SAM3U_DMACHAN2_BASE+SAM3U_DMACHAN_SADDR_OFFSET)
-#define SAM3U_DMACHAN2_DADDR (SAM3U_DMACHAN2_BASE+SAM3U_DMACHAN_DADDR_OFFSET)
-#define SAM3U_DMACHAN2_DSCR (SAM3U_DMACHAN2_BASE+SAM3U_DMACHAN_DSCR_OFFSET)
-#define SAM3U_DMACHAN2_CTRLA (SAM3U_DMACHAN2_BASE+SAM3U_DMACHAN_CTRLA_OFFSET)
-#define SAM3U_DMACHAN2_CTRLB (SAM3U_DMACHAN2_BASE+SAM3U_DMACHAN_CTRLB_OFFSET)
-#define SAM3U_DMACHAN2_CFG (SAM3U_DMACHAN2_BASE+SAM3U_DMACHAN_CFG_OFFSET)
-
-#define SAM3U_DMACHAN3_SADDR (SAM3U_DMACHAN3_BASE+SAM3U_DMACHAN_SADDR_OFFSET)
-#define SAM3U_DMACHAN3_DADDR (SAM3U_DMACHAN3_BASE+SAM3U_DMACHAN_DADDR_OFFSET)
-#define SAM3U_DMACHAN3_DSCR (SAM3U_DMACHAN3_BASE+SAM3U_DMACHAN_DSCR_OFFSET)
-#define SAM3U_DMACHAN3_CTRLA (SAM3U_DMACHAN3_BASE+SAM3U_DMACHAN_CTRLA_OFFSET)
-#define SAM3U_DMACHAN3_CTRLB (SAM3U_DMACHAN3_BASE+SAM3U_DMACHAN_CTRLB_OFFSET)
-#define SAM3U_DMACHAN3_CFG (SAM3U_DMACHAN3_BASE+SAM3U_DMACHAN_CFG_OFFSET)
-
-/* DMAC register bit definitions ********************************************************/
-
-/* Global Registers */
-
-/* DMAC Global Configuration Register */
-
-#define DMAC_GCFG_ARB_CFG (1 << 4) /* Bit 4: Round robin (vs fixed) arbiter */
-
-/* DMAC Enable Register */
-
-#define DMAC_EN_ENABLE (1 << 0) /* Bit 0: DMA controller enable */
-
-/* DMAC Software Single Request Register */
-
-#define DMAC_SREQ_SHIFT(n) ((n)<<1)
-#define DMAC_SREQ_MASK(n) (3 << DMAC_SREQ_SHIFT(n))
-#define DMAC_SREQ0_SHIFT (0) /* Bits 0-1: Channel 0 */
-#define DMAC_SREQ0_MASK (3 << DMAC_SREQ0_SHIFT)
-#define DMAC_SREQ1_SHIFT (2) /* Bits 2-3: Channel 1 */
-#define DMAC_SREQ1_MASK (3 << DMAC_SREQ1_SHIFT)
-#define DMAC_SREQ2_SHIFT (4) /* Bits 4-5: Channel 2 */
-#define DMAC_SREQ2_MASK (3 << DMAC_SREQ2_SHIFT)
-#define DMAC_SREQ3_SHIFT (6) /* Bits 6-7: Channel 3 */
-#define DMAC_SREQ3_MASK (3 << DMAC_SREQ3_SHIFT)
-
-#define DMAC_SREQ_SSREQ_SHIFT (0) /* Bits 0, 2, 4, 6: Request a source single transfer */
-# define DMAC_SREQ_SSREQ(n) (1 << (DMAC_SREQ_SSREQ_SHIFT+DMAC_SREQ_SHIFT(n)))
-# define DMAC_SREQ_SSREQ0 (1 << (DMAC_SREQ_SSREQ_SHIFT+DMAC_SREQ0_SHIFT)
-# define DMAC_SREQ_SSREQ1 (1 << (DMAC_SREQ_SSREQ_SHIFT+DMAC_SREQ1_SHIFT)
-# define DMAC_SREQ_SSREQ2 (1 << (DMAC_SREQ_SSREQ_SHIFT+DMAC_SREQ2_SHIFT)
-# define DMAC_SREQ_SSREQ3 (1 << (DMAC_SREQ_SSREQ_SHIFT+DMAC_SREQ3_SHIFT)
-#define DMAC_SREQ_DSREQ_SHIFT (1) /* Bits 1, 3, 5, 7: Request a destination single transfer */
-# define DMAC_SREQ_DSREQ(n) (1 << (DMAC_SREQ_DSREQ_SHIFT+DMAC_SREQ_SHIFT(n))))
-# define DMAC_SREQ_DSREQ0 (1 << (DMAC_SREQ_DSREQ_SHIFT+DMAC_SREQ0_SHIFT)
-# define DMAC_SREQ_DSREQ1 (1 << (DMAC_SREQ_DSREQ_SHIFT+DMAC_SREQ1_SHIFT)
-# define DMAC_SREQ_DSREQ2 (1 << (DMAC_SREQ_DSREQ_SHIFT+DMAC_SREQ2_SHIFT)
-# define DMAC_SREQ_DSREQ3 (1 << (DMAC_SREQ_DSREQ_SHIFT+DMAC_SREQ3_SHIFT)
-
-/* DMAC Software Chunk Transfer Request Register */
-
-#define DMAC_CREQ_SHIFT(n) ((n)<<1)
-#define DMAC_CREQ_MASK(n) (3 << DMAC_CREQ_SHIFT(n))
-#define DMAC_CREQ0_SHIFT (0) /* Bits 0-1: Channel 0 */
-#define DMAC_CREQ0_MASK (3 << DMAC_CREQ0_SHIFT)
-#define DMAC_CREQ1_SHIFT (2) /* Bits 2-3: Channel 1 */
-#define DMAC_CREQ1_MASK (3 << DMAC_CREQ1_SHIFT)
-#define DMAC_CREQ2_SHIFT (4) /* Bits 4-5: Channel 2 */
-#define DMAC_CREQ2_MASK (3 << DMAC_CREQ2_SHIFT)
-#define DMAC_CREQ3_SHIFT (6) /* Bits 6-7: Channel 3 */
-#define DMAC_CREQ3_MASK (3 << DMAC_CREQ3_SHIFT)
-
-#define DMAC_CREQ_SCREQ_SHIFT (0) /* Bits 0, 2, 4, 6: Request a source chunk transfer */
-# define DMAC_CREQ_SCREQ(n) (1 << (DMAC_CREQ_SCREQ_SHIFT+DMAC_CREQ_SHIFT(n)))
-# define DMAC_CREQ_SCREQ0 (1 << (DMAC_CREQ_SCREQ_SHIFT+DMAC_CREQ0_SHIFT)
-# define DMAC_CREQ_SCREQ1 (1 << (DMAC_CREQ_SCREQ_SHIFT+DMAC_CREQ1_SHIFT)
-# define DMAC_CREQ_SCREQ2 (1 << (DMAC_CREQ_SCREQ_SHIFT+DMAC_CREQ2_SHIFT)
-# define DMAC_CREQ_SCREQ3 (1 << (DMAC_CREQ_SCREQ_SHIFT+DMAC_CREQ3_SHIFT)
-#define DMAC_CREQ_DCREQ_SHIFT (1) /* Bits 1, 3, 5, 7: Request a destination chunk transfer */
-# define DMAC_CREQ_DCREQ(n) (1 << (DMAC_CREQ_DCREQ_SHIFT+DMAC_CREQ_SHIFT(n))))
-# define DMAC_CREQ_DCREQ0 (1 << (DMAC_CREQ_DCREQ_SHIFT+DMAC_CREQ0_SHIFT)
-# define DMAC_CREQ_DCREQ1 (1 << (DMAC_CREQ_DCREQ_SHIFT+DMAC_CREQ1_SHIFT)
-# define DMAC_CREQ_DCREQ2 (1 << (DMAC_CREQ_DCREQ_SHIFT+DMAC_CREQ2_SHIFT)
-# define DMAC_CREQ_DCREQ3 (1 << (DMAC_CREQ_DCREQ_SHIFT+DMAC_CREQ3_SHIFT)
-
-/* DMAC Software Last Transfer Flag Register */
-
-#define DMAC_LAST_SHIFT(n) ((n)<<1)
-#define DMAC_LAST_MASK(n) (3 << DMAC_LAST_SHIFT(n))
-#define DMAC_LAST0_SHIFT (0) /* Bits 0-1: Channel 0 */
-#define DMAC_LAST0_MASK (3 << DMAC_LAST0_SHIFT)
-#define DMAC_LAST1_SHIFT (2) /* Bits 2-3: Channel 1 */
-#define DMAC_LAST1_MASK (3 << DMAC_LAST1_SHIFT)
-#define DMAC_LAST2_SHIFT (4) /* Bits 4-5: Channel 2 */
-#define DMAC_LAST2_MASK (3 << DMAC_LAST2_SHIFT)
-#define DMAC_LAST3_SHIFT (6) /* Bits 6-7: Channel 3 */
-#define DMAC_LAST3_MASK (3 << DMAC_LAST3_SHIFT)
-
-#define DMAC_LAST_SLAST_SHIFT (0) /* Bits 0, 2, 4, 6: Indicates the last transfer */
-# define DMAC_LAST_SLAST(n) (1 << (DMAC_LAST_SLAST_SHIFT+DMAC_LAST_SHIFT(n)))
-# define DMAC_LAST_SLAST0 (1 << (DMAC_LAST_SLAST_SHIFT+DMAC_LAST0_SHIFT)
-# define DMAC_LAST_SLAST1 (1 << (DMAC_LAST_SLAST_SHIFT+DMAC_LAST1_SHIFT)
-# define DMAC_LAST_SLAST2 (1 << (DMAC_LAST_SLAST_SHIFT+DMAC_LAST2_SHIFT)
-# define DMAC_LAST_SLAST3 (1 << (DMAC_LAST_SLAST_SHIFT+DMAC_LAST3_SHIFT)
-#define DMAC_LAST_DLAST_SHIFT (1) /* Bits 1, 3, 5, 7: Indicates the last transfer */
-# define DMAC_LAST_DLAST(n) (1 << (DMAC_LAST_DLAST_SHIFT+DMAC_LAST_SHIFT(n))))
-# define DMAC_LAST_DLAST0 (1 << (DMAC_LAST_DLAST_SHIFT+DMAC_LAST0_SHIFT)
-# define DMAC_LAST_DLAST1 (1 << (DMAC_LAST_DLAST_SHIFT+DMAC_LAST1_SHIFT)
-# define DMAC_LAST_DLAST2 (1 << (DMAC_LAST_DLAST_SHIFT+DMAC_LAST2_SHIFT)
-# define DMAC_LAST_DLAST3 (1 << (DMAC_LAST_DLAST_SHIFT+DMAC_LAST3_SHIFT)
-
-/* DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Enable Register,
- * DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Disable Register,
- * DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Mask Register, and
- * DMAC Error, Buffer Transfer and Chained Buffer Transfer Status Register common
- * bit field definitions
- */
-
-#define DMAC_EBC_BTC_SHIFT (0) /* Bits 0-3: Buffer Transfer Completed Interrupt Enable */
-#define DMAC_EBC_BTC_MASK (15 << DMAC_EBC_BTC_SHIFT)
-# define DMAC_EBC_BTC(n) (1 << (DMAC_EBC_BTC_SHIFT+(n)))
-# define DMAC_EBC_BTC0 (1 << (DMAC_EBC_BTC_SHIFT+0))
-# define DMAC_EBC_BTC1 (1 << (DMAC_EBC_BTC_SHIFT+1))
-# define DMAC_EBC_BTC2 (1 << (DMAC_EBC_BTC_SHIFT+2))
-# define DMAC_EBC_BTC3 (1 << (DMAC_EBC_BTC_SHIFT+3))
-#define DMAC_EBC_CBTC_SHIFT (8) /* Bits 8-11: Chained Buffer Transfer Completed Interrupt Enable */
-#define DMAC_EBC_CBTC_MASK (15 << DMAC_EBC_CBTC_SHIFT)
-# define DMAC_EBC_CBTC(n) (1 << (DMAC_EBC_CBTC_SHIFT+(n)))
-# define DMAC_EBC_CBTC0 (1 << (DMAC_EBC_CBTC_SHIFT+0))
-# define DMAC_EBC_CBTC1 (1 << (DMAC_EBC_CBTC_SHIFT+1))
-# define DMAC_EBC_CBTC2 (1 << (DMAC_EBC_CBTC_SHIFT+2))
-# define DMAC_EBC_CBTC3 (1 << (DMAC_EBC_CBTC_SHIFT+3))
-#define DMAC_EBC_ERR_SHIFT (16) /* Bits 16-19: Access Error Interrupt Enable */
-#define DMAC_EBC_ERR_MASK (15 << DMAC_EBC_ERR_SHIFT)
-# define DMAC_EBC_ERR(n) (1 << (DMAC_EBC_ERR_SHIFT+(n)))
-# define DMAC_EBC_ERR0 (1 << (DMAC_EBC_ERR_SHIFT+0))
-# define DMAC_EBC_ERR1 (1 << (DMAC_EBC_ERR_SHIFT+1))
-# define DMAC_EBC_ERR2 (1 << (DMAC_EBC_ERR_SHIFT+2))
-# define DMAC_EBC_ERR3 (1 << (DMAC_EBC_ERR_SHIFT+3))
-
-#define DMAC_EBC_BTCINTS(n) (0x00010001 << (n)) /* BTC + ERR interrupts */
-#define DMAC_EBC_CBTCINTS(n) (0x00010100 << (n)) /* CBT + ERR interrupts */
-#define DMAC_EBC_CHANINTS(n) (0x00010101 << (n)) /* All channel interrupts */
-#define DMAC_EBC_ALLINTS (0x000f0f0f) /* All interrupts */
-
-/* DMAC Channel Handler Enable Register */
-
-#define DMAC_CHER_ENA_SHIFT (0) /* Bits 0-3: Enable channel */
-#define DMAC_CHER_ENA_MASK (15 << DMAC_CHER_ENA_SHIFT)
-# define DMAC_CHER_ENA(n) (1 << (DMAC_CHER_ENA_SHIFT+(n)))
-# define DMAC_CHER_ENA0 (1 << (DMAC_CHER_ENA_SHIFT+0))
-# define DMAC_CHER_ENA1 (1 << (DMAC_CHER_ENA_SHIFT+1))
-# define DMAC_CHER_ENA2 (1 << (DMAC_CHER_ENA_SHIFT+2))
-# define DMAC_CHER_ENA3 (1 << (DMAC_CHER_ENA_SHIFT+3))
-#define DMAC_CHER_SUSP_SHIFT (8) /* Bits 8-11: Freeze channel and its context */
-#define DMAC_CHER_SUSP_MASK (15 << DMAC_CHER_SUSP_SHIFT)
-# define DMAC_CHER_SUSP(n) (1 << (DMAC_CHER_SUSP_SHIFT+(n)))
-# define DMAC_CHER_SUSP0 (1 << (DMAC_CHER_SUSP_SHIFT+0))
-# define DMAC_CHER_SUSP1 (1 << (DMAC_CHER_SUSP_SHIFT+1))
-# define DMAC_CHER_SUSP2 (1 << (DMAC_CHER_SUSP_SHIFT+2))
-# define DMAC_CHER_SUSP3 (1 << (DMAC_CHER_SUSP_SHIFT+3))
-#define DMAC_CHER_KEEP_SHIFT (24) /* Bits 24-27: Resume channel from automatic stall */
-#define DMAC_CHER_KEEP_MASK (15 << DMAC_CHER_KEEP_SHIFT)
-# define DMAC_CHER_KEEP(n) (1 << (DMAC_CHER_KEEP_SHIFT+(n)))
-# define DMAC_CHER_KEEP0 (1 << (DMAC_CHER_KEEP_SHIFT+0))
-# define DMAC_CHER_KEEP1 (1 << (DMAC_CHER_KEEP_SHIFT+1))
-# define DMAC_CHER_KEEP2 (1 << (DMAC_CHER_KEEP_SHIFT+2))
-# define DMAC_CHER_KEEP3 (1 << (DMAC_CHER_KEEP_SHIFT+3))
-
-/* DMAC Channel Handler Disable Register */
-
-#define DMAC_CHDR_DIS_SHIFT (0) /* Bits 0-3: Disable DMAC channel */
-#define DMAC_CHDR_DIS_MASK (15 << DMAC_CHDR_DIS_SHIFT)
-# define DMAC_CHDR_DIS(n) (1 << (DMAC_CHDR_DIS_SHIFT+(n)))
-# define DMAC_CHDR_DIS0 (1 << (DMAC_CHDR_DIS_SHIFT+0))
-# define DMAC_CHDR_DIS1 (1 << (DMAC_CHDR_DIS_SHIFT+1))
-# define DMAC_CHDR_DIS2 (1 << (DMAC_CHDR_DIS_SHIFT+2))
-# define DMAC_CHDR_DIS3 (1 << (DMAC_CHDR_DIS_SHIFT+3))
-# define DMAC_CHDR_DIS_ALL DMAC_CHDR_DIS_MASK
-#define DMAC_CHDR_RES_SHIFT (8) /* Bits 8-11: Resume trasnfer, restoring context */
-#define DMAC_CHDR_RES_MASK (15 << DMAC_CHDR_RES_SHIFT)
-# define DMAC_CHDR_RES(n) (1 << (DMAC_CHDR_RES_SHIFT+(n)))
-# define DMAC_CHDR_RES0 (1 << (DMAC_CHDR_RES_SHIFT+0))
-# define DMAC_CHDR_RES1 (1 << (DMAC_CHDR_RES_SHIFT+1))
-# define DMAC_CHDR_RES2 (1 << (DMAC_CHDR_RES_SHIFT+2))
-# define DMAC_CHDR_RES3 (1 << (DMAC_CHDR_RES_SHIFT+3))
-
-/* DMAC Channel Handler Status Register */
-
-#define DMAC_CHSR_ENA_SHIFT (0) /* Bits 0-3: Indicates that the channel is stalling */
-#define DMAC_CHSR_ENA_MASK (15 << DMAC_CHSR_ENA_SHIFT)
-# define DMAC_CHSR_ENA(n) (1 << (DMAC_CHSR_ENA_SHIFT+(n)))
-# define DMAC_CHSR_ENA0 (1 << (DMAC_CHSR_ENA_SHIFT+0))
-# define DMAC_CHSR_ENA1 (1 << (DMAC_CHSR_ENA_SHIFT+1))
-# define DMAC_CHSR_ENA2 (1 << (DMAC_CHSR_ENA_SHIFT+2))
-# define DMAC_CHSR_ENA3 (1 << (DMAC_CHSR_ENA_SHIFT+3))
-#define DMAC_CHSR_SUSP_SHIFT (8) /* Bits 8-11: Indicates that the channel is empty */
-#define DMAC_CHSR_SUSP_MASK (15 << DMAC_CHSR_SUSP_SHIFT)
-# define DMAC_CHSR_SUSP(n) (1 << (DMAC_CHSR_SUSP_SHIFT+(n)))
-# define DMAC_CHSR_SUSP0 (1 << (DMAC_CHSR_SUSP_SHIFT+0))
-# define DMAC_CHSR_SUSP1 (1 << (DMAC_CHSR_SUSP_SHIFT+1))
-# define DMAC_CHSR_SUSP2 (1 << (DMAC_CHSR_SUSP_SHIFT+2))
-# define DMAC_CHSR_SUSP3 (1 << (DMAC_CHSR_SUSP_SHIFT+3))
-#define DMAC_CHSR_EMPT_SHIFT (16) /* Bits 16-19: Access Error Interrupt Enable */
-#define DMAC_CHSR_EMPT_MASK (15 << DMAC_CHSR_EMPT_SHIFT)
-# define DMAC_CHSR_EMPT(n) (1 << (DMAC_CHSR_EMPT_SHIFT+(n)))
-# define DMAC_CHSR_EMPT0 (1 << (DMAC_CHSR_EMPT_SHIFT+0))
-# define DMAC_CHSR_EMPT1 (1 << (DMAC_CHSR_EMPT_SHIFT+1))
-# define DMAC_CHSR_EMPT2 (1 << (DMAC_CHSR_EMPT_SHIFT+2))
-# define DMAC_CHSR_EMPT3 (1 << (DMAC_CHSR_EMPT_SHIFT+3))
-#define DMAC_CHSR_STAL_SHIFT (24) /* Bits 24-27: Access Error Interrupt Enable */
-#define DMAC_CHSR_STAL_MASK (15 << DMAC_CHSR_STAL_SHIFT)
-# define DMAC_CHSR_STAL(n) (1 << (DMAC_CHSR_STAL_SHIFT+(n)))
-# define DMAC_CHSR_STAL0 (1 << (DMAC_CHSR_STAL_SHIFT+0))
-# define DMAC_CHSR_STAL1 (1 << (DMAC_CHSR_STAL_SHIFT+1))
-# define DMAC_CHSR_STAL2 (1 << (DMAC_CHSR_STAL_SHIFT+2))
-# define DMAC_CHSR_STAL3 (1 << (DMAC_CHSR_STAL_SHIFT+3))
-
-/* DMA channel registers */
-/* DMAC Channel n [n = 0..3] Control A Register */
-
-#define DMACHAN_CTRLA_BTSIZE_MAX (0xfff)
-#define DMACHAN_CTRLA_BTSIZE_SHIFT (0) /* Bits 0-11: Buffer Transfer Size */
-#define DMACHAN_CTRLA_BTSIZE_MASK (DMACHAN_CTRLA_BTSIZE_MAX << DMACHAN_CTRLA_BTSIZE_SHIFT)
-#define DMACHAN_CTRLA_SCSIZE (1 << 16) /* Bit 16: Source Chunk Transfer Size */
-# define DMACHAN_CTRLA_SCSIZE_1 (0)
-# define DMACHAN_CTRLA_SCSIZE_4 DMACHAN_CTRLA_SCSIZE
-#define DMACHAN_CTRLA_DCSIZE (1 << 20) /* Bit 20: Destination Chunk Transfer size */
-# define DMACHAN_CTRLA_DCSIZE_1 (0)
-# define DMACHAN_CTRLA_DCSIZE_4 DMACHAN_CTRLA_DCSIZE
-#define DMACHAN_CTRLA_SRCWIDTH_SHIFT (24) /* Bits 24-25 */
-#define DMACHAN_CTRLA_SRCWIDTH_MASK (3 << DMACHAN_CTRLA_SRCWIDTH_SHIFT)
-# define DMACHAN_CTRLA_SRCWIDTH_BYTE (0 << DMACHAN_CTRLA_SRCWIDTH_SHIFT)
-# define DMACHAN_CTRLA_SRCWIDTH_HWORD (1 << DMACHAN_CTRLA_SRCWIDTH_SHIFT)
-# define DMACHAN_CTRLA_SRCWIDTH_WORD (2 << DMACHAN_CTRLA_SRCWIDTH_SHIFT)
-#define DMACHAN_CTRLA_DSTWIDTH_SHIFT (28) /* Bits 28-29 */
-#define DMACHAN_CTRLA_DSTWIDTH_MASK (3 << DMACHAN_CTRLA_DSTWIDTH_SHIFT)
-# define DMACHAN_CTRLA_DSTWIDTH_BYTE (0 << DMACHAN_CTRLA_DSTWIDTH_SHIFT)
-# define DMACHAN_CTRLA_DSTWIDTH_HWORD (1 << DMACHAN_CTRLA_DSTWIDTH_SHIFT)
-# define DMACHAN_CTRLA_DSTWIDTH_WORD (2 << DMACHAN_CTRLA_DSTWIDTH_SHIFT)
-#define DMACHAN_CTRLA_DONE (1 << 31) /* Bit 31: Auto disable DMAC */
-
-/* DMAC Channel n [n = 0..3] Control B Register */
-
-#define DMACHAN_CTRLB_SRCDSCR (1 << 16) /* Bit 16: Source buffer descriptor fetch operation disabled */
-#define DMACHAN_CTRLB_DSTDSCR (1 << 20) /* Bit 20: Dest buffer descriptor fetch operation disabled */
-#define DMACHAN_CTRLB_FC_SHIFT (21) /* Bits 21-22: Flow controller */
-#define DMACHAN_CTRLB_FC_MASK (3 << DMACHAN_CTRLB_FC_SHIFT)
-# define DMACHAN_CTRLB_FC_M2M (0 << DMACHAN_CTRLB_FC_SHIFT) /* Memory-to-Memory */
-# define DMACHAN_CTRLB_FC_M2P (1 << DMACHAN_CTRLB_FC_SHIFT) /* Memory-to-Peripheral */
-# define DMACHAN_CTRLB_FC_P2M (2 << DMACHAN_CTRLB_FC_SHIFT) /* Peripheral-to-Memory */
-# define DMACHAN_CTRLB_FC_P2P (3 << DMACHAN_CTRLB_FC_SHIFT) /* Peripheral-to-Peripheral */
-#define DMACHAN_CTRLB_SRCINCR_SHIFT (24) /* Bits 24-25 */
-#define DMACHAN_CTRLB_SRCINCR_MASK (3 << DMACHAN_CTRLB_SRCINCR_SHIFT)
-# define DMACHAN_CTRLB_SRCINCR_INCR (0 << DMACHAN_CTRLB_SRCINCR_SHIFT) /* Incrementing address */
-# define DMACHAN_CTRLB_SRCINCR_FIXED (2 << DMACHAN_CTRLB_SRCINCR_SHIFT) /* Fixed address */
-#define DMACHAN_CTRLB_DSTINCR_SHIFT (28) /* Bits 28-29 */
-#define DMACHAN_CTRLB_DSTINCR_MASK (3 << DMACHAN_CTRLB_DSTINCR_SHIFT)
-# define DMACHAN_CTRLB_DSTINCR_INCR (0 << DMACHAN_CTRLB_DSTINCR_SHIFT) /* Incrementing address */
-# define DMACHAN_CTRLB_DSTINCR_FIXED (2 << DMACHAN_CTRLB_DSTINCR_SHIFT) /* Fixed address */
-#define DMACHAN_CTRLB_IEN (1 << 30) /* Bit 30: Clear sets BTC[n] flag in EBCISR */
-
-/* DMAC Channel n [n = 0..3] Configuration Register */
-
-#define DMACHAN_CFG_SRCPER_SHIFT (0) /* Bits 0-3: Channel source associated with peripheral ID */
-#define DMACHAN_CFG_SRCPER_MASK (15 << DMACHAN_CFG_SRCPER_SHIFT)
-#define DMACHAN_CFG_DSTPER_SHIFT (4) /* Bits 4-7: Channel dest associated with peripheral ID */
-#define DMACHAN_CFG_DSTPER_MASK (15 << DMACHAN_CFG_DSTPER_SHIFT)
-#define DMACHAN_CFG_SRCH2SEL (1 << 9) /* Bit 9: HW handshake triggers transfer */
-#define DMACHAN_CFG_DSTH2SEL (1 << 13) /* Bit 13: HW handshake trigger transfer */
-#define DMACHAN_CFG_SOD (1 << 16) /* Bit 16: Stop on done */
-#define DMACHAN_CFG_LOCKIF (1 << 20) /* Bit 20: Enable lock interface capability */
-#define DMACHAN_CFG_LOCKB (1 << 21) /* Bit 21: Enable AHB Bus Locking capability */
-#define DMACHAN_CFG_LOCKIFL (1 << 22) /* Bit 22: Lock Master Interface Arbiter */
-#define DMACHAN_CFG_AHBPRO_SHIFT (24) /* Bits 24-26: Bus access privilege */
-#define DMACHAN_CFG_AHBPRO_MASK (7 << DMACHAN_CFG_AHBPRO_SHIFT)
-# define DMACHAN_CFG_AHBPRO_PRIV (1 << DMACHAN_CFG_AHBPRO_SHIFT)
-# define DMACHAN_CFG_AHBPRO_BUFF (2 << DMACHAN_CFG_AHBPRO_SHIFT)
-# define DMACHAN_CFG_AHBPRO_CACHE (4 << DMACHAN_CFG_AHBPRO_SHIFT)
-#define DMACHAN_CFG_FIFOCFG_SHIFT (28) /* Bits 28-29 */
-#define DMACHAN_CFG_FIFOCFG_MASK (3 << DMACHAN_CFG_FIFOCFG_SHIFT)
-# define DMACHAN_CFG_FIFOCFG_LARGEST (0 << DMACHAN_CFG_FIFOCFG_SHIFT) /* Largest length AHB burst */
-# define DMACHAN_CFG_FIFOCFG_HALF (1 << DMACHAN_CFG_FIFOCFG_SHIFT) /* Half FIFO size */
-# define DMACHAN_CFG_FIFOCFG_SINGLE (2 << DMACHAN_CFG_FIFOCFG_SHIFT) /* Single AHB access */
-
-/* DMA Peripheral IDs *******************************************************************/
-
-#define DMACHAN_PID_MCI0 0
-#define DMACHAN_PID_SSC 3
-#define DMACHAN_PID_MCI1 13
-
-/****************************************************************************************
- * Public Types
- ****************************************************************************************/
-
-/* DMA multi buffer transfer link list entry structure */
-
-struct dma_linklist_s
-{
- uint32_t src; /* Source address */
- uint32_t dest; /* Destination address */
- uint32_t ctrla; /* Control A value */
- uint32_t ctrlb; /* Control B value */
- uint32_t next; /* Next descriptor address */
-};
-
-/****************************************************************************************
- * Public Data
- ****************************************************************************************/
-
-/****************************************************************************************
- * Public Functions
- ****************************************************************************************/
-
-#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_DMAC_H */
+/**************************************************************************************** + * arch/arm/src/sam3u/sam3u_dmac.h + * + * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_DMAC_H +#define __ARCH_ARM_SRC_SAM3U_SAM3U_DMAC_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +#include <nuttx/config.h> + +#include "chip.h" +#include "sam3u_memorymap.h" + +/**************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************/ + +/* DMAC register offsets ****************************************************************/ + +/* Global Registers */ + +#define SAM3U_DMAC_GCFG_OFFSET 0x00 /* DMAC Global Configuration Register */ +#define SAM3U_DMAC_EN_OFFSET 0x04 /* DMAC Enable Register */ +#define SAM3U_DMAC_SREQ_OFFSET 0x08 /* DMAC Software Single Request Register */ +#define SAM3U_DMAC_CREQ_OFFSET 0x0c /* DMAC Software Chunk Transfer Request Register */ +#define SAM3U_DMAC_LAST_OFFSET 0x10 /* DMAC Software Last Transfer Flag Register */ + /* 0x014-0x18: Reserved */ +#define SAM3U_DMAC_EBCIER_OFFSET 0x18 /* DMAC Error Enable */ +#define SAM3U_DMAC_EBCIDR_OFFSET 0x1C /* DMAC Error Disable */ +#define SAM3U_DMAC_EBCIMR_OFFSET 0x20 /* DMAC Error Mask */ +#define SAM3U_DMAC_EBCISR_OFFSET 0x24 /* DMAC Error Status */ +#define SAM3U_DMAC_CHER_OFFSET 0x28 /* DMAC Channel Handler Enable Register */ +#define SAM3U_DMAC_CHDR_OFFSET 0x2c /* DMAC Channel Handler Disable Register */ +#define SAM3U_DMAC_CHSR_OFFSET 0x30 /* DMAC Channel Handler Status Register */ + /* 0x034-0x38: Reserved */ +/* DMA channel registers */ + +#define SAM3U_DMACHAN_OFFSET(n) (0x3c+((n)*0x28)) +#define SAM3U_DMACHAN0_OFFSET 0x3c /* 0x3c-0x60: Channel 0 */ +#define SAM3U_DMACHAN1_OFFSET 0x64 /* 0x64-0x88: Channel 1 */ +#define SAM3U_DMACHAN2_OFFSET 0x8c /* 0x8c-0xb0: Channel 2 */ +#define SAM3U_DMACHAN3_OFFSET 0xb4 /* 0xb4-0xd8: Channel 3 */ + +#define SAM3U_DMACHAN_SADDR_OFFSET 0x00 /* DMAC Channel Source Address Register */ +#define SAM3U_DMACHAN_DADDR_OFFSET 0x04 /* DMAC Channel Destination Address Register */ +#define SAM3U_DMACHAN_DSCR_OFFSET 0x08 /* DMAC Channel Descriptor Address Register */ +#define SAM3U_DMACHAN_CTRLA_OFFSET 0x0c /* DMAC Channel Control A Register */ +#define SAM3U_DMACHAN_CTRLB_OFFSET 0x10 /* DMAC Channel Control B Register */ +#define SAM3U_DMACHAN_CFG_OFFSET 0x14 /* DMAC Channel Configuration Register */ + /* 0x18-0x24: Reserved */ + + /* 0x017c-0x1fc: Reserved */ + +/* DMAC register adresses ***************************************************************/ + +/* Global Registers */ + +#define SAM3U_DMAC_GCFG (SAM3U_DMAC_BASE+SAM3U_DMAC_GCFG_OFFSET) +#define SAM3U_DMAC_EN (SAM3U_DMAC_BASE+SAM3U_DMAC_EN_OFFSET) +#define SAM3U_DMAC_SREQ (SAM3U_DMAC_BASE+SAM3U_DMAC_SREQ_OFFSET) +#define SAM3U_DMAC_CREQ (SAM3U_DMAC_BASE+SAM3U_DMAC_CREQ_OFFSET) +#define SAM3U_DMAC_LAST (SAM3U_DMAC_BASE+SAM3U_DMAC_LAST_OFFSET) +#define SAM3U_DMAC_EBCIER (SAM3U_DMAC_BASE+SAM3U_DMAC_EBCIER_OFFSET) +#define SAM3U_DMAC_EBCIDR (SAM3U_DMAC_BASE+SAM3U_DMAC_EBCIDR_OFFSET) +#define SAM3U_DMAC_EBCIMR (SAM3U_DMAC_BASE+SAM3U_DMAC_EBCIMR_OFFSET) +#define SAM3U_DMAC_EBCISR (SAM3U_DMAC_BASE+SAM3U_DMAC_EBCISR_OFFSET) +#define SAM3U_DMAC_CHER (SAM3U_DMAC_BASE+SAM3U_DMAC_CHER_OFFSET) +#define SAM3U_DMAC_CHDR (SAM3U_DMAC_BASE+SAM3U_DMAC_CHDR_OFFSET) +#define SAM3U_DMAC_CHSR (SAM3U_DMAC_BASE+SAM3U_DMAC_CHSR_OFFSET) + +/* DMA channel registers */ + +#define SAM3U_DMACHAN_BASE(n) (SAM3U_DMAC_BASE+SAM3U_DMACHAN_OFFSET(n)) +#define SAM3U_DMACHAN0_BASE (SAM3U_DMAC_BASE+SAM3U_DMACHAN0_OFFSET) +#define SAM3U_DMACHAN1_BASE (SAM3U_DMAC_BASE+SAM3U_DMACHAN1_OFFSET) +#define SAM3U_DMACHAN2_BASE (SAM3U_DMAC_BASE+SAM3U_DMACHAN2_OFFSET) +#define SAM3U_DMACHAN3_BASE (SAM3U_DMAC_BASE+SAM3U_DMACHAN3_OFFSET) + +#define SAM3U_DMACHAN_SADDR(n) (SAM3U_DMACHAN_BASE(n)+SAM3U_DMACHAN_SADDR_OFFSET) +#define SAM3U_DMACHAN_DADDR(n) (SAM3U_DMACHAN_BASE(n)+SAM3U_DMACHAN_DADDR_OFFSET) +#define SAM3U_DMACHAN_DSCR(n) (SAM3U_DMACHAN_BASE(n)+SAM3U_DMACHAN_DSCR_OFFSET) +#define SAM3U_DMACHAN_CTRLA(n) (SAM3U_DMACHAN_BASE(n)+SAM3U_DMACHAN_CTRLA_OFFSET) +#define SAM3U_DMACHAN_CTRLB(n) (SAM3U_DMACHAN_BASE(n)+SAM3U_DMACHAN_CTRLB_OFFSET) +#define SAM3U_DMACHAN_CFG(n) (SAM3U_DMACHAN_BASE(n)+SAM3U_DMACHAN_CFG_OFFSET) + +#define SAM3U_DMACHAN0_SADDR (SAM3U_DMACHAN0_BASE+SAM3U_DMACHAN_SADDR_OFFSET) +#define SAM3U_DMACHAN0_DADDR (SAM3U_DMACHAN0_BASE+SAM3U_DMACHAN_DADDR_OFFSET) +#define SAM3U_DMACHAN0_DSCR (SAM3U_DMACHAN0_BASE+SAM3U_DMACHAN_DSCR_OFFSET) +#define SAM3U_DMACHAN0_CTRLA (SAM3U_DMACHAN0_BASE+SAM3U_DMACHAN_CTRLA_OFFSET) +#define SAM3U_DMACHAN0_CTRLB (SAM3U_DMACHAN0_BASE+SAM3U_DMACHAN_CTRLB_OFFSET) +#define SAM3U_DMACHAN0_CFG (SAM3U_DMACHAN0_BASE+SAM3U_DMACHAN_CFG_OFFSET) + +#define SAM3U_DMACHAN1_SADDR (SAM3U_DMACHAN1_BASE+SAM3U_DMACHAN_SADDR_OFFSET) +#define SAM3U_DMACHAN1_DADDR (SAM3U_DMACHAN1_BASE+SAM3U_DMACHAN_DADDR_OFFSET) +#define SAM3U_DMACHAN1_DSCR (SAM3U_DMACHAN1_BASE+SAM3U_DMACHAN_DSCR_OFFSET) +#define SAM3U_DMACHAN1_CTRLA (SAM3U_DMACHAN1_BASE+SAM3U_DMACHAN_CTRLA_OFFSET) +#define SAM3U_DMACHAN1_CTRLB (SAM3U_DMACHAN1_BASE+SAM3U_DMACHAN_CTRLB_OFFSET) +#define SAM3U_DMACHAN1_CFG (SAM3U_DMACHAN1_BASE+SAM3U_DMACHAN_CFG_OFFSET) + +#define SAM3U_DMACHAN2_SADDR (SAM3U_DMACHAN2_BASE+SAM3U_DMACHAN_SADDR_OFFSET) +#define SAM3U_DMACHAN2_DADDR (SAM3U_DMACHAN2_BASE+SAM3U_DMACHAN_DADDR_OFFSET) +#define SAM3U_DMACHAN2_DSCR (SAM3U_DMACHAN2_BASE+SAM3U_DMACHAN_DSCR_OFFSET) +#define SAM3U_DMACHAN2_CTRLA (SAM3U_DMACHAN2_BASE+SAM3U_DMACHAN_CTRLA_OFFSET) +#define SAM3U_DMACHAN2_CTRLB (SAM3U_DMACHAN2_BASE+SAM3U_DMACHAN_CTRLB_OFFSET) +#define SAM3U_DMACHAN2_CFG (SAM3U_DMACHAN2_BASE+SAM3U_DMACHAN_CFG_OFFSET) + +#define SAM3U_DMACHAN3_SADDR (SAM3U_DMACHAN3_BASE+SAM3U_DMACHAN_SADDR_OFFSET) +#define SAM3U_DMACHAN3_DADDR (SAM3U_DMACHAN3_BASE+SAM3U_DMACHAN_DADDR_OFFSET) +#define SAM3U_DMACHAN3_DSCR (SAM3U_DMACHAN3_BASE+SAM3U_DMACHAN_DSCR_OFFSET) +#define SAM3U_DMACHAN3_CTRLA (SAM3U_DMACHAN3_BASE+SAM3U_DMACHAN_CTRLA_OFFSET) +#define SAM3U_DMACHAN3_CTRLB (SAM3U_DMACHAN3_BASE+SAM3U_DMACHAN_CTRLB_OFFSET) +#define SAM3U_DMACHAN3_CFG (SAM3U_DMACHAN3_BASE+SAM3U_DMACHAN_CFG_OFFSET) + +/* DMAC register bit definitions ********************************************************/ + +/* Global Registers */ + +/* DMAC Global Configuration Register */ + +#define DMAC_GCFG_ARB_CFG (1 << 4) /* Bit 4: Round robin (vs fixed) arbiter */ + +/* DMAC Enable Register */ + +#define DMAC_EN_ENABLE (1 << 0) /* Bit 0: DMA controller enable */ + +/* DMAC Software Single Request Register */ + +#define DMAC_SREQ_SHIFT(n) ((n)<<1) +#define DMAC_SREQ_MASK(n) (3 << DMAC_SREQ_SHIFT(n)) +#define DMAC_SREQ0_SHIFT (0) /* Bits 0-1: Channel 0 */ +#define DMAC_SREQ0_MASK (3 << DMAC_SREQ0_SHIFT) +#define DMAC_SREQ1_SHIFT (2) /* Bits 2-3: Channel 1 */ +#define DMAC_SREQ1_MASK (3 << DMAC_SREQ1_SHIFT) +#define DMAC_SREQ2_SHIFT (4) /* Bits 4-5: Channel 2 */ +#define DMAC_SREQ2_MASK (3 << DMAC_SREQ2_SHIFT) +#define DMAC_SREQ3_SHIFT (6) /* Bits 6-7: Channel 3 */ +#define DMAC_SREQ3_MASK (3 << DMAC_SREQ3_SHIFT) + +#define DMAC_SREQ_SSREQ_SHIFT (0) /* Bits 0, 2, 4, 6: Request a source single transfer */ +# define DMAC_SREQ_SSREQ(n) (1 << (DMAC_SREQ_SSREQ_SHIFT+DMAC_SREQ_SHIFT(n))) +# define DMAC_SREQ_SSREQ0 (1 << (DMAC_SREQ_SSREQ_SHIFT+DMAC_SREQ0_SHIFT) +# define DMAC_SREQ_SSREQ1 (1 << (DMAC_SREQ_SSREQ_SHIFT+DMAC_SREQ1_SHIFT) +# define DMAC_SREQ_SSREQ2 (1 << (DMAC_SREQ_SSREQ_SHIFT+DMAC_SREQ2_SHIFT) +# define DMAC_SREQ_SSREQ3 (1 << (DMAC_SREQ_SSREQ_SHIFT+DMAC_SREQ3_SHIFT) +#define DMAC_SREQ_DSREQ_SHIFT (1) /* Bits 1, 3, 5, 7: Request a destination single transfer */ +# define DMAC_SREQ_DSREQ(n) (1 << (DMAC_SREQ_DSREQ_SHIFT+DMAC_SREQ_SHIFT(n)))) +# define DMAC_SREQ_DSREQ0 (1 << (DMAC_SREQ_DSREQ_SHIFT+DMAC_SREQ0_SHIFT) +# define DMAC_SREQ_DSREQ1 (1 << (DMAC_SREQ_DSREQ_SHIFT+DMAC_SREQ1_SHIFT) +# define DMAC_SREQ_DSREQ2 (1 << (DMAC_SREQ_DSREQ_SHIFT+DMAC_SREQ2_SHIFT) +# define DMAC_SREQ_DSREQ3 (1 << (DMAC_SREQ_DSREQ_SHIFT+DMAC_SREQ3_SHIFT) + +/* DMAC Software Chunk Transfer Request Register */ + +#define DMAC_CREQ_SHIFT(n) ((n)<<1) +#define DMAC_CREQ_MASK(n) (3 << DMAC_CREQ_SHIFT(n)) +#define DMAC_CREQ0_SHIFT (0) /* Bits 0-1: Channel 0 */ +#define DMAC_CREQ0_MASK (3 << DMAC_CREQ0_SHIFT) +#define DMAC_CREQ1_SHIFT (2) /* Bits 2-3: Channel 1 */ +#define DMAC_CREQ1_MASK (3 << DMAC_CREQ1_SHIFT) +#define DMAC_CREQ2_SHIFT (4) /* Bits 4-5: Channel 2 */ +#define DMAC_CREQ2_MASK (3 << DMAC_CREQ2_SHIFT) +#define DMAC_CREQ3_SHIFT (6) /* Bits 6-7: Channel 3 */ +#define DMAC_CREQ3_MASK (3 << DMAC_CREQ3_SHIFT) + +#define DMAC_CREQ_SCREQ_SHIFT (0) /* Bits 0, 2, 4, 6: Request a source chunk transfer */ +# define DMAC_CREQ_SCREQ(n) (1 << (DMAC_CREQ_SCREQ_SHIFT+DMAC_CREQ_SHIFT(n))) +# define DMAC_CREQ_SCREQ0 (1 << (DMAC_CREQ_SCREQ_SHIFT+DMAC_CREQ0_SHIFT) +# define DMAC_CREQ_SCREQ1 (1 << (DMAC_CREQ_SCREQ_SHIFT+DMAC_CREQ1_SHIFT) +# define DMAC_CREQ_SCREQ2 (1 << (DMAC_CREQ_SCREQ_SHIFT+DMAC_CREQ2_SHIFT) +# define DMAC_CREQ_SCREQ3 (1 << (DMAC_CREQ_SCREQ_SHIFT+DMAC_CREQ3_SHIFT) +#define DMAC_CREQ_DCREQ_SHIFT (1) /* Bits 1, 3, 5, 7: Request a destination chunk transfer */ +# define DMAC_CREQ_DCREQ(n) (1 << (DMAC_CREQ_DCREQ_SHIFT+DMAC_CREQ_SHIFT(n)))) +# define DMAC_CREQ_DCREQ0 (1 << (DMAC_CREQ_DCREQ_SHIFT+DMAC_CREQ0_SHIFT) +# define DMAC_CREQ_DCREQ1 (1 << (DMAC_CREQ_DCREQ_SHIFT+DMAC_CREQ1_SHIFT) +# define DMAC_CREQ_DCREQ2 (1 << (DMAC_CREQ_DCREQ_SHIFT+DMAC_CREQ2_SHIFT) +# define DMAC_CREQ_DCREQ3 (1 << (DMAC_CREQ_DCREQ_SHIFT+DMAC_CREQ3_SHIFT) + +/* DMAC Software Last Transfer Flag Register */ + +#define DMAC_LAST_SHIFT(n) ((n)<<1) +#define DMAC_LAST_MASK(n) (3 << DMAC_LAST_SHIFT(n)) +#define DMAC_LAST0_SHIFT (0) /* Bits 0-1: Channel 0 */ +#define DMAC_LAST0_MASK (3 << DMAC_LAST0_SHIFT) +#define DMAC_LAST1_SHIFT (2) /* Bits 2-3: Channel 1 */ +#define DMAC_LAST1_MASK (3 << DMAC_LAST1_SHIFT) +#define DMAC_LAST2_SHIFT (4) /* Bits 4-5: Channel 2 */ +#define DMAC_LAST2_MASK (3 << DMAC_LAST2_SHIFT) +#define DMAC_LAST3_SHIFT (6) /* Bits 6-7: Channel 3 */ +#define DMAC_LAST3_MASK (3 << DMAC_LAST3_SHIFT) + +#define DMAC_LAST_SLAST_SHIFT (0) /* Bits 0, 2, 4, 6: Indicates the last transfer */ +# define DMAC_LAST_SLAST(n) (1 << (DMAC_LAST_SLAST_SHIFT+DMAC_LAST_SHIFT(n))) +# define DMAC_LAST_SLAST0 (1 << (DMAC_LAST_SLAST_SHIFT+DMAC_LAST0_SHIFT) +# define DMAC_LAST_SLAST1 (1 << (DMAC_LAST_SLAST_SHIFT+DMAC_LAST1_SHIFT) +# define DMAC_LAST_SLAST2 (1 << (DMAC_LAST_SLAST_SHIFT+DMAC_LAST2_SHIFT) +# define DMAC_LAST_SLAST3 (1 << (DMAC_LAST_SLAST_SHIFT+DMAC_LAST3_SHIFT) +#define DMAC_LAST_DLAST_SHIFT (1) /* Bits 1, 3, 5, 7: Indicates the last transfer */ +# define DMAC_LAST_DLAST(n) (1 << (DMAC_LAST_DLAST_SHIFT+DMAC_LAST_SHIFT(n)))) +# define DMAC_LAST_DLAST0 (1 << (DMAC_LAST_DLAST_SHIFT+DMAC_LAST0_SHIFT) +# define DMAC_LAST_DLAST1 (1 << (DMAC_LAST_DLAST_SHIFT+DMAC_LAST1_SHIFT) +# define DMAC_LAST_DLAST2 (1 << (DMAC_LAST_DLAST_SHIFT+DMAC_LAST2_SHIFT) +# define DMAC_LAST_DLAST3 (1 << (DMAC_LAST_DLAST_SHIFT+DMAC_LAST3_SHIFT) + +/* DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Enable Register, + * DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Disable Register, + * DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Mask Register, and + * DMAC Error, Buffer Transfer and Chained Buffer Transfer Status Register common + * bit field definitions + */ + +#define DMAC_EBC_BTC_SHIFT (0) /* Bits 0-3: Buffer Transfer Completed Interrupt Enable */ +#define DMAC_EBC_BTC_MASK (15 << DMAC_EBC_BTC_SHIFT) +# define DMAC_EBC_BTC(n) (1 << (DMAC_EBC_BTC_SHIFT+(n))) +# define DMAC_EBC_BTC0 (1 << (DMAC_EBC_BTC_SHIFT+0)) +# define DMAC_EBC_BTC1 (1 << (DMAC_EBC_BTC_SHIFT+1)) +# define DMAC_EBC_BTC2 (1 << (DMAC_EBC_BTC_SHIFT+2)) +# define DMAC_EBC_BTC3 (1 << (DMAC_EBC_BTC_SHIFT+3)) +#define DMAC_EBC_CBTC_SHIFT (8) /* Bits 8-11: Chained Buffer Transfer Completed Interrupt Enable */ +#define DMAC_EBC_CBTC_MASK (15 << DMAC_EBC_CBTC_SHIFT) +# define DMAC_EBC_CBTC(n) (1 << (DMAC_EBC_CBTC_SHIFT+(n))) +# define DMAC_EBC_CBTC0 (1 << (DMAC_EBC_CBTC_SHIFT+0)) +# define DMAC_EBC_CBTC1 (1 << (DMAC_EBC_CBTC_SHIFT+1)) +# define DMAC_EBC_CBTC2 (1 << (DMAC_EBC_CBTC_SHIFT+2)) +# define DMAC_EBC_CBTC3 (1 << (DMAC_EBC_CBTC_SHIFT+3)) +#define DMAC_EBC_ERR_SHIFT (16) /* Bits 16-19: Access Error Interrupt Enable */ +#define DMAC_EBC_ERR_MASK (15 << DMAC_EBC_ERR_SHIFT) +# define DMAC_EBC_ERR(n) (1 << (DMAC_EBC_ERR_SHIFT+(n))) +# define DMAC_EBC_ERR0 (1 << (DMAC_EBC_ERR_SHIFT+0)) +# define DMAC_EBC_ERR1 (1 << (DMAC_EBC_ERR_SHIFT+1)) +# define DMAC_EBC_ERR2 (1 << (DMAC_EBC_ERR_SHIFT+2)) +# define DMAC_EBC_ERR3 (1 << (DMAC_EBC_ERR_SHIFT+3)) + +#define DMAC_EBC_BTCINTS(n) (0x00010001 << (n)) /* BTC + ERR interrupts */ +#define DMAC_EBC_CBTCINTS(n) (0x00010100 << (n)) /* CBT + ERR interrupts */ +#define DMAC_EBC_CHANINTS(n) (0x00010101 << (n)) /* All channel interrupts */ +#define DMAC_EBC_ALLINTS (0x000f0f0f) /* All interrupts */ + +/* DMAC Channel Handler Enable Register */ + +#define DMAC_CHER_ENA_SHIFT (0) /* Bits 0-3: Enable channel */ +#define DMAC_CHER_ENA_MASK (15 << DMAC_CHER_ENA_SHIFT) +# define DMAC_CHER_ENA(n) (1 << (DMAC_CHER_ENA_SHIFT+(n))) +# define DMAC_CHER_ENA0 (1 << (DMAC_CHER_ENA_SHIFT+0)) +# define DMAC_CHER_ENA1 (1 << (DMAC_CHER_ENA_SHIFT+1)) +# define DMAC_CHER_ENA2 (1 << (DMAC_CHER_ENA_SHIFT+2)) +# define DMAC_CHER_ENA3 (1 << (DMAC_CHER_ENA_SHIFT+3)) +#define DMAC_CHER_SUSP_SHIFT (8) /* Bits 8-11: Freeze channel and its context */ +#define DMAC_CHER_SUSP_MASK (15 << DMAC_CHER_SUSP_SHIFT) +# define DMAC_CHER_SUSP(n) (1 << (DMAC_CHER_SUSP_SHIFT+(n))) +# define DMAC_CHER_SUSP0 (1 << (DMAC_CHER_SUSP_SHIFT+0)) +# define DMAC_CHER_SUSP1 (1 << (DMAC_CHER_SUSP_SHIFT+1)) +# define DMAC_CHER_SUSP2 (1 << (DMAC_CHER_SUSP_SHIFT+2)) +# define DMAC_CHER_SUSP3 (1 << (DMAC_CHER_SUSP_SHIFT+3)) +#define DMAC_CHER_KEEP_SHIFT (24) /* Bits 24-27: Resume channel from automatic stall */ +#define DMAC_CHER_KEEP_MASK (15 << DMAC_CHER_KEEP_SHIFT) +# define DMAC_CHER_KEEP(n) (1 << (DMAC_CHER_KEEP_SHIFT+(n))) +# define DMAC_CHER_KEEP0 (1 << (DMAC_CHER_KEEP_SHIFT+0)) +# define DMAC_CHER_KEEP1 (1 << (DMAC_CHER_KEEP_SHIFT+1)) +# define DMAC_CHER_KEEP2 (1 << (DMAC_CHER_KEEP_SHIFT+2)) +# define DMAC_CHER_KEEP3 (1 << (DMAC_CHER_KEEP_SHIFT+3)) + +/* DMAC Channel Handler Disable Register */ + +#define DMAC_CHDR_DIS_SHIFT (0) /* Bits 0-3: Disable DMAC channel */ +#define DMAC_CHDR_DIS_MASK (15 << DMAC_CHDR_DIS_SHIFT) +# define DMAC_CHDR_DIS(n) (1 << (DMAC_CHDR_DIS_SHIFT+(n))) +# define DMAC_CHDR_DIS0 (1 << (DMAC_CHDR_DIS_SHIFT+0)) +# define DMAC_CHDR_DIS1 (1 << (DMAC_CHDR_DIS_SHIFT+1)) +# define DMAC_CHDR_DIS2 (1 << (DMAC_CHDR_DIS_SHIFT+2)) +# define DMAC_CHDR_DIS3 (1 << (DMAC_CHDR_DIS_SHIFT+3)) +# define DMAC_CHDR_DIS_ALL DMAC_CHDR_DIS_MASK +#define DMAC_CHDR_RES_SHIFT (8) /* Bits 8-11: Resume trasnfer, restoring context */ +#define DMAC_CHDR_RES_MASK (15 << DMAC_CHDR_RES_SHIFT) +# define DMAC_CHDR_RES(n) (1 << (DMAC_CHDR_RES_SHIFT+(n))) +# define DMAC_CHDR_RES0 (1 << (DMAC_CHDR_RES_SHIFT+0)) +# define DMAC_CHDR_RES1 (1 << (DMAC_CHDR_RES_SHIFT+1)) +# define DMAC_CHDR_RES2 (1 << (DMAC_CHDR_RES_SHIFT+2)) +# define DMAC_CHDR_RES3 (1 << (DMAC_CHDR_RES_SHIFT+3)) + +/* DMAC Channel Handler Status Register */ + +#define DMAC_CHSR_ENA_SHIFT (0) /* Bits 0-3: Indicates that the channel is stalling */ +#define DMAC_CHSR_ENA_MASK (15 << DMAC_CHSR_ENA_SHIFT) +# define DMAC_CHSR_ENA(n) (1 << (DMAC_CHSR_ENA_SHIFT+(n))) +# define DMAC_CHSR_ENA0 (1 << (DMAC_CHSR_ENA_SHIFT+0)) +# define DMAC_CHSR_ENA1 (1 << (DMAC_CHSR_ENA_SHIFT+1)) +# define DMAC_CHSR_ENA2 (1 << (DMAC_CHSR_ENA_SHIFT+2)) +# define DMAC_CHSR_ENA3 (1 << (DMAC_CHSR_ENA_SHIFT+3)) +#define DMAC_CHSR_SUSP_SHIFT (8) /* Bits 8-11: Indicates that the channel is empty */ +#define DMAC_CHSR_SUSP_MASK (15 << DMAC_CHSR_SUSP_SHIFT) +# define DMAC_CHSR_SUSP(n) (1 << (DMAC_CHSR_SUSP_SHIFT+(n))) +# define DMAC_CHSR_SUSP0 (1 << (DMAC_CHSR_SUSP_SHIFT+0)) +# define DMAC_CHSR_SUSP1 (1 << (DMAC_CHSR_SUSP_SHIFT+1)) +# define DMAC_CHSR_SUSP2 (1 << (DMAC_CHSR_SUSP_SHIFT+2)) +# define DMAC_CHSR_SUSP3 (1 << (DMAC_CHSR_SUSP_SHIFT+3)) +#define DMAC_CHSR_EMPT_SHIFT (16) /* Bits 16-19: Access Error Interrupt Enable */ +#define DMAC_CHSR_EMPT_MASK (15 << DMAC_CHSR_EMPT_SHIFT) +# define DMAC_CHSR_EMPT(n) (1 << (DMAC_CHSR_EMPT_SHIFT+(n))) +# define DMAC_CHSR_EMPT0 (1 << (DMAC_CHSR_EMPT_SHIFT+0)) +# define DMAC_CHSR_EMPT1 (1 << (DMAC_CHSR_EMPT_SHIFT+1)) +# define DMAC_CHSR_EMPT2 (1 << (DMAC_CHSR_EMPT_SHIFT+2)) +# define DMAC_CHSR_EMPT3 (1 << (DMAC_CHSR_EMPT_SHIFT+3)) +#define DMAC_CHSR_STAL_SHIFT (24) /* Bits 24-27: Access Error Interrupt Enable */ +#define DMAC_CHSR_STAL_MASK (15 << DMAC_CHSR_STAL_SHIFT) +# define DMAC_CHSR_STAL(n) (1 << (DMAC_CHSR_STAL_SHIFT+(n))) +# define DMAC_CHSR_STAL0 (1 << (DMAC_CHSR_STAL_SHIFT+0)) +# define DMAC_CHSR_STAL1 (1 << (DMAC_CHSR_STAL_SHIFT+1)) +# define DMAC_CHSR_STAL2 (1 << (DMAC_CHSR_STAL_SHIFT+2)) +# define DMAC_CHSR_STAL3 (1 << (DMAC_CHSR_STAL_SHIFT+3)) + +/* DMA channel registers */ +/* DMAC Channel n [n = 0..3] Control A Register */ + +#define DMACHAN_CTRLA_BTSIZE_MAX (0xfff) +#define DMACHAN_CTRLA_BTSIZE_SHIFT (0) /* Bits 0-11: Buffer Transfer Size */ +#define DMACHAN_CTRLA_BTSIZE_MASK (DMACHAN_CTRLA_BTSIZE_MAX << DMACHAN_CTRLA_BTSIZE_SHIFT) +#define DMACHAN_CTRLA_SCSIZE (1 << 16) /* Bit 16: Source Chunk Transfer Size */ +# define DMACHAN_CTRLA_SCSIZE_1 (0) +# define DMACHAN_CTRLA_SCSIZE_4 DMACHAN_CTRLA_SCSIZE +#define DMACHAN_CTRLA_DCSIZE (1 << 20) /* Bit 20: Destination Chunk Transfer size */ +# define DMACHAN_CTRLA_DCSIZE_1 (0) +# define DMACHAN_CTRLA_DCSIZE_4 DMACHAN_CTRLA_DCSIZE +#define DMACHAN_CTRLA_SRCWIDTH_SHIFT (24) /* Bits 24-25 */ +#define DMACHAN_CTRLA_SRCWIDTH_MASK (3 << DMACHAN_CTRLA_SRCWIDTH_SHIFT) +# define DMACHAN_CTRLA_SRCWIDTH_BYTE (0 << DMACHAN_CTRLA_SRCWIDTH_SHIFT) +# define DMACHAN_CTRLA_SRCWIDTH_HWORD (1 << DMACHAN_CTRLA_SRCWIDTH_SHIFT) +# define DMACHAN_CTRLA_SRCWIDTH_WORD (2 << DMACHAN_CTRLA_SRCWIDTH_SHIFT) +#define DMACHAN_CTRLA_DSTWIDTH_SHIFT (28) /* Bits 28-29 */ +#define DMACHAN_CTRLA_DSTWIDTH_MASK (3 << DMACHAN_CTRLA_DSTWIDTH_SHIFT) +# define DMACHAN_CTRLA_DSTWIDTH_BYTE (0 << DMACHAN_CTRLA_DSTWIDTH_SHIFT) +# define DMACHAN_CTRLA_DSTWIDTH_HWORD (1 << DMACHAN_CTRLA_DSTWIDTH_SHIFT) +# define DMACHAN_CTRLA_DSTWIDTH_WORD (2 << DMACHAN_CTRLA_DSTWIDTH_SHIFT) +#define DMACHAN_CTRLA_DONE (1 << 31) /* Bit 31: Auto disable DMAC */ + +/* DMAC Channel n [n = 0..3] Control B Register */ + +#define DMACHAN_CTRLB_SRCDSCR (1 << 16) /* Bit 16: Source buffer descriptor fetch operation disabled */ +#define DMACHAN_CTRLB_DSTDSCR (1 << 20) /* Bit 20: Dest buffer descriptor fetch operation disabled */ +#define DMACHAN_CTRLB_FC_SHIFT (21) /* Bits 21-22: Flow controller */ +#define DMACHAN_CTRLB_FC_MASK (3 << DMACHAN_CTRLB_FC_SHIFT) +# define DMACHAN_CTRLB_FC_M2M (0 << DMACHAN_CTRLB_FC_SHIFT) /* Memory-to-Memory */ +# define DMACHAN_CTRLB_FC_M2P (1 << DMACHAN_CTRLB_FC_SHIFT) /* Memory-to-Peripheral */ +# define DMACHAN_CTRLB_FC_P2M (2 << DMACHAN_CTRLB_FC_SHIFT) /* Peripheral-to-Memory */ +# define DMACHAN_CTRLB_FC_P2P (3 << DMACHAN_CTRLB_FC_SHIFT) /* Peripheral-to-Peripheral */ +#define DMACHAN_CTRLB_SRCINCR_SHIFT (24) /* Bits 24-25 */ +#define DMACHAN_CTRLB_SRCINCR_MASK (3 << DMACHAN_CTRLB_SRCINCR_SHIFT) +# define DMACHAN_CTRLB_SRCINCR_INCR (0 << DMACHAN_CTRLB_SRCINCR_SHIFT) /* Incrementing address */ +# define DMACHAN_CTRLB_SRCINCR_FIXED (2 << DMACHAN_CTRLB_SRCINCR_SHIFT) /* Fixed address */ +#define DMACHAN_CTRLB_DSTINCR_SHIFT (28) /* Bits 28-29 */ +#define DMACHAN_CTRLB_DSTINCR_MASK (3 << DMACHAN_CTRLB_DSTINCR_SHIFT) +# define DMACHAN_CTRLB_DSTINCR_INCR (0 << DMACHAN_CTRLB_DSTINCR_SHIFT) /* Incrementing address */ +# define DMACHAN_CTRLB_DSTINCR_FIXED (2 << DMACHAN_CTRLB_DSTINCR_SHIFT) /* Fixed address */ +#define DMACHAN_CTRLB_IEN (1 << 30) /* Bit 30: Clear sets BTC[n] flag in EBCISR */ + +/* DMAC Channel n [n = 0..3] Configuration Register */ + +#define DMACHAN_CFG_SRCPER_SHIFT (0) /* Bits 0-3: Channel source associated with peripheral ID */ +#define DMACHAN_CFG_SRCPER_MASK (15 << DMACHAN_CFG_SRCPER_SHIFT) +#define DMACHAN_CFG_DSTPER_SHIFT (4) /* Bits 4-7: Channel dest associated with peripheral ID */ +#define DMACHAN_CFG_DSTPER_MASK (15 << DMACHAN_CFG_DSTPER_SHIFT) +#define DMACHAN_CFG_SRCH2SEL (1 << 9) /* Bit 9: HW handshake triggers transfer */ +#define DMACHAN_CFG_DSTH2SEL (1 << 13) /* Bit 13: HW handshake trigger transfer */ +#define DMACHAN_CFG_SOD (1 << 16) /* Bit 16: Stop on done */ +#define DMACHAN_CFG_LOCKIF (1 << 20) /* Bit 20: Enable lock interface capability */ +#define DMACHAN_CFG_LOCKB (1 << 21) /* Bit 21: Enable AHB Bus Locking capability */ +#define DMACHAN_CFG_LOCKIFL (1 << 22) /* Bit 22: Lock Master Interface Arbiter */ +#define DMACHAN_CFG_AHBPRO_SHIFT (24) /* Bits 24-26: Bus access privilege */ +#define DMACHAN_CFG_AHBPRO_MASK (7 << DMACHAN_CFG_AHBPRO_SHIFT) +# define DMACHAN_CFG_AHBPRO_PRIV (1 << DMACHAN_CFG_AHBPRO_SHIFT) +# define DMACHAN_CFG_AHBPRO_BUFF (2 << DMACHAN_CFG_AHBPRO_SHIFT) +# define DMACHAN_CFG_AHBPRO_CACHE (4 << DMACHAN_CFG_AHBPRO_SHIFT) +#define DMACHAN_CFG_FIFOCFG_SHIFT (28) /* Bits 28-29 */ +#define DMACHAN_CFG_FIFOCFG_MASK (3 << DMACHAN_CFG_FIFOCFG_SHIFT) +# define DMACHAN_CFG_FIFOCFG_LARGEST (0 << DMACHAN_CFG_FIFOCFG_SHIFT) /* Largest length AHB burst */ +# define DMACHAN_CFG_FIFOCFG_HALF (1 << DMACHAN_CFG_FIFOCFG_SHIFT) /* Half FIFO size */ +# define DMACHAN_CFG_FIFOCFG_SINGLE (2 << DMACHAN_CFG_FIFOCFG_SHIFT) /* Single AHB access */ + +/* DMA Peripheral IDs *******************************************************************/ + +#define DMACHAN_PID_MCI0 0 +#define DMACHAN_PID_SSC 3 +#define DMACHAN_PID_MCI1 13 + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +/* DMA multi buffer transfer link list entry structure */ + +struct dma_linklist_s +{ + uint32_t src; /* Source address */ + uint32_t dest; /* Destination address */ + uint32_t ctrla; /* Control A value */ + uint32_t ctrlb; /* Control B value */ + uint32_t next; /* Next descriptor address */ +}; + +/**************************************************************************************** + * Public Data + ****************************************************************************************/ + +/**************************************************************************************** + * Public Functions + ****************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_DMAC_H */ diff --git a/nuttx/arch/arm/src/sam3u/sam3u_eefc.h b/nuttx/arch/arm/src/sam3u/sam3u_eefc.h index ed88a0134..d32c6670b 100644 --- a/nuttx/arch/arm/src/sam3u/sam3u_eefc.h +++ b/nuttx/arch/arm/src/sam3u/sam3u_eefc.h @@ -1,120 +1,120 @@ -/****************************************************************************************
- * arch/arm/src/sam3u/sam3u_eefc.h
- *
- * Copyright (C) 2009 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_EEFC_H
-#define __ARCH_ARM_SRC_SAM3U_SAM3U_EEFC_H
-
-/****************************************************************************************
- * Included Files
- ****************************************************************************************/
-
-#include <nuttx/config.h>
-
-#include "chip.h"
-#include "sam3u_memorymap.h"
-
-/****************************************************************************************
- * Pre-processor Definitions
- ****************************************************************************************/
-
-/* EEFC register offsets ****************************************************************/
-
-#define SAM3U_EEFC_FMR_OFFSET 0x00 /* EEFC Flash Mode Register */
-#define SAM3U_EEFC_FCR_OFFSET 0x04 /* EEFC Flash Command Register */
-#define SAM3U_EEFC_FSR_OFFSET 0x08 /* EEFC Flash Status Register */
-#define SAM3U_EEFC_FRR_OFFSET 0x0c /* EEFC Flash Result Register */
-
-/* EEFC register adresses ***************************************************************/
-
-#define SAM3U_EEFC_FMR(n) (SAM3U_EEFCN_BASE(n)+SAM3U_EEFC_FMR_OFFSET)
-#define SAM3U_EEFC_FCR(n) (SAM3U_EEFCN_BASE(n)+SAM3U_EEFC_FCR_OFFSET)
-#define SAM3U_EEFC_FSR(n) (SAM3U_EEFCN_BASE(n)+SAM3U_EEFC_FSR_OFFSET)
-#define SAM3U_EEFC_FRR(n) (SAM3U_EEFCN_BASE(n)+SAM3U_EEFC_FRR_OFFSET)
-
-#define SAM3U_EEFC0_FMR (SAM3U_EEFC0_BASE+SAM3U_EEFC_FMR_OFFSET)
-#define SAM3U_EEFC0_FCR (SAM3U_EEFC0_BASE+SAM3U_EEFC_FCR_OFFSET)
-#define SAM3U_EEFC0_FSR (SAM3U_EEFC0_BASE+SAM3U_EEFC_FSR_OFFSET)
-#define SAM3U_EEFC0_FRR (SAM3U_EEFC0_BASE+SAM3U_EEFC_FRR_OFFSET)
-
-#define SAM3U_EEFC1_FMR (SAM3U_EEFC1_BASE+SAM3U_EEFC_FMR_OFFSET)
-#define SAM3U_EEFC1_FCR (SAM3U_EEFC1_BASE+SAM3U_EEFC_FCR_OFFSET)
-#define SAM3U_EEFC1_FSR (SAM3U_EEFC1_BASE+SAM3U_EEFC_FSR_OFFSET)
-#define SAM3U_EEFC1_FRR (SAM3U_EEFC1_BASE+SAM3U_EEFC_FRR_OFFSET)
-
-/* EEFC register bit definitions ********************************************************/
-
-#define EEFC_FMR_FRDY (1 << 0) /* Bit 0: Ready Interrupt Enable */
-#define EEFC_FMR_FWS_SHIFT (8) /* Bits 8-11: Flash Wait State */
-#define EEFC_FMR_FWS_MASK (15 << EEFC_FMR_FWS_SHIFT)
-#define EEFC_FMR_FAM (1 << 24) /* Bit 24: Flash Access Mode */
-
-#define EEFC_FCR_FCMD_SHIFT (0) /* Bits 0-7: Flash Command */
-#define EEFC_FCR_FCMD_MASK (0xff << EEFC_FCR_FCMD_SHIFT)
-# define EEFC_FCR_FCMD_GETD (0 << EEFC_FCR_FCMD_SHIFT) /* Get Flash Descriptor */
-# define EEFC_FCR_FCMD_WP (1 << EEFC_FCR_FCMD_SHIFT) /* Write page */
-# define EEFC_FCR_FCMD_WPL (2 << EEFC_FCR_FCMD_SHIFT) /* Write page and lock */
-# define EEFC_FCR_FCMD_EWP (3 << EEFC_FCR_FCMD_SHIFT) /* Erase page and write page */
-# define EEFC_FCR_FCMD_EWPL (4 << EEFC_FCR_FCMD_SHIFT) /* Erase page and write page then lock */
-# define EEFC_FCR_FCMD_EA (5 << EEFC_FCR_FCMD_SHIFT) /* Erase all */
-# define EEFC_FCR_FCMD_SLB (8 << EEFC_FCR_FCMD_SHIFT) /* Set Lock Bit */
-# define EEFC_FCR_FCMD_CLB (9 << EEFC_FCR_FCMD_SHIFT) /* Clear Lock Bit */
-# define EEFC_FCR_FCMD_GLB (10 << EEFC_FCR_FCMD_SHIFT) /* Get Lock Bit */
-# define EEFC_FCR_FCMD_SGPB (11 << EEFC_FCR_FCMD_SHIFT) /* Set GPNVM Bit */
-# define EEFC_FCR_FCMD_CGPB (12 << EEFC_FCR_FCMD_SHIFT) /* Clear GPNVM Bit */
-# define EEFC_FCR_FCMD_GGPB (13 << EEFC_FCR_FCMD_SHIFT) /* Get GPNVM Bit */
-# define EEFC_FCR_FCMD_STUI (14 << EEFC_FCR_FCMD_SHIFT) /* Start Read Unique Identifier */
-# define EEFC_FCR_FCMD_SPUI (15 << EEFC_FCR_FCMD_SHIFT) /* Stop Read Unique Identifier */
-#define EEFC_FCR_FARG_SHIFT (8) /* Bits 8-23: Flash Command Argument */
-#define EEFC_FCR_FARG_MASK (0xffff << EEFC_FCR_FARG_SHIFT)
-#define EEFC_FCR_FKEY_SHIFT (24) /* Bits 24-31: Flash Writing Protection Key */
-#define EEFC_FCR_FKEY__MASK (0xff << EEFC_FCR_FKEY_SHIFT)
-
-#define EEFC_FSR_FRDY (1 << 0) /* Bit 0: Flash Ready Status */
-#define EEFC_FSR_FCMDE (1 << 1) /* Bit 1: Flash Command Error Status */
-#define EEFC_FSR_FLOCKE (1 << 2) /* Bit 2: Flash Lock Error Status */
-
-/****************************************************************************************
- * Public Types
- ****************************************************************************************/
-
-/****************************************************************************************
- * Public Data
- ****************************************************************************************/
-
-/****************************************************************************************
- * Public Functions
- ****************************************************************************************/
-
-#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_EEFC_H */
+/**************************************************************************************** + * arch/arm/src/sam3u/sam3u_eefc.h + * + * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_EEFC_H +#define __ARCH_ARM_SRC_SAM3U_SAM3U_EEFC_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +#include <nuttx/config.h> + +#include "chip.h" +#include "sam3u_memorymap.h" + +/**************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************/ + +/* EEFC register offsets ****************************************************************/ + +#define SAM3U_EEFC_FMR_OFFSET 0x00 /* EEFC Flash Mode Register */ +#define SAM3U_EEFC_FCR_OFFSET 0x04 /* EEFC Flash Command Register */ +#define SAM3U_EEFC_FSR_OFFSET 0x08 /* EEFC Flash Status Register */ +#define SAM3U_EEFC_FRR_OFFSET 0x0c /* EEFC Flash Result Register */ + +/* EEFC register adresses ***************************************************************/ + +#define SAM3U_EEFC_FMR(n) (SAM3U_EEFCN_BASE(n)+SAM3U_EEFC_FMR_OFFSET) +#define SAM3U_EEFC_FCR(n) (SAM3U_EEFCN_BASE(n)+SAM3U_EEFC_FCR_OFFSET) +#define SAM3U_EEFC_FSR(n) (SAM3U_EEFCN_BASE(n)+SAM3U_EEFC_FSR_OFFSET) +#define SAM3U_EEFC_FRR(n) (SAM3U_EEFCN_BASE(n)+SAM3U_EEFC_FRR_OFFSET) + +#define SAM3U_EEFC0_FMR (SAM3U_EEFC0_BASE+SAM3U_EEFC_FMR_OFFSET) +#define SAM3U_EEFC0_FCR (SAM3U_EEFC0_BASE+SAM3U_EEFC_FCR_OFFSET) +#define SAM3U_EEFC0_FSR (SAM3U_EEFC0_BASE+SAM3U_EEFC_FSR_OFFSET) +#define SAM3U_EEFC0_FRR (SAM3U_EEFC0_BASE+SAM3U_EEFC_FRR_OFFSET) + +#define SAM3U_EEFC1_FMR (SAM3U_EEFC1_BASE+SAM3U_EEFC_FMR_OFFSET) +#define SAM3U_EEFC1_FCR (SAM3U_EEFC1_BASE+SAM3U_EEFC_FCR_OFFSET) +#define SAM3U_EEFC1_FSR (SAM3U_EEFC1_BASE+SAM3U_EEFC_FSR_OFFSET) +#define SAM3U_EEFC1_FRR (SAM3U_EEFC1_BASE+SAM3U_EEFC_FRR_OFFSET) + +/* EEFC register bit definitions ********************************************************/ + +#define EEFC_FMR_FRDY (1 << 0) /* Bit 0: Ready Interrupt Enable */ +#define EEFC_FMR_FWS_SHIFT (8) /* Bits 8-11: Flash Wait State */ +#define EEFC_FMR_FWS_MASK (15 << EEFC_FMR_FWS_SHIFT) +#define EEFC_FMR_FAM (1 << 24) /* Bit 24: Flash Access Mode */ + +#define EEFC_FCR_FCMD_SHIFT (0) /* Bits 0-7: Flash Command */ +#define EEFC_FCR_FCMD_MASK (0xff << EEFC_FCR_FCMD_SHIFT) +# define EEFC_FCR_FCMD_GETD (0 << EEFC_FCR_FCMD_SHIFT) /* Get Flash Descriptor */ +# define EEFC_FCR_FCMD_WP (1 << EEFC_FCR_FCMD_SHIFT) /* Write page */ +# define EEFC_FCR_FCMD_WPL (2 << EEFC_FCR_FCMD_SHIFT) /* Write page and lock */ +# define EEFC_FCR_FCMD_EWP (3 << EEFC_FCR_FCMD_SHIFT) /* Erase page and write page */ +# define EEFC_FCR_FCMD_EWPL (4 << EEFC_FCR_FCMD_SHIFT) /* Erase page and write page then lock */ +# define EEFC_FCR_FCMD_EA (5 << EEFC_FCR_FCMD_SHIFT) /* Erase all */ +# define EEFC_FCR_FCMD_SLB (8 << EEFC_FCR_FCMD_SHIFT) /* Set Lock Bit */ +# define EEFC_FCR_FCMD_CLB (9 << EEFC_FCR_FCMD_SHIFT) /* Clear Lock Bit */ +# define EEFC_FCR_FCMD_GLB (10 << EEFC_FCR_FCMD_SHIFT) /* Get Lock Bit */ +# define EEFC_FCR_FCMD_SGPB (11 << EEFC_FCR_FCMD_SHIFT) /* Set GPNVM Bit */ +# define EEFC_FCR_FCMD_CGPB (12 << EEFC_FCR_FCMD_SHIFT) /* Clear GPNVM Bit */ +# define EEFC_FCR_FCMD_GGPB (13 << EEFC_FCR_FCMD_SHIFT) /* Get GPNVM Bit */ +# define EEFC_FCR_FCMD_STUI (14 << EEFC_FCR_FCMD_SHIFT) /* Start Read Unique Identifier */ +# define EEFC_FCR_FCMD_SPUI (15 << EEFC_FCR_FCMD_SHIFT) /* Stop Read Unique Identifier */ +#define EEFC_FCR_FARG_SHIFT (8) /* Bits 8-23: Flash Command Argument */ +#define EEFC_FCR_FARG_MASK (0xffff << EEFC_FCR_FARG_SHIFT) +#define EEFC_FCR_FKEY_SHIFT (24) /* Bits 24-31: Flash Writing Protection Key */ +#define EEFC_FCR_FKEY__MASK (0xff << EEFC_FCR_FKEY_SHIFT) + +#define EEFC_FSR_FRDY (1 << 0) /* Bit 0: Flash Ready Status */ +#define EEFC_FSR_FCMDE (1 << 1) /* Bit 1: Flash Command Error Status */ +#define EEFC_FSR_FLOCKE (1 << 2) /* Bit 2: Flash Lock Error Status */ + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +/**************************************************************************************** + * Public Data + ****************************************************************************************/ + +/**************************************************************************************** + * Public Functions + ****************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_EEFC_H */ diff --git a/nuttx/arch/arm/src/sam3u/sam3u_gpbr.h b/nuttx/arch/arm/src/sam3u/sam3u_gpbr.h index e3ac0c128..7e9853180 100644 --- a/nuttx/arch/arm/src/sam3u/sam3u_gpbr.h +++ b/nuttx/arch/arm/src/sam3u/sam3u_gpbr.h @@ -1,90 +1,90 @@ -/****************************************************************************************
- * arch/arm/src/sam3u/sam3u_gpbr.h
- *
- * Copyright (C) 2009 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_GPBR_H
-#define __ARCH_ARM_SRC_SAM3U_SAM3U_GPBR_H
-
-/****************************************************************************************
- * Included Files
- ****************************************************************************************/
-
-#include <nuttx/config.h>
-
-#include "chip.h"
-#include "sam3u_memorymap.h"
-
-/****************************************************************************************
- * Pre-processor Definitions
- ****************************************************************************************/
-
-/* GPBR register offsets ****************************************************************/
-
-#define SAM3U_GPBR_OFFSET(n) ((n)<<2) /* General purpose back-up registers */
-#define SAM3U_GPBR0_OFFSET 0x00
-#define SAM3U_GPBR1_OFFSET 0x04
-#define SAM3U_GPBR2_OFFSET 0x08
-#define SAM3U_GPBR3_OFFSET 0x0c
-#define SAM3U_GPBR4_OFFSET 0x10
-#define SAM3U_GPBR5_OFFSET 0x14
-#define SAM3U_GPBR6_OFFSET 0x18
-#define SAM3U_GPBR7_OFFSET 0x1c
-
-/* GPBR register adresses ***************************************************************/
-
-#define SAM3U_GPBR(n)) (SAM3U_GPBR_BASE+SAM3U_GPBR_OFFSET(n))
-#define SAM3U_GPBR0 (SAM3U_GPBR_BASE+SAM3U_GPBR0_OFFSET)
-#define SAM3U_GPBR1 (SAM3U_GPBR_BASE+SAM3U_GPBR1_OFFSET)
-#define SAM3U_GPBR2 (SAM3U_GPBR_BASE+SAM3U_GPBR2_OFFSET)
-#define SAM3U_GPBR3 (SAM3U_GPBR_BASE+SAM3U_GPBR3_OFFSET)
-#define SAM3U_GPBR4 (SAM3U_GPBR_BASE+SAM3U_GPBR4_OFFSET)
-#define SAM3U_GPBR5 (SAM3U_GPBR_BASE+SAM3U_GPBR5_OFFSET)
-#define SAM3U_GPBR6 (SAM3U_GPBR_BASE+SAM3U_GPBR6_OFFSET)
-#define SAM3U_GPBR7 (SAM3U_GPBR_BASE+SAM3U_GPBR7_OFFSET)
-
-/* GPBR register bit definitions ********************************************************/
-
-/****************************************************************************************
- * Public Types
- ****************************************************************************************/
-
-/****************************************************************************************
- * Public Data
- ****************************************************************************************/
-
-/****************************************************************************************
- * Public Functions
- ****************************************************************************************/
-
-#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_GPBR_H */
+/**************************************************************************************** + * arch/arm/src/sam3u/sam3u_gpbr.h + * + * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_GPBR_H +#define __ARCH_ARM_SRC_SAM3U_SAM3U_GPBR_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +#include <nuttx/config.h> + +#include "chip.h" +#include "sam3u_memorymap.h" + +/**************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************/ + +/* GPBR register offsets ****************************************************************/ + +#define SAM3U_GPBR_OFFSET(n) ((n)<<2) /* General purpose back-up registers */ +#define SAM3U_GPBR0_OFFSET 0x00 +#define SAM3U_GPBR1_OFFSET 0x04 +#define SAM3U_GPBR2_OFFSET 0x08 +#define SAM3U_GPBR3_OFFSET 0x0c +#define SAM3U_GPBR4_OFFSET 0x10 +#define SAM3U_GPBR5_OFFSET 0x14 +#define SAM3U_GPBR6_OFFSET 0x18 +#define SAM3U_GPBR7_OFFSET 0x1c + +/* GPBR register adresses ***************************************************************/ + +#define SAM3U_GPBR(n)) (SAM3U_GPBR_BASE+SAM3U_GPBR_OFFSET(n)) +#define SAM3U_GPBR0 (SAM3U_GPBR_BASE+SAM3U_GPBR0_OFFSET) +#define SAM3U_GPBR1 (SAM3U_GPBR_BASE+SAM3U_GPBR1_OFFSET) +#define SAM3U_GPBR2 (SAM3U_GPBR_BASE+SAM3U_GPBR2_OFFSET) +#define SAM3U_GPBR3 (SAM3U_GPBR_BASE+SAM3U_GPBR3_OFFSET) +#define SAM3U_GPBR4 (SAM3U_GPBR_BASE+SAM3U_GPBR4_OFFSET) +#define SAM3U_GPBR5 (SAM3U_GPBR_BASE+SAM3U_GPBR5_OFFSET) +#define SAM3U_GPBR6 (SAM3U_GPBR_BASE+SAM3U_GPBR6_OFFSET) +#define SAM3U_GPBR7 (SAM3U_GPBR_BASE+SAM3U_GPBR7_OFFSET) + +/* GPBR register bit definitions ********************************************************/ + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +/**************************************************************************************** + * Public Data + ****************************************************************************************/ + +/**************************************************************************************** + * Public Functions + ****************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_GPBR_H */ diff --git a/nuttx/arch/arm/src/sam3u/sam3u_gpioirq.c b/nuttx/arch/arm/src/sam3u/sam3u_gpioirq.c index bcc597b86..dc01374a9 100644 --- a/nuttx/arch/arm/src/sam3u/sam3u_gpioirq.c +++ b/nuttx/arch/arm/src/sam3u/sam3u_gpioirq.c @@ -3,7 +3,7 @@ * arch/arm/src/chip/sam3u_gpioirq.c * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/sam3u/sam3u_hsmci.h b/nuttx/arch/arm/src/sam3u/sam3u_hsmci.h index 3923adf5a..1667789a6 100644 --- a/nuttx/arch/arm/src/sam3u/sam3u_hsmci.h +++ b/nuttx/arch/arm/src/sam3u/sam3u_hsmci.h @@ -1,297 +1,297 @@ -/****************************************************************************************
- * arch/arm/src/sam3u/sam3u_hsmci.h
- *
- * Copyright (C) 2009 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_HSMCI_H
-#define __ARCH_ARM_SRC_SAM3U_SAM3U_HSMCI_H
-
-/****************************************************************************************
- * Included Files
- ****************************************************************************************/
-
-#include <nuttx/config.h>
-
-#include "chip.h"
-#include "sam3u_memorymap.h"
-
-/****************************************************************************************
- * Pre-processor Definitions
- ****************************************************************************************/
-
-/* HSMCI register offsets ***************************************************************/
-
-#define SAM3U_HSMCI_CR_OFFSET 0x0000 /* Control Register */
-#define SAM3U_HSMCI_MR_OFFSET 0x0004 /* Mode Register */
-#define SAM3U_HSMCI_DTOR_OFFSET 0x0008 /* Data Timeout Register */
-#define SAM3U_HSMCI_SDCR_OFFSET 0x000c /* SD/SDIO Card Register */
-#define SAM3U_HSMCI_ARGR_OFFSET 0x0010 /* Argument Register */
-#define SAM3U_HSMCI_CMDR_OFFSET 0x0014 /* Command Register */
-#define SAM3U_HSMCI_BLKR_OFFSET 0x0018 /* Block Register */
-#define SAM3U_HSMCI_CSTOR_OFFSET 0x001c /* Completion Signal Timeout Register */
-#define SAM3U_HSMCI_RSPR0_OFFSET 0x0020 /* Response Register 0 */
-#define SAM3U_HSMCI_RSPR1_OFFSET 0x0024 /* Response Register 1 */
-#define SAM3U_HSMCI_RSPR2_OFFSET 0x0028 /* Response Register 2 */
-#define SAM3U_HSMCI_RSPR3_OFFSET 0x002c /* Response Register 3 */
-#define SAM3U_HSMCI_RDR_OFFSET 0x0030 /* Receive Data Register */
-#define SAM3U_HSMCI_TDR_OFFSET 0x0034 /* Transmit Data Register */
- /* 0x0038-0x003c: Reserved */
-#define SAM3U_HSMCI_SR_OFFSET 0x0040 /* Status Register */
-#define SAM3U_HSMCI_IER_OFFSET 0x0044 /* Interrupt Enable Register */
-#define SAM3U_HSMCI_IDR_OFFSET 0x0048 /* Interrupt Disable Register */
-#define SAM3U_HSMCI_IMR_OFFSET 0x004c /* Interrupt Mask Register */
-#define SAM3U_HSMCI_DMA_OFFSET 0x0050 /* DMA Configuration Register */
-#define SAM3U_HSMCI_CFG_OFFSET 0x0054 /* Configuration Register */
- /* 0x0058-0x00e0: Reserved */
-#define SAM3U_HSMCI_WPMR_OFFSET 0x00e4 /* Write Protection Mode Register */
-#define SAM3U_HSMCI_WPSR_OFFSET 0x00e8 /* Write Protection Status Register */
- /* 0x00ec-0x00fc: Reserved */
- /* 0x0100-0x0124: Reserved */
-#define SAM3U_HSMCI_FIFO_OFFSET 0x0200 /* 0x0200-0x3ffc FIFO Memory Aperture */
-
-/* HSMCI register adresses **************************************************************/
-
-#define SAM3U_HSMCI_CR (SAM3U_MCI_BASE+SAM3U_HSMCI_CR_OFFSET)
-#define SAM3U_HSMCI_MR (SAM3U_MCI_BASE+SAM3U_HSMCI_MR_OFFSET)
-#define SAM3U_HSMCI_DTOR (SAM3U_MCI_BASE+SAM3U_HSMCI_DTOR_OFFSET)
-#define SAM3U_HSMCI_SDCR (SAM3U_MCI_BASE+SAM3U_HSMCI_SDCR_OFFSET)
-#define SAM3U_HSMCI_ARGR (SAM3U_MCI_BASE+SAM3U_HSMCI_ARGR_OFFSET)
-#define SAM3U_HSMCI_CMDR (SAM3U_MCI_BASE+SAM3U_HSMCI_CMDR_OFFSET)
-#define SAM3U_HSMCI_BLKR (SAM3U_MCI_BASE+SAM3U_HSMCI_BLKR_OFFSET)
-#define SAM3U_HSMCI_CSTOR (SAM3U_MCI_BASE+SAM3U_HSMCI_CSTOR_OFFSET)
-#define SAM3U_HSMCI_RSPR0 (SAM3U_MCI_BASE+SAM3U_HSMCI_RSPR0_OFFSET)
-#define SAM3U_HSMCI_RSPR1 (SAM3U_MCI_BASE+SAM3U_HSMCI_RSPR1_OFFSET)
-#define SAM3U_HSMCI_RSPR2 (SAM3U_MCI_BASE+SAM3U_HSMCI_RSPR2_OFFSET)
-#define SAM3U_HSMCI_RSPR3 (SAM3U_MCI_BASE+SAM3U_HSMCI_RSPR3_OFFSET)
-#define SAM3U_HSMCI_RDR (SAM3U_MCI_BASE+SAM3U_HSMCI_RDR_OFFSET)
-#define SAM3U_HSMCI_TDR (SAM3U_MCI_BASE+SAM3U_HSMCI_TDR_OFFSET)
-#define SAM3U_HSMCI_SR (SAM3U_MCI_BASE+SAM3U_HSMCI_SR_OFFSET)
-#define SAM3U_HSMCI_IER (SAM3U_MCI_BASE+SAM3U_HSMCI_IER_OFFSET)
-#define SAM3U_HSMCI_IDR (SAM3U_MCI_BASE+SAM3U_HSMCI_IDR_OFFSET)
-#define SAM3U_HSMCI_IMR (SAM3U_MCI_BASE+SAM3U_HSMCI_IMR_OFFSET)
-#define SAM3U_HSMCI_DMA (SAM3U_MCI_BASE+SAM3U_HSMCI_DMA_OFFSET)
-#define SAM3U_HSMCI_CFG (SAM3U_MCI_BASE+SAM3U_HSMCI_CFG_OFFSET)
-#define SAM3U_HSMCI_WPMR (SAM3U_MCI_BASE+SAM3U_HSMCI_WPMR_OFFSET)
-#define SAM3U_HSMCI_WPSR (SAM3U_MCI_BASE+SAM3U_HSMCI_WPSR_OFFSET)
-#define SAM3U_HSMCI_FIFO (SAM3U_MCI_BASE+SAM3U_HSMCI_FIFO_OFFSET)
-
-/* HSMCI register bit definitions *******************************************************/
-
-/* HSMCI Control Register */
-
-#define HSMCI_CR_MCIEN (1 << 0) /* Bit 0: Multi-Media Interface Enable */
-#define HSMCI_CR_MCIDIS (1 << 1) /* Bit 1: Multi-Media Interface Disable */
-#define HSMCI_CR_PWSEN (1 << 2) /* Bit 2: Power Save Mode Enable */
-#define HSMCI_CR_PWSDIS (1 << 3) /* Bit 3: Power Save Mode Disable */
-#define HSMCI_CR_SWRST (1 << 7) /* Bit 7: Software Reset */
-
-/* HSMCI Mode Register */
-
-#define HSMCI_MR_CLKDIV_SHIFT (0) /* Bits 0-7: Clock Divider */
-#define HSMCI_MR_CLKDIV_MASK (0xff << HSMCI_MR_CLKDIV_SHIFT)
-#define HSMCI_MR_PWSDIV_SHIFT (8) /* Bits 8-10: Power Saving Divider */
-#define HSMCI_MR_PWSDIV_MASK (7 << HSMCI_MR_PWSDIV_SHIFT)
-# define HSMCI_MR_PWSDIV_MAX (7 << HSMCI_MR_PWSDIV_SHIFT)
-#define HSMCI_MR_RDPROOF (1 << 11) /* Bit 11: Read Proof Enable */
-#define HSMCI_MR_WRPROOF (1 << 12) /* Bit 12: Write Proof Enable */
-#define HSMCI_MR_FBYTE (1 << 13) /* Bit 13: Force Byte Transfer */
-#define HSMCI_MR_PADV (1 << 14) /* Bit 14: Padding Value */
-#define HSMCI_MR_BLKLEN_SHIFT (16) /* Bits 16-31: Data Block Length */
-#define HSMCI_MR_BLKLEN_MASK (0xffff << HSMCI_MR_BLKLEN_SHIFT)
-
-/* HSMCI Data Timeout Register */
-
-#define HSMCI_DTOR_DTOCYC_SHIFT (0) /* Bits 0-3: Data Timeout Cycle Number */
-#define HSMCI_DTOR_DTOCYC_MASK (15 << HSMCI_DTOR_DTOCYC_SHIFT)
-# define HSMCI_DTOR_DTOCYC_MAX (15 << HSMCI_DTOR_DTOCYC_SHIFT)
-#define HSMCI_DTOR_DTOMUL_SHIFT (4) /* Bits 4-6: Data Timeout Multiplier */
-#define HSMCI_DTOR_DTOMUL_MASK (7 << HSMCI_DTOR_DTOMUL_SHIFT)
-# define HSMCI_DTOR_DTOMUL_1 (0 << HSMCI_DTOR_DTOMUL_SHIFT)
-# define HSMCI_DTOR_DTOMUL_16 (1 << HSMCI_DTOR_DTOMUL_SHIFT)
-# define HSMCI_DTOR_DTOMUL_128 (2 << HSMCI_DTOR_DTOMUL_SHIFT)
-# define HSMCI_DTOR_DTOMUL_256 (3 << HSMCI_DTOR_DTOMUL_SHIFT)
-# define HSMCI_DTOR_DTOMUL_1024 (4 << HSMCI_DTOR_DTOMUL_SHIFT)
-# define HSMCI_DTOR_DTOMUL_4096 (5 << HSMCI_DTOR_DTOMUL_SHIFT)
-# define HSMCI_DTOR_DTOMUL_65536 (6 << HSMCI_DTOR_DTOMUL_SHIFT)
-# define HSMCI_DTOR_DTOMUL_1048576 (7 << HSMCI_DTOR_DTOMUL_SHIFT)
-# define HSMCI_DTOR_DTOMUL_MAX (7 << HSMCI_DTOR_DTOMUL_SHIFT)
-
-/* HSMCI SDCard/SDIO Register */
-
-#define HSMCI_SDCR_SDCSEL_SHIFT (0) /* Bits 0-1: SDCard/SDIO Slot */
-#define HSMCI_SDCR_SDCSEL_MASK (3 << HSMCI_SDCR_SDCSEL_SHIFT)
-# define HSMCI_SDCR_SDCSEL_SLOTA (0 << HSMCI_SDCR_SDCSEL_SHIFT)
-#define HSMCI_SDCR_SDCBUS_SHIFT (6) /* Bits 6-7: SDCard/SDIO Bus Width */
-#define HSMCI_SDCR_SDCBUS_MASK (3 << HSMCI_SDCR_SDCBUS_SHIFT)
-# define HSMCI_SDCR_SDCBUS_1BIT (0 << HSMCI_SDCR_SDCBUS_SHIFT)
-# define HSMCI_SDCR_SDCBUS_4BIT (2 << HSMCI_SDCR_SDCBUS_SHIFT)
-# define HSMCI_SDCR_SDCBUS_8BIT (3 << HSMCI_SDCR_SDCBUS_SHIFT)
-
-/* HSMCI Command Register */
-
-#define HSMCI_CMDR_CMDNB_SHIFT (0) /* Bits 0-5: Command Number */
-#define HSMCI_CMDR_CMDNB_MASK (63 << HSMCI_CMDR_CMDNB_SHIFT)
-#define HSMCI_CMDR_RSPTYP_SHIFT (6) /* Bits 6-7: Response Type */
-#define HSMCI_CMDR_RSPTYP_MASK (3 << HSMCI_CMDR_RSPTYP_SHIFT)
-# define HSMCI_CMDR_RSPTYP_NONE (0 << HSMCI_CMDR_RSPTYP_SHIFT) /* No response */
-# define HSMCI_CMDR_RSPTYP_48BIT (1 << HSMCI_CMDR_RSPTYP_SHIFT) /* 48-bit response */
-# define HSMCI_CMDR_RSPTYP_136BIT (2 << HSMCI_CMDR_RSPTYP_SHIFT) /* 136-bit response */
-# define HSMCI_CMDR_RSPTYP_R1B (3 << HSMCI_CMDR_RSPTYP_SHIFT) /* R1b response type */
-#define HSMCI_CMDR_SPCMD_SHIFT (8) /* Bits 8-10: Special Command */
-#define HSMCI_CMDR_SPCMD_MASK (7 << HSMCI_CMDR_SPCMD_SHIFT)
-# define HSMCI_CMDR_SPCMD_NORMAL (0 << HSMCI_CMDR_SPCMD_SHIFT) /* Not a special CMD */
-# define HSMCI_CMDR_SPCMD_INIT (1 << HSMCI_CMDR_SPCMD_SHIFT) /* Initialization CMD */
-# define HSMCI_CMDR_SPCMD_SYNC (2 << HSMCI_CMDR_SPCMD_SHIFT) /* Synchronized CMD */
-# define HSMCI_CMDR_SPCMD_CEATAC (3 << HSMCI_CMDR_SPCMD_SHIFT) /* CE-ATA Completion Signal disable CMD */
-# define HSMCI_CMDR_SPCMD_INTCMD (4 << HSMCI_CMDR_SPCMD_SHIFT) /* Interrupt command */
-# define HSMCI_CMDR_SPCMD_INTRESP (5 << HSMCI_CMDR_SPCMD_SHIFT) /* Interrupt response */
-# define HSMCI_CMDR_SPCMD_BOOTOP (6 << HSMCI_CMDR_SPCMD_SHIFT) /* Boot Operation Request */
-# define HSMCI_CMDR_SPCMD_BOOTEND (7 << HSMCI_CMDR_SPCMD_SHIFT) /* End Boot Operation */
-#define HSMCI_CMDR_OPDCMD (1 << 11) /* Bit 11: Open Drain Command */
-#define HSMCI_CMDR_MAXLAT (1 << 12) /* Bit 12: Max Latency for Command to Response */
-#define HSMCI_CMDR_TRCMD_SHIFT (16) /* Bits 16-17: Transfer Command */
-#define HSMCI_CMDR_TRCMD_MASK (3 << HSMCI_CMDR_TRCMD_SHIFT)
-# define HSMCI_CMDR_TRCMD_NONE (0 << HSMCI_CMDR_TRCMD_SHIFT) /* No data transfer */
-# define HSMCI_CMDR_TRCMD_START (1 << HSMCI_CMDR_TRCMD_SHIFT) /* Start data transfer */
-# define HSMCI_CMDR_TRCMD_STOP (2 << HSMCI_CMDR_TRCMD_SHIFT) /* Stop data transfer */
-#define HSMCI_CMDR_TRDIR (1 << 18) /* Bit 18: Transfer Direction */
-# define HSMCI_CMDR_TRDIR_WRITE (0 << 18)
-# define HSMCI_CMDR_TRDIR_READ (1 << 18)
-#define HSMCI_CMDR_TRTYP_SHIFT (19) /* Bits 19-21: Transfer Type */
-#define HSMCI_CMDR_TRTYP_MASK (7 << HSMCI_CMDR_TRTYP_SHIFT)
-# define HSMCI_CMDR_TRTYP_SINGLE (0 << HSMCI_CMDR_TRTYP_SHIFT) /* MMC/SDCard Single Block */
-# define HSMCI_CMDR_TRTYP_MULTI (1 << HSMCI_CMDR_TRTYP_SHIFT) /* MMC/SDCard Multiple Block */
-# define HSMCI_CMDR_TRTYP_STREAM (2 << HSMCI_CMDR_TRTYP_SHIFT) /* MMC Stream */
-# define HSMCI_CMDR_TRTYP_SDIOBYTE (4 << HSMCI_CMDR_TRTYP_SHIFT) /* SDIO Byte */
-# define HSMCI_CMDR_TRTYP_SDIOBLK (5 << HSMCI_CMDR_TRTYP_SHIFT) /* SDIO Block */
-#define HSMCI_CMDR_IOSPCMD_SHIFT (24) /* Bits 24-25: SDIO Special Command */
-#define HSMCI_CMDR_IOSPCMD_MASK (3 << HSMCI_CMDR_IOSPCMD_SHIFT)
-# define HSMCI_CMDR_IOSPCMD_NORMAL (0 << HSMCI_CMDR_IOSPCMD_SHIFT) /* Not an SDIO Special Command */
-# define HSMCI_CMDR_IOSPCMD_SUSP (1 << HSMCI_CMDR_IOSPCMD_SHIFT) /* SDIO Suspend Command */
-# define HSMCI_CMDR_IOSPCMD_RESUME (2 << HSMCI_CMDR_IOSPCMD_SHIFT) /* SDIO Resume Command */
-#define HSMCI_CMDR_ATACS (1 << 26) /* Bit 26: ATA with Command Completion Signal */
-#define HSMCI_CMDR_BOOTACK (1 << 17) /* Bit 27: Boot Operation Acknowledge */
-
-/* HSMCI Block Register */
-
-#define HSMCI_BLKR_BCNT_SHIFT (0) /* Bits 0-15: MMC/SDIO Block Count - SDIO Byte Count */
-#define HSMCI_BLKR_BCNT_MASK (0xffff << HSMCI_BLKR_BCNT_SHIFT)
-#define HSMCI_BLKR_BLKLEN_SHIFT (16) /* Bits 16-31: Data Block Length */
-#define HSMCI_BLKR_BLKLEN_MASK (0xffff << HSMCI_BLKR_BLKLEN_SHIFT)
-
-/* HSMCI Completion Signal Timeout Register */
-
-#define HSMCI_CSTOR_CSTOCYC_SHIFT (0) /* Bits 0-3: Completion Signal Timeout Cycle Number */
-#define HSMCI_CSTOR_CSTOCYC_MASK (15 << HSMCI_CSTOR_CSTOCYC_SHIFT)
-#define HSMCI_CSTOR_CSTOMUL_SHIFT (4) /* Bits 4-6: Completion Signal Timeout Multiplier */
-#define HSMCI_CSTOR_CSTOMUL_MASK (7 << HSMCI_CSTOR_CSTOMUL_SHIFT)
-# define HSMCI_CSTOR_CSTOMUL_1 (0 << HSMCI_CSTOR_CSTOMUL_SHIFT)
-# define HSMCI_CSTOR_CSTOMUL_16 (1 << HSMCI_CSTOR_CSTOMUL_SHIFT)
-# define HSMCI_CSTOR_CSTOMUL_128 (2 << HSMCI_CSTOR_CSTOMUL_SHIFT)
-# define HSMCI_CSTOR_CSTOMUL_256 (3 << HSMCI_CSTOR_CSTOMUL_SHIFT)
-# define HSMCI_CSTOR_CSTOMUL_1024 (4 << HSMCI_CSTOR_CSTOMUL_SHIFT)
-# define HSMCI_CSTOR_CSTOMUL_4096 (5 << HSMCI_CSTOR_CSTOMUL_SHIFT)
-# define HSMCI_CSTOR_CSTOMUL_65536 (6 << HSMCI_CSTOR_CSTOMUL_SHIFT)
-# define HSMCI_CSTOR_CSTOMUL_1048576 (7 << HSMCI_CSTOR_CSTOMUL_SHIFT)
-
-/* HSMCI Status Register, HSMCI Interrupt Enable Register, HSMCI Interrupt Disable
- * Register, and HSMCI Interrupt Mask Register common bit-field definitions
- */
-
-#define HSMCI_INT_CMDRDY (1 << 0) /* Bit 0: Command Ready */
-#define HSMCI_INT_RXRDY (1 << 1) /* Bit 1: Receiver Ready */
-#define HSMCI_INT_TXRDY (1 << 2) /* Bit 2: Transmit Ready */
-#define HSMCI_INT_BLKE (1 << 3) /* Bit 3: Data Block Ended */
-#define HSMCI_INT_DTIP (1 << 4) /* Bit 4: Data Transfer in Progress */
-#define HSMCI_INT_NOTBUSY (1 << 5) /* Bit 6: HSMCI Not Busy */
-#define HSMCI_INT_SDIOIRQA (1 << 8) /* Bit 8: SDIO Interrupt for Slot A */
-#define HSMCI_INT_SDIOWAIT (1 << 12) /* Bit 12: SDIO Read Wait Operation Status */
-#define HSMCI_INT_CSRCV (1 << 13) /* Bit 13: CE-ATA Completion Signal Received */
-#define HSMCI_INT_RINDE (1 << 16) /* Bit 16: Response Index Error */
-#define HSMCI_INT_RDIRE (1 << 17) /* Bit 17: Response Direction Error */
-#define HSMCI_INT_RCRCE (1 << 18) /* Bit 18: Response CRC Error */
-#define HSMCI_INT_RENDE (1 << 19) /* Bit 19: Response End Bit Error */
-#define HSMCI_INT_RTOE (1 << 20) /* Bit 20: Response Time-out */
-#define HSMCI_INT_DCRCE (1 << 21) /* Bit 21: Data CRC Error */
-#define HSMCI_INT_DTOE (1 << 22) /* Bit 22: Data Time-out Error */
-#define HSMCI_INT_CSTOE (1 << 23) /* Bit 23: Completion Signal Time-out Error */
-#define HSMCI_INT_BLKOVRE (1 << 24) /* Bit 24: DMA Block Overrun Error */
-#define HSMCI_INT_DMADONE (1 << 25) /* Bit 25: DMA Transfer done */
-#define HSMCI_INT_FIFOEMPTY (1 << 26) /* Bit 26: FIFO empty flag */
-#define HSMCI_INT_XFRDONE (1 << 27) /* Bit 27: Transfer Done flag */
-#define HSMCI_INT_ACKRCV (1 << 28) /* Bit 28: Boot Operation Acknowledge Received */
-#define HSMCI_INT_ACKRCVE (1 << 29) /* Bit 29: Boot Operation Acknowledge Error */
-#define HSMCI_INT_OVRE (1 << 30) /* Bit 30: Overrun */
-#define HSMCI_INT_UNRE (1 << 31) /* Bit 31: Underrun */
-
-/* HSMCI DMA Configuration Register */
-
-#define HSMCI_DMA_OFFSET_SHIFT (0) /* Bits 0-1: DMA Write Buffer Offset */
-#define HSMCI_DMA_OFFSET_MASK (3 << HSMCI_DMA_OFFSET_SHIFT)
-#define HSMCI_DMA_CHKSIZE (1 << 4) /* Bit 4: DMA Channel Read and Write Chunk Size */
-#define HSMCI_DMA_DMAEN (1 << 8) /* Bit 8: DMA Hardware Handshaking Enable */
-#define HSMCI_DMA_ROPT (1 << 12) /* Bit 12: Read Optimization with padding */
-
-/* HSMCI Configuration Register */
-
-#define HSMCI_CFG_FIFOMODE (1 << 0) /* Bit 0: HSMCI Internal FIFO control mode */
-#define HSMCI_CFG_FERRCTRL (1 << 4) /* Bit 4: Flow Error flag reset control mode */
-#define HSMCI_CFG_HSMODE (1 << 8) /* Bit 8: High Speed Mode */
-#define HSMCI_CFG_LSYNC (1 << 12) /* Bit 12: Synchronize on the last block */
-
-/* HSMCI Write Protect Mode Register */
-
-#define HSMCI_WPMR_WP_EN (1 << 0) /* Bit 0: Write Protection Enable */
-#define HSMCI_WPMR_WP_KEY_SHIFT (8) /* Bits 8-31: Write Protection Key password */
-#define HSMCI_WPMR_WP_KEY_MASK (0x00ffffff << HSMCI_WPMR_WP_KEY_SHIFT)
-
-/* HSMCI Write Protect Status Register */
-
-#define HSMCI_WPSR_WP_VS_SHIFT (0) /* Bits 0-3: Write Protection Violation Status */
-#define HSMCI_WPSR_WP_VS_MASK (15 << HSMCI_WPSR_WP_VS_SHIFT)
-#define HSMCI_WPSR_WP_VSRC_SHIFT (8) /* Bits 8-23: Write Protection Violation Source */
-#define HSMCI_WPSR_WP_VSRC_MASK (0xffff << HSMCI_WPSR_WP_VSRC_SHIFT)
-
-/****************************************************************************************
- * Public Types
- ****************************************************************************************/
-
-/****************************************************************************************
- * Public Data
- ****************************************************************************************/
-
-/****************************************************************************************
- * Public Functions
- ****************************************************************************************/
-
-#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_HSMCI_H */
+/**************************************************************************************** + * arch/arm/src/sam3u/sam3u_hsmci.h + * + * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_HSMCI_H +#define __ARCH_ARM_SRC_SAM3U_SAM3U_HSMCI_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +#include <nuttx/config.h> + +#include "chip.h" +#include "sam3u_memorymap.h" + +/**************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************/ + +/* HSMCI register offsets ***************************************************************/ + +#define SAM3U_HSMCI_CR_OFFSET 0x0000 /* Control Register */ +#define SAM3U_HSMCI_MR_OFFSET 0x0004 /* Mode Register */ +#define SAM3U_HSMCI_DTOR_OFFSET 0x0008 /* Data Timeout Register */ +#define SAM3U_HSMCI_SDCR_OFFSET 0x000c /* SD/SDIO Card Register */ +#define SAM3U_HSMCI_ARGR_OFFSET 0x0010 /* Argument Register */ +#define SAM3U_HSMCI_CMDR_OFFSET 0x0014 /* Command Register */ +#define SAM3U_HSMCI_BLKR_OFFSET 0x0018 /* Block Register */ +#define SAM3U_HSMCI_CSTOR_OFFSET 0x001c /* Completion Signal Timeout Register */ +#define SAM3U_HSMCI_RSPR0_OFFSET 0x0020 /* Response Register 0 */ +#define SAM3U_HSMCI_RSPR1_OFFSET 0x0024 /* Response Register 1 */ +#define SAM3U_HSMCI_RSPR2_OFFSET 0x0028 /* Response Register 2 */ +#define SAM3U_HSMCI_RSPR3_OFFSET 0x002c /* Response Register 3 */ +#define SAM3U_HSMCI_RDR_OFFSET 0x0030 /* Receive Data Register */ +#define SAM3U_HSMCI_TDR_OFFSET 0x0034 /* Transmit Data Register */ + /* 0x0038-0x003c: Reserved */ +#define SAM3U_HSMCI_SR_OFFSET 0x0040 /* Status Register */ +#define SAM3U_HSMCI_IER_OFFSET 0x0044 /* Interrupt Enable Register */ +#define SAM3U_HSMCI_IDR_OFFSET 0x0048 /* Interrupt Disable Register */ +#define SAM3U_HSMCI_IMR_OFFSET 0x004c /* Interrupt Mask Register */ +#define SAM3U_HSMCI_DMA_OFFSET 0x0050 /* DMA Configuration Register */ +#define SAM3U_HSMCI_CFG_OFFSET 0x0054 /* Configuration Register */ + /* 0x0058-0x00e0: Reserved */ +#define SAM3U_HSMCI_WPMR_OFFSET 0x00e4 /* Write Protection Mode Register */ +#define SAM3U_HSMCI_WPSR_OFFSET 0x00e8 /* Write Protection Status Register */ + /* 0x00ec-0x00fc: Reserved */ + /* 0x0100-0x0124: Reserved */ +#define SAM3U_HSMCI_FIFO_OFFSET 0x0200 /* 0x0200-0x3ffc FIFO Memory Aperture */ + +/* HSMCI register adresses **************************************************************/ + +#define SAM3U_HSMCI_CR (SAM3U_MCI_BASE+SAM3U_HSMCI_CR_OFFSET) +#define SAM3U_HSMCI_MR (SAM3U_MCI_BASE+SAM3U_HSMCI_MR_OFFSET) +#define SAM3U_HSMCI_DTOR (SAM3U_MCI_BASE+SAM3U_HSMCI_DTOR_OFFSET) +#define SAM3U_HSMCI_SDCR (SAM3U_MCI_BASE+SAM3U_HSMCI_SDCR_OFFSET) +#define SAM3U_HSMCI_ARGR (SAM3U_MCI_BASE+SAM3U_HSMCI_ARGR_OFFSET) +#define SAM3U_HSMCI_CMDR (SAM3U_MCI_BASE+SAM3U_HSMCI_CMDR_OFFSET) +#define SAM3U_HSMCI_BLKR (SAM3U_MCI_BASE+SAM3U_HSMCI_BLKR_OFFSET) +#define SAM3U_HSMCI_CSTOR (SAM3U_MCI_BASE+SAM3U_HSMCI_CSTOR_OFFSET) +#define SAM3U_HSMCI_RSPR0 (SAM3U_MCI_BASE+SAM3U_HSMCI_RSPR0_OFFSET) +#define SAM3U_HSMCI_RSPR1 (SAM3U_MCI_BASE+SAM3U_HSMCI_RSPR1_OFFSET) +#define SAM3U_HSMCI_RSPR2 (SAM3U_MCI_BASE+SAM3U_HSMCI_RSPR2_OFFSET) +#define SAM3U_HSMCI_RSPR3 (SAM3U_MCI_BASE+SAM3U_HSMCI_RSPR3_OFFSET) +#define SAM3U_HSMCI_RDR (SAM3U_MCI_BASE+SAM3U_HSMCI_RDR_OFFSET) +#define SAM3U_HSMCI_TDR (SAM3U_MCI_BASE+SAM3U_HSMCI_TDR_OFFSET) +#define SAM3U_HSMCI_SR (SAM3U_MCI_BASE+SAM3U_HSMCI_SR_OFFSET) +#define SAM3U_HSMCI_IER (SAM3U_MCI_BASE+SAM3U_HSMCI_IER_OFFSET) +#define SAM3U_HSMCI_IDR (SAM3U_MCI_BASE+SAM3U_HSMCI_IDR_OFFSET) +#define SAM3U_HSMCI_IMR (SAM3U_MCI_BASE+SAM3U_HSMCI_IMR_OFFSET) +#define SAM3U_HSMCI_DMA (SAM3U_MCI_BASE+SAM3U_HSMCI_DMA_OFFSET) +#define SAM3U_HSMCI_CFG (SAM3U_MCI_BASE+SAM3U_HSMCI_CFG_OFFSET) +#define SAM3U_HSMCI_WPMR (SAM3U_MCI_BASE+SAM3U_HSMCI_WPMR_OFFSET) +#define SAM3U_HSMCI_WPSR (SAM3U_MCI_BASE+SAM3U_HSMCI_WPSR_OFFSET) +#define SAM3U_HSMCI_FIFO (SAM3U_MCI_BASE+SAM3U_HSMCI_FIFO_OFFSET) + +/* HSMCI register bit definitions *******************************************************/ + +/* HSMCI Control Register */ + +#define HSMCI_CR_MCIEN (1 << 0) /* Bit 0: Multi-Media Interface Enable */ +#define HSMCI_CR_MCIDIS (1 << 1) /* Bit 1: Multi-Media Interface Disable */ +#define HSMCI_CR_PWSEN (1 << 2) /* Bit 2: Power Save Mode Enable */ +#define HSMCI_CR_PWSDIS (1 << 3) /* Bit 3: Power Save Mode Disable */ +#define HSMCI_CR_SWRST (1 << 7) /* Bit 7: Software Reset */ + +/* HSMCI Mode Register */ + +#define HSMCI_MR_CLKDIV_SHIFT (0) /* Bits 0-7: Clock Divider */ +#define HSMCI_MR_CLKDIV_MASK (0xff << HSMCI_MR_CLKDIV_SHIFT) +#define HSMCI_MR_PWSDIV_SHIFT (8) /* Bits 8-10: Power Saving Divider */ +#define HSMCI_MR_PWSDIV_MASK (7 << HSMCI_MR_PWSDIV_SHIFT) +# define HSMCI_MR_PWSDIV_MAX (7 << HSMCI_MR_PWSDIV_SHIFT) +#define HSMCI_MR_RDPROOF (1 << 11) /* Bit 11: Read Proof Enable */ +#define HSMCI_MR_WRPROOF (1 << 12) /* Bit 12: Write Proof Enable */ +#define HSMCI_MR_FBYTE (1 << 13) /* Bit 13: Force Byte Transfer */ +#define HSMCI_MR_PADV (1 << 14) /* Bit 14: Padding Value */ +#define HSMCI_MR_BLKLEN_SHIFT (16) /* Bits 16-31: Data Block Length */ +#define HSMCI_MR_BLKLEN_MASK (0xffff << HSMCI_MR_BLKLEN_SHIFT) + +/* HSMCI Data Timeout Register */ + +#define HSMCI_DTOR_DTOCYC_SHIFT (0) /* Bits 0-3: Data Timeout Cycle Number */ +#define HSMCI_DTOR_DTOCYC_MASK (15 << HSMCI_DTOR_DTOCYC_SHIFT) +# define HSMCI_DTOR_DTOCYC_MAX (15 << HSMCI_DTOR_DTOCYC_SHIFT) +#define HSMCI_DTOR_DTOMUL_SHIFT (4) /* Bits 4-6: Data Timeout Multiplier */ +#define HSMCI_DTOR_DTOMUL_MASK (7 << HSMCI_DTOR_DTOMUL_SHIFT) +# define HSMCI_DTOR_DTOMUL_1 (0 << HSMCI_DTOR_DTOMUL_SHIFT) +# define HSMCI_DTOR_DTOMUL_16 (1 << HSMCI_DTOR_DTOMUL_SHIFT) +# define HSMCI_DTOR_DTOMUL_128 (2 << HSMCI_DTOR_DTOMUL_SHIFT) +# define HSMCI_DTOR_DTOMUL_256 (3 << HSMCI_DTOR_DTOMUL_SHIFT) +# define HSMCI_DTOR_DTOMUL_1024 (4 << HSMCI_DTOR_DTOMUL_SHIFT) +# define HSMCI_DTOR_DTOMUL_4096 (5 << HSMCI_DTOR_DTOMUL_SHIFT) +# define HSMCI_DTOR_DTOMUL_65536 (6 << HSMCI_DTOR_DTOMUL_SHIFT) +# define HSMCI_DTOR_DTOMUL_1048576 (7 << HSMCI_DTOR_DTOMUL_SHIFT) +# define HSMCI_DTOR_DTOMUL_MAX (7 << HSMCI_DTOR_DTOMUL_SHIFT) + +/* HSMCI SDCard/SDIO Register */ + +#define HSMCI_SDCR_SDCSEL_SHIFT (0) /* Bits 0-1: SDCard/SDIO Slot */ +#define HSMCI_SDCR_SDCSEL_MASK (3 << HSMCI_SDCR_SDCSEL_SHIFT) +# define HSMCI_SDCR_SDCSEL_SLOTA (0 << HSMCI_SDCR_SDCSEL_SHIFT) +#define HSMCI_SDCR_SDCBUS_SHIFT (6) /* Bits 6-7: SDCard/SDIO Bus Width */ +#define HSMCI_SDCR_SDCBUS_MASK (3 << HSMCI_SDCR_SDCBUS_SHIFT) +# define HSMCI_SDCR_SDCBUS_1BIT (0 << HSMCI_SDCR_SDCBUS_SHIFT) +# define HSMCI_SDCR_SDCBUS_4BIT (2 << HSMCI_SDCR_SDCBUS_SHIFT) +# define HSMCI_SDCR_SDCBUS_8BIT (3 << HSMCI_SDCR_SDCBUS_SHIFT) + +/* HSMCI Command Register */ + +#define HSMCI_CMDR_CMDNB_SHIFT (0) /* Bits 0-5: Command Number */ +#define HSMCI_CMDR_CMDNB_MASK (63 << HSMCI_CMDR_CMDNB_SHIFT) +#define HSMCI_CMDR_RSPTYP_SHIFT (6) /* Bits 6-7: Response Type */ +#define HSMCI_CMDR_RSPTYP_MASK (3 << HSMCI_CMDR_RSPTYP_SHIFT) +# define HSMCI_CMDR_RSPTYP_NONE (0 << HSMCI_CMDR_RSPTYP_SHIFT) /* No response */ +# define HSMCI_CMDR_RSPTYP_48BIT (1 << HSMCI_CMDR_RSPTYP_SHIFT) /* 48-bit response */ +# define HSMCI_CMDR_RSPTYP_136BIT (2 << HSMCI_CMDR_RSPTYP_SHIFT) /* 136-bit response */ +# define HSMCI_CMDR_RSPTYP_R1B (3 << HSMCI_CMDR_RSPTYP_SHIFT) /* R1b response type */ +#define HSMCI_CMDR_SPCMD_SHIFT (8) /* Bits 8-10: Special Command */ +#define HSMCI_CMDR_SPCMD_MASK (7 << HSMCI_CMDR_SPCMD_SHIFT) +# define HSMCI_CMDR_SPCMD_NORMAL (0 << HSMCI_CMDR_SPCMD_SHIFT) /* Not a special CMD */ +# define HSMCI_CMDR_SPCMD_INIT (1 << HSMCI_CMDR_SPCMD_SHIFT) /* Initialization CMD */ +# define HSMCI_CMDR_SPCMD_SYNC (2 << HSMCI_CMDR_SPCMD_SHIFT) /* Synchronized CMD */ +# define HSMCI_CMDR_SPCMD_CEATAC (3 << HSMCI_CMDR_SPCMD_SHIFT) /* CE-ATA Completion Signal disable CMD */ +# define HSMCI_CMDR_SPCMD_INTCMD (4 << HSMCI_CMDR_SPCMD_SHIFT) /* Interrupt command */ +# define HSMCI_CMDR_SPCMD_INTRESP (5 << HSMCI_CMDR_SPCMD_SHIFT) /* Interrupt response */ +# define HSMCI_CMDR_SPCMD_BOOTOP (6 << HSMCI_CMDR_SPCMD_SHIFT) /* Boot Operation Request */ +# define HSMCI_CMDR_SPCMD_BOOTEND (7 << HSMCI_CMDR_SPCMD_SHIFT) /* End Boot Operation */ +#define HSMCI_CMDR_OPDCMD (1 << 11) /* Bit 11: Open Drain Command */ +#define HSMCI_CMDR_MAXLAT (1 << 12) /* Bit 12: Max Latency for Command to Response */ +#define HSMCI_CMDR_TRCMD_SHIFT (16) /* Bits 16-17: Transfer Command */ +#define HSMCI_CMDR_TRCMD_MASK (3 << HSMCI_CMDR_TRCMD_SHIFT) +# define HSMCI_CMDR_TRCMD_NONE (0 << HSMCI_CMDR_TRCMD_SHIFT) /* No data transfer */ +# define HSMCI_CMDR_TRCMD_START (1 << HSMCI_CMDR_TRCMD_SHIFT) /* Start data transfer */ +# define HSMCI_CMDR_TRCMD_STOP (2 << HSMCI_CMDR_TRCMD_SHIFT) /* Stop data transfer */ +#define HSMCI_CMDR_TRDIR (1 << 18) /* Bit 18: Transfer Direction */ +# define HSMCI_CMDR_TRDIR_WRITE (0 << 18) +# define HSMCI_CMDR_TRDIR_READ (1 << 18) +#define HSMCI_CMDR_TRTYP_SHIFT (19) /* Bits 19-21: Transfer Type */ +#define HSMCI_CMDR_TRTYP_MASK (7 << HSMCI_CMDR_TRTYP_SHIFT) +# define HSMCI_CMDR_TRTYP_SINGLE (0 << HSMCI_CMDR_TRTYP_SHIFT) /* MMC/SDCard Single Block */ +# define HSMCI_CMDR_TRTYP_MULTI (1 << HSMCI_CMDR_TRTYP_SHIFT) /* MMC/SDCard Multiple Block */ +# define HSMCI_CMDR_TRTYP_STREAM (2 << HSMCI_CMDR_TRTYP_SHIFT) /* MMC Stream */ +# define HSMCI_CMDR_TRTYP_SDIOBYTE (4 << HSMCI_CMDR_TRTYP_SHIFT) /* SDIO Byte */ +# define HSMCI_CMDR_TRTYP_SDIOBLK (5 << HSMCI_CMDR_TRTYP_SHIFT) /* SDIO Block */ +#define HSMCI_CMDR_IOSPCMD_SHIFT (24) /* Bits 24-25: SDIO Special Command */ +#define HSMCI_CMDR_IOSPCMD_MASK (3 << HSMCI_CMDR_IOSPCMD_SHIFT) +# define HSMCI_CMDR_IOSPCMD_NORMAL (0 << HSMCI_CMDR_IOSPCMD_SHIFT) /* Not an SDIO Special Command */ +# define HSMCI_CMDR_IOSPCMD_SUSP (1 << HSMCI_CMDR_IOSPCMD_SHIFT) /* SDIO Suspend Command */ +# define HSMCI_CMDR_IOSPCMD_RESUME (2 << HSMCI_CMDR_IOSPCMD_SHIFT) /* SDIO Resume Command */ +#define HSMCI_CMDR_ATACS (1 << 26) /* Bit 26: ATA with Command Completion Signal */ +#define HSMCI_CMDR_BOOTACK (1 << 17) /* Bit 27: Boot Operation Acknowledge */ + +/* HSMCI Block Register */ + +#define HSMCI_BLKR_BCNT_SHIFT (0) /* Bits 0-15: MMC/SDIO Block Count - SDIO Byte Count */ +#define HSMCI_BLKR_BCNT_MASK (0xffff << HSMCI_BLKR_BCNT_SHIFT) +#define HSMCI_BLKR_BLKLEN_SHIFT (16) /* Bits 16-31: Data Block Length */ +#define HSMCI_BLKR_BLKLEN_MASK (0xffff << HSMCI_BLKR_BLKLEN_SHIFT) + +/* HSMCI Completion Signal Timeout Register */ + +#define HSMCI_CSTOR_CSTOCYC_SHIFT (0) /* Bits 0-3: Completion Signal Timeout Cycle Number */ +#define HSMCI_CSTOR_CSTOCYC_MASK (15 << HSMCI_CSTOR_CSTOCYC_SHIFT) +#define HSMCI_CSTOR_CSTOMUL_SHIFT (4) /* Bits 4-6: Completion Signal Timeout Multiplier */ +#define HSMCI_CSTOR_CSTOMUL_MASK (7 << HSMCI_CSTOR_CSTOMUL_SHIFT) +# define HSMCI_CSTOR_CSTOMUL_1 (0 << HSMCI_CSTOR_CSTOMUL_SHIFT) +# define HSMCI_CSTOR_CSTOMUL_16 (1 << HSMCI_CSTOR_CSTOMUL_SHIFT) +# define HSMCI_CSTOR_CSTOMUL_128 (2 << HSMCI_CSTOR_CSTOMUL_SHIFT) +# define HSMCI_CSTOR_CSTOMUL_256 (3 << HSMCI_CSTOR_CSTOMUL_SHIFT) +# define HSMCI_CSTOR_CSTOMUL_1024 (4 << HSMCI_CSTOR_CSTOMUL_SHIFT) +# define HSMCI_CSTOR_CSTOMUL_4096 (5 << HSMCI_CSTOR_CSTOMUL_SHIFT) +# define HSMCI_CSTOR_CSTOMUL_65536 (6 << HSMCI_CSTOR_CSTOMUL_SHIFT) +# define HSMCI_CSTOR_CSTOMUL_1048576 (7 << HSMCI_CSTOR_CSTOMUL_SHIFT) + +/* HSMCI Status Register, HSMCI Interrupt Enable Register, HSMCI Interrupt Disable + * Register, and HSMCI Interrupt Mask Register common bit-field definitions + */ + +#define HSMCI_INT_CMDRDY (1 << 0) /* Bit 0: Command Ready */ +#define HSMCI_INT_RXRDY (1 << 1) /* Bit 1: Receiver Ready */ +#define HSMCI_INT_TXRDY (1 << 2) /* Bit 2: Transmit Ready */ +#define HSMCI_INT_BLKE (1 << 3) /* Bit 3: Data Block Ended */ +#define HSMCI_INT_DTIP (1 << 4) /* Bit 4: Data Transfer in Progress */ +#define HSMCI_INT_NOTBUSY (1 << 5) /* Bit 6: HSMCI Not Busy */ +#define HSMCI_INT_SDIOIRQA (1 << 8) /* Bit 8: SDIO Interrupt for Slot A */ +#define HSMCI_INT_SDIOWAIT (1 << 12) /* Bit 12: SDIO Read Wait Operation Status */ +#define HSMCI_INT_CSRCV (1 << 13) /* Bit 13: CE-ATA Completion Signal Received */ +#define HSMCI_INT_RINDE (1 << 16) /* Bit 16: Response Index Error */ +#define HSMCI_INT_RDIRE (1 << 17) /* Bit 17: Response Direction Error */ +#define HSMCI_INT_RCRCE (1 << 18) /* Bit 18: Response CRC Error */ +#define HSMCI_INT_RENDE (1 << 19) /* Bit 19: Response End Bit Error */ +#define HSMCI_INT_RTOE (1 << 20) /* Bit 20: Response Time-out */ +#define HSMCI_INT_DCRCE (1 << 21) /* Bit 21: Data CRC Error */ +#define HSMCI_INT_DTOE (1 << 22) /* Bit 22: Data Time-out Error */ +#define HSMCI_INT_CSTOE (1 << 23) /* Bit 23: Completion Signal Time-out Error */ +#define HSMCI_INT_BLKOVRE (1 << 24) /* Bit 24: DMA Block Overrun Error */ +#define HSMCI_INT_DMADONE (1 << 25) /* Bit 25: DMA Transfer done */ +#define HSMCI_INT_FIFOEMPTY (1 << 26) /* Bit 26: FIFO empty flag */ +#define HSMCI_INT_XFRDONE (1 << 27) /* Bit 27: Transfer Done flag */ +#define HSMCI_INT_ACKRCV (1 << 28) /* Bit 28: Boot Operation Acknowledge Received */ +#define HSMCI_INT_ACKRCVE (1 << 29) /* Bit 29: Boot Operation Acknowledge Error */ +#define HSMCI_INT_OVRE (1 << 30) /* Bit 30: Overrun */ +#define HSMCI_INT_UNRE (1 << 31) /* Bit 31: Underrun */ + +/* HSMCI DMA Configuration Register */ + +#define HSMCI_DMA_OFFSET_SHIFT (0) /* Bits 0-1: DMA Write Buffer Offset */ +#define HSMCI_DMA_OFFSET_MASK (3 << HSMCI_DMA_OFFSET_SHIFT) +#define HSMCI_DMA_CHKSIZE (1 << 4) /* Bit 4: DMA Channel Read and Write Chunk Size */ +#define HSMCI_DMA_DMAEN (1 << 8) /* Bit 8: DMA Hardware Handshaking Enable */ +#define HSMCI_DMA_ROPT (1 << 12) /* Bit 12: Read Optimization with padding */ + +/* HSMCI Configuration Register */ + +#define HSMCI_CFG_FIFOMODE (1 << 0) /* Bit 0: HSMCI Internal FIFO control mode */ +#define HSMCI_CFG_FERRCTRL (1 << 4) /* Bit 4: Flow Error flag reset control mode */ +#define HSMCI_CFG_HSMODE (1 << 8) /* Bit 8: High Speed Mode */ +#define HSMCI_CFG_LSYNC (1 << 12) /* Bit 12: Synchronize on the last block */ + +/* HSMCI Write Protect Mode Register */ + +#define HSMCI_WPMR_WP_EN (1 << 0) /* Bit 0: Write Protection Enable */ +#define HSMCI_WPMR_WP_KEY_SHIFT (8) /* Bits 8-31: Write Protection Key password */ +#define HSMCI_WPMR_WP_KEY_MASK (0x00ffffff << HSMCI_WPMR_WP_KEY_SHIFT) + +/* HSMCI Write Protect Status Register */ + +#define HSMCI_WPSR_WP_VS_SHIFT (0) /* Bits 0-3: Write Protection Violation Status */ +#define HSMCI_WPSR_WP_VS_MASK (15 << HSMCI_WPSR_WP_VS_SHIFT) +#define HSMCI_WPSR_WP_VSRC_SHIFT (8) /* Bits 8-23: Write Protection Violation Source */ +#define HSMCI_WPSR_WP_VSRC_MASK (0xffff << HSMCI_WPSR_WP_VSRC_SHIFT) + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +/**************************************************************************************** + * Public Data + ****************************************************************************************/ + +/**************************************************************************************** + * Public Functions + ****************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_HSMCI_H */ diff --git a/nuttx/arch/arm/src/sam3u/sam3u_irq.c b/nuttx/arch/arm/src/sam3u/sam3u_irq.c index 156cba319..db79314c0 100644 --- a/nuttx/arch/arm/src/sam3u/sam3u_irq.c +++ b/nuttx/arch/arm/src/sam3u/sam3u_irq.c @@ -3,7 +3,7 @@ * arch/arm/src/chip/sam3u_irq.c * * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/sam3u/sam3u_lowputc.c b/nuttx/arch/arm/src/sam3u/sam3u_lowputc.c index a0e0f9926..7a1e74248 100644 --- a/nuttx/arch/arm/src/sam3u/sam3u_lowputc.c +++ b/nuttx/arch/arm/src/sam3u/sam3u_lowputc.c @@ -2,7 +2,7 @@ * arch/arm/src/sam3u/sam3u_lowputc.c * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/sam3u/sam3u_matrix.h b/nuttx/arch/arm/src/sam3u/sam3u_matrix.h index e9d41a658..52232bfa5 100644 --- a/nuttx/arch/arm/src/sam3u/sam3u_matrix.h +++ b/nuttx/arch/arm/src/sam3u/sam3u_matrix.h @@ -1,214 +1,214 @@ -/****************************************************************************************
- * arch/arm/src/sam3u/sam3u_matric.h
- *
- * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_MATRIX_H
-#define __ARCH_ARM_SRC_SAM3U_SAM3U_MATRIX_H
-
-/****************************************************************************************
- * Included Files
- ****************************************************************************************/
-
-#include <nuttx/config.h>
-
-#include "chip.h"
-#include "sam3u_memorymap.h"
-
-/****************************************************************************************
- * Pre-processor Definitions
- ****************************************************************************************/
-
-/* MATRIX register offsets **************************************************************/
-
-#define SAM3U_MATRIX_MCFG_OFFSET(n) ((n)<<2)
-#define SAM3U_MATRIX_MCFG0_OFFSET 0x0000 /* Master Configuration Register 0 */
-#define SAM3U_MATRIX_MCFG1_OFFSET 0x0004 /* Master Configuration Register 1 */
-#define SAM3U_MATRIX_MCFG2_OFFSET 0x0008 /* Master Configuration Register 2 */
-#define SAM3U_MATRIX_MCFG3_OFFSET 0x000c /* Master Configuration Register 3 */
-#define SAM3U_MATRIX_MCFG4_OFFSET 0x0010 /* Master Configuration Register 4 */
- /* 0x0014-0x003c: Reserved */
-#define SAM3U_MATRIX_SCFG_OFFSET(n) (0x0040+((n)<<2))
-#define SAM3U_MATRIX_SCFG0_OFFSET 0x0040 /* Slave Configuration Register 0 */
-#define SAM3U_MATRIX_SCFG1_OFFSET 0x0044 /* Slave Configuration Register 1 */
-#define SAM3U_MATRIX_SCFG2_OFFSET 0x0048 /* Slave Configuration Register 2 */
-#define SAM3U_MATRIX_SCFG3_OFFSET 0x004c /* Slave Configuration Register 3 */
-#define SAM3U_MATRIX_SCFG4_OFFSET 0x0050 /* Slave Configuration Register 4 */
-#define SAM3U_MATRIX_SCFG5_OFFSET 0x0054 /* Slave Configuration Register 5 */
-#define SAM3U_MATRIX_SCFG6_OFFSET 0x0058 /* Slave Configuration Register 6 */
-#define SAM3U_MATRIX_SCFG7_OFFSET 0x005c /* Slave Configuration Register 7 */
-#define SAM3U_MATRIX_SCFG8_OFFSET 0x0060 /* Slave Configuration Register 8 */
-#define SAM3U_MATRIX_SCFG9_OFFSET 0x0064 /* Slave Configuration Register 9 */
- /* 0x0068-0x007c: Reserved */
-#define SAM3U_MATRIX_PRAS_OFFSET(n) (0x0080+((n)<<3))
-#define SAM3U_MATRIX_PRAS0_OFFSET 0x0080 /* Priority Register A for Slave 0 */
- /* 0x0084: Reserved */
-#define SAM3U_MATRIX_PRAS1_OFFSET 0x0088 /* Priority Register A for Slave 1 */
- /* 0x008c: Reserved */
-#define SAM3U_MATRIX_PRAS2_OFFSET 0x0090 /* Priority Register A for Slave 2 */
- /* 0x0094: Reserved */
-#define SAM3U_MATRIX_PRAS3_OFFSET 0x0098 /* Priority Register A for Slave 3 */
- /* 0x009c: Reserved */
-#define SAM3U_MATRIX_PRAS4_OFFSET 0x00a0 /* Priority Register A for Slave 4 */
- /* 0x00a4: Reserved */
-#define SAM3U_MATRIX_PRAS5_OFFSET 0x00a8 /* Priority Register A for Slave 5 */
- /* 0x00ac: Reserved */
-#define SAM3U_MATRIX_PRAS6_OFFSET 0x00b0 /* Priority Register A for Slave 6 */
- /* 0x00b4: Reserved */
-#define SAM3U_MATRIX_PRAS7_OFFSET 0x00b8 /* Priority Register A for Slave 7 */
- /* 0x00bc: Reserved */
-#define SAM3U_MATRIX_PRAS8_OFFSET 0x00c0 /* Priority Register A for Slave 8 */
- /* 0x00c4: Reserved */
-#define SAM3U_MATRIX_PRAS9_OFFSET 0x00c8 /* Priority Register A for Slave 9 */
- /* 0x00cc-0x00fc: Reserved */
-#define SAM3U_MATRIX_MRCR_OFFSET 0x0100 /* Master Remap Control Register */
- /* 0x0104-0x010c: Reserved */
-#define SAM3U_MATRIX_WPMR_OFFSET 0x01e4 /* Write Protect Mode Register */
-#define SAM3U_MATRIX_WPSR_OFFSET 0x01e8 /* Write Protect Status Register */
- /* 0x0110 - 0x01fc: Reserved */
-
-/* MATRIX register adresses *************************************************************/
-
-#define SAM3U_MATRIX_MCFG(n)) (SAM3U_MATRIX_BASE+SAM3U_MATRIX_MCFG_OFFSET(n))
-#define SAM3U_MATRIX_MCFG0 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_MCFG0_OFFSET)
-#define SAM3U_MATRIX_MCFG1 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_MCFG1_OFFSET)
-#define SAM3U_MATRIX_MCFG2 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_MCFG2_OFFSET)
-#define SAM3U_MATRIX_MCFG3 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_MCFG3_OFFSET)
-#define SAM3U_MATRIX_MCFG4 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_MCFG4_OFFSET)
-
-#define SAM3U_MATRIX_SCFG(n) (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG_OFFSET(n))
-#define SAM3U_MATRIX_SCFG0 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG0_OFFSET)
-#define SAM3U_MATRIX_SCFG1 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG1_OFFSET)
-#define SAM3U_MATRIX_SCFG2 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG2_OFFSET)
-#define SAM3U_MATRIX_SCFG3 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG3_OFFSET)
-#define SAM3U_MATRIX_SCFG4 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG4_OFFSET)
-#define SAM3U_MATRIX_SCFG5 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG5_OFFSET)
-#define SAM3U_MATRIX_SCFG6 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG6_OFFSET)
-#define SAM3U_MATRIX_SCFG7 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG7_OFFSET)
-#define SAM3U_MATRIX_SCFG8 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG8_OFFSET)
-#define SAM3U_MATRIX_SCFG9 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG9_OFFSET)
-
-#define SAM3U_MATRIX_PRAS(n) (SAM3U_MATRIX_BASE+SAM3U_MATRIX_PRAS_OFFSET(n))
-#define SAM3U_MATRIX_PRAS0 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_PRAS0_OFFSET)
-#define SAM3U_MATRIX_PRAS1 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_PRAS1_OFFSET)
-#define SAM3U_MATRIX_PRAS2 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_PRAS2_OFFSET)
-#define SAM3U_MATRIX_PRAS3 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_PRAS3_OFFSET)
-#define SAM3U_MATRIX_PRAS4 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_PRAS4_OFFSET)
-#define SAM3U_MATRIX_PRAS5 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_PRAS5_OFFSET)
-#define SAM3U_MATRIX_PRAS6 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_PRAS6_OFFSET)
-#define SAM3U_MATRIX_PRAS7 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_PRAS7_OFFSET)
-#define SAM3U_MATRIX_PRAS8 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_PRAS8_OFFSET)
-#define SAM3U_MATRIX_PRAS9 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_PRAS9_OFFSET)
-
-#define SAM3U_MATRIX_MRCR (SAM3U_MATRIX_BASE+SAM3U_MATRIX_MRCR_OFFSET)
-#define SAM3U_MATRIX_WPMR (SAM3U_MATRIX_BASE+SAM3U_MATRIX_WPMR_OFFSET)
-#define SAM3U_MATRIX_WPSR (SAM3U_MATRIX_BASE+SAM3U_MATRIX_WPSR_OFFSET)
-
-/* MATRIX register bit definitions ******************************************************/
-
-#define MATRIX_MCFG_ULBT_SHIFT (0) /* Bits 0-2: Undefined Length Burst Type */
-#define MATRIX_MCFG_ULBT_MASK (7 << MATRIX_MCFG_ULBT_SHIFT)
-# define MATRIX_MCFG_ULBT_INF (0 << MATRIX_MCFG_ULBT_SHIFT) /* Infinite Length Burst */
-# define MATRIX_MCFG_ULBT_SINGLE (1 << MATRIX_MCFG_ULBT_SHIFT) /* Single Access */
-# define MATRIX_MCFG_ULBT_4BEAT (2 << MATRIX_MCFG_ULBT_SHIFT) /* Four Beat Burst */
-# define MATRIX_MCFG_ULBT_8BEAT (3 << MATRIX_MCFG_ULBT_SHIFT) /* Eight Beat Burst */
-# define MATRIX_MCFG_ULBT_16BEAT (4 << MATRIX_MCFG_ULBT_SHIFT) /* Sixteen Beat Burst */
-
-#define MATRIX_SCFG_SLOTCYCLE_SHIFT (0) /* Bits 0-7: Maximum Number of Allowed Cycles for a Burst */
-#define MATRIX_SCFG_SLOTCYCLE_MASK (0xff << MATRIX_SCFG_SLOTCYCLE_SHIFT)
-#define MATRIX_SCFG_DEFMSTRTYPE_SHIFT (16) /* Bits 16-17: Default Master Type */
-#define MATRIX_SCFG_DEFMSTRTYPE_MASK (3 << MATRIX_SCFG_DEFMSTRTYPE_SHIFT)
-# define MATRIX_SCFG_DEFMSTRTYPE_NONE (0 << MATRIX_SCFG_DEFMSTRTYPE_SHIFT)
-# define MATRIX_SCFG_DEFMSTRTYPE_LAST (1 << MATRIX_SCFG_DEFMSTRTYPE_SHIFT)
-# define MATRIX_SCFG_DEFMSTRTYPE_FIXED (2 << MATRIX_SCFG_DEFMSTRTYPE_SHIFT)
-#define MATRIX_SCFG_FIXEDDEFMSTR_SHIFT (18) /* Bits 18-20: Fixed Default Master */
-#define MATRIX_SCFG_FIXEDDEFMSTR_MASK (7 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT)
-# define MATRIX_SCFG0_FIXEDDEFMSTR_ARMS (1 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT)
-# define MATRIX_SCFG1_FIXEDDEFMSTR_ARMS (1 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT)
-# define MATRIX_SCFG2_FIXEDDEFMSTR_ARMS (1 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT)
-# define MATRIX_SCFG3_FIXEDDEFMSTR_ARMC (0 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT)
-# define MATRIX_SCFG4_FIXEDDEFMSTR_ARMC (0 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT)
-# define MATRIX_SCFG5_FIXEDDEFMSTR_ARMS (1 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT)
-# define MATRIX_SCFG6_FIXEDDEFMSTR_ARMS (1 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT)
-# define MATRIX_SCFG7_FIXEDDEFMSTR_ARMS (1 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT)
-# define MATRIX_SCFG8_FIXEDDEFMSTR_ARMS (1 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT)
-# define MATRIX_SCFG8_FIXEDDEFMSTR_HDMA (4 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT)
-# define MATRIX_SCFG9_FIXEDDEFMSTR_ARMS (1 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT)
-# define MATRIX_SCFG9_FIXEDDEFMSTR_HDMA (4 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT)
-
-#define MATRIX_SCFG_ARBT_SHIFT (24) /* Bits 24-25: Arbitration Type */
-#define MATRIX_SCFG_ARBT_MASK (3 << MATRIX_SCFG_ARBT_SHIFT)
-# define MATRIX_SCFG_ARBT_RR (0 << MATRIX_SCFG_ARBT_SHIFT) /* Round-Robin Arbitration */
-# define MATRIX_SCFG_ARBT_FIXED (1 << MATRIX_SCFG_ARBT_SHIFT) /* Fixed Priority Arbitration */
-
-#define MATRIX_PRAS_MPR_SHIFT(x) ((n)<<2)
-#define MATRIX_PRAS_MPR_MASK(x) (3 << MATRIX_PRAS_MPR_SHIFT(x))
-#define MATRIX_PRAS_M0PR_SHIFT (0) /* Bits 0-1: Master 0 Priority */
-#define MATRIX_PRAS_M0PR_MASK (3 << MATRIX_PRAS_M0PR_SHIFT)
-#define MATRIX_PRAS_M1PR_SHIFT (4) /* Bits 4-5: Master 1 Priority */
-#define MATRIX_PRAS_M1PR_MASK (3 << MATRIX_PRAS_M1PR_SHIFT)
-#define MATRIX_PRAS_M2PR_SHIFT (8) /* Bits 8-9: Master 2 Priority */
-#define MATRIX_PRAS_M2PR_MASK (3 << MATRIX_PRAS_M2PR_SHIFT)
-#define MATRIX_PRAS_M3PR_SHIFT (12) /* Bits 12-13: Master 3 Priority */
-#define MATRIX_PRAS_M3PR_MASK (3 << MATRIX_PRAS_M3PR_SHIFT)
-#define MATRIX_PRAS_M4PR_SHIFT (16) /* Bits 16-17 Master 4 Priority */
-#define MATRIX_PRAS_M4PR_MASK (3 << MATRIX_PRAS_M4PR_SHIFT)
-
-#define MATRIX_MRCR_RCB(x) (1 << (x))
-#define MATRIX_MRCR_RCB0 (1 << 0) /* Bit 0: Remap Command Bit for AHB Master 0 */
-#define MATRIX_MRCR_RCB1 (1 << 1) /* Bit 1: Remap Command Bit for AHB Master 1 */
-#define MATRIX_MRCR_RCB2 (1 << 2) /* Bit 2: Remap Command Bit for AHB Master 2 */
-#define MATRIX_MRCR_RCB3 (1 << 3) /* Bit 3: Remap Command Bit for AHB Master 3 */
-#define MATRIX_MRCR_RCB4 (1 << 4) /* Bit 4: Remap Command Bit for AHB Master 4 */
-
-#define MATRIX_WPMR_WPEN (1 << 0) /* Bit 0: Write Protect Enable */
-#define MATRIX_WPMR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protect KEY (Write-only) */
-#define MATRIX_WPMR_WPKEY_MASK (0x00ffffff << MATRIX_WPMR_WPKEY_SHIFT)
-
-#define MATRIX_WPSR_WPVS (1 << 0) /* Bit 0: Enable Write Protect */
-#define MATRIX_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protect Violation Source */
-#define MATRIX_WPSR_WPVSRC_MASK (0xffff << MATRIX_WPSR_WPVSRC_SHIFT)
-
-/****************************************************************************************
- * Public Types
- ****************************************************************************************/
-
-/****************************************************************************************
- * Public Data
- ****************************************************************************************/
-
-/****************************************************************************************
- * Public Functions
- ****************************************************************************************/
-
-#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_MATRIX_H */
+/**************************************************************************************** + * arch/arm/src/sam3u/sam3u_matric.h + * + * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_MATRIX_H +#define __ARCH_ARM_SRC_SAM3U_SAM3U_MATRIX_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +#include <nuttx/config.h> + +#include "chip.h" +#include "sam3u_memorymap.h" + +/**************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************/ + +/* MATRIX register offsets **************************************************************/ + +#define SAM3U_MATRIX_MCFG_OFFSET(n) ((n)<<2) +#define SAM3U_MATRIX_MCFG0_OFFSET 0x0000 /* Master Configuration Register 0 */ +#define SAM3U_MATRIX_MCFG1_OFFSET 0x0004 /* Master Configuration Register 1 */ +#define SAM3U_MATRIX_MCFG2_OFFSET 0x0008 /* Master Configuration Register 2 */ +#define SAM3U_MATRIX_MCFG3_OFFSET 0x000c /* Master Configuration Register 3 */ +#define SAM3U_MATRIX_MCFG4_OFFSET 0x0010 /* Master Configuration Register 4 */ + /* 0x0014-0x003c: Reserved */ +#define SAM3U_MATRIX_SCFG_OFFSET(n) (0x0040+((n)<<2)) +#define SAM3U_MATRIX_SCFG0_OFFSET 0x0040 /* Slave Configuration Register 0 */ +#define SAM3U_MATRIX_SCFG1_OFFSET 0x0044 /* Slave Configuration Register 1 */ +#define SAM3U_MATRIX_SCFG2_OFFSET 0x0048 /* Slave Configuration Register 2 */ +#define SAM3U_MATRIX_SCFG3_OFFSET 0x004c /* Slave Configuration Register 3 */ +#define SAM3U_MATRIX_SCFG4_OFFSET 0x0050 /* Slave Configuration Register 4 */ +#define SAM3U_MATRIX_SCFG5_OFFSET 0x0054 /* Slave Configuration Register 5 */ +#define SAM3U_MATRIX_SCFG6_OFFSET 0x0058 /* Slave Configuration Register 6 */ +#define SAM3U_MATRIX_SCFG7_OFFSET 0x005c /* Slave Configuration Register 7 */ +#define SAM3U_MATRIX_SCFG8_OFFSET 0x0060 /* Slave Configuration Register 8 */ +#define SAM3U_MATRIX_SCFG9_OFFSET 0x0064 /* Slave Configuration Register 9 */ + /* 0x0068-0x007c: Reserved */ +#define SAM3U_MATRIX_PRAS_OFFSET(n) (0x0080+((n)<<3)) +#define SAM3U_MATRIX_PRAS0_OFFSET 0x0080 /* Priority Register A for Slave 0 */ + /* 0x0084: Reserved */ +#define SAM3U_MATRIX_PRAS1_OFFSET 0x0088 /* Priority Register A for Slave 1 */ + /* 0x008c: Reserved */ +#define SAM3U_MATRIX_PRAS2_OFFSET 0x0090 /* Priority Register A for Slave 2 */ + /* 0x0094: Reserved */ +#define SAM3U_MATRIX_PRAS3_OFFSET 0x0098 /* Priority Register A for Slave 3 */ + /* 0x009c: Reserved */ +#define SAM3U_MATRIX_PRAS4_OFFSET 0x00a0 /* Priority Register A for Slave 4 */ + /* 0x00a4: Reserved */ +#define SAM3U_MATRIX_PRAS5_OFFSET 0x00a8 /* Priority Register A for Slave 5 */ + /* 0x00ac: Reserved */ +#define SAM3U_MATRIX_PRAS6_OFFSET 0x00b0 /* Priority Register A for Slave 6 */ + /* 0x00b4: Reserved */ +#define SAM3U_MATRIX_PRAS7_OFFSET 0x00b8 /* Priority Register A for Slave 7 */ + /* 0x00bc: Reserved */ +#define SAM3U_MATRIX_PRAS8_OFFSET 0x00c0 /* Priority Register A for Slave 8 */ + /* 0x00c4: Reserved */ +#define SAM3U_MATRIX_PRAS9_OFFSET 0x00c8 /* Priority Register A for Slave 9 */ + /* 0x00cc-0x00fc: Reserved */ +#define SAM3U_MATRIX_MRCR_OFFSET 0x0100 /* Master Remap Control Register */ + /* 0x0104-0x010c: Reserved */ +#define SAM3U_MATRIX_WPMR_OFFSET 0x01e4 /* Write Protect Mode Register */ +#define SAM3U_MATRIX_WPSR_OFFSET 0x01e8 /* Write Protect Status Register */ + /* 0x0110 - 0x01fc: Reserved */ + +/* MATRIX register adresses *************************************************************/ + +#define SAM3U_MATRIX_MCFG(n)) (SAM3U_MATRIX_BASE+SAM3U_MATRIX_MCFG_OFFSET(n)) +#define SAM3U_MATRIX_MCFG0 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_MCFG0_OFFSET) +#define SAM3U_MATRIX_MCFG1 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_MCFG1_OFFSET) +#define SAM3U_MATRIX_MCFG2 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_MCFG2_OFFSET) +#define SAM3U_MATRIX_MCFG3 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_MCFG3_OFFSET) +#define SAM3U_MATRIX_MCFG4 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_MCFG4_OFFSET) + +#define SAM3U_MATRIX_SCFG(n) (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG_OFFSET(n)) +#define SAM3U_MATRIX_SCFG0 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG0_OFFSET) +#define SAM3U_MATRIX_SCFG1 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG1_OFFSET) +#define SAM3U_MATRIX_SCFG2 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG2_OFFSET) +#define SAM3U_MATRIX_SCFG3 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG3_OFFSET) +#define SAM3U_MATRIX_SCFG4 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG4_OFFSET) +#define SAM3U_MATRIX_SCFG5 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG5_OFFSET) +#define SAM3U_MATRIX_SCFG6 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG6_OFFSET) +#define SAM3U_MATRIX_SCFG7 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG7_OFFSET) +#define SAM3U_MATRIX_SCFG8 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG8_OFFSET) +#define SAM3U_MATRIX_SCFG9 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG9_OFFSET) + +#define SAM3U_MATRIX_PRAS(n) (SAM3U_MATRIX_BASE+SAM3U_MATRIX_PRAS_OFFSET(n)) +#define SAM3U_MATRIX_PRAS0 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_PRAS0_OFFSET) +#define SAM3U_MATRIX_PRAS1 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_PRAS1_OFFSET) +#define SAM3U_MATRIX_PRAS2 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_PRAS2_OFFSET) +#define SAM3U_MATRIX_PRAS3 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_PRAS3_OFFSET) +#define SAM3U_MATRIX_PRAS4 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_PRAS4_OFFSET) +#define SAM3U_MATRIX_PRAS5 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_PRAS5_OFFSET) +#define SAM3U_MATRIX_PRAS6 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_PRAS6_OFFSET) +#define SAM3U_MATRIX_PRAS7 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_PRAS7_OFFSET) +#define SAM3U_MATRIX_PRAS8 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_PRAS8_OFFSET) +#define SAM3U_MATRIX_PRAS9 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_PRAS9_OFFSET) + +#define SAM3U_MATRIX_MRCR (SAM3U_MATRIX_BASE+SAM3U_MATRIX_MRCR_OFFSET) +#define SAM3U_MATRIX_WPMR (SAM3U_MATRIX_BASE+SAM3U_MATRIX_WPMR_OFFSET) +#define SAM3U_MATRIX_WPSR (SAM3U_MATRIX_BASE+SAM3U_MATRIX_WPSR_OFFSET) + +/* MATRIX register bit definitions ******************************************************/ + +#define MATRIX_MCFG_ULBT_SHIFT (0) /* Bits 0-2: Undefined Length Burst Type */ +#define MATRIX_MCFG_ULBT_MASK (7 << MATRIX_MCFG_ULBT_SHIFT) +# define MATRIX_MCFG_ULBT_INF (0 << MATRIX_MCFG_ULBT_SHIFT) /* Infinite Length Burst */ +# define MATRIX_MCFG_ULBT_SINGLE (1 << MATRIX_MCFG_ULBT_SHIFT) /* Single Access */ +# define MATRIX_MCFG_ULBT_4BEAT (2 << MATRIX_MCFG_ULBT_SHIFT) /* Four Beat Burst */ +# define MATRIX_MCFG_ULBT_8BEAT (3 << MATRIX_MCFG_ULBT_SHIFT) /* Eight Beat Burst */ +# define MATRIX_MCFG_ULBT_16BEAT (4 << MATRIX_MCFG_ULBT_SHIFT) /* Sixteen Beat Burst */ + +#define MATRIX_SCFG_SLOTCYCLE_SHIFT (0) /* Bits 0-7: Maximum Number of Allowed Cycles for a Burst */ +#define MATRIX_SCFG_SLOTCYCLE_MASK (0xff << MATRIX_SCFG_SLOTCYCLE_SHIFT) +#define MATRIX_SCFG_DEFMSTRTYPE_SHIFT (16) /* Bits 16-17: Default Master Type */ +#define MATRIX_SCFG_DEFMSTRTYPE_MASK (3 << MATRIX_SCFG_DEFMSTRTYPE_SHIFT) +# define MATRIX_SCFG_DEFMSTRTYPE_NONE (0 << MATRIX_SCFG_DEFMSTRTYPE_SHIFT) +# define MATRIX_SCFG_DEFMSTRTYPE_LAST (1 << MATRIX_SCFG_DEFMSTRTYPE_SHIFT) +# define MATRIX_SCFG_DEFMSTRTYPE_FIXED (2 << MATRIX_SCFG_DEFMSTRTYPE_SHIFT) +#define MATRIX_SCFG_FIXEDDEFMSTR_SHIFT (18) /* Bits 18-20: Fixed Default Master */ +#define MATRIX_SCFG_FIXEDDEFMSTR_MASK (7 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT) +# define MATRIX_SCFG0_FIXEDDEFMSTR_ARMS (1 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT) +# define MATRIX_SCFG1_FIXEDDEFMSTR_ARMS (1 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT) +# define MATRIX_SCFG2_FIXEDDEFMSTR_ARMS (1 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT) +# define MATRIX_SCFG3_FIXEDDEFMSTR_ARMC (0 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT) +# define MATRIX_SCFG4_FIXEDDEFMSTR_ARMC (0 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT) +# define MATRIX_SCFG5_FIXEDDEFMSTR_ARMS (1 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT) +# define MATRIX_SCFG6_FIXEDDEFMSTR_ARMS (1 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT) +# define MATRIX_SCFG7_FIXEDDEFMSTR_ARMS (1 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT) +# define MATRIX_SCFG8_FIXEDDEFMSTR_ARMS (1 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT) +# define MATRIX_SCFG8_FIXEDDEFMSTR_HDMA (4 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT) +# define MATRIX_SCFG9_FIXEDDEFMSTR_ARMS (1 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT) +# define MATRIX_SCFG9_FIXEDDEFMSTR_HDMA (4 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT) + +#define MATRIX_SCFG_ARBT_SHIFT (24) /* Bits 24-25: Arbitration Type */ +#define MATRIX_SCFG_ARBT_MASK (3 << MATRIX_SCFG_ARBT_SHIFT) +# define MATRIX_SCFG_ARBT_RR (0 << MATRIX_SCFG_ARBT_SHIFT) /* Round-Robin Arbitration */ +# define MATRIX_SCFG_ARBT_FIXED (1 << MATRIX_SCFG_ARBT_SHIFT) /* Fixed Priority Arbitration */ + +#define MATRIX_PRAS_MPR_SHIFT(x) ((n)<<2) +#define MATRIX_PRAS_MPR_MASK(x) (3 << MATRIX_PRAS_MPR_SHIFT(x)) +#define MATRIX_PRAS_M0PR_SHIFT (0) /* Bits 0-1: Master 0 Priority */ +#define MATRIX_PRAS_M0PR_MASK (3 << MATRIX_PRAS_M0PR_SHIFT) +#define MATRIX_PRAS_M1PR_SHIFT (4) /* Bits 4-5: Master 1 Priority */ +#define MATRIX_PRAS_M1PR_MASK (3 << MATRIX_PRAS_M1PR_SHIFT) +#define MATRIX_PRAS_M2PR_SHIFT (8) /* Bits 8-9: Master 2 Priority */ +#define MATRIX_PRAS_M2PR_MASK (3 << MATRIX_PRAS_M2PR_SHIFT) +#define MATRIX_PRAS_M3PR_SHIFT (12) /* Bits 12-13: Master 3 Priority */ +#define MATRIX_PRAS_M3PR_MASK (3 << MATRIX_PRAS_M3PR_SHIFT) +#define MATRIX_PRAS_M4PR_SHIFT (16) /* Bits 16-17 Master 4 Priority */ +#define MATRIX_PRAS_M4PR_MASK (3 << MATRIX_PRAS_M4PR_SHIFT) + +#define MATRIX_MRCR_RCB(x) (1 << (x)) +#define MATRIX_MRCR_RCB0 (1 << 0) /* Bit 0: Remap Command Bit for AHB Master 0 */ +#define MATRIX_MRCR_RCB1 (1 << 1) /* Bit 1: Remap Command Bit for AHB Master 1 */ +#define MATRIX_MRCR_RCB2 (1 << 2) /* Bit 2: Remap Command Bit for AHB Master 2 */ +#define MATRIX_MRCR_RCB3 (1 << 3) /* Bit 3: Remap Command Bit for AHB Master 3 */ +#define MATRIX_MRCR_RCB4 (1 << 4) /* Bit 4: Remap Command Bit for AHB Master 4 */ + +#define MATRIX_WPMR_WPEN (1 << 0) /* Bit 0: Write Protect Enable */ +#define MATRIX_WPMR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protect KEY (Write-only) */ +#define MATRIX_WPMR_WPKEY_MASK (0x00ffffff << MATRIX_WPMR_WPKEY_SHIFT) + +#define MATRIX_WPSR_WPVS (1 << 0) /* Bit 0: Enable Write Protect */ +#define MATRIX_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protect Violation Source */ +#define MATRIX_WPSR_WPVSRC_MASK (0xffff << MATRIX_WPSR_WPVSRC_SHIFT) + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +/**************************************************************************************** + * Public Data + ****************************************************************************************/ + +/**************************************************************************************** + * Public Functions + ****************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_MATRIX_H */ diff --git a/nuttx/arch/arm/src/sam3u/sam3u_memorymap.h b/nuttx/arch/arm/src/sam3u/sam3u_memorymap.h index b38864ae5..81027f7b4 100644 --- a/nuttx/arch/arm/src/sam3u/sam3u_memorymap.h +++ b/nuttx/arch/arm/src/sam3u/sam3u_memorymap.h @@ -1,145 +1,145 @@ -/************************************************************************************************
- * arch/arm/src/sam3u/sam3u_memorymap.h
- *
- * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_MEMORYMAP_H
-#define __ARCH_ARM_SRC_SAM3U_SAM3U_MEMORYMAP_H
-
-/************************************************************************************************
- * Included Files
- ************************************************************************************************/
-
-#include <nuttx/config.h>
-#include "chip.h"
-
-/************************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************************/
-
-#define SAM3U_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: Code space */
-# define SAM3U_BOOTMEMORY_BASE 0x00000000 /* 0x00000000-0x0007ffff: Boot Memory */
-# define SAM3U_INTFLASH0_BASE 0x00080000 /* 0x00080000-0x000fffff: Internal FLASH 0 */
-# define SAM3U_INTFLASH1_BASE 0x00100000 /* 0x00100000-0x0017ffff: Internal FLASH 1 */
-# define SAM3U_INTROM_BASE 0x00180000 /* 0x00180000-0x001fffff: Internal ROM */
- /* 0x00200000-0x1fffffff: Reserved */
-#define SAM3U_INTSRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: Internal SRAM */
-# define SAM3U_INTSRAM0_BASE 0x20000000 /* 0x20000000-0x2007ffff: SRAM0 (see chip.h) */
-# define SAM3U_INTSRAM1_BASE 0x20080000 /* 0x20080000-0x200fffff: SRAM1 (see chip.h) */
-# define SAM3U_NFCSRAM_BASE 0x20100000 /* 0x20100000-0x207fffff: NAND FLASH controller (SRAM) */
-# define SAM3U_UDPHPSDMS_BASE 0x20180000 /* 0x20180000-0x201fffff: USB Device High Speed (DMA) */
- /* 0x20200000-0x2fffffff: Undefined */
-# define SAM3U_BBSRAM_BASE 0x22000000 /* 0x22000000-0x23ffffff: 32Mb bit-band alias */
- /* 0x24000000-0x3fffffff: Undefined */
-#define SAM3U_PERIPHERALS_BASE 0x40000000 /* 0x40000000-0x5fffffff: Peripherals */
-# define SAM3U_MCI_BASE 0x40000000 /* 0x40000000-0x400003ff: High Speed Multimedia Card Interface */
-# define SAM3U_SSC_BASE 0x40004000 /* 0x40004000-0x40007fff: Synchronous Serial Controller */
-# define SAM3U_SPI_BASE 0x40008000 /* 0x40008000-0x4000bfff: Serial Peripheral Interface */
- /* 0x4000c000-0x4007ffff: Reserved */
-# define SAM3U_TC_BASE 0x40080000 /* 0x40080000-0x40083fff: Timer Counters */
-# define SAM3U_TCN_BASE(n) (0x40080000+((n)<<6))
-# define SAM3U_TC0_BASE 0x40080000 /* 0x40080000-0x4008003f: Timer Counter 0 */
-# define SAM3U_TC1_BASE 0x40080040 /* 0x40080040-0x4008007f: Timer Counter 1 */
-# define SAM3U_TC2_BASE 0x40080080 /* 0x40080080-0x400800bf: Timer Counter 2 */
-# define SAM3U_TWI_BASE 0x40084000 /* 0x40084000-0x4008ffff: Two-Wire Interface */
-# define SAM3U_TWIN_BASE(n) (0x40084000+((n)<<14))
-# define SAM3U_TWI0_BASE 0x40084000 /* 0x40084000-0x40087fff: Two-Wire Interface 0 */
-# define SAM3U_TWI1_BASE 0x40088000 /* 0x40088000-0x4008bfff: Two-Wire Interface 1 */
-# define SAM3U_PWM_BASE 0x4008c000 /* 0x4008c000-0x4008ffff: Pulse Width Modulation Controller */
-# define SAM3U_USART_BASE 0x40090000 /* 0x40090000-0x4009ffff: USART */
-# define SAM3U_USARTN_BASE(n) (0x40090000+((n)<<14))
-# define SAM3U_USART0_BASE 0x40090000 /* 0x40090000-0x40093fff: USART0 */
-# define SAM3U_USART1_BASE 0x40094000 /* 0x40094000-0x40097fff: USART1 */
-# define SAM3U_USART2_BASE 0x40098000 /* 0x40098000-0x4009bfff: USART2 */
-# define SAM3U_USART3_BASE 0x4009c000 /* 0x4009c000-0x4009ffff: USART3 */
- /* 0x400a0000-0x400a3fff: Reserved */
-# define SAM3U_UDPHS_BASE 0x400a4000 /* 0x400a4000-0x400a7fff: USB Device High Speed */
-# define SAM3U_ADC12B_BASE 0x400a8000 /* 0x400a8000-0x400abfff: 12-bit ADC Controller */
-# define SAM3U_ADC_BASE 0x400ac000 /* 0x400ac000-0x400affff: 10-bit ADC Controller */
-# define SAM3U_DMAC_BASE 0x400b0000 /* 0x400b0000-0x400b3fff: DMA controller */
- /* 0x400b4000-0x400dffff: Reserved */
-# define SAM3U_SYSCTRLR_BASE 0x400e0000 /* 0x400e0000-0x400e25ff: System controller */
- /* 0x400e2600-0x400fffff: Reserved */
- /* 0x40100000-0x41ffffff: Reserved */
-# define SAM3U_BBPERIPH__BASE 0x42000000 /* 0x42000000-0x43ffffff: 32Mb bit-band alias */
- /* 0x44000000-0x5fffffff: Reserved */
-#define SAM3U_EXTSRAM_BASE 0x60000000 /* 0x60000000-0x9fffffff: External SRAM */
-# define SAM3U_EXTCS_BASE 0x60000000 /* 0x60000000-0x63ffffff: Chip selects */
-# define SAM3U_EXTCSN_BASE(n) (0x60000000*((n)<<24))
-# define SAM3U_EXTCS0_BASE 0x60000000 /* 0x60000000-0x60ffffff: Chip select 0 */
-# define SAM3U_EXTCS1_BASE 0x61000000 /* 0x61000000-0x601fffff: Chip select 1 */
-# define SAM3U_EXTCS2_BASE 0x62000000 /* 0x62000000-0x62ffffff: Chip select 2 */
-# define SAM3U_EXTCS3_BASE 0x63000000 /* 0x63000000-0x63ffffff: Chip select 3 */
- /* 0x64000000-0x67ffffff: Reserved */
-# define SAM3U_NFC_BASE 0x68000000 /* 0x68000000-0x68ffffff: NAND FLASH controller */
- /* 0x69000000-0x9fffffff: Reserved */
- /* 0xa0000000-0xdfffffff: Reserved */
-#define SAM3U_SYSTEM_BASE 0xe0000000 /* 0xe0000000-0xffffffff: System */
-
-/* System Controller Register Blocks: 0x400e0000-0x4007ffff */
-
-#define SAM3U_SMC_BASE 0x400e0000 /* 0x400e0000-0x400e01ff: Static Memory Controller */
-#define SAM3U_MATRIX_BASE 0x400e0200 /* 0x400e0200-0x400e03ff: MATRIX */
-#define SAM3U_PMC_BASE 0x400e0400 /* 0x400e0400-0x400e05ff: Power Management Controller */
-#define SAM3U_UART_BASE 0x400e0600 /* 0x400e0600-0x400e073f: UART */
-#define SAM3U_CHIPID_BASE 0x400e0740 /* 0x400e0740-0x400e07ff: CHIP ID */
-#define SAM3U_EEFC_BASE 0x400e0800 /* 0x400e0800-0x400e0bff: Enhanced Embedded Flash Controllers*/
-# define SAM3U_EEFCN_BASE(n) (0x400e0800+((n)<<9))
-# define SAM3U_EEFC0_BASE 0x400e0800 /* 0x400e0800-0x400e09ff: Enhanced Embedded Flash Controller 0 */
-# define SAM3U_EEFC1_BASE 0x400e0a00 /* 0x400e0a00-0x400e0bff: Enhanced Embedded Flash Controller 1 */
-#define SAM3U_PIO_BASE 0x400e0c00 /* 0x400e0c00-0x400e11ff: Parallel I/O Controllers */
-# define SAM3U_PION_BASE(n) (0x400e0c00+((n)<<9))
-# define SAM3U_PIOA_BASE 0x400e0c00 /* 0x400e0c00-0x400e0dff: Parallel I/O Controller A */
-# define SAM3U_PIOB_BASE 0x400e0e00 /* 0x400e0e00-0x400e0fff: Parallel I/O Controller B */
-# define SAM3U_PIOC_BASE 0x400e1000 /* 0x400e1000-0x400e11ff: Parallel I/O Controller C */
-#define SAM3U_RSTC_BASE 0x400e1200 /* 0x400e1200-0x400e120f: Reset Controller */
-#define SAM3U_SUPC_BASE 0x400e1210 /* 0x400e1210-0x400e122f: Supply Controller */
-#define SAM3U_RTT_BASE 0x400e1230 /* 0x400e1230-0x400e124f: Real Time Timer */
-#define SAM3U_WDT_BASE 0x400e1250 /* 0x400e1250-0x400e125f: Watchdog Timer */
-#define SAM3U_RTC_BASE 0x400e1260 /* 0x400e1260-0x400e128f: Real Time Clock */
-#define SAM3U_GPBR_BASE 0x400e1290 /* 0x400e1290-0x400e13ff: GPBR */
- /* 0x490e1400-0x4007ffff: Reserved */
-
-/************************************************************************************************
- * Public Types
- ************************************************************************************************/
-
-/************************************************************************************************
- * Public Data
- ************************************************************************************************/
-
-/************************************************************************************************
- * Public Functions
- ************************************************************************************************/
-
-#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_MEMORYMAP_H */
+/************************************************************************************************ + * arch/arm/src/sam3u/sam3u_memorymap.h + * + * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_MEMORYMAP_H +#define __ARCH_ARM_SRC_SAM3U_SAM3U_MEMORYMAP_H + +/************************************************************************************************ + * Included Files + ************************************************************************************************/ + +#include <nuttx/config.h> +#include "chip.h" + +/************************************************************************************************ + * Pre-processor Definitions + ************************************************************************************************/ + +#define SAM3U_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: Code space */ +# define SAM3U_BOOTMEMORY_BASE 0x00000000 /* 0x00000000-0x0007ffff: Boot Memory */ +# define SAM3U_INTFLASH0_BASE 0x00080000 /* 0x00080000-0x000fffff: Internal FLASH 0 */ +# define SAM3U_INTFLASH1_BASE 0x00100000 /* 0x00100000-0x0017ffff: Internal FLASH 1 */ +# define SAM3U_INTROM_BASE 0x00180000 /* 0x00180000-0x001fffff: Internal ROM */ + /* 0x00200000-0x1fffffff: Reserved */ +#define SAM3U_INTSRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: Internal SRAM */ +# define SAM3U_INTSRAM0_BASE 0x20000000 /* 0x20000000-0x2007ffff: SRAM0 (see chip.h) */ +# define SAM3U_INTSRAM1_BASE 0x20080000 /* 0x20080000-0x200fffff: SRAM1 (see chip.h) */ +# define SAM3U_NFCSRAM_BASE 0x20100000 /* 0x20100000-0x207fffff: NAND FLASH controller (SRAM) */ +# define SAM3U_UDPHPSDMS_BASE 0x20180000 /* 0x20180000-0x201fffff: USB Device High Speed (DMA) */ + /* 0x20200000-0x2fffffff: Undefined */ +# define SAM3U_BBSRAM_BASE 0x22000000 /* 0x22000000-0x23ffffff: 32Mb bit-band alias */ + /* 0x24000000-0x3fffffff: Undefined */ +#define SAM3U_PERIPHERALS_BASE 0x40000000 /* 0x40000000-0x5fffffff: Peripherals */ +# define SAM3U_MCI_BASE 0x40000000 /* 0x40000000-0x400003ff: High Speed Multimedia Card Interface */ +# define SAM3U_SSC_BASE 0x40004000 /* 0x40004000-0x40007fff: Synchronous Serial Controller */ +# define SAM3U_SPI_BASE 0x40008000 /* 0x40008000-0x4000bfff: Serial Peripheral Interface */ + /* 0x4000c000-0x4007ffff: Reserved */ +# define SAM3U_TC_BASE 0x40080000 /* 0x40080000-0x40083fff: Timer Counters */ +# define SAM3U_TCN_BASE(n) (0x40080000+((n)<<6)) +# define SAM3U_TC0_BASE 0x40080000 /* 0x40080000-0x4008003f: Timer Counter 0 */ +# define SAM3U_TC1_BASE 0x40080040 /* 0x40080040-0x4008007f: Timer Counter 1 */ +# define SAM3U_TC2_BASE 0x40080080 /* 0x40080080-0x400800bf: Timer Counter 2 */ +# define SAM3U_TWI_BASE 0x40084000 /* 0x40084000-0x4008ffff: Two-Wire Interface */ +# define SAM3U_TWIN_BASE(n) (0x40084000+((n)<<14)) +# define SAM3U_TWI0_BASE 0x40084000 /* 0x40084000-0x40087fff: Two-Wire Interface 0 */ +# define SAM3U_TWI1_BASE 0x40088000 /* 0x40088000-0x4008bfff: Two-Wire Interface 1 */ +# define SAM3U_PWM_BASE 0x4008c000 /* 0x4008c000-0x4008ffff: Pulse Width Modulation Controller */ +# define SAM3U_USART_BASE 0x40090000 /* 0x40090000-0x4009ffff: USART */ +# define SAM3U_USARTN_BASE(n) (0x40090000+((n)<<14)) +# define SAM3U_USART0_BASE 0x40090000 /* 0x40090000-0x40093fff: USART0 */ +# define SAM3U_USART1_BASE 0x40094000 /* 0x40094000-0x40097fff: USART1 */ +# define SAM3U_USART2_BASE 0x40098000 /* 0x40098000-0x4009bfff: USART2 */ +# define SAM3U_USART3_BASE 0x4009c000 /* 0x4009c000-0x4009ffff: USART3 */ + /* 0x400a0000-0x400a3fff: Reserved */ +# define SAM3U_UDPHS_BASE 0x400a4000 /* 0x400a4000-0x400a7fff: USB Device High Speed */ +# define SAM3U_ADC12B_BASE 0x400a8000 /* 0x400a8000-0x400abfff: 12-bit ADC Controller */ +# define SAM3U_ADC_BASE 0x400ac000 /* 0x400ac000-0x400affff: 10-bit ADC Controller */ +# define SAM3U_DMAC_BASE 0x400b0000 /* 0x400b0000-0x400b3fff: DMA controller */ + /* 0x400b4000-0x400dffff: Reserved */ +# define SAM3U_SYSCTRLR_BASE 0x400e0000 /* 0x400e0000-0x400e25ff: System controller */ + /* 0x400e2600-0x400fffff: Reserved */ + /* 0x40100000-0x41ffffff: Reserved */ +# define SAM3U_BBPERIPH__BASE 0x42000000 /* 0x42000000-0x43ffffff: 32Mb bit-band alias */ + /* 0x44000000-0x5fffffff: Reserved */ +#define SAM3U_EXTSRAM_BASE 0x60000000 /* 0x60000000-0x9fffffff: External SRAM */ +# define SAM3U_EXTCS_BASE 0x60000000 /* 0x60000000-0x63ffffff: Chip selects */ +# define SAM3U_EXTCSN_BASE(n) (0x60000000*((n)<<24)) +# define SAM3U_EXTCS0_BASE 0x60000000 /* 0x60000000-0x60ffffff: Chip select 0 */ +# define SAM3U_EXTCS1_BASE 0x61000000 /* 0x61000000-0x601fffff: Chip select 1 */ +# define SAM3U_EXTCS2_BASE 0x62000000 /* 0x62000000-0x62ffffff: Chip select 2 */ +# define SAM3U_EXTCS3_BASE 0x63000000 /* 0x63000000-0x63ffffff: Chip select 3 */ + /* 0x64000000-0x67ffffff: Reserved */ +# define SAM3U_NFC_BASE 0x68000000 /* 0x68000000-0x68ffffff: NAND FLASH controller */ + /* 0x69000000-0x9fffffff: Reserved */ + /* 0xa0000000-0xdfffffff: Reserved */ +#define SAM3U_SYSTEM_BASE 0xe0000000 /* 0xe0000000-0xffffffff: System */ + +/* System Controller Register Blocks: 0x400e0000-0x4007ffff */ + +#define SAM3U_SMC_BASE 0x400e0000 /* 0x400e0000-0x400e01ff: Static Memory Controller */ +#define SAM3U_MATRIX_BASE 0x400e0200 /* 0x400e0200-0x400e03ff: MATRIX */ +#define SAM3U_PMC_BASE 0x400e0400 /* 0x400e0400-0x400e05ff: Power Management Controller */ +#define SAM3U_UART_BASE 0x400e0600 /* 0x400e0600-0x400e073f: UART */ +#define SAM3U_CHIPID_BASE 0x400e0740 /* 0x400e0740-0x400e07ff: CHIP ID */ +#define SAM3U_EEFC_BASE 0x400e0800 /* 0x400e0800-0x400e0bff: Enhanced Embedded Flash Controllers*/ +# define SAM3U_EEFCN_BASE(n) (0x400e0800+((n)<<9)) +# define SAM3U_EEFC0_BASE 0x400e0800 /* 0x400e0800-0x400e09ff: Enhanced Embedded Flash Controller 0 */ +# define SAM3U_EEFC1_BASE 0x400e0a00 /* 0x400e0a00-0x400e0bff: Enhanced Embedded Flash Controller 1 */ +#define SAM3U_PIO_BASE 0x400e0c00 /* 0x400e0c00-0x400e11ff: Parallel I/O Controllers */ +# define SAM3U_PION_BASE(n) (0x400e0c00+((n)<<9)) +# define SAM3U_PIOA_BASE 0x400e0c00 /* 0x400e0c00-0x400e0dff: Parallel I/O Controller A */ +# define SAM3U_PIOB_BASE 0x400e0e00 /* 0x400e0e00-0x400e0fff: Parallel I/O Controller B */ +# define SAM3U_PIOC_BASE 0x400e1000 /* 0x400e1000-0x400e11ff: Parallel I/O Controller C */ +#define SAM3U_RSTC_BASE 0x400e1200 /* 0x400e1200-0x400e120f: Reset Controller */ +#define SAM3U_SUPC_BASE 0x400e1210 /* 0x400e1210-0x400e122f: Supply Controller */ +#define SAM3U_RTT_BASE 0x400e1230 /* 0x400e1230-0x400e124f: Real Time Timer */ +#define SAM3U_WDT_BASE 0x400e1250 /* 0x400e1250-0x400e125f: Watchdog Timer */ +#define SAM3U_RTC_BASE 0x400e1260 /* 0x400e1260-0x400e128f: Real Time Clock */ +#define SAM3U_GPBR_BASE 0x400e1290 /* 0x400e1290-0x400e13ff: GPBR */ + /* 0x490e1400-0x4007ffff: Reserved */ + +/************************************************************************************************ + * Public Types + ************************************************************************************************/ + +/************************************************************************************************ + * Public Data + ************************************************************************************************/ + +/************************************************************************************************ + * Public Functions + ************************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_MEMORYMAP_H */ diff --git a/nuttx/arch/arm/src/sam3u/sam3u_mpuinit.c b/nuttx/arch/arm/src/sam3u/sam3u_mpuinit.c index beff4d43b..c6788d3b5 100644 --- a/nuttx/arch/arm/src/sam3u/sam3u_mpuinit.c +++ b/nuttx/arch/arm/src/sam3u/sam3u_mpuinit.c @@ -2,7 +2,7 @@ * arch/arm/src/common/sam3u_mpuinit.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/sam3u/sam3u_pdc.h b/nuttx/arch/arm/src/sam3u/sam3u_pdc.h index 3520d74c3..106b2cd91 100644 --- a/nuttx/arch/arm/src/sam3u/sam3u_pdc.h +++ b/nuttx/arch/arm/src/sam3u/sam3u_pdc.h @@ -1,103 +1,103 @@ -/****************************************************************************************
- * arch/arm/src/sam3u/sam3u_pdc.h
- *
- * Copyright (C) 2009 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_PDC_H
-#define __ARCH_ARM_SRC_SAM3U_SAM3U_PDC_H
-
-/****************************************************************************************
- * Included Files
- ****************************************************************************************/
-
-#include <nuttx/config.h>
-
-#include "chip.h"
-#include "sam3u_memorymap.h"
-
-/****************************************************************************************
- * Pre-processor Definitions
- ****************************************************************************************/
-
-/* PDC register offsets *****************************************************************/
-
-#define SAM3U_PDC_RPR_OFFSET 0x100 /* Receive Pointer Register */
-#define SAM3U_PDC_RCR_OFFSET 0x104 /* Receive Counter Register */
-#define SAM3U_PDC_TPR_OFFSET 0x108 /* Transmit Pointer Register */
-#define SAM3U_PDC_TCR_OFFSET 0x10c /* Transmit Counter Register */
-#define SAM3U_PDC_RNPR_OFFSET 0x110 /* Receive Next Pointer Register */
-#define SAM3U_PDC_RNCR_OFFSET 0x114 /* Receive Next Counter Register */
-#define SAM3U_PDC_TNPR_OFFSET 0x118 /* Transmit Next Pointer Register */
-#define SAM3U_PDC_TNCR_OFFSET 0x11c /* Transmit Next Counter Register */
-#define SAM3U_PDC_PTCR_OFFSET 0x120 /* Transfer Control Register */
-#define SAM3U_PDC_PTSR_OFFSET 0x124 /* Transfer Status Register */
-
-/* PDC register adresses ****************************************************************/
-
-/* These 10 registers are mapped in the peripheral memory space at the same offset. */
-
-/* PDC register bit definitions *********************************************************/
-
-#define PDC_RCR_RXCTR_SHIFT (0) /* Bits 0-15: Receive Counter Register */
-#define PDC_RCR_RXCTR_MASK (0xffff << PDC_RCR_RXCTR_SHIFT)
-
-#define PDC_TCR_TXCTR_SHIFT (0) /* Bits 0-15: Transmit Counter Register */
-#define PDC_TCR_TXCTR_MASK (0xffff << PDC_TCR_TXCTR_SHIFT)
-
-#define PDC_RNCR_RXNCTR_SHIFT (0) /* Bits 0-15: Receive Next Counter */
-#define PDC_RNCR_RXNCTR_MASK (0xffff << PDC_RNCR_RXNCTR_SHIFT)
-
-#define PDC_TNCR_TXNCTR_SHIFT (0) /* Bits 0-15: Transmit Counter Next */
-#define PDC_TNCR_TXNCTR_MASK (0xffff << PDC_TNCR_TXNCTR_SHIFT)
-
-#define PDC_PTCR_RXTEN (1 << 0) /* Bit 0: Receiver Transfer Enable */
-#define PDC_PTCR_RXTDIS (1 << 1) /* Bit 1: Receiver Transfer Disable */
-#define PDC_PTCR_TXTEN (1 << 8) /* Bit 8: Transmitter Transfer Enable */
-#define PDC_PTCR_TXTDIS (1 << 9) /* Bit 9: Transmitter Transfer Disable */
-
-#define PDC_PTSR_RXTEN (1 << 0) /* Bit 0: Receiver Transfer Enable */
-#define PDC_PTSR_TXTEN (1 << 8) /* Bit 8: Transmitter Transfer Enable */
-
-/****************************************************************************************
- * Public Types
- ****************************************************************************************/
-
-/****************************************************************************************
- * Public Data
- ****************************************************************************************/
-
-/****************************************************************************************
- * Public Functions
- ****************************************************************************************/
-
-#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_PDC_H */
+/**************************************************************************************** + * arch/arm/src/sam3u/sam3u_pdc.h + * + * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_PDC_H +#define __ARCH_ARM_SRC_SAM3U_SAM3U_PDC_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +#include <nuttx/config.h> + +#include "chip.h" +#include "sam3u_memorymap.h" + +/**************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************/ + +/* PDC register offsets *****************************************************************/ + +#define SAM3U_PDC_RPR_OFFSET 0x100 /* Receive Pointer Register */ +#define SAM3U_PDC_RCR_OFFSET 0x104 /* Receive Counter Register */ +#define SAM3U_PDC_TPR_OFFSET 0x108 /* Transmit Pointer Register */ +#define SAM3U_PDC_TCR_OFFSET 0x10c /* Transmit Counter Register */ +#define SAM3U_PDC_RNPR_OFFSET 0x110 /* Receive Next Pointer Register */ +#define SAM3U_PDC_RNCR_OFFSET 0x114 /* Receive Next Counter Register */ +#define SAM3U_PDC_TNPR_OFFSET 0x118 /* Transmit Next Pointer Register */ +#define SAM3U_PDC_TNCR_OFFSET 0x11c /* Transmit Next Counter Register */ +#define SAM3U_PDC_PTCR_OFFSET 0x120 /* Transfer Control Register */ +#define SAM3U_PDC_PTSR_OFFSET 0x124 /* Transfer Status Register */ + +/* PDC register adresses ****************************************************************/ + +/* These 10 registers are mapped in the peripheral memory space at the same offset. */ + +/* PDC register bit definitions *********************************************************/ + +#define PDC_RCR_RXCTR_SHIFT (0) /* Bits 0-15: Receive Counter Register */ +#define PDC_RCR_RXCTR_MASK (0xffff << PDC_RCR_RXCTR_SHIFT) + +#define PDC_TCR_TXCTR_SHIFT (0) /* Bits 0-15: Transmit Counter Register */ +#define PDC_TCR_TXCTR_MASK (0xffff << PDC_TCR_TXCTR_SHIFT) + +#define PDC_RNCR_RXNCTR_SHIFT (0) /* Bits 0-15: Receive Next Counter */ +#define PDC_RNCR_RXNCTR_MASK (0xffff << PDC_RNCR_RXNCTR_SHIFT) + +#define PDC_TNCR_TXNCTR_SHIFT (0) /* Bits 0-15: Transmit Counter Next */ +#define PDC_TNCR_TXNCTR_MASK (0xffff << PDC_TNCR_TXNCTR_SHIFT) + +#define PDC_PTCR_RXTEN (1 << 0) /* Bit 0: Receiver Transfer Enable */ +#define PDC_PTCR_RXTDIS (1 << 1) /* Bit 1: Receiver Transfer Disable */ +#define PDC_PTCR_TXTEN (1 << 8) /* Bit 8: Transmitter Transfer Enable */ +#define PDC_PTCR_TXTDIS (1 << 9) /* Bit 9: Transmitter Transfer Disable */ + +#define PDC_PTSR_RXTEN (1 << 0) /* Bit 0: Receiver Transfer Enable */ +#define PDC_PTSR_TXTEN (1 << 8) /* Bit 8: Transmitter Transfer Enable */ + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +/**************************************************************************************** + * Public Data + ****************************************************************************************/ + +/**************************************************************************************** + * Public Functions + ****************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_PDC_H */ diff --git a/nuttx/arch/arm/src/sam3u/sam3u_pio.h b/nuttx/arch/arm/src/sam3u/sam3u_pio.h index ab20ace9b..b55197ae1 100644 --- a/nuttx/arch/arm/src/sam3u/sam3u_pio.h +++ b/nuttx/arch/arm/src/sam3u/sam3u_pio.h @@ -1,324 +1,324 @@ -/****************************************************************************************
- * arch/arm/src/sam3u/sam3u_pio.h
- *
- * Copyright (C) 2009 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_PIO_H
-#define __ARCH_ARM_SRC_SAM3U_SAM3U_PIO_H
-
-/****************************************************************************************
- * Included Files
- ****************************************************************************************/
-
-#include <nuttx/config.h>
-
-#include "chip.h"
-#include "sam3u_memorymap.h"
-
-/****************************************************************************************
- * Pre-processor Definitions
- ****************************************************************************************/
-
-/* PIO register offsets *****************************************************************/
-
-#define SAM3U_PIO_PER_OFFSET 0x0000 /* PIO Enable Register */
-#define SAM3U_PIO_PDR_OFFSET 0x0004 /* PIO Disable Register */
-#define SAM3U_PIO_PSR_OFFSET 0x0008 /* PIO Status Register */
- /* 0x000c: Reserved */
-#define SAM3U_PIO_OER_OFFSET 0x0010 /* Output Enable Register */
-#define SAM3U_PIO_ODR_OFFSET 0x0014 /* Output Disable Register */
-#define SAM3U_PIO_OSR_OFFSET 0x0018 /* utput Status Register */
- /* 0x001c: Reserved */
-#define SAM3U_PIO_IFER_OFFSET 0x0020 /* Glitch Input Filter Enable Register */
-#define SAM3U_PIO_IFDR_OFFSET 0x0024 /* Glitch Input Filter Disable Register */
-#define SAM3U_PIO_IFSR_OFFSET 0x0028 /* Glitch Input Filter Status Register */
- /* 0x002c: Reserved */
-#define SAM3U_PIO_SODR_OFFSET 0x0030 /* Set Output Data Register */
-#define SAM3U_PIO_CODR_OFFSET 0x0034 /* Clear Output Data Register */
-#define SAM3U_PIO_ODSR_OFFSET 0x0038 /* Output Data Status Register */
-#define SAM3U_PIO_PDSR_OFFSET 0x003c /* Pin Data Status Register */
-#define SAM3U_PIO_IER_OFFSET 0x0040 /* Interrupt Enable Register */
-#define SAM3U_PIO_IDR_OFFSET 0x0044 /* Interrupt Disable Register */
-#define SAM3U_PIO_IMR_OFFSET 0x0048 /* Interrupt Mask Register */
-#define SAM3U_PIO_ISR_OFFSET 0x004c /* Interrupt Status Register */
-#define SAM3U_PIO_MDER_OFFSET 0x0050 /* Multi-driver Enable Register */
-#define SAM3U_PIO_MDDR_OFFSET 0x0054 /* Multi-driver Disable Register */
-#define SAM3U_PIO_MDSR_OFFSET 0x0058 /* Multi-driver Status Register */
- /* 0x005c: Reserved */
-#define SAM3U_PIO_PUDR_OFFSET 0x0060 /* Pull-up Disable Register */
-#define SAM3U_PIO_PUER_OFFSET 0x0064 /* Pull-up Enable Register */
-#define SAM3U_PIO_PUSR_OFFSET 0x0068 /* Pad Pull-up Status Register */
- /* 0x006c: Reserved */
-#define SAM3U_PIO_ABSR_OFFSET 0x0070 /* Peripheral AB Select Register */
- /* 0x0074-0x007c: Reserved */
-#define SAM3U_PIO_SCIFSR_OFFSET 0x0080 /* System Clock Glitch Input Filter Select Register */
-#define SAM3U_PIO_DIFSR_OFFSET 0x0084 /* Debouncing Input Filter Select Register */
-#define SAM3U_PIO_IFDGSR_OFFSET 0x0088 /* Glitch or Debouncing Input Filter Clock Selection Status Register */
-#define SAM3U_PIO_SCDR_OFFSET 0x008c /* Slow Clock Divider Debouncing Register */
- /* 0x0090-0x009c: Reserved */
-#define SAM3U_PIO_OWER_OFFSET 0x00a0 /* Output Write Enable */
-#define SAM3U_PIO_OWDR_OFFSET 0x00a4 /* Output Write Disable */
-#define SAM3U_PIO_OWSR_OFFSET 0x00a8 /* Output Write Status Register */
- /* 0x00ac: Reserved */
-#define SAM3U_PIO_AIMER_OFFSET 0x00b0 /* Additional Interrupt Modes Enable Register */
-#define SAM3U_PIO_AIMDR_OFFSET 0x00b4 /* Additional Interrupt Modes Disables Register */
-#define SAM3U_PIO_AIMMR_OFFSET 0x00b8 /* Additional Interrupt Modes Mask Register */
- /* 0x00bc: Reserved */
-#define SAM3U_PIO_ESR_OFFSET 0x00c0 /* Edge Select Register */
-#define SAM3U_PIO_LSR_OFFSET 0x00c4 /* Level Select Register */
-#define SAM3U_PIO_ELSR_OFFSET 0x00c8 /* Edge/Level Status Register */
- /* 0x00cc: Reserved */
-#define SAM3U_PIO_FELLSR_OFFSET 0x00d0 /* Falling Edge/Low Level Select Register */
-#define SAM3U_PIO_REHLSR_OFFSET 0x00d4 /* Rising Edge/ High Level Select Register */
-#define SAM3U_PIO_FRLHSR_OFFSET 0x00d8 /* Fall/Rise - Low/High Status Register */
- /* 0x00dc: Reserved */
-#define SAM3U_PIO_LOCKSR_OFFSET 0x00e0 /* Lock Status */
-#define SAM3U_PIO_WPMR_OFFSET 0x00e4 /* Write Protect Mode Register */
-#define SAM3U_PIO_WPSR_OFFSET 0x00e8 /* Write Protect Status Register */
- /* 0x00ec-0x00f8: Reserved */
- /* 0x0100-0x0144: Reserved */
-
-/* PIO register adresses ****************************************************************/
-
-#define PIOA (0)
-#define PIOB (1)
-#define PIOC (2)
-#define NPIO (3)
-
-#define SAM3U_PIO_PER(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_PER_OFFSET)
-#define SAM3U_PIO_PDR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_PDR_OFFSET)
-#define SAM3U_PIO_PSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_PSR_OFFSET)
-#define SAM3U_PIO_OER(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_OER_OFFSET)
-#define SAM3U_PIO_ODR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_ODR_OFFSET)
-#define SAM3U_PIO_OSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_OSR_OFFSET)
-#define SAM3U_PIO_IFER(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_IFER_OFFSET)
-#define SAM3U_PIO_IFDR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_IFDR_OFFSET)
-#define SAM3U_PIO_IFSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_IFSR_OFFSET)
-#define SAM3U_PIO_SODR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_SODR_OFFSET)
-#define SAM3U_PIO_CODR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_CODR_OFFSET)
-#define SAM3U_PIO_ODSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_ODSR_OFFSET)
-#define SAM3U_PIO_PDSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_PDSR_OFFSET)
-#define SAM3U_PIO_IER(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_IER_OFFSET)
-#define SAM3U_PIO_IDR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_IDR_OFFSET)
-#define SAM3U_PIO_IMR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_IMR_OFFSET)
-#define SAM3U_PIO_ISR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_ISR_OFFSET)
-#define SAM3U_PIO_MDER(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_MDER_OFFSET)
-#define SAM3U_PIO_MDDR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_MDDR_OFFSET)
-#define SAM3U_PIO_MDSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_MDSR_OFFSET)
-#define SAM3U_PIO_PUDR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_PUDR_OFFSET)
-#define SAM3U_PIO_PUER(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_PUER_OFFSET)
-#define SAM3U_PIO_PUSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_PUSR_OFFSET)
-#define SAM3U_PIO_ABSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_ABSR_OFFSET)
-#define SAM3U_PIO_SCIFSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_SCIFSR_OFFSET)
-#define SAM3U_PIO_DIFSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_DIFSR_OFFSET)
-#define SAM3U_PIO_IFDGSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_IFDGSR_OFFSET)
-#define SAM3U_PIO_SCDR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_SCDR_OFFSET)
-#define SAM3U_PIO_OWER(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_OWER_OFFSET)
-#define SAM3U_PIO_OWDR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_OWDR_OFFSET)
-#define SAM3U_PIO_OWSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_OWSR_OFFSET)
-#define SAM3U_PIO_AIMER(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_AIMER_OFFSET)
-#define SAM3U_PIO_AIMDR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_AIMDR_OFFSET)
-#define SAM3U_PIO_AIMMR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_AIMMR_OFFSET)
-#define SAM3U_PIO_ESR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_ESR_OFFSET)
-#define SAM3U_PIO_LSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_LSR_OFFSET)
-#define SAM3U_PIO_ELSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_ELSR_OFFSET)
-#define SAM3U_PIO_FELLSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_FELLSR_OFFSET)
-#define SAM3U_PIO_REHLSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_REHLSR_OFFSET)
-#define SAM3U_PIO_FRLHSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_FRLHSR_OFFSET)
-#define SAM3U_PIO_LOCKSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_LOCKSR_OFFSET)
-#define SAM3U_PIO_WPMR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_WPMR_OFFSET)
-#define SAM3U_PIO_WPSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_WPSR_OFFSET)
-
-#define SAM3U_PIOA_PER (SAM3U_PIOA_BASE+SAM3U_PIO_PER_OFFSET)
-#define SAM3U_PIOA_PDR_ (SAM3U_PIOA_BASE+SAM3U_PIO_PDR_OFFSET)
-#define SAM3U_PIOA_PSR (SAM3U_PIOA_BASE+SAM3U_PIO_PSR_OFFSET)
-#define SAM3U_PIOA_OER (SAM3U_PIOA_BASE+SAM3U_PIO_OER_OFFSET)
-#define SAM3U_PIOA_ODR (SAM3U_PIOA_BASE+SAM3U_PIO_ODR_OFFSET)
-#define SAM3U_PIOA_OSR (SAM3U_PIOA_BASE+SAM3U_PIO_OSR_OFFSET)
-#define SAM3U_PIOA_IFER (SAM3U_PIOA_BASE+SAM3U_PIO_IFER_OFFSET)
-#define SAM3U_PIOA_IFDR (SAM3U_PIOA_BASE+SAM3U_PIO_IFDR_OFFSET)
-#define SAM3U_PIOA_IFSR (SAM3U_PIOA_BASE+SAM3U_PIO_IFSR_OFFSET)
-#define SAM3U_PIOA_SODR (SAM3U_PIOA_BASE+SAM3U_PIO_SODR_OFFSET)
-#define SAM3U_PIOA_CODR (SAM3U_PIOA_BASE+SAM3U_PIO_CODR_OFFSET)
-#define SAM3U_PIOA_ODSR (SAM3U_PIOA_BASE+SAM3U_PIO_ODSR_OFFSET)
-#define SAM3U_PIOA_PDSR (SAM3U_PIOA_BASE+SAM3U_PIO_PDSR_OFFSET)
-#define SAM3U_PIOA_IER (SAM3U_PIOA_BASE+SAM3U_PIO_IER_OFFSET)
-#define SAM3U_PIOA_IDR (SAM3U_PIOA_BASE+SAM3U_PIO_IDR_OFFSET)
-#define SAM3U_PIOA_IMR (SAM3U_PIOA_BASE+SAM3U_PIO_IMR_OFFSET)
-#define SAM3U_PIOA_ISR (SAM3U_PIOA_BASE+SAM3U_PIO_ISR_OFFSET)
-#define SAM3U_PIOA_MDER (SAM3U_PIOA_BASE+SAM3U_PIO_MDER_OFFSET)
-#define SAM3U_PIOA_MDDR (SAM3U_PIOA_BASE+SAM3U_PIO_MDDR_OFFSET)
-#define SAM3U_PIOA_MDSR (SAM3U_PIOA_BASE+SAM3U_PIO_MDSR_OFFSET)
-#define SAM3U_PIOA_PUDR (SAM3U_PIOA_BASE+SAM3U_PIO_PUDR_OFFSET)
-#define SAM3U_PIOA_PUER (SAM3U_PIOA_BASE+SAM3U_PIO_PUER_OFFSET)
-#define SAM3U_PIOA_PUSR (SAM3U_PIOA_BASE+SAM3U_PIO_PUSR_OFFSET)
-#define SAM3U_PIOA_ABSR (SAM3U_PIOA_BASE+SAM3U_PIO_ABSR_OFFSET)
-#define SAM3U_PIOA_SCIFSR (SAM3U_PIOA_BASE+SAM3U_PIO_SCIFSR_OFFSET)
-#define SAM3U_PIOA_DIFSR (SAM3U_PIOA_BASE+SAM3U_PIO_DIFSR_OFFSET)
-#define SAM3U_PIOA_IFDGSR (SAM3U_PIOA_BASE+SAM3U_PIO_IFDGSR_OFFSET)
-#define SAM3U_PIOA_SCDR (SAM3U_PIOA_BASE+SAM3U_PIO_SCDR_OFFSET)
-#define SAM3U_PIOA_OWER (SAM3U_PIOA_BASE+SAM3U_PIO_OWER_OFFSET)
-#define SAM3U_PIOA_OWDR (SAM3U_PIOA_BASE+SAM3U_PIO_OWDR_OFFSET)
-#define SAM3U_PIOA_OWSR (SAM3U_PIOA_BASE+SAM3U_PIO_OWSR_OFFSET)
-#define SAM3U_PIOA_AIMER (SAM3U_PIOA_BASE+SAM3U_PIO_AIMER_OFFSET)
-#define SAM3U_PIOA_AIMDR (SAM3U_PIOA_BASE+SAM3U_PIO_AIMDR_OFFSET)
-#define SAM3U_PIOA_AIMMR (SAM3U_PIOA_BASE+SAM3U_PIO_AIMMR_OFFSET)
-#define SAM3U_PIOA_ESR (SAM3U_PIOA_BASE+SAM3U_PIO_ESR_OFFSET)
-#define SAM3U_PIOA_LSR (SAM3U_PIOA_BASE+SAM3U_PIO_LSR_OFFSET)
-#define SAM3U_PIOA_ELSR (SAM3U_PIOA_BASE+SAM3U_PIO_ELSR_OFFSET)
-#define SAM3U_PIOA_FELLSR (SAM3U_PIOA_BASE+SAM3U_PIO_FELLSR_OFFSET)
-#define SAM3U_PIOA_REHLSR (SAM3U_PIOA_BASE+SAM3U_PIO_REHLSR_OFFSET)
-#define SAM3U_PIOA_FRLHSR (SAM3U_PIOA_BASE+SAM3U_PIO_FRLHSR_OFFSET)
-#define SAM3U_PIOA_LOCKSR (SAM3U_PIOA_BASE+SAM3U_PIO_LOCKSR_OFFSET)
-#define SAM3U_PIOA_WPMR (SAM3U_PIOA_BASE+SAM3U_PIO_WPMR_OFFSET)
-#define SAM3U_PIOA_WPSR (SAM3U_PIOA_BASE+SAM3U_PIO_WPSR_OFFSET)
-
-#define SAM3U_PIOB_PER (SAM3U_PIOB_BASE+SAM3U_PIO_PER_OFFSET)
-#define SAM3U_PIOB_PDR_ (SAM3U_PIOB_BASE+SAM3U_PIO_PDR_OFFSET)
-#define SAM3U_PIOB_PSR (SAM3U_PIOB_BASE+SAM3U_PIO_PSR_OFFSET)
-#define SAM3U_PIOB_OER (SAM3U_PIOB_BASE+SAM3U_PIO_OER_OFFSET)
-#define SAM3U_PIOB_ODR (SAM3U_PIOB_BASE+SAM3U_PIO_ODR_OFFSET)
-#define SAM3U_PIOB_OSR (SAM3U_PIOB_BASE+SAM3U_PIO_OSR_OFFSET)
-#define SAM3U_PIOB_IFER (SAM3U_PIOB_BASE+SAM3U_PIO_IFER_OFFSET)
-#define SAM3U_PIOB_IFDR (SAM3U_PIOB_BASE+SAM3U_PIO_IFDR_OFFSET)
-#define SAM3U_PIOB_IFSR (SAM3U_PIOB_BASE+SAM3U_PIO_IFSR_OFFSET)
-#define SAM3U_PIOB_SODR (SAM3U_PIOB_BASE+SAM3U_PIO_SODR_OFFSET)
-#define SAM3U_PIOB_CODR (SAM3U_PIOB_BASE+SAM3U_PIO_CODR_OFFSET)
-#define SAM3U_PIOB_ODSR (SAM3U_PIOB_BASE+SAM3U_PIO_ODSR_OFFSET)
-#define SAM3U_PIOB_PDSR (SAM3U_PIOB_BASE+SAM3U_PIO_PDSR_OFFSET)
-#define SAM3U_PIOB_IER (SAM3U_PIOB_BASE+SAM3U_PIO_IER_OFFSET)
-#define SAM3U_PIOB_IDR (SAM3U_PIOB_BASE+SAM3U_PIO_IDR_OFFSET)
-#define SAM3U_PIOB_IMR (SAM3U_PIOB_BASE+SAM3U_PIO_IMR_OFFSET)
-#define SAM3U_PIOB_ISR (SAM3U_PIOB_BASE+SAM3U_PIO_ISR_OFFSET)
-#define SAM3U_PIOB_MDER (SAM3U_PIOB_BASE+SAM3U_PIO_MDER_OFFSET)
-#define SAM3U_PIOB_MDDR (SAM3U_PIOB_BASE+SAM3U_PIO_MDDR_OFFSET)
-#define SAM3U_PIOB_MDSR (SAM3U_PIOB_BASE+SAM3U_PIO_MDSR_OFFSET)
-#define SAM3U_PIOB_PUDR (SAM3U_PIOB_BASE+SAM3U_PIO_PUDR_OFFSET)
-#define SAM3U_PIOB_PUER (SAM3U_PIOB_BASE+SAM3U_PIO_PUER_OFFSET)
-#define SAM3U_PIOB_PUSR (SAM3U_PIOB_BASE+SAM3U_PIO_PUSR_OFFSET)
-#define SAM3U_PIOB_ABSR (SAM3U_PIOB_BASE+SAM3U_PIO_ABSR_OFFSET)
-#define SAM3U_PIOB_SCIFSR (SAM3U_PIOB_BASE+SAM3U_PIO_SCIFSR_OFFSET)
-#define SAM3U_PIOB_DIFSR (SAM3U_PIOB_BASE+SAM3U_PIO_DIFSR_OFFSET)
-#define SAM3U_PIOB_IFDGSR (SAM3U_PIOB_BASE+SAM3U_PIO_IFDGSR_OFFSET)
-#define SAM3U_PIOB_SCDR (SAM3U_PIOB_BASE+SAM3U_PIO_SCDR_OFFSET)
-#define SAM3U_PIOB_OWER (SAM3U_PIOB_BASE+SAM3U_PIO_OWER_OFFSET)
-#define SAM3U_PIOB_OWDR (SAM3U_PIOB_BASE+SAM3U_PIO_OWDR_OFFSET)
-#define SAM3U_PIOB_OWSR (SAM3U_PIOB_BASE+SAM3U_PIO_OWSR_OFFSET)
-#define SAM3U_PIOB_AIMER (SAM3U_PIOB_BASE+SAM3U_PIO_AIMER_OFFSET)
-#define SAM3U_PIOB_AIMDR (SAM3U_PIOB_BASE+SAM3U_PIO_AIMDR_OFFSET)
-#define SAM3U_PIOB_AIMMR (SAM3U_PIOB_BASE+SAM3U_PIO_AIMMR_OFFSET)
-#define SAM3U_PIOB_ESR (SAM3U_PIOB_BASE+SAM3U_PIO_ESR_OFFSET)
-#define SAM3U_PIOB_LSR (SAM3U_PIOB_BASE+SAM3U_PIO_LSR_OFFSET)
-#define SAM3U_PIOB_ELSR (SAM3U_PIOB_BASE+SAM3U_PIO_ELSR_OFFSET)
-#define SAM3U_PIOB_FELLSR (SAM3U_PIOB_BASE+SAM3U_PIO_FELLSR_OFFSET)
-#define SAM3U_PIOB_REHLSR (SAM3U_PIOB_BASE+SAM3U_PIO_REHLSR_OFFSET)
-#define SAM3U_PIOB_FRLHSR (SAM3U_PIOB_BASE+SAM3U_PIO_FRLHSR_OFFSET)
-#define SAM3U_PIOB_LOCKSR (SAM3U_PIOB_BASE+SAM3U_PIO_LOCKSR_OFFSET)
-#define SAM3U_PIOB_WPMR (SAM3U_PIOB_BASE+SAM3U_PIO_WPMR_OFFSET)
-#define SAM3U_PIOB_WPSR (SAM3U_PIOB_BASE+SAM3U_PIO_WPSR_OFFSET)
-
-#define SAM3U_PIOC_PER (SAM3U_PIOC_BASE+SAM3U_PIO_PER_OFFSET)
-#define SAM3U_PIOC_PDR_ (SAM3U_PIOC_BASE+SAM3U_PIO_PDR_OFFSET)
-#define SAM3U_PIOC_PSR (SAM3U_PIOC_BASE+SAM3U_PIO_PSR_OFFSET)
-#define SAM3U_PIOC_OER (SAM3U_PIOC_BASE+SAM3U_PIO_OER_OFFSET)
-#define SAM3U_PIOC_ODR (SAM3U_PIOC_BASE+SAM3U_PIO_ODR_OFFSET)
-#define SAM3U_PIOC_OSR (SAM3U_PIOC_BASE+SAM3U_PIO_OSR_OFFSET)
-#define SAM3U_PIOC_IFER (SAM3U_PIOC_BASE+SAM3U_PIO_IFER_OFFSET)
-#define SAM3U_PIOC_IFDR (SAM3U_PIOC_BASE+SAM3U_PIO_IFDR_OFFSET)
-#define SAM3U_PIOC_IFSR (SAM3U_PIOC_BASE+SAM3U_PIO_IFSR_OFFSET)
-#define SAM3U_PIOC_SODR (SAM3U_PIOC_BASE+SAM3U_PIO_SODR_OFFSET)
-#define SAM3U_PIOC_CODR (SAM3U_PIOC_BASE+SAM3U_PIO_CODR_OFFSET)
-#define SAM3U_PIOC_ODSR (SAM3U_PIOC_BASE+SAM3U_PIO_ODSR_OFFSET)
-#define SAM3U_PIOC_PDSR (SAM3U_PIOC_BASE+SAM3U_PIO_PDSR_OFFSET)
-#define SAM3U_PIOC_IER (SAM3U_PIOC_BASE+SAM3U_PIO_IER_OFFSET)
-#define SAM3U_PIOC_IDR (SAM3U_PIOC_BASE+SAM3U_PIO_IDR_OFFSET)
-#define SAM3U_PIOC_IMR (SAM3U_PIOC_BASE+SAM3U_PIO_IMR_OFFSET)
-#define SAM3U_PIOC_ISR (SAM3U_PIOC_BASE+SAM3U_PIO_ISR_OFFSET)
-#define SAM3U_PIOC_MDER (SAM3U_PIOC_BASE+SAM3U_PIO_MDER_OFFSET)
-#define SAM3U_PIOC_MDDR (SAM3U_PIOC_BASE+SAM3U_PIO_MDDR_OFFSET)
-#define SAM3U_PIOC_MDSR (SAM3U_PIOC_BASE+SAM3U_PIO_MDSR_OFFSET)
-#define SAM3U_PIOC_PUDR (SAM3U_PIOC_BASE+SAM3U_PIO_PUDR_OFFSET)
-#define SAM3U_PIOC_PUER (SAM3U_PIOC_BASE+SAM3U_PIO_PUER_OFFSET)
-#define SAM3U_PIOC_PUSR (SAM3U_PIOC_BASE+SAM3U_PIO_PUSR_OFFSET)
-#define SAM3U_PIOC_ABSR (SAM3U_PIOC_BASE+SAM3U_PIO_ABSR_OFFSET)
-#define SAM3U_PIOC_SCIFSR (SAM3U_PIOC_BASE+SAM3U_PIO_SCIFSR_OFFSET)
-#define SAM3U_PIOC_DIFSR (SAM3U_PIOC_BASE+SAM3U_PIO_DIFSR_OFFSET)
-#define SAM3U_PIOC_IFDGSR (SAM3U_PIOC_BASE+SAM3U_PIO_IFDGSR_OFFSET)
-#define SAM3U_PIOC_SCDR (SAM3U_PIOC_BASE+SAM3U_PIO_SCDR_OFFSET)
-#define SAM3U_PIOC_OWER (SAM3U_PIOC_BASE+SAM3U_PIO_OWER_OFFSET)
-#define SAM3U_PIOC_OWDR (SAM3U_PIOC_BASE+SAM3U_PIO_OWDR_OFFSET)
-#define SAM3U_PIOC_OWSR (SAM3U_PIOC_BASE+SAM3U_PIO_OWSR_OFFSET)
-#define SAM3U_PIOC_AIMER (SAM3U_PIOC_BASE+SAM3U_PIO_AIMER_OFFSET)
-#define SAM3U_PIOC_AIMDR (SAM3U_PIOC_BASE+SAM3U_PIO_AIMDR_OFFSET)
-#define SAM3U_PIOC_AIMMR (SAM3U_PIOC_BASE+SAM3U_PIO_AIMMR_OFFSET)
-#define SAM3U_PIOC_ESR (SAM3U_PIOC_BASE+SAM3U_PIO_ESR_OFFSET)
-#define SAM3U_PIOC_LSR (SAM3U_PIOC_BASE+SAM3U_PIO_LSR_OFFSET)
-#define SAM3U_PIOC_ELSR (SAM3U_PIOC_BASE+SAM3U_PIO_ELSR_OFFSET)
-#define SAM3U_PIOC_FELLSR (SAM3U_PIOC_BASE+SAM3U_PIO_FELLSR_OFFSET)
-#define SAM3U_PIOC_REHLSR (SAM3U_PIOC_BASE+SAM3U_PIO_REHLSR_OFFSET)
-#define SAM3U_PIOC_FRLHSR (SAM3U_PIOC_BASE+SAM3U_PIO_FRLHSR_OFFSET)
-#define SAM3U_PIOC_LOCKSR (SAM3U_PIOC_BASE+SAM3U_PIO_LOCKSR_OFFSET)
-#define SAM3U_PIOC_WPMR (SAM3U_PIOC_BASE+SAM3U_PIO_WPMR_OFFSET)
-#define SAM3U_PIOC_WPSR (SAM3U_PIOC_BASE+SAM3U_PIO_WPSR_OFFSET)
-
-/* PIO register bit definitions *********************************************************/
-
-/* Common bit definitions for ALMOST all IO registers (exceptions follow) */
-
-#define PIO(n) (1<<(n)) /* Bit n: PIO n */
-
-/* PIO Write Protect Mode Register */
-
-#define PIO_WPMR_WPEN (1 << 0) /* Bit 0: Write Protect Enable */
-#define PIO_WPMR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protect KEY */
-#define PIO_WPMR_WPKEY_MASK (0xffffff << PIO_WPMR_WPKEY_SHIFT)
-
-/* PIO Write Protect Status Register */
-
-#define PIO_WPSR_WPVS (1 << 0) /* Bit 0: Write Protect Violation Status */
-#define PIO_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protect Violation Source */
-#define PIO_WPSR_WPVSRC_MASK (0xffff << PIO_WPSR_WPVSRC_SHIFT)
-
-/****************************************************************************************
- * Public Types
- ****************************************************************************************/
-
-/****************************************************************************************
- * Public Data
- ****************************************************************************************/
-
-/****************************************************************************************
- * Public Functions
- ****************************************************************************************/
-
-#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_PIO_H */
+/**************************************************************************************** + * arch/arm/src/sam3u/sam3u_pio.h + * + * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_PIO_H +#define __ARCH_ARM_SRC_SAM3U_SAM3U_PIO_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +#include <nuttx/config.h> + +#include "chip.h" +#include "sam3u_memorymap.h" + +/**************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************/ + +/* PIO register offsets *****************************************************************/ + +#define SAM3U_PIO_PER_OFFSET 0x0000 /* PIO Enable Register */ +#define SAM3U_PIO_PDR_OFFSET 0x0004 /* PIO Disable Register */ +#define SAM3U_PIO_PSR_OFFSET 0x0008 /* PIO Status Register */ + /* 0x000c: Reserved */ +#define SAM3U_PIO_OER_OFFSET 0x0010 /* Output Enable Register */ +#define SAM3U_PIO_ODR_OFFSET 0x0014 /* Output Disable Register */ +#define SAM3U_PIO_OSR_OFFSET 0x0018 /* utput Status Register */ + /* 0x001c: Reserved */ +#define SAM3U_PIO_IFER_OFFSET 0x0020 /* Glitch Input Filter Enable Register */ +#define SAM3U_PIO_IFDR_OFFSET 0x0024 /* Glitch Input Filter Disable Register */ +#define SAM3U_PIO_IFSR_OFFSET 0x0028 /* Glitch Input Filter Status Register */ + /* 0x002c: Reserved */ +#define SAM3U_PIO_SODR_OFFSET 0x0030 /* Set Output Data Register */ +#define SAM3U_PIO_CODR_OFFSET 0x0034 /* Clear Output Data Register */ +#define SAM3U_PIO_ODSR_OFFSET 0x0038 /* Output Data Status Register */ +#define SAM3U_PIO_PDSR_OFFSET 0x003c /* Pin Data Status Register */ +#define SAM3U_PIO_IER_OFFSET 0x0040 /* Interrupt Enable Register */ +#define SAM3U_PIO_IDR_OFFSET 0x0044 /* Interrupt Disable Register */ +#define SAM3U_PIO_IMR_OFFSET 0x0048 /* Interrupt Mask Register */ +#define SAM3U_PIO_ISR_OFFSET 0x004c /* Interrupt Status Register */ +#define SAM3U_PIO_MDER_OFFSET 0x0050 /* Multi-driver Enable Register */ +#define SAM3U_PIO_MDDR_OFFSET 0x0054 /* Multi-driver Disable Register */ +#define SAM3U_PIO_MDSR_OFFSET 0x0058 /* Multi-driver Status Register */ + /* 0x005c: Reserved */ +#define SAM3U_PIO_PUDR_OFFSET 0x0060 /* Pull-up Disable Register */ +#define SAM3U_PIO_PUER_OFFSET 0x0064 /* Pull-up Enable Register */ +#define SAM3U_PIO_PUSR_OFFSET 0x0068 /* Pad Pull-up Status Register */ + /* 0x006c: Reserved */ +#define SAM3U_PIO_ABSR_OFFSET 0x0070 /* Peripheral AB Select Register */ + /* 0x0074-0x007c: Reserved */ +#define SAM3U_PIO_SCIFSR_OFFSET 0x0080 /* System Clock Glitch Input Filter Select Register */ +#define SAM3U_PIO_DIFSR_OFFSET 0x0084 /* Debouncing Input Filter Select Register */ +#define SAM3U_PIO_IFDGSR_OFFSET 0x0088 /* Glitch or Debouncing Input Filter Clock Selection Status Register */ +#define SAM3U_PIO_SCDR_OFFSET 0x008c /* Slow Clock Divider Debouncing Register */ + /* 0x0090-0x009c: Reserved */ +#define SAM3U_PIO_OWER_OFFSET 0x00a0 /* Output Write Enable */ +#define SAM3U_PIO_OWDR_OFFSET 0x00a4 /* Output Write Disable */ +#define SAM3U_PIO_OWSR_OFFSET 0x00a8 /* Output Write Status Register */ + /* 0x00ac: Reserved */ +#define SAM3U_PIO_AIMER_OFFSET 0x00b0 /* Additional Interrupt Modes Enable Register */ +#define SAM3U_PIO_AIMDR_OFFSET 0x00b4 /* Additional Interrupt Modes Disables Register */ +#define SAM3U_PIO_AIMMR_OFFSET 0x00b8 /* Additional Interrupt Modes Mask Register */ + /* 0x00bc: Reserved */ +#define SAM3U_PIO_ESR_OFFSET 0x00c0 /* Edge Select Register */ +#define SAM3U_PIO_LSR_OFFSET 0x00c4 /* Level Select Register */ +#define SAM3U_PIO_ELSR_OFFSET 0x00c8 /* Edge/Level Status Register */ + /* 0x00cc: Reserved */ +#define SAM3U_PIO_FELLSR_OFFSET 0x00d0 /* Falling Edge/Low Level Select Register */ +#define SAM3U_PIO_REHLSR_OFFSET 0x00d4 /* Rising Edge/ High Level Select Register */ +#define SAM3U_PIO_FRLHSR_OFFSET 0x00d8 /* Fall/Rise - Low/High Status Register */ + /* 0x00dc: Reserved */ +#define SAM3U_PIO_LOCKSR_OFFSET 0x00e0 /* Lock Status */ +#define SAM3U_PIO_WPMR_OFFSET 0x00e4 /* Write Protect Mode Register */ +#define SAM3U_PIO_WPSR_OFFSET 0x00e8 /* Write Protect Status Register */ + /* 0x00ec-0x00f8: Reserved */ + /* 0x0100-0x0144: Reserved */ + +/* PIO register adresses ****************************************************************/ + +#define PIOA (0) +#define PIOB (1) +#define PIOC (2) +#define NPIO (3) + +#define SAM3U_PIO_PER(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_PER_OFFSET) +#define SAM3U_PIO_PDR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_PDR_OFFSET) +#define SAM3U_PIO_PSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_PSR_OFFSET) +#define SAM3U_PIO_OER(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_OER_OFFSET) +#define SAM3U_PIO_ODR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_ODR_OFFSET) +#define SAM3U_PIO_OSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_OSR_OFFSET) +#define SAM3U_PIO_IFER(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_IFER_OFFSET) +#define SAM3U_PIO_IFDR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_IFDR_OFFSET) +#define SAM3U_PIO_IFSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_IFSR_OFFSET) +#define SAM3U_PIO_SODR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_SODR_OFFSET) +#define SAM3U_PIO_CODR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_CODR_OFFSET) +#define SAM3U_PIO_ODSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_ODSR_OFFSET) +#define SAM3U_PIO_PDSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_PDSR_OFFSET) +#define SAM3U_PIO_IER(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_IER_OFFSET) +#define SAM3U_PIO_IDR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_IDR_OFFSET) +#define SAM3U_PIO_IMR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_IMR_OFFSET) +#define SAM3U_PIO_ISR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_ISR_OFFSET) +#define SAM3U_PIO_MDER(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_MDER_OFFSET) +#define SAM3U_PIO_MDDR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_MDDR_OFFSET) +#define SAM3U_PIO_MDSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_MDSR_OFFSET) +#define SAM3U_PIO_PUDR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_PUDR_OFFSET) +#define SAM3U_PIO_PUER(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_PUER_OFFSET) +#define SAM3U_PIO_PUSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_PUSR_OFFSET) +#define SAM3U_PIO_ABSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_ABSR_OFFSET) +#define SAM3U_PIO_SCIFSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_SCIFSR_OFFSET) +#define SAM3U_PIO_DIFSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_DIFSR_OFFSET) +#define SAM3U_PIO_IFDGSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_IFDGSR_OFFSET) +#define SAM3U_PIO_SCDR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_SCDR_OFFSET) +#define SAM3U_PIO_OWER(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_OWER_OFFSET) +#define SAM3U_PIO_OWDR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_OWDR_OFFSET) +#define SAM3U_PIO_OWSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_OWSR_OFFSET) +#define SAM3U_PIO_AIMER(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_AIMER_OFFSET) +#define SAM3U_PIO_AIMDR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_AIMDR_OFFSET) +#define SAM3U_PIO_AIMMR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_AIMMR_OFFSET) +#define SAM3U_PIO_ESR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_ESR_OFFSET) +#define SAM3U_PIO_LSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_LSR_OFFSET) +#define SAM3U_PIO_ELSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_ELSR_OFFSET) +#define SAM3U_PIO_FELLSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_FELLSR_OFFSET) +#define SAM3U_PIO_REHLSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_REHLSR_OFFSET) +#define SAM3U_PIO_FRLHSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_FRLHSR_OFFSET) +#define SAM3U_PIO_LOCKSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_LOCKSR_OFFSET) +#define SAM3U_PIO_WPMR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_WPMR_OFFSET) +#define SAM3U_PIO_WPSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_WPSR_OFFSET) + +#define SAM3U_PIOA_PER (SAM3U_PIOA_BASE+SAM3U_PIO_PER_OFFSET) +#define SAM3U_PIOA_PDR_ (SAM3U_PIOA_BASE+SAM3U_PIO_PDR_OFFSET) +#define SAM3U_PIOA_PSR (SAM3U_PIOA_BASE+SAM3U_PIO_PSR_OFFSET) +#define SAM3U_PIOA_OER (SAM3U_PIOA_BASE+SAM3U_PIO_OER_OFFSET) +#define SAM3U_PIOA_ODR (SAM3U_PIOA_BASE+SAM3U_PIO_ODR_OFFSET) +#define SAM3U_PIOA_OSR (SAM3U_PIOA_BASE+SAM3U_PIO_OSR_OFFSET) +#define SAM3U_PIOA_IFER (SAM3U_PIOA_BASE+SAM3U_PIO_IFER_OFFSET) +#define SAM3U_PIOA_IFDR (SAM3U_PIOA_BASE+SAM3U_PIO_IFDR_OFFSET) +#define SAM3U_PIOA_IFSR (SAM3U_PIOA_BASE+SAM3U_PIO_IFSR_OFFSET) +#define SAM3U_PIOA_SODR (SAM3U_PIOA_BASE+SAM3U_PIO_SODR_OFFSET) +#define SAM3U_PIOA_CODR (SAM3U_PIOA_BASE+SAM3U_PIO_CODR_OFFSET) +#define SAM3U_PIOA_ODSR (SAM3U_PIOA_BASE+SAM3U_PIO_ODSR_OFFSET) +#define SAM3U_PIOA_PDSR (SAM3U_PIOA_BASE+SAM3U_PIO_PDSR_OFFSET) +#define SAM3U_PIOA_IER (SAM3U_PIOA_BASE+SAM3U_PIO_IER_OFFSET) +#define SAM3U_PIOA_IDR (SAM3U_PIOA_BASE+SAM3U_PIO_IDR_OFFSET) +#define SAM3U_PIOA_IMR (SAM3U_PIOA_BASE+SAM3U_PIO_IMR_OFFSET) +#define SAM3U_PIOA_ISR (SAM3U_PIOA_BASE+SAM3U_PIO_ISR_OFFSET) +#define SAM3U_PIOA_MDER (SAM3U_PIOA_BASE+SAM3U_PIO_MDER_OFFSET) +#define SAM3U_PIOA_MDDR (SAM3U_PIOA_BASE+SAM3U_PIO_MDDR_OFFSET) +#define SAM3U_PIOA_MDSR (SAM3U_PIOA_BASE+SAM3U_PIO_MDSR_OFFSET) +#define SAM3U_PIOA_PUDR (SAM3U_PIOA_BASE+SAM3U_PIO_PUDR_OFFSET) +#define SAM3U_PIOA_PUER (SAM3U_PIOA_BASE+SAM3U_PIO_PUER_OFFSET) +#define SAM3U_PIOA_PUSR (SAM3U_PIOA_BASE+SAM3U_PIO_PUSR_OFFSET) +#define SAM3U_PIOA_ABSR (SAM3U_PIOA_BASE+SAM3U_PIO_ABSR_OFFSET) +#define SAM3U_PIOA_SCIFSR (SAM3U_PIOA_BASE+SAM3U_PIO_SCIFSR_OFFSET) +#define SAM3U_PIOA_DIFSR (SAM3U_PIOA_BASE+SAM3U_PIO_DIFSR_OFFSET) +#define SAM3U_PIOA_IFDGSR (SAM3U_PIOA_BASE+SAM3U_PIO_IFDGSR_OFFSET) +#define SAM3U_PIOA_SCDR (SAM3U_PIOA_BASE+SAM3U_PIO_SCDR_OFFSET) +#define SAM3U_PIOA_OWER (SAM3U_PIOA_BASE+SAM3U_PIO_OWER_OFFSET) +#define SAM3U_PIOA_OWDR (SAM3U_PIOA_BASE+SAM3U_PIO_OWDR_OFFSET) +#define SAM3U_PIOA_OWSR (SAM3U_PIOA_BASE+SAM3U_PIO_OWSR_OFFSET) +#define SAM3U_PIOA_AIMER (SAM3U_PIOA_BASE+SAM3U_PIO_AIMER_OFFSET) +#define SAM3U_PIOA_AIMDR (SAM3U_PIOA_BASE+SAM3U_PIO_AIMDR_OFFSET) +#define SAM3U_PIOA_AIMMR (SAM3U_PIOA_BASE+SAM3U_PIO_AIMMR_OFFSET) +#define SAM3U_PIOA_ESR (SAM3U_PIOA_BASE+SAM3U_PIO_ESR_OFFSET) +#define SAM3U_PIOA_LSR (SAM3U_PIOA_BASE+SAM3U_PIO_LSR_OFFSET) +#define SAM3U_PIOA_ELSR (SAM3U_PIOA_BASE+SAM3U_PIO_ELSR_OFFSET) +#define SAM3U_PIOA_FELLSR (SAM3U_PIOA_BASE+SAM3U_PIO_FELLSR_OFFSET) +#define SAM3U_PIOA_REHLSR (SAM3U_PIOA_BASE+SAM3U_PIO_REHLSR_OFFSET) +#define SAM3U_PIOA_FRLHSR (SAM3U_PIOA_BASE+SAM3U_PIO_FRLHSR_OFFSET) +#define SAM3U_PIOA_LOCKSR (SAM3U_PIOA_BASE+SAM3U_PIO_LOCKSR_OFFSET) +#define SAM3U_PIOA_WPMR (SAM3U_PIOA_BASE+SAM3U_PIO_WPMR_OFFSET) +#define SAM3U_PIOA_WPSR (SAM3U_PIOA_BASE+SAM3U_PIO_WPSR_OFFSET) + +#define SAM3U_PIOB_PER (SAM3U_PIOB_BASE+SAM3U_PIO_PER_OFFSET) +#define SAM3U_PIOB_PDR_ (SAM3U_PIOB_BASE+SAM3U_PIO_PDR_OFFSET) +#define SAM3U_PIOB_PSR (SAM3U_PIOB_BASE+SAM3U_PIO_PSR_OFFSET) +#define SAM3U_PIOB_OER (SAM3U_PIOB_BASE+SAM3U_PIO_OER_OFFSET) +#define SAM3U_PIOB_ODR (SAM3U_PIOB_BASE+SAM3U_PIO_ODR_OFFSET) +#define SAM3U_PIOB_OSR (SAM3U_PIOB_BASE+SAM3U_PIO_OSR_OFFSET) +#define SAM3U_PIOB_IFER (SAM3U_PIOB_BASE+SAM3U_PIO_IFER_OFFSET) +#define SAM3U_PIOB_IFDR (SAM3U_PIOB_BASE+SAM3U_PIO_IFDR_OFFSET) +#define SAM3U_PIOB_IFSR (SAM3U_PIOB_BASE+SAM3U_PIO_IFSR_OFFSET) +#define SAM3U_PIOB_SODR (SAM3U_PIOB_BASE+SAM3U_PIO_SODR_OFFSET) +#define SAM3U_PIOB_CODR (SAM3U_PIOB_BASE+SAM3U_PIO_CODR_OFFSET) +#define SAM3U_PIOB_ODSR (SAM3U_PIOB_BASE+SAM3U_PIO_ODSR_OFFSET) +#define SAM3U_PIOB_PDSR (SAM3U_PIOB_BASE+SAM3U_PIO_PDSR_OFFSET) +#define SAM3U_PIOB_IER (SAM3U_PIOB_BASE+SAM3U_PIO_IER_OFFSET) +#define SAM3U_PIOB_IDR (SAM3U_PIOB_BASE+SAM3U_PIO_IDR_OFFSET) +#define SAM3U_PIOB_IMR (SAM3U_PIOB_BASE+SAM3U_PIO_IMR_OFFSET) +#define SAM3U_PIOB_ISR (SAM3U_PIOB_BASE+SAM3U_PIO_ISR_OFFSET) +#define SAM3U_PIOB_MDER (SAM3U_PIOB_BASE+SAM3U_PIO_MDER_OFFSET) +#define SAM3U_PIOB_MDDR (SAM3U_PIOB_BASE+SAM3U_PIO_MDDR_OFFSET) +#define SAM3U_PIOB_MDSR (SAM3U_PIOB_BASE+SAM3U_PIO_MDSR_OFFSET) +#define SAM3U_PIOB_PUDR (SAM3U_PIOB_BASE+SAM3U_PIO_PUDR_OFFSET) +#define SAM3U_PIOB_PUER (SAM3U_PIOB_BASE+SAM3U_PIO_PUER_OFFSET) +#define SAM3U_PIOB_PUSR (SAM3U_PIOB_BASE+SAM3U_PIO_PUSR_OFFSET) +#define SAM3U_PIOB_ABSR (SAM3U_PIOB_BASE+SAM3U_PIO_ABSR_OFFSET) +#define SAM3U_PIOB_SCIFSR (SAM3U_PIOB_BASE+SAM3U_PIO_SCIFSR_OFFSET) +#define SAM3U_PIOB_DIFSR (SAM3U_PIOB_BASE+SAM3U_PIO_DIFSR_OFFSET) +#define SAM3U_PIOB_IFDGSR (SAM3U_PIOB_BASE+SAM3U_PIO_IFDGSR_OFFSET) +#define SAM3U_PIOB_SCDR (SAM3U_PIOB_BASE+SAM3U_PIO_SCDR_OFFSET) +#define SAM3U_PIOB_OWER (SAM3U_PIOB_BASE+SAM3U_PIO_OWER_OFFSET) +#define SAM3U_PIOB_OWDR (SAM3U_PIOB_BASE+SAM3U_PIO_OWDR_OFFSET) +#define SAM3U_PIOB_OWSR (SAM3U_PIOB_BASE+SAM3U_PIO_OWSR_OFFSET) +#define SAM3U_PIOB_AIMER (SAM3U_PIOB_BASE+SAM3U_PIO_AIMER_OFFSET) +#define SAM3U_PIOB_AIMDR (SAM3U_PIOB_BASE+SAM3U_PIO_AIMDR_OFFSET) +#define SAM3U_PIOB_AIMMR (SAM3U_PIOB_BASE+SAM3U_PIO_AIMMR_OFFSET) +#define SAM3U_PIOB_ESR (SAM3U_PIOB_BASE+SAM3U_PIO_ESR_OFFSET) +#define SAM3U_PIOB_LSR (SAM3U_PIOB_BASE+SAM3U_PIO_LSR_OFFSET) +#define SAM3U_PIOB_ELSR (SAM3U_PIOB_BASE+SAM3U_PIO_ELSR_OFFSET) +#define SAM3U_PIOB_FELLSR (SAM3U_PIOB_BASE+SAM3U_PIO_FELLSR_OFFSET) +#define SAM3U_PIOB_REHLSR (SAM3U_PIOB_BASE+SAM3U_PIO_REHLSR_OFFSET) +#define SAM3U_PIOB_FRLHSR (SAM3U_PIOB_BASE+SAM3U_PIO_FRLHSR_OFFSET) +#define SAM3U_PIOB_LOCKSR (SAM3U_PIOB_BASE+SAM3U_PIO_LOCKSR_OFFSET) +#define SAM3U_PIOB_WPMR (SAM3U_PIOB_BASE+SAM3U_PIO_WPMR_OFFSET) +#define SAM3U_PIOB_WPSR (SAM3U_PIOB_BASE+SAM3U_PIO_WPSR_OFFSET) + +#define SAM3U_PIOC_PER (SAM3U_PIOC_BASE+SAM3U_PIO_PER_OFFSET) +#define SAM3U_PIOC_PDR_ (SAM3U_PIOC_BASE+SAM3U_PIO_PDR_OFFSET) +#define SAM3U_PIOC_PSR (SAM3U_PIOC_BASE+SAM3U_PIO_PSR_OFFSET) +#define SAM3U_PIOC_OER (SAM3U_PIOC_BASE+SAM3U_PIO_OER_OFFSET) +#define SAM3U_PIOC_ODR (SAM3U_PIOC_BASE+SAM3U_PIO_ODR_OFFSET) +#define SAM3U_PIOC_OSR (SAM3U_PIOC_BASE+SAM3U_PIO_OSR_OFFSET) +#define SAM3U_PIOC_IFER (SAM3U_PIOC_BASE+SAM3U_PIO_IFER_OFFSET) +#define SAM3U_PIOC_IFDR (SAM3U_PIOC_BASE+SAM3U_PIO_IFDR_OFFSET) +#define SAM3U_PIOC_IFSR (SAM3U_PIOC_BASE+SAM3U_PIO_IFSR_OFFSET) +#define SAM3U_PIOC_SODR (SAM3U_PIOC_BASE+SAM3U_PIO_SODR_OFFSET) +#define SAM3U_PIOC_CODR (SAM3U_PIOC_BASE+SAM3U_PIO_CODR_OFFSET) +#define SAM3U_PIOC_ODSR (SAM3U_PIOC_BASE+SAM3U_PIO_ODSR_OFFSET) +#define SAM3U_PIOC_PDSR (SAM3U_PIOC_BASE+SAM3U_PIO_PDSR_OFFSET) +#define SAM3U_PIOC_IER (SAM3U_PIOC_BASE+SAM3U_PIO_IER_OFFSET) +#define SAM3U_PIOC_IDR (SAM3U_PIOC_BASE+SAM3U_PIO_IDR_OFFSET) +#define SAM3U_PIOC_IMR (SAM3U_PIOC_BASE+SAM3U_PIO_IMR_OFFSET) +#define SAM3U_PIOC_ISR (SAM3U_PIOC_BASE+SAM3U_PIO_ISR_OFFSET) +#define SAM3U_PIOC_MDER (SAM3U_PIOC_BASE+SAM3U_PIO_MDER_OFFSET) +#define SAM3U_PIOC_MDDR (SAM3U_PIOC_BASE+SAM3U_PIO_MDDR_OFFSET) +#define SAM3U_PIOC_MDSR (SAM3U_PIOC_BASE+SAM3U_PIO_MDSR_OFFSET) +#define SAM3U_PIOC_PUDR (SAM3U_PIOC_BASE+SAM3U_PIO_PUDR_OFFSET) +#define SAM3U_PIOC_PUER (SAM3U_PIOC_BASE+SAM3U_PIO_PUER_OFFSET) +#define SAM3U_PIOC_PUSR (SAM3U_PIOC_BASE+SAM3U_PIO_PUSR_OFFSET) +#define SAM3U_PIOC_ABSR (SAM3U_PIOC_BASE+SAM3U_PIO_ABSR_OFFSET) +#define SAM3U_PIOC_SCIFSR (SAM3U_PIOC_BASE+SAM3U_PIO_SCIFSR_OFFSET) +#define SAM3U_PIOC_DIFSR (SAM3U_PIOC_BASE+SAM3U_PIO_DIFSR_OFFSET) +#define SAM3U_PIOC_IFDGSR (SAM3U_PIOC_BASE+SAM3U_PIO_IFDGSR_OFFSET) +#define SAM3U_PIOC_SCDR (SAM3U_PIOC_BASE+SAM3U_PIO_SCDR_OFFSET) +#define SAM3U_PIOC_OWER (SAM3U_PIOC_BASE+SAM3U_PIO_OWER_OFFSET) +#define SAM3U_PIOC_OWDR (SAM3U_PIOC_BASE+SAM3U_PIO_OWDR_OFFSET) +#define SAM3U_PIOC_OWSR (SAM3U_PIOC_BASE+SAM3U_PIO_OWSR_OFFSET) +#define SAM3U_PIOC_AIMER (SAM3U_PIOC_BASE+SAM3U_PIO_AIMER_OFFSET) +#define SAM3U_PIOC_AIMDR (SAM3U_PIOC_BASE+SAM3U_PIO_AIMDR_OFFSET) +#define SAM3U_PIOC_AIMMR (SAM3U_PIOC_BASE+SAM3U_PIO_AIMMR_OFFSET) +#define SAM3U_PIOC_ESR (SAM3U_PIOC_BASE+SAM3U_PIO_ESR_OFFSET) +#define SAM3U_PIOC_LSR (SAM3U_PIOC_BASE+SAM3U_PIO_LSR_OFFSET) +#define SAM3U_PIOC_ELSR (SAM3U_PIOC_BASE+SAM3U_PIO_ELSR_OFFSET) +#define SAM3U_PIOC_FELLSR (SAM3U_PIOC_BASE+SAM3U_PIO_FELLSR_OFFSET) +#define SAM3U_PIOC_REHLSR (SAM3U_PIOC_BASE+SAM3U_PIO_REHLSR_OFFSET) +#define SAM3U_PIOC_FRLHSR (SAM3U_PIOC_BASE+SAM3U_PIO_FRLHSR_OFFSET) +#define SAM3U_PIOC_LOCKSR (SAM3U_PIOC_BASE+SAM3U_PIO_LOCKSR_OFFSET) +#define SAM3U_PIOC_WPMR (SAM3U_PIOC_BASE+SAM3U_PIO_WPMR_OFFSET) +#define SAM3U_PIOC_WPSR (SAM3U_PIOC_BASE+SAM3U_PIO_WPSR_OFFSET) + +/* PIO register bit definitions *********************************************************/ + +/* Common bit definitions for ALMOST all IO registers (exceptions follow) */ + +#define PIO(n) (1<<(n)) /* Bit n: PIO n */ + +/* PIO Write Protect Mode Register */ + +#define PIO_WPMR_WPEN (1 << 0) /* Bit 0: Write Protect Enable */ +#define PIO_WPMR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protect KEY */ +#define PIO_WPMR_WPKEY_MASK (0xffffff << PIO_WPMR_WPKEY_SHIFT) + +/* PIO Write Protect Status Register */ + +#define PIO_WPSR_WPVS (1 << 0) /* Bit 0: Write Protect Violation Status */ +#define PIO_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protect Violation Source */ +#define PIO_WPSR_WPVSRC_MASK (0xffff << PIO_WPSR_WPVSRC_SHIFT) + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +/**************************************************************************************** + * Public Data + ****************************************************************************************/ + +/**************************************************************************************** + * Public Functions + ****************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_PIO_H */ diff --git a/nuttx/arch/arm/src/sam3u/sam3u_pmc.h b/nuttx/arch/arm/src/sam3u/sam3u_pmc.h index 3fde5b642..75545f239 100644 --- a/nuttx/arch/arm/src/sam3u/sam3u_pmc.h +++ b/nuttx/arch/arm/src/sam3u/sam3u_pmc.h @@ -1,316 +1,316 @@ -/****************************************************************************************
- * arch/arm/src/sam3u/sam3u_pmc.h
- *
- * Copyright (C) 2009 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_PMC_H
-#define __ARCH_ARM_SRC_SAM3U_SAM3U_PMC_H
-
-/****************************************************************************************
- * Included Files
- ****************************************************************************************/
-
-#include <nuttx/config.h>
-
-#include "chip.h"
-#include "sam3u_memorymap.h"
-
-/****************************************************************************************
- * Pre-processor Definitions
- ****************************************************************************************/
-
-/* PMC register offsets *****************************************************************/
-
-#define SAM3U_PMC_SCER_OFFSET 0x0000 /* System Clock Enable Register */
-#define SAM3U_PMC_SCDR_OFFSET 0x0004 /* System Clock Disable Register */
-#define SAM3U_PMC_SCSR_OFFSET 0x0008 /* System Clock Status Register */
- /* 0x000c: Reserved */
-#define SAM3U_PMC_PCER_OFFSET 0x0010 /* Peripheral Clock Enable Register */
-#define SAM3U_PMC_PCDR_OFFSET 0x0014 /* Peripheral Clock Disable Register */
-#define SAM3U_PMC_PCSR_OFFSET 0x0018 /* Peripheral Clock Status Register */
-#define SAM3U_CKGR_UCKR_OFFSET 0x001c /* UTMI Clock Register */
-#define SAM3U_CKGR_MOR_OFFSET 0x0020 /* Main Oscillator Register */
-#define SAM3U_CKGR_MCFR_OFFSET 0x0024 /* Main Clock Frequency Register */
-#define SAM3U_CKGR_PLLAR_OFFSET 0x0028 /* PLLA Register */
- /* 0x002c: Reserved */
-#define SAM3U_PMC_MCKR_OFFSET 0x0030 /* Master Clock Register */
- /* 0x0034-0x003C Reserved */
-#define SAM3U_PMC_PCK_OFFSET(n) (0x0040+((n)<<2))
-#define SAM3U_PMC_PCK0_OFFSET 0x0040 /* Programmable Clock 0 Register */
-#define SAM3U_PMC_PCK1_OFFSET 0x0044 /* Programmable Clock 1 Register */
-#define SAM3U_PMC_PCK2_OFFSET 0x0048 /* Programmable Clock 2 Register */
- /* 0x004c-0x005c: Reserved */
-#define SAM3U_PMC_IER_OFFSET 0x0060 /* Interrupt Enable Register */
-#define SAM3U_PMC_IDR_OFFSET 0x0064 /* Interrupt Disable Register */
-#define SAM3U_PMC_SR_OFFSET 0x0068 /* Status Register */
-#define SAM3U_PMC_IMR_OFFSET 0x006c /* Interrupt Mask Register */
-#define SAM3U_PMC_FSMR_OFFSET 0x0070 /* Fast Startup Mode Register */
-#define SAM3U_PMC_FSPR_OFFSET 0x0074 /* Fast Startup Polarity Register */
-#define SAM3U_PMC_FOCR_OFFSET 0x0078 /* Fault Output Clear Register */
- /* 0x007c-0x00fc: Reserved */
-#define SAM3U_PMC_WPMR_OFFSET 0x00e4 /* Write Protect Mode Register */
-#define SAM3U_PMC_WPSR_OFFSET 0x00e8 /* Write Protect Status Register */
-
-/* PMC register adresses ****************************************************************/
-
-#define SAM3U_PMC_SCER (SAM3U_PMC_BASE+SAM3U_PMC_SCER_OFFSET)
-#define SAM3U_PMC_SCDR (SAM3U_PMC_BASE+SAM3U_PMC_SCDR_OFFSET)
-#define SAM3U_PMC_SCSR (SAM3U_PMC_BASE+SAM3U_PMC_SCSR_OFFSET)
-#define SAM3U_PMC_PCER (SAM3U_PMC_BASE+SAM3U_PMC_PCER_OFFSET)
-#define SAM3U_PMC_PCDR (SAM3U_PMC_BASE+SAM3U_PMC_PCDR_OFFSET)
-#define SAM3U_PMC_PCSR (SAM3U_PMC_BASE+SAM3U_PMC_PCSR_OFFSET)
-#define SAM3U_CKGR_UCKR (SAM3U_PMC_BASE+SAM3U_CKGR_UCKR_OFFSET)
-#define SAM3U_CKGR_MOR (SAM3U_PMC_BASE+SAM3U_CKGR_MOR_OFFSET)
-#define SAM3U_CKGR_MCFR (SAM3U_PMC_BASE+SAM3U_CKGR_MCFR_OFFSET)
-#define SAM3U_CKGR_PLLAR (SAM3U_PMC_BASE+SAM3U_CKGR_PLLAR_OFFSET)
-#define SAM3U_PMC_MCKR (SAM3U_PMC_BASE+SAM3U_PMC_MCKR_OFFSET)
-#define SAM3U_PMC_PCK(n) (SAM3U_PMC_BASE+SAM3U_PMC_PCK_OFFSET(n))
-#define SAM3U_PMC_PCK0 (SAM3U_PMC_BASE+SAM3U_PMC_PCK0_OFFSET)
-#define SAM3U_PMC_PCK1 (SAM3U_PMC_BASE+SAM3U_PMC_PCK1_OFFSET)
-#define SAM3U_PMC_PCK2 (SAM3U_PMC_BASE+SAM3U_PMC_PCK2_OFFSET)
-#define SAM3U_PMC_IER (SAM3U_PMC_BASE+SAM3U_PMC_IER_OFFSET)
-#define SAM3U_PMC_IDR (SAM3U_PMC_BASE+SAM3U_PMC_IDR_OFFSET)
-#define SAM3U_PMC_SR (SAM3U_PMC_BASE+SAM3U_PMC_SR_OFFSET)
-#define SAM3U_PMC_IMR (SAM3U_PMC_BASE+SAM3U_PMC_IMR_OFFSET)
-#define SAM3U_PMC_FSMR (SAM3U_PMC_BASE+SAM3U_PMC_FSMR_OFFSET)
-#define SAM3U_PMC_FSPR (SAM3U_PMC_BASE+SAM3U_PMC_FSPR_OFFSET)
-#define SAM3U_PMC_FOCR (SAM3U_PMC_BASE+SAM3U_PMC_FOCR_OFFSET)
-#define SAM3U_PMC_WPMR (SAM3U_PMC_BASE+SAM3U_PMC_WPMR_OFFSET)
-#define SAM3U_PMC_WPSR (SAM3U_PMC_BASE+SAM3U_PMC_WPSR_OFFSET)
-
-/* PMC register bit definitions *********************************************************/
-
-/* PMC System Clock Enable Register, PMC System Clock Disable Register, and PMC System
- * Clock Status Register common bit-field definitions
- */
-
-#define PMC_PCK(n) (1 <<((n)+8)
-#define PMC_PCK0 (1 << 8) /* Bit 8: Programmable Clock 0 Output Enable */
-#define PMC_PCK1 (1 << 9) /* Bit 9: Programmable Clock 1 Output Enable */
-#define PMC_PCK2 (1 << 10) /* Bit 10: Programmable Clock 2 Output Enable */
-
-/* PMC Peripheral Clock Enable Register, PMC Peripheral Clock Disable Register, and PMC
- * Peripheral Clock Status Register common bit-field definitions.
- */
-
-#define PMC_PID(n) (1<<(n))
-#define PMC_PID2 (1 << 2) /* Bit 2: Peripheral Clock 2 Enable */
-#define PMC_PID3 (1 << 3) /* Bit 3: Peripheral Clock 3 Enable */
-#define PMC_PID4 (1 << 4) /* Bit 4: Peripheral Clock 4 Enable */
-#define PMC_PID5 (1 << 5) /* Bit 5: Peripheral Clock 5 Enable */
-#define PMC_PID6 (1 << 6) /* Bit 6: Peripheral Clock 6 Enable */
-#define PMC_PID7 (1 << 7) /* Bit 7: Peripheral Clock 7 Enable */
-#define PMC_PID8 (1 << 8) /* Bit 8: Peripheral Clock 8 Enable */
-#define PMC_PID9 (1 << 9) /* Bit 9: Peripheral Clock 9 Enable */
-#define PMC_PID10 (1 << 10) /* Bit 10: Peripheral Clock 10 Enable */
-#define PMC_PID11 (1 << 11) /* Bit 11: Peripheral Clock 11 Enable */
-#define PMC_PID12 (1 << 12) /* Bit 12: Peripheral Clock 12 Enable */
-#define PMC_PID13 (1 << 13) /* Bit 13: Peripheral Clock 13 Enable */
-#define PMC_PID14 (1 << 14) /* Bit 14: Peripheral Clock 14 Enable */
-#define PMC_PID15 (1 << 15) /* Bit 15: Peripheral Clock 15 Enable */
-#define PMC_PID16 (1 << 16) /* Bit 16: Peripheral Clock 16 Enable */
-#define PMC_PID17 (1 << 17) /* Bit 17: Peripheral Clock 17 Enable */
-#define PMC_PID18 (1 << 18) /* Bit 18: Peripheral Clock 18 Enable */
-#define PMC_PID19 (1 << 19) /* Bit 19: Peripheral Clock 19 Enable */
-#define PMC_PID20 (1 << 20) /* Bit 20: Peripheral Clock 20 Enable */
-#define PMC_PID21 (1 << 21) /* Bit 21: Peripheral Clock 21 Enable */
-#define PMC_PID22 (1 << 22) /* Bit 22: Peripheral Clock 22 Enable */
-#define PMC_PID23 (1 << 23) /* Bit 23: Peripheral Clock 23 Enable */
-#define PMC_PID24 (1 << 24) /* Bit 24: Peripheral Clock 24 Enable */
-#define PMC_PID25 (1 << 25) /* Bit 25: Peripheral Clock 25 Enable */
-#define PMC_PID26 (1 << 26) /* Bit 26: Peripheral Clock 26 Enable */
-#define PMC_PID27 (1 << 27) /* Bit 27: Peripheral Clock 27 Enable */
-#define PMC_PID28 (1 << 28) /* Bit 28: Peripheral Clock 28 Enable */
-#define PMC_PID29 (1 << 29) /* Bit 29: Peripheral Clock 29 Enable */
-#define PMC_PID30 (1 << 30) /* Bit 30: Peripheral Clock 30 Enable */
-#define PMC_PID31 (1 << 31) /* Bit 31: Peripheral Clock 31 Enable */
-
-/* PMC UTMI Clock Configuration Register */
-
-#define CKGR_UCKR_UPLLEN (1 << 16) /* Bit 16: UTMI PLL Enable */
-#define CKGR_UCKR_UPLLCOUNT_SHIFT (20) /* Bits 20-23: UTMI PLL Start-up Time */
-#define CKGR_UCKR_UPLLCOUNT_MASK (15 << CKGR_UCKR_UPLLCOUNT_SHIFT)
-
-/* PMC Clock Generator Main Oscillator Register */
-
-#define CKGR_MOR_MOSCXTEN (1 << 0) /* Bit 0: Main Crystal Oscillator Enable */
-#define CKGR_MOR_MOSCXTBY (1 << 1) /* Bit 1: Main Crystal Oscillator Bypass */
-#define CKGR_MOR_WAITMODE (1 << 2) /* Bit 2: Wait Mode Command */
-#define CKGR_MOR_MOSCRCEN (1 << 3) /* Bit 3: Main On-Chip RC Oscillator Enable */
-#define CKGR_MOR_MOSCRCF_SHIFT (4) /* Bits 4-6: Main On-Chip RC Oscillator Frequency Selection */
-#define CKGR_MOR_MOSCRCF_MASK (7 << CKGR_MOR_MOSCRCF_SHIFT)
-#define CKGR_MOR_MOSCXTST_SHIFT (8) /* Bits 8-16: Main Crystal Oscillator Start-up Time */
-#define CKGR_MOR_MOSCXTST_MASK (0x1ff << CKGR_MOR_MOSCXTST_SHIFT)
-#define CKGR_MOR_KEY_SHIFT (16) /* Bits 16-23: Password */
-#define CKGR_MOR_KEY_MASK (0xff << CKGR_MOR_KEY_SHIFT)
-#define CKGR_MOR_MOSCSEL (1 << 24) /* Bit 24: Main Oscillator Selection */
-#define CKGR_MOR_CFDEN (1 << 25) /* Bit 25: Clock Failure Detector Enable */
-
-
-/* PMC Clock Generator Main Clock Frequency Register */
-
-#define CKGR_MCFR_MAINF_SHIFT (0) /* Bits 0-15: Main Clock Frequency */
-#define CKGR_MCFR_MAINF_MASK (0xffff << CKGR_MCFR_MAINF_SHIFT)
-#define CKGR_MCFR_MAINFRDY (1 << 16) /* Bit 16: Main Clock Ready */
-
-/* PMC Clock Generator PLLA Register */
-
-#define CKGR_PLLAR_DIVA_SHIFT (0) /* Bits 0-7: Divider */
-#define CKGR_PLLAR_DIVA_MASK (0xff << CKGR_PLLAR_DIVA_SHIFT)
-# define CKGR_PLLAR_DIVA_ZERO (0 << CKGR_PLLAR_DIVA_SHIFT) /* Divider output is 0 */
-# define CKGR_PLLAR_DIVA_BYPASS (1 << CKGR_PLLAR_DIVA_SHIFT) /* Divider is bypassed (DIVA=1) */
-# define CKGR_PLLAR_DIVA(n) ((n) << CKGR_PLLAR_DIVA_SHIFT) /* Divider output is DIVA=n, n=2..255 */
-#define CKGR_PLLAR_PLLACOUNT_SHIFT (8) /* Bits 8-13: PLLA Counter */
-#define CKGR_PLLAR_PLLACOUNT_MASK (63 << CKGR_PLLAR_PLLACOUNT_SHIFT)
-#define CKGR_PLLAR_STMODE_SHIFT (14) /* Bits 14-15: Start Mode */
-#define CKGR_PLLAR_STMODE_MASK (3 << CKGR_PLLAR_STMODE_SHIFT)
-# define CKGR_PLLAR_STMODE_FAST (0 << CKGR_PLLAR_STMODE_SHIFT) /* Fast Startup */
-# define CKGR_PLLAR_STMODE_NORMAL (2 << CKGR_PLLAR_STMODE_SHIFT) /* Normal Startup */
-#define CKGR_PLLAR_MULA_SHIFT (16) /* Bits 16-26: PLLA Multiplier */
-#define CKGR_PLLAR_MULA_MASK (0x7ff << CKGR_PLLAR_MULA_SHIFT)
-#define CKGR_PLLAR_ONE (1 << 29) /* Bit 29: Always one */
-
-/* PMC Master Clock Register */
-
-#define PMC_MCKR_CSS_SHIFT (0) /* Bits 0-1: Master Clock Source Selection */
-#define PMC_MCKR_CSS_MASK (3 << PMC_MCKR_CSS_SHIFT)
-# define PMC_MCKR_CSS_SLOW (0 << PMC_MCKR_CSS_SHIFT) /* Slow Clock */
-# define PMC_MCKR_CSS_MAIN (1 << PMC_MCKR_CSS_SHIFT) /* Main Clock */
-# define PMC_MCKR_CSS_PLLA (2 << PMC_MCKR_CSS_SHIFT) /* PLLA Clock */
-# define PMC_MCKR_CSS_UPLL (3 << PMC_MCKR_CSS_SHIFT) /* UPLL Clock */
-#define PMC_MCKR_PRES_SHIFT (4) /* Bits 4-6: Processor Clock Prescaler */
-#define PMC_MCKR_PRES_MASK (7 << PMC_MCKR_PRES_SHIFT)
-# define PMC_MCKR_PRES_DIV1 (0 << PMC_MCKR_PRES_SHIFT) /* Selected clock */
-# define PMC_MCKR_PRES_DIV2 (1 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 2 */
-# define PMC_MCKR_PRES_DIV4 (2 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 4 */
-# define PMC_MCKR_PRES_DIV8 (3 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 8 */
-# define PMC_MCKR_PRES_DIV16 (4 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 16 */
-# define PMC_MCKR_PRES_DIV32K (5 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 32 */
-# define PMC_MCKR_PRES_DIV64 (6 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 64 */
-# define PMC_MCKR_PRES_DIV3 (7 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 3 */
-#define PMC_MCKR_UPLLDIV (1 << 13) /* Bit 13: UPLL Divider */
-
-/* PMC Programmable Clock Register (0,1,2) */
-
-#define PMC_PCK_CSS_SHIFT (0) /* Bits 0-2: Master Clock Source Selection */
-#define PMC_PCK_CSS_MASK (7 << PMC_PCK_CSS_MASK)
-# define PMC_PCK_CSS_SLOW (0 << PMC_PCK_CSS_MASK) /* Slow Clock */
-# define PMC_PCK_CSS_MAIN (1 << PMC_PCK_CSS_MASK) /* Main Clock */
-# define PMC_PCK_CSS_PLLA (2 << PMC_PCK_CSS_MASK) /* PLLA Clock */
-# define PMC_PCK_CSS_UPLL (3 << PMC_PCK_CSS_MASK) /* UPLL Clock */
-# define PMC_PCK_CSS_MASTER (4 << PMC_PCK_CSS_MASK) /* Master Clock */
-#define PMC_PCK_PRES_SHIFT (4) /* Bits 4-6: Programmable Clock Prescaler */
-#define PMC_PCK_PRES_MASK (7 << PMC_PCK_PRES_SHIFT)
-# define PMC_PCK_PRES_DIV1 (0 << PMC_PCK_PRES_SHIFT) /* Selected clock */
-# define PMC_PCK_PRES_DIV2 (1 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 2 */
-# define PMC_PCK_PRES_DIV4 (2 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 4 */
-# define PMC_PCK_PRES_DIV8 (3 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 8 */
-# define PMC_PCK_PRES_DIV16 (4 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 16 */
-# define PMC_PCK_PRES_DIV32K (5 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 32 */
-# define PMC_PCK_PRES_DIV64 (6 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 64 */
-
-/* PMC Interrupt Enable Register, PMC Interrupt Disable Register, PMC Status Register,
- * and PMC Interrupt Mask Register common bit-field definitions
- */
-
-#define PMC_INT_MOSCXTS (1 << 0) /* Bit 0: Main Crystal Oscillator Status Interrupt */
-#define PMC_INT_LOCKA (1 << 1) /* Bit 1: PLL A Lock Interrupt */
-#define PMC_INT_MCKRDY (1 << 3) /* Bit 3: Master Clock Ready Interrupt */
-#define PMC_INT_LOCKU (1 << 6) /* Bit 6: UTMI PLL Lock Interrupt */
-#define PMC_SR_OSCSELS (1 << 7) /* Bit 7: Slow Clock Oscillator Selection (SR only) */
-#define PMC_INT_PCKRDY(n) (1<<((n)+8)
-#define PMC_INT_PCKRDY0 (1 << 8) /* Bit 8: Programmable Clock Ready 0 Interrupt */
-#define PMC_INT_PCKRDY1 (1 << 9) /* Bit 9: Programmable Clock Ready 1 Interrupt */
-#define PMC_INT_PCKRDY2 (1 << 10) /* Bit 10: Programmable Clock Ready 2 Interrupt */
-#define PMC_INT_MOSCSELS (1 << 16) /* Bit 16: Main Oscillator Selection Status Interrupt */
-#define PMC_INT_MOSCRCS (1 << 17) /* Bit 17: Main On-Chip RC Status Interrupt */
-#define PMC_INT_CFDEV (1 << 18) /* Bit 18: Clock Failure Detector Event Interrupt */
-#define PMC_SR_CFDS (1 << 19) /* Bit 19: Clock Failure Detector Status (SR only) */
-#define PMC_SR_FOS (1 << 20) /* Bit 20: Clock Failure Detector Fault Output Status (SR only) */
-
-/* PMC Fast Startup Mode Register and PMC Fast Startup Polarity Register common bit-field
- * definitions
- */
-
-#define PMC_FSTI(n) (1<<(n))
-#define PMC_FSTI0 (1 << 0) /* Bit 0: Fast Startup Input 0 */
-#define PMC_FSTI1 (1 << 1) /* Bit 1: Fast Startup Input 1 */
-#define PMC_FSTI2 (1 << 2) /* Bit 2: Fast Startup Input 2 */
-#define PMC_FSTI3 (1 << 3) /* Bit 3: Fast Startup Input 3 */
-#define PMC_FSTI4 (1 << 4) /* Bit 4: Fast Startup Input 4 */
-#define PMC_FSTI5 (1 << 5) /* Bit 5: Fast Startup Input 5 */
-#define PMC_FSTI6 (1 << 6) /* Bit 6: Fast Startup Input 6 */
-#define PMC_FSTI7 (1 << 7) /* Bit 7: Fast Startup Input 7 */
-#define PMC_FSTI8 (1 << 8) /* Bit 8: Fast Startup Input 8 */
-#define PMC_FSTI9 (1 << 9) /* Bit 9: Fast Startup Input 9 */
-#define PMC_FSTI10 (1 << 10) /* Bit 10: Fast Startup Input 10 */
-#define PMC_FSTI11 (1 << 11) /* Bit 11: Fast Startup Input 11 */
-#define PMC_FSTI12 (1 << 12) /* Bit 12: Fast Startup Input 12 */
-#define PMC_FSTI13 (1 << 13) /* Bit 13: Fast Startup Input 13 */
-#define PMC_FSTI14 (1 << 14) /* Bit 14: Fast Startup Input 14 */
-#define PMC_FSTI15 (1 << 15) /* Bit 15: Fast Startup Input 15 */
-
-#define PMC_FSMR_RTTAL (1 << 16) /* Bit 16: RTT Alarm Enable (MR only) */
-#define PMC_FSMR_RTCAL (1 << 17) /* Bit 17: RTC Alarm Enable (MR only) */
-#define PMC_FSMR_USBAL (1 << 18) /* Bit 18: USB Alarm Enable (MR only) */
-#define PMC_FSMR_LPM (1 << 20) /* Bit 20: Low Power Mode (MR only) */
-
-/* PMC Fault Output Clear Register */
-
-#define PMC_FOCLR (1 << 0) /* Bit 0: Fault Output Clear */
-
-/* PMC Write Protect Mode Register */
-
-#define PMC_WPMR_WPEN (1 << 0) /* Bit 0: Write Protect Enable */
-#define PMC_WPMR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protect KEY */
-#define PMC_WPMR_WPKEY_MASK (0x00ffffff << PMC_WPMR_WPKEY_SHIFT)
-
-/* PMC Write Protect Status Register */
-
-#define PMC_WPSR_WPVS (1 << 0) /* Bit 0: Write Protect Violation Status */
-#define PMC_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protect Violation Source */
-#define PMC_WPSR_WPVSRC_MASK (0xffff << PMC_WPSR_WPVSRC_SHIFT)
-
-/****************************************************************************************
- * Public Types
- ****************************************************************************************/
-
-/****************************************************************************************
- * Public Data
- ****************************************************************************************/
-
-/****************************************************************************************
- * Public Functions
- ****************************************************************************************/
-
-#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_PMC_H */
+/**************************************************************************************** + * arch/arm/src/sam3u/sam3u_pmc.h + * + * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_PMC_H +#define __ARCH_ARM_SRC_SAM3U_SAM3U_PMC_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +#include <nuttx/config.h> + +#include "chip.h" +#include "sam3u_memorymap.h" + +/**************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************/ + +/* PMC register offsets *****************************************************************/ + +#define SAM3U_PMC_SCER_OFFSET 0x0000 /* System Clock Enable Register */ +#define SAM3U_PMC_SCDR_OFFSET 0x0004 /* System Clock Disable Register */ +#define SAM3U_PMC_SCSR_OFFSET 0x0008 /* System Clock Status Register */ + /* 0x000c: Reserved */ +#define SAM3U_PMC_PCER_OFFSET 0x0010 /* Peripheral Clock Enable Register */ +#define SAM3U_PMC_PCDR_OFFSET 0x0014 /* Peripheral Clock Disable Register */ +#define SAM3U_PMC_PCSR_OFFSET 0x0018 /* Peripheral Clock Status Register */ +#define SAM3U_CKGR_UCKR_OFFSET 0x001c /* UTMI Clock Register */ +#define SAM3U_CKGR_MOR_OFFSET 0x0020 /* Main Oscillator Register */ +#define SAM3U_CKGR_MCFR_OFFSET 0x0024 /* Main Clock Frequency Register */ +#define SAM3U_CKGR_PLLAR_OFFSET 0x0028 /* PLLA Register */ + /* 0x002c: Reserved */ +#define SAM3U_PMC_MCKR_OFFSET 0x0030 /* Master Clock Register */ + /* 0x0034-0x003C Reserved */ +#define SAM3U_PMC_PCK_OFFSET(n) (0x0040+((n)<<2)) +#define SAM3U_PMC_PCK0_OFFSET 0x0040 /* Programmable Clock 0 Register */ +#define SAM3U_PMC_PCK1_OFFSET 0x0044 /* Programmable Clock 1 Register */ +#define SAM3U_PMC_PCK2_OFFSET 0x0048 /* Programmable Clock 2 Register */ + /* 0x004c-0x005c: Reserved */ +#define SAM3U_PMC_IER_OFFSET 0x0060 /* Interrupt Enable Register */ +#define SAM3U_PMC_IDR_OFFSET 0x0064 /* Interrupt Disable Register */ +#define SAM3U_PMC_SR_OFFSET 0x0068 /* Status Register */ +#define SAM3U_PMC_IMR_OFFSET 0x006c /* Interrupt Mask Register */ +#define SAM3U_PMC_FSMR_OFFSET 0x0070 /* Fast Startup Mode Register */ +#define SAM3U_PMC_FSPR_OFFSET 0x0074 /* Fast Startup Polarity Register */ +#define SAM3U_PMC_FOCR_OFFSET 0x0078 /* Fault Output Clear Register */ + /* 0x007c-0x00fc: Reserved */ +#define SAM3U_PMC_WPMR_OFFSET 0x00e4 /* Write Protect Mode Register */ +#define SAM3U_PMC_WPSR_OFFSET 0x00e8 /* Write Protect Status Register */ + +/* PMC register adresses ****************************************************************/ + +#define SAM3U_PMC_SCER (SAM3U_PMC_BASE+SAM3U_PMC_SCER_OFFSET) +#define SAM3U_PMC_SCDR (SAM3U_PMC_BASE+SAM3U_PMC_SCDR_OFFSET) +#define SAM3U_PMC_SCSR (SAM3U_PMC_BASE+SAM3U_PMC_SCSR_OFFSET) +#define SAM3U_PMC_PCER (SAM3U_PMC_BASE+SAM3U_PMC_PCER_OFFSET) +#define SAM3U_PMC_PCDR (SAM3U_PMC_BASE+SAM3U_PMC_PCDR_OFFSET) +#define SAM3U_PMC_PCSR (SAM3U_PMC_BASE+SAM3U_PMC_PCSR_OFFSET) +#define SAM3U_CKGR_UCKR (SAM3U_PMC_BASE+SAM3U_CKGR_UCKR_OFFSET) +#define SAM3U_CKGR_MOR (SAM3U_PMC_BASE+SAM3U_CKGR_MOR_OFFSET) +#define SAM3U_CKGR_MCFR (SAM3U_PMC_BASE+SAM3U_CKGR_MCFR_OFFSET) +#define SAM3U_CKGR_PLLAR (SAM3U_PMC_BASE+SAM3U_CKGR_PLLAR_OFFSET) +#define SAM3U_PMC_MCKR (SAM3U_PMC_BASE+SAM3U_PMC_MCKR_OFFSET) +#define SAM3U_PMC_PCK(n) (SAM3U_PMC_BASE+SAM3U_PMC_PCK_OFFSET(n)) +#define SAM3U_PMC_PCK0 (SAM3U_PMC_BASE+SAM3U_PMC_PCK0_OFFSET) +#define SAM3U_PMC_PCK1 (SAM3U_PMC_BASE+SAM3U_PMC_PCK1_OFFSET) +#define SAM3U_PMC_PCK2 (SAM3U_PMC_BASE+SAM3U_PMC_PCK2_OFFSET) +#define SAM3U_PMC_IER (SAM3U_PMC_BASE+SAM3U_PMC_IER_OFFSET) +#define SAM3U_PMC_IDR (SAM3U_PMC_BASE+SAM3U_PMC_IDR_OFFSET) +#define SAM3U_PMC_SR (SAM3U_PMC_BASE+SAM3U_PMC_SR_OFFSET) +#define SAM3U_PMC_IMR (SAM3U_PMC_BASE+SAM3U_PMC_IMR_OFFSET) +#define SAM3U_PMC_FSMR (SAM3U_PMC_BASE+SAM3U_PMC_FSMR_OFFSET) +#define SAM3U_PMC_FSPR (SAM3U_PMC_BASE+SAM3U_PMC_FSPR_OFFSET) +#define SAM3U_PMC_FOCR (SAM3U_PMC_BASE+SAM3U_PMC_FOCR_OFFSET) +#define SAM3U_PMC_WPMR (SAM3U_PMC_BASE+SAM3U_PMC_WPMR_OFFSET) +#define SAM3U_PMC_WPSR (SAM3U_PMC_BASE+SAM3U_PMC_WPSR_OFFSET) + +/* PMC register bit definitions *********************************************************/ + +/* PMC System Clock Enable Register, PMC System Clock Disable Register, and PMC System + * Clock Status Register common bit-field definitions + */ + +#define PMC_PCK(n) (1 <<((n)+8) +#define PMC_PCK0 (1 << 8) /* Bit 8: Programmable Clock 0 Output Enable */ +#define PMC_PCK1 (1 << 9) /* Bit 9: Programmable Clock 1 Output Enable */ +#define PMC_PCK2 (1 << 10) /* Bit 10: Programmable Clock 2 Output Enable */ + +/* PMC Peripheral Clock Enable Register, PMC Peripheral Clock Disable Register, and PMC + * Peripheral Clock Status Register common bit-field definitions. + */ + +#define PMC_PID(n) (1<<(n)) +#define PMC_PID2 (1 << 2) /* Bit 2: Peripheral Clock 2 Enable */ +#define PMC_PID3 (1 << 3) /* Bit 3: Peripheral Clock 3 Enable */ +#define PMC_PID4 (1 << 4) /* Bit 4: Peripheral Clock 4 Enable */ +#define PMC_PID5 (1 << 5) /* Bit 5: Peripheral Clock 5 Enable */ +#define PMC_PID6 (1 << 6) /* Bit 6: Peripheral Clock 6 Enable */ +#define PMC_PID7 (1 << 7) /* Bit 7: Peripheral Clock 7 Enable */ +#define PMC_PID8 (1 << 8) /* Bit 8: Peripheral Clock 8 Enable */ +#define PMC_PID9 (1 << 9) /* Bit 9: Peripheral Clock 9 Enable */ +#define PMC_PID10 (1 << 10) /* Bit 10: Peripheral Clock 10 Enable */ +#define PMC_PID11 (1 << 11) /* Bit 11: Peripheral Clock 11 Enable */ +#define PMC_PID12 (1 << 12) /* Bit 12: Peripheral Clock 12 Enable */ +#define PMC_PID13 (1 << 13) /* Bit 13: Peripheral Clock 13 Enable */ +#define PMC_PID14 (1 << 14) /* Bit 14: Peripheral Clock 14 Enable */ +#define PMC_PID15 (1 << 15) /* Bit 15: Peripheral Clock 15 Enable */ +#define PMC_PID16 (1 << 16) /* Bit 16: Peripheral Clock 16 Enable */ +#define PMC_PID17 (1 << 17) /* Bit 17: Peripheral Clock 17 Enable */ +#define PMC_PID18 (1 << 18) /* Bit 18: Peripheral Clock 18 Enable */ +#define PMC_PID19 (1 << 19) /* Bit 19: Peripheral Clock 19 Enable */ +#define PMC_PID20 (1 << 20) /* Bit 20: Peripheral Clock 20 Enable */ +#define PMC_PID21 (1 << 21) /* Bit 21: Peripheral Clock 21 Enable */ +#define PMC_PID22 (1 << 22) /* Bit 22: Peripheral Clock 22 Enable */ +#define PMC_PID23 (1 << 23) /* Bit 23: Peripheral Clock 23 Enable */ +#define PMC_PID24 (1 << 24) /* Bit 24: Peripheral Clock 24 Enable */ +#define PMC_PID25 (1 << 25) /* Bit 25: Peripheral Clock 25 Enable */ +#define PMC_PID26 (1 << 26) /* Bit 26: Peripheral Clock 26 Enable */ +#define PMC_PID27 (1 << 27) /* Bit 27: Peripheral Clock 27 Enable */ +#define PMC_PID28 (1 << 28) /* Bit 28: Peripheral Clock 28 Enable */ +#define PMC_PID29 (1 << 29) /* Bit 29: Peripheral Clock 29 Enable */ +#define PMC_PID30 (1 << 30) /* Bit 30: Peripheral Clock 30 Enable */ +#define PMC_PID31 (1 << 31) /* Bit 31: Peripheral Clock 31 Enable */ + +/* PMC UTMI Clock Configuration Register */ + +#define CKGR_UCKR_UPLLEN (1 << 16) /* Bit 16: UTMI PLL Enable */ +#define CKGR_UCKR_UPLLCOUNT_SHIFT (20) /* Bits 20-23: UTMI PLL Start-up Time */ +#define CKGR_UCKR_UPLLCOUNT_MASK (15 << CKGR_UCKR_UPLLCOUNT_SHIFT) + +/* PMC Clock Generator Main Oscillator Register */ + +#define CKGR_MOR_MOSCXTEN (1 << 0) /* Bit 0: Main Crystal Oscillator Enable */ +#define CKGR_MOR_MOSCXTBY (1 << 1) /* Bit 1: Main Crystal Oscillator Bypass */ +#define CKGR_MOR_WAITMODE (1 << 2) /* Bit 2: Wait Mode Command */ +#define CKGR_MOR_MOSCRCEN (1 << 3) /* Bit 3: Main On-Chip RC Oscillator Enable */ +#define CKGR_MOR_MOSCRCF_SHIFT (4) /* Bits 4-6: Main On-Chip RC Oscillator Frequency Selection */ +#define CKGR_MOR_MOSCRCF_MASK (7 << CKGR_MOR_MOSCRCF_SHIFT) +#define CKGR_MOR_MOSCXTST_SHIFT (8) /* Bits 8-16: Main Crystal Oscillator Start-up Time */ +#define CKGR_MOR_MOSCXTST_MASK (0x1ff << CKGR_MOR_MOSCXTST_SHIFT) +#define CKGR_MOR_KEY_SHIFT (16) /* Bits 16-23: Password */ +#define CKGR_MOR_KEY_MASK (0xff << CKGR_MOR_KEY_SHIFT) +#define CKGR_MOR_MOSCSEL (1 << 24) /* Bit 24: Main Oscillator Selection */ +#define CKGR_MOR_CFDEN (1 << 25) /* Bit 25: Clock Failure Detector Enable */ + + +/* PMC Clock Generator Main Clock Frequency Register */ + +#define CKGR_MCFR_MAINF_SHIFT (0) /* Bits 0-15: Main Clock Frequency */ +#define CKGR_MCFR_MAINF_MASK (0xffff << CKGR_MCFR_MAINF_SHIFT) +#define CKGR_MCFR_MAINFRDY (1 << 16) /* Bit 16: Main Clock Ready */ + +/* PMC Clock Generator PLLA Register */ + +#define CKGR_PLLAR_DIVA_SHIFT (0) /* Bits 0-7: Divider */ +#define CKGR_PLLAR_DIVA_MASK (0xff << CKGR_PLLAR_DIVA_SHIFT) +# define CKGR_PLLAR_DIVA_ZERO (0 << CKGR_PLLAR_DIVA_SHIFT) /* Divider output is 0 */ +# define CKGR_PLLAR_DIVA_BYPASS (1 << CKGR_PLLAR_DIVA_SHIFT) /* Divider is bypassed (DIVA=1) */ +# define CKGR_PLLAR_DIVA(n) ((n) << CKGR_PLLAR_DIVA_SHIFT) /* Divider output is DIVA=n, n=2..255 */ +#define CKGR_PLLAR_PLLACOUNT_SHIFT (8) /* Bits 8-13: PLLA Counter */ +#define CKGR_PLLAR_PLLACOUNT_MASK (63 << CKGR_PLLAR_PLLACOUNT_SHIFT) +#define CKGR_PLLAR_STMODE_SHIFT (14) /* Bits 14-15: Start Mode */ +#define CKGR_PLLAR_STMODE_MASK (3 << CKGR_PLLAR_STMODE_SHIFT) +# define CKGR_PLLAR_STMODE_FAST (0 << CKGR_PLLAR_STMODE_SHIFT) /* Fast Startup */ +# define CKGR_PLLAR_STMODE_NORMAL (2 << CKGR_PLLAR_STMODE_SHIFT) /* Normal Startup */ +#define CKGR_PLLAR_MULA_SHIFT (16) /* Bits 16-26: PLLA Multiplier */ +#define CKGR_PLLAR_MULA_MASK (0x7ff << CKGR_PLLAR_MULA_SHIFT) +#define CKGR_PLLAR_ONE (1 << 29) /* Bit 29: Always one */ + +/* PMC Master Clock Register */ + +#define PMC_MCKR_CSS_SHIFT (0) /* Bits 0-1: Master Clock Source Selection */ +#define PMC_MCKR_CSS_MASK (3 << PMC_MCKR_CSS_SHIFT) +# define PMC_MCKR_CSS_SLOW (0 << PMC_MCKR_CSS_SHIFT) /* Slow Clock */ +# define PMC_MCKR_CSS_MAIN (1 << PMC_MCKR_CSS_SHIFT) /* Main Clock */ +# define PMC_MCKR_CSS_PLLA (2 << PMC_MCKR_CSS_SHIFT) /* PLLA Clock */ +# define PMC_MCKR_CSS_UPLL (3 << PMC_MCKR_CSS_SHIFT) /* UPLL Clock */ +#define PMC_MCKR_PRES_SHIFT (4) /* Bits 4-6: Processor Clock Prescaler */ +#define PMC_MCKR_PRES_MASK (7 << PMC_MCKR_PRES_SHIFT) +# define PMC_MCKR_PRES_DIV1 (0 << PMC_MCKR_PRES_SHIFT) /* Selected clock */ +# define PMC_MCKR_PRES_DIV2 (1 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 2 */ +# define PMC_MCKR_PRES_DIV4 (2 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 4 */ +# define PMC_MCKR_PRES_DIV8 (3 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 8 */ +# define PMC_MCKR_PRES_DIV16 (4 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 16 */ +# define PMC_MCKR_PRES_DIV32K (5 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 32 */ +# define PMC_MCKR_PRES_DIV64 (6 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 64 */ +# define PMC_MCKR_PRES_DIV3 (7 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 3 */ +#define PMC_MCKR_UPLLDIV (1 << 13) /* Bit 13: UPLL Divider */ + +/* PMC Programmable Clock Register (0,1,2) */ + +#define PMC_PCK_CSS_SHIFT (0) /* Bits 0-2: Master Clock Source Selection */ +#define PMC_PCK_CSS_MASK (7 << PMC_PCK_CSS_MASK) +# define PMC_PCK_CSS_SLOW (0 << PMC_PCK_CSS_MASK) /* Slow Clock */ +# define PMC_PCK_CSS_MAIN (1 << PMC_PCK_CSS_MASK) /* Main Clock */ +# define PMC_PCK_CSS_PLLA (2 << PMC_PCK_CSS_MASK) /* PLLA Clock */ +# define PMC_PCK_CSS_UPLL (3 << PMC_PCK_CSS_MASK) /* UPLL Clock */ +# define PMC_PCK_CSS_MASTER (4 << PMC_PCK_CSS_MASK) /* Master Clock */ +#define PMC_PCK_PRES_SHIFT (4) /* Bits 4-6: Programmable Clock Prescaler */ +#define PMC_PCK_PRES_MASK (7 << PMC_PCK_PRES_SHIFT) +# define PMC_PCK_PRES_DIV1 (0 << PMC_PCK_PRES_SHIFT) /* Selected clock */ +# define PMC_PCK_PRES_DIV2 (1 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 2 */ +# define PMC_PCK_PRES_DIV4 (2 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 4 */ +# define PMC_PCK_PRES_DIV8 (3 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 8 */ +# define PMC_PCK_PRES_DIV16 (4 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 16 */ +# define PMC_PCK_PRES_DIV32K (5 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 32 */ +# define PMC_PCK_PRES_DIV64 (6 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 64 */ + +/* PMC Interrupt Enable Register, PMC Interrupt Disable Register, PMC Status Register, + * and PMC Interrupt Mask Register common bit-field definitions + */ + +#define PMC_INT_MOSCXTS (1 << 0) /* Bit 0: Main Crystal Oscillator Status Interrupt */ +#define PMC_INT_LOCKA (1 << 1) /* Bit 1: PLL A Lock Interrupt */ +#define PMC_INT_MCKRDY (1 << 3) /* Bit 3: Master Clock Ready Interrupt */ +#define PMC_INT_LOCKU (1 << 6) /* Bit 6: UTMI PLL Lock Interrupt */ +#define PMC_SR_OSCSELS (1 << 7) /* Bit 7: Slow Clock Oscillator Selection (SR only) */ +#define PMC_INT_PCKRDY(n) (1<<((n)+8) +#define PMC_INT_PCKRDY0 (1 << 8) /* Bit 8: Programmable Clock Ready 0 Interrupt */ +#define PMC_INT_PCKRDY1 (1 << 9) /* Bit 9: Programmable Clock Ready 1 Interrupt */ +#define PMC_INT_PCKRDY2 (1 << 10) /* Bit 10: Programmable Clock Ready 2 Interrupt */ +#define PMC_INT_MOSCSELS (1 << 16) /* Bit 16: Main Oscillator Selection Status Interrupt */ +#define PMC_INT_MOSCRCS (1 << 17) /* Bit 17: Main On-Chip RC Status Interrupt */ +#define PMC_INT_CFDEV (1 << 18) /* Bit 18: Clock Failure Detector Event Interrupt */ +#define PMC_SR_CFDS (1 << 19) /* Bit 19: Clock Failure Detector Status (SR only) */ +#define PMC_SR_FOS (1 << 20) /* Bit 20: Clock Failure Detector Fault Output Status (SR only) */ + +/* PMC Fast Startup Mode Register and PMC Fast Startup Polarity Register common bit-field + * definitions + */ + +#define PMC_FSTI(n) (1<<(n)) +#define PMC_FSTI0 (1 << 0) /* Bit 0: Fast Startup Input 0 */ +#define PMC_FSTI1 (1 << 1) /* Bit 1: Fast Startup Input 1 */ +#define PMC_FSTI2 (1 << 2) /* Bit 2: Fast Startup Input 2 */ +#define PMC_FSTI3 (1 << 3) /* Bit 3: Fast Startup Input 3 */ +#define PMC_FSTI4 (1 << 4) /* Bit 4: Fast Startup Input 4 */ +#define PMC_FSTI5 (1 << 5) /* Bit 5: Fast Startup Input 5 */ +#define PMC_FSTI6 (1 << 6) /* Bit 6: Fast Startup Input 6 */ +#define PMC_FSTI7 (1 << 7) /* Bit 7: Fast Startup Input 7 */ +#define PMC_FSTI8 (1 << 8) /* Bit 8: Fast Startup Input 8 */ +#define PMC_FSTI9 (1 << 9) /* Bit 9: Fast Startup Input 9 */ +#define PMC_FSTI10 (1 << 10) /* Bit 10: Fast Startup Input 10 */ +#define PMC_FSTI11 (1 << 11) /* Bit 11: Fast Startup Input 11 */ +#define PMC_FSTI12 (1 << 12) /* Bit 12: Fast Startup Input 12 */ +#define PMC_FSTI13 (1 << 13) /* Bit 13: Fast Startup Input 13 */ +#define PMC_FSTI14 (1 << 14) /* Bit 14: Fast Startup Input 14 */ +#define PMC_FSTI15 (1 << 15) /* Bit 15: Fast Startup Input 15 */ + +#define PMC_FSMR_RTTAL (1 << 16) /* Bit 16: RTT Alarm Enable (MR only) */ +#define PMC_FSMR_RTCAL (1 << 17) /* Bit 17: RTC Alarm Enable (MR only) */ +#define PMC_FSMR_USBAL (1 << 18) /* Bit 18: USB Alarm Enable (MR only) */ +#define PMC_FSMR_LPM (1 << 20) /* Bit 20: Low Power Mode (MR only) */ + +/* PMC Fault Output Clear Register */ + +#define PMC_FOCLR (1 << 0) /* Bit 0: Fault Output Clear */ + +/* PMC Write Protect Mode Register */ + +#define PMC_WPMR_WPEN (1 << 0) /* Bit 0: Write Protect Enable */ +#define PMC_WPMR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protect KEY */ +#define PMC_WPMR_WPKEY_MASK (0x00ffffff << PMC_WPMR_WPKEY_SHIFT) + +/* PMC Write Protect Status Register */ + +#define PMC_WPSR_WPVS (1 << 0) /* Bit 0: Write Protect Violation Status */ +#define PMC_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protect Violation Source */ +#define PMC_WPSR_WPVSRC_MASK (0xffff << PMC_WPSR_WPVSRC_SHIFT) + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +/**************************************************************************************** + * Public Data + ****************************************************************************************/ + +/**************************************************************************************** + * Public Functions + ****************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_PMC_H */ diff --git a/nuttx/arch/arm/src/sam3u/sam3u_pwm.h b/nuttx/arch/arm/src/sam3u/sam3u_pwm.h index 5890d0f67..e8278d795 100644 --- a/nuttx/arch/arm/src/sam3u/sam3u_pwm.h +++ b/nuttx/arch/arm/src/sam3u/sam3u_pwm.h @@ -1,633 +1,633 @@ -/****************************************************************************************
- * arch/arm/src/sam3u/sam3u_pwm.h
- *
- * Copyright (C) 2009 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_PWM_H
-#define __ARCH_ARM_SRC_SAM3U_SAM3U_PWM_H
-
-/****************************************************************************************
- * Included Files
- ****************************************************************************************/
-
-#include <nuttx/config.h>
-
-#include "chip.h"
-#include "sam3u_memorymap.h"
-
-/****************************************************************************************
- * Pre-processor Definitions
- ****************************************************************************************/
-
-/* PWM register offsets *****************************************************************/
-
-#define SAM3U_PWM_CLK_OFFSET 0x000 /* PWM Clock Register */
-#define SAM3U_PWM_ENA_OFFSET 0x004 /* PWM Enable Register */
-#define SAM3U_PWM_DIS_OFFSET 0x008 /* PWM Disable Register */
-#define SAM3U_PWM_SR_OFFSET 0x00c /* PWM Status Register */
-#define SAM3U_PWM_IER1_OFFSET 0x010 /* PWM Interrupt Enable Register 1 */
-#define SAM3U_PWM_IDR1_OFFSET 0x014 /* PWM Interrupt Disable Register 1 */
-#define SAM3U_PWM_IMR1_OFFSET 0x018 /* PWM Interrupt Mask Register 1 */
-#define SAM3U_PWM_ISR1_OFFSET 0x01c /* PWM Interrupt Status Register 1 */
-#define SAM3U_PWM_SCM_OFFSET 0x020 /* PWM Sync Channels Mode Register */
- /* 0x024: Reserved */
-#define SAM3U_PWM_SCUC_OFFSET 0x028 /* PWM Sync Channels Update Control Register */
-#define SAM3U_PWM_SCUP_OFFSET 0x02c /* PWM Sync Channels Update Period Register */
-#define SAM3U_PWM_SCUPUPD_OFFSET 0x030 /* PWM Sync Channels Update Period Update Register */
-#define SAM3U_PWM_IER2_OFFSET 0x034 /* PWM Interrupt Enable Register 2 */
-#define SAM3U_PWM_IDR2_OFFSET 0x038 /* PWM Interrupt Disable Register 2 */
-#define SAM3U_PWM_IMR2_OFFSET 0x03c /* PWM Interrupt Mask Register 2 */
-#define SAM3U_PWM_ISR2_OFFSET 0x040 /* PWM Interrupt Status Register 2 */
-#define SAM3U_PWM_OOV_OFFSET 0x044 /* PWM Output Override Value Register */
-#define SAM3U_PWM_OS_OFFSET 0x048 /* PWM Output Selection Register */
-#define SAM3U_PWM_OSS_OFFSET 0x04c /* PWM Output Selection Set Register */
-#define SAM3U_PWM_OSC_OFFSET 0x050 /* PWM Output Selection Clear Register */
-#define SAM3U_PWM_OSSUPD_OFFSET 0x054 /* PWM Output Selection Set Update Register */
-#define SAM3U_PWM_OSCUPD_OFFSET 0x058 /* PWM Output Selection Clear Update Register */
-#define SAM3U_PWM_FMR_OFFSET 0x05c /* PWM Fault Mode Register */
-#define SAM3U_PWM_FSR_OFFSET 0x060 /* PWM Fault Status Register */
-#define SAM3U_PWM_FCR_OFFSET 0x064 /* PWM Fault Clear Register */
-#define SAM3U_PWM_FPV_OFFSET 0x068 /* PWM Fault Protection Value Register */
-#define SAM3U_PWM_FPE_OFFSET 0x06c /* PWM Fault Protection Enable Register */
- /* 0x070-0x078: Reserved */
-#define SAM3U_PWM_EL0MR_OFFSET 0x07c /* PWM Event Line 0 Mode Register */
-#define SAM3U_PWM_EL1MR_OFFSET 0x080 /* PWM Event Line 1 Mode Register */
- /* 0x084-0x0ac: Reserved */
- /* 0x0b4-0x0e0: Reserved */
-#define SAM3U_PWM_WPCR_OFFSET 0x0e4 /* PWM Write Protect Control Register */
-#define SAM3U_PWM_WPSR_OFFSET 0x0e8 /* PWM Write Protect Status Register */
- /* 0x100-0x128: Reserved for PDC registers */
- /* 0x12c: Reserved */
-/* PWM Comparison Registers */
-
-#define SAM3U_PWMCMP_OFFSET(n) (0x130+((n)<<4))
-#define SAM3U_PWMCMP_V_OFFSET 0x00 /* PWM Comparison Value Register */
-#define SAM3U_PWMCMP_VUPD_OFFSET 0x04 /* PWM Comparison Value Update Register */
-#define SAM3U_PWMCMP_M_OFFSET 0x08 /* PWM Comparison Mode Register */
-#define SAM3U_PWMCMP_MUPD_OFFSET 0x0c /* PWM Comparison Mode Update Register */
-
-#define SAM3U_PWMCMP0_V_OFFSET 0x130 /* PWM Comparison 0 Value Register */
-#define SAM3U_PWMCMP0_VUPD_OFFSET 0x134 /* PWM Comparison 0 Value Update Register */
-#define SAM3U_PWMCMP0_M_OFFSET 0x138 /* PWM Comparison 0 Mode Register */
-#define SAM3U_PWMCMP0_MUPD_OFFSET 0x13c /* PWM Comparison 0 Mode Update Register */
-
-#define SAM3U_PWMCMP1_V_OFFSET 0x140 /* PWM Comparison 1 Value Register */
-#define SAM3U_PWMCMP1_VUPD_OFFSET 0x144 /* PWM Comparison 1 Value Update Register */
-#define SAM3U_PWMCMP1_M_OFFSET 0x148 /* PWM Comparison 1 Mode Register */
-#define SAM3U_PWMCMP1_MUPD_OFFSET 0x14c /* PWM Comparison 1 Mode Update Register */
-
-#define SAM3U_PWMCMP2_V_OFFSET 0x150 /* PWM Comparison 2 Value Register */
-#define SAM3U_PWMCMP2_VUPD_OFFSET 0x154 /* PWM Comparison 2 Value Update Register */
-#define SAM3U_PWMCMP2_M_OFFSET 0x158 /* PWM Comparison 2 Mode Register */
-#define SAM3U_PWMCMP2_MUPD_OFFSET 0x15c /* PWM Comparison 2 Mode Update Register */
-
-#define SAM3U_PWMCMP3_V_OFFSET 0x160 /* PWM Comparison 3 Value Register */
-#define SAM3U_PWMCMP3_VUPD_OFFSET 0x164 /* PWM Comparison 3 Value Update Register */
-#define SAM3U_PWMCMP3_M_OFFSET 0x168 /* PWM Comparison 3 Mode Register */
-#define SAM3U_PWMCMP3_MUPD_OFFSET 0x16c /* PWM Comparison 3 Mode Update Register */
-
-#define SAM3U_PWMCMP4_V_OFFSET 0x170 /* PWM Comparison 4 Value Register */
-#define SAM3U_PWMCMP4_VUPD_OFFSET 0x174 /* PWM Comparison 4 Value Update Register */
-#define SAM3U_PWMCMP4_M_OFFSET 0x178 /* PWM Comparison 4 Mode Register */
-#define SAM3U_PWMCMP4_MUPD_OFFSET 0x17c /* PWM Comparison 4 Mode Update Register */
-
-#define SAM3U_PWMCMP5_V_OFFSET 0x180 /* PWM Comparison 5 Value Register */
-#define SAM3U_PWMCMP5_VUPD_OFFSET 0x184 /* PWM Comparison 5 Value Update Register */
-#define SAM3U_PWMCMP5_M_OFFSET 0x188 /* PWM Comparison 5 Mode Register */
-#define SAM3U_PWMCMP5_MUPD_OFFSET 0x18c /* PWM Comparison 5 Mode Update Register */
-
-#define SAM3U_PWMCMP6_V_OFFSET 0x190 /* PWM Comparison 6 Value Register */
-#define SAM3U_PWMCMP6_VUPD_OFFSET 0x194 /* PWM Comparison 6 Value Update Register */
-#define SAM3U_PWMCMP6_M_OFFSET 0x198 /* PWM Comparison 6 Mode Register */
-#define SAM3U_PWMCMP6_MUPD_OFFSET 0x19c /* PWM Comparison 6 Mode Update Register */
-
-#define SAM3U_PWMCMP7_V_OFFSET 0x1a0 /* PWM Comparison 7 Value Register */
-#define SAM3U_PWMCMP7_VUPD_OFFSET 0x1a4 /* PWM Comparison 7 Value Update Register */
-#define SAM3U_PWMCMP7_M_OFFSET 0x1a8 /* PWM Comparison 7 Mode Register */
-#define SAM3U_PWMCMP7_MUPD_OFFSET 0x1ac /* PWM Comparison 7 Mode Update Register */
- /* 0x1b0-0x1fc: Reserved */
-/* PWM Channel Registers */
-
-#define SAM3U_PWMCH_OFFSET(n) (0x200+((n)<< 5))
-#define SAM3U_PWMCH_MR_OFFSET 0x00 /* PWM Channel Mode Register */
-#define SAM3U_PWMCH_DTY_OFFSET 0x04 /* PWM Channel Duty Cycle Register */
-#define SAM3U_PWMCH_DTYUPD_OFFSET 0x08 /* PWM Channel Duty Cycle Update Register */
-#define SAM3U_PWMCH_PRD_OFFSET 0x0c /* PWM Channel Period Register */
-#define SAM3U_PWMCH_PRDUPD_OFFSET 0x10 /* PWM Channel Period Update Register */
-#define SAM3U_PWMCH_CCNT_OFFSET 0x14 /* PWM Channel Counter Register */
-#define SAM3U_PWMCH_DT_OFFSET 0x18 /* PWM Channel Dead Time Register */
-#define SAM3U_PWMCH_DTUPD_OFFSET 0x1c /* PWM Channel Dead Time Update Register */
-
-#define SAM3U_PWMCH0_MR_OFFSET 0x200 /* PWM Channel 0 Mode Register */
-#define SAM3U_PWMCH0_DTY_OFFSET 0x204 /* PWM Channel 0 Duty Cycle Register */
-#define SAM3U_PWMCH0_DTYUPD_OFFSET 0x208 /* PWM Channel 0 Duty Cycle Update Register */
-#define SAM3U_PWMCH0_PRD_OFFSET 0x20c /* PWM Channel 0 Period Register */
-#define SAM3U_PWMCH0_PRDUPD_OFFSET 0x210 /* PWM Channel 0 Period Update Register */
-#define SAM3U_PWMCH0_CCNT_OFFSET 0x214 /* PWM Channel 0 Counter Register */
-#define SAM3U_PWMCH0_DT_OFFSET 0x218 /* PWM Channel 0 Dead Time Register */
-#define SAM3U_PWMCH0_DTUPD_OFFSET 0x21c /* PWM Channel 0 Dead Time Update Register */
-
-#define SAM3U_PWMCH1_MR_OFFSET 0x220 /* PWM Channel 1 Mode Register */
-#define SAM3U_PWMCH1_DTY_OFFSET 0x224 /* PWM Channel 1 Duty Cycle Register */
-#define SAM3U_PWMCH1_DTYUPD_OFFSET 0x228 /* PWM Channel 1 Duty Cycle Update Register */
-#define SAM3U_PWMCH1_PRD_OFFSET 0x22c /* PWM Channel 1 Period Register */
-#define SAM3U_PWMCH1_PRDUPD_OFFSET 0x230 /* PWM Channel 1 Period Update Register */
-#define SAM3U_PWMCH1_CCNT_OFFSET 0x234 /* PWM Channel 1 Counter Register */
-#define SAM3U_PWMCH1_DT_OFFSET 0x238 /* PWM Channel 1 Dead Time Register */
-#define SAM3U_PWMCH1_DTUPD_OFFSET 0x23c /* PWM Channel 1 Dead Time Update Register */
-
-#define SAM3U_PWMCH2_MR_OFFSET 0x240 /* PWM Channel 2 Mode Register */
-#define SAM3U_PWMCH2_DTY_OFFSET 0x244 /* PWM Channel 2 Duty Cycle Register */
-#define SAM3U_PWMCH2_DTYUPD_OFFSET 0x248 /* PWM Channel 2 Duty Cycle Update Register */
-#define SAM3U_PWMCH2_PRD_OFFSET 0x24c /* PWM Channel 2 Period Register */
-#define SAM3U_PWMCH2_PRDUPD_OFFSET 0x250 /* PWM Channel 2 Period Update Register */
-#define SAM3U_PWMCH2_CCNT_OFFSET 0x254 /* PWM Channel 2 Counter Register */
-#define SAM3U_PWMCH2_DT_OFFSET 0x258 /* PWM Channel 2 Dead Time Register */
-#define SAM3U_PWMCH2_DTUPD_OFFSET 0x25c /* PWM Channel 2 Dead Time Update Register */
-
-#define SAM3U_PWMCH3_MR_OFFSET 0x260 /* PWM Channel 3 Mode Register */
-#define SAM3U_PWMCH3_DTY_OFFSET 0x264 /* PWM Channel 3 Duty Cycle Register */
-#define SAM3U_PWMCH3_DTYUPD_OFFSET 0x268 /* PWM Channel 3 Duty Cycle Update Register */
-#define SAM3U_PWMCH3_PRD_OFFSET 0x26c /* PWM Channel 3 Period Register */
-#define SAM3U_PWMCH3_PRDUPD_OFFSET 0x270 /* PWM Channel 3 Period Update Register */
-#define SAM3U_PWMCH3_CCNT_OFFSET 0x274 /* PWM Channel 3 Counter Register */
-#define SAM3U_PWMCH3_DT_OFFSET 0x278 /* PWM Channel 3 Dead Time Register */
-#define SAM3U_PWMCH3_DTUPD_OFFSET 0x27c /* PWM Channel 3 Dead Time Update Register */
-
-/* PWM register adresses ****************************************************************/
-
-#define SAM3U_PWM_CLK (SAM3U_PWM_BASE+SAM3U_PWM_CLK_OFFSET)
-#define SAM3U_PWM_ENA (SAM3U_PWM_BASE+SAM3U_PWM_ENA_OFFSET)
-#define SAM3U_PWM_DIS (SAM3U_PWM_BASE+SAM3U_PWM_DIS_OFFSET)
-#define SAM3U_PWM_SR (SAM3U_PWM_BASE+SAM3U_PWM_SR_OFFSET)
-#define SAM3U_PWM_IER1 (SAM3U_PWM_BASE+SAM3U_PWM_IER1_OFFSET)
-#define SAM3U_PWM_IDR1 (SAM3U_PWM_BASE+SAM3U_PWM_IDR1_OFFSET)
-#define SAM3U_PWM_IMR1 (SAM3U_PWM_BASE+SAM3U_PWM_IMR1_OFFSET)
-#define SAM3U_PWM_ISR1 (SAM3U_PWM_BASE+SAM3U_PWM_ISR1_OFFSET)
-#define SAM3U_PWM_SCM (SAM3U_PWM_BASE+SAM3U_PWM_SCM_OFFSET)
-#define SAM3U_PWM_SCUC (SAM3U_PWM_BASE+SAM3U_PWM_SCUC_OFFSET)
-#define SAM3U_PWM_SCUP (SAM3U_PWM_BASE+SAM3U_PWM_SCUP_OFFSET)
-#define SAM3U_PWM_SCUPUPD (SAM3U_PWM_BASE+SAM3U_PWM_SCUPUPD_OFFSET)
-#define SAM3U_PWM_IER2 (SAM3U_PWM_BASE+SAM3U_PWM_IER2_OFFSET)
-#define SAM3U_PWM_IDR2 (SAM3U_PWM_BASE+SAM3U_PWM_IDR2_OFFSET)
-#define SAM3U_PWM_IMR2 (SAM3U_PWM_BASE+SAM3U_PWM_IMR2_OFFSET)
-#define SAM3U_PWM_ISR2 (SAM3U_PWM_BASE+SAM3U_PWM_ISR2_OFFSET)
-#define SAM3U_PWM_OOV (SAM3U_PWM_BASE+SAM3U_PWM_OOV_OFFSET)
-#define SAM3U_PWM_OS (SAM3U_PWM_BASE+SAM3U_PWM_OS_OFFSET)
-#define SAM3U_PWM_OSS (SAM3U_PWM_BASE+SAM3U_PWM_OSS_OFFSET)
-#define SAM3U_PWM_OSC (SAM3U_PWM_BASE+SAM3U_PWM_OSC_OFFSET)
-#define SAM3U_PWM_OSSUPD (SAM3U_PWM_BASE+SAM3U_PWM_OSSUPD_OFFSET)
-#define SAM3U_PWM_OSCUPD (SAM3U_PWM_BASE+SAM3U_PWM_OSCUPD_OFFSET)
-#define SAM3U_PWM_FMR (SAM3U_PWM_BASE+SAM3U_PWM_FMR_OFFSET)
-#define SAM3U_PWM_FSR (SAM3U_PWM_BASE+SAM3U_PWM_FSR_OFFSET)
-#define SAM3U_PWM_FCR (SAM3U_PWM_BASE+SAM3U_PWM_FCR_OFFSET)
-#define SAM3U_PWM_FPV (SAM3U_PWM_BASE+SAM3U_PWM_FPV_OFFSET)
-#define SAM3U_PWM_FPE (SAM3U_PWM_BASE+SAM3U_PWM_FPE_OFFSET)
-#define SAM3U_PWM_EL0MR (SAM3U_PWM_BASE+SAM3U_PWM_EL0MR_OFFSET)
-#define SAM3U_PWM_EL1MR (SAM3U_PWM_BASE+SAM3U_PWM_EL1MR_OFFSET)
-#define SAM3U_PWM_WPCR (SAM3U_PWM_BASE+SAM3U_PWM_WPCR_OFFSET)
-#define SAM3U_PWM_WPSR (SAM3U_PWM_BASE+SAM3U_PWM_WPSR_OFFSET)
-
-/* PWM Comparison Registers */
-
-#define SAM3U_PWCMP_BASE(n) (SAM3U_PWM_BASE+SAM3U_PWCMP_OFFSET(n))
-#define SAM3U_PWMCMP0_BASE (SAM3U_PWM_BASE+0x0130)
-#define SAM3U_PWMCMP1_BASE (SAM3U_PWM_BASE+0x0140)
-#define SAM3U_PWMCMP2_BASE (SAM3U_PWM_BASE+0x0150)
-#define SAM3U_PWMCMP3_BASE (SAM3U_PWM_BASE+0x0160)
-#define SAM3U_PWMCMP4_BASE (SAM3U_PWM_BASE+0x0170)
-#define SAM3U_PWMCMP5_BASE (SAM3U_PWM_BASE+0x0180)
-#define SAM3U_PWMCMP6_BASE (SAM3U_PWM_BASE+0x0190)
-#define SAM3U_PWMCMP7_BASE (SAM3U_PWM_BASE+0x01a0)
-
-#define SAM3U_PWMCMP0_V (SAM3U_PWMCMP0_BASE+SAM3U_PWMCMP_V_OFFSET)
-#define SAM3U_PWMCMP0_VUPD (SAM3U_PWMCMP0_BASE+SAM3U_PWMCMP_VUPD_OFFSET)
-#define SAM3U_PWMCMP0_M (SAM3U_PWMCMP0_BASE+SAM3U_PWMCMP_M_OFFSET)
-#define SAM3U_PWMCMP0_MUPD (SAM3U_PWMCMP0_BASE+SAM3U_PWMCMP_MUPD_OFFSET)
-
-#define SAM3U_PWMCMP1_V (SAM3U_PWMCMP1_BASE+SAM3U_PWMCMP_V_OFFSET)
-#define SAM3U_PWMCMP1_VUPD (SAM3U_PWMCMP1_BASE+SAM3U_PWMCMP_VUPD_OFFSET)
-#define SAM3U_PWMCMP1_M (SAM3U_PWMCMP1_BASE+SAM3U_PWMCMP_M_OFFSET)
-#define SAM3U_PWMCMP1_MUPD (SAM3U_PWMCMP1_BASE+SAM3U_PWMCMP_MUPD_OFFSET)
-
-#define SAM3U_PWMCMP2_V (SAM3U_PWMCMP2_BASE+SAM3U_PWMCMP_V_OFFSET)
-#define SAM3U_PWMCMP2_VUPD (SAM3U_PWMCMP2_BASE+SAM3U_PWMCMP_VUPD_OFFSET)
-#define SAM3U_PWMCMP2_M (SAM3U_PWMCMP2_BASE+SAM3U_PWMCMP_M_OFFSET)
-#define SAM3U_PWMCMP2_MUPD (SAM3U_PWMCMP2_BASE+SAM3U_PWMCMP_MUPD_OFFSET)
-
-#define SAM3U_PWMCMP3_V (SAM3U_PWMCMP3_BASE+SAM3U_PWMCMP_V_OFFSET)
-#define SAM3U_PWMCMP3_VUPD (SAM3U_PWMCMP3_BASE+SAM3U_PWMCMP_VUPD_OFFSET)
-#define SAM3U_PWMCMP3_M (SAM3U_PWMCMP3_BASE+SAM3U_PWMCMP_M_OFFSET)
-#define SAM3U_PWMCMP3_MUPD (SAM3U_PWMCMP3_BASE+SAM3U_PWMCMP_MUPD_OFFSET)
-
-#define SAM3U_PWMCMP4_V (SAM3U_PWMCMP4_BASE+SAM3U_PWMCMP_V_OFFSET)
-#define SAM3U_PWMCMP4_VUPD (SAM3U_PWMCMP4_BASE+SAM3U_PWMCMP_VUPD_OFFSET)
-#define SAM3U_PWMCMP4_M (SAM3U_PWMCMP4_BASE+SAM3U_PWMCMP_M_OFFSET)
-#define SAM3U_PWMCMP4_MUPD (SAM3U_PWMCMP4_BASE+SAM3U_PWMCMP_MUPD_OFFSET)
-
-#define SAM3U_PWMCMP5_V (SAM3U_PWMCMP5_BASE+SAM3U_PWMCMP_V_OFFSET)
-#define SAM3U_PWMCMP5_VUPD (SAM3U_PWMCMP5_BASE+SAM3U_PWMCMP_VUPD_OFFSET)
-#define SAM3U_PWMCMP5_M (SAM3U_PWMCMP5_BASE+SAM3U_PWMCMP_M_OFFSET)
-#define SAM3U_PWMCMP5_MUPD (SAM3U_PWMCMP5_BASE+SAM3U_PWMCMP_MUPD_OFFSET)
-
-#define SAM3U_PWMCMP6_V (SAM3U_PWMCMP6_BASE+SAM3U_PWMCMP_V_OFFSET)
-#define SAM3U_PWMCMP6_VUPD (SAM3U_PWMCMP6_BASE+SAM3U_PWMCMP_VUPD_OFFSET)
-#define SAM3U_PWMCMP6_M (SAM3U_PWMCMP6_BASE+SAM3U_PWMCMP_M_OFFSET)
-#define SAM3U_PWMCMP6_MUPD (SAM3U_PWMCMP6_BASE+SAM3U_PWMCMP_MUPD_OFFSET)
-
-#define SAM3U_PWMCMP7_V (SAM3U_PWMCMP7_BASE+SAM3U_PWMCMP_V_OFFSET)
-#define SAM3U_PWMCMP7_VUPD (SAM3U_PWMCMP7_BASE+SAM3U_PWMCMP_VUPD_OFFSET)
-#define SAM3U_PWMCMP7_M (SAM3U_PWMCMP7_BASE+SAM3U_PWMCMP_M_OFFSET)
-#define SAM3U_PWMCMP7_MUPD (SAM3U_PWMCMP7_BASE+SAM3U_PWMCMP_MUPD_OFFSET)
-
-/* PWM Channel Registers */
-
-#define SAM3U_PWCH_BASE(n) (SAM3U_PWM_BASE+SAM3U_PWCH_OFFSET(n))
-#define SAM3U_PWMCH0_BASE (SAM3U_PWM_BASE+0x0200)
-#define SAM3U_PWMCH1_BASE (SAM3U_PWM_BASE+0x0220)
-#define SAM3U_PWMCH2_BASE (SAM3U_PWM_BASE+0x0240)
-#define SAM3U_PWMCH3_BASE (SAM3U_PWM_BASE+0x0260)
-
-#define SAM3U_PWMCH0_MR (SAM3U_PWMCH0_BASE+SAM3U_PWMCH_MR_OFFSET)
-#define SAM3U_PWMCH0_DTY (SAM3U_PWMCH0_BASE+SAM3U_PWMCH_DTY_OFFSET)
-#define SAM3U_PWMCH0_DTYUPD (SAM3U_PWMCH0_BASE+SAM3U_PWMCH_DTYUPD_OFFSET)
-#define SAM3U_PWMCH0_PRD (SAM3U_PWMCH0_BASE+SAM3U_PWMCH_PRD_OFFSET)
-#define SAM3U_PWMCH0_PRDUPD (SAM3U_PWMCH0_BASE+SAM3U_PWMCH_PRDUPD_OFFSET)
-#define SAM3U_PWMCH0_CCNT (SAM3U_PWMCH0_BASE+SAM3U_PWMCH_CCNT_OFFSET)
-#define SAM3U_PWMCH0_DT (SAM3U_PWMCH0_BASE+SAM3U_PWMCH_DT_OFFSET)
-#define SAM3U_PWMCH0_DTUPD (SAM3U_PWMCH0_BASE+SAM3U_PWMCH_DTUPD_OFFSET)
-
-#define SAM3U_PWMCH1_MR (SAM3U_PWMCH1_BASE+SAM3U_PWMCH_MR_OFFSET)
-#define SAM3U_PWMCH1_DTY (SAM3U_PWMCH1_BASE+SAM3U_PWMCH_DTY_OFFSET)
-#define SAM3U_PWMCH1_DTYUPD (SAM3U_PWMCH1_BASE+SAM3U_PWMCH_DTYUPD_OFFSET)
-#define SAM3U_PWMCH1_PRD (SAM3U_PWMCH1_BASE+SAM3U_PWMCH_PRD_OFFSET)
-#define SAM3U_PWMCH1_PRDUPD (SAM3U_PWMCH1_BASE+SAM3U_PWMCH_PRDUPD_OFFSET)
-#define SAM3U_PWMCH1_CCNT (SAM3U_PWMCH1_BASE+SAM3U_PWMCH_CCNT_OFFSET)
-#define SAM3U_PWMCH1_DT (SAM3U_PWMCH1_BASE+SAM3U_PWMCH_DT_OFFSET)
-#define SAM3U_PWMCH1_DTUPD (SAM3U_PWMCH1_BASE+SAM3U_PWMCH_DTUPD_OFFSET)
-
-#define SAM3U_PWMCH2_MR (SAM3U_PWMCH2_BASE+SAM3U_PWMCH_MR_OFFSET)
-#define SAM3U_PWMCH2_DTY (SAM3U_PWMCH2_BASE+SAM3U_PWMCH_DTY_OFFSET)
-#define SAM3U_PWMCH2_DTYUPD (SAM3U_PWMCH2_BASE+SAM3U_PWMCH_DTYUPD_OFFSET)
-#define SAM3U_PWMCH2_PRD (SAM3U_PWMCH2_BASE+SAM3U_PWMCH_PRD_OFFSET)
-#define SAM3U_PWMCH2_PRDUPD (SAM3U_PWMCH2_BASE+SAM3U_PWMCH_PRDUPD_OFFSET)
-#define SAM3U_PWMCH2_CCNT (SAM3U_PWMCH2_BASE+SAM3U_PWMCH_CCNT_OFFSET)
-#define SAM3U_PWMCH2_DT (SAM3U_PWMCH2_BASE+SAM3U_PWMCH_DT_OFFSET)
-#define SAM3U_PWMCH2_DTUPD (SAM3U_PWMCH2_BASE+SAM3U_PWMCH_DTUPD_OFFSET)
-
-#define SAM3U_PWMCH3_MR (SAM3U_PWMCH3_BASE+SAM3U_PWMCH_MR_OFFSET)
-#define SAM3U_PWMCH3_DTY (SAM3U_PWMCH3_BASE+SAM3U_PWMCH_DTY_OFFSET)
-#define SAM3U_PWMCH3_DTYUPD (SAM3U_PWMCH3_BASE+SAM3U_PWMCH_DTYUPD_OFFSET)
-#define SAM3U_PWMCH3_PRD (SAM3U_PWMCH3_BASE+SAM3U_PWMCH_PRD_OFFSET)
-#define SAM3U_PWMCH3_PRDUPD (SAM3U_PWMCH3_BASE+SAM3U_PWMCH_PRDUPD_OFFSET)
-#define SAM3U_PWMCH3_CCNT (SAM3U_PWMCH3_BASE+SAM3U_PWMCH_CCNT_OFFSET)
-#define SAM3U_PWMCH3_DT (SAM3U_PWMCH3_BASE+SAM3U_PWMCH_DT_OFFSET)
-#define SAM3U_PWMCH3_DTUPD (SAM3U_PWMCH3_BASE+SAM3U_PWMCH_DTUPD_OFFSET)
-
-/* PWM register bit definitions *********************************************************/
-
-/* PWM Clock Register */
-
-#define PWM_CLK_DIVA_SHIFT (0) /* Bits 0-7: CLKA Divide Factor */
-#define PWM_CLK_DIVA_MASK (0xff << PWM_CLK_DIVA_SHIFT)
-#define PWM_CLK_PREA_SHIFT (8) /* Bits 8-11: CLKA Source Clock Selection */
-#define PWM_CLK_PREA_MASK (15 << PWM_CLK_PREA_SHIFT)
-# define PWM_CLK_PREA_MCK (0 << PWM_CLK_PREA_SHIFT) /* MCK */
-# define PWM_CLK_PREA_MCKDIV2 (1 << PWM_CLK_PREA_SHIFT) /* MCK/2 */
-# define PWM_CLK_PREA_MCKDIV4 (2 << PWM_CLK_PREA_SHIFT) /* MCK/4 */
-# define PWM_CLK_PREA_MCKDIV8 (3 << PWM_CLK_PREA_SHIFT) /* MCK/8 */
-# define PWM_CLK_PREA_MCKDIV16 (4 << PWM_CLK_PREA_SHIFT) /* MCK/16 */
-# define PWM_CLK_PREA_MCKDIV32 (5 << PWM_CLK_PREA_SHIFT) /* MCK/32 */
-# define PWM_CLK_PREA_MCKDIV64 (6 << PWM_CLK_PREA_SHIFT) /* MCK/64 */
-# define PWM_CLK_PREA_MCKDIV128 (7 << PWM_CLK_PREA_SHIFT) /* MCK/128 */
-# define PWM_CLK_PREA_MCKDIV256 (8 << PWM_CLK_PREA_SHIFT) /* MCK/256 */
-# define PWM_CLK_PREA_MCKDIV512 (9 << PWM_CLK_PREA_SHIFT) /* MCK/512 */
-# define PWM_CLK_PREA_MCKDIV1024 (10 << PWM_CLK_PREA_SHIFT) /* MCK/1024 */
-#define PWM_CLK_DIVB_SHIFT (16) /* Bits 16-23: CLKB Divide Factor */
-#define PWM_CLK_DIVB_MASK (0xff << PWM_CLK_DIVB_SHIFT)
-#define PWM_CLK_PREB_SHIFT (24) /* Bit 24-27: CLKB Source Clock Selection */
-#define PWM_CLK_PREB_MASK (15 << PWM_CLK_PREB_SHIFT)
-# define PWM_CLK_PREB_MCK (0 << PWM_CLK_PREB_SHIFT) /* MCK */
-# define PWM_CLK_PREB_MCKDIV2 (1 << PWM_CLK_PREB_SHIFT) /* MCK/2 */
-# define PWM_CLK_PREB_MCKDIV4 (2 << PWM_CLK_PREB_SHIFT) /* MCK/4 */
-# define PWM_CLK_PREB_MCKDIV8 (3 << PWM_CLK_PREB_SHIFT) /* MCK/8 */
-# define PWM_CLK_PREB_MCKDIV16 (4 << PWM_CLK_PREB_SHIFT) /* MCK/16 */
-# define PWM_CLK_PREB_MCKDIV32 (5 << PWM_CLK_PREB_SHIFT) /* MCK/32 */
-# define PWM_CLK_PREB_MCKDIV64 (6 << PWM_CLK_PREB_SHIFT) /* MCK/64 */
-# define PWM_CLK_PREB_MCKDIV128 (7 << PWM_CLK_PREB_SHIFT) /* MCK/128 */
-# define PWM_CLK_PREB_MCKDIV256 (8 << PWM_CLK_PREB_SHIFT) /* MCK/256 */
-# define PWM_CLK_PREB_MCKDIV512 (9 << PWM_CLK_PREB_SHIFT) /* MCK/512 */
-# define PWM_CLK_PREB_MCKDIV1024 (10 << PWM_CLK_PREB_SHIFT) /* MCK/1024 */
-
-/* PWM Enable Register, PWM Disable Register, and PWM Status Register common bit-field definitions */
-
-#define SAM3U_ENAB_CHID(n) (1 << ((n))
-#define SAM3U_ENAB_CHID0 (1 << 0) /* Bit 0: Counter Event Channel 0 Interrupt */
-#define SAM3U_ENAB_CHID1 (1 << 1) /* Bit 1: Counter Event Channel 1 Interrupt */
-#define SAM3U_ENAB_CHID2 (1 << 2) /* Bit 2: Counter Event Channel 2 Interrupt */
-#define SAM3U_ENAB_CHID3 (1 << 3) /* Bit 3: Counter Event Channel 3 Interrupt */
-
-/* PWM Interrupt Enable Register 1, PWM Interrupt Disable Register 1, PWM Interrupt
- * Mask Register 1, and PWM Interrupt Status Register 1 common bit definitions
- */
-
-#define SAM3U_INT_CHID(n) (1 << (n))
-#define SAM3U_INT_CHID0 (1 << 0) /* Bit 0: Counter Event Channel 0 Interrupt */
-#define SAM3U_INT_CHID1 (1 << 1) /* Bit 1: Counter Event Channel 1 Interrupt */
-#define SAM3U_INT_CHID2 (1 << 2) /* Bit 2: Counter Event Channel 2 Interrupt */
-#define SAM3U_INT_CHID3 (1 << 3) /* Bit 3: Counter Event Channel 3 Interrupt */
-#define SAM3U_INT_FCHID(n) (1 << ((n)+16))
-#define SAM3U_INT_FCHID0 (1 << 16) /* Bit 16: Fault Protection Trigger Channel 0 Interrupt */
-#define SAM3U_INT_FCHID1 (1 << 17) /* Bit 17: Fault Protection Trigger Channel 1 Interrupt */
-#define SAM3U_INT_FCHID2 (1 << 18) /* Bit 18: Fault Protection Trigger Channel 2 Interrupt */
-#define SAM3U_INT_FCHID3 (1 << 19) /* Bit 19: Fault Protection Trigger Channel 3 Interrupt */
-
-/* PWM Sync Channels Mode Register */
-
-#define PWM_SCM_SYNC(n) (1 << (n))
-#define PWM_SCM_SYNC0 (1 << 0) /* Bit 0: Synchronous Channel 0 */
-#define PWM_SCM_SYNC1 (1 << 1) /* Bit 1: Synchronous Channel 1 */
-#define PWM_SCM_SYNC2 (1 << 2) /* Bit 2: Synchronous Channel 2 */
-#define PWM_SCM_SYNC3 (1 << 3) /* Bit 3: Synchronous Channel 3 */
-#define PWM_SCM_UPDM_SHIFT (16) /* Bits 16-17: Synchronous Channels Update Mode */
-#define PWM_SCM_UPDM_MASK (3 << PWM_SCM_UPDM_SHIFT)
-# define PWM_SCM_UPDM_MANMAN (0 << PWM_SCM_UPDM_SHIFT) /* Manual write/manual update */
-# define PWM_SCM_UPDM_MANAUTO (1 << PWM_SCM_UPDM_SHIFT) /* Manual write/automatic update */
-# define PWM_SCM_UPDM_AUTOAUTO (2 << PWM_SCM_UPDM_SHIFT) /* Auto write/automatic update */
-#define PWM_SCM_PTRM (1 << 20) /* Bit 20: PDC Transfer Request Mode */
-#define PWM_SCM_PTRCS_SHIFT (21) /* Bits 21-23: PDC Transfer Request Comparison Selection */
-#define PWM_SCM_PTRCS_MASK (7 << PWM_SCM_PTRCS_SHIFT)
-
-/* PWM Sync Channels Update Control Register */
-
-#define PWM_SCUC_UPDULOCK (1 << 0) /* Bit 0: Synchronous Channels Update Unlock */
-
-/* PWM Sync Channels Update Period Register */
-
-#define PWM_SCUP_UPR_SHIFT (0) /* Bits 0-3: Update Period */
-#define PWM_SCUP_UPR_MASK (15 << PWM_SCUP_UPR_MASK)
-#define PWM_SCUP_UPRCNT_SHIFT (4) /* Bits 4-7: Update Period Counter */
-#define PWM_SCUP_UPRCNT_MASK (15 << PWM_SCUP_UPRCNT_SHIFT)
-
-/* PWM Sync Channels Update Period Update Register */
-
-#define PWM_SCUPUPD_SHIFT (0) /* Bits 0-3: Update Period Update */
-#define PWM_SCUPUPD_MASK (15 << PWM_SCUPUPD_SHIFT)
-
-/* PWM Interrupt Enable Register 2, PWM Interrupt Disable Register 2, PWM Interrupt Mask Register 2, and PWM Interrupt Status Register 2 common bit-field definitions */
-
-#define SAM3U_INT_WRDY (1 << 0) /* Bit 0: Write Ready Update Interrupt */
-#define SAM3U_INT_ENDTX (1 << 1) /* Bit 1: PDC End of TX Buffer Interrupt */
-#define SAM3U_INT_TXBUFE (1 << 2) /* Bit 2: PDC TX Buffer Empty Interrupt */
-#define SAM3U_INT_UNRE (1 << 3) /* Bit 3: Synch Update Underrun Error Interrupt */
-#define SAM3U_INT_CMPM(n) (1 << ((n)+8))
-#define SAM3U_INT_CMPM0 (1 << 8) /* Bit 8: Comparison 0 Match Interrupt */
-#define SAM3U_INT_CMPM1 (1 << 9) /* Bit 9: Comparison 1 Match Interrupt */
-#define SAM3U_INT_CMPM2 (1 << 10) /* Bit 10: Comparison 2 Match Interrupt */
-#define SAM3U_INT_CMPM3 (1 << 11) /* Bit 11: Comparison 3 Match Interrupt */
-#define SAM3U_INT_CMPM4 (1 << 12) /* Bit 12: Comparison 4 Match Interrupt */
-#define SAM3U_INT_CMPM5 (1 << 13) /* Bit 13: Comparison 5 Match Interrupt */
-#define SAM3U_INT_CMPM6 (1 << 14) /* Bit 14: Comparison 6 Match Interrupt */
-#define SAM3U_INT_CMPM7 (1 << 15) /* Bit 15: Comparison 7 Match Interrupt */
-#define SAM3U_INT_CMPU(n) (1 << ((n)+16))
-#define SAM3U_INT_CMPU0 (1 << 16) /* Bit 16: Comparison o Update Interrupt */
-#define SAM3U_INT_CMPU1 (1 << 17) /* Bit 17: Comparison 1 Update Interrupt */
-#define SAM3U_INT_CMPU2 (1 << 18) /* Bit 18: Comparison 2 Update Interrupt */
-#define SAM3U_INT_CMPU3 (1 << 19) /* Bit 19: Comparison 3 Update Interrupt */
-#define SAM3U_INT_CMPU4 (1 << 20) /* Bit 20: Comparison 4 Update Interrupt */
-#define SAM3U_INT_CMPU5 (1 << 21) /* Bit 21: Comparison 5 Update Interrupt */
-#define SAM3U_INT_CMPU6 (1 << 22) /* Bit 22: Comparison 6 Update Interrupt */
-#define SAM3U_INT_CMPU7 (1 << 23) /* Bit 23: Comparison 7 Update Interrupt */
-
-/* PWM Output Override Value Register, PWM Output Selection Register, PWM Output
- * Selection Set Register, PWM Output Selection Clear Register, PWM Output Selection
- * Set Update Register, and PWM Output Selection Clear Update Register common bit-field
- * definitions
- */
-
-#define PWM_OUT_OH(n) (1 << (n))
-#define PWM_OUT_OH0 (1 << 0) /* Bit 0: Value for PWMH output of the channel 0 */
-#define PWM_OUT_OH1 (1 << 1) /* Bit 1: Value for PWMH output of the channel 1 */
-#define PWM_OUT_OH2 (1 << 2) /* Bit 2: Value for PWMH output of the channel 2 */
-#define PWM_OUT_OH3 (1 << 3) /* Bit 3: Value for PWMH output of the channel 3 */
-#define PWM_OUT_OL(n) (1 << ((n)+16))
-#define PWM_OUT_OL0 (1 << 16) /* Bit 16: Value for PWML output of the channel 0 */
-#define PWM_OUT_OL1 (1 << 17) /* Bit 17: Value for PWML output of the channel 1 */
-#define PWM_OUT_OL2 (1 << 18) /* Bit 18: Value for PWML output of the channel 2 */
-#define PWM_OUT_OL3 (1 << 19) /* Bit 19: Value for PWML output of the channel 3 */
-
-/* PWM Fault Mode Register */
-
-#define PWM_FMR_FPOL(n) (1 << (n))
-#define PWM_FMR_FPOL0 (1 << 0) /* Bit 0: Fault 0 Polarity */
-#define PWM_FMR_FPOL1 (1 << 1) /* Bit 1: Fault 1 Polarity */
-#define PWM_FMR_FPOL2 (1 << 2) /* Bit 2: Fault 2 Polarity */
-#define PWM_FMR_FPOL3 (1 << 3) /* Bit 3: Fault 3 Polarity */
-#define PWM_FMR_FMOD(n) (1 << ((n)+8))
-#define PWM_FMR_FMOD0 (1 << 8) /* Bit 8: Fault 0 Activation Mode */
-#define PWM_FMR_FMOD1 (1 << 9) /* Bit 9: Fault 1 Activation Mode */
-#define PWM_FMR_FMOD2 (1 << 10) /* Bit 10: Fault 2 Activation Mode */
-#define PWM_FMR_FMOD3 (1 << 11) /* Bit 11: Fault 3 Activation Mode */
-#define PWM_FMR_FFIL(n) (1 << ((n)+16))
-#define PWM_FMR_FFIL0 (1 << 16) /* Bit 16: Fault 0 Filter */
-#define PWM_FMR_FFIL1 (1 << 17) /* Bit 17: Fault 1 Filter */
-#define PWM_FMR_FFIL2 (1 << 18) /* Bit 18: Fault 2 Filter */
-#define PWM_FMR_FFIL3 (1 << 19) /* Bit 19: Fault 3 Filter */
-
-/* PWM Fault Status Register */
-
-#define PWM_FSR_FIV(n) (1 << (n))
-#define PWM_FSR_FIV0 (1 << 0) /* Bit 0: Fault Input 0 Value */
-#define PWM_FSR_FIV1 (1 << 1) /* Bit 1: Fault Input 1 Value */
-#define PWM_FSR_FIV2 (1 << 2) /* Bit 2: Fault Input 2 Value */
-#define PWM_FSR_FIV3 (1 << 3) /* Bit 3: Fault Input 3 Value */
-#define PWM_FSR_FS(n) (1 << ((n)+8))
-#define PWM_FSR_FS0 (1 << 8) /* Bit 8: Fault 0 Status */
-#define PWM_FSR_FS1 (1 << 9) /* Bit 9: Fault 1 Status */
-#define PWM_FSR_FS2 (1 << 10) /* Bit 10: Fault 2 Status */
-#define PWM_FSR_FS3 (1 << 11) /* Bit 11: Fault 3 Status */
-
-/* PWM Fault Clear Register */
-
-#define PWM_FCR_FCLR(n) (1 << (n))
-#define PWM_FCR_FCLR0 (1 << 0) /* Bit 0: Fault 0 Clear */
-#define PWM_FCR_FCLR1 (1 << 1) /* Bit 1: Fault 1 Clear */
-#define PWM_FCR_FCLR2 (1 << 2) /* Bit 2: Fault 2 Clear */
-#define PWM_FCR_FCLR3 (1 << 3) /* Bit 3: Fault 3 Clear */
-
-/* PWM Fault Protection Value Register */
-
-#define PWM_FPV_FPVH(n) (1 << (n))
-#define PWM_FPV_FPVH0 (1 << 0) /* Bit 0: Fault Protection Value PWMH output channel 0 */
-#define PWM_FPV_FPVH1 (1 << 1) /* Bit 1: Fault Protection Value PWMH output channel 1 */
-#define PWM_FPV_FPVH2 (1 << 2) /* Bit 2: Fault Protection Value PWMH output channel 2 */
-#define PWM_FPV_FPVH3 (1 << 3) /* Bit 3: Fault Protection Value PWMH output channel 3 */
-#define PWM_FPV_FPVL(n) (1 << ((n)+16))
-#define PWM_FPV_FPVL0 (1 << 16) /* Bit 16: Fault Protection Value PWML output channel 0 */
-#define PWM_FPV_FPVL1 (1 << 17) /* Bit 17: Fault Protection Value PWML output channel 1 */
-#define PWM_FPV_FPVL2 (1 << 18) /* Bit 18: Fault Protection Value PWML output channel 2 */
-#define PWM_FPV_FPVL3 (1 << 19) /* Bit 19: Fault Protection Value PWML output channel 3 */
-
-/* PWM Fault Protection Enable Register */
-
-#define PWM_FPE_FPEN(n,y) (1 << (((n)<<8)+y))
-#define PWM_FPE_FPE0(y) (1 << (y)) /* Bits 0-7: Fault Protection Enable Fault=y chan=0 */
-#define PWM_FPE_FPE1(y) (1 << ((y)+8)) /* Bits 8-15: Fault Protection Enable Fault=y chan=1 */
-#define PWM_FPE_FPE2(y) (1 << ((y)+16)) /* Bits 16-23: Fault Protection Enable Fault=y chan=2 */
-#define PWM_FPE_FPE3(y) (1 << ((y)+24) /* Bits 24-31: Fault Protection Enable Fault=y chan=3 */
-
-/* PWM Event Line 1/2 Register */
-
-#define PWM_ELMR_CSEL(n) (1 << (n))
-#define PWM_ELMR_CSEL0 (1 << 0) /* Bit 0: Comparison 0 Selection */
-#define PWM_ELMR_CSEL1 (1 << 1) /* Bit 1: Comparison 1 Selection */
-#define PWM_ELMR_CSEL2 (1 << 2) /* Bit 2: Comparison 2 Selection */
-#define PWM_ELMR_CSEL3 (1 << 3) /* Bit 3: Comparison 3 Selection */
-#define PWM_ELMR_CSEL4 (1 << 4) /* Bit 4: Comparison 4 Selection */
-#define PWM_ELMR_CSEL5 (1 << 5) /* Bit 5: Comparison 5 Selection */
-#define PWM_ELMR_CSEL6 (1 << 6) /* Bit 6: Comparison 6 Selection */
-#define PWM_ELMR_CSEL7 (1 << 7) /* Bit 7: Comparison 7 Selection */
-
-/* PWM Write Protect Control Register */
-
-#define PWM_WPCR_WPCMD_SHIFT (0) /* Bits 0-1: Write Protect Command */
-#define PWM_WPCR_WPCMD_MASK (3 << PWM_WPCR_WPCMD_SHIFT)
-#define PWM_WPCR_WPRG(n) (1 << ((n)+2))
-#define PWM_WPCR_WPRG0 (1 << 2) /* Bit 2: Write Protect Register Group 0 */
-#define PWM_WPCR_WPRG1 (1 << 3) /* Bit 3: Write Protect Register Group 1 */
-#define PWM_WPCR_WPRG2 (1 << 4) /* Bit 4: Write Protect Register Group 2 */
-#define PWM_WPCR_WPRG3 (1 << 5) /* Bit 5: Write Protect Register Group 3 */
-#define PWM_WPCR_WPRG4 (1 << 6) /* Bit 6: Write Protect Register Group 4 */
-#define PWM_WPCR_WPRG5 (1 << 7) /* Bit 7: Write Protect Register Group 5 */
-#define PWM_WPCR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protect Key */
-#define PWM_WPCR_WPKEY_MASK (0x00ffffff << PWM_WPCR_WPKEY_SHIFT)
-
-/* PWM Write Protect Status Register */
-
-#define PWM_WPSR_WPSWS(n) (1 << (n))
-#define PWM_WPSR_WPSWS0 (1 << 0) /* Bit 0: Write Protect SW Status */
-#define PWM_WPSR_WPSWS1 (1 << 1) /* Bit 1: Write Protect SW Status */
-#define PWM_WPSR_WPSWS2 (1 << 2) /* Bit 2: Write Protect SW Status */
-#define PWM_WPSR_WPSWS3 (1 << 3) /* Bit 3: Write Protect SW Status */
-#define PWM_WPSR_WPSWS4 (1 << 4) /* Bit 4: Write Protect SW Status */
-#define PWM_WPSR_WPSWS5 (1 << 5) /* Bit 5: Write Protect SW Status */
-#define PWM_WPSR_WPVS (1 << 7) /* Bit 7: Write Protect Violation Status */
-#define PWM_WPSR_WPHWS(n) (1 << ((n)+8))
-#define PWM_WPSR_WPHWS0 (1 << 8) /* Bit 8: Write Protect HW Status */
-#define PWM_WPSR_WPHWS1 (1 << 9) /* Bit 9: Write Protect HW Status */
-#define PWM_WPSR_WPHWS2 (1 << 10) /* Bit 10: Write Protect HW Status */
-#define PWM_WPSR_WPHWS3 (1 << 11) /* Bit 11: Write Protect HW Status */
-#define PWM_WPSR_WPHWS4 (1 << 12) /* Bit 12: Write Protect HW Status */
-#define PWM_WPSR_WPHWS5 (1 << 13) /* Bit 13: Write Protect HW Status */
-#define PWM_WPSR_WPVSRC_SHIFT (16) /* Bits 16-31: Write Protect Violation Source */
-#define PWM_WPSR_WPVSRC_MASK (0xffff << PWM_WPSR_WPVSRC_SHIFT)
-
-/* PWM Comparison x Value Register and PWM Comparison x Value Update Register */
-
-#define PWMCMP_CV_SHIFT (0) /* Bits 0-23: Comparison x Value */
-#define PWMCMP_CV_MASK (0x00ffffff << PWMCMP_CV_SHIFT)
-#define PWMCMP_CVM (1 << 24) /* Bit 24: Comparison x Value Mode */
-
-/* PWM Comparison x Mode Register and PWM Comparison x Mode Update Register */
-
-#define PWMCMP_CEN (1 << 0) /* Bit 0: Comparison x Enable */
-#define PWMCMP_CTR_SHIFT (4) /* Bits 4-7: Comparison x Trigger */
-#define PWMCMP_CTR_MASK (15 << PWMCMP_CTR_SHIFT)
-#define PWMCMP_CPR_SHIFT (8) /* Bits 8-11: Comparison x Period */
-#define PWMCMP_CPR_MASK (15 << PWMCMP_CPR_SHIFT)
-#define PWMCMP_M_CPRCNT_SHIFT (12) /* Bits 12-15: Comparison x Period Count (M only) */
-#define PWMCMP_M_CPRCNT_MASK (15 << PWMCMP_M_CPRCNT_SHIFT)
-#define PWMCMP_CUPR_SHIFT (16) /* Bits 16-19: Comparison x Update Period */
-#define PWMCMP_CUPR_MASK (15 << PWMCMP_CUPR_SHIFT)
-#define PWMCMP_M_CUPRCNT_SHIFT (20) /* Bits 20-23: Comparison x Update Period Counter (M only) */
-#define PWMCMP_M_CUPRCNT_MASK (15 << PWMCMP_M_CUPRCNT_SHIFT)
-
-/* PWM Channel Mode Register */
-
-#define PWMCH_MR_CPRE_SHIFT (0) /* Bits 0-3: Channel Pre-scaler */
-#define PWMCH_MR_CPRE_MASK (15 << PWMCH_MR_CPRE_SHIFT)
-# define PWMCH_MR_CPRE_MCK (0 << PWMCH_MR_CPRE_SHIFT) /* MCK */
-# define PWMCH_MR_CPRE_MCKDIV2 (1 << PWMCH_MR_CPRE_SHIFT) /* MCK/2 */
-# define PWMCH_MR_CPRE_MCKDIV4 (2 << PWMCH_MR_CPRE_SHIFT) /* MCK/4 */
-# define PWMCH_MR_CPRE_MCKDIV8 (3 << PWMCH_MR_CPRE_SHIFT) /* MCK/8 */
-# define PWMCH_MR_CPRE_MCKDIV16 (4 << PWMCH_MR_CPRE_SHIFT) /* MCK/16 */
-# define PWMCH_MR_CPRE_MCKDIV32 (5 << PWMCH_MR_CPRE_SHIFT) /* MCK/32 */
-# define PWMCH_MR_CPRE_MCKDIV64 (6 << PWMCH_MR_CPRE_SHIFT) /* MCK/64 */
-# define PWMCH_MR_CPRE_MCKDIV128 (7 << PWMCH_MR_CPRE_SHIFT) /* MCK/128 */
-# define PWMCH_MR_CPRE_MCKDIV256 (8 << PWMCH_MR_CPRE_SHIFT) /* MCK/256 */
-# define PWMCH_MR_CPRE_MCKDIV512 (9 << PWMCH_MR_CPRE_SHIFT) /* MCK/512 */
-# define PWMCH_MR_CPRE_MCKDIV1024 (10 << PWMCH_MR_CPRE_SHIFT) /* MCK/1024 */
-# define PWMCH_MR_CPRE_CLKA (11 << PWMCH_MR_CPRE_SHIFT) /*CLKA */
-# define PWMCH_MR_CPRE_CLKB (12 << PWMCH_MR_CPRE_SHIFT) /* CLKB */
-#define PWMCH_MR_CALG (1 << 8) /* Bit 8: Channel Alignment */
-#define PWMCH_MR_CPOL (1 << 9) /* Bit 9: Channel Polarity */
-#define PWMCH_MR_CES (1 << 10) /* Bit 10: Counter Event Selection */
-#define PWMCH_MR_DTE (1 << 16) /* Bit 16: Dead-Time Generator Enable */
-#define PWMCH_MR_DTHI (1 << 17) /* Bit 17: Dead-Time PWMHx Output Inverted */
-#define PWMCH_MR_DTLI (1 << 18) /* Bit 18: Dead-Time PWMLx Output Inverted */
-
-/* PWM Channel Duty Cycle Register and PWM Channel Duty Cycle Update Register common bit-field definitions */
-
-#define PWMCH_DTY_SHIFT (0) /* Bits 0-23: Channel Duty-Cycle */
-#define PWMCH_DTY_MASK (0x00ffffff << PWMCH_DTY_SHIFT)
-
-/* PWM Channel Period Register and PWM Channel Period Update Register common bit-field definitions */
-
-#define PWMCH_PRD_SHIFT (0) /* Bits 0-23: Channel Period */
-#define PWMCH_PRD_MASK (0x00ffffff << PWMCH_PRD_SHIFT)
-
-/* PWM Channel Counter Register */
-
-#define PWMCH_CCNT_SHIFT (0) /* Bits 0-23: Channel Counter Register */
-#define PWMCH_CCNT_MASK (0x00ffffff << PWMCH_CCNT_SHIFT)
-
-/* PWM Channel Dead Time Register and PWM Channel Dead Time Update Register common bit-field definitions */
-
-#define PWMCH_DTH_SHIFT (0) /* Bits 0-15: Dead-Time Value for PWMHx Output */
-#define PWMCH_DTH_MASK (0xffff << PWMCH_DTH_SHIFT)
-#define PWMCH_DTL_SHIFT (16) /* Bits 16-31: Dead-Time Value for PWMLx Output */
-#define PWMCH_DTL_MASK (0xffff << PWMCH_DTL_SHIFT)
-
-/****************************************************************************************
- * Public Types
- ****************************************************************************************/
-
-/****************************************************************************************
- * Public Data
- ****************************************************************************************/
-
-/****************************************************************************************
- * Public Functions
- ****************************************************************************************/
-
-#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_PWM_H */
+/**************************************************************************************** + * arch/arm/src/sam3u/sam3u_pwm.h + * + * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_PWM_H +#define __ARCH_ARM_SRC_SAM3U_SAM3U_PWM_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +#include <nuttx/config.h> + +#include "chip.h" +#include "sam3u_memorymap.h" + +/**************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************/ + +/* PWM register offsets *****************************************************************/ + +#define SAM3U_PWM_CLK_OFFSET 0x000 /* PWM Clock Register */ +#define SAM3U_PWM_ENA_OFFSET 0x004 /* PWM Enable Register */ +#define SAM3U_PWM_DIS_OFFSET 0x008 /* PWM Disable Register */ +#define SAM3U_PWM_SR_OFFSET 0x00c /* PWM Status Register */ +#define SAM3U_PWM_IER1_OFFSET 0x010 /* PWM Interrupt Enable Register 1 */ +#define SAM3U_PWM_IDR1_OFFSET 0x014 /* PWM Interrupt Disable Register 1 */ +#define SAM3U_PWM_IMR1_OFFSET 0x018 /* PWM Interrupt Mask Register 1 */ +#define SAM3U_PWM_ISR1_OFFSET 0x01c /* PWM Interrupt Status Register 1 */ +#define SAM3U_PWM_SCM_OFFSET 0x020 /* PWM Sync Channels Mode Register */ + /* 0x024: Reserved */ +#define SAM3U_PWM_SCUC_OFFSET 0x028 /* PWM Sync Channels Update Control Register */ +#define SAM3U_PWM_SCUP_OFFSET 0x02c /* PWM Sync Channels Update Period Register */ +#define SAM3U_PWM_SCUPUPD_OFFSET 0x030 /* PWM Sync Channels Update Period Update Register */ +#define SAM3U_PWM_IER2_OFFSET 0x034 /* PWM Interrupt Enable Register 2 */ +#define SAM3U_PWM_IDR2_OFFSET 0x038 /* PWM Interrupt Disable Register 2 */ +#define SAM3U_PWM_IMR2_OFFSET 0x03c /* PWM Interrupt Mask Register 2 */ +#define SAM3U_PWM_ISR2_OFFSET 0x040 /* PWM Interrupt Status Register 2 */ +#define SAM3U_PWM_OOV_OFFSET 0x044 /* PWM Output Override Value Register */ +#define SAM3U_PWM_OS_OFFSET 0x048 /* PWM Output Selection Register */ +#define SAM3U_PWM_OSS_OFFSET 0x04c /* PWM Output Selection Set Register */ +#define SAM3U_PWM_OSC_OFFSET 0x050 /* PWM Output Selection Clear Register */ +#define SAM3U_PWM_OSSUPD_OFFSET 0x054 /* PWM Output Selection Set Update Register */ +#define SAM3U_PWM_OSCUPD_OFFSET 0x058 /* PWM Output Selection Clear Update Register */ +#define SAM3U_PWM_FMR_OFFSET 0x05c /* PWM Fault Mode Register */ +#define SAM3U_PWM_FSR_OFFSET 0x060 /* PWM Fault Status Register */ +#define SAM3U_PWM_FCR_OFFSET 0x064 /* PWM Fault Clear Register */ +#define SAM3U_PWM_FPV_OFFSET 0x068 /* PWM Fault Protection Value Register */ +#define SAM3U_PWM_FPE_OFFSET 0x06c /* PWM Fault Protection Enable Register */ + /* 0x070-0x078: Reserved */ +#define SAM3U_PWM_EL0MR_OFFSET 0x07c /* PWM Event Line 0 Mode Register */ +#define SAM3U_PWM_EL1MR_OFFSET 0x080 /* PWM Event Line 1 Mode Register */ + /* 0x084-0x0ac: Reserved */ + /* 0x0b4-0x0e0: Reserved */ +#define SAM3U_PWM_WPCR_OFFSET 0x0e4 /* PWM Write Protect Control Register */ +#define SAM3U_PWM_WPSR_OFFSET 0x0e8 /* PWM Write Protect Status Register */ + /* 0x100-0x128: Reserved for PDC registers */ + /* 0x12c: Reserved */ +/* PWM Comparison Registers */ + +#define SAM3U_PWMCMP_OFFSET(n) (0x130+((n)<<4)) +#define SAM3U_PWMCMP_V_OFFSET 0x00 /* PWM Comparison Value Register */ +#define SAM3U_PWMCMP_VUPD_OFFSET 0x04 /* PWM Comparison Value Update Register */ +#define SAM3U_PWMCMP_M_OFFSET 0x08 /* PWM Comparison Mode Register */ +#define SAM3U_PWMCMP_MUPD_OFFSET 0x0c /* PWM Comparison Mode Update Register */ + +#define SAM3U_PWMCMP0_V_OFFSET 0x130 /* PWM Comparison 0 Value Register */ +#define SAM3U_PWMCMP0_VUPD_OFFSET 0x134 /* PWM Comparison 0 Value Update Register */ +#define SAM3U_PWMCMP0_M_OFFSET 0x138 /* PWM Comparison 0 Mode Register */ +#define SAM3U_PWMCMP0_MUPD_OFFSET 0x13c /* PWM Comparison 0 Mode Update Register */ + +#define SAM3U_PWMCMP1_V_OFFSET 0x140 /* PWM Comparison 1 Value Register */ +#define SAM3U_PWMCMP1_VUPD_OFFSET 0x144 /* PWM Comparison 1 Value Update Register */ +#define SAM3U_PWMCMP1_M_OFFSET 0x148 /* PWM Comparison 1 Mode Register */ +#define SAM3U_PWMCMP1_MUPD_OFFSET 0x14c /* PWM Comparison 1 Mode Update Register */ + +#define SAM3U_PWMCMP2_V_OFFSET 0x150 /* PWM Comparison 2 Value Register */ +#define SAM3U_PWMCMP2_VUPD_OFFSET 0x154 /* PWM Comparison 2 Value Update Register */ +#define SAM3U_PWMCMP2_M_OFFSET 0x158 /* PWM Comparison 2 Mode Register */ +#define SAM3U_PWMCMP2_MUPD_OFFSET 0x15c /* PWM Comparison 2 Mode Update Register */ + +#define SAM3U_PWMCMP3_V_OFFSET 0x160 /* PWM Comparison 3 Value Register */ +#define SAM3U_PWMCMP3_VUPD_OFFSET 0x164 /* PWM Comparison 3 Value Update Register */ +#define SAM3U_PWMCMP3_M_OFFSET 0x168 /* PWM Comparison 3 Mode Register */ +#define SAM3U_PWMCMP3_MUPD_OFFSET 0x16c /* PWM Comparison 3 Mode Update Register */ + +#define SAM3U_PWMCMP4_V_OFFSET 0x170 /* PWM Comparison 4 Value Register */ +#define SAM3U_PWMCMP4_VUPD_OFFSET 0x174 /* PWM Comparison 4 Value Update Register */ +#define SAM3U_PWMCMP4_M_OFFSET 0x178 /* PWM Comparison 4 Mode Register */ +#define SAM3U_PWMCMP4_MUPD_OFFSET 0x17c /* PWM Comparison 4 Mode Update Register */ + +#define SAM3U_PWMCMP5_V_OFFSET 0x180 /* PWM Comparison 5 Value Register */ +#define SAM3U_PWMCMP5_VUPD_OFFSET 0x184 /* PWM Comparison 5 Value Update Register */ +#define SAM3U_PWMCMP5_M_OFFSET 0x188 /* PWM Comparison 5 Mode Register */ +#define SAM3U_PWMCMP5_MUPD_OFFSET 0x18c /* PWM Comparison 5 Mode Update Register */ + +#define SAM3U_PWMCMP6_V_OFFSET 0x190 /* PWM Comparison 6 Value Register */ +#define SAM3U_PWMCMP6_VUPD_OFFSET 0x194 /* PWM Comparison 6 Value Update Register */ +#define SAM3U_PWMCMP6_M_OFFSET 0x198 /* PWM Comparison 6 Mode Register */ +#define SAM3U_PWMCMP6_MUPD_OFFSET 0x19c /* PWM Comparison 6 Mode Update Register */ + +#define SAM3U_PWMCMP7_V_OFFSET 0x1a0 /* PWM Comparison 7 Value Register */ +#define SAM3U_PWMCMP7_VUPD_OFFSET 0x1a4 /* PWM Comparison 7 Value Update Register */ +#define SAM3U_PWMCMP7_M_OFFSET 0x1a8 /* PWM Comparison 7 Mode Register */ +#define SAM3U_PWMCMP7_MUPD_OFFSET 0x1ac /* PWM Comparison 7 Mode Update Register */ + /* 0x1b0-0x1fc: Reserved */ +/* PWM Channel Registers */ + +#define SAM3U_PWMCH_OFFSET(n) (0x200+((n)<< 5)) +#define SAM3U_PWMCH_MR_OFFSET 0x00 /* PWM Channel Mode Register */ +#define SAM3U_PWMCH_DTY_OFFSET 0x04 /* PWM Channel Duty Cycle Register */ +#define SAM3U_PWMCH_DTYUPD_OFFSET 0x08 /* PWM Channel Duty Cycle Update Register */ +#define SAM3U_PWMCH_PRD_OFFSET 0x0c /* PWM Channel Period Register */ +#define SAM3U_PWMCH_PRDUPD_OFFSET 0x10 /* PWM Channel Period Update Register */ +#define SAM3U_PWMCH_CCNT_OFFSET 0x14 /* PWM Channel Counter Register */ +#define SAM3U_PWMCH_DT_OFFSET 0x18 /* PWM Channel Dead Time Register */ +#define SAM3U_PWMCH_DTUPD_OFFSET 0x1c /* PWM Channel Dead Time Update Register */ + +#define SAM3U_PWMCH0_MR_OFFSET 0x200 /* PWM Channel 0 Mode Register */ +#define SAM3U_PWMCH0_DTY_OFFSET 0x204 /* PWM Channel 0 Duty Cycle Register */ +#define SAM3U_PWMCH0_DTYUPD_OFFSET 0x208 /* PWM Channel 0 Duty Cycle Update Register */ +#define SAM3U_PWMCH0_PRD_OFFSET 0x20c /* PWM Channel 0 Period Register */ +#define SAM3U_PWMCH0_PRDUPD_OFFSET 0x210 /* PWM Channel 0 Period Update Register */ +#define SAM3U_PWMCH0_CCNT_OFFSET 0x214 /* PWM Channel 0 Counter Register */ +#define SAM3U_PWMCH0_DT_OFFSET 0x218 /* PWM Channel 0 Dead Time Register */ +#define SAM3U_PWMCH0_DTUPD_OFFSET 0x21c /* PWM Channel 0 Dead Time Update Register */ + +#define SAM3U_PWMCH1_MR_OFFSET 0x220 /* PWM Channel 1 Mode Register */ +#define SAM3U_PWMCH1_DTY_OFFSET 0x224 /* PWM Channel 1 Duty Cycle Register */ +#define SAM3U_PWMCH1_DTYUPD_OFFSET 0x228 /* PWM Channel 1 Duty Cycle Update Register */ +#define SAM3U_PWMCH1_PRD_OFFSET 0x22c /* PWM Channel 1 Period Register */ +#define SAM3U_PWMCH1_PRDUPD_OFFSET 0x230 /* PWM Channel 1 Period Update Register */ +#define SAM3U_PWMCH1_CCNT_OFFSET 0x234 /* PWM Channel 1 Counter Register */ +#define SAM3U_PWMCH1_DT_OFFSET 0x238 /* PWM Channel 1 Dead Time Register */ +#define SAM3U_PWMCH1_DTUPD_OFFSET 0x23c /* PWM Channel 1 Dead Time Update Register */ + +#define SAM3U_PWMCH2_MR_OFFSET 0x240 /* PWM Channel 2 Mode Register */ +#define SAM3U_PWMCH2_DTY_OFFSET 0x244 /* PWM Channel 2 Duty Cycle Register */ +#define SAM3U_PWMCH2_DTYUPD_OFFSET 0x248 /* PWM Channel 2 Duty Cycle Update Register */ +#define SAM3U_PWMCH2_PRD_OFFSET 0x24c /* PWM Channel 2 Period Register */ +#define SAM3U_PWMCH2_PRDUPD_OFFSET 0x250 /* PWM Channel 2 Period Update Register */ +#define SAM3U_PWMCH2_CCNT_OFFSET 0x254 /* PWM Channel 2 Counter Register */ +#define SAM3U_PWMCH2_DT_OFFSET 0x258 /* PWM Channel 2 Dead Time Register */ +#define SAM3U_PWMCH2_DTUPD_OFFSET 0x25c /* PWM Channel 2 Dead Time Update Register */ + +#define SAM3U_PWMCH3_MR_OFFSET 0x260 /* PWM Channel 3 Mode Register */ +#define SAM3U_PWMCH3_DTY_OFFSET 0x264 /* PWM Channel 3 Duty Cycle Register */ +#define SAM3U_PWMCH3_DTYUPD_OFFSET 0x268 /* PWM Channel 3 Duty Cycle Update Register */ +#define SAM3U_PWMCH3_PRD_OFFSET 0x26c /* PWM Channel 3 Period Register */ +#define SAM3U_PWMCH3_PRDUPD_OFFSET 0x270 /* PWM Channel 3 Period Update Register */ +#define SAM3U_PWMCH3_CCNT_OFFSET 0x274 /* PWM Channel 3 Counter Register */ +#define SAM3U_PWMCH3_DT_OFFSET 0x278 /* PWM Channel 3 Dead Time Register */ +#define SAM3U_PWMCH3_DTUPD_OFFSET 0x27c /* PWM Channel 3 Dead Time Update Register */ + +/* PWM register adresses ****************************************************************/ + +#define SAM3U_PWM_CLK (SAM3U_PWM_BASE+SAM3U_PWM_CLK_OFFSET) +#define SAM3U_PWM_ENA (SAM3U_PWM_BASE+SAM3U_PWM_ENA_OFFSET) +#define SAM3U_PWM_DIS (SAM3U_PWM_BASE+SAM3U_PWM_DIS_OFFSET) +#define SAM3U_PWM_SR (SAM3U_PWM_BASE+SAM3U_PWM_SR_OFFSET) +#define SAM3U_PWM_IER1 (SAM3U_PWM_BASE+SAM3U_PWM_IER1_OFFSET) +#define SAM3U_PWM_IDR1 (SAM3U_PWM_BASE+SAM3U_PWM_IDR1_OFFSET) +#define SAM3U_PWM_IMR1 (SAM3U_PWM_BASE+SAM3U_PWM_IMR1_OFFSET) +#define SAM3U_PWM_ISR1 (SAM3U_PWM_BASE+SAM3U_PWM_ISR1_OFFSET) +#define SAM3U_PWM_SCM (SAM3U_PWM_BASE+SAM3U_PWM_SCM_OFFSET) +#define SAM3U_PWM_SCUC (SAM3U_PWM_BASE+SAM3U_PWM_SCUC_OFFSET) +#define SAM3U_PWM_SCUP (SAM3U_PWM_BASE+SAM3U_PWM_SCUP_OFFSET) +#define SAM3U_PWM_SCUPUPD (SAM3U_PWM_BASE+SAM3U_PWM_SCUPUPD_OFFSET) +#define SAM3U_PWM_IER2 (SAM3U_PWM_BASE+SAM3U_PWM_IER2_OFFSET) +#define SAM3U_PWM_IDR2 (SAM3U_PWM_BASE+SAM3U_PWM_IDR2_OFFSET) +#define SAM3U_PWM_IMR2 (SAM3U_PWM_BASE+SAM3U_PWM_IMR2_OFFSET) +#define SAM3U_PWM_ISR2 (SAM3U_PWM_BASE+SAM3U_PWM_ISR2_OFFSET) +#define SAM3U_PWM_OOV (SAM3U_PWM_BASE+SAM3U_PWM_OOV_OFFSET) +#define SAM3U_PWM_OS (SAM3U_PWM_BASE+SAM3U_PWM_OS_OFFSET) +#define SAM3U_PWM_OSS (SAM3U_PWM_BASE+SAM3U_PWM_OSS_OFFSET) +#define SAM3U_PWM_OSC (SAM3U_PWM_BASE+SAM3U_PWM_OSC_OFFSET) +#define SAM3U_PWM_OSSUPD (SAM3U_PWM_BASE+SAM3U_PWM_OSSUPD_OFFSET) +#define SAM3U_PWM_OSCUPD (SAM3U_PWM_BASE+SAM3U_PWM_OSCUPD_OFFSET) +#define SAM3U_PWM_FMR (SAM3U_PWM_BASE+SAM3U_PWM_FMR_OFFSET) +#define SAM3U_PWM_FSR (SAM3U_PWM_BASE+SAM3U_PWM_FSR_OFFSET) +#define SAM3U_PWM_FCR (SAM3U_PWM_BASE+SAM3U_PWM_FCR_OFFSET) +#define SAM3U_PWM_FPV (SAM3U_PWM_BASE+SAM3U_PWM_FPV_OFFSET) +#define SAM3U_PWM_FPE (SAM3U_PWM_BASE+SAM3U_PWM_FPE_OFFSET) +#define SAM3U_PWM_EL0MR (SAM3U_PWM_BASE+SAM3U_PWM_EL0MR_OFFSET) +#define SAM3U_PWM_EL1MR (SAM3U_PWM_BASE+SAM3U_PWM_EL1MR_OFFSET) +#define SAM3U_PWM_WPCR (SAM3U_PWM_BASE+SAM3U_PWM_WPCR_OFFSET) +#define SAM3U_PWM_WPSR (SAM3U_PWM_BASE+SAM3U_PWM_WPSR_OFFSET) + +/* PWM Comparison Registers */ + +#define SAM3U_PWCMP_BASE(n) (SAM3U_PWM_BASE+SAM3U_PWCMP_OFFSET(n)) +#define SAM3U_PWMCMP0_BASE (SAM3U_PWM_BASE+0x0130) +#define SAM3U_PWMCMP1_BASE (SAM3U_PWM_BASE+0x0140) +#define SAM3U_PWMCMP2_BASE (SAM3U_PWM_BASE+0x0150) +#define SAM3U_PWMCMP3_BASE (SAM3U_PWM_BASE+0x0160) +#define SAM3U_PWMCMP4_BASE (SAM3U_PWM_BASE+0x0170) +#define SAM3U_PWMCMP5_BASE (SAM3U_PWM_BASE+0x0180) +#define SAM3U_PWMCMP6_BASE (SAM3U_PWM_BASE+0x0190) +#define SAM3U_PWMCMP7_BASE (SAM3U_PWM_BASE+0x01a0) + +#define SAM3U_PWMCMP0_V (SAM3U_PWMCMP0_BASE+SAM3U_PWMCMP_V_OFFSET) +#define SAM3U_PWMCMP0_VUPD (SAM3U_PWMCMP0_BASE+SAM3U_PWMCMP_VUPD_OFFSET) +#define SAM3U_PWMCMP0_M (SAM3U_PWMCMP0_BASE+SAM3U_PWMCMP_M_OFFSET) +#define SAM3U_PWMCMP0_MUPD (SAM3U_PWMCMP0_BASE+SAM3U_PWMCMP_MUPD_OFFSET) + +#define SAM3U_PWMCMP1_V (SAM3U_PWMCMP1_BASE+SAM3U_PWMCMP_V_OFFSET) +#define SAM3U_PWMCMP1_VUPD (SAM3U_PWMCMP1_BASE+SAM3U_PWMCMP_VUPD_OFFSET) +#define SAM3U_PWMCMP1_M (SAM3U_PWMCMP1_BASE+SAM3U_PWMCMP_M_OFFSET) +#define SAM3U_PWMCMP1_MUPD (SAM3U_PWMCMP1_BASE+SAM3U_PWMCMP_MUPD_OFFSET) + +#define SAM3U_PWMCMP2_V (SAM3U_PWMCMP2_BASE+SAM3U_PWMCMP_V_OFFSET) +#define SAM3U_PWMCMP2_VUPD (SAM3U_PWMCMP2_BASE+SAM3U_PWMCMP_VUPD_OFFSET) +#define SAM3U_PWMCMP2_M (SAM3U_PWMCMP2_BASE+SAM3U_PWMCMP_M_OFFSET) +#define SAM3U_PWMCMP2_MUPD (SAM3U_PWMCMP2_BASE+SAM3U_PWMCMP_MUPD_OFFSET) + +#define SAM3U_PWMCMP3_V (SAM3U_PWMCMP3_BASE+SAM3U_PWMCMP_V_OFFSET) +#define SAM3U_PWMCMP3_VUPD (SAM3U_PWMCMP3_BASE+SAM3U_PWMCMP_VUPD_OFFSET) +#define SAM3U_PWMCMP3_M (SAM3U_PWMCMP3_BASE+SAM3U_PWMCMP_M_OFFSET) +#define SAM3U_PWMCMP3_MUPD (SAM3U_PWMCMP3_BASE+SAM3U_PWMCMP_MUPD_OFFSET) + +#define SAM3U_PWMCMP4_V (SAM3U_PWMCMP4_BASE+SAM3U_PWMCMP_V_OFFSET) +#define SAM3U_PWMCMP4_VUPD (SAM3U_PWMCMP4_BASE+SAM3U_PWMCMP_VUPD_OFFSET) +#define SAM3U_PWMCMP4_M (SAM3U_PWMCMP4_BASE+SAM3U_PWMCMP_M_OFFSET) +#define SAM3U_PWMCMP4_MUPD (SAM3U_PWMCMP4_BASE+SAM3U_PWMCMP_MUPD_OFFSET) + +#define SAM3U_PWMCMP5_V (SAM3U_PWMCMP5_BASE+SAM3U_PWMCMP_V_OFFSET) +#define SAM3U_PWMCMP5_VUPD (SAM3U_PWMCMP5_BASE+SAM3U_PWMCMP_VUPD_OFFSET) +#define SAM3U_PWMCMP5_M (SAM3U_PWMCMP5_BASE+SAM3U_PWMCMP_M_OFFSET) +#define SAM3U_PWMCMP5_MUPD (SAM3U_PWMCMP5_BASE+SAM3U_PWMCMP_MUPD_OFFSET) + +#define SAM3U_PWMCMP6_V (SAM3U_PWMCMP6_BASE+SAM3U_PWMCMP_V_OFFSET) +#define SAM3U_PWMCMP6_VUPD (SAM3U_PWMCMP6_BASE+SAM3U_PWMCMP_VUPD_OFFSET) +#define SAM3U_PWMCMP6_M (SAM3U_PWMCMP6_BASE+SAM3U_PWMCMP_M_OFFSET) +#define SAM3U_PWMCMP6_MUPD (SAM3U_PWMCMP6_BASE+SAM3U_PWMCMP_MUPD_OFFSET) + +#define SAM3U_PWMCMP7_V (SAM3U_PWMCMP7_BASE+SAM3U_PWMCMP_V_OFFSET) +#define SAM3U_PWMCMP7_VUPD (SAM3U_PWMCMP7_BASE+SAM3U_PWMCMP_VUPD_OFFSET) +#define SAM3U_PWMCMP7_M (SAM3U_PWMCMP7_BASE+SAM3U_PWMCMP_M_OFFSET) +#define SAM3U_PWMCMP7_MUPD (SAM3U_PWMCMP7_BASE+SAM3U_PWMCMP_MUPD_OFFSET) + +/* PWM Channel Registers */ + +#define SAM3U_PWCH_BASE(n) (SAM3U_PWM_BASE+SAM3U_PWCH_OFFSET(n)) +#define SAM3U_PWMCH0_BASE (SAM3U_PWM_BASE+0x0200) +#define SAM3U_PWMCH1_BASE (SAM3U_PWM_BASE+0x0220) +#define SAM3U_PWMCH2_BASE (SAM3U_PWM_BASE+0x0240) +#define SAM3U_PWMCH3_BASE (SAM3U_PWM_BASE+0x0260) + +#define SAM3U_PWMCH0_MR (SAM3U_PWMCH0_BASE+SAM3U_PWMCH_MR_OFFSET) +#define SAM3U_PWMCH0_DTY (SAM3U_PWMCH0_BASE+SAM3U_PWMCH_DTY_OFFSET) +#define SAM3U_PWMCH0_DTYUPD (SAM3U_PWMCH0_BASE+SAM3U_PWMCH_DTYUPD_OFFSET) +#define SAM3U_PWMCH0_PRD (SAM3U_PWMCH0_BASE+SAM3U_PWMCH_PRD_OFFSET) +#define SAM3U_PWMCH0_PRDUPD (SAM3U_PWMCH0_BASE+SAM3U_PWMCH_PRDUPD_OFFSET) +#define SAM3U_PWMCH0_CCNT (SAM3U_PWMCH0_BASE+SAM3U_PWMCH_CCNT_OFFSET) +#define SAM3U_PWMCH0_DT (SAM3U_PWMCH0_BASE+SAM3U_PWMCH_DT_OFFSET) +#define SAM3U_PWMCH0_DTUPD (SAM3U_PWMCH0_BASE+SAM3U_PWMCH_DTUPD_OFFSET) + +#define SAM3U_PWMCH1_MR (SAM3U_PWMCH1_BASE+SAM3U_PWMCH_MR_OFFSET) +#define SAM3U_PWMCH1_DTY (SAM3U_PWMCH1_BASE+SAM3U_PWMCH_DTY_OFFSET) +#define SAM3U_PWMCH1_DTYUPD (SAM3U_PWMCH1_BASE+SAM3U_PWMCH_DTYUPD_OFFSET) +#define SAM3U_PWMCH1_PRD (SAM3U_PWMCH1_BASE+SAM3U_PWMCH_PRD_OFFSET) +#define SAM3U_PWMCH1_PRDUPD (SAM3U_PWMCH1_BASE+SAM3U_PWMCH_PRDUPD_OFFSET) +#define SAM3U_PWMCH1_CCNT (SAM3U_PWMCH1_BASE+SAM3U_PWMCH_CCNT_OFFSET) +#define SAM3U_PWMCH1_DT (SAM3U_PWMCH1_BASE+SAM3U_PWMCH_DT_OFFSET) +#define SAM3U_PWMCH1_DTUPD (SAM3U_PWMCH1_BASE+SAM3U_PWMCH_DTUPD_OFFSET) + +#define SAM3U_PWMCH2_MR (SAM3U_PWMCH2_BASE+SAM3U_PWMCH_MR_OFFSET) +#define SAM3U_PWMCH2_DTY (SAM3U_PWMCH2_BASE+SAM3U_PWMCH_DTY_OFFSET) +#define SAM3U_PWMCH2_DTYUPD (SAM3U_PWMCH2_BASE+SAM3U_PWMCH_DTYUPD_OFFSET) +#define SAM3U_PWMCH2_PRD (SAM3U_PWMCH2_BASE+SAM3U_PWMCH_PRD_OFFSET) +#define SAM3U_PWMCH2_PRDUPD (SAM3U_PWMCH2_BASE+SAM3U_PWMCH_PRDUPD_OFFSET) +#define SAM3U_PWMCH2_CCNT (SAM3U_PWMCH2_BASE+SAM3U_PWMCH_CCNT_OFFSET) +#define SAM3U_PWMCH2_DT (SAM3U_PWMCH2_BASE+SAM3U_PWMCH_DT_OFFSET) +#define SAM3U_PWMCH2_DTUPD (SAM3U_PWMCH2_BASE+SAM3U_PWMCH_DTUPD_OFFSET) + +#define SAM3U_PWMCH3_MR (SAM3U_PWMCH3_BASE+SAM3U_PWMCH_MR_OFFSET) +#define SAM3U_PWMCH3_DTY (SAM3U_PWMCH3_BASE+SAM3U_PWMCH_DTY_OFFSET) +#define SAM3U_PWMCH3_DTYUPD (SAM3U_PWMCH3_BASE+SAM3U_PWMCH_DTYUPD_OFFSET) +#define SAM3U_PWMCH3_PRD (SAM3U_PWMCH3_BASE+SAM3U_PWMCH_PRD_OFFSET) +#define SAM3U_PWMCH3_PRDUPD (SAM3U_PWMCH3_BASE+SAM3U_PWMCH_PRDUPD_OFFSET) +#define SAM3U_PWMCH3_CCNT (SAM3U_PWMCH3_BASE+SAM3U_PWMCH_CCNT_OFFSET) +#define SAM3U_PWMCH3_DT (SAM3U_PWMCH3_BASE+SAM3U_PWMCH_DT_OFFSET) +#define SAM3U_PWMCH3_DTUPD (SAM3U_PWMCH3_BASE+SAM3U_PWMCH_DTUPD_OFFSET) + +/* PWM register bit definitions *********************************************************/ + +/* PWM Clock Register */ + +#define PWM_CLK_DIVA_SHIFT (0) /* Bits 0-7: CLKA Divide Factor */ +#define PWM_CLK_DIVA_MASK (0xff << PWM_CLK_DIVA_SHIFT) +#define PWM_CLK_PREA_SHIFT (8) /* Bits 8-11: CLKA Source Clock Selection */ +#define PWM_CLK_PREA_MASK (15 << PWM_CLK_PREA_SHIFT) +# define PWM_CLK_PREA_MCK (0 << PWM_CLK_PREA_SHIFT) /* MCK */ +# define PWM_CLK_PREA_MCKDIV2 (1 << PWM_CLK_PREA_SHIFT) /* MCK/2 */ +# define PWM_CLK_PREA_MCKDIV4 (2 << PWM_CLK_PREA_SHIFT) /* MCK/4 */ +# define PWM_CLK_PREA_MCKDIV8 (3 << PWM_CLK_PREA_SHIFT) /* MCK/8 */ +# define PWM_CLK_PREA_MCKDIV16 (4 << PWM_CLK_PREA_SHIFT) /* MCK/16 */ +# define PWM_CLK_PREA_MCKDIV32 (5 << PWM_CLK_PREA_SHIFT) /* MCK/32 */ +# define PWM_CLK_PREA_MCKDIV64 (6 << PWM_CLK_PREA_SHIFT) /* MCK/64 */ +# define PWM_CLK_PREA_MCKDIV128 (7 << PWM_CLK_PREA_SHIFT) /* MCK/128 */ +# define PWM_CLK_PREA_MCKDIV256 (8 << PWM_CLK_PREA_SHIFT) /* MCK/256 */ +# define PWM_CLK_PREA_MCKDIV512 (9 << PWM_CLK_PREA_SHIFT) /* MCK/512 */ +# define PWM_CLK_PREA_MCKDIV1024 (10 << PWM_CLK_PREA_SHIFT) /* MCK/1024 */ +#define PWM_CLK_DIVB_SHIFT (16) /* Bits 16-23: CLKB Divide Factor */ +#define PWM_CLK_DIVB_MASK (0xff << PWM_CLK_DIVB_SHIFT) +#define PWM_CLK_PREB_SHIFT (24) /* Bit 24-27: CLKB Source Clock Selection */ +#define PWM_CLK_PREB_MASK (15 << PWM_CLK_PREB_SHIFT) +# define PWM_CLK_PREB_MCK (0 << PWM_CLK_PREB_SHIFT) /* MCK */ +# define PWM_CLK_PREB_MCKDIV2 (1 << PWM_CLK_PREB_SHIFT) /* MCK/2 */ +# define PWM_CLK_PREB_MCKDIV4 (2 << PWM_CLK_PREB_SHIFT) /* MCK/4 */ +# define PWM_CLK_PREB_MCKDIV8 (3 << PWM_CLK_PREB_SHIFT) /* MCK/8 */ +# define PWM_CLK_PREB_MCKDIV16 (4 << PWM_CLK_PREB_SHIFT) /* MCK/16 */ +# define PWM_CLK_PREB_MCKDIV32 (5 << PWM_CLK_PREB_SHIFT) /* MCK/32 */ +# define PWM_CLK_PREB_MCKDIV64 (6 << PWM_CLK_PREB_SHIFT) /* MCK/64 */ +# define PWM_CLK_PREB_MCKDIV128 (7 << PWM_CLK_PREB_SHIFT) /* MCK/128 */ +# define PWM_CLK_PREB_MCKDIV256 (8 << PWM_CLK_PREB_SHIFT) /* MCK/256 */ +# define PWM_CLK_PREB_MCKDIV512 (9 << PWM_CLK_PREB_SHIFT) /* MCK/512 */ +# define PWM_CLK_PREB_MCKDIV1024 (10 << PWM_CLK_PREB_SHIFT) /* MCK/1024 */ + +/* PWM Enable Register, PWM Disable Register, and PWM Status Register common bit-field definitions */ + +#define SAM3U_ENAB_CHID(n) (1 << ((n)) +#define SAM3U_ENAB_CHID0 (1 << 0) /* Bit 0: Counter Event Channel 0 Interrupt */ +#define SAM3U_ENAB_CHID1 (1 << 1) /* Bit 1: Counter Event Channel 1 Interrupt */ +#define SAM3U_ENAB_CHID2 (1 << 2) /* Bit 2: Counter Event Channel 2 Interrupt */ +#define SAM3U_ENAB_CHID3 (1 << 3) /* Bit 3: Counter Event Channel 3 Interrupt */ + +/* PWM Interrupt Enable Register 1, PWM Interrupt Disable Register 1, PWM Interrupt + * Mask Register 1, and PWM Interrupt Status Register 1 common bit definitions + */ + +#define SAM3U_INT_CHID(n) (1 << (n)) +#define SAM3U_INT_CHID0 (1 << 0) /* Bit 0: Counter Event Channel 0 Interrupt */ +#define SAM3U_INT_CHID1 (1 << 1) /* Bit 1: Counter Event Channel 1 Interrupt */ +#define SAM3U_INT_CHID2 (1 << 2) /* Bit 2: Counter Event Channel 2 Interrupt */ +#define SAM3U_INT_CHID3 (1 << 3) /* Bit 3: Counter Event Channel 3 Interrupt */ +#define SAM3U_INT_FCHID(n) (1 << ((n)+16)) +#define SAM3U_INT_FCHID0 (1 << 16) /* Bit 16: Fault Protection Trigger Channel 0 Interrupt */ +#define SAM3U_INT_FCHID1 (1 << 17) /* Bit 17: Fault Protection Trigger Channel 1 Interrupt */ +#define SAM3U_INT_FCHID2 (1 << 18) /* Bit 18: Fault Protection Trigger Channel 2 Interrupt */ +#define SAM3U_INT_FCHID3 (1 << 19) /* Bit 19: Fault Protection Trigger Channel 3 Interrupt */ + +/* PWM Sync Channels Mode Register */ + +#define PWM_SCM_SYNC(n) (1 << (n)) +#define PWM_SCM_SYNC0 (1 << 0) /* Bit 0: Synchronous Channel 0 */ +#define PWM_SCM_SYNC1 (1 << 1) /* Bit 1: Synchronous Channel 1 */ +#define PWM_SCM_SYNC2 (1 << 2) /* Bit 2: Synchronous Channel 2 */ +#define PWM_SCM_SYNC3 (1 << 3) /* Bit 3: Synchronous Channel 3 */ +#define PWM_SCM_UPDM_SHIFT (16) /* Bits 16-17: Synchronous Channels Update Mode */ +#define PWM_SCM_UPDM_MASK (3 << PWM_SCM_UPDM_SHIFT) +# define PWM_SCM_UPDM_MANMAN (0 << PWM_SCM_UPDM_SHIFT) /* Manual write/manual update */ +# define PWM_SCM_UPDM_MANAUTO (1 << PWM_SCM_UPDM_SHIFT) /* Manual write/automatic update */ +# define PWM_SCM_UPDM_AUTOAUTO (2 << PWM_SCM_UPDM_SHIFT) /* Auto write/automatic update */ +#define PWM_SCM_PTRM (1 << 20) /* Bit 20: PDC Transfer Request Mode */ +#define PWM_SCM_PTRCS_SHIFT (21) /* Bits 21-23: PDC Transfer Request Comparison Selection */ +#define PWM_SCM_PTRCS_MASK (7 << PWM_SCM_PTRCS_SHIFT) + +/* PWM Sync Channels Update Control Register */ + +#define PWM_SCUC_UPDULOCK (1 << 0) /* Bit 0: Synchronous Channels Update Unlock */ + +/* PWM Sync Channels Update Period Register */ + +#define PWM_SCUP_UPR_SHIFT (0) /* Bits 0-3: Update Period */ +#define PWM_SCUP_UPR_MASK (15 << PWM_SCUP_UPR_MASK) +#define PWM_SCUP_UPRCNT_SHIFT (4) /* Bits 4-7: Update Period Counter */ +#define PWM_SCUP_UPRCNT_MASK (15 << PWM_SCUP_UPRCNT_SHIFT) + +/* PWM Sync Channels Update Period Update Register */ + +#define PWM_SCUPUPD_SHIFT (0) /* Bits 0-3: Update Period Update */ +#define PWM_SCUPUPD_MASK (15 << PWM_SCUPUPD_SHIFT) + +/* PWM Interrupt Enable Register 2, PWM Interrupt Disable Register 2, PWM Interrupt Mask Register 2, and PWM Interrupt Status Register 2 common bit-field definitions */ + +#define SAM3U_INT_WRDY (1 << 0) /* Bit 0: Write Ready Update Interrupt */ +#define SAM3U_INT_ENDTX (1 << 1) /* Bit 1: PDC End of TX Buffer Interrupt */ +#define SAM3U_INT_TXBUFE (1 << 2) /* Bit 2: PDC TX Buffer Empty Interrupt */ +#define SAM3U_INT_UNRE (1 << 3) /* Bit 3: Synch Update Underrun Error Interrupt */ +#define SAM3U_INT_CMPM(n) (1 << ((n)+8)) +#define SAM3U_INT_CMPM0 (1 << 8) /* Bit 8: Comparison 0 Match Interrupt */ +#define SAM3U_INT_CMPM1 (1 << 9) /* Bit 9: Comparison 1 Match Interrupt */ +#define SAM3U_INT_CMPM2 (1 << 10) /* Bit 10: Comparison 2 Match Interrupt */ +#define SAM3U_INT_CMPM3 (1 << 11) /* Bit 11: Comparison 3 Match Interrupt */ +#define SAM3U_INT_CMPM4 (1 << 12) /* Bit 12: Comparison 4 Match Interrupt */ +#define SAM3U_INT_CMPM5 (1 << 13) /* Bit 13: Comparison 5 Match Interrupt */ +#define SAM3U_INT_CMPM6 (1 << 14) /* Bit 14: Comparison 6 Match Interrupt */ +#define SAM3U_INT_CMPM7 (1 << 15) /* Bit 15: Comparison 7 Match Interrupt */ +#define SAM3U_INT_CMPU(n) (1 << ((n)+16)) +#define SAM3U_INT_CMPU0 (1 << 16) /* Bit 16: Comparison o Update Interrupt */ +#define SAM3U_INT_CMPU1 (1 << 17) /* Bit 17: Comparison 1 Update Interrupt */ +#define SAM3U_INT_CMPU2 (1 << 18) /* Bit 18: Comparison 2 Update Interrupt */ +#define SAM3U_INT_CMPU3 (1 << 19) /* Bit 19: Comparison 3 Update Interrupt */ +#define SAM3U_INT_CMPU4 (1 << 20) /* Bit 20: Comparison 4 Update Interrupt */ +#define SAM3U_INT_CMPU5 (1 << 21) /* Bit 21: Comparison 5 Update Interrupt */ +#define SAM3U_INT_CMPU6 (1 << 22) /* Bit 22: Comparison 6 Update Interrupt */ +#define SAM3U_INT_CMPU7 (1 << 23) /* Bit 23: Comparison 7 Update Interrupt */ + +/* PWM Output Override Value Register, PWM Output Selection Register, PWM Output + * Selection Set Register, PWM Output Selection Clear Register, PWM Output Selection + * Set Update Register, and PWM Output Selection Clear Update Register common bit-field + * definitions + */ + +#define PWM_OUT_OH(n) (1 << (n)) +#define PWM_OUT_OH0 (1 << 0) /* Bit 0: Value for PWMH output of the channel 0 */ +#define PWM_OUT_OH1 (1 << 1) /* Bit 1: Value for PWMH output of the channel 1 */ +#define PWM_OUT_OH2 (1 << 2) /* Bit 2: Value for PWMH output of the channel 2 */ +#define PWM_OUT_OH3 (1 << 3) /* Bit 3: Value for PWMH output of the channel 3 */ +#define PWM_OUT_OL(n) (1 << ((n)+16)) +#define PWM_OUT_OL0 (1 << 16) /* Bit 16: Value for PWML output of the channel 0 */ +#define PWM_OUT_OL1 (1 << 17) /* Bit 17: Value for PWML output of the channel 1 */ +#define PWM_OUT_OL2 (1 << 18) /* Bit 18: Value for PWML output of the channel 2 */ +#define PWM_OUT_OL3 (1 << 19) /* Bit 19: Value for PWML output of the channel 3 */ + +/* PWM Fault Mode Register */ + +#define PWM_FMR_FPOL(n) (1 << (n)) +#define PWM_FMR_FPOL0 (1 << 0) /* Bit 0: Fault 0 Polarity */ +#define PWM_FMR_FPOL1 (1 << 1) /* Bit 1: Fault 1 Polarity */ +#define PWM_FMR_FPOL2 (1 << 2) /* Bit 2: Fault 2 Polarity */ +#define PWM_FMR_FPOL3 (1 << 3) /* Bit 3: Fault 3 Polarity */ +#define PWM_FMR_FMOD(n) (1 << ((n)+8)) +#define PWM_FMR_FMOD0 (1 << 8) /* Bit 8: Fault 0 Activation Mode */ +#define PWM_FMR_FMOD1 (1 << 9) /* Bit 9: Fault 1 Activation Mode */ +#define PWM_FMR_FMOD2 (1 << 10) /* Bit 10: Fault 2 Activation Mode */ +#define PWM_FMR_FMOD3 (1 << 11) /* Bit 11: Fault 3 Activation Mode */ +#define PWM_FMR_FFIL(n) (1 << ((n)+16)) +#define PWM_FMR_FFIL0 (1 << 16) /* Bit 16: Fault 0 Filter */ +#define PWM_FMR_FFIL1 (1 << 17) /* Bit 17: Fault 1 Filter */ +#define PWM_FMR_FFIL2 (1 << 18) /* Bit 18: Fault 2 Filter */ +#define PWM_FMR_FFIL3 (1 << 19) /* Bit 19: Fault 3 Filter */ + +/* PWM Fault Status Register */ + +#define PWM_FSR_FIV(n) (1 << (n)) +#define PWM_FSR_FIV0 (1 << 0) /* Bit 0: Fault Input 0 Value */ +#define PWM_FSR_FIV1 (1 << 1) /* Bit 1: Fault Input 1 Value */ +#define PWM_FSR_FIV2 (1 << 2) /* Bit 2: Fault Input 2 Value */ +#define PWM_FSR_FIV3 (1 << 3) /* Bit 3: Fault Input 3 Value */ +#define PWM_FSR_FS(n) (1 << ((n)+8)) +#define PWM_FSR_FS0 (1 << 8) /* Bit 8: Fault 0 Status */ +#define PWM_FSR_FS1 (1 << 9) /* Bit 9: Fault 1 Status */ +#define PWM_FSR_FS2 (1 << 10) /* Bit 10: Fault 2 Status */ +#define PWM_FSR_FS3 (1 << 11) /* Bit 11: Fault 3 Status */ + +/* PWM Fault Clear Register */ + +#define PWM_FCR_FCLR(n) (1 << (n)) +#define PWM_FCR_FCLR0 (1 << 0) /* Bit 0: Fault 0 Clear */ +#define PWM_FCR_FCLR1 (1 << 1) /* Bit 1: Fault 1 Clear */ +#define PWM_FCR_FCLR2 (1 << 2) /* Bit 2: Fault 2 Clear */ +#define PWM_FCR_FCLR3 (1 << 3) /* Bit 3: Fault 3 Clear */ + +/* PWM Fault Protection Value Register */ + +#define PWM_FPV_FPVH(n) (1 << (n)) +#define PWM_FPV_FPVH0 (1 << 0) /* Bit 0: Fault Protection Value PWMH output channel 0 */ +#define PWM_FPV_FPVH1 (1 << 1) /* Bit 1: Fault Protection Value PWMH output channel 1 */ +#define PWM_FPV_FPVH2 (1 << 2) /* Bit 2: Fault Protection Value PWMH output channel 2 */ +#define PWM_FPV_FPVH3 (1 << 3) /* Bit 3: Fault Protection Value PWMH output channel 3 */ +#define PWM_FPV_FPVL(n) (1 << ((n)+16)) +#define PWM_FPV_FPVL0 (1 << 16) /* Bit 16: Fault Protection Value PWML output channel 0 */ +#define PWM_FPV_FPVL1 (1 << 17) /* Bit 17: Fault Protection Value PWML output channel 1 */ +#define PWM_FPV_FPVL2 (1 << 18) /* Bit 18: Fault Protection Value PWML output channel 2 */ +#define PWM_FPV_FPVL3 (1 << 19) /* Bit 19: Fault Protection Value PWML output channel 3 */ + +/* PWM Fault Protection Enable Register */ + +#define PWM_FPE_FPEN(n,y) (1 << (((n)<<8)+y)) +#define PWM_FPE_FPE0(y) (1 << (y)) /* Bits 0-7: Fault Protection Enable Fault=y chan=0 */ +#define PWM_FPE_FPE1(y) (1 << ((y)+8)) /* Bits 8-15: Fault Protection Enable Fault=y chan=1 */ +#define PWM_FPE_FPE2(y) (1 << ((y)+16)) /* Bits 16-23: Fault Protection Enable Fault=y chan=2 */ +#define PWM_FPE_FPE3(y) (1 << ((y)+24) /* Bits 24-31: Fault Protection Enable Fault=y chan=3 */ + +/* PWM Event Line 1/2 Register */ + +#define PWM_ELMR_CSEL(n) (1 << (n)) +#define PWM_ELMR_CSEL0 (1 << 0) /* Bit 0: Comparison 0 Selection */ +#define PWM_ELMR_CSEL1 (1 << 1) /* Bit 1: Comparison 1 Selection */ +#define PWM_ELMR_CSEL2 (1 << 2) /* Bit 2: Comparison 2 Selection */ +#define PWM_ELMR_CSEL3 (1 << 3) /* Bit 3: Comparison 3 Selection */ +#define PWM_ELMR_CSEL4 (1 << 4) /* Bit 4: Comparison 4 Selection */ +#define PWM_ELMR_CSEL5 (1 << 5) /* Bit 5: Comparison 5 Selection */ +#define PWM_ELMR_CSEL6 (1 << 6) /* Bit 6: Comparison 6 Selection */ +#define PWM_ELMR_CSEL7 (1 << 7) /* Bit 7: Comparison 7 Selection */ + +/* PWM Write Protect Control Register */ + +#define PWM_WPCR_WPCMD_SHIFT (0) /* Bits 0-1: Write Protect Command */ +#define PWM_WPCR_WPCMD_MASK (3 << PWM_WPCR_WPCMD_SHIFT) +#define PWM_WPCR_WPRG(n) (1 << ((n)+2)) +#define PWM_WPCR_WPRG0 (1 << 2) /* Bit 2: Write Protect Register Group 0 */ +#define PWM_WPCR_WPRG1 (1 << 3) /* Bit 3: Write Protect Register Group 1 */ +#define PWM_WPCR_WPRG2 (1 << 4) /* Bit 4: Write Protect Register Group 2 */ +#define PWM_WPCR_WPRG3 (1 << 5) /* Bit 5: Write Protect Register Group 3 */ +#define PWM_WPCR_WPRG4 (1 << 6) /* Bit 6: Write Protect Register Group 4 */ +#define PWM_WPCR_WPRG5 (1 << 7) /* Bit 7: Write Protect Register Group 5 */ +#define PWM_WPCR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protect Key */ +#define PWM_WPCR_WPKEY_MASK (0x00ffffff << PWM_WPCR_WPKEY_SHIFT) + +/* PWM Write Protect Status Register */ + +#define PWM_WPSR_WPSWS(n) (1 << (n)) +#define PWM_WPSR_WPSWS0 (1 << 0) /* Bit 0: Write Protect SW Status */ +#define PWM_WPSR_WPSWS1 (1 << 1) /* Bit 1: Write Protect SW Status */ +#define PWM_WPSR_WPSWS2 (1 << 2) /* Bit 2: Write Protect SW Status */ +#define PWM_WPSR_WPSWS3 (1 << 3) /* Bit 3: Write Protect SW Status */ +#define PWM_WPSR_WPSWS4 (1 << 4) /* Bit 4: Write Protect SW Status */ +#define PWM_WPSR_WPSWS5 (1 << 5) /* Bit 5: Write Protect SW Status */ +#define PWM_WPSR_WPVS (1 << 7) /* Bit 7: Write Protect Violation Status */ +#define PWM_WPSR_WPHWS(n) (1 << ((n)+8)) +#define PWM_WPSR_WPHWS0 (1 << 8) /* Bit 8: Write Protect HW Status */ +#define PWM_WPSR_WPHWS1 (1 << 9) /* Bit 9: Write Protect HW Status */ +#define PWM_WPSR_WPHWS2 (1 << 10) /* Bit 10: Write Protect HW Status */ +#define PWM_WPSR_WPHWS3 (1 << 11) /* Bit 11: Write Protect HW Status */ +#define PWM_WPSR_WPHWS4 (1 << 12) /* Bit 12: Write Protect HW Status */ +#define PWM_WPSR_WPHWS5 (1 << 13) /* Bit 13: Write Protect HW Status */ +#define PWM_WPSR_WPVSRC_SHIFT (16) /* Bits 16-31: Write Protect Violation Source */ +#define PWM_WPSR_WPVSRC_MASK (0xffff << PWM_WPSR_WPVSRC_SHIFT) + +/* PWM Comparison x Value Register and PWM Comparison x Value Update Register */ + +#define PWMCMP_CV_SHIFT (0) /* Bits 0-23: Comparison x Value */ +#define PWMCMP_CV_MASK (0x00ffffff << PWMCMP_CV_SHIFT) +#define PWMCMP_CVM (1 << 24) /* Bit 24: Comparison x Value Mode */ + +/* PWM Comparison x Mode Register and PWM Comparison x Mode Update Register */ + +#define PWMCMP_CEN (1 << 0) /* Bit 0: Comparison x Enable */ +#define PWMCMP_CTR_SHIFT (4) /* Bits 4-7: Comparison x Trigger */ +#define PWMCMP_CTR_MASK (15 << PWMCMP_CTR_SHIFT) +#define PWMCMP_CPR_SHIFT (8) /* Bits 8-11: Comparison x Period */ +#define PWMCMP_CPR_MASK (15 << PWMCMP_CPR_SHIFT) +#define PWMCMP_M_CPRCNT_SHIFT (12) /* Bits 12-15: Comparison x Period Count (M only) */ +#define PWMCMP_M_CPRCNT_MASK (15 << PWMCMP_M_CPRCNT_SHIFT) +#define PWMCMP_CUPR_SHIFT (16) /* Bits 16-19: Comparison x Update Period */ +#define PWMCMP_CUPR_MASK (15 << PWMCMP_CUPR_SHIFT) +#define PWMCMP_M_CUPRCNT_SHIFT (20) /* Bits 20-23: Comparison x Update Period Counter (M only) */ +#define PWMCMP_M_CUPRCNT_MASK (15 << PWMCMP_M_CUPRCNT_SHIFT) + +/* PWM Channel Mode Register */ + +#define PWMCH_MR_CPRE_SHIFT (0) /* Bits 0-3: Channel Pre-scaler */ +#define PWMCH_MR_CPRE_MASK (15 << PWMCH_MR_CPRE_SHIFT) +# define PWMCH_MR_CPRE_MCK (0 << PWMCH_MR_CPRE_SHIFT) /* MCK */ +# define PWMCH_MR_CPRE_MCKDIV2 (1 << PWMCH_MR_CPRE_SHIFT) /* MCK/2 */ +# define PWMCH_MR_CPRE_MCKDIV4 (2 << PWMCH_MR_CPRE_SHIFT) /* MCK/4 */ +# define PWMCH_MR_CPRE_MCKDIV8 (3 << PWMCH_MR_CPRE_SHIFT) /* MCK/8 */ +# define PWMCH_MR_CPRE_MCKDIV16 (4 << PWMCH_MR_CPRE_SHIFT) /* MCK/16 */ +# define PWMCH_MR_CPRE_MCKDIV32 (5 << PWMCH_MR_CPRE_SHIFT) /* MCK/32 */ +# define PWMCH_MR_CPRE_MCKDIV64 (6 << PWMCH_MR_CPRE_SHIFT) /* MCK/64 */ +# define PWMCH_MR_CPRE_MCKDIV128 (7 << PWMCH_MR_CPRE_SHIFT) /* MCK/128 */ +# define PWMCH_MR_CPRE_MCKDIV256 (8 << PWMCH_MR_CPRE_SHIFT) /* MCK/256 */ +# define PWMCH_MR_CPRE_MCKDIV512 (9 << PWMCH_MR_CPRE_SHIFT) /* MCK/512 */ +# define PWMCH_MR_CPRE_MCKDIV1024 (10 << PWMCH_MR_CPRE_SHIFT) /* MCK/1024 */ +# define PWMCH_MR_CPRE_CLKA (11 << PWMCH_MR_CPRE_SHIFT) /*CLKA */ +# define PWMCH_MR_CPRE_CLKB (12 << PWMCH_MR_CPRE_SHIFT) /* CLKB */ +#define PWMCH_MR_CALG (1 << 8) /* Bit 8: Channel Alignment */ +#define PWMCH_MR_CPOL (1 << 9) /* Bit 9: Channel Polarity */ +#define PWMCH_MR_CES (1 << 10) /* Bit 10: Counter Event Selection */ +#define PWMCH_MR_DTE (1 << 16) /* Bit 16: Dead-Time Generator Enable */ +#define PWMCH_MR_DTHI (1 << 17) /* Bit 17: Dead-Time PWMHx Output Inverted */ +#define PWMCH_MR_DTLI (1 << 18) /* Bit 18: Dead-Time PWMLx Output Inverted */ + +/* PWM Channel Duty Cycle Register and PWM Channel Duty Cycle Update Register common bit-field definitions */ + +#define PWMCH_DTY_SHIFT (0) /* Bits 0-23: Channel Duty-Cycle */ +#define PWMCH_DTY_MASK (0x00ffffff << PWMCH_DTY_SHIFT) + +/* PWM Channel Period Register and PWM Channel Period Update Register common bit-field definitions */ + +#define PWMCH_PRD_SHIFT (0) /* Bits 0-23: Channel Period */ +#define PWMCH_PRD_MASK (0x00ffffff << PWMCH_PRD_SHIFT) + +/* PWM Channel Counter Register */ + +#define PWMCH_CCNT_SHIFT (0) /* Bits 0-23: Channel Counter Register */ +#define PWMCH_CCNT_MASK (0x00ffffff << PWMCH_CCNT_SHIFT) + +/* PWM Channel Dead Time Register and PWM Channel Dead Time Update Register common bit-field definitions */ + +#define PWMCH_DTH_SHIFT (0) /* Bits 0-15: Dead-Time Value for PWMHx Output */ +#define PWMCH_DTH_MASK (0xffff << PWMCH_DTH_SHIFT) +#define PWMCH_DTL_SHIFT (16) /* Bits 16-31: Dead-Time Value for PWMLx Output */ +#define PWMCH_DTL_MASK (0xffff << PWMCH_DTL_SHIFT) + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +/**************************************************************************************** + * Public Data + ****************************************************************************************/ + +/**************************************************************************************** + * Public Functions + ****************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_PWM_H */ diff --git a/nuttx/arch/arm/src/sam3u/sam3u_rstc.h b/nuttx/arch/arm/src/sam3u/sam3u_rstc.h index 4241eeba4..688631fb6 100644 --- a/nuttx/arch/arm/src/sam3u/sam3u_rstc.h +++ b/nuttx/arch/arm/src/sam3u/sam3u_rstc.h @@ -1,102 +1,102 @@ -/****************************************************************************************
- * arch/arm/src/sam3u/sam3u_rstc.h
- *
- * Copyright (C) 2009 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_RSTC_H
-#define __ARCH_ARM_SRC_SAM3U_SAM3U_RSTC_H
-
-/****************************************************************************************
- * Included Files
- ****************************************************************************************/
-
-#include <nuttx/config.h>
-
-#include "chip.h"
-#include "sam3u_memorymap.h"
-
-/****************************************************************************************
- * Pre-processor Definitions
- ****************************************************************************************/
-
-/* RSTC register offsets ****************************************************************/
-
-#define SAM3U_RSTC_CR_OFFSET 0x00 /* Control Register */
-#define SAM3U_RSTC_SR_OFFSET 0x04 /* Status Register */
-#define SAM3U_RSTC_MR_OFFSET 0x08 /* Mode Register */
-
-/* RSTC register adresses ***************************************************************/
-
-#define SAM3U_RSTC_CR (SAM3U_RSTC_BASE+SAM3U_RSTC_CR_OFFSET)
-#define SAM3U_RSTC_SR (SAM3U_RSTC_BASE+SAM3U_RSTC_SR_OFFSET)
-#define SAM3U_RSTC_MR (SAM3U_RSTC_BASE+SAM3U_RSTC_MR_OFFSET)
-
-/* RSTC register bit definitions ********************************************************/
-
-#define RSTC_CR_PROCRST (1 << 0) /* Bit 0: Processor Reset */
-#define RSTC_CR_PERRST (1 << 2) /* Bit 2: Peripheral Reset */
-#define RSTC_CR_EXTRST (1 << 3) /* Bit 3: External Reset */
-#define RSTC_CR_KEY_SHIFT (24) /* Bits 24-31: Password */
-#define RSTC_CR_KEY_MASK (0xff << RSTC_CR_KEY_SHIFT)
-
-#define RSTC_SR_URSTS (1 << 0) /* Bit 0: User Reset Status */
-#define RSTC_SR_RSTTYP_SHIFT (8) /* Bits 8-10: Reset Type */
-#define RSTC_SR_RSTTYP_MASK (7 << RSTC_SR_RSTTYP_SHIFT)
-# define RSTC_SR_RSTTYP_PWRUP (0 << RSTC_SR_RSTTYP_SHIFT) /* General Reset */
-# define RSTC_SR_RSTTYP_BACKUP (1 << RSTC_SR_RSTTYP_SHIFT) /* Backup Reset */
-# define RSTC_SR_RSTTYP_WDOG (2 << RSTC_SR_RSTTYP_SHIFT) /* Watchdog Reset */
-# define RSTC_SR_RSTTYP_SWRST (3 << RSTC_SR_RSTTYP_SHIFT) /* Software Reset */
-# define RSTC_SR_RSTTYP_NRST (4 << RSTC_SR_RSTTYP_SHIFT) /* User Reset NRST pin */
-#define RSTC_SR_NRSTL (1 << 16) /* Bit 16: NRST Pin Level */
-#define RSTC_SR_SRCMP (1 << 17) /* Bit 17: Software Reset Command in Progress */
-
-#define RSTC_MR_URSTEN (1 << 0) /* Bit 0: User Reset Enable */
-#define RSTC_MR_URSTIEN (1 << 4) /* Bit 4: User Reset Interrupt Enable */
-#define RSTC_MR_ERSTL_SHIFT (8) /* Bits 8-11: External Reset Length */
-#define RSTC_MR_ERSTL_MASK (15 << RSTC_MR_ERSTL_SHIFT)
-#define RSTC_MR_KEY_SHIFT (24) /* Bits 24-31: Password */
-#define RSTC_MR_KEY_MASK (0xff << RSTC_CR_KEY_SHIFT)
-
-/****************************************************************************************
- * Public Types
- ****************************************************************************************/
-
-/****************************************************************************************
- * Public Data
- ****************************************************************************************/
-
-/****************************************************************************************
- * Public Functions
- ****************************************************************************************/
-
-#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_RSTC_H */
+/**************************************************************************************** + * arch/arm/src/sam3u/sam3u_rstc.h + * + * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_RSTC_H +#define __ARCH_ARM_SRC_SAM3U_SAM3U_RSTC_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +#include <nuttx/config.h> + +#include "chip.h" +#include "sam3u_memorymap.h" + +/**************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************/ + +/* RSTC register offsets ****************************************************************/ + +#define SAM3U_RSTC_CR_OFFSET 0x00 /* Control Register */ +#define SAM3U_RSTC_SR_OFFSET 0x04 /* Status Register */ +#define SAM3U_RSTC_MR_OFFSET 0x08 /* Mode Register */ + +/* RSTC register adresses ***************************************************************/ + +#define SAM3U_RSTC_CR (SAM3U_RSTC_BASE+SAM3U_RSTC_CR_OFFSET) +#define SAM3U_RSTC_SR (SAM3U_RSTC_BASE+SAM3U_RSTC_SR_OFFSET) +#define SAM3U_RSTC_MR (SAM3U_RSTC_BASE+SAM3U_RSTC_MR_OFFSET) + +/* RSTC register bit definitions ********************************************************/ + +#define RSTC_CR_PROCRST (1 << 0) /* Bit 0: Processor Reset */ +#define RSTC_CR_PERRST (1 << 2) /* Bit 2: Peripheral Reset */ +#define RSTC_CR_EXTRST (1 << 3) /* Bit 3: External Reset */ +#define RSTC_CR_KEY_SHIFT (24) /* Bits 24-31: Password */ +#define RSTC_CR_KEY_MASK (0xff << RSTC_CR_KEY_SHIFT) + +#define RSTC_SR_URSTS (1 << 0) /* Bit 0: User Reset Status */ +#define RSTC_SR_RSTTYP_SHIFT (8) /* Bits 8-10: Reset Type */ +#define RSTC_SR_RSTTYP_MASK (7 << RSTC_SR_RSTTYP_SHIFT) +# define RSTC_SR_RSTTYP_PWRUP (0 << RSTC_SR_RSTTYP_SHIFT) /* General Reset */ +# define RSTC_SR_RSTTYP_BACKUP (1 << RSTC_SR_RSTTYP_SHIFT) /* Backup Reset */ +# define RSTC_SR_RSTTYP_WDOG (2 << RSTC_SR_RSTTYP_SHIFT) /* Watchdog Reset */ +# define RSTC_SR_RSTTYP_SWRST (3 << RSTC_SR_RSTTYP_SHIFT) /* Software Reset */ +# define RSTC_SR_RSTTYP_NRST (4 << RSTC_SR_RSTTYP_SHIFT) /* User Reset NRST pin */ +#define RSTC_SR_NRSTL (1 << 16) /* Bit 16: NRST Pin Level */ +#define RSTC_SR_SRCMP (1 << 17) /* Bit 17: Software Reset Command in Progress */ + +#define RSTC_MR_URSTEN (1 << 0) /* Bit 0: User Reset Enable */ +#define RSTC_MR_URSTIEN (1 << 4) /* Bit 4: User Reset Interrupt Enable */ +#define RSTC_MR_ERSTL_SHIFT (8) /* Bits 8-11: External Reset Length */ +#define RSTC_MR_ERSTL_MASK (15 << RSTC_MR_ERSTL_SHIFT) +#define RSTC_MR_KEY_SHIFT (24) /* Bits 24-31: Password */ +#define RSTC_MR_KEY_MASK (0xff << RSTC_CR_KEY_SHIFT) + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +/**************************************************************************************** + * Public Data + ****************************************************************************************/ + +/**************************************************************************************** + * Public Functions + ****************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_RSTC_H */ diff --git a/nuttx/arch/arm/src/sam3u/sam3u_rtc.h b/nuttx/arch/arm/src/sam3u/sam3u_rtc.h index 479afb045..61e6bb68e 100644 --- a/nuttx/arch/arm/src/sam3u/sam3u_rtc.h +++ b/nuttx/arch/arm/src/sam3u/sam3u_rtc.h @@ -1,184 +1,184 @@ -/****************************************************************************************
- * arch/arm/src/sam3u/sam3u_rtc.h
- *
- * Copyright (C) 2009 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_RTC_H
-#define __ARCH_ARM_SRC_SAM3U_SAM3U_RTC_H
-
-/****************************************************************************************
- * Included Files
- ****************************************************************************************/
-
-#include <nuttx/config.h>
-
-#include "chip.h"
-#include "sam3u_memorymap.h"
-
-/****************************************************************************************
- * Pre-processor Definitions
- ****************************************************************************************/
-
-/* RTC register offsets *****************************************************************/
-
-#define SAM3U_RTC_CR_OFFSET 0x00 /* Control Register */
-#define SAM3U_RTC_MR_OFFSET 0x04 /* Mode Register */
-#define SAM3U_RTC_TIMR_OFFSET 0x08 /* Time Register */
-#define SAM3U_RTC_CALR_OFFSET 0x0c /* Calendar Register */
-#define SAM3U_RTC_TIMALR_OFFSET 0x10 /* Time Alarm Register */
-#define SAM3U_RTC_CALALR_OFFSET 0x14 /* Calendar Alarm Register */
-#define SAM3U_RTC_SR_OFFSET 0x18 /* Status Register */
-#define SAM3U_RTC_SCCR_OFFSET 0x1c /* Status Clear Command Register */
-#define SAM3U_RTC_IER_OFFSET 0x20 /* Interrupt Enable Register */
-#define SAM3U_RTC_IDR_OFFSET 0x24 /* Interrupt Disable Register */
-#define SAM3U_RTC_IMR_OFFSET 0x28 /* Interrupt Mask Register */
-#define SAM3U_RTC_VER_OFFSET 0x2c /* Valid Entry Register */
-
-/* RTC register adresses ****************************************************************/
-
-#define SAM3U_RTC_CR (SAM3U_RTC_BASE+SAM3U_RTC_CR_OFFSET)
-#define SAM3U_RTC_MR (SAM3U_RTC_BASE+SAM3U_RTC_MR_OFFSET)
-#define SAM3U_RTC_TIMR (SAM3U_RTC_BASE+SAM3U_RTC_TIMR_OFFSET)
-#define SAM3U_RTC_CALR (SAM3U_RTC_BASE+SAM3U_RTC_CALR_OFFSET)
-#define SAM3U_RTC_TIMALR (SAM3U_RTC_BASE+SAM3U_RTC_TIMALR_OFFSET)
-#define SAM3U_RTC_CALALR (SAM3U_RTC_BASE+SAM3U_RTC_CALALR_OFFSET)
-#define SAM3U_RTC_SR (SAM3U_RTC_BASE+SAM3U_RTC_SR_OFFSET)
-#define SAM3U_RTC_SCCR (SAM3U_RTC_BASE+SAM3U_RTC_SCCR_OFFSET)
-#define SAM3U_RTC_IER (SAM3U_RTC_BASE+SAM3U_RTC_IER_OFFSET)
-#define SAM3U_RTC_IDR (SAM3U_RTC_BASE+SAM3U_RTC_IDR_OFFSET)
-#define SAM3U_RTC_IMR (SAM3U_RTC_BASE+SAM3U_RTC_IMR_OFFSET)
-#define SAM3U_RTC_VER (SAM3U_RTC_BASE+SAM3U_RTC_VER_OFFSET)
-
-/* RTC register bit definitions *********************************************************/
-
-#define RTC_CR_UPDTIM (1 << 0) /* Bit 0: Update Request Time Register */
-#define RTC_CR_UPDCAL (1 << 1) /* Bit 1: Update Request Calendar Register */
-#define RTC_CR_TIMEVSEL_SHIFT (8) /* Bits 8-9: Time Event Selection */
-#define RTC_CR_TIMEVSEL_MASK (3 << RTC_CR_TIMEVSEL_SHIFT)
-# define RTC_CR_TIMEVSEL_MIN (0 << RTC_CR_TIMEVSEL_SHIFT)
-# define RTC_CR_TIMEVSEL_HOUR (1 << RTC_CR_TIMEVSEL_SHIFT)
-# define RTC_CR_TIMEVSEL_MIDNIGHT (2 << RTC_CR_TIMEVSEL_SHIFT)
-# define RTC_CR_TIMEVSEL_NOON (3 << RTC_CR_TIMEVSEL_SHIFT)
-#define RTC_CR_CALEVSEL_SHIFT (16) /* Bits 16-17: Calendar Event Selection */
-#define RTC_CR_CALEVSEL_MASK (3 << RTC_CR_CALEVSEL_SHIFT)
-# define RTC_CR_CALEVSEL_WEEK (0 << RTC_CR_CALEVSEL_SHIFT)
-# define RTC_CR_CALEVSEL_MONTH (1 << RTC_CR_CALEVSEL_SHIFT)
-# define RTC_CR_CALEVSEL_YEAR (2 << RTC_CR_CALEVSEL_SHIFT)
-
-#define RTC_MR_HRMOD (1 << 0) /* Bit 0: 12-/24-hour Mode */
-
-#define RTC_TIMR_SEC_SHIFT (0) /* Bits 0-6: Current Second */
-#define RTC_TIMR_SEC_MASK (0x7f << RTC_TIMR_SEC_SHIFT)
-#define RTC_TIMR_MIN_SHIFT (8) /* Bits 8-14: Current Minute */
-#define RTC_TIMR_MIN_MASK (0x7f << RTC_TIMR_MIN_SHIFT)
-#define RTC_TIMR_HOUR_SHIFT (16) /* Bits 16-21: Current Hour */
-#define RTC_TIMR_HOUR_MASK (0x3f << RTC_TIMR_HOUR_SHIFT)
-#define RTC_TIMR_AMPM (1 << 22) /* Bit 22: Ante Meridiem Post Meridiem Indicator */
-
-#define RTC_CALR_CENT_SHIFT (0) /* Bits 0-6: Current Century */
-#define RTC_CALR_CENT_MASK (0x7f << RTC_TIMR_HOUR_SHIFT)
-#define RTC_CALR_YEAR_SHIFT (8) /* Bits 8-15: Current Year */
-#define RTC_CALR_YEAR_MASK (0xff << RTC_CALR_YEAR_SHIFT)
-#define RTC_CALR_MONTH_SHIFT (16) /* Bits 16-20: Current Month */
-#define RTC_CALR_MONTH_MASK (0x1f << RTC_CALR_MONTH_SHIFT)
-#define RTC_CALR_DAY_SHIFT (21) /* Bits 21-23: Current Day in Current Week */
-#define RTC_CALR_DAY_MASK (7 << RTC_CALR_DAY_SHIFT)
-#define RTC_CALR_DATE_SHIFT (24) /* Bits 24-29: Current Day in Current Month */
-#define RTC_CALR_DATE_MASK (0x3f << RTC_CALR_DATE_SHIFT)
-
-#define RTC_TIMALR_SEC_SHIFT (0) /* Bits 0-6: Second Alarm */
-#define RTC_TIMALR_SEC_MASK (0x7f << RTC_TIMALR_SEC_SHIFT)
-#define RTC_TIMALR_SECEN (1 << 7) /* Bit 7: Second Alarm Enable */
-#define RTC_TIMALR_MIN_SHIFT (8) /* Bits 8-14: Minute Alarm */
-#define RTC_TIMALR_MIN_MASK (0x7f << RTC_TIMALR_MIN_SHIFT)
-#define RTC_TIMALR_MINEN (1 << 15) /* Bit 15: Minute Alarm Enable */
-#define RTC_TIMALR_HOUR_SHIFT (16) /* Bits 16-21: Hour Alarm */
-#define RTC_TIMALR_HOUR_MASK (0x3f << RTC_TIMALR_HOUR_SHIFT)
-#define RTC_TIMALR_AMPM (1 << 22) /* Bit 22: AM/PM Indicator */
-#define RTC_TIMALR_HOUREN (1 << 23) /* Bit 23: Hour Alarm Enable */
-
-#define RTC_CALALR_MONTH_SHIFT (16) /* Bits 16-20: Month Alarm */
-#define RTC_CALALR_MONTH_MASK (0x1f << RTC_CALALR_MONTH_SHIFT)
-#define RTC_CALALR_MTHEN (1 << 23) /* Bit 23: Month Alarm Enable */
-#define RTC_CALALR_DATE_SHIFT (24) /* Bits 24-29: Date Alarm */
-#define RTC_CALALR_DATE_MASK (0x3c << RTC_CALALR_DATE_SHIFT)
-#define RTC_CALALR_DATEEN (1 << 31) /* Bit 31: Date Alarm Enable */
-
-#define RTC_SR_ACKUPD (1 << 0) /* Bit 0: Acknowledge for Update */
-#define RTC_SR_ALARM (1 << 1) /* Bit 1: Alarm Flag */
-#define RTC_SR_SEC (1 << 2) /* Bit 2: Second Event */
-#define RTC_SR_TIMEV (1 << 3) /* Bit 3: Time Event */
-#define RTC_SR_CALEV (1 << 4) /* Bit 4: Calendar Event */
-
-#define RTC_SCCR_ACKCLR (1 << 0) /* Bit 0: Acknowledge Clear */
-#define RTC_SCCR_ALRCLR (1 << 1) /* Bit 1: Alarm Clear */
-#define RTC_SCCR_SECCLR (1 << 2) /* Bit 2: Second Clear */
-#define RTC_SCCR_TIMCLR (1 << 3) /* Bit 3: Time Clear */
-#define RTC_SCCR_CALCLR (1 << 4) /* Bit 4: Calendar Clear */
-
-#define RTC_IER_ACKEN (1 << 0) /* Bit 0: Acknowledge Update Interrupt Enable */
-#define RTC_IER_ALREN (1 << 1) /* Bit 1: Alarm Interrupt Enable */
-#define RTC_IER_SECEN (1 << 2) /* Bit 2: Second Event Interrupt Enable */
-#define RTC_IER_TIMEN (1 << 3) /* Bit 3: Time Event Interrupt Enable */
-#define RTC_IER_CALEN (1 << 4) /* Bit 4: Calendar Event Interrupt Enable */
-
-#define RTC_IDR_ACKDIS (1 << 0) /* Bit 0: Acknowledge Update Interrupt Disable */
-#define RTC_IDR_ALRDIS (1 << 1) /* Bit 1: Alarm Interrupt Disable */
-#define RTC_IDR_SECDIS (1 << 2) /* Bit 2: Second Event Interrupt Disable */
-#define RTC_IDR_TIMDIS (1 << 3) /* Bit 3: Time Event Interrupt Disable */
-#define RTC_IDR_CALDIS (1 << 4) /* Bit 4: Calendar Event Interrupt Disable */
-
-#define RTC_IMR_ACK (1 << 0) /* Bit 0: Acknowledge Update Interrupt Mask */
-#define RTC_IMR_ALR (1 << 1) /* Bit 1: Alarm Interrupt Mask */
-#define RTC_IMR_SEC (1 << 2) /* Bit 2: Second Event Interrupt Mask */
-#define RTC_IMR_TIM (1 << 3) /* Bit 3: Time Event Interrupt Mask */
-#define RTC_IMR_CAL (1 << 4) /* Bit 4: Calendar Event Interrupt Mask */
-
-#define RTC_VER_NVTIM (1 << 0) /* Bit 0: Non-valid Time */
-#define RTC_VER_NVCAL (1 << 1) /* Bit 1: Non-valid Calendar */
-#define RTC_VER_NVTIMALR (1 << 2) /* Bit 2: Non-valid Time Alarm */
-#define RTC_VER_NVCALALR (1 << 3) /* Bit 3: Non-valid Calendar Alarm */
-
-/****************************************************************************************
- * Public Types
- ****************************************************************************************/
-
-/****************************************************************************************
- * Public Data
- ****************************************************************************************/
-
-/****************************************************************************************
- * Public Functions
- ****************************************************************************************/
-
-#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_RTC_H */
+/**************************************************************************************** + * arch/arm/src/sam3u/sam3u_rtc.h + * + * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_RTC_H +#define __ARCH_ARM_SRC_SAM3U_SAM3U_RTC_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +#include <nuttx/config.h> + +#include "chip.h" +#include "sam3u_memorymap.h" + +/**************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************/ + +/* RTC register offsets *****************************************************************/ + +#define SAM3U_RTC_CR_OFFSET 0x00 /* Control Register */ +#define SAM3U_RTC_MR_OFFSET 0x04 /* Mode Register */ +#define SAM3U_RTC_TIMR_OFFSET 0x08 /* Time Register */ +#define SAM3U_RTC_CALR_OFFSET 0x0c /* Calendar Register */ +#define SAM3U_RTC_TIMALR_OFFSET 0x10 /* Time Alarm Register */ +#define SAM3U_RTC_CALALR_OFFSET 0x14 /* Calendar Alarm Register */ +#define SAM3U_RTC_SR_OFFSET 0x18 /* Status Register */ +#define SAM3U_RTC_SCCR_OFFSET 0x1c /* Status Clear Command Register */ +#define SAM3U_RTC_IER_OFFSET 0x20 /* Interrupt Enable Register */ +#define SAM3U_RTC_IDR_OFFSET 0x24 /* Interrupt Disable Register */ +#define SAM3U_RTC_IMR_OFFSET 0x28 /* Interrupt Mask Register */ +#define SAM3U_RTC_VER_OFFSET 0x2c /* Valid Entry Register */ + +/* RTC register adresses ****************************************************************/ + +#define SAM3U_RTC_CR (SAM3U_RTC_BASE+SAM3U_RTC_CR_OFFSET) +#define SAM3U_RTC_MR (SAM3U_RTC_BASE+SAM3U_RTC_MR_OFFSET) +#define SAM3U_RTC_TIMR (SAM3U_RTC_BASE+SAM3U_RTC_TIMR_OFFSET) +#define SAM3U_RTC_CALR (SAM3U_RTC_BASE+SAM3U_RTC_CALR_OFFSET) +#define SAM3U_RTC_TIMALR (SAM3U_RTC_BASE+SAM3U_RTC_TIMALR_OFFSET) +#define SAM3U_RTC_CALALR (SAM3U_RTC_BASE+SAM3U_RTC_CALALR_OFFSET) +#define SAM3U_RTC_SR (SAM3U_RTC_BASE+SAM3U_RTC_SR_OFFSET) +#define SAM3U_RTC_SCCR (SAM3U_RTC_BASE+SAM3U_RTC_SCCR_OFFSET) +#define SAM3U_RTC_IER (SAM3U_RTC_BASE+SAM3U_RTC_IER_OFFSET) +#define SAM3U_RTC_IDR (SAM3U_RTC_BASE+SAM3U_RTC_IDR_OFFSET) +#define SAM3U_RTC_IMR (SAM3U_RTC_BASE+SAM3U_RTC_IMR_OFFSET) +#define SAM3U_RTC_VER (SAM3U_RTC_BASE+SAM3U_RTC_VER_OFFSET) + +/* RTC register bit definitions *********************************************************/ + +#define RTC_CR_UPDTIM (1 << 0) /* Bit 0: Update Request Time Register */ +#define RTC_CR_UPDCAL (1 << 1) /* Bit 1: Update Request Calendar Register */ +#define RTC_CR_TIMEVSEL_SHIFT (8) /* Bits 8-9: Time Event Selection */ +#define RTC_CR_TIMEVSEL_MASK (3 << RTC_CR_TIMEVSEL_SHIFT) +# define RTC_CR_TIMEVSEL_MIN (0 << RTC_CR_TIMEVSEL_SHIFT) +# define RTC_CR_TIMEVSEL_HOUR (1 << RTC_CR_TIMEVSEL_SHIFT) +# define RTC_CR_TIMEVSEL_MIDNIGHT (2 << RTC_CR_TIMEVSEL_SHIFT) +# define RTC_CR_TIMEVSEL_NOON (3 << RTC_CR_TIMEVSEL_SHIFT) +#define RTC_CR_CALEVSEL_SHIFT (16) /* Bits 16-17: Calendar Event Selection */ +#define RTC_CR_CALEVSEL_MASK (3 << RTC_CR_CALEVSEL_SHIFT) +# define RTC_CR_CALEVSEL_WEEK (0 << RTC_CR_CALEVSEL_SHIFT) +# define RTC_CR_CALEVSEL_MONTH (1 << RTC_CR_CALEVSEL_SHIFT) +# define RTC_CR_CALEVSEL_YEAR (2 << RTC_CR_CALEVSEL_SHIFT) + +#define RTC_MR_HRMOD (1 << 0) /* Bit 0: 12-/24-hour Mode */ + +#define RTC_TIMR_SEC_SHIFT (0) /* Bits 0-6: Current Second */ +#define RTC_TIMR_SEC_MASK (0x7f << RTC_TIMR_SEC_SHIFT) +#define RTC_TIMR_MIN_SHIFT (8) /* Bits 8-14: Current Minute */ +#define RTC_TIMR_MIN_MASK (0x7f << RTC_TIMR_MIN_SHIFT) +#define RTC_TIMR_HOUR_SHIFT (16) /* Bits 16-21: Current Hour */ +#define RTC_TIMR_HOUR_MASK (0x3f << RTC_TIMR_HOUR_SHIFT) +#define RTC_TIMR_AMPM (1 << 22) /* Bit 22: Ante Meridiem Post Meridiem Indicator */ + +#define RTC_CALR_CENT_SHIFT (0) /* Bits 0-6: Current Century */ +#define RTC_CALR_CENT_MASK (0x7f << RTC_TIMR_HOUR_SHIFT) +#define RTC_CALR_YEAR_SHIFT (8) /* Bits 8-15: Current Year */ +#define RTC_CALR_YEAR_MASK (0xff << RTC_CALR_YEAR_SHIFT) +#define RTC_CALR_MONTH_SHIFT (16) /* Bits 16-20: Current Month */ +#define RTC_CALR_MONTH_MASK (0x1f << RTC_CALR_MONTH_SHIFT) +#define RTC_CALR_DAY_SHIFT (21) /* Bits 21-23: Current Day in Current Week */ +#define RTC_CALR_DAY_MASK (7 << RTC_CALR_DAY_SHIFT) +#define RTC_CALR_DATE_SHIFT (24) /* Bits 24-29: Current Day in Current Month */ +#define RTC_CALR_DATE_MASK (0x3f << RTC_CALR_DATE_SHIFT) + +#define RTC_TIMALR_SEC_SHIFT (0) /* Bits 0-6: Second Alarm */ +#define RTC_TIMALR_SEC_MASK (0x7f << RTC_TIMALR_SEC_SHIFT) +#define RTC_TIMALR_SECEN (1 << 7) /* Bit 7: Second Alarm Enable */ +#define RTC_TIMALR_MIN_SHIFT (8) /* Bits 8-14: Minute Alarm */ +#define RTC_TIMALR_MIN_MASK (0x7f << RTC_TIMALR_MIN_SHIFT) +#define RTC_TIMALR_MINEN (1 << 15) /* Bit 15: Minute Alarm Enable */ +#define RTC_TIMALR_HOUR_SHIFT (16) /* Bits 16-21: Hour Alarm */ +#define RTC_TIMALR_HOUR_MASK (0x3f << RTC_TIMALR_HOUR_SHIFT) +#define RTC_TIMALR_AMPM (1 << 22) /* Bit 22: AM/PM Indicator */ +#define RTC_TIMALR_HOUREN (1 << 23) /* Bit 23: Hour Alarm Enable */ + +#define RTC_CALALR_MONTH_SHIFT (16) /* Bits 16-20: Month Alarm */ +#define RTC_CALALR_MONTH_MASK (0x1f << RTC_CALALR_MONTH_SHIFT) +#define RTC_CALALR_MTHEN (1 << 23) /* Bit 23: Month Alarm Enable */ +#define RTC_CALALR_DATE_SHIFT (24) /* Bits 24-29: Date Alarm */ +#define RTC_CALALR_DATE_MASK (0x3c << RTC_CALALR_DATE_SHIFT) +#define RTC_CALALR_DATEEN (1 << 31) /* Bit 31: Date Alarm Enable */ + +#define RTC_SR_ACKUPD (1 << 0) /* Bit 0: Acknowledge for Update */ +#define RTC_SR_ALARM (1 << 1) /* Bit 1: Alarm Flag */ +#define RTC_SR_SEC (1 << 2) /* Bit 2: Second Event */ +#define RTC_SR_TIMEV (1 << 3) /* Bit 3: Time Event */ +#define RTC_SR_CALEV (1 << 4) /* Bit 4: Calendar Event */ + +#define RTC_SCCR_ACKCLR (1 << 0) /* Bit 0: Acknowledge Clear */ +#define RTC_SCCR_ALRCLR (1 << 1) /* Bit 1: Alarm Clear */ +#define RTC_SCCR_SECCLR (1 << 2) /* Bit 2: Second Clear */ +#define RTC_SCCR_TIMCLR (1 << 3) /* Bit 3: Time Clear */ +#define RTC_SCCR_CALCLR (1 << 4) /* Bit 4: Calendar Clear */ + +#define RTC_IER_ACKEN (1 << 0) /* Bit 0: Acknowledge Update Interrupt Enable */ +#define RTC_IER_ALREN (1 << 1) /* Bit 1: Alarm Interrupt Enable */ +#define RTC_IER_SECEN (1 << 2) /* Bit 2: Second Event Interrupt Enable */ +#define RTC_IER_TIMEN (1 << 3) /* Bit 3: Time Event Interrupt Enable */ +#define RTC_IER_CALEN (1 << 4) /* Bit 4: Calendar Event Interrupt Enable */ + +#define RTC_IDR_ACKDIS (1 << 0) /* Bit 0: Acknowledge Update Interrupt Disable */ +#define RTC_IDR_ALRDIS (1 << 1) /* Bit 1: Alarm Interrupt Disable */ +#define RTC_IDR_SECDIS (1 << 2) /* Bit 2: Second Event Interrupt Disable */ +#define RTC_IDR_TIMDIS (1 << 3) /* Bit 3: Time Event Interrupt Disable */ +#define RTC_IDR_CALDIS (1 << 4) /* Bit 4: Calendar Event Interrupt Disable */ + +#define RTC_IMR_ACK (1 << 0) /* Bit 0: Acknowledge Update Interrupt Mask */ +#define RTC_IMR_ALR (1 << 1) /* Bit 1: Alarm Interrupt Mask */ +#define RTC_IMR_SEC (1 << 2) /* Bit 2: Second Event Interrupt Mask */ +#define RTC_IMR_TIM (1 << 3) /* Bit 3: Time Event Interrupt Mask */ +#define RTC_IMR_CAL (1 << 4) /* Bit 4: Calendar Event Interrupt Mask */ + +#define RTC_VER_NVTIM (1 << 0) /* Bit 0: Non-valid Time */ +#define RTC_VER_NVCAL (1 << 1) /* Bit 1: Non-valid Calendar */ +#define RTC_VER_NVTIMALR (1 << 2) /* Bit 2: Non-valid Time Alarm */ +#define RTC_VER_NVCALALR (1 << 3) /* Bit 3: Non-valid Calendar Alarm */ + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +/**************************************************************************************** + * Public Data + ****************************************************************************************/ + +/**************************************************************************************** + * Public Functions + ****************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_RTC_H */ diff --git a/nuttx/arch/arm/src/sam3u/sam3u_rtt.h b/nuttx/arch/arm/src/sam3u/sam3u_rtt.h index ea25fbc4a..9cbb69b0a 100644 --- a/nuttx/arch/arm/src/sam3u/sam3u_rtt.h +++ b/nuttx/arch/arm/src/sam3u/sam3u_rtt.h @@ -1,89 +1,89 @@ -/****************************************************************************************
- * arch/arm/src/sam3u/sam3u_rtt.h
- *
- * Copyright (C) 2009 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_RTT_H
-#define __ARCH_ARM_SRC_SAM3U_SAM3U_RTT_H
-
-/****************************************************************************************
- * Included Files
- ****************************************************************************************/
-
-#include <nuttx/config.h>
-
-#include "chip.h"
-#include "sam3u_memorymap.h"
-
-/****************************************************************************************
- * Pre-processor Definitions
- ****************************************************************************************/
-
-/* RTT register offsets *****************************************************************/
-
-#define SAM3U_RTT_MR_OFFSET 0x00 /* Mode Register */
-#define SAM3U_RTT_AR_OFFSET 0x04 /* Alarm Register */
-#define SAM3U_RTT_VR_OFFSET 0x08 /* Value Register */
-#define SAM3U_RTT_SR_OFFSET 0x0c /* Status Register */
-
-/* RTT register adresses ***************************************************************/
-
-#define SAM3U_RTT_MR (SAM3U_RTT_BASE+SAM3U_RTT_MR_OFFSET)
-#define SAM3U_RTT_AR (SAM3U_RTT_BASE+SAM3U_RTT_AR_OFFSET)
-#define SAM3U_RTT_VR (SAM3U_RTT_BASE+SAM3U_RTT_VR_OFFSET)
-#define SAM3U_RTT_SR (SAM3U_RTT_BASE+SAM3U_RTT_SR_OFFSET)
-
-/* RTT register bit definitions ********************************************************/
-
-#define RTT_MR_RTPRES_SHIFT (0) /* Bits 0-15: Real-time Timer Prescaler Value */
-#define RTT_MR_RTPRES__MASK (0xffff << RTT_MR_RTPRES_SHIFT)
-#define RTT_MR_ALMIEN (1 << 16) /* Bit 16: Alarm Interrupt Enable */
-#define RTT_MR_RTTINCIEN (1 << 17) /* Bit 17: Real-time Timer Increment Int Enable */
-#define RTT_MR_RTTRST (1 << 18) /* Bit 18: Real-time Timer Restart */
-
-#define RTT_SR_ALMS (1 << 0) /* Bit 0: Real-time Alarm Status */
-#define RTT_SR_RTTINC (1 << 1) /* Bit 1: Real-time Timer Increment */
-
-/****************************************************************************************
- * Public Types
- ****************************************************************************************/
-
-/****************************************************************************************
- * Public Data
- ****************************************************************************************/
-
-/****************************************************************************************
- * Public Functions
- ****************************************************************************************/
-
-#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_RTT_H */
+/**************************************************************************************** + * arch/arm/src/sam3u/sam3u_rtt.h + * + * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_RTT_H +#define __ARCH_ARM_SRC_SAM3U_SAM3U_RTT_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +#include <nuttx/config.h> + +#include "chip.h" +#include "sam3u_memorymap.h" + +/**************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************/ + +/* RTT register offsets *****************************************************************/ + +#define SAM3U_RTT_MR_OFFSET 0x00 /* Mode Register */ +#define SAM3U_RTT_AR_OFFSET 0x04 /* Alarm Register */ +#define SAM3U_RTT_VR_OFFSET 0x08 /* Value Register */ +#define SAM3U_RTT_SR_OFFSET 0x0c /* Status Register */ + +/* RTT register adresses ***************************************************************/ + +#define SAM3U_RTT_MR (SAM3U_RTT_BASE+SAM3U_RTT_MR_OFFSET) +#define SAM3U_RTT_AR (SAM3U_RTT_BASE+SAM3U_RTT_AR_OFFSET) +#define SAM3U_RTT_VR (SAM3U_RTT_BASE+SAM3U_RTT_VR_OFFSET) +#define SAM3U_RTT_SR (SAM3U_RTT_BASE+SAM3U_RTT_SR_OFFSET) + +/* RTT register bit definitions ********************************************************/ + +#define RTT_MR_RTPRES_SHIFT (0) /* Bits 0-15: Real-time Timer Prescaler Value */ +#define RTT_MR_RTPRES__MASK (0xffff << RTT_MR_RTPRES_SHIFT) +#define RTT_MR_ALMIEN (1 << 16) /* Bit 16: Alarm Interrupt Enable */ +#define RTT_MR_RTTINCIEN (1 << 17) /* Bit 17: Real-time Timer Increment Int Enable */ +#define RTT_MR_RTTRST (1 << 18) /* Bit 18: Real-time Timer Restart */ + +#define RTT_SR_ALMS (1 << 0) /* Bit 0: Real-time Alarm Status */ +#define RTT_SR_RTTINC (1 << 1) /* Bit 1: Real-time Timer Increment */ + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +/**************************************************************************************** + * Public Data + ****************************************************************************************/ + +/**************************************************************************************** + * Public Functions + ****************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_RTT_H */ diff --git a/nuttx/arch/arm/src/sam3u/sam3u_smc.h b/nuttx/arch/arm/src/sam3u/sam3u_smc.h index f8b6e837e..c831a91cd 100644 --- a/nuttx/arch/arm/src/sam3u/sam3u_smc.h +++ b/nuttx/arch/arm/src/sam3u/sam3u_smc.h @@ -1,432 +1,432 @@ -/****************************************************************************************
- * arch/arm/src/sam3u/sam3u_smc.h
- *
- * Copyright (C) 2009 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_SMC_H
-#define __ARCH_ARM_SRC_SAM3U_SAM3U_SMC_H
-
-/****************************************************************************************
- * Included Files
- ****************************************************************************************/
-
-#include <nuttx/config.h>
-
-#include "chip.h"
-#include "sam3u_memorymap.h"
-
-/****************************************************************************************
- * Pre-processor Definitions
- ****************************************************************************************/
-
-/* SMC register offsets *****************************************************************/
-
-#define SAM3U_SMC_CFG_OFFSET 0x000 /* SMC NFC Configuration Register */
-#define SAM3U_SMC_CTRL_OFFSET 0x004 /* SMC NFC Control Register */
-#define SAM3U_SMC_SR_OFFSET 0x008 /* SMC NFC Status Register */
-#define SAM3U_SMC_IER_OFFSET 0x00c /* SMC NFC Interrupt Enable Register */
-#define SAM3U_SMC_IDR_OFFSET 0x010 /* SMC NFC Interrupt Disable Register */
-#define SAM3U_SMC_IMR_OFFSET 0x014 /* SMC NFC Interrupt Mask Register */
-#define SAM3U_SMC_ADDR_OFFSET 0x018 /* SMC NFC Address Cycle Zero Register */
-#define SAM3U_SMC_BANK_OFFSET 0x01c /* SMC Bank Address Register */
-#define SAM3U_SMC_ECCCTRL_OFFSET 0x020 /* SMC ECC Control Register */
-#define SAM3U_SMC_ECCMD_OFFSET 0x024 /* SMC ECC Mode Register */
-#define SAM3U_SMC_ECCSR1_OFFSET 0x028 /* SMC ECC Status 1 Register */
-#define SAM3U_SMC_ECCPR0_OFFSET 0x02c /* SMC ECC parity 0 Register */
-#define SAM3U_SMC_ECCPR1_OFFSET 0x030 /* SMC ECC parity 1 Register */
-#define SAM3U_SMC_ECCSR2_OFFSET 0x034 /* SMC ECC status 2 Register */
-#define SAM3U_SMC_ECCPR2_OFFSET 0x038 /* SMC ECC parity 2 Register */
-#define SAM3U_SMC_ECCPR3_OFFSET 0x03c /* SMC ECC parity 3 Register */
-#define SAM3U_SMC_ECCPR4_OFFSET 0x040 /* SMC ECC parity 4 Register */
-#define SAM3U_SMC_ECCPR5_OFFSET 0x044 /* SMC ECC parity 5 Register */
-#define SAM3U_SMC_ECCPR6_OFFSET 0x048 /* SMC ECC parity 6 Register */
-#define SAM3U_SMC_ECCPR7_OFFSET 0x04c /* SMC ECC parity 7 Register */
-#define SAM3U_SMC_ECCPR8_OFFSET 0x050 /* SMC ECC parity 8 Register */
-#define SAM3U_SMC_ECCPR9_OFFSET 0x054 /* SMC ECC parity 9 Register */
-#define SAM3U_SMC_ECCPR10_OFFSET 0x058 /* SMC ECC parity 10 Register */
-#define SAM3U_SMC_ECCPR11_OFFSET 0x05c /* SMC ECC parity 11 Register */
-#define SAM3U_SMC_ECCPR12_OFFSET 0x060 /* SMC ECC parity 12 Register */
-#define SAM3U_SMC_ECCPR13_OFFSET 0x064 /* SMC ECC parity 13 Register */
-#define SAM3U_SMC_ECCPR14_OFFSET 0x068 /* SMC ECC parity 14 Register */
-#define SAM3U_SMC_ECCPR15_OFFSET 0x06c /* SMC ECC parity 15 Register */
-
-#define SAM3U_SMCCS_OFFSET(n) (0x070+((n)*0x014))
-#define SAM3U_SMCCS_SETUP_OFFSET 0x000 /* SMC SETUP Register */
-#define SAM3U_SMCCS_PULSE_OFFSET 0x004 /* SMC PULSE Register */
-#define SAM3U_SMCCS_CYCLE_OFFSET 0x008 /* SMC CYCLE Register */
-#define SAM3U_SMCCS_TIMINGS_OFFSET 0x00c /* SMC TIMINGS Register */
-#define SAM3U_SMCCS_MODE_OFFSET 0x010 /* SMC MODE Register */
-
-#define SAM3U_SMC_OCMS_OFFSET 0x110 /* SMC OCMS MODE Register */
-#define SAM3U_SMC_KEY1_OFFSET 0x114 /* SMC KEY1 Register */
-#define SAM3U_SMC_KEY2_OFFSET 0x118 /* SMC KEY2 Register */
-#define SAM3U_SMC_WPCR_OFFSET 0x1e4 /* Write Protection Control Register */
-#define SAM3U_SMC_WPSR_OFFSET 0x1e8 /* Write Protection Status Register */
-
-/* SMC register adresses ****************************************************************/
-
-#define SAM3U_SMC_CFG (SAM3U_SMC_BASE+SAM3U_SMC_CFG_OFFSET)
-#define SAM3U_SMC_CTRL (SAM3U_SMC_BASE+SAM3U_SMC_CTRL_OFFSET)
-#define SAM3U_SMC_SR (SAM3U_SMC_BASE+SAM3U_SMC_SR_OFFSET)
-#define SAM3U_SMC_IER (SAM3U_SMC_BASE+SAM3U_SMC_IER_OFFSET)
-#define SAM3U_SMC_IDR (SAM3U_SMC_BASE+SAM3U_SMC_IDR_OFFSET)
-#define SAM3U_SMC_IMR (SAM3U_SMC_BASE+SAM3U_SMC_IMR_OFFSET)
-#define SAM3U_SMC_ADDR (SAM3U_SMC_BASE+SAM3U_SMC_ADDR_OFFSET)
-#define SAM3U_SMC_BANK (SAM3U_SMC_BASE+SAM3U_SMC_BANK_OFFSET)
-#define SAM3U_SMC_ECCCTRL (SAM3U_SMC_BASE+SAM3U_SMC_ECCCTRL_OFFSET)
-#define SAM3U_SMC_ECCMD (SAM3U_SMC_BASE+SAM3U_SMC_ECCMD_OFFSET)
-#define SAM3U_SMC_ECCSR1 (SAM3U_SMC_BASE+SAM3U_SMC_ECCSR1_OFFSET)
-#define SAM3U_SMC_ECCPR0 (SAM3U_SMC_BASE+SAM3U_SMC_ECCPR0_OFFSET)
-#define SAM3U_SMC_ECCPR1 (SAM3U_SMC_BASE+SAM3U_SMC_ECCPR1_OFFSET)
-#define SAM3U_SMC_ECCSR2 (SAM3U_SMC_BASE+SAM3U_SMC_ECCSR2_OFFSET)
-#define SAM3U_SMC_ECCPR2 (SAM3U_SMC_BASE+SAM3U_SMC_ECCPR2_OFFSET)
-#define SAM3U_SMC_ECCPR3 (SAM3U_SMC_BASE+SAM3U_SMC_ECCPR3_OFFSET)
-#define SAM3U_SMC_ECCPR4 (SAM3U_SMC_BASE+SAM3U_SMC_ECCPR4_OFFSET)
-#define SAM3U_SMC_ECCPR5 (SAM3U_SMC_BASE+SAM3U_SMC_ECCPR5_OFFSET)
-#define SAM3U_SMC_ECCPR6 (SAM3U_SMC_BASE+SAM3U_SMC_ECCPR6_OFFSET)
-#define SAM3U_SMC_ECCPR7 (SAM3U_SMC_BASE+SAM3U_SMC_ECCPR7_OFFSET)
-#define SAM3U_SMC_ECCPR8 (SAM3U_SMC_BASE+SAM3U_SMC_ECCPR8_OFFSET)
-#define SAM3U_SMC_ECCPR9 (SAM3U_SMC_BASE+SAM3U_SMC_ECCPR9_OFFSET)
-#define SAM3U_SMC_ECCPR10 (SAM3U_SMC_BASE+SAM3U_SMC_ECCPR10_OFFSET)
-#define SAM3U_SMC_ECCPR11 (SAM3U_SMC_BASE+SAM3U_SMC_ECCPR11_OFFSET)
-#define SAM3U_SMC_ECCPR12 (SAM3U_SMC_BASE+SAM3U_SMC_ECCPR12_OFFSET)
-#define SAM3U_SMC_ECCPR13 (SAM3U_SMC_BASE+SAM3U_SMC_ECCPR13_OFFSET)
-#define SAM3U_SMC_ECCPR14 (SAM3U_SMC_BASE+SAM3U_SMC_ECCPR14_OFFSET)
-#define SAM3U_SMC_ECCPR15 (SAM3U_SMC_BASE+SAM3U_SMC_ECCPR15_OFFSET)
-
-#define SAM3U_SMCCS_BASE(n) (SAM3U_SMC_BASE+SAM3U_SMCCS_OFFSET(n))
-# define SAM3U_SMC_CS0_BASE (SAM3U_SMC_BASE+SAM3U_SMCCS_OFFSET(0))
-# define SAM3U_SMC_CS1_BASE (SAM3U_SMC_BASE+SAM3U_SMCCS_OFFSET(1))
-# define SAM3U_SMC_CS2_BASE (SAM3U_SMC_BASE+SAM3U_SMCCS_OFFSET(2))
-# define SAM3U_SMC_CS3_BASE (SAM3U_SMC_BASE+SAM3U_SMCCS_OFFSET(3))
-#define SAM3U_SMCCS_SETUP(n) (SAM3U_SMCCS_BASE(n)+SAM3U_SMCCS_SETUP_OFFSET)
-#define SAM3U_SMCCS_PULSE(n) (SAM3U_SMCCS_BASE(n)+SAM3U_SMCCS_PULSE_OFFSET)
-#define SAM3U_SMCCS_CYCLE(n) (SAM3U_SMCCS_BASE(n)+SAM3U_SMCCS_CYCLE_OFFSET)
-#define SAM3U_SMCCS_TIMINGS(n) (SAM3U_SMCCS_BASE(n)+SAM3U_SMCCS_TIMINGS_OFFSET)
-#define SAM3U_SMCCS_MODE(n) (SAM3U_SMCCS_BASE(n)+SAM3U_SMCCS_MODE_OFFSET)
-
-#define SAM3U_SMC_OCMS (SAM3U_SMC_BASE+SAM3U_SMC_OCMS_OFFSET)
-#define SAM3U_SMC_KEY1 (SAM3U_SMC_BASE+SAM3U_SMC_KEY1_OFFSET)
-#define SAM3U_SMC_KEY2 (SAM3U_SMC_BASE+SAM3U_SMC_KEY2_OFFSET)
-#define SAM3U_SMC_WPCR (SAM3U_SMC_BASE+SAM3U_SMC_WPCR_OFFSET)
-#define SAM3U_SMC_WPSR (SAM3U_SMC_BASE+SAM3U_SMC_WPSR_OFFSET)
-
-/* SMC register bit definitions *********************************************************/
-
-/* SMC NFC Configuration Register */
-
-#define SMC_CFG_PAGESIZE_SHIFT (0) /* Bits 0-1: Page size of NAND Flash device */
-#define SMC_CFG_PAGESIZE_MASK (3 << SMC_CFG_PAGESIZE_SHIFT)
-# define SMC_CFG_PAGESIZE_16 BYTES (0 << SMC_CFG_PAGESIZE_SHIFT) /* 528 Bytes 16 byte */
-# define SMC_CFG_PAGESIZE_ 2 BYTES (1 << SMC_CFG_PAGESIZE_SHIFT) /* 1056 Bytes 32 bytes */
-# define SMC_CFG_PAGESIZE_64 BYTES (2 << SMC_CFG_PAGESIZE_SHIFT) /* 2112 Bytes 64 bytes */
-# define SMC_CFG_PAGESIZE_128 BYTES (3 << SMC_CFG_PAGESIZE_SHIFT) /* 4224 Bytes 128 bytes */
-#define SMC_CFG_WSPARE (1 << 8) /* Bit 8: Write Spare Area */
-#define SMC_CFG_RSPARE (1 << 9) /* Bit 9: Read Spare Area */
-#define SMC_CFG_EDGECTRL (1 << 12) /* Bit 12: Rising/Falling Edge Detection Control */
-#define SMC_CFG_RBEDGE (1 << 13) /* Bit 13: Ready/Busy Signal Edge Detection */
-#define SMC_CFG_DTOCYC_SHIFT (16) /* Bits 16-19: Data Timeout Cycle Number */
-#define SMC_CFG_DTOCYC_MASK (15 << SMC_CFG_DTOCYC_SHIFT)
-#define SMC_CFG_DTOMUL_SHIFT (20) /* Bits 20-22: Data Timeout Multiplier */
-#define SMC_CFG_DTOMUL_MASK (7 << SMC_CFG_DTOMUL_SHIFT)
-# define SMC_CFG_DTOMUL_1 (0 << SMC_CFG_DTOMUL_SHIFT)
-# define SMC_CFG_DTOMUL_16 (1 << SMC_CFG_DTOMUL_SHIFT)
-# define SMC_CFG_DTOMUL_128 (2 << SMC_CFG_DTOMUL_SHIFT)
-# define SMC_CFG_DTOMUL_256 (3 << SMC_CFG_DTOMUL_SHIFT)
-# define SMC_CFG_DTOMUL_1024 (4 << SMC_CFG_DTOMUL_SHIFT)
-# define SMC_CFG_DTOMUL_4096 (5 << SMC_CFG_DTOMUL_SHIFT)
-# define SMC_CFG_DTOMUL_65536 (6 << SMC_CFG_DTOMUL_SHIFT)
-# define SMC_CFG_DTOMUL_1048576 (7 << SMC_CFG_DTOMUL_SHIFT)
-
-/* SMC NFC Control Register */
-
-#define SMC_CTRL_NFCEN (1 << 0) /* Bit 0: NAND Flash Controller Enable */
-#define SMC_CTRL_NFCDIS (1 << 1) /* Bit 1: NAND Flash Controller Disable */
-
-/* SMC NFC Status Register, SMC NFC Interrupt Enable Register, SMC NFC Interrupt
- * Disable Register, and SMC NFC Interrupt Mask Register common bit-field definitions
- */
-
-#define SMC_SR_SMCSTS (1 << 0) /* Bit 0: NAND Flash Controller status (SR only) */
-#define SMC_INT_RBRISE (1 << 4) /* Bit 4: Ready Busy Rising Edge Detection Interrupt */
-#define SMC_INT_RBFALL (1 << 5) /* Bit 5: Ready Busy Falling Edge Detection Interrupt */
-#define SMC_SR_NFCBUSY (1 << 8) /* Bit 8: NFC Busy (SR only) */
-#define SMC_SR_NFCWR (1 << 11) /* Bit 11: NFC Write/Read Operation (SR only) */
-#define SMC_SR_NFCSID (1 << 12) /* Bit 13: NFC Chip Select ID (SR only) */
-#define SMC_INT_XFRDONE (1 << 16) /* Bit 16: Transfer Done Interrupt */
-#define SMC_INT_CMDDONE (1 << 17) /* Bit 17: Command Done Interrupt */
-#define SMC_INT_DTOE (1 << 20) /* Bit 20: Data Timeout Error Interrupt */
-#define SMC_INT_UNDEF (1 << 21) /* Bit 21: Undefined Area Access Interrupt */
-#define SMC_INT_AWB (1 << 22) /* Bit 22: Accessing While Busy Interrupt */
-#define SMC_INT_NFCASE (1 << 23) /* Bit 23: NFC Access Size Error Interrupt */
-#define SMC_INT_RBEDGE(n) (1<<((n)+24))
-#define SMC_INT_RB_EDGE0 (1 << 24) /* Bit 24: Ready/Busy Line 0 Interrupt */
-#define SMC_INT_RB_EDGE1 (1 << 25) /* Bit 25: Ready/Busy Line 1 Interrupt */
-#define SMC_INT_RB_EDGE2 (1 << 26) /* Bit 26: Ready/Busy Line 2 Interrupt */
-#define SMC_INT_RB_EDGE3 (1 << 27) /* Bit 27: Ready/Busy Line 3 Interrupt */
-#define SMC_INT_RB_EDGE4 (1 << 28) /* Bit 28: Ready/Busy Line 4 Interrupt */
-#define SMC_INT_RB_EDGE5 (1 << 29) /* Bit 29: Ready/Busy Line 5 Interrupt */
-#define SMC_INT_RB_EDGE6 (1 << 30) /* Bit 30: Ready/Busy Line 6 Interrupt */
-#define SMC_INT_RB_EDGE7 (1 << 31) /* Bit 31: Ready/Busy Line 7 Interrupt */
-
-/* SMC NFC Address Cycle Zero Register */
-
-#define SMC_ADDR_ADDR_CYCLE0_SHIFT (3) /* Bits 0-7: NAND Flash Array Address cycle 0 */
-#define SMC_ADDR_ADDR_CYCLE0_SHIFT (3) /* Bits 0-7: NAND Flash Array Address cycle 0 */
-
-/* SMC NFC Bank Register */
-
-#define SMC_BANK_SHIFT (0) /* Bits 0-2: Bank identifier */
-#define SMC_BANK_MASK (7 << SMC_BANK_SHIFT)
-
-/* SMC ECC Control Register */
-
-#define SMC_ECCCTRL_RST (1 << 0) /* Bit 0: Reset ECC */
-#define SMC_ECCCTRL_SWRST (1 << 1) /* Bit 1: Software Reset */
-
-/* SMC ECC MODE Register */
-
-#define SMC_ECCMD_ECC_PAGESIZE_SHIFT (0) /* Bits 0-1 */
-#define SMC_ECCMD_ECC_PAGESIZE_MASK (3 << SMC_ECCMD_ECC_PAGESIZE_SHIFT)
-# define SMC_ECCMD_ECC_PAGESIZE_528 (0 << SMC_ECCMD_ECC_PAGESIZE_SHIFT)
-# define SMC_ECCMD_ECC_PAGESIZE_1056 (1 << SMC_ECCMD_ECC_PAGESIZE_SHIFT)
-# define SMC_ECCMD_ECC_PAGESIZE_2112 (2 << SMC_ECCMD_ECC_PAGESIZE_SHIFT)
-# define SMC_ECCMD_ECC_PAGESIZE_4224 (3 << SMC_ECCMD_ECC_PAGESIZE_SHIFT)
-#define SMC_ECCMD_TYPCORREC_SHIFT (4) /* Bits 4-5: type of correction */
-#define SMC_ECCMD_TYPCORREC_MASK (3 << SMC_ECCMD_TYPCORREC_SHIFT)
-# define SMC_ECCMD_TYPCORREC_PAGE (0 << SMC_ECCMD_TYPCORREC_SHIFT) /* 1 bit correction for a page */
-# define SMC_ECCMD_TYPCORREC_256 (1 << SMC_ECCMD_TYPCORREC_SHIFT) /* 1 bit correction for 256 bytes */
-# define SMC_ECCMD_TYPCORREC_512 (2 << SMC_ECCMD_TYPCORREC_SHIFT) /* 1 bit correction for 512 bytes */
-
-/* SMC ECC Status Register 1 */
-
-#define _RECERR (0) /* Recoverable Error */
-#define _ECCERR (1) /* ECC Error */
-#define _MULERR (2) /* Multiple Error */
-
-#define SMC_ECCSR1_RECERR(n) (1 << (((n)<<4)+_RECERR))
-#define SMC_ECCSR1_ECCERR(n) (1 << (((n)<<4)+_ECCERR))
-#define SMC_ECCSR1_MULERR(n) (1 << (((n)<<4)+_MULERR))
-
-#define SMC_ECCSR1_RECERR0 SMC_ECCSR1_RECERR(0)
-#define SMC_ECCSR1_ECCERR0 SMC_ECCSR1_ECCERR(0)
-#define SMC_ECCSR1_MULERR0 SMC_ECCSR1_MULERR(0)
-#define SMC_ECCSR1_RECERR1 SMC_ECCSR1_RECERR(1)
-#define SMC_ECCSR1_ECCERR1 SMC_ECCSR1_ECCERR(1)
-#define SMC_ECCSR1_MULERR1 SMC_ECCSR1_MULERR(1)
-#define SMC_ECCSR1_RECERR2 SMC_ECCSR1_RECERR(2)
-#define SMC_ECCSR1_ECCERR2 SMC_ECCSR1_ECCERR(2)
-#define SMC_ECCSR1_MULERR2 SMC_ECCSR1_MULERR(2)
-#define SMC_ECCSR1_RECERR3 SMC_ECCSR1_RECERR(3)
-#define SMC_ECCSR1_ECCERR3 SMC_ECCSR1_ECCERR(3)
-#define SMC_ECCSR1_MULERR3 SMC_ECCSR1_MULERR(3)
-#define SMC_ECCSR1_RECERR4 SMC_ECCSR1_RECERR(4)
-#define SMC_ECCSR1_ECCERR4 SMC_ECCSR1_ECCERR(4)
-#define SMC_ECCSR1_MULERR4 SMC_ECCSR1_MULERR(4)
-#define SMC_ECCSR1_RECERR5 SMC_ECCSR1_RECERR(5)
-#define SMC_ECCSR1_ECCERR5 SMC_ECCSR1_ECCERR(5)
-#define SMC_ECCSR1_MULERR5 SMC_ECCSR1_MULERR(5)
-#define SMC_ECCSR1_RECERR6 SMC_ECCSR1_RECERR(6)
-#define SMC_ECCSR1_ECCERR6 SMC_ECCSR1_ECCERR(6)
-#define SMC_ECCSR1_MULERR6 SMC_ECCSR1_MULERR(6)
-#define SMC_ECCSR1_RECERR7 SMC_ECCSR1_RECERR(7)
-#define SMC_ECCSR1_ECCERR7 SMC_ECCSR1_ECCERR(7)
-#define SMC_ECCSR1_MULERR7 SMC_ECCSR1_MULERR(7)
-
-/* SMC ECC Status Register 2 */
-
-#define SMC_ECCSR2_RECERR(n) (1 << ((((n)-8)<<4)+_RECERR))
-#define SMC_ECCSR2_ECCERR(n) (1 << ((((n)-8)<<4)+_ECCERR))
-#define SMC_ECCSR2_MULERR(n) (1 << ((((n)-8)<<4)+_MULERR))
-
-#define SMC_ECCSR2_RECERR8 SMC_ECCSR2_RECERR(8)
-#define SMC_ECCSR2_ECCERR8 SMC_ECCSR2_ECCERR(8)
-#define SMC_ECCSR2_MULERR8 SMC_ECCSR2_MULERR(8)
-#define SMC_ECCSR2_RECERR9 SMC_ECCSR2_RECERR(9)
-#define SMC_ECCSR2_ECCERR9 SMC_ECCSR2_ECCERR(9)
-#define SMC_ECCSR2_MULERR9 SMC_ECCSR2_MULERR(9)
-#define SMC_ECCSR2_RECERR10 SMC_ECCSR2_RECERR(10)
-#define SMC_ECCSR2_ECCERR10 SMC_ECCSR2_ECCERR(10)
-#define SMC_ECCSR2_MULERR10 SMC_ECCSR2_MULERR(10)
-#define SMC_ECCSR2_RECERR11 SMC_ECCSR2_RECERR(11)
-#define SMC_ECCSR2_ECCERR11 SMC_ECCSR2_ECCERR(11)
-#define SMC_ECCSR2_MULERR11 SMC_ECCSR2_MULERR(11)
-#define SMC_ECCSR2_RECERR12 SMC_ECCSR2_RECERR(12)
-#define SMC_ECCSR2_ECCERR12 SMC_ECCSR2_ECCERR(12)
-#define SMC_ECCSR2_MULERR12 SMC_ECCSR2_MULERR(12)
-#define SMC_ECCSR2_RECERR13 SMC_ECCSR2_RECERR(13)
-#define SMC_ECCSR2_ECCERR13 SMC_ECCSR2_ECCERR(13)
-#define SMC_ECCSR2_MULERR13 SMC_ECCSR2_MULERR(13)
-#define SMC_ECCSR1_RECERR14 SMC_ECCSR2_RECERR(14)
-#define SMC_ECCSR1_ECCERR14 SMC_ECCSR2_ECCERR(14)
-#define SMC_ECCSR1_MULERR14 SMC_ECCSR2_MULERR(14)
-#define SMC_ECCSR1_RECERR15 SMC_ECCSR2_RECERR(15)
-#define SMC_ECCSR1_ECCERR15 SMC_ECCSR2_ECCERR(15)
-#define SMC_ECCSR1_MULERR15 SMC_ECCSR2_MULERR(15)
-
-/* Registers for 1 ECC for a page of 512/1024/2048/4096 bytes */
-/* SMC_ECC_PR0 */
-
-#define SMC_ECCPR0_BITADDR_SHIFT (0) /* Bits 0-3: Bit Address */
-#define SMC_ECCPR0_BITADDR_MASK (15 << SMC_ECCPR0_BITADDR_SHIFT)
-#define SMC_ECCPR0_WORDADDR_SHIFT (4) /* Bits 4-15: Word Address */
-#define SMC_ECCPR0_WORDADDR_MASK (0xfff << SMC_ECCPR0_WORDADDR_SHIFT)
-
-#define SMC_ECCPR1_NPARITY_SHIFT (0) /* Bits 0-15 */
-#define SMC_ECCPR1_NPARITY_MASK (0xffff << SMC_ECCPR1_NPARITY_SHIFT)
-
-/* Registers for 1 ECC per 512 bytes for a page of 512/2048/4096 bytes, 8-bit word */
-
-#define SMC_ECCPR512_BITADDR_SHIFT (0) /* Bits 0-3: Bit Address */
-#define SMC_ECCPR512_BITADDR_MASK (15 << SMC_ECCPR512_BITADDR_SHIFT)
-#define SMC_ECCPR512_WORDADDR_SHIFT (4) /* Bits 4-15: Word Address */
-#define SMC_ECCPR512_WORDADDR_MASK (0xfff << SMC_ECCPR512_WORDADDR_SHIFT)
-#define SMC_ECCPR512_NPARITY_SHIFT (12) /* Bits 12-23 (or is it 31?) */
-#define SMC_ECCPR512_NPARITY_MASK (0xfff << SMC_ECCPR512_NPARITY_SHIFT)
-
-/* Registers for 1 ECC per 256 bytes for a page of 512/2048/4096 bytes, 8-bit word */
-
-#define SMC_ECCPR256_BITADDR_SHIFT (0) /* Bits 0-2: Bit Address */
-#define SMC_ECCPR256_BITADDR_MASK (7 << SMC_ECCPR256_BITADDR_SHIFT)
-#define SMC_ECCPR256_WORDADDR_SHIFT (4) /* Bits 4-10: Word Address */
-#define SMC_ECCPR256_WORDADDR_MASK (0x7f << SMC_ECCPR256_WORDADDR_SHIFT)
-#define SMC_ECCPR256_NPARITY_SHIFT (12) /* Bits 12-22 */
-#define SMC_ECCPR256_NPARITY_MASK (0x7ff << SMC_ECCPR256_NPARITY_SHIFT)
-
-/* SMC Setup Register */
-
-#define SMCCS_SETUP_NWESETUP_SHIFT (0) /* Bits 0-5: NWE Setup length */
-#define SMCCS_SETUP_NWESETUP_MASK (63 << SMCCS_SETUP_NWESETUP_SHIFT)
-#define SMCCS_SETUP_NCSWRSETUP_SHIFT (8) /* Bits 8-13: NCS Setup length in Write access */
-#define SMCCS_SETUP_NCSWRSETUP_MASK (63 << SMCCS_SETUP_NCSWRSETUP_SHIFT)
-#define SMCCS_SETUP_NRDSETUP_SHIFT (16) /* Bits 16-21: NRD Setup length */
-#define SMCCS_SETUP_NRDSETUP_MASK (63 << SMCCS_SETUP_NRDSETUP_SHIFT)
-#define SMCCS_SETUP_NCSRDSETUP_SHIFT (24) /* Bits 24-29: NCS Setup length in Read access */
-#define SMCCS_SETUP_NCSRDSETUP_MASK (63 << SMCCS_SETUP_NCSRDSETUP_SHIFT)
-
-/* SMC Pulse Register */
-
-#define SMCCS_PULSE_NWEPULSE_SHIFT (0) /* Bits 0-5: NWE Pulse Length */
-#define SMCCS_PULSE_NWEPULSE_MASK (63 << SMCCS_PULSE_NWEPULSE_SHIFT)
-#define SMCCS_PULSE_NCSWRPULSE_SHIFT (8) /* Bits 8-13: NCS Pulse Length in WRITE Access */
-#define SMCCS_PULSE_NCSWRPULSE_MASK (63 << SMCCS_PULSE_NCSWRPULSE_SHIFT)
-#define SMCCS_PULSE_RDPULSE_SHIFT (16) /* Bits 16-21: NRD Pulse Length */
-#define SMCCS_PULSE_RDPULSE_MASK (63 << SMCCS_PULSE_RDPULSE_SHIFT)
-#define SMCCS_PULSE_NCSRDPULSE_SHIFT (24) /* Bits 24-29: NCS Pulse Length in READ Access */
-#define SMCCS_PULSE_NCSRDPULSE_MASK (63 << SMCCS_PULSE_NCSRDPULSE_SHIFT)
-
-/* SMC Cycle Register */
-
-#define SMCCS_CYCLE_NWECYCLE_SHIFT (0) /* Bits 0-8: Total Write Cycle Length */
-#define SMCCS_CYCLE_NWECYCLE_MASK (0x1ff << SMCCS_CYCLE_NWECYCLE_SHIFT)
-#define SMCCS_CYCLE_NRDCYCLE_SHIFT (16) /* Bits 16-24: Total Read Cycle Length */
-#define SMCCS_CYCLE_NRDCYCLE_MASK (0x1ff << SMCCS_CYCLE_NRDCYCLE_SHIFT)
-
-/* SMC Timings Register */
-
-#define SMCCS_TIMINGS_TCLR_SHIFT (0) /* Bits 0-3: CLE to REN Low Delay */
-#define SMCCS_TIMINGS_TCLR_MASK (15 << SMCCS_TIMINGS_TCLR_SHIFT)
-#define SMCCS_TIMINGS_TADL_SHIFT (4) /* Bits 4-7: ALE to Data Start */
-#define SMCCS_TIMINGS_TADL_MASK (15 << SMCCS_TIMINGS_TADL_SHIFT)
-#define SMCCS_TIMINGS_TAR_SHIFT (8) /* Bits 8-11: ALE to REN Low Delay */
-#define SMCCS_TIMINGS_TAR_MASK (15 << SMCCS_TIMINGS_TAR_SHIFT)
-#define SMCCS_TIMINGS_OCMS (1 << 12) /* Bit 12: Off Chip Memory Scrambling Enable */
-#define SMCCS_TIMINGS_TRR_SHIFT (16) /* Bits 16-19: Ready to REN Low Delay */
-#define SMCCS_TIMINGS_TRR_MASK (15 << SMCCS_TIMINGS_TRR_SHIFT)
-#define SMCCS_TIMINGS_TWB_SHIFT (24) /* Bits 24-27: WEN High to REN to Busy */
-#define SMCCS_TIMINGS_TWB_MASK (15 << SMCCS_TIMINGS_TWB_SHIFT)
-#define SMCCS_TIMINGS_RBNSEL_SHIFT (28) /* Bits 28-30: Ready/Busy Line Selection */
-#define SMCCS_TIMINGS_RBNSEL_MASK (7 << SMCCS_TIMINGS_RBNSEL_SHIFT)
-#define SMCCS_TIMINGS_NFSEL (1 << 31) /* Bit 31: NAND Flash Selection */
-
-/* SMC Mode Register */
-
-#define SMCCS_MODE_READMODE (1 << 0) /* Bit 0: Read mode */
-#define SMCCS_MODE_WRITEMODE (1 << 1) /* Bit 1: Write mode */
-#define SMCCS_MODE_EXNWMODE_SHIFT (4) /* Bits 4-5: NWAIT Mode */
-#define SMCCS_MODE_EXNWMODE_MASK (3 << SMCCS_MODE_EXNWMODE_SHIFT)
-# define SMCCS_EXNWMODE_DISABLED (0 << SMCCS_MODE_EXNWMODE_SHIFT)
-# define SMCCS_EXNWMODE_FROZEN (2 << SMCCS_MODE_EXNWMODE_SHIFT)
-# define SMCCS_EXNWMODE_READY (3 << SMCCS_MODE_EXNWMODE_SHIFT)
-#define SMCCS_MODE_BAT (1 << 8) /* Bit 8: Byte Access Type */
-#define SMCCS_MODE_DBW_SHIFT (12) /* Bits 12-13: Data Bus Width */
-#define SMCCS_MODE_DBW_MASK (3 << SMCCS_MODE_DBW_SHIFT)
-# define SMCCS_MODE_DBW_8BITS (0 << 12) /* 8 bits */
-# define SMCCS_MODE_DBW_16BITS (1 << 12) /* 16 bits */
-# define SMCCS_MODE_DBW_32BITS (2 << 12) /* 32 bits */
-#define SMCCS_MODE_TDFCYCLES_SHIFT (16) /* Bits 16-19: Data Float Time */
-#define SMCCS_MODE_TDFCYCLES_MASK (15 << SMCCS_MODE_TDFCYCLES_SHIFT)
-#define SMCCS_MODE_TDFMODE (1 << 20) /* Bit 20: TDF Optimization */
-#define SMCCS_MODE_PMEN (1 << 24) /* Bit 24: Page Mode Enabled */
-#define SMCCS_MODE_PS_SHIFT (28) /* Bits 28-29: Page Size */
-#define SMCCS_MODE_PS_MASK (3 << SMCCS_MODE_PS_SHIFT)
-# define SMCCS_MODE_PS_SIZE_4BYTES (0 << SMCCS_MODE_PS_SHIFT) /* 4 bytes */
-# define SMCCS_MODE_PS_SIZE_8BYTES (1 << SMCCS_MODE_PS_SHIFT) /* 8 bytes */
-# define SMCCS_MODE_PS_SIZE_16BYTES (2 << SMCCS_MODE_PS_SHIFT) /* 16 bytes */
-# define SMCCS_MODE_PS_SIZE_32BYTES (3 << SMCCS_MODE_PS_SHIFT) /* 32 bytes */
-
-/* SMC OCMS Register */
-
-#define SMC_OCMS_SMSE (1 << 0) /* Bit 0: Static Memory Controller Scrambling Enable */
-#define SMC_OCMS_SRSE (1 << 1) /* Bit 1: SRAM Scrambling Enable */
-
-/* SMC Write Protection Control */
-
-#define SMC_WPCR_WPPEN (1 << 9) /* Bit 9: Write Protection Enable */
-#define SMC_WPCR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protection KEY password */
-#define SMC_WPCR_WPKEY_MASK (0x00ffffff << SMC_WPCR_WPKEY_SHIFT)
-
-/* SMC Write Protection Status */
-
-#define SMC_WPSR_PVS_SHIFT (0) /* Bits 0-3: Write Protection Violation Status */
-#define SMC_WPSR_PVS_MASK (15 << SMC_WPSR_PVS_SHIFT)
-# define SMC_WPSR_PVS_NONE (0 << SMC_WPSR_PVS_SHIFT) /* No Write Protection Violation */
-# define SMC_WPSR_PVS_ RCREG (1 << SMC_WPSR_PVS_SHIFT) /* Attempt to write a control reg */
-# define SMC_WPSR_PVS_RESET (2 << SMC_WPSR_PVS_SHIFT) /* Software reset */
-# define SMC_WPSR_PVS_BOTH (3 << SMC_WPSR_PVS_SHIFT) /* Write + reset */
-#define SMC_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protection Violation Source */
-#define SMC_WPSR_WPVSRC_MASK (0xffff << SMC_WPSR_WPVSRC_SHIFT)
-
-/****************************************************************************************
- * Public Types
- ****************************************************************************************/
-
-/****************************************************************************************
- * Public Data
- ****************************************************************************************/
-
-/****************************************************************************************
- * Public Functions
- ****************************************************************************************/
-
-#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_SMC_H */
+/**************************************************************************************** + * arch/arm/src/sam3u/sam3u_smc.h + * + * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_SMC_H +#define __ARCH_ARM_SRC_SAM3U_SAM3U_SMC_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +#include <nuttx/config.h> + +#include "chip.h" +#include "sam3u_memorymap.h" + +/**************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************/ + +/* SMC register offsets *****************************************************************/ + +#define SAM3U_SMC_CFG_OFFSET 0x000 /* SMC NFC Configuration Register */ +#define SAM3U_SMC_CTRL_OFFSET 0x004 /* SMC NFC Control Register */ +#define SAM3U_SMC_SR_OFFSET 0x008 /* SMC NFC Status Register */ +#define SAM3U_SMC_IER_OFFSET 0x00c /* SMC NFC Interrupt Enable Register */ +#define SAM3U_SMC_IDR_OFFSET 0x010 /* SMC NFC Interrupt Disable Register */ +#define SAM3U_SMC_IMR_OFFSET 0x014 /* SMC NFC Interrupt Mask Register */ +#define SAM3U_SMC_ADDR_OFFSET 0x018 /* SMC NFC Address Cycle Zero Register */ +#define SAM3U_SMC_BANK_OFFSET 0x01c /* SMC Bank Address Register */ +#define SAM3U_SMC_ECCCTRL_OFFSET 0x020 /* SMC ECC Control Register */ +#define SAM3U_SMC_ECCMD_OFFSET 0x024 /* SMC ECC Mode Register */ +#define SAM3U_SMC_ECCSR1_OFFSET 0x028 /* SMC ECC Status 1 Register */ +#define SAM3U_SMC_ECCPR0_OFFSET 0x02c /* SMC ECC parity 0 Register */ +#define SAM3U_SMC_ECCPR1_OFFSET 0x030 /* SMC ECC parity 1 Register */ +#define SAM3U_SMC_ECCSR2_OFFSET 0x034 /* SMC ECC status 2 Register */ +#define SAM3U_SMC_ECCPR2_OFFSET 0x038 /* SMC ECC parity 2 Register */ +#define SAM3U_SMC_ECCPR3_OFFSET 0x03c /* SMC ECC parity 3 Register */ +#define SAM3U_SMC_ECCPR4_OFFSET 0x040 /* SMC ECC parity 4 Register */ +#define SAM3U_SMC_ECCPR5_OFFSET 0x044 /* SMC ECC parity 5 Register */ +#define SAM3U_SMC_ECCPR6_OFFSET 0x048 /* SMC ECC parity 6 Register */ +#define SAM3U_SMC_ECCPR7_OFFSET 0x04c /* SMC ECC parity 7 Register */ +#define SAM3U_SMC_ECCPR8_OFFSET 0x050 /* SMC ECC parity 8 Register */ +#define SAM3U_SMC_ECCPR9_OFFSET 0x054 /* SMC ECC parity 9 Register */ +#define SAM3U_SMC_ECCPR10_OFFSET 0x058 /* SMC ECC parity 10 Register */ +#define SAM3U_SMC_ECCPR11_OFFSET 0x05c /* SMC ECC parity 11 Register */ +#define SAM3U_SMC_ECCPR12_OFFSET 0x060 /* SMC ECC parity 12 Register */ +#define SAM3U_SMC_ECCPR13_OFFSET 0x064 /* SMC ECC parity 13 Register */ +#define SAM3U_SMC_ECCPR14_OFFSET 0x068 /* SMC ECC parity 14 Register */ +#define SAM3U_SMC_ECCPR15_OFFSET 0x06c /* SMC ECC parity 15 Register */ + +#define SAM3U_SMCCS_OFFSET(n) (0x070+((n)*0x014)) +#define SAM3U_SMCCS_SETUP_OFFSET 0x000 /* SMC SETUP Register */ +#define SAM3U_SMCCS_PULSE_OFFSET 0x004 /* SMC PULSE Register */ +#define SAM3U_SMCCS_CYCLE_OFFSET 0x008 /* SMC CYCLE Register */ +#define SAM3U_SMCCS_TIMINGS_OFFSET 0x00c /* SMC TIMINGS Register */ +#define SAM3U_SMCCS_MODE_OFFSET 0x010 /* SMC MODE Register */ + +#define SAM3U_SMC_OCMS_OFFSET 0x110 /* SMC OCMS MODE Register */ +#define SAM3U_SMC_KEY1_OFFSET 0x114 /* SMC KEY1 Register */ +#define SAM3U_SMC_KEY2_OFFSET 0x118 /* SMC KEY2 Register */ +#define SAM3U_SMC_WPCR_OFFSET 0x1e4 /* Write Protection Control Register */ +#define SAM3U_SMC_WPSR_OFFSET 0x1e8 /* Write Protection Status Register */ + +/* SMC register adresses ****************************************************************/ + +#define SAM3U_SMC_CFG (SAM3U_SMC_BASE+SAM3U_SMC_CFG_OFFSET) +#define SAM3U_SMC_CTRL (SAM3U_SMC_BASE+SAM3U_SMC_CTRL_OFFSET) +#define SAM3U_SMC_SR (SAM3U_SMC_BASE+SAM3U_SMC_SR_OFFSET) +#define SAM3U_SMC_IER (SAM3U_SMC_BASE+SAM3U_SMC_IER_OFFSET) +#define SAM3U_SMC_IDR (SAM3U_SMC_BASE+SAM3U_SMC_IDR_OFFSET) +#define SAM3U_SMC_IMR (SAM3U_SMC_BASE+SAM3U_SMC_IMR_OFFSET) +#define SAM3U_SMC_ADDR (SAM3U_SMC_BASE+SAM3U_SMC_ADDR_OFFSET) +#define SAM3U_SMC_BANK (SAM3U_SMC_BASE+SAM3U_SMC_BANK_OFFSET) +#define SAM3U_SMC_ECCCTRL (SAM3U_SMC_BASE+SAM3U_SMC_ECCCTRL_OFFSET) +#define SAM3U_SMC_ECCMD (SAM3U_SMC_BASE+SAM3U_SMC_ECCMD_OFFSET) +#define SAM3U_SMC_ECCSR1 (SAM3U_SMC_BASE+SAM3U_SMC_ECCSR1_OFFSET) +#define SAM3U_SMC_ECCPR0 (SAM3U_SMC_BASE+SAM3U_SMC_ECCPR0_OFFSET) +#define SAM3U_SMC_ECCPR1 (SAM3U_SMC_BASE+SAM3U_SMC_ECCPR1_OFFSET) +#define SAM3U_SMC_ECCSR2 (SAM3U_SMC_BASE+SAM3U_SMC_ECCSR2_OFFSET) +#define SAM3U_SMC_ECCPR2 (SAM3U_SMC_BASE+SAM3U_SMC_ECCPR2_OFFSET) +#define SAM3U_SMC_ECCPR3 (SAM3U_SMC_BASE+SAM3U_SMC_ECCPR3_OFFSET) +#define SAM3U_SMC_ECCPR4 (SAM3U_SMC_BASE+SAM3U_SMC_ECCPR4_OFFSET) +#define SAM3U_SMC_ECCPR5 (SAM3U_SMC_BASE+SAM3U_SMC_ECCPR5_OFFSET) +#define SAM3U_SMC_ECCPR6 (SAM3U_SMC_BASE+SAM3U_SMC_ECCPR6_OFFSET) +#define SAM3U_SMC_ECCPR7 (SAM3U_SMC_BASE+SAM3U_SMC_ECCPR7_OFFSET) +#define SAM3U_SMC_ECCPR8 (SAM3U_SMC_BASE+SAM3U_SMC_ECCPR8_OFFSET) +#define SAM3U_SMC_ECCPR9 (SAM3U_SMC_BASE+SAM3U_SMC_ECCPR9_OFFSET) +#define SAM3U_SMC_ECCPR10 (SAM3U_SMC_BASE+SAM3U_SMC_ECCPR10_OFFSET) +#define SAM3U_SMC_ECCPR11 (SAM3U_SMC_BASE+SAM3U_SMC_ECCPR11_OFFSET) +#define SAM3U_SMC_ECCPR12 (SAM3U_SMC_BASE+SAM3U_SMC_ECCPR12_OFFSET) +#define SAM3U_SMC_ECCPR13 (SAM3U_SMC_BASE+SAM3U_SMC_ECCPR13_OFFSET) +#define SAM3U_SMC_ECCPR14 (SAM3U_SMC_BASE+SAM3U_SMC_ECCPR14_OFFSET) +#define SAM3U_SMC_ECCPR15 (SAM3U_SMC_BASE+SAM3U_SMC_ECCPR15_OFFSET) + +#define SAM3U_SMCCS_BASE(n) (SAM3U_SMC_BASE+SAM3U_SMCCS_OFFSET(n)) +# define SAM3U_SMC_CS0_BASE (SAM3U_SMC_BASE+SAM3U_SMCCS_OFFSET(0)) +# define SAM3U_SMC_CS1_BASE (SAM3U_SMC_BASE+SAM3U_SMCCS_OFFSET(1)) +# define SAM3U_SMC_CS2_BASE (SAM3U_SMC_BASE+SAM3U_SMCCS_OFFSET(2)) +# define SAM3U_SMC_CS3_BASE (SAM3U_SMC_BASE+SAM3U_SMCCS_OFFSET(3)) +#define SAM3U_SMCCS_SETUP(n) (SAM3U_SMCCS_BASE(n)+SAM3U_SMCCS_SETUP_OFFSET) +#define SAM3U_SMCCS_PULSE(n) (SAM3U_SMCCS_BASE(n)+SAM3U_SMCCS_PULSE_OFFSET) +#define SAM3U_SMCCS_CYCLE(n) (SAM3U_SMCCS_BASE(n)+SAM3U_SMCCS_CYCLE_OFFSET) +#define SAM3U_SMCCS_TIMINGS(n) (SAM3U_SMCCS_BASE(n)+SAM3U_SMCCS_TIMINGS_OFFSET) +#define SAM3U_SMCCS_MODE(n) (SAM3U_SMCCS_BASE(n)+SAM3U_SMCCS_MODE_OFFSET) + +#define SAM3U_SMC_OCMS (SAM3U_SMC_BASE+SAM3U_SMC_OCMS_OFFSET) +#define SAM3U_SMC_KEY1 (SAM3U_SMC_BASE+SAM3U_SMC_KEY1_OFFSET) +#define SAM3U_SMC_KEY2 (SAM3U_SMC_BASE+SAM3U_SMC_KEY2_OFFSET) +#define SAM3U_SMC_WPCR (SAM3U_SMC_BASE+SAM3U_SMC_WPCR_OFFSET) +#define SAM3U_SMC_WPSR (SAM3U_SMC_BASE+SAM3U_SMC_WPSR_OFFSET) + +/* SMC register bit definitions *********************************************************/ + +/* SMC NFC Configuration Register */ + +#define SMC_CFG_PAGESIZE_SHIFT (0) /* Bits 0-1: Page size of NAND Flash device */ +#define SMC_CFG_PAGESIZE_MASK (3 << SMC_CFG_PAGESIZE_SHIFT) +# define SMC_CFG_PAGESIZE_16 BYTES (0 << SMC_CFG_PAGESIZE_SHIFT) /* 528 Bytes 16 byte */ +# define SMC_CFG_PAGESIZE_ 2 BYTES (1 << SMC_CFG_PAGESIZE_SHIFT) /* 1056 Bytes 32 bytes */ +# define SMC_CFG_PAGESIZE_64 BYTES (2 << SMC_CFG_PAGESIZE_SHIFT) /* 2112 Bytes 64 bytes */ +# define SMC_CFG_PAGESIZE_128 BYTES (3 << SMC_CFG_PAGESIZE_SHIFT) /* 4224 Bytes 128 bytes */ +#define SMC_CFG_WSPARE (1 << 8) /* Bit 8: Write Spare Area */ +#define SMC_CFG_RSPARE (1 << 9) /* Bit 9: Read Spare Area */ +#define SMC_CFG_EDGECTRL (1 << 12) /* Bit 12: Rising/Falling Edge Detection Control */ +#define SMC_CFG_RBEDGE (1 << 13) /* Bit 13: Ready/Busy Signal Edge Detection */ +#define SMC_CFG_DTOCYC_SHIFT (16) /* Bits 16-19: Data Timeout Cycle Number */ +#define SMC_CFG_DTOCYC_MASK (15 << SMC_CFG_DTOCYC_SHIFT) +#define SMC_CFG_DTOMUL_SHIFT (20) /* Bits 20-22: Data Timeout Multiplier */ +#define SMC_CFG_DTOMUL_MASK (7 << SMC_CFG_DTOMUL_SHIFT) +# define SMC_CFG_DTOMUL_1 (0 << SMC_CFG_DTOMUL_SHIFT) +# define SMC_CFG_DTOMUL_16 (1 << SMC_CFG_DTOMUL_SHIFT) +# define SMC_CFG_DTOMUL_128 (2 << SMC_CFG_DTOMUL_SHIFT) +# define SMC_CFG_DTOMUL_256 (3 << SMC_CFG_DTOMUL_SHIFT) +# define SMC_CFG_DTOMUL_1024 (4 << SMC_CFG_DTOMUL_SHIFT) +# define SMC_CFG_DTOMUL_4096 (5 << SMC_CFG_DTOMUL_SHIFT) +# define SMC_CFG_DTOMUL_65536 (6 << SMC_CFG_DTOMUL_SHIFT) +# define SMC_CFG_DTOMUL_1048576 (7 << SMC_CFG_DTOMUL_SHIFT) + +/* SMC NFC Control Register */ + +#define SMC_CTRL_NFCEN (1 << 0) /* Bit 0: NAND Flash Controller Enable */ +#define SMC_CTRL_NFCDIS (1 << 1) /* Bit 1: NAND Flash Controller Disable */ + +/* SMC NFC Status Register, SMC NFC Interrupt Enable Register, SMC NFC Interrupt + * Disable Register, and SMC NFC Interrupt Mask Register common bit-field definitions + */ + +#define SMC_SR_SMCSTS (1 << 0) /* Bit 0: NAND Flash Controller status (SR only) */ +#define SMC_INT_RBRISE (1 << 4) /* Bit 4: Ready Busy Rising Edge Detection Interrupt */ +#define SMC_INT_RBFALL (1 << 5) /* Bit 5: Ready Busy Falling Edge Detection Interrupt */ +#define SMC_SR_NFCBUSY (1 << 8) /* Bit 8: NFC Busy (SR only) */ +#define SMC_SR_NFCWR (1 << 11) /* Bit 11: NFC Write/Read Operation (SR only) */ +#define SMC_SR_NFCSID (1 << 12) /* Bit 13: NFC Chip Select ID (SR only) */ +#define SMC_INT_XFRDONE (1 << 16) /* Bit 16: Transfer Done Interrupt */ +#define SMC_INT_CMDDONE (1 << 17) /* Bit 17: Command Done Interrupt */ +#define SMC_INT_DTOE (1 << 20) /* Bit 20: Data Timeout Error Interrupt */ +#define SMC_INT_UNDEF (1 << 21) /* Bit 21: Undefined Area Access Interrupt */ +#define SMC_INT_AWB (1 << 22) /* Bit 22: Accessing While Busy Interrupt */ +#define SMC_INT_NFCASE (1 << 23) /* Bit 23: NFC Access Size Error Interrupt */ +#define SMC_INT_RBEDGE(n) (1<<((n)+24)) +#define SMC_INT_RB_EDGE0 (1 << 24) /* Bit 24: Ready/Busy Line 0 Interrupt */ +#define SMC_INT_RB_EDGE1 (1 << 25) /* Bit 25: Ready/Busy Line 1 Interrupt */ +#define SMC_INT_RB_EDGE2 (1 << 26) /* Bit 26: Ready/Busy Line 2 Interrupt */ +#define SMC_INT_RB_EDGE3 (1 << 27) /* Bit 27: Ready/Busy Line 3 Interrupt */ +#define SMC_INT_RB_EDGE4 (1 << 28) /* Bit 28: Ready/Busy Line 4 Interrupt */ +#define SMC_INT_RB_EDGE5 (1 << 29) /* Bit 29: Ready/Busy Line 5 Interrupt */ +#define SMC_INT_RB_EDGE6 (1 << 30) /* Bit 30: Ready/Busy Line 6 Interrupt */ +#define SMC_INT_RB_EDGE7 (1 << 31) /* Bit 31: Ready/Busy Line 7 Interrupt */ + +/* SMC NFC Address Cycle Zero Register */ + +#define SMC_ADDR_ADDR_CYCLE0_SHIFT (3) /* Bits 0-7: NAND Flash Array Address cycle 0 */ +#define SMC_ADDR_ADDR_CYCLE0_SHIFT (3) /* Bits 0-7: NAND Flash Array Address cycle 0 */ + +/* SMC NFC Bank Register */ + +#define SMC_BANK_SHIFT (0) /* Bits 0-2: Bank identifier */ +#define SMC_BANK_MASK (7 << SMC_BANK_SHIFT) + +/* SMC ECC Control Register */ + +#define SMC_ECCCTRL_RST (1 << 0) /* Bit 0: Reset ECC */ +#define SMC_ECCCTRL_SWRST (1 << 1) /* Bit 1: Software Reset */ + +/* SMC ECC MODE Register */ + +#define SMC_ECCMD_ECC_PAGESIZE_SHIFT (0) /* Bits 0-1 */ +#define SMC_ECCMD_ECC_PAGESIZE_MASK (3 << SMC_ECCMD_ECC_PAGESIZE_SHIFT) +# define SMC_ECCMD_ECC_PAGESIZE_528 (0 << SMC_ECCMD_ECC_PAGESIZE_SHIFT) +# define SMC_ECCMD_ECC_PAGESIZE_1056 (1 << SMC_ECCMD_ECC_PAGESIZE_SHIFT) +# define SMC_ECCMD_ECC_PAGESIZE_2112 (2 << SMC_ECCMD_ECC_PAGESIZE_SHIFT) +# define SMC_ECCMD_ECC_PAGESIZE_4224 (3 << SMC_ECCMD_ECC_PAGESIZE_SHIFT) +#define SMC_ECCMD_TYPCORREC_SHIFT (4) /* Bits 4-5: type of correction */ +#define SMC_ECCMD_TYPCORREC_MASK (3 << SMC_ECCMD_TYPCORREC_SHIFT) +# define SMC_ECCMD_TYPCORREC_PAGE (0 << SMC_ECCMD_TYPCORREC_SHIFT) /* 1 bit correction for a page */ +# define SMC_ECCMD_TYPCORREC_256 (1 << SMC_ECCMD_TYPCORREC_SHIFT) /* 1 bit correction for 256 bytes */ +# define SMC_ECCMD_TYPCORREC_512 (2 << SMC_ECCMD_TYPCORREC_SHIFT) /* 1 bit correction for 512 bytes */ + +/* SMC ECC Status Register 1 */ + +#define _RECERR (0) /* Recoverable Error */ +#define _ECCERR (1) /* ECC Error */ +#define _MULERR (2) /* Multiple Error */ + +#define SMC_ECCSR1_RECERR(n) (1 << (((n)<<4)+_RECERR)) +#define SMC_ECCSR1_ECCERR(n) (1 << (((n)<<4)+_ECCERR)) +#define SMC_ECCSR1_MULERR(n) (1 << (((n)<<4)+_MULERR)) + +#define SMC_ECCSR1_RECERR0 SMC_ECCSR1_RECERR(0) +#define SMC_ECCSR1_ECCERR0 SMC_ECCSR1_ECCERR(0) +#define SMC_ECCSR1_MULERR0 SMC_ECCSR1_MULERR(0) +#define SMC_ECCSR1_RECERR1 SMC_ECCSR1_RECERR(1) +#define SMC_ECCSR1_ECCERR1 SMC_ECCSR1_ECCERR(1) +#define SMC_ECCSR1_MULERR1 SMC_ECCSR1_MULERR(1) +#define SMC_ECCSR1_RECERR2 SMC_ECCSR1_RECERR(2) +#define SMC_ECCSR1_ECCERR2 SMC_ECCSR1_ECCERR(2) +#define SMC_ECCSR1_MULERR2 SMC_ECCSR1_MULERR(2) +#define SMC_ECCSR1_RECERR3 SMC_ECCSR1_RECERR(3) +#define SMC_ECCSR1_ECCERR3 SMC_ECCSR1_ECCERR(3) +#define SMC_ECCSR1_MULERR3 SMC_ECCSR1_MULERR(3) +#define SMC_ECCSR1_RECERR4 SMC_ECCSR1_RECERR(4) +#define SMC_ECCSR1_ECCERR4 SMC_ECCSR1_ECCERR(4) +#define SMC_ECCSR1_MULERR4 SMC_ECCSR1_MULERR(4) +#define SMC_ECCSR1_RECERR5 SMC_ECCSR1_RECERR(5) +#define SMC_ECCSR1_ECCERR5 SMC_ECCSR1_ECCERR(5) +#define SMC_ECCSR1_MULERR5 SMC_ECCSR1_MULERR(5) +#define SMC_ECCSR1_RECERR6 SMC_ECCSR1_RECERR(6) +#define SMC_ECCSR1_ECCERR6 SMC_ECCSR1_ECCERR(6) +#define SMC_ECCSR1_MULERR6 SMC_ECCSR1_MULERR(6) +#define SMC_ECCSR1_RECERR7 SMC_ECCSR1_RECERR(7) +#define SMC_ECCSR1_ECCERR7 SMC_ECCSR1_ECCERR(7) +#define SMC_ECCSR1_MULERR7 SMC_ECCSR1_MULERR(7) + +/* SMC ECC Status Register 2 */ + +#define SMC_ECCSR2_RECERR(n) (1 << ((((n)-8)<<4)+_RECERR)) +#define SMC_ECCSR2_ECCERR(n) (1 << ((((n)-8)<<4)+_ECCERR)) +#define SMC_ECCSR2_MULERR(n) (1 << ((((n)-8)<<4)+_MULERR)) + +#define SMC_ECCSR2_RECERR8 SMC_ECCSR2_RECERR(8) +#define SMC_ECCSR2_ECCERR8 SMC_ECCSR2_ECCERR(8) +#define SMC_ECCSR2_MULERR8 SMC_ECCSR2_MULERR(8) +#define SMC_ECCSR2_RECERR9 SMC_ECCSR2_RECERR(9) +#define SMC_ECCSR2_ECCERR9 SMC_ECCSR2_ECCERR(9) +#define SMC_ECCSR2_MULERR9 SMC_ECCSR2_MULERR(9) +#define SMC_ECCSR2_RECERR10 SMC_ECCSR2_RECERR(10) +#define SMC_ECCSR2_ECCERR10 SMC_ECCSR2_ECCERR(10) +#define SMC_ECCSR2_MULERR10 SMC_ECCSR2_MULERR(10) +#define SMC_ECCSR2_RECERR11 SMC_ECCSR2_RECERR(11) +#define SMC_ECCSR2_ECCERR11 SMC_ECCSR2_ECCERR(11) +#define SMC_ECCSR2_MULERR11 SMC_ECCSR2_MULERR(11) +#define SMC_ECCSR2_RECERR12 SMC_ECCSR2_RECERR(12) +#define SMC_ECCSR2_ECCERR12 SMC_ECCSR2_ECCERR(12) +#define SMC_ECCSR2_MULERR12 SMC_ECCSR2_MULERR(12) +#define SMC_ECCSR2_RECERR13 SMC_ECCSR2_RECERR(13) +#define SMC_ECCSR2_ECCERR13 SMC_ECCSR2_ECCERR(13) +#define SMC_ECCSR2_MULERR13 SMC_ECCSR2_MULERR(13) +#define SMC_ECCSR1_RECERR14 SMC_ECCSR2_RECERR(14) +#define SMC_ECCSR1_ECCERR14 SMC_ECCSR2_ECCERR(14) +#define SMC_ECCSR1_MULERR14 SMC_ECCSR2_MULERR(14) +#define SMC_ECCSR1_RECERR15 SMC_ECCSR2_RECERR(15) +#define SMC_ECCSR1_ECCERR15 SMC_ECCSR2_ECCERR(15) +#define SMC_ECCSR1_MULERR15 SMC_ECCSR2_MULERR(15) + +/* Registers for 1 ECC for a page of 512/1024/2048/4096 bytes */ +/* SMC_ECC_PR0 */ + +#define SMC_ECCPR0_BITADDR_SHIFT (0) /* Bits 0-3: Bit Address */ +#define SMC_ECCPR0_BITADDR_MASK (15 << SMC_ECCPR0_BITADDR_SHIFT) +#define SMC_ECCPR0_WORDADDR_SHIFT (4) /* Bits 4-15: Word Address */ +#define SMC_ECCPR0_WORDADDR_MASK (0xfff << SMC_ECCPR0_WORDADDR_SHIFT) + +#define SMC_ECCPR1_NPARITY_SHIFT (0) /* Bits 0-15 */ +#define SMC_ECCPR1_NPARITY_MASK (0xffff << SMC_ECCPR1_NPARITY_SHIFT) + +/* Registers for 1 ECC per 512 bytes for a page of 512/2048/4096 bytes, 8-bit word */ + +#define SMC_ECCPR512_BITADDR_SHIFT (0) /* Bits 0-3: Bit Address */ +#define SMC_ECCPR512_BITADDR_MASK (15 << SMC_ECCPR512_BITADDR_SHIFT) +#define SMC_ECCPR512_WORDADDR_SHIFT (4) /* Bits 4-15: Word Address */ +#define SMC_ECCPR512_WORDADDR_MASK (0xfff << SMC_ECCPR512_WORDADDR_SHIFT) +#define SMC_ECCPR512_NPARITY_SHIFT (12) /* Bits 12-23 (or is it 31?) */ +#define SMC_ECCPR512_NPARITY_MASK (0xfff << SMC_ECCPR512_NPARITY_SHIFT) + +/* Registers for 1 ECC per 256 bytes for a page of 512/2048/4096 bytes, 8-bit word */ + +#define SMC_ECCPR256_BITADDR_SHIFT (0) /* Bits 0-2: Bit Address */ +#define SMC_ECCPR256_BITADDR_MASK (7 << SMC_ECCPR256_BITADDR_SHIFT) +#define SMC_ECCPR256_WORDADDR_SHIFT (4) /* Bits 4-10: Word Address */ +#define SMC_ECCPR256_WORDADDR_MASK (0x7f << SMC_ECCPR256_WORDADDR_SHIFT) +#define SMC_ECCPR256_NPARITY_SHIFT (12) /* Bits 12-22 */ +#define SMC_ECCPR256_NPARITY_MASK (0x7ff << SMC_ECCPR256_NPARITY_SHIFT) + +/* SMC Setup Register */ + +#define SMCCS_SETUP_NWESETUP_SHIFT (0) /* Bits 0-5: NWE Setup length */ +#define SMCCS_SETUP_NWESETUP_MASK (63 << SMCCS_SETUP_NWESETUP_SHIFT) +#define SMCCS_SETUP_NCSWRSETUP_SHIFT (8) /* Bits 8-13: NCS Setup length in Write access */ +#define SMCCS_SETUP_NCSWRSETUP_MASK (63 << SMCCS_SETUP_NCSWRSETUP_SHIFT) +#define SMCCS_SETUP_NRDSETUP_SHIFT (16) /* Bits 16-21: NRD Setup length */ +#define SMCCS_SETUP_NRDSETUP_MASK (63 << SMCCS_SETUP_NRDSETUP_SHIFT) +#define SMCCS_SETUP_NCSRDSETUP_SHIFT (24) /* Bits 24-29: NCS Setup length in Read access */ +#define SMCCS_SETUP_NCSRDSETUP_MASK (63 << SMCCS_SETUP_NCSRDSETUP_SHIFT) + +/* SMC Pulse Register */ + +#define SMCCS_PULSE_NWEPULSE_SHIFT (0) /* Bits 0-5: NWE Pulse Length */ +#define SMCCS_PULSE_NWEPULSE_MASK (63 << SMCCS_PULSE_NWEPULSE_SHIFT) +#define SMCCS_PULSE_NCSWRPULSE_SHIFT (8) /* Bits 8-13: NCS Pulse Length in WRITE Access */ +#define SMCCS_PULSE_NCSWRPULSE_MASK (63 << SMCCS_PULSE_NCSWRPULSE_SHIFT) +#define SMCCS_PULSE_RDPULSE_SHIFT (16) /* Bits 16-21: NRD Pulse Length */ +#define SMCCS_PULSE_RDPULSE_MASK (63 << SMCCS_PULSE_RDPULSE_SHIFT) +#define SMCCS_PULSE_NCSRDPULSE_SHIFT (24) /* Bits 24-29: NCS Pulse Length in READ Access */ +#define SMCCS_PULSE_NCSRDPULSE_MASK (63 << SMCCS_PULSE_NCSRDPULSE_SHIFT) + +/* SMC Cycle Register */ + +#define SMCCS_CYCLE_NWECYCLE_SHIFT (0) /* Bits 0-8: Total Write Cycle Length */ +#define SMCCS_CYCLE_NWECYCLE_MASK (0x1ff << SMCCS_CYCLE_NWECYCLE_SHIFT) +#define SMCCS_CYCLE_NRDCYCLE_SHIFT (16) /* Bits 16-24: Total Read Cycle Length */ +#define SMCCS_CYCLE_NRDCYCLE_MASK (0x1ff << SMCCS_CYCLE_NRDCYCLE_SHIFT) + +/* SMC Timings Register */ + +#define SMCCS_TIMINGS_TCLR_SHIFT (0) /* Bits 0-3: CLE to REN Low Delay */ +#define SMCCS_TIMINGS_TCLR_MASK (15 << SMCCS_TIMINGS_TCLR_SHIFT) +#define SMCCS_TIMINGS_TADL_SHIFT (4) /* Bits 4-7: ALE to Data Start */ +#define SMCCS_TIMINGS_TADL_MASK (15 << SMCCS_TIMINGS_TADL_SHIFT) +#define SMCCS_TIMINGS_TAR_SHIFT (8) /* Bits 8-11: ALE to REN Low Delay */ +#define SMCCS_TIMINGS_TAR_MASK (15 << SMCCS_TIMINGS_TAR_SHIFT) +#define SMCCS_TIMINGS_OCMS (1 << 12) /* Bit 12: Off Chip Memory Scrambling Enable */ +#define SMCCS_TIMINGS_TRR_SHIFT (16) /* Bits 16-19: Ready to REN Low Delay */ +#define SMCCS_TIMINGS_TRR_MASK (15 << SMCCS_TIMINGS_TRR_SHIFT) +#define SMCCS_TIMINGS_TWB_SHIFT (24) /* Bits 24-27: WEN High to REN to Busy */ +#define SMCCS_TIMINGS_TWB_MASK (15 << SMCCS_TIMINGS_TWB_SHIFT) +#define SMCCS_TIMINGS_RBNSEL_SHIFT (28) /* Bits 28-30: Ready/Busy Line Selection */ +#define SMCCS_TIMINGS_RBNSEL_MASK (7 << SMCCS_TIMINGS_RBNSEL_SHIFT) +#define SMCCS_TIMINGS_NFSEL (1 << 31) /* Bit 31: NAND Flash Selection */ + +/* SMC Mode Register */ + +#define SMCCS_MODE_READMODE (1 << 0) /* Bit 0: Read mode */ +#define SMCCS_MODE_WRITEMODE (1 << 1) /* Bit 1: Write mode */ +#define SMCCS_MODE_EXNWMODE_SHIFT (4) /* Bits 4-5: NWAIT Mode */ +#define SMCCS_MODE_EXNWMODE_MASK (3 << SMCCS_MODE_EXNWMODE_SHIFT) +# define SMCCS_EXNWMODE_DISABLED (0 << SMCCS_MODE_EXNWMODE_SHIFT) +# define SMCCS_EXNWMODE_FROZEN (2 << SMCCS_MODE_EXNWMODE_SHIFT) +# define SMCCS_EXNWMODE_READY (3 << SMCCS_MODE_EXNWMODE_SHIFT) +#define SMCCS_MODE_BAT (1 << 8) /* Bit 8: Byte Access Type */ +#define SMCCS_MODE_DBW_SHIFT (12) /* Bits 12-13: Data Bus Width */ +#define SMCCS_MODE_DBW_MASK (3 << SMCCS_MODE_DBW_SHIFT) +# define SMCCS_MODE_DBW_8BITS (0 << 12) /* 8 bits */ +# define SMCCS_MODE_DBW_16BITS (1 << 12) /* 16 bits */ +# define SMCCS_MODE_DBW_32BITS (2 << 12) /* 32 bits */ +#define SMCCS_MODE_TDFCYCLES_SHIFT (16) /* Bits 16-19: Data Float Time */ +#define SMCCS_MODE_TDFCYCLES_MASK (15 << SMCCS_MODE_TDFCYCLES_SHIFT) +#define SMCCS_MODE_TDFMODE (1 << 20) /* Bit 20: TDF Optimization */ +#define SMCCS_MODE_PMEN (1 << 24) /* Bit 24: Page Mode Enabled */ +#define SMCCS_MODE_PS_SHIFT (28) /* Bits 28-29: Page Size */ +#define SMCCS_MODE_PS_MASK (3 << SMCCS_MODE_PS_SHIFT) +# define SMCCS_MODE_PS_SIZE_4BYTES (0 << SMCCS_MODE_PS_SHIFT) /* 4 bytes */ +# define SMCCS_MODE_PS_SIZE_8BYTES (1 << SMCCS_MODE_PS_SHIFT) /* 8 bytes */ +# define SMCCS_MODE_PS_SIZE_16BYTES (2 << SMCCS_MODE_PS_SHIFT) /* 16 bytes */ +# define SMCCS_MODE_PS_SIZE_32BYTES (3 << SMCCS_MODE_PS_SHIFT) /* 32 bytes */ + +/* SMC OCMS Register */ + +#define SMC_OCMS_SMSE (1 << 0) /* Bit 0: Static Memory Controller Scrambling Enable */ +#define SMC_OCMS_SRSE (1 << 1) /* Bit 1: SRAM Scrambling Enable */ + +/* SMC Write Protection Control */ + +#define SMC_WPCR_WPPEN (1 << 9) /* Bit 9: Write Protection Enable */ +#define SMC_WPCR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protection KEY password */ +#define SMC_WPCR_WPKEY_MASK (0x00ffffff << SMC_WPCR_WPKEY_SHIFT) + +/* SMC Write Protection Status */ + +#define SMC_WPSR_PVS_SHIFT (0) /* Bits 0-3: Write Protection Violation Status */ +#define SMC_WPSR_PVS_MASK (15 << SMC_WPSR_PVS_SHIFT) +# define SMC_WPSR_PVS_NONE (0 << SMC_WPSR_PVS_SHIFT) /* No Write Protection Violation */ +# define SMC_WPSR_PVS_ RCREG (1 << SMC_WPSR_PVS_SHIFT) /* Attempt to write a control reg */ +# define SMC_WPSR_PVS_RESET (2 << SMC_WPSR_PVS_SHIFT) /* Software reset */ +# define SMC_WPSR_PVS_BOTH (3 << SMC_WPSR_PVS_SHIFT) /* Write + reset */ +#define SMC_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protection Violation Source */ +#define SMC_WPSR_WPVSRC_MASK (0xffff << SMC_WPSR_WPVSRC_SHIFT) + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +/**************************************************************************************** + * Public Data + ****************************************************************************************/ + +/**************************************************************************************** + * Public Functions + ****************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_SMC_H */ diff --git a/nuttx/arch/arm/src/sam3u/sam3u_ssc.h b/nuttx/arch/arm/src/sam3u/sam3u_ssc.h index d4f848c13..5a5df824b 100644 --- a/nuttx/arch/arm/src/sam3u/sam3u_ssc.h +++ b/nuttx/arch/arm/src/sam3u/sam3u_ssc.h @@ -1,292 +1,292 @@ -/****************************************************************************************
- * arch/arm/src/sam3u/sam3u_ssc.h
- *
- * Copyright (C) 2009 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_SSC_H
-#define __ARCH_ARM_SRC_SAM3U_SAM3U_SSC_H
-
-/****************************************************************************************
- * Included Files
- ****************************************************************************************/
-
-#include <nuttx/config.h>
-
-#include "chip.h"
-#include "sam3u_memorymap.h"
-
-/****************************************************************************************
- * Pre-processor Definitions
- ****************************************************************************************/
-
-/* SSC register offsets *****************************************************************/
-
-#define SAM3U_SSC_CR_OFFSET 0x000 /* Control Register */
-#define SAM3U_SSC_CMR_OFFSET 0x004 /* Clock Mode Register */
- /* 0x008: Reserved */
- /* 0x00c: Reserved */
-#define SAM3U_SSC_RCMR_OFFSET 0x010 /* Receive Clock Mode Register */
-#define SAM3U_SSC_RFMR_OFFSET 0x014 /* Receive Frame Mode Register */
-#define SAM3U_SSC_TCMR_OFFSET 0x018 /* Transmit Clock Mode Register */
-#define SAM3U_SSC_TFMR_OFFSET 0x01c /* Transmit Frame Mode Register */
-#define SAM3U_SSC_RHR_OFFSET 0x020 /* Receive Holding Register */
-#define SAM3U_SSC_THR_OFFSET 0x024 /* Transmit Holding Register */
- /* 0x028: Reserved */
- /* 0x02c: Reserved */
-#define SAM3U_SSC_RSHR_OFFSET 0x030 /* Receive Sync. Holding Register */
-#define SAM3U_SSC_TSHR_OFFSET 0x034 /* Transmit Sync. Holding Register */
-#define SAM3U_SSC_RC0R_OFFSET 0x038 /* Receive Compare 0 Register */
-#define SAM3U_SSC_RC1R_OFFSET 0x03c /* Receive Compare 1 Register */
-#define SAM3U_SSC_SR_OFFSET 0x040 /* Status Register */
-#define SAM3U_SSC_IER_OFFSET 0x044 /* Interrupt Enable Register */
-#define SAM3U_SSC_IDR_OFFSET 0x048 /* Interrupt Disable Register */
-#define SAM3U_SSC_IMR_OFFSET 0x04c /* Interrupt Mask Register */
-#define SAM3U_SSC_WPMR_OFFSET 0x0e4 /* Write Protect Mode Register */
-#define SAM3U_SSC_WPSR_OFFSET 0x0e8 /* Write Protect Status Register */
- /* 0x050-0x0fc: Reserved */
- /* 0x100-0x124: Reserved */
-
-/* SSC register adresses ****************************************************************/
-
-#define SAM3U_SSC_CR (SAM3U_SSC_BASE+SAM3U_SSC_CR_OFFSET)
-#define SAM3U_SSC_CMR (SAM3U_SSC_BASE+SAM3U_SSC_CMR_OFFSET)
-#define SAM3U_SSC_RCMR (SAM3U_SSC_BASE+SAM3U_SSC_RCMR_OFFSET)
-#define SAM3U_SSC_RFMR (SAM3U_SSC_BASE+SAM3U_SSC_RFMR_OFFSET)
-#define SAM3U_SSC_TCMR (SAM3U_SSC_BASE+SAM3U_SSC_TCMR_OFFSET)
-#define SAM3U_SSC_TFMR (SAM3U_SSC_BASE+SAM3U_SSC_TFMR_OFFSET)
-#define SAM3U_SSC_RHR (SAM3U_SSC_BASE+SAM3U_SSC_RHR_OFFSET)
-#define SAM3U_SSC_THR (SAM3U_SSC_BASE+SAM3U_SSC_THR_OFFSET)
-#define SAM3U_SSC_RSHR (SAM3U_SSC_BASE+SAM3U_SSC_RSHR_OFFSET)
-#define SAM3U_SSC_TSHR (SAM3U_SSC_BASE+SAM3U_SSC_TSHR_OFFSET)
-#define SAM3U_SSC_RC0R (SAM3U_SSC_BASE+SAM3U_SSC_RC0R_OFFSET)
-#define SAM3U_SSC_RC1R (SAM3U_SSC_BASE+SAM3U_SSC_RC1R_OFFSET)
-#define SAM3U_SSC_SR (SAM3U_SSC_BASE+SAM3U_SSC_SR_OFFSET)
-#define SAM3U_SSC_IER (SAM3U_SSC_BASE+SAM3U_SSC_IER_OFFSET)
-#define SAM3U_SSC_IDR (SAM3U_SSC_BASE+SAM3U_SSC_IDR_OFFSET)
-#define SAM3U_SSC_IMR (SAM3U_SSC_BASE+SAM3U_SSC_IMR_OFFSET)
-#define SAM3U_SSC_WPMR (SAM3U_SSC_BASE+SAM3U_SSC_WPMR_OFFSET)
-#define SAM3U_SSC_WPSR (SAM3U_SSC_BASE+SAM3U_SSC_WPSR_OFFSET)
-
-/* SSC register bit definitions *********************************************************/
-
-/* SSC Control Register */
-
-#define SSC_CR_RXEN (1 << 0) /* Bit 0: Receive Enable */
-#define SSC_CR_RXDIS (1 << 1) /* Bit 1: Receive Disable */
-#define SSC_CR_TXEN (1 << 8) /* Bit 8: Transmit Enable */
-#define SSC_CR_TXDIS (1 << 9) /* Bit 9: Transmit Disable */
-#define SSC_CR_SWRST (1 << 15) /* Bit 15: Software Reset */
-
-/* SSC Clock Mode Register */
-
-#define SSC_CMR_DIV_SHIFT (0) /* Bits 0-11: Clock Divider */
-#define SSC_CMR_DIV_MASK (0xfff << SSC_CMR_DIV_SHIFT)
-
-/* SSC Receive Clock Mode Register */
-
-#define SSC_RCMR_CKS_SHIFT (0) /* Bits 0-1: Receive Clock Selection */
-#define SSC_RCMR_CKS_MASK (3 << SSC_RCMR_CKS_SHIFT)
-# define SSC_RCMR_CKS_DIVIDED (0 << SSC_RCMR_CKS_SHIFT) /* Divided Clock */
-# define SSC_RCMR_CKS_TK (1 << SSC_RCMR_CKS_SHIFT) /* TK Clock signal */
-# define SSC_RCMR_CKS_RK (2 << SSC_RCMR_CKS_SHIFT) /* RK pin */
-#define SSC_RCMR_CKO_SHIFT (2) /* Bits 2-4: Receive Clock Output Mode Selection */
-#define SSC_RCMR_CKO_MASK (7 << SSC_RCMR_CKO_SHIFT)
-# define SSC_RCMR_CKO_ NONE (0 << SSC_RCMR_CKO_SHIFT) /* None */
-# define SSC_RCMR_CKO_CONTINUOUS (1 << SSC_RCMR_CKO_SHIFT) /* Continuous Receive Clock */
-# define SSC_RCMR_CKO_XFERS (2 << SSC_RCMR_CKO_SHIFT) /* Receive Clock only during data transfers */
-#define SSC_RCMR_CKI (1 << 5) /* Bit 5: Receive Clock Inversion */
-#define SSC_RCMR_CKG_SHIFT (6) /* Bits 6-7: Receive Clock Gating Selection */
-#define SSC_RCMR_CKG_MASK (3 << SSC_RCMR_CKG_SHIFT)
-# define SSC_RCMR_CKG_NONE (0 << SSC_RCMR_CKG_SHIFT) /* None, continuous clock */
-# define SSC_RCMR_CKG_RFLOW (1 << SSC_RCMR_CKG_SHIFT) /* Receive Clock enabled only if RF Low */
-# define SSC_RCMR_CKG_RFHIGH (2 << SSC_RCMR_CKG_SHIFT) /* Receive Clock enabled only if RF High */
-#define SSC_RCMR_START_SHIFT (8) /* Bits 8-11: Receive Start Selection */
-#define SSC_RCMR_START_MASK (15 << SSC_RCMR_START_SHIFT)
-# define SSC_RCMR_START_CONTINOUS (0 << SSC_RCMR_START_SHIFT) /* Continuous */
-# define SSC_RCMR_START_START (1 << SSC_RCMR_START_SHIFT) /* Transmit start */
-# define SSC_RCMR_START_RFLOW (2 << SSC_RCMR_START_SHIFT) /* Low level on RF signal */
-# define SSC_RCMR_START_RFHIGH (3 << SSC_RCMR_START_SHIFT) /* High level on RF signal */
-# define SSC_RCMR_START_RFFALL (4 << SSC_RCMR_START_SHIFT) /* Falling edge on RF signal */
-# define SSC_RCMR_START_RFRISE (5 << SSC_RCMR_START_SHIFT) /* Rising edge on RF signal */
-# define SSC_RCMR_START_ANYLEVEL (6 << SSC_RCMR_START_SHIFT) /* Any level change on RF signal */
-# define SSC_RCMR_START_ANYEDGE (7 << SSC_RCMR_START_SHIFT) /* Any edge on RF signal */
-# define SSC_RCMR_START_CMP0 (8 << SSC_RCMR_START_SHIFT) /* Compare 0 */
-#define SSC_RCMR_STOP (1 << 12) /* Bit 12: Receive Stop Select */
-#define SSC_RCMR_STTDLY_SHIFT (15) /* Bits 16-23: Receive Start Delay */
-#define SSC_RCMR_STTDLY_MASK (0xff << SSC_RCMR_STTDLY_SHIFT)
-#define SSC_RCMR_PERIOD_SHIFT (24) /* Bits 24-31: Receive Period Divider Selection */
-#define SSC_RCMR_PERIOD_MASK (0xff << SSC_RCMR_PERIOD_SHIFT)
-
-
-/* SSC Receive Frame Mode Register */
-
-#define SSC_RFMR_DATLEN_SHIFT (0) /* Bits 0-4: Data Length */
-#define SSC_RFMR_DATLEN_MASK (31 << SSC_RFMR_DATLEN_SHIFT)
-#define SSC_RFMR_LOOP (1 << 5) /* Bit 5: Loop Mode */
-#define SSC_RFMR_MSBF (1 << 7) /* Bit 7: Most Significant Bit First */
-#define SSC_RFMR_DATNB_SHIFT (8) /* Bits 8-11: Data Number per Frame */
-#define SSC_RFMR_DATNB_MASK (15 << SSC_RFMR_DATNB_SHIFT)
-#define SSC_RFMR_FSLEN_SHIFT (16) /* Bits 16-19: Receive Frame Sync Length */
-#define SSC_RFMR_FSLEN_MASK (15 << SSC_RFMR_FSLEN_SHIFT)
-#define SSC_RFMR_FSOS_SHIFT (20) /* Bits 20-22: Receive Frame Sync Output Selection */
-#define SSC_RFMR_FSOS_MASK (7 << SSC_RFMR_FSOS_SHIFT)
-# define SSC_RFMR_FSOS_NONE (0 << SSC_RFMR_FSOS_SHIFT) /* None */
-# define SSC_RFMR_FSOS_NEG (1 << SSC_RFMR_FSOS_SHIFT) /* 0x1 Negative Pulse */
-# define SSC_RFMR_FSOS_POW (2 << SSC_RFMR_FSOS_SHIFT) /* 0x2 Positive Pulse */
-# define SSC_RFMR_FSOS_LOW (3 << SSC_RFMR_FSOS_SHIFT) /* 0x3 Driven Low during data transfer */
-# define SSC_RFMR_FSOS_HIGH (4 << SSC_RFMR_FSOS_SHIFT) /* 0x4 Driven High during data transfer */
-# define SSC_RFMR_FSOS_TOGGLE (5 << SSC_RFMR_FSOS_SHIFT) /* 0x5 Toggling at each start of data transfer */
-#define SSC_RFMR_FSEDGE (1 << 24) /* Bit 24: Frame Sync Edge Detect */
-#define SSC_RFMR_FSLENEXT_SHIFT (28) /* Bits 28-31: FSLEN Field Extension */
-#define SSC_RFMR_FSLENEXT_MASK (15 << SSC_RFMR_FSLENEXT_SHIFT)
-
-/* SSC Transmit Clock Mode Register */
-
-#define SSC_TCMR_CKS_SHIFT (0) /* Bits 0-1: Transmit Clock Selection */
-#define SSC_TCMR_CKS_MASK (3 << SSC_TCMR_CKS_SHIFT)
-# define SSC_TCMR_CKS_DIVIDED (0 << SSC_TCMR_CKS_SHIFT) /* Divided Clock */
-# define SSC_TCMR_CKS_TK (1 << SSC_TCMR_CKS_SHIFT) /* TK Clock signal */
-# define SSC_TCMR_CKS_RK (2 << SSC_TCMR_CKS_SHIFT) /* RK pin */
-#define SSC_TCMR_CKO_SHIFT (2) /* Bits 2-4: Transmit Clock Output Mode Selection */
-#define SSC_TCMR_CKO_MASK (7 << SSC_TCMR_CKO_SHIFT)
-# define SSC_TCMR_CKO_ NONE (0 << SSC_TCMR_CKO_SHIFT) /* None */
-# define SSC_TCMR_CKO_CONTINUOUS (1 << SSC_TCMR_CKO_SHIFT) /* Continuous Transmit Clock */
-# define SSC_TCMR_CKO_XFERS (2 << SSC_TCMR_CKO_SHIFT) /* Transmit Clock only during data transfers */
-#define SSC_TCMR_CKI (1 << 5) /* Bit 5: Transmit Clock Inversion */
-#define SSC_TCMR_CKG_SHIFT (6) /* Bits 6-7: Transmit Clock Gating Selection */
-#define SSC_TCMR_CKG_MASK (3 << SSC_TCMR_CKG_SHIFT)
-# define SSC_TCMR_CKG_NONE (0 << SSC_TCMR_CKG_SHIFT) /* None, continuous clock */
-# define SSC_tCMR_CKG_TFLOW (1 << SSC_TCMR_CKG_SHIFT) /* Receive Clock enabled only if TF Low */
-# define SSC_TCMR_CKG_TFHIGH (2 << SSC_TCMR_CKG_SHIFT) /* Receive Clock enabled only if TF High */
-#define SSC_TCMR_START_SHIFT (8) /* Bits 8-11: Transmit Start Selection */
-#define SSC_TCMR_START_MASK (15 << SSC_TCMR_START_SHIFT)
-# define SSC_TCMR_START_CONTINOUS (0 << SSC_TCMR_START_SHIFT) /* Continuous */
-# define SSC_TCMR_START_START (1 << SSC_TCMR_START_SHIFT) /* Receive start */
-# define SSC_TCMR_START_TFLOW (2 << SSC_TCMR_START_SHIFT) /* Low level on TF signal */
-# define SSC_TCMR_START_TFHIGH (3 << SSC_TCMR_START_SHIFT) /* High level on TF signal */
-# define SSC_TCMR_START_TFFALL (4 << SSC_TCMR_START_SHIFT) /* Falling edge on TF signal */
-# define SSC_TCMR_START_TFRISE (5 << SSC_TCMR_START_SHIFT) /* Rising edge on TF signal */
-# define SSC_TCMR_START_ANYLEVEL (6 << SSC_TCMR_START_SHIFT) /* Any level change on TF signal */
-# define SSC_TCMR_START_ANYEDGE (7 << SSC_TCMR_START_SHIFT) /* Any edge on TF signal */
-#define SSC_TCMR_STTDLY_SHIFT (16) /* Bits 16-23: Transmit Start Delay */
-#define SSC_TCMR_STTDLY_MASK (0xff << SSC_TCMR_STTDLY_SHIFT)
-#define SSC_TCMR_PERIOD_SHIFT (24) /* Bits 24-31: Transmit Period Divider Selection */
-#define SSC_TCMR_PERIOD_MASK (0xff << SSC_TCMR_PERIOD_SHIFT)
-
-/* SSC Transmit Frame Mode Register */
-
-#define SSC_TFMR_DATLEN_SHIFT (0) /* Bits 0-4: Data Length */
-#define SSC_TFMR_DATLEN_MASK (31 << SSC_TFMR_DATLEN_SHIFT)
-#define SSC_TFMR_DATDEF (1 << 5) /* Bit 5: Data Default Value */
-#define SSC_TFMR_MSBF (1 << 7) /* Bit 7: Most Significant Bit First */
-#define SSC_TFMR_DATNB_SHIFT (8) /* Bits 8-11: Data Number per frame */
-#define SSC_TFMR_DATNB_MASK (15 << SSC_TFMR_DATNB_SHIFT)
-#define SSC_TFMR_FSLEN_SHIFT (16) /* Bits 16-19: Transmit Frame Syn Length */
-#define SSC_TFMR_FSLEN_MASK (15 << SSC_TFMR_FSLEN_SHIFT)
-#define SSC_TFMR_FSOS_SHIFT (20) /* Bits 20-22: Transmit Frame Sync Output Selection */
-#define SSC_TFMR_FSOS_MASK (7 << SSC_TFMR_FSOS_SHIFT)
-# define SSC_TFMR_FSOS_NONE (0 << SSC_TFMR_FSOS_SHIFT) /* None */
-# define SSC_TFMR_FSOS_NEG (1 << SSC_TFMR_FSOS_SHIFT) /* 0x1 Negative Pulse */
-# define SSC_TFMR_FSOS_POW (2 << SSC_TFMR_FSOS_SHIFT) /* 0x2 Positive Pulse */
-# define SSC_TFMR_FSOS_LOW (3 << SSC_TFMR_FSOS_SHIFT) /* 0x3 Driven Low during data transfer */
-# define SSC_TFMR_FSOS_HIGH (4 << SSC_TFMR_FSOS_SHIFT) /* 0x4 Driven High during data transfer */
-# define SSC_TFMR_FSOS_TOGGLE (5 << SSC_TFMR_FSOS_SHIFT) /* 0x5 Toggling at each start of data transfer */
-#define SSC_TFMR_FSDEN (1 << 23) /* Bit 23: Frame Sync Data Enable */
-#define SSC_TFMR_FSEDGE (1 << 24) /* Bit 24: Frame Sync Edge Detection */
-#define SSC_TFMR_FSLENEXT_SHIFT (28) /* Bits 28-31: FSLEN Field Extension */
-#define SSC_TFMR_FSLENEXT_MASK (15 << SSC_TFMR_FSLENEXT_SHIFT)
-
-/* SSC Receive Synchronization Holding Register */
-
-#define SSC_RSHR_RSDAT_SHIFT (0) /* Bits 0-15: Receive Synchronization Data */
-#define SSC_RSHR_RSDAT_MASK (0xffff << SSC_RSHR_RSDAT_SHIFT)
-
-/* SSC Transmit Synchronization Holding Register */
-
-#define SSC_TSHR_TSDAT_SHIFT (0) /* Bits 0-15: Transmit Synchronization Data */
-#define SSC_TSHR_TSDAT_MASK (0xffff << SSC_TSHR_TSDAT_SHIFT)
-
-/* SSC Receive Compare 0 Register */
-
-#define SSC_RC0R_CP0_SHIFT (0) /* Bits 0-15: Receive Compare Data 0 */
-#define SSC_RC0R_CP0_MASK (0xffff << SSC_RC0R_CP0_SHIFT)
-
-/* SSC Receive Compare 1 Register */
-
-#define SSC_RC1R_CP1_SHIFT (0) /* Bits 0-15: Receive Compare Data 1 */
-#define SSC_RC1R_CP1_MASK (0xffff << SSC_RC1R_CP1_SHIFT)
-
-/* SSC Status Register, SSC Interrupt Enable Register, SSC Interrupt Disable
- * Register, and SSC Interrupt Mask Register commin bit-field definitions
- */
-
-#define SSC_INT_TXRDY (1 << 0) /* Bit 0: Transmit Ready */
-#define SSC_INT_TXEMPTY (1 << 1) /* Bit 1: Transmit Empty */
-#define SSC_INT_ENDTX (1 << 2) /* Bit 2: End of Transmission */
-#define SSC_INT_TXBUFE (1 << 3) /* Bit 3: Transmit Buffer Empty */
-#define SSC_INT_RXRDY (1 << 4) /* Bit 4: Receive Ready */
-#define SSC_INT_OVRUN (1 << 5) /* Bit 5: Receive Overrun */
-#define SSC_INT_ENDRX (1 << 6) /* Bit 6: End of Reception */
-#define SSC_INT_RXBUFF (1 << 7) /* Bit 7: Receive Buffer Full */
-#define SSC_INT_CP0 (1 << 8) /* Bit 8: Compare 0 */
-#define SSC_INT_CP1 (1 << 9) /* Bit 9: Compare 1 */
-#define SSC_INT_TXSYN (1 << 10) /* Bit 10: Transmit Sync */
-#define SSC_INT_RXSYN (1 << 11) /* Bit 11: Receive Sync */
-#define SSC_SR_TXEN (1 << 16) /* Bit 16: Transmit Enable (SR only) */
-#define SSC_SR_RXEN (1 << 17) /* Bit 17: Receive Enable (SR only) */
-
-/* SSC Write Protect Mode Register */
-
-#define SSC_WPMR_WPEN (1 << 0) /* Bit 0: Write Protect Enable */
-#define SSC_WPMR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protect KEY */
-#define SSC_WPMR_WPKEY_MASK (0x00ffffff << SSC_WPMR_WPKEY_SHIFT)
-
-/* SSC Write Protect Status Register */
-
-#define SSC_WPSR_WPVS (1 << 0) /* Bit 0: Write Protect Violation Status */
-#define SSC_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protect Violation Source */
-#define SSC_WPSR_WPVSRC_MASK (0xffff << SSC_WPSR_WPVSRC_SHIFT)
-
-/****************************************************************************************
- * Public Types
- ****************************************************************************************/
-
-/****************************************************************************************
- * Public Data
- ****************************************************************************************/
-
-/****************************************************************************************
- * Public Functions
- ****************************************************************************************/
-
-#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_SSC_H */
+/**************************************************************************************** + * arch/arm/src/sam3u/sam3u_ssc.h + * + * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_SSC_H +#define __ARCH_ARM_SRC_SAM3U_SAM3U_SSC_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +#include <nuttx/config.h> + +#include "chip.h" +#include "sam3u_memorymap.h" + +/**************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************/ + +/* SSC register offsets *****************************************************************/ + +#define SAM3U_SSC_CR_OFFSET 0x000 /* Control Register */ +#define SAM3U_SSC_CMR_OFFSET 0x004 /* Clock Mode Register */ + /* 0x008: Reserved */ + /* 0x00c: Reserved */ +#define SAM3U_SSC_RCMR_OFFSET 0x010 /* Receive Clock Mode Register */ +#define SAM3U_SSC_RFMR_OFFSET 0x014 /* Receive Frame Mode Register */ +#define SAM3U_SSC_TCMR_OFFSET 0x018 /* Transmit Clock Mode Register */ +#define SAM3U_SSC_TFMR_OFFSET 0x01c /* Transmit Frame Mode Register */ +#define SAM3U_SSC_RHR_OFFSET 0x020 /* Receive Holding Register */ +#define SAM3U_SSC_THR_OFFSET 0x024 /* Transmit Holding Register */ + /* 0x028: Reserved */ + /* 0x02c: Reserved */ +#define SAM3U_SSC_RSHR_OFFSET 0x030 /* Receive Sync. Holding Register */ +#define SAM3U_SSC_TSHR_OFFSET 0x034 /* Transmit Sync. Holding Register */ +#define SAM3U_SSC_RC0R_OFFSET 0x038 /* Receive Compare 0 Register */ +#define SAM3U_SSC_RC1R_OFFSET 0x03c /* Receive Compare 1 Register */ +#define SAM3U_SSC_SR_OFFSET 0x040 /* Status Register */ +#define SAM3U_SSC_IER_OFFSET 0x044 /* Interrupt Enable Register */ +#define SAM3U_SSC_IDR_OFFSET 0x048 /* Interrupt Disable Register */ +#define SAM3U_SSC_IMR_OFFSET 0x04c /* Interrupt Mask Register */ +#define SAM3U_SSC_WPMR_OFFSET 0x0e4 /* Write Protect Mode Register */ +#define SAM3U_SSC_WPSR_OFFSET 0x0e8 /* Write Protect Status Register */ + /* 0x050-0x0fc: Reserved */ + /* 0x100-0x124: Reserved */ + +/* SSC register adresses ****************************************************************/ + +#define SAM3U_SSC_CR (SAM3U_SSC_BASE+SAM3U_SSC_CR_OFFSET) +#define SAM3U_SSC_CMR (SAM3U_SSC_BASE+SAM3U_SSC_CMR_OFFSET) +#define SAM3U_SSC_RCMR (SAM3U_SSC_BASE+SAM3U_SSC_RCMR_OFFSET) +#define SAM3U_SSC_RFMR (SAM3U_SSC_BASE+SAM3U_SSC_RFMR_OFFSET) +#define SAM3U_SSC_TCMR (SAM3U_SSC_BASE+SAM3U_SSC_TCMR_OFFSET) +#define SAM3U_SSC_TFMR (SAM3U_SSC_BASE+SAM3U_SSC_TFMR_OFFSET) +#define SAM3U_SSC_RHR (SAM3U_SSC_BASE+SAM3U_SSC_RHR_OFFSET) +#define SAM3U_SSC_THR (SAM3U_SSC_BASE+SAM3U_SSC_THR_OFFSET) +#define SAM3U_SSC_RSHR (SAM3U_SSC_BASE+SAM3U_SSC_RSHR_OFFSET) +#define SAM3U_SSC_TSHR (SAM3U_SSC_BASE+SAM3U_SSC_TSHR_OFFSET) +#define SAM3U_SSC_RC0R (SAM3U_SSC_BASE+SAM3U_SSC_RC0R_OFFSET) +#define SAM3U_SSC_RC1R (SAM3U_SSC_BASE+SAM3U_SSC_RC1R_OFFSET) +#define SAM3U_SSC_SR (SAM3U_SSC_BASE+SAM3U_SSC_SR_OFFSET) +#define SAM3U_SSC_IER (SAM3U_SSC_BASE+SAM3U_SSC_IER_OFFSET) +#define SAM3U_SSC_IDR (SAM3U_SSC_BASE+SAM3U_SSC_IDR_OFFSET) +#define SAM3U_SSC_IMR (SAM3U_SSC_BASE+SAM3U_SSC_IMR_OFFSET) +#define SAM3U_SSC_WPMR (SAM3U_SSC_BASE+SAM3U_SSC_WPMR_OFFSET) +#define SAM3U_SSC_WPSR (SAM3U_SSC_BASE+SAM3U_SSC_WPSR_OFFSET) + +/* SSC register bit definitions *********************************************************/ + +/* SSC Control Register */ + +#define SSC_CR_RXEN (1 << 0) /* Bit 0: Receive Enable */ +#define SSC_CR_RXDIS (1 << 1) /* Bit 1: Receive Disable */ +#define SSC_CR_TXEN (1 << 8) /* Bit 8: Transmit Enable */ +#define SSC_CR_TXDIS (1 << 9) /* Bit 9: Transmit Disable */ +#define SSC_CR_SWRST (1 << 15) /* Bit 15: Software Reset */ + +/* SSC Clock Mode Register */ + +#define SSC_CMR_DIV_SHIFT (0) /* Bits 0-11: Clock Divider */ +#define SSC_CMR_DIV_MASK (0xfff << SSC_CMR_DIV_SHIFT) + +/* SSC Receive Clock Mode Register */ + +#define SSC_RCMR_CKS_SHIFT (0) /* Bits 0-1: Receive Clock Selection */ +#define SSC_RCMR_CKS_MASK (3 << SSC_RCMR_CKS_SHIFT) +# define SSC_RCMR_CKS_DIVIDED (0 << SSC_RCMR_CKS_SHIFT) /* Divided Clock */ +# define SSC_RCMR_CKS_TK (1 << SSC_RCMR_CKS_SHIFT) /* TK Clock signal */ +# define SSC_RCMR_CKS_RK (2 << SSC_RCMR_CKS_SHIFT) /* RK pin */ +#define SSC_RCMR_CKO_SHIFT (2) /* Bits 2-4: Receive Clock Output Mode Selection */ +#define SSC_RCMR_CKO_MASK (7 << SSC_RCMR_CKO_SHIFT) +# define SSC_RCMR_CKO_ NONE (0 << SSC_RCMR_CKO_SHIFT) /* None */ +# define SSC_RCMR_CKO_CONTINUOUS (1 << SSC_RCMR_CKO_SHIFT) /* Continuous Receive Clock */ +# define SSC_RCMR_CKO_XFERS (2 << SSC_RCMR_CKO_SHIFT) /* Receive Clock only during data transfers */ +#define SSC_RCMR_CKI (1 << 5) /* Bit 5: Receive Clock Inversion */ +#define SSC_RCMR_CKG_SHIFT (6) /* Bits 6-7: Receive Clock Gating Selection */ +#define SSC_RCMR_CKG_MASK (3 << SSC_RCMR_CKG_SHIFT) +# define SSC_RCMR_CKG_NONE (0 << SSC_RCMR_CKG_SHIFT) /* None, continuous clock */ +# define SSC_RCMR_CKG_RFLOW (1 << SSC_RCMR_CKG_SHIFT) /* Receive Clock enabled only if RF Low */ +# define SSC_RCMR_CKG_RFHIGH (2 << SSC_RCMR_CKG_SHIFT) /* Receive Clock enabled only if RF High */ +#define SSC_RCMR_START_SHIFT (8) /* Bits 8-11: Receive Start Selection */ +#define SSC_RCMR_START_MASK (15 << SSC_RCMR_START_SHIFT) +# define SSC_RCMR_START_CONTINOUS (0 << SSC_RCMR_START_SHIFT) /* Continuous */ +# define SSC_RCMR_START_START (1 << SSC_RCMR_START_SHIFT) /* Transmit start */ +# define SSC_RCMR_START_RFLOW (2 << SSC_RCMR_START_SHIFT) /* Low level on RF signal */ +# define SSC_RCMR_START_RFHIGH (3 << SSC_RCMR_START_SHIFT) /* High level on RF signal */ +# define SSC_RCMR_START_RFFALL (4 << SSC_RCMR_START_SHIFT) /* Falling edge on RF signal */ +# define SSC_RCMR_START_RFRISE (5 << SSC_RCMR_START_SHIFT) /* Rising edge on RF signal */ +# define SSC_RCMR_START_ANYLEVEL (6 << SSC_RCMR_START_SHIFT) /* Any level change on RF signal */ +# define SSC_RCMR_START_ANYEDGE (7 << SSC_RCMR_START_SHIFT) /* Any edge on RF signal */ +# define SSC_RCMR_START_CMP0 (8 << SSC_RCMR_START_SHIFT) /* Compare 0 */ +#define SSC_RCMR_STOP (1 << 12) /* Bit 12: Receive Stop Select */ +#define SSC_RCMR_STTDLY_SHIFT (15) /* Bits 16-23: Receive Start Delay */ +#define SSC_RCMR_STTDLY_MASK (0xff << SSC_RCMR_STTDLY_SHIFT) +#define SSC_RCMR_PERIOD_SHIFT (24) /* Bits 24-31: Receive Period Divider Selection */ +#define SSC_RCMR_PERIOD_MASK (0xff << SSC_RCMR_PERIOD_SHIFT) + + +/* SSC Receive Frame Mode Register */ + +#define SSC_RFMR_DATLEN_SHIFT (0) /* Bits 0-4: Data Length */ +#define SSC_RFMR_DATLEN_MASK (31 << SSC_RFMR_DATLEN_SHIFT) +#define SSC_RFMR_LOOP (1 << 5) /* Bit 5: Loop Mode */ +#define SSC_RFMR_MSBF (1 << 7) /* Bit 7: Most Significant Bit First */ +#define SSC_RFMR_DATNB_SHIFT (8) /* Bits 8-11: Data Number per Frame */ +#define SSC_RFMR_DATNB_MASK (15 << SSC_RFMR_DATNB_SHIFT) +#define SSC_RFMR_FSLEN_SHIFT (16) /* Bits 16-19: Receive Frame Sync Length */ +#define SSC_RFMR_FSLEN_MASK (15 << SSC_RFMR_FSLEN_SHIFT) +#define SSC_RFMR_FSOS_SHIFT (20) /* Bits 20-22: Receive Frame Sync Output Selection */ +#define SSC_RFMR_FSOS_MASK (7 << SSC_RFMR_FSOS_SHIFT) +# define SSC_RFMR_FSOS_NONE (0 << SSC_RFMR_FSOS_SHIFT) /* None */ +# define SSC_RFMR_FSOS_NEG (1 << SSC_RFMR_FSOS_SHIFT) /* 0x1 Negative Pulse */ +# define SSC_RFMR_FSOS_POW (2 << SSC_RFMR_FSOS_SHIFT) /* 0x2 Positive Pulse */ +# define SSC_RFMR_FSOS_LOW (3 << SSC_RFMR_FSOS_SHIFT) /* 0x3 Driven Low during data transfer */ +# define SSC_RFMR_FSOS_HIGH (4 << SSC_RFMR_FSOS_SHIFT) /* 0x4 Driven High during data transfer */ +# define SSC_RFMR_FSOS_TOGGLE (5 << SSC_RFMR_FSOS_SHIFT) /* 0x5 Toggling at each start of data transfer */ +#define SSC_RFMR_FSEDGE (1 << 24) /* Bit 24: Frame Sync Edge Detect */ +#define SSC_RFMR_FSLENEXT_SHIFT (28) /* Bits 28-31: FSLEN Field Extension */ +#define SSC_RFMR_FSLENEXT_MASK (15 << SSC_RFMR_FSLENEXT_SHIFT) + +/* SSC Transmit Clock Mode Register */ + +#define SSC_TCMR_CKS_SHIFT (0) /* Bits 0-1: Transmit Clock Selection */ +#define SSC_TCMR_CKS_MASK (3 << SSC_TCMR_CKS_SHIFT) +# define SSC_TCMR_CKS_DIVIDED (0 << SSC_TCMR_CKS_SHIFT) /* Divided Clock */ +# define SSC_TCMR_CKS_TK (1 << SSC_TCMR_CKS_SHIFT) /* TK Clock signal */ +# define SSC_TCMR_CKS_RK (2 << SSC_TCMR_CKS_SHIFT) /* RK pin */ +#define SSC_TCMR_CKO_SHIFT (2) /* Bits 2-4: Transmit Clock Output Mode Selection */ +#define SSC_TCMR_CKO_MASK (7 << SSC_TCMR_CKO_SHIFT) +# define SSC_TCMR_CKO_ NONE (0 << SSC_TCMR_CKO_SHIFT) /* None */ +# define SSC_TCMR_CKO_CONTINUOUS (1 << SSC_TCMR_CKO_SHIFT) /* Continuous Transmit Clock */ +# define SSC_TCMR_CKO_XFERS (2 << SSC_TCMR_CKO_SHIFT) /* Transmit Clock only during data transfers */ +#define SSC_TCMR_CKI (1 << 5) /* Bit 5: Transmit Clock Inversion */ +#define SSC_TCMR_CKG_SHIFT (6) /* Bits 6-7: Transmit Clock Gating Selection */ +#define SSC_TCMR_CKG_MASK (3 << SSC_TCMR_CKG_SHIFT) +# define SSC_TCMR_CKG_NONE (0 << SSC_TCMR_CKG_SHIFT) /* None, continuous clock */ +# define SSC_tCMR_CKG_TFLOW (1 << SSC_TCMR_CKG_SHIFT) /* Receive Clock enabled only if TF Low */ +# define SSC_TCMR_CKG_TFHIGH (2 << SSC_TCMR_CKG_SHIFT) /* Receive Clock enabled only if TF High */ +#define SSC_TCMR_START_SHIFT (8) /* Bits 8-11: Transmit Start Selection */ +#define SSC_TCMR_START_MASK (15 << SSC_TCMR_START_SHIFT) +# define SSC_TCMR_START_CONTINOUS (0 << SSC_TCMR_START_SHIFT) /* Continuous */ +# define SSC_TCMR_START_START (1 << SSC_TCMR_START_SHIFT) /* Receive start */ +# define SSC_TCMR_START_TFLOW (2 << SSC_TCMR_START_SHIFT) /* Low level on TF signal */ +# define SSC_TCMR_START_TFHIGH (3 << SSC_TCMR_START_SHIFT) /* High level on TF signal */ +# define SSC_TCMR_START_TFFALL (4 << SSC_TCMR_START_SHIFT) /* Falling edge on TF signal */ +# define SSC_TCMR_START_TFRISE (5 << SSC_TCMR_START_SHIFT) /* Rising edge on TF signal */ +# define SSC_TCMR_START_ANYLEVEL (6 << SSC_TCMR_START_SHIFT) /* Any level change on TF signal */ +# define SSC_TCMR_START_ANYEDGE (7 << SSC_TCMR_START_SHIFT) /* Any edge on TF signal */ +#define SSC_TCMR_STTDLY_SHIFT (16) /* Bits 16-23: Transmit Start Delay */ +#define SSC_TCMR_STTDLY_MASK (0xff << SSC_TCMR_STTDLY_SHIFT) +#define SSC_TCMR_PERIOD_SHIFT (24) /* Bits 24-31: Transmit Period Divider Selection */ +#define SSC_TCMR_PERIOD_MASK (0xff << SSC_TCMR_PERIOD_SHIFT) + +/* SSC Transmit Frame Mode Register */ + +#define SSC_TFMR_DATLEN_SHIFT (0) /* Bits 0-4: Data Length */ +#define SSC_TFMR_DATLEN_MASK (31 << SSC_TFMR_DATLEN_SHIFT) +#define SSC_TFMR_DATDEF (1 << 5) /* Bit 5: Data Default Value */ +#define SSC_TFMR_MSBF (1 << 7) /* Bit 7: Most Significant Bit First */ +#define SSC_TFMR_DATNB_SHIFT (8) /* Bits 8-11: Data Number per frame */ +#define SSC_TFMR_DATNB_MASK (15 << SSC_TFMR_DATNB_SHIFT) +#define SSC_TFMR_FSLEN_SHIFT (16) /* Bits 16-19: Transmit Frame Syn Length */ +#define SSC_TFMR_FSLEN_MASK (15 << SSC_TFMR_FSLEN_SHIFT) +#define SSC_TFMR_FSOS_SHIFT (20) /* Bits 20-22: Transmit Frame Sync Output Selection */ +#define SSC_TFMR_FSOS_MASK (7 << SSC_TFMR_FSOS_SHIFT) +# define SSC_TFMR_FSOS_NONE (0 << SSC_TFMR_FSOS_SHIFT) /* None */ +# define SSC_TFMR_FSOS_NEG (1 << SSC_TFMR_FSOS_SHIFT) /* 0x1 Negative Pulse */ +# define SSC_TFMR_FSOS_POW (2 << SSC_TFMR_FSOS_SHIFT) /* 0x2 Positive Pulse */ +# define SSC_TFMR_FSOS_LOW (3 << SSC_TFMR_FSOS_SHIFT) /* 0x3 Driven Low during data transfer */ +# define SSC_TFMR_FSOS_HIGH (4 << SSC_TFMR_FSOS_SHIFT) /* 0x4 Driven High during data transfer */ +# define SSC_TFMR_FSOS_TOGGLE (5 << SSC_TFMR_FSOS_SHIFT) /* 0x5 Toggling at each start of data transfer */ +#define SSC_TFMR_FSDEN (1 << 23) /* Bit 23: Frame Sync Data Enable */ +#define SSC_TFMR_FSEDGE (1 << 24) /* Bit 24: Frame Sync Edge Detection */ +#define SSC_TFMR_FSLENEXT_SHIFT (28) /* Bits 28-31: FSLEN Field Extension */ +#define SSC_TFMR_FSLENEXT_MASK (15 << SSC_TFMR_FSLENEXT_SHIFT) + +/* SSC Receive Synchronization Holding Register */ + +#define SSC_RSHR_RSDAT_SHIFT (0) /* Bits 0-15: Receive Synchronization Data */ +#define SSC_RSHR_RSDAT_MASK (0xffff << SSC_RSHR_RSDAT_SHIFT) + +/* SSC Transmit Synchronization Holding Register */ + +#define SSC_TSHR_TSDAT_SHIFT (0) /* Bits 0-15: Transmit Synchronization Data */ +#define SSC_TSHR_TSDAT_MASK (0xffff << SSC_TSHR_TSDAT_SHIFT) + +/* SSC Receive Compare 0 Register */ + +#define SSC_RC0R_CP0_SHIFT (0) /* Bits 0-15: Receive Compare Data 0 */ +#define SSC_RC0R_CP0_MASK (0xffff << SSC_RC0R_CP0_SHIFT) + +/* SSC Receive Compare 1 Register */ + +#define SSC_RC1R_CP1_SHIFT (0) /* Bits 0-15: Receive Compare Data 1 */ +#define SSC_RC1R_CP1_MASK (0xffff << SSC_RC1R_CP1_SHIFT) + +/* SSC Status Register, SSC Interrupt Enable Register, SSC Interrupt Disable + * Register, and SSC Interrupt Mask Register commin bit-field definitions + */ + +#define SSC_INT_TXRDY (1 << 0) /* Bit 0: Transmit Ready */ +#define SSC_INT_TXEMPTY (1 << 1) /* Bit 1: Transmit Empty */ +#define SSC_INT_ENDTX (1 << 2) /* Bit 2: End of Transmission */ +#define SSC_INT_TXBUFE (1 << 3) /* Bit 3: Transmit Buffer Empty */ +#define SSC_INT_RXRDY (1 << 4) /* Bit 4: Receive Ready */ +#define SSC_INT_OVRUN (1 << 5) /* Bit 5: Receive Overrun */ +#define SSC_INT_ENDRX (1 << 6) /* Bit 6: End of Reception */ +#define SSC_INT_RXBUFF (1 << 7) /* Bit 7: Receive Buffer Full */ +#define SSC_INT_CP0 (1 << 8) /* Bit 8: Compare 0 */ +#define SSC_INT_CP1 (1 << 9) /* Bit 9: Compare 1 */ +#define SSC_INT_TXSYN (1 << 10) /* Bit 10: Transmit Sync */ +#define SSC_INT_RXSYN (1 << 11) /* Bit 11: Receive Sync */ +#define SSC_SR_TXEN (1 << 16) /* Bit 16: Transmit Enable (SR only) */ +#define SSC_SR_RXEN (1 << 17) /* Bit 17: Receive Enable (SR only) */ + +/* SSC Write Protect Mode Register */ + +#define SSC_WPMR_WPEN (1 << 0) /* Bit 0: Write Protect Enable */ +#define SSC_WPMR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protect KEY */ +#define SSC_WPMR_WPKEY_MASK (0x00ffffff << SSC_WPMR_WPKEY_SHIFT) + +/* SSC Write Protect Status Register */ + +#define SSC_WPSR_WPVS (1 << 0) /* Bit 0: Write Protect Violation Status */ +#define SSC_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protect Violation Source */ +#define SSC_WPSR_WPVSRC_MASK (0xffff << SSC_WPSR_WPVSRC_SHIFT) + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +/**************************************************************************************** + * Public Data + ****************************************************************************************/ + +/**************************************************************************************** + * Public Functions + ****************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_SSC_H */ diff --git a/nuttx/arch/arm/src/sam3u/sam3u_supc.h b/nuttx/arch/arm/src/sam3u/sam3u_supc.h index 8cde5389e..5bd28de50 100644 --- a/nuttx/arch/arm/src/sam3u/sam3u_supc.h +++ b/nuttx/arch/arm/src/sam3u/sam3u_supc.h @@ -1,164 +1,164 @@ -/****************************************************************************************
- * arch/arm/src/sam3u/sam3u_supc.h
- *
- * Copyright (C) 2009 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_SUPC_H
-#define __ARCH_ARM_SRC_SAM3U_SAM3U_SUPC_H
-
-/****************************************************************************************
- * Included Files
- ****************************************************************************************/
-
-#include <nuttx/config.h>
-
-#include "chip.h"
-#include "sam3u_memorymap.h"
-
-/****************************************************************************************
- * Pre-processor Definitions
- ****************************************************************************************/
-
-/* SUPC register offsets ****************************************************************/
-
-#define SAM3U_SUPC_CR_OFFSET 0x00 /* Supply Controller Control Register */
-#define SAM3U_SUPC_SMMR_OFFSET 0x04 /* Supply Controller Supply Monitor Mode Register */
-#define SAM3U_SUPC_MR_OFFSET 0x08 /* Supply Controller Mode Register */
-#define SAM3U_SUPC_WUMR_OFFSET 0x0c /* Supply Controller Wake Up Mode Register */
-#define SAM3U_SUPC_WUIR_OFFSET 0x10 /* Supply Controller Wake Up Inputs Register */
-#define SAM3U_SUPC_SR_OFFSET 0x14 /* Supply Controller Status Register */
-
-/* SUPC register adresses ***************************************************************/
-
-#define SAM3U_SUPC_CR (SAM3U_SUPC_BASE+SAM3U_SUPC_CR_OFFSET)
-#define SAM3U_SUPC_SMMR (SAM3U_SUPC_BASE+SAM3U_SUPC_SMMR_OFFSET)
-#define SAM3U_SUPC_MR (SAM3U_SUPC_BASE+SAM3U_SUPC_MR_OFFSET)
-#define SAM3U_SUPC_WUMR (SAM3U_SUPC_BASE+SAM3U_SUPC_WUMR_OFFSET)
-#define SAM3U_SUPC_WUIR (SAM3U_SUPC_BASE+SAM3U_SUPC_WUIR_OFFSET)
-#define SAM3U_SUPC_SR (SAM3U_SUPC_BASE+SAM3U_SUPC_SR_OFFSET)
-
-/* SUPC register bit definitions ********************************************************/
-
-#define SUPC_CR_VROFF (1 << 2) /* Bit 2: Voltage Regulator Off */
-#define SUPC_CR_XTALSEL (1 << 3) /* Bit 3: Crystal Oscillator Select */
-#define SUPC_CR_KEY_SHIFT (24) /* Bits 24-31: Password */
-#define SUPC_CR_KEY_MASK (0xff << SUPC_CR_KEY_SHIFT)
-
-#define SUPC_SMMR_SMTH_SHIFT (0) /* Bits 0-3: Supply Monitor Threshold */
-#define SUPC_SMMR_SMTH_MASK (15 << SUPC_SMMR_SMTH_SHIFT)
-# define SUPC_SMMR_SMTH_1p9V (0 << SUPC_SMMR_SMTH_SHIFT) /* 1.9V */
-# define SUPC_SMMR_SMTH_2p0V (1 << SUPC_SMMR_SMTH_SHIFT) /* 2.0V */
-# define SUPC_SMMR_SMTH_2p1V (2 << SUPC_SMMR_SMTH_SHIFT) /* 2.1V */
-# define SUPC_SMMR_SMTH_2p2V (3 << SUPC_SMMR_SMTH_SHIFT) /* 2.2V */
-# define SUPC_SMMR_SMTH_2p3V (4 << SUPC_SMMR_SMTH_SHIFT) /* 2.3V */
-# define SUPC_SMMR_SMTH_2p4V (5 << SUPC_SMMR_SMTH_SHIFT) /* 2.4V */
-# define SUPC_SMMR_SMTH_2p5V (6 << SUPC_SMMR_SMTH_SHIFT) /* 2.5V */
-# define SUPC_SMMR_SMTH_2p6V (7 << SUPC_SMMR_SMTH_SHIFT) /* 2.6V */
-# define SUPC_SMMR_SMTH_2p7V (8 << SUPC_SMMR_SMTH_SHIFT) /* 2.7V */
-# define SUPC_SMMR_SMTH_2p8V (9 << SUPC_SMMR_SMTH_SHIFT) /* 2.8V */
-# define SUPC_SMMR_SMTH_2p9V (10 << SUPC_SMMR_SMTH_SHIFT) /* 2.9V */
-# define SUPC_SMMR_SMTH_3p0V (11 << SUPC_SMMR_SMTH_SHIFT) /* 3.0V */
-# define SUPC_SMMR_SMTH_3p1V (12 << SUPC_SMMR_SMTH_SHIFT) /* 3.1V */
-# define SUPC_SMMR_SMTH_3p2V (13 << SUPC_SMMR_SMTH_SHIFT) /* 3.2V */
-# define SUPC_SMMR_SMTH_3p3V (14 << SUPC_SMMR_SMTH_SHIFT) /* 3.3V */
-# define SUPC_SMMR_SMTH_3p4V (15 << SUPC_SMMR_SMTH_SHIFT) /* 3.4V */
-#define SUPC_SMMR_SMSMPL_SHIFT (8) /* Bits 8-10: Supply Monitor Sampling Period */
-#define SUPC_SMMR_SMSMPL_MASK (7 << SUPC_SMMR_SMSMPL_SHIFT)
-# define SUPC_SMMR_SMSMPL_SMD (0 << SUPC_SMMR_SMSMPL_SHIFT) /* Supply Monitor disabled */
-# define SUPC_SMMR_SMSMPL_CSM (1 << SUPC_SMMR_SMSMPL_SHIFT) /* Continuous Supply Monitor */
-# define SUPC_SMMR_SMSMPL_32SLCK (2 << SUPC_SMMR_SMSMPL_SHIFT) /* Eevery 32 SLCK periods */
-# define SUPC_SMMR_SMSMPL_256SLCK (3 << SUPC_SMMR_SMSMPL_SHIFT) /* Every 256 SLCK periods */
-# define SUPC_SMMR_SMSMPL_2048SLCK (4 << SUPC_SMMR_SMSMPL_SHIFT) /* Every 2,048 SLCK periods */
-#define SUPC_SMMR_SMRSTEN (1 << 12) /* Bit 12: Supply Monitor Reset Enable */
-#define SUPC_SMMR_SMIEN (1 << 13) /* Bit 13: Supply Monitor Interrupt Enable */
-
-#define SUPC_MR_BODRSTEN (1 << 12) /* Bit 12: Brownout Detector Reset Enable */
-#define SUPC_MR_BODDIS (1 << 13) /* Bit 13: Brownout Detector Disable */
-#define SUPC_MR_VDDIORDY (1 << 14) /* Bit 14: VDDIO Ready */
-#define SUPC_MR_OSCBYPASS (1 << 20) /* Bit 20: Oscillator Bypass */
-#define SUPC_MR_KEY_SHIFT (24) /* Bits 24-31: Password Key */
-#define SUPC_MR_KEY_MASK (0xff << SUPC_MR_KEY_SHIFT)
-
-#define SUPC_WUMR_FWUPEN (1 << 0) /* Bit 0: Force Wake Up Enable */
-#define SUPC_WUMR_SMEN (1 << 1) /* Bit 1: Supply Monitor Wake Up Enable */
-#define SUPC_WUMR_RTTEN (1 << 2) /* Bit 2: Real Time Timer Wake Up Enable */
-#define SUPC_WUMR_RTCEN (1 << 3) /* Bit 3: Real Time Clock Wake Up Enable */
-#define SUPC_WUMR_FWUPDBC_SHIFT (8) /* Bits 8-10: Force Wake Up Debouncer */
-#define SUPC_WUMR_FWUPDBC_MASK (7 << SUPC_WUMR_FWUPDBC_SHIFT)
- #define SUPC_WUMR_FWUPDBC_1SCLK (0 << SUPC_WUMR_FWUPDBC_SHIFT) /* Immediate, no debouncing */
- #define SUPC_WUMR_FWUPDBC_3SCLK (1 << SUPC_WUMR_FWUPDBC_SHIFT) /* FWUP at least 3 SLCK periods */
- #define SUPC_WUMR_FWUPDBC_32SCLK (2 << SUPC_WUMR_FWUPDBC_SHIFT) /* FWUP at least 32 SLCK periods */
- #define SUPC_WUMR_FWUPDBC_512SCLK (3 << SUPC_WUMR_FWUPDBC_SHIFT) /* FWUP at least 512 SLCK periods */
- #define SUPC_WUMR_FWUPDBC_4096SCLK (4 << SUPC_WUMR_FWUPDBC_SHIFT) /* FWUP at least 4096 SLCK periods */
- #define SUPC_WUMR_FWUPDBC_32768SCLK (5 << SUPC_WUMR_FWUPDBC_SHIFT) /* FWUP at least 32768 SLCK periods */
-#define SUPC_WUMR_WKUPDBC_SHIFT (12) /* Bits 12-14: Wake Up Inputs Debouncer */
-#define SUPC_WUMR_WKUPDBC_MASK (7 << SUPC_WUMR_WKUPDBC_SHIFT)
-# define SUPC_WUMR_WKUPDBC_1SCLK (0 << SUPC_WUMR_WKUPDBC_SHIFT) /* Immediate, no debouncing */
-# define SUPC_WUMR_WKUPDBC_3SCLK (1 << SUPC_WUMR_WKUPDBC_SHIFT) /* Input active at least 3 SLCK periods */
-# define SUPC_WUMR_WKUPDBC_32SCLK (2 << SUPC_WUMR_WKUPDBC_SHIFT) /* Input active at least 32 SLCK periods */
-# define SUPC_WUMR_WKUPDBC_512SCLK (3 << SUPC_WUMR_WKUPDBC_SHIFT) /* Input active at least 512 SLCK periods */
-# define SUPC_WUMR_WKUPDBC_4096SCLK (4 << SUPC_WUMR_WKUPDBC_SHIFT) /* Input active at least 4096 SLCK periods */
-# define SUPC_WUMR_WKUPDBC_32768SCLK (5 << SUPC_WUMR_WKUPDBC_SHIFT) /* Input active at least 32768 SLCK periods */
-
-#define SUPC_WUIR_WKUPEN_SHIFT (0) /* Bits 0-15: Wake Up Input Enable 0 to 15 */
-#define SUPC_WUIR_WKUPEN_MASK (0xffff << SUPC_WUIR_WKUPEN_SHIFT)
-#define SUPC_WUIR_WKUPEN(n) ((1 << (n)) << SUPC_WUIR_WKUPEN_SHIFT)
-#define SUPC_WUIR_WKUPT_SHIFT (16) /* Bits 16-31 Wake Up Input Transition 0 to 15 */
-#define SUPC_WUIR_WKUPT_MASK (0xffff << SUPC_WUIR_WKUPT_SHIFT)
-#define SUPC_WUIR_WKUPT(n) ((1 << (n)) << SUPC_WUIR_WKUPT_SHIFT)
-
-#define SUPC_SR_FWUPS (1 << 0) /* Bit 0: FWUP Wake Up Status */
-#define SUPC_SR_WKUPS (1 << 1) /* Bit 1: WKUP Wake Up Status */
-#define SUPC_SR_SMWS (1 << 2) /* Bit 2: Supply Monitor Detection Wake Up Status */
-#define SUPC_SR_BODRSTS (1 << 3) /* Bit 3: Brownout Detector Reset Status */
-#define SUPC_SR_SMRSTS (1 << 4) /* Bit 4: Supply Monitor Reset Status */
-#define SUPC_SR_SMS (1 << 5) /* Bit 5: Supply Monitor Status */
-#define SUPC_SR_SMOS (1 << 6) /* Bit 6: Supply Monitor Output Status */
-#define SUPC_SR_OSCSEL (1 << 7) /* Bit 7: 32-kHz Oscillator Selection Status */
-#define SUPC_SR_FWUPIS (1 << 12) /* Bit 12: FWUP Input Status */
-#define SUPC_SR_WKUPIS_SHIFT (16) /* Bits 16-31: WKUP Input Status 0 to 15 */
-#define SUPC_SR_WKUPIS_MASK (0xffff << SUPC_SR_WKUPIS_SHIFT)
-
-/****************************************************************************************
- * Public Types
- ****************************************************************************************/
-
-/****************************************************************************************
- * Public Data
- ****************************************************************************************/
-
-/****************************************************************************************
- * Public Functions
- ****************************************************************************************/
-
-#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_SUPC_H */
+/**************************************************************************************** + * arch/arm/src/sam3u/sam3u_supc.h + * + * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_SUPC_H +#define __ARCH_ARM_SRC_SAM3U_SAM3U_SUPC_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +#include <nuttx/config.h> + +#include "chip.h" +#include "sam3u_memorymap.h" + +/**************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************/ + +/* SUPC register offsets ****************************************************************/ + +#define SAM3U_SUPC_CR_OFFSET 0x00 /* Supply Controller Control Register */ +#define SAM3U_SUPC_SMMR_OFFSET 0x04 /* Supply Controller Supply Monitor Mode Register */ +#define SAM3U_SUPC_MR_OFFSET 0x08 /* Supply Controller Mode Register */ +#define SAM3U_SUPC_WUMR_OFFSET 0x0c /* Supply Controller Wake Up Mode Register */ +#define SAM3U_SUPC_WUIR_OFFSET 0x10 /* Supply Controller Wake Up Inputs Register */ +#define SAM3U_SUPC_SR_OFFSET 0x14 /* Supply Controller Status Register */ + +/* SUPC register adresses ***************************************************************/ + +#define SAM3U_SUPC_CR (SAM3U_SUPC_BASE+SAM3U_SUPC_CR_OFFSET) +#define SAM3U_SUPC_SMMR (SAM3U_SUPC_BASE+SAM3U_SUPC_SMMR_OFFSET) +#define SAM3U_SUPC_MR (SAM3U_SUPC_BASE+SAM3U_SUPC_MR_OFFSET) +#define SAM3U_SUPC_WUMR (SAM3U_SUPC_BASE+SAM3U_SUPC_WUMR_OFFSET) +#define SAM3U_SUPC_WUIR (SAM3U_SUPC_BASE+SAM3U_SUPC_WUIR_OFFSET) +#define SAM3U_SUPC_SR (SAM3U_SUPC_BASE+SAM3U_SUPC_SR_OFFSET) + +/* SUPC register bit definitions ********************************************************/ + +#define SUPC_CR_VROFF (1 << 2) /* Bit 2: Voltage Regulator Off */ +#define SUPC_CR_XTALSEL (1 << 3) /* Bit 3: Crystal Oscillator Select */ +#define SUPC_CR_KEY_SHIFT (24) /* Bits 24-31: Password */ +#define SUPC_CR_KEY_MASK (0xff << SUPC_CR_KEY_SHIFT) + +#define SUPC_SMMR_SMTH_SHIFT (0) /* Bits 0-3: Supply Monitor Threshold */ +#define SUPC_SMMR_SMTH_MASK (15 << SUPC_SMMR_SMTH_SHIFT) +# define SUPC_SMMR_SMTH_1p9V (0 << SUPC_SMMR_SMTH_SHIFT) /* 1.9V */ +# define SUPC_SMMR_SMTH_2p0V (1 << SUPC_SMMR_SMTH_SHIFT) /* 2.0V */ +# define SUPC_SMMR_SMTH_2p1V (2 << SUPC_SMMR_SMTH_SHIFT) /* 2.1V */ +# define SUPC_SMMR_SMTH_2p2V (3 << SUPC_SMMR_SMTH_SHIFT) /* 2.2V */ +# define SUPC_SMMR_SMTH_2p3V (4 << SUPC_SMMR_SMTH_SHIFT) /* 2.3V */ +# define SUPC_SMMR_SMTH_2p4V (5 << SUPC_SMMR_SMTH_SHIFT) /* 2.4V */ +# define SUPC_SMMR_SMTH_2p5V (6 << SUPC_SMMR_SMTH_SHIFT) /* 2.5V */ +# define SUPC_SMMR_SMTH_2p6V (7 << SUPC_SMMR_SMTH_SHIFT) /* 2.6V */ +# define SUPC_SMMR_SMTH_2p7V (8 << SUPC_SMMR_SMTH_SHIFT) /* 2.7V */ +# define SUPC_SMMR_SMTH_2p8V (9 << SUPC_SMMR_SMTH_SHIFT) /* 2.8V */ +# define SUPC_SMMR_SMTH_2p9V (10 << SUPC_SMMR_SMTH_SHIFT) /* 2.9V */ +# define SUPC_SMMR_SMTH_3p0V (11 << SUPC_SMMR_SMTH_SHIFT) /* 3.0V */ +# define SUPC_SMMR_SMTH_3p1V (12 << SUPC_SMMR_SMTH_SHIFT) /* 3.1V */ +# define SUPC_SMMR_SMTH_3p2V (13 << SUPC_SMMR_SMTH_SHIFT) /* 3.2V */ +# define SUPC_SMMR_SMTH_3p3V (14 << SUPC_SMMR_SMTH_SHIFT) /* 3.3V */ +# define SUPC_SMMR_SMTH_3p4V (15 << SUPC_SMMR_SMTH_SHIFT) /* 3.4V */ +#define SUPC_SMMR_SMSMPL_SHIFT (8) /* Bits 8-10: Supply Monitor Sampling Period */ +#define SUPC_SMMR_SMSMPL_MASK (7 << SUPC_SMMR_SMSMPL_SHIFT) +# define SUPC_SMMR_SMSMPL_SMD (0 << SUPC_SMMR_SMSMPL_SHIFT) /* Supply Monitor disabled */ +# define SUPC_SMMR_SMSMPL_CSM (1 << SUPC_SMMR_SMSMPL_SHIFT) /* Continuous Supply Monitor */ +# define SUPC_SMMR_SMSMPL_32SLCK (2 << SUPC_SMMR_SMSMPL_SHIFT) /* Eevery 32 SLCK periods */ +# define SUPC_SMMR_SMSMPL_256SLCK (3 << SUPC_SMMR_SMSMPL_SHIFT) /* Every 256 SLCK periods */ +# define SUPC_SMMR_SMSMPL_2048SLCK (4 << SUPC_SMMR_SMSMPL_SHIFT) /* Every 2,048 SLCK periods */ +#define SUPC_SMMR_SMRSTEN (1 << 12) /* Bit 12: Supply Monitor Reset Enable */ +#define SUPC_SMMR_SMIEN (1 << 13) /* Bit 13: Supply Monitor Interrupt Enable */ + +#define SUPC_MR_BODRSTEN (1 << 12) /* Bit 12: Brownout Detector Reset Enable */ +#define SUPC_MR_BODDIS (1 << 13) /* Bit 13: Brownout Detector Disable */ +#define SUPC_MR_VDDIORDY (1 << 14) /* Bit 14: VDDIO Ready */ +#define SUPC_MR_OSCBYPASS (1 << 20) /* Bit 20: Oscillator Bypass */ +#define SUPC_MR_KEY_SHIFT (24) /* Bits 24-31: Password Key */ +#define SUPC_MR_KEY_MASK (0xff << SUPC_MR_KEY_SHIFT) + +#define SUPC_WUMR_FWUPEN (1 << 0) /* Bit 0: Force Wake Up Enable */ +#define SUPC_WUMR_SMEN (1 << 1) /* Bit 1: Supply Monitor Wake Up Enable */ +#define SUPC_WUMR_RTTEN (1 << 2) /* Bit 2: Real Time Timer Wake Up Enable */ +#define SUPC_WUMR_RTCEN (1 << 3) /* Bit 3: Real Time Clock Wake Up Enable */ +#define SUPC_WUMR_FWUPDBC_SHIFT (8) /* Bits 8-10: Force Wake Up Debouncer */ +#define SUPC_WUMR_FWUPDBC_MASK (7 << SUPC_WUMR_FWUPDBC_SHIFT) + #define SUPC_WUMR_FWUPDBC_1SCLK (0 << SUPC_WUMR_FWUPDBC_SHIFT) /* Immediate, no debouncing */ + #define SUPC_WUMR_FWUPDBC_3SCLK (1 << SUPC_WUMR_FWUPDBC_SHIFT) /* FWUP at least 3 SLCK periods */ + #define SUPC_WUMR_FWUPDBC_32SCLK (2 << SUPC_WUMR_FWUPDBC_SHIFT) /* FWUP at least 32 SLCK periods */ + #define SUPC_WUMR_FWUPDBC_512SCLK (3 << SUPC_WUMR_FWUPDBC_SHIFT) /* FWUP at least 512 SLCK periods */ + #define SUPC_WUMR_FWUPDBC_4096SCLK (4 << SUPC_WUMR_FWUPDBC_SHIFT) /* FWUP at least 4096 SLCK periods */ + #define SUPC_WUMR_FWUPDBC_32768SCLK (5 << SUPC_WUMR_FWUPDBC_SHIFT) /* FWUP at least 32768 SLCK periods */ +#define SUPC_WUMR_WKUPDBC_SHIFT (12) /* Bits 12-14: Wake Up Inputs Debouncer */ +#define SUPC_WUMR_WKUPDBC_MASK (7 << SUPC_WUMR_WKUPDBC_SHIFT) +# define SUPC_WUMR_WKUPDBC_1SCLK (0 << SUPC_WUMR_WKUPDBC_SHIFT) /* Immediate, no debouncing */ +# define SUPC_WUMR_WKUPDBC_3SCLK (1 << SUPC_WUMR_WKUPDBC_SHIFT) /* Input active at least 3 SLCK periods */ +# define SUPC_WUMR_WKUPDBC_32SCLK (2 << SUPC_WUMR_WKUPDBC_SHIFT) /* Input active at least 32 SLCK periods */ +# define SUPC_WUMR_WKUPDBC_512SCLK (3 << SUPC_WUMR_WKUPDBC_SHIFT) /* Input active at least 512 SLCK periods */ +# define SUPC_WUMR_WKUPDBC_4096SCLK (4 << SUPC_WUMR_WKUPDBC_SHIFT) /* Input active at least 4096 SLCK periods */ +# define SUPC_WUMR_WKUPDBC_32768SCLK (5 << SUPC_WUMR_WKUPDBC_SHIFT) /* Input active at least 32768 SLCK periods */ + +#define SUPC_WUIR_WKUPEN_SHIFT (0) /* Bits 0-15: Wake Up Input Enable 0 to 15 */ +#define SUPC_WUIR_WKUPEN_MASK (0xffff << SUPC_WUIR_WKUPEN_SHIFT) +#define SUPC_WUIR_WKUPEN(n) ((1 << (n)) << SUPC_WUIR_WKUPEN_SHIFT) +#define SUPC_WUIR_WKUPT_SHIFT (16) /* Bits 16-31 Wake Up Input Transition 0 to 15 */ +#define SUPC_WUIR_WKUPT_MASK (0xffff << SUPC_WUIR_WKUPT_SHIFT) +#define SUPC_WUIR_WKUPT(n) ((1 << (n)) << SUPC_WUIR_WKUPT_SHIFT) + +#define SUPC_SR_FWUPS (1 << 0) /* Bit 0: FWUP Wake Up Status */ +#define SUPC_SR_WKUPS (1 << 1) /* Bit 1: WKUP Wake Up Status */ +#define SUPC_SR_SMWS (1 << 2) /* Bit 2: Supply Monitor Detection Wake Up Status */ +#define SUPC_SR_BODRSTS (1 << 3) /* Bit 3: Brownout Detector Reset Status */ +#define SUPC_SR_SMRSTS (1 << 4) /* Bit 4: Supply Monitor Reset Status */ +#define SUPC_SR_SMS (1 << 5) /* Bit 5: Supply Monitor Status */ +#define SUPC_SR_SMOS (1 << 6) /* Bit 6: Supply Monitor Output Status */ +#define SUPC_SR_OSCSEL (1 << 7) /* Bit 7: 32-kHz Oscillator Selection Status */ +#define SUPC_SR_FWUPIS (1 << 12) /* Bit 12: FWUP Input Status */ +#define SUPC_SR_WKUPIS_SHIFT (16) /* Bits 16-31: WKUP Input Status 0 to 15 */ +#define SUPC_SR_WKUPIS_MASK (0xffff << SUPC_SR_WKUPIS_SHIFT) + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +/**************************************************************************************** + * Public Data + ****************************************************************************************/ + +/**************************************************************************************** + * Public Functions + ****************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_SUPC_H */ diff --git a/nuttx/arch/arm/src/sam3u/sam3u_tc.h b/nuttx/arch/arm/src/sam3u/sam3u_tc.h index 1c330d38b..0fb36da97 100644 --- a/nuttx/arch/arm/src/sam3u/sam3u_tc.h +++ b/nuttx/arch/arm/src/sam3u/sam3u_tc.h @@ -1,347 +1,347 @@ -/************************************************************************************************
- * arch/arm/src/sam3u/sam3u_tc.h
- *
- * Copyright (C) 2009 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_TC_H
-#define __ARCH_ARM_SRC_SAM3U_SAM3U_TC_H
-
-/************************************************************************************************
- * Included Files
- ************************************************************************************************/
-
-#include <nuttx/config.h>
-
-#include "chip.h"
-#include "sam3u_memorymap.h"
-
-/************************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************************/
-
-/* TC register offsets **************************************************************************/
-
-/* Timer channel offsets (with respect to timer base offset 0f 0x00, 0x40, or 0x80 */
-
-#define SAM3U_TCN_OFFSET(n) (0x00 + ((n)<<6)) /* 0x00, 0x40, 0x80 */
-#define SAM3U_TCN_CCR_OFFSET 0x00 /* Channel Control Register */
-#define SAM3U_TCN_CMR_OFFSET 0x04 /* Channel Mode Register */
- /* 0x08 Reserved */
- /* 0x0c Reserved */
-#define SAM3U_TCN_CV_OFFSET 0x10 /* Counter Value */
-#define SAM3U_TCN_RA_OFFSET 0x14 /* Register A */
-#define SAM3U_TCN_RB_OFFSET 0x18 /* Register B */
-#define SAM3U_TCN_RC_OFFSET 0x1c /* Register C */
-#define SAM3U_TCN_SR_OFFSET 0x20 /* Status Register */
-#define SAM3U_TCN_IER_OFFSET 0x24 /* Interrupt Enable Register */
-#define SAM3U_TCN_IDR_OFFSET 0x28 /* Interrupt Disable Register */
-#define SAM3U_TCN_IMR_OFFSET 0x2c /* Interrupt Mask Register */
-
-/* Timer common registers */
-
-#define SAM3U_TC_BCR_OFFSET 0xc0 /* Block Control Register */
-#define SAM3U_TC_BMR_OFFSET 0xc4 /* Block Mode Register */
-#define SAM3U_TC_QIER_OFFSET 0xc8 /* QDEC Interrupt Enable Register */
-#define SAM3U_TC_QIDR_OFFSET 0xcc /* QDEC Interrupt Disable Register */
-#define SAM3U_TC_QIMR_OFFSET 0xd0 /* QDEC Interrupt Mask Register */
-#define SAM3U_TC_QISR_OFFSET 0xd4 /* QDEC Interrupt Status Register */
- /* 0xd8 Reserved */
- /* 0xe4 Reserved */
-
-/* TC register adresses *************************************************************************/
-
-/* Timer channel offsets (with respect to timer base offset 0f 0x00, 0x40, or 0x80 */
-
-#define SAM3U_TC_CCR(n) (SAM3U_TCN_BASE(n)+SAM3U_TCN_CCR_OFFSET)
-#define SAM3U_TC_CMR(n) (SAM3U_TCN_BASE(n)+SAM3U_TCN_CMR_OFFSET)
-#define SAM3U_TC_CV(n) (SAM3U_TCN_BASE(n)+SAM3U_TCN_CV_OFFSET)
-#define SAM3U_TC_RA(n) (SAM3U_TCN_BASE(n)+SAM3U_TCN_RA_OFFSET)
-#define SAM3U_TC_RB(n) (SAM3U_TCN_BASE(n)+SAM3U_TCN_RB_OFFSET)
-#define SAM3U_TC_RC(n) (SAM3U_TCN_BASE(n)+SAM3U_TCN_RC_OFFSET)
-#define SAM3U_TC_SR(n) (SAM3U_TCN_BASE(n)+SAM3U_TCN_SR_OFFSET)
-#define SAM3U_TC_IER(n) (SAM3U_TCN_BASE(n)+SAM3U_TCN_IER_OFFSET)
-#define SAM3U_TC_IDR(n) (SAM3U_TCN_BASE(n)+SAM3U_TCN_IDR_OFFSET)
-#define SAM3U_TC_IMR(n) (SAM3U_TCN_BASE(n)+SAM3U_TCN_IMR_OFFSET)
-
-#define SAM3U_TC0_CCR (SAM3U_TC0_BASE+SAM3U_TCN_CCR_OFFSET)
-#define SAM3U_TC0_CMR (SAM3U_TC0_BASE+SAM3U_TCN_CMR_OFFSET)
-#define SAM3U_TC0_CV (SAM3U_TC0_BASE+SAM3U_TCN_CV_OFFSET)
-#define SAM3U_TC0_RA (SAM3U_TC0_BASE+SAM3U_TCN_RA_OFFSET)
-#define SAM3U_TC0_RB (SAM3U_TC0_BASE+SAM3U_TCN_RB_OFFSET)
-#define SAM3U_TC0_RC (SAM3U_TC0_BASE+SAM3U_TCN_RC_OFFSET)
-#define SAM3U_TC0_SR (SAM3U_TC0_BASE+SAM3U_TCN_SR_OFFSET)
-#define SAM3U_TC0_IER (SAM3U_TC0_BASE+SAM3U_TCN_IER_OFFSET)
-#define SAM3U_TC0_IDR (SAM3U_TC0_BASE+SAM3U_TCN_IDR_OFFSET)
-#define SAM3U_TC0_IMR (SAM3U_TC0_BASE+SAM3U_TCN_IMR_OFFSET)
-
-#define SAM3U_TC1_CCR (SAM3U_TC1_BASE+SAM3U_TCN_CCR_OFFSET)
-#define SAM3U_TC1_CMR (SAM3U_TC1_BASE+SAM3U_TCN_CMR_OFFSET)
-#define SAM3U_TC1_CV (SAM3U_TC1_BASE+SAM3U_TCN_CV_OFFSET)
-#define SAM3U_TC1_RA (SAM3U_TC1_BASE+SAM3U_TCN_RA_OFFSET)
-#define SAM3U_TC1_RB (SAM3U_TC1_BASE+SAM3U_TCN_RB_OFFSET)
-#define SAM3U_TC1_RC (SAM3U_TC1_BASE+SAM3U_TCN_RC_OFFSET)
-#define SAM3U_TC1_SR (SAM3U_TC1_BASE+SAM3U_TCN_SR_OFFSET)
-#define SAM3U_TC1_IER (SAM3U_TC1_BASE+SAM3U_TCN_IER_OFFSET)
-#define SAM3U_TC1_IDR (SAM3U_TC1_BASE+SAM3U_TCN_IDR_OFFSET)
-#define SAM3U_TC1_IMR (SAM3U_TC1_BASE+SAM3U_TCN_IMR_OFFSET)
-
-#define SAM3U_TC2_CCR (SAM3U_TC2_BASE+SAM3U_TCN_CCR_OFFSET)
-#define SAM3U_TC2_CMR (SAM3U_TC2_BASE+SAM3U_TCN_CMR_OFFSET)
-#define SAM3U_TC2_CV (SAM3U_TC2_BASE+SAM3U_TCN_CV_OFFSET)
-#define SAM3U_TC2_RA (SAM3U_TC2_BASE+SAM3U_TCN_RA_OFFSET)
-#define SAM3U_TC2_RB (SAM3U_TC2_BASE+SAM3U_TCN_RB_OFFSET)
-#define SAM3U_TC2_RC (SAM3U_TC2_BASE+SAM3U_TCN_RC_OFFSET)
-#define SAM3U_TC2_SR (SAM3U_TC2_BASE+SAM3U_TCN_SR_OFFSET)
-#define SAM3U_TC2_IER (SAM3U_TC2_BASE+SAM3U_TCN_IER_OFFSET)
-#define SAM3U_TC2_IDR (SAM3U_TC2_BASE+SAM3U_TCN_IDR_OFFSET)
-#define SAM3U_TC2_IMR (SAM3U_TC2_BASE+SAM3U_TCN_IMR_OFFSET)
-
-/* Timer common registers */
-
-#define SAM3U_TC_BCR (SAM3U_TC_BASE+SAM3U_TC_BCR_OFFSET)
-#define SAM3U_TC_BMR (SAM3U_TC_BASE+SAM3U_TC_BMR_OFFSET)
-#define SAM3U_TC_QIER (SAM3U_TC_BASE+SAM3U_TC_QIER_OFFSET)
-#define SAM3U_TC_QIDR (SAM3U_TC_BASE+SAM3U_TC_QIDR_OFFSET)
-#define SAM3U_TC_QIMR (SAM3U_TC_BASE+SAM3U_TC_QIMR_OFFSET)
-#define SAM3U_TC_QISR (SAM3U_TC_BASE+SAM3U_TC_QISR_OFFSET)
-
-/* TC register bit definitions ******************************************************************/
-
-/* Timer common registers */
-/* TC Block Control Register */
-
-#define TC_BCR_SYNC (1 << 0) /* Bit 0: Synchro Command
-
-/* TC Block Mode Register */
-
-#define TC_BMR_TC0XC0S_SHIFT (0) /* Bits 0-1: External Clock Signal 0 Selection */
-#define TC_BMR_TC0XC0S_MASK (3 << TC_BMR_TC0XC0S_SHIFT)
-# define TC_BMR_TC0XC0S_TCLK0 (0 << TC_BMR_TC0XC0S_SHIFT)
-# define TC_BMR_TC0XC0S_NONE (1 << TC_BMR_TC0XC0S_SHIFT)
-# define TC_BMR_TC0XC0S_TIOA1 (2 << TC_BMR_TC0XC0S_SHIFT)
-# define TC_BMR_TC0XC0S_TIOA2 (3 << TC_BMR_TC0XC0S_SHIFT)
-#define TC_BMR_TC1XC1S_SHIFT (2) /* Bits 2-3: External Clock Signal 1 Selection */
-#define TC_BMR_TC1XC1S_MASK (3 << TC_BMR_TC1XC1S_MASK)
-# define TC_BMR_TC1XC1S_TCLK1 (0 << TC_BMR_TC1XC1S_SHIFT)
-# define TC_BMR_TC1XC1S_NONE (1 << TC_BMR_TC1XC1S_SHIFT)
-# define TC_BMR_TC1XC1S_TIOA0 (2 << TC_BMR_TC1XC1S_SHIFT)
-# define TC_BMR_TC1XC1S_TIOA2 (3 << TC_BMR_TC1XC1S_SHIFT)
-#define TC_BMR_TC2XC2S_SHIFT (4) /* Bits 4-5: External Clock Signal 2 Selection */
-#define TC_BMR_TC2XC2S_MASK (3 << TC_BMR_TC2XC2S_SHIFT)
-# define TC_BMR_TC2XC2S_TCLK2 (0 << TC_BMR_TC2XC2S_SHIFT)
-# define TC_BMR_TC2XC2S_NONE (1 << TC_BMR_TC2XC2S_SHIFT)
-# define TC_BMR_TC2XC2S_TIOA0 (2 << TC_BMR_TC2XC2S_SHIFT)
-# define TC_BMR_TC2XC2S_TIOA1 (3 << TC_BMR_TC2XC2S_SHIFT)
-#define TC_BMR_QDEN (1 << 8) /* Bit 8: Quadrature Decoder Enabled */
-#define TC_BMR_POSEN (1 << 9) /* Bit 9: Position Enabled */
-#define TC_BMR_SPEEDEN (1 << 10) /* Bit 10: Speed Enabled */
-#define TC_BMR_QDTRANS (1 << 11) /* Bit 11: Quadrature Decoding Transparent */
-#define TC_BMR_EDGPHA (1 << 12) /* Bit 12: Edge on PHA count mode */
-#define TC_BMR_INVA (1 << 13) /* Bit 13: Inverted PHA */
-#define TC_BMR_INVB (1 << 14) /* Bit 14: Inverted PHB */
-#define TC_BMR_SWAP (1 << 15) /* Bit 15: Swap PHA and PHB */
-#define TC_BMR_INVIDX (1 << 16) /* Bit 16: Inverted Index */
-#define TC_BMR_IDXPHB (1 << 17) /* Bit 17: Index pin is PHB pin */
-#define TC_BMR_FILTER (1 << 19) /* Bit 19 */
-#define TC_BMR_MAXFILT_SHIFT (20) /* Bits 20-25: Maximum Filter */
-#define TC_BMR_MAXFILT_MASK (63 << TC_BMR_MAXFILT_SHIFT)
-
-/* TC QDEC Interrupt Enable Register, TC QDEC Interrupt Disable Register,
- * TC QDEC Interrupt Mask Register, TC QDEC Interrupt Status Register common
- * bit field definitions
- */
-
-#define TC_QINT_IDX (1 << 0) /* Bit 0: Index (Common) */
-#define TC_QINT_DIRCHG (1 << 1) /* Bit 1: Direction Change (Common) */
-#define TC_QINT_QERR (1 << 2) /* Bit 2: Quadrature Error (Common) */
-#define TC_QISR_DIR (1 << 8) /* Bit 8: Direction (QISR only) */
-
-/* Timer Channel Registers */
-/* TC Channel Control Register */
-
-#define TCN_CCR_CLKEN (1 << 0) /* Bit 0: Counter Clock Enable Command */
-#define TCN_CCR_CLKDIS (1 << 1) /* Bit 1: Counter Clock Disable Command */
-#define TCN_CCR_SWTRG (1 << 2) /* Bit 2: Software Trigger Command */
-
-/* TC Channel Mode Register */
-
-#define TCN_CMR_TCCLKS_SHIFT (0) /* Bits 0-2: Clock Selection (Common) */
-#define TCN_CMR_TCCLKS_MASK (7 << TCN_CMR_TCCLKS_SHIFT)
-# define TCN_CMR_TCCLKS_TIMERCLOCK1 (0 << TCN_CMR_TCCLKS_SHIFT)
-# define TCN_CMR_TCCLKS_TIMERCLOCK2 (1 << TCN_CMR_TCCLKS_SHIFT)
-# define TCN_CMR_TCCLKS_TIMERCLOCK3 (2 << TCN_CMR_TCCLKS_SHIFT)
-# define TCN_CMR_TCCLKS_TIMERCLOCK4 (3 << TCN_CMR_TCCLKS_SHIFT)
-# define TCN_CMR_TCCLKS_TIMERCLOCK5 (4 << TCN_CMR_TCCLKS_SHIFT)
-# define TCN_CMR_TCCLKS_XC0 (5 << TCN_CMR_TCCLKS_SHIFT)
-# define TCN_CMR_TCCLKS_XC1 (6 << TCN_CMR_TCCLKS_SHIFT)
-# define TCN_CMR_TCCLKS_XC2 (7 << TCN_CMR_TCCLKS_SHIFT)
-#define TCN_CMR_CLKI (1 << 3) /* Bit 3: Clock Invert (Common) */
-#define TCN_CMR_BURST_SHIFT (4) /* Bits 4-5: Burst Signal Selection (Common) */
-#define TCN_CMR_BURST_MASK (3 << TCN_CMR_BURST_MASK)
-#define TCN_CMR_BURST_MASK (3 << TCN_CMR_BURST_MASK)
-# define TCN_CMR_BURST_NOTGATED (0 << TCN_CMR_BURST_MASK) /* Nott gated by external signal */
-# define TCN_CMR_BURST_XC0 (1 << TCN_CMR_BURST_MASK) /* XC0 ANDed with selected clock */
-# define TCN_CMR_BURST_XC1 (2 << TCN_CMR_BURST_MASK) /* XC1 ANDed with selected clock */
-# define TCN_CMR_BURST_XC2 (3 << TCN_CMR_BURST_MASK) /* XC2 ANDed with selected clock */
-#define TCN_CMR_WAVE (1 << 15) /* Bit 15: (Common) */
-
-#define TCN_CMR_LDBSTOP (1 << 6) /* Bit 6: Counter stopped with RB Loading (Capture mode) */
-#define TCN_CMR_LDBDIS (1 << 7) /* Bit 7: Counter disable with RB Loading (Capture mode) */
-#define TCN_CMR_ETRGEDG_SHIFT (8) /* Bits 8-9: External Trigger Edge Selection (Capture mode) */
-#define TCN_CMR_ETRGEDG_MASK (3 << TCN_CMR_ETRGEDG_SHIFT)
-# define TCN_CMR_ETRGEDG_NONE (0 << TCN_CMR_ETRGEDG_SHIFT) /* None */
-# define TCN_CMR_ETRGEDG_REDGE (1 << TCN_CMR_ETRGEDG_SHIFT) /* Rising edge */
-# define TCN_CMR_ETRGEDG_FEDGE (2 << TCN_CMR_ETRGEDG_SHIFT) /* Falling edge */
-# define TCN_CMR_ETRGEDG_EACH (3 << TCN_CMR_ETRGEDG_SHIFT) /* Each */
-#define TCN_CMR_ABETRG (1 << 10) /* Bit 10: TIOA or TIOB External Trigger Selection (Capture mode) */
-#define TCN_CMR_CPCTRG (1 << 14) /* Bit 14: RC Compare Trigger Enable (Capture mode) */
-#define TCN_CMR_LDRA_SHIFT (16) /* Bits 16-17: RA Loading Selection (Capture mode) */
-#define TCN_CMR_LDRA_MASK (3 << TCN_CMR_LDRA_SHIFT)
-# define TCN_CMR_LDRA_NONE (0 << TCN_CMR_LDRA_SHIFT) /* None */
-# define TCN_CMR_LDRA_REDGE (1 << TCN_CMR_LDRA_SHIFT) /* Rising edge of TIOA */
-# define TCN_CMR_LDRA_FEDGE (2 << TCN_CMR_LDRA_SHIFT) /* Falling edge of TIOA */
-# define TCN_CMR_LDRA_EACH (3 << TCN_CMR_LDRA_SHIFT) /* Each edge of TIOA */
-#define TCN_CMR_LDRB_SHIFT (18) /* Bits 18-19: RB Loading Selection (Capture mode) */
-#define TCN_CMR_LDRB_MASK (3 << TCN_CMR_LDRB_SHIFT)
-# define TCN_CMR_LDRB_NONE (0 << TCN_CMR_LDRB_SHIFT) /* None */
-# define TCN_CMR_LDRB_REDGE (1 << TCN_CMR_LDRB_SHIFT) /* Rising edge of TIOB */
-# define TCN_CMR_LDRB_FEDGE (2 << TCN_CMR_LDRB_SHIFT) /* Falling edge of TIOB */
-# define TCN_CMR_LDRB_EACH (3 << TCN_CMR_LDRB_SHIFT) /* Each edge of TIOB */
-
-#define TCN_CMR_CPCSTOP (1 << 6) /* Bit 6: Counter Clock Stopped with RC Compare (Waveform mode) */
-#define TCN_CMR_CPCDIS (1 << 7) /* Bit 7: Counter Clock Disable with RC Compare (Waveform mode) */
-#define TCN_CMR_EEVTEDG_SHIFT (8) /* Bits 8-9: External Event Edge Selection (Waveform mode) */
-#define TCN_CMR_EEVTEDG_MASK (3 << TCN_CMR_EEVTEDG_SHIFT)
-# define TCN_CMR_EEVTEDG_NONE (0 << TCN_CMR_EEVTEDG_SHIFT) /* None */
-# define TCN_CMR_EEVTEDG_REDGE (1 << TCN_CMR_EEVTEDG_SHIFT) /* Rising edge */
-# define TCN_CMR_EEVTEDG_FEDGE (2 << TCN_CMR_EEVTEDG_SHIFT) /* Falling edge */
-# define TCN_CMR_EEVTEDG_EACH (3 << TCN_CMR_EEVTEDG_SHIFT) /* Each edge */
-#define TCN_CMR_EEVT_SHIFT (10) /* Bits 10-11: External Event Selection (Waveform mode) */
-#define TCN_CMR_EEVT_MASK (3 << TCN_CMR_EEVT_SHIFT)
-# define TCN_CMR_EEVT_TIOB (0 << TCN_CMR_EEVT_SHIFT) /* TIOB input */
-# define TCN_CMR_EEVT_XC0 (1 << TCN_CMR_EEVT_SHIFT) /* XC0 output */
-# define TCN_CMR_EEVT_XC1 (2 << TCN_CMR_EEVT_SHIFT) /* XC1 output */
-# define TCN_CMR_EEVT_XC2 (3 << TCN_CMR_EEVT_SHIFT) /* XC2 output */
-#define TCN_CMR_ENETRG (1 << 12) /* Bit 12: External Event Trigger Enable (Waveform mode) */
-#define TCN_CMR_WAVSEL_SHIFT (13) /* Bits 13-14: Waveform Selection (Waveform mode) */
-#define TCN_CMR_WAVSEL_MASK (3 << TCN_CMR_WAVSEL_SHIFT)
-# define TCN_CMR_WAVSEL_UP (0 << TCN_CMR_WAVSEL_SHIFT) /* UP mode w/o auto trigger (Waveform mode) */
-# define TCN_CMR_WAVSEL_UPAUTO (1 << TCN_CMR_WAVSEL_SHIFT) /* UP mode with auto trigger (Waveform mode) */
-# define TCN_CMR_WAVSEL_UPDWN (2 << TCN_CMR_WAVSEL_SHIFT) /* UPDOWN mode w/o auto trigger (Waveform mode) */
-# define TCN_CMR_WAVSEL_UPDWNAUTO (3 << TCN_CMR_WAVSEL_SHIFT) /* UPDOWN mode with auto trigger (Waveform mode) */
-#define TCN_CMR_ACPA_SHIFT (16) /* Bits 16-17: RA Compare Effect on TIOA (Waveform mode) */
-#define TCN_CMR_ACPA_MASK (3 << TCN_CMR_ACPA_SHIFT)
-# define TCN_CMR_ACPA_NONE (0 << TCN_CMR_ACPA_SHIFT)
-# define TCN_CMR_ACPA_SET (1 << TCN_CMR_ACPA_SHIFT)
-# define TCN_CMR_ACPA_CLEAR (2 << TCN_CMR_ACPA_SHIFT)
-# define TCN_CMR_ACPA_TOGGLE (3 << TCN_CMR_ACPA_SHIFT)
-#define TCN_CMR_ACPC_SHIFT (18) /* Bits 18-19: RC Compare Effect on TIOA (Waveform mode) */
-#define TCN_CMR_ACPC_MASK (3 << TCN_CMR_ACPC_SHIFT)
-# define TCN_CMR_ACPC_NONE (0 << TCN_CMR_ACPC_SHIFT)
-# define TCN_CMR_ACPC_SET (1 << TCN_CMR_ACPC_SHIFT)
-# define TCN_CMR_ACPC_CLEAR (2 << TCN_CMR_ACPC_SHIFT)
-# define TCN_CMR_ACPC_TOGGLE (3 << TCN_CMR_ACPC_SHIFT)
-#define TCN_CMR_AEEVT_SHIFT (20) /* Bits 20-21: External Event Effect on TIOA (Waveform mode) */
-#define TCN_CMR_AEEVT_MASK (3 << TCN_CMR_AEEVT_SHIFT)
-# define TCN_CMR_AEEVT_NONE (0 << TCN_CMR_AEEVT_SHIFT)
-# define TCN_CMR_AEEVT_SET (1 << TCN_CMR_AEEVT_SHIFT)
-# define TCN_CMR_AEEVT_CLEAR (2 << TCN_CMR_AEEVT_SHIFT)
-# define TCN_CMR_AEEVT_TOGGLE (3 << TCN_CMR_AEEVT_SHIFT)
-#define TCN_CMR_ASWTRG_SHIFT (22) /* Bits 22-23: Software Trigger Effect on TIOA (Waveform mode) */
-#define TCN_CMR_ASWTRG_MASK (3 << TCN_CMR_ASWTRG_SHIFT)
-# define TCN_CMR_ASWTRG_NONE (0 << TCN_CMR_ASWTRG_SHIFT)
-# define TCN_CMR_ASWTRG_SET (1 << TCN_CMR_ASWTRG_SHIFT)
-# define TCN_CMR_ASWTRG_CLEAR (2 << TCN_CMR_ASWTRG_SHIFT)
-# define TCN_CMR_ASWTRG_TOGGLE (3 << TCN_CMR_ASWTRG_SHIFT)
-#define TCN_CMR_BCPB_SHIFT (24) /* Bits 24-25: RB Compare Effect on TIOB (Waveform mode) */
-#define TCN_CMR_BCPB_MASK (3 << TCN_CMR_BCPB_SHIFT)
-# define TCN_CMR_BCPB_NONE (0 << TCN_CMR_BCPB_SHIFT)
-# define TCN_CMR_BCPB_SET (1 << TCN_CMR_BCPB_SHIFT)
-# define TCN_CMR_BCPB_CLEAR (2 << TCN_CMR_BCPB_SHIFT)
-# define TCN_CMR_BCPB_TOGGLE (3 << TCN_CMR_BCPB_SHIFT)
-#define TCN_CMR_BCPC_SHIFT (26) /* Bits 26-27: RC Compare Effect on TIOB (Waveform mode) */
-#define TCN_CMR_BCPC_MASK (3 << TCN_CMR_BCPC_SHIFT)
-# define TCN_CMR_BCPC_NONE (0 << TCN_CMR_BCPC_SHIFT)
-# define TCN_CMR_BCPC_SET (1 << TCN_CMR_BCPC_SHIFT)
-# define TCN_CMR_BCPC_CLEAR (2 << TCN_CMR_BCPC_SHIFT)
-# define TCN_CMR_BCPC_TOGGLE (3 << TCN_CMR_BCPC_SHIFT)
-#define TCN_CMR_BEEVT_SHIFT (28) /* Bits 28-29: External Event Effect on TIOB (Waveform mode) */
-#define TCN_CMR_BEEVT_MASK (3 << TCN_CMR_BEEVT_SHIFT)
-# define TCN_CMR_BEEVT_NONE (0 << TCN_CMR_BEEVT_SHIFT)
-# define TCN_CMR_BEEVT_SET (1 << TCN_CMR_BEEVT_SHIFT)
-# define TCN_CMR_BEEVT_CLEAR (2 << TCN_CMR_BEEVT_SHIFT)
-# define TCN_CMR_BEEVT_TOGGLE (3 << TCN_CMR_BEEVT_SHIFT)
-#define TCN_CMR_BSWTRG_SHIFT (30) /* Bits 30-31: Software Trigger Effect on TIOB (Waveform mode) */
-#define TCN_CMR_BSWTRG_MASK (3 << TCN_CMR_BSWTRG_SHIFT)
-# define TCN_CMR_BSWTRG_NONE (0 << TCN_CMR_BSWTRG_SHIFT)
-# define TCN_CMR_BSWTRG_SET (1 << TCN_CMR_BSWTRG_SHIFT)
-# define TCN_CMR_BSWTRG_CLEAR (2 << TCN_CMR_BSWTRG_SHIFT)
-# define TCN_CMR_BSWTRG_TOGGLE (3 << TCN_CMR_BSWTRG_SHIFT)
-
-/* TC Counter Value Register */
-
-#define TCN_CV_SHIFT (0) /* Bits 0-15: Counter Value */
-#define TCN_CV_MASK (0xffff << TCN_CV_SHIFT)
-
-/* TC Register A, B, C */
-
-#define TCN_RVALUE_SHIFT (0) /* Bits 0-15: Register A, B, or C value */
-#define TCN_RVALUE_MASK (0xffff << TCN_RVALUE_SHIFT)
-
-/* TC Status Register, TC Interrupt Enable Register, TC Interrupt Disable Register, and TC Interrupt Mask Register common bit-field definitions */
-
-#define TCN_INT_COVFS (1 << 0) /* Bit 0: Counter Overflow */
-#define TCN_INT_LOVRS (1 << 1) /* Bit 1: Load Overrun */
-#define TCN_INT_CPAS (1 << 2) /* Bit 2: RA Compare */
-#define TCN_INT_CPBS (1 << 3) /* Bit 3: RB Compare */
-#define TCN_INT_CPCS (1 << 4) /* Bit 4: RC Compare */
-#define TCN_INT_LDRAS (1 << 5) /* Bit 5: RA Loading */
-#define TCN_INT_LDRBS (1 << 6) /* Bit 6: RB Loading */
-#define TCN_INT_ETRGS (1 << 7) /* Bit 7: External Trigger */
-#define TCN_INT_CLKSTA (1 << 16) /* Bit 16: Clock Enabling (SR only) */
-#define TCN_SR_MTIOA (1 << 17) /* Bit 17: TIOA Mirror (SR only) */
-#define TCN_SR_MTIOB (1 << 18) /* Bit 18: TIOB Mirror (SR only)*/
-
-/************************************************************************************************
- * Public Types
- ************************************************************************************************/
-
-/************************************************************************************************
- * Public Data
- ************************************************************************************************/
-
-/************************************************************************************************
- * Public Functions
- ************************************************************************************************/
-
-#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_TC_H */
+/************************************************************************************************ + * arch/arm/src/sam3u/sam3u_tc.h + * + * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_TC_H +#define __ARCH_ARM_SRC_SAM3U_SAM3U_TC_H + +/************************************************************************************************ + * Included Files + ************************************************************************************************/ + +#include <nuttx/config.h> + +#include "chip.h" +#include "sam3u_memorymap.h" + +/************************************************************************************************ + * Pre-processor Definitions + ************************************************************************************************/ + +/* TC register offsets **************************************************************************/ + +/* Timer channel offsets (with respect to timer base offset 0f 0x00, 0x40, or 0x80 */ + +#define SAM3U_TCN_OFFSET(n) (0x00 + ((n)<<6)) /* 0x00, 0x40, 0x80 */ +#define SAM3U_TCN_CCR_OFFSET 0x00 /* Channel Control Register */ +#define SAM3U_TCN_CMR_OFFSET 0x04 /* Channel Mode Register */ + /* 0x08 Reserved */ + /* 0x0c Reserved */ +#define SAM3U_TCN_CV_OFFSET 0x10 /* Counter Value */ +#define SAM3U_TCN_RA_OFFSET 0x14 /* Register A */ +#define SAM3U_TCN_RB_OFFSET 0x18 /* Register B */ +#define SAM3U_TCN_RC_OFFSET 0x1c /* Register C */ +#define SAM3U_TCN_SR_OFFSET 0x20 /* Status Register */ +#define SAM3U_TCN_IER_OFFSET 0x24 /* Interrupt Enable Register */ +#define SAM3U_TCN_IDR_OFFSET 0x28 /* Interrupt Disable Register */ +#define SAM3U_TCN_IMR_OFFSET 0x2c /* Interrupt Mask Register */ + +/* Timer common registers */ + +#define SAM3U_TC_BCR_OFFSET 0xc0 /* Block Control Register */ +#define SAM3U_TC_BMR_OFFSET 0xc4 /* Block Mode Register */ +#define SAM3U_TC_QIER_OFFSET 0xc8 /* QDEC Interrupt Enable Register */ +#define SAM3U_TC_QIDR_OFFSET 0xcc /* QDEC Interrupt Disable Register */ +#define SAM3U_TC_QIMR_OFFSET 0xd0 /* QDEC Interrupt Mask Register */ +#define SAM3U_TC_QISR_OFFSET 0xd4 /* QDEC Interrupt Status Register */ + /* 0xd8 Reserved */ + /* 0xe4 Reserved */ + +/* TC register adresses *************************************************************************/ + +/* Timer channel offsets (with respect to timer base offset 0f 0x00, 0x40, or 0x80 */ + +#define SAM3U_TC_CCR(n) (SAM3U_TCN_BASE(n)+SAM3U_TCN_CCR_OFFSET) +#define SAM3U_TC_CMR(n) (SAM3U_TCN_BASE(n)+SAM3U_TCN_CMR_OFFSET) +#define SAM3U_TC_CV(n) (SAM3U_TCN_BASE(n)+SAM3U_TCN_CV_OFFSET) +#define SAM3U_TC_RA(n) (SAM3U_TCN_BASE(n)+SAM3U_TCN_RA_OFFSET) +#define SAM3U_TC_RB(n) (SAM3U_TCN_BASE(n)+SAM3U_TCN_RB_OFFSET) +#define SAM3U_TC_RC(n) (SAM3U_TCN_BASE(n)+SAM3U_TCN_RC_OFFSET) +#define SAM3U_TC_SR(n) (SAM3U_TCN_BASE(n)+SAM3U_TCN_SR_OFFSET) +#define SAM3U_TC_IER(n) (SAM3U_TCN_BASE(n)+SAM3U_TCN_IER_OFFSET) +#define SAM3U_TC_IDR(n) (SAM3U_TCN_BASE(n)+SAM3U_TCN_IDR_OFFSET) +#define SAM3U_TC_IMR(n) (SAM3U_TCN_BASE(n)+SAM3U_TCN_IMR_OFFSET) + +#define SAM3U_TC0_CCR (SAM3U_TC0_BASE+SAM3U_TCN_CCR_OFFSET) +#define SAM3U_TC0_CMR (SAM3U_TC0_BASE+SAM3U_TCN_CMR_OFFSET) +#define SAM3U_TC0_CV (SAM3U_TC0_BASE+SAM3U_TCN_CV_OFFSET) +#define SAM3U_TC0_RA (SAM3U_TC0_BASE+SAM3U_TCN_RA_OFFSET) +#define SAM3U_TC0_RB (SAM3U_TC0_BASE+SAM3U_TCN_RB_OFFSET) +#define SAM3U_TC0_RC (SAM3U_TC0_BASE+SAM3U_TCN_RC_OFFSET) +#define SAM3U_TC0_SR (SAM3U_TC0_BASE+SAM3U_TCN_SR_OFFSET) +#define SAM3U_TC0_IER (SAM3U_TC0_BASE+SAM3U_TCN_IER_OFFSET) +#define SAM3U_TC0_IDR (SAM3U_TC0_BASE+SAM3U_TCN_IDR_OFFSET) +#define SAM3U_TC0_IMR (SAM3U_TC0_BASE+SAM3U_TCN_IMR_OFFSET) + +#define SAM3U_TC1_CCR (SAM3U_TC1_BASE+SAM3U_TCN_CCR_OFFSET) +#define SAM3U_TC1_CMR (SAM3U_TC1_BASE+SAM3U_TCN_CMR_OFFSET) +#define SAM3U_TC1_CV (SAM3U_TC1_BASE+SAM3U_TCN_CV_OFFSET) +#define SAM3U_TC1_RA (SAM3U_TC1_BASE+SAM3U_TCN_RA_OFFSET) +#define SAM3U_TC1_RB (SAM3U_TC1_BASE+SAM3U_TCN_RB_OFFSET) +#define SAM3U_TC1_RC (SAM3U_TC1_BASE+SAM3U_TCN_RC_OFFSET) +#define SAM3U_TC1_SR (SAM3U_TC1_BASE+SAM3U_TCN_SR_OFFSET) +#define SAM3U_TC1_IER (SAM3U_TC1_BASE+SAM3U_TCN_IER_OFFSET) +#define SAM3U_TC1_IDR (SAM3U_TC1_BASE+SAM3U_TCN_IDR_OFFSET) +#define SAM3U_TC1_IMR (SAM3U_TC1_BASE+SAM3U_TCN_IMR_OFFSET) + +#define SAM3U_TC2_CCR (SAM3U_TC2_BASE+SAM3U_TCN_CCR_OFFSET) +#define SAM3U_TC2_CMR (SAM3U_TC2_BASE+SAM3U_TCN_CMR_OFFSET) +#define SAM3U_TC2_CV (SAM3U_TC2_BASE+SAM3U_TCN_CV_OFFSET) +#define SAM3U_TC2_RA (SAM3U_TC2_BASE+SAM3U_TCN_RA_OFFSET) +#define SAM3U_TC2_RB (SAM3U_TC2_BASE+SAM3U_TCN_RB_OFFSET) +#define SAM3U_TC2_RC (SAM3U_TC2_BASE+SAM3U_TCN_RC_OFFSET) +#define SAM3U_TC2_SR (SAM3U_TC2_BASE+SAM3U_TCN_SR_OFFSET) +#define SAM3U_TC2_IER (SAM3U_TC2_BASE+SAM3U_TCN_IER_OFFSET) +#define SAM3U_TC2_IDR (SAM3U_TC2_BASE+SAM3U_TCN_IDR_OFFSET) +#define SAM3U_TC2_IMR (SAM3U_TC2_BASE+SAM3U_TCN_IMR_OFFSET) + +/* Timer common registers */ + +#define SAM3U_TC_BCR (SAM3U_TC_BASE+SAM3U_TC_BCR_OFFSET) +#define SAM3U_TC_BMR (SAM3U_TC_BASE+SAM3U_TC_BMR_OFFSET) +#define SAM3U_TC_QIER (SAM3U_TC_BASE+SAM3U_TC_QIER_OFFSET) +#define SAM3U_TC_QIDR (SAM3U_TC_BASE+SAM3U_TC_QIDR_OFFSET) +#define SAM3U_TC_QIMR (SAM3U_TC_BASE+SAM3U_TC_QIMR_OFFSET) +#define SAM3U_TC_QISR (SAM3U_TC_BASE+SAM3U_TC_QISR_OFFSET) + +/* TC register bit definitions ******************************************************************/ + +/* Timer common registers */ +/* TC Block Control Register */ + +#define TC_BCR_SYNC (1 << 0) /* Bit 0: Synchro Command + +/* TC Block Mode Register */ + +#define TC_BMR_TC0XC0S_SHIFT (0) /* Bits 0-1: External Clock Signal 0 Selection */ +#define TC_BMR_TC0XC0S_MASK (3 << TC_BMR_TC0XC0S_SHIFT) +# define TC_BMR_TC0XC0S_TCLK0 (0 << TC_BMR_TC0XC0S_SHIFT) +# define TC_BMR_TC0XC0S_NONE (1 << TC_BMR_TC0XC0S_SHIFT) +# define TC_BMR_TC0XC0S_TIOA1 (2 << TC_BMR_TC0XC0S_SHIFT) +# define TC_BMR_TC0XC0S_TIOA2 (3 << TC_BMR_TC0XC0S_SHIFT) +#define TC_BMR_TC1XC1S_SHIFT (2) /* Bits 2-3: External Clock Signal 1 Selection */ +#define TC_BMR_TC1XC1S_MASK (3 << TC_BMR_TC1XC1S_MASK) +# define TC_BMR_TC1XC1S_TCLK1 (0 << TC_BMR_TC1XC1S_SHIFT) +# define TC_BMR_TC1XC1S_NONE (1 << TC_BMR_TC1XC1S_SHIFT) +# define TC_BMR_TC1XC1S_TIOA0 (2 << TC_BMR_TC1XC1S_SHIFT) +# define TC_BMR_TC1XC1S_TIOA2 (3 << TC_BMR_TC1XC1S_SHIFT) +#define TC_BMR_TC2XC2S_SHIFT (4) /* Bits 4-5: External Clock Signal 2 Selection */ +#define TC_BMR_TC2XC2S_MASK (3 << TC_BMR_TC2XC2S_SHIFT) +# define TC_BMR_TC2XC2S_TCLK2 (0 << TC_BMR_TC2XC2S_SHIFT) +# define TC_BMR_TC2XC2S_NONE (1 << TC_BMR_TC2XC2S_SHIFT) +# define TC_BMR_TC2XC2S_TIOA0 (2 << TC_BMR_TC2XC2S_SHIFT) +# define TC_BMR_TC2XC2S_TIOA1 (3 << TC_BMR_TC2XC2S_SHIFT) +#define TC_BMR_QDEN (1 << 8) /* Bit 8: Quadrature Decoder Enabled */ +#define TC_BMR_POSEN (1 << 9) /* Bit 9: Position Enabled */ +#define TC_BMR_SPEEDEN (1 << 10) /* Bit 10: Speed Enabled */ +#define TC_BMR_QDTRANS (1 << 11) /* Bit 11: Quadrature Decoding Transparent */ +#define TC_BMR_EDGPHA (1 << 12) /* Bit 12: Edge on PHA count mode */ +#define TC_BMR_INVA (1 << 13) /* Bit 13: Inverted PHA */ +#define TC_BMR_INVB (1 << 14) /* Bit 14: Inverted PHB */ +#define TC_BMR_SWAP (1 << 15) /* Bit 15: Swap PHA and PHB */ +#define TC_BMR_INVIDX (1 << 16) /* Bit 16: Inverted Index */ +#define TC_BMR_IDXPHB (1 << 17) /* Bit 17: Index pin is PHB pin */ +#define TC_BMR_FILTER (1 << 19) /* Bit 19 */ +#define TC_BMR_MAXFILT_SHIFT (20) /* Bits 20-25: Maximum Filter */ +#define TC_BMR_MAXFILT_MASK (63 << TC_BMR_MAXFILT_SHIFT) + +/* TC QDEC Interrupt Enable Register, TC QDEC Interrupt Disable Register, + * TC QDEC Interrupt Mask Register, TC QDEC Interrupt Status Register common + * bit field definitions + */ + +#define TC_QINT_IDX (1 << 0) /* Bit 0: Index (Common) */ +#define TC_QINT_DIRCHG (1 << 1) /* Bit 1: Direction Change (Common) */ +#define TC_QINT_QERR (1 << 2) /* Bit 2: Quadrature Error (Common) */ +#define TC_QISR_DIR (1 << 8) /* Bit 8: Direction (QISR only) */ + +/* Timer Channel Registers */ +/* TC Channel Control Register */ + +#define TCN_CCR_CLKEN (1 << 0) /* Bit 0: Counter Clock Enable Command */ +#define TCN_CCR_CLKDIS (1 << 1) /* Bit 1: Counter Clock Disable Command */ +#define TCN_CCR_SWTRG (1 << 2) /* Bit 2: Software Trigger Command */ + +/* TC Channel Mode Register */ + +#define TCN_CMR_TCCLKS_SHIFT (0) /* Bits 0-2: Clock Selection (Common) */ +#define TCN_CMR_TCCLKS_MASK (7 << TCN_CMR_TCCLKS_SHIFT) +# define TCN_CMR_TCCLKS_TIMERCLOCK1 (0 << TCN_CMR_TCCLKS_SHIFT) +# define TCN_CMR_TCCLKS_TIMERCLOCK2 (1 << TCN_CMR_TCCLKS_SHIFT) +# define TCN_CMR_TCCLKS_TIMERCLOCK3 (2 << TCN_CMR_TCCLKS_SHIFT) +# define TCN_CMR_TCCLKS_TIMERCLOCK4 (3 << TCN_CMR_TCCLKS_SHIFT) +# define TCN_CMR_TCCLKS_TIMERCLOCK5 (4 << TCN_CMR_TCCLKS_SHIFT) +# define TCN_CMR_TCCLKS_XC0 (5 << TCN_CMR_TCCLKS_SHIFT) +# define TCN_CMR_TCCLKS_XC1 (6 << TCN_CMR_TCCLKS_SHIFT) +# define TCN_CMR_TCCLKS_XC2 (7 << TCN_CMR_TCCLKS_SHIFT) +#define TCN_CMR_CLKI (1 << 3) /* Bit 3: Clock Invert (Common) */ +#define TCN_CMR_BURST_SHIFT (4) /* Bits 4-5: Burst Signal Selection (Common) */ +#define TCN_CMR_BURST_MASK (3 << TCN_CMR_BURST_MASK) +#define TCN_CMR_BURST_MASK (3 << TCN_CMR_BURST_MASK) +# define TCN_CMR_BURST_NOTGATED (0 << TCN_CMR_BURST_MASK) /* Nott gated by external signal */ +# define TCN_CMR_BURST_XC0 (1 << TCN_CMR_BURST_MASK) /* XC0 ANDed with selected clock */ +# define TCN_CMR_BURST_XC1 (2 << TCN_CMR_BURST_MASK) /* XC1 ANDed with selected clock */ +# define TCN_CMR_BURST_XC2 (3 << TCN_CMR_BURST_MASK) /* XC2 ANDed with selected clock */ +#define TCN_CMR_WAVE (1 << 15) /* Bit 15: (Common) */ + +#define TCN_CMR_LDBSTOP (1 << 6) /* Bit 6: Counter stopped with RB Loading (Capture mode) */ +#define TCN_CMR_LDBDIS (1 << 7) /* Bit 7: Counter disable with RB Loading (Capture mode) */ +#define TCN_CMR_ETRGEDG_SHIFT (8) /* Bits 8-9: External Trigger Edge Selection (Capture mode) */ +#define TCN_CMR_ETRGEDG_MASK (3 << TCN_CMR_ETRGEDG_SHIFT) +# define TCN_CMR_ETRGEDG_NONE (0 << TCN_CMR_ETRGEDG_SHIFT) /* None */ +# define TCN_CMR_ETRGEDG_REDGE (1 << TCN_CMR_ETRGEDG_SHIFT) /* Rising edge */ +# define TCN_CMR_ETRGEDG_FEDGE (2 << TCN_CMR_ETRGEDG_SHIFT) /* Falling edge */ +# define TCN_CMR_ETRGEDG_EACH (3 << TCN_CMR_ETRGEDG_SHIFT) /* Each */ +#define TCN_CMR_ABETRG (1 << 10) /* Bit 10: TIOA or TIOB External Trigger Selection (Capture mode) */ +#define TCN_CMR_CPCTRG (1 << 14) /* Bit 14: RC Compare Trigger Enable (Capture mode) */ +#define TCN_CMR_LDRA_SHIFT (16) /* Bits 16-17: RA Loading Selection (Capture mode) */ +#define TCN_CMR_LDRA_MASK (3 << TCN_CMR_LDRA_SHIFT) +# define TCN_CMR_LDRA_NONE (0 << TCN_CMR_LDRA_SHIFT) /* None */ +# define TCN_CMR_LDRA_REDGE (1 << TCN_CMR_LDRA_SHIFT) /* Rising edge of TIOA */ +# define TCN_CMR_LDRA_FEDGE (2 << TCN_CMR_LDRA_SHIFT) /* Falling edge of TIOA */ +# define TCN_CMR_LDRA_EACH (3 << TCN_CMR_LDRA_SHIFT) /* Each edge of TIOA */ +#define TCN_CMR_LDRB_SHIFT (18) /* Bits 18-19: RB Loading Selection (Capture mode) */ +#define TCN_CMR_LDRB_MASK (3 << TCN_CMR_LDRB_SHIFT) +# define TCN_CMR_LDRB_NONE (0 << TCN_CMR_LDRB_SHIFT) /* None */ +# define TCN_CMR_LDRB_REDGE (1 << TCN_CMR_LDRB_SHIFT) /* Rising edge of TIOB */ +# define TCN_CMR_LDRB_FEDGE (2 << TCN_CMR_LDRB_SHIFT) /* Falling edge of TIOB */ +# define TCN_CMR_LDRB_EACH (3 << TCN_CMR_LDRB_SHIFT) /* Each edge of TIOB */ + +#define TCN_CMR_CPCSTOP (1 << 6) /* Bit 6: Counter Clock Stopped with RC Compare (Waveform mode) */ +#define TCN_CMR_CPCDIS (1 << 7) /* Bit 7: Counter Clock Disable with RC Compare (Waveform mode) */ +#define TCN_CMR_EEVTEDG_SHIFT (8) /* Bits 8-9: External Event Edge Selection (Waveform mode) */ +#define TCN_CMR_EEVTEDG_MASK (3 << TCN_CMR_EEVTEDG_SHIFT) +# define TCN_CMR_EEVTEDG_NONE (0 << TCN_CMR_EEVTEDG_SHIFT) /* None */ +# define TCN_CMR_EEVTEDG_REDGE (1 << TCN_CMR_EEVTEDG_SHIFT) /* Rising edge */ +# define TCN_CMR_EEVTEDG_FEDGE (2 << TCN_CMR_EEVTEDG_SHIFT) /* Falling edge */ +# define TCN_CMR_EEVTEDG_EACH (3 << TCN_CMR_EEVTEDG_SHIFT) /* Each edge */ +#define TCN_CMR_EEVT_SHIFT (10) /* Bits 10-11: External Event Selection (Waveform mode) */ +#define TCN_CMR_EEVT_MASK (3 << TCN_CMR_EEVT_SHIFT) +# define TCN_CMR_EEVT_TIOB (0 << TCN_CMR_EEVT_SHIFT) /* TIOB input */ +# define TCN_CMR_EEVT_XC0 (1 << TCN_CMR_EEVT_SHIFT) /* XC0 output */ +# define TCN_CMR_EEVT_XC1 (2 << TCN_CMR_EEVT_SHIFT) /* XC1 output */ +# define TCN_CMR_EEVT_XC2 (3 << TCN_CMR_EEVT_SHIFT) /* XC2 output */ +#define TCN_CMR_ENETRG (1 << 12) /* Bit 12: External Event Trigger Enable (Waveform mode) */ +#define TCN_CMR_WAVSEL_SHIFT (13) /* Bits 13-14: Waveform Selection (Waveform mode) */ +#define TCN_CMR_WAVSEL_MASK (3 << TCN_CMR_WAVSEL_SHIFT) +# define TCN_CMR_WAVSEL_UP (0 << TCN_CMR_WAVSEL_SHIFT) /* UP mode w/o auto trigger (Waveform mode) */ +# define TCN_CMR_WAVSEL_UPAUTO (1 << TCN_CMR_WAVSEL_SHIFT) /* UP mode with auto trigger (Waveform mode) */ +# define TCN_CMR_WAVSEL_UPDWN (2 << TCN_CMR_WAVSEL_SHIFT) /* UPDOWN mode w/o auto trigger (Waveform mode) */ +# define TCN_CMR_WAVSEL_UPDWNAUTO (3 << TCN_CMR_WAVSEL_SHIFT) /* UPDOWN mode with auto trigger (Waveform mode) */ +#define TCN_CMR_ACPA_SHIFT (16) /* Bits 16-17: RA Compare Effect on TIOA (Waveform mode) */ +#define TCN_CMR_ACPA_MASK (3 << TCN_CMR_ACPA_SHIFT) +# define TCN_CMR_ACPA_NONE (0 << TCN_CMR_ACPA_SHIFT) +# define TCN_CMR_ACPA_SET (1 << TCN_CMR_ACPA_SHIFT) +# define TCN_CMR_ACPA_CLEAR (2 << TCN_CMR_ACPA_SHIFT) +# define TCN_CMR_ACPA_TOGGLE (3 << TCN_CMR_ACPA_SHIFT) +#define TCN_CMR_ACPC_SHIFT (18) /* Bits 18-19: RC Compare Effect on TIOA (Waveform mode) */ +#define TCN_CMR_ACPC_MASK (3 << TCN_CMR_ACPC_SHIFT) +# define TCN_CMR_ACPC_NONE (0 << TCN_CMR_ACPC_SHIFT) +# define TCN_CMR_ACPC_SET (1 << TCN_CMR_ACPC_SHIFT) +# define TCN_CMR_ACPC_CLEAR (2 << TCN_CMR_ACPC_SHIFT) +# define TCN_CMR_ACPC_TOGGLE (3 << TCN_CMR_ACPC_SHIFT) +#define TCN_CMR_AEEVT_SHIFT (20) /* Bits 20-21: External Event Effect on TIOA (Waveform mode) */ +#define TCN_CMR_AEEVT_MASK (3 << TCN_CMR_AEEVT_SHIFT) +# define TCN_CMR_AEEVT_NONE (0 << TCN_CMR_AEEVT_SHIFT) +# define TCN_CMR_AEEVT_SET (1 << TCN_CMR_AEEVT_SHIFT) +# define TCN_CMR_AEEVT_CLEAR (2 << TCN_CMR_AEEVT_SHIFT) +# define TCN_CMR_AEEVT_TOGGLE (3 << TCN_CMR_AEEVT_SHIFT) +#define TCN_CMR_ASWTRG_SHIFT (22) /* Bits 22-23: Software Trigger Effect on TIOA (Waveform mode) */ +#define TCN_CMR_ASWTRG_MASK (3 << TCN_CMR_ASWTRG_SHIFT) +# define TCN_CMR_ASWTRG_NONE (0 << TCN_CMR_ASWTRG_SHIFT) +# define TCN_CMR_ASWTRG_SET (1 << TCN_CMR_ASWTRG_SHIFT) +# define TCN_CMR_ASWTRG_CLEAR (2 << TCN_CMR_ASWTRG_SHIFT) +# define TCN_CMR_ASWTRG_TOGGLE (3 << TCN_CMR_ASWTRG_SHIFT) +#define TCN_CMR_BCPB_SHIFT (24) /* Bits 24-25: RB Compare Effect on TIOB (Waveform mode) */ +#define TCN_CMR_BCPB_MASK (3 << TCN_CMR_BCPB_SHIFT) +# define TCN_CMR_BCPB_NONE (0 << TCN_CMR_BCPB_SHIFT) +# define TCN_CMR_BCPB_SET (1 << TCN_CMR_BCPB_SHIFT) +# define TCN_CMR_BCPB_CLEAR (2 << TCN_CMR_BCPB_SHIFT) +# define TCN_CMR_BCPB_TOGGLE (3 << TCN_CMR_BCPB_SHIFT) +#define TCN_CMR_BCPC_SHIFT (26) /* Bits 26-27: RC Compare Effect on TIOB (Waveform mode) */ +#define TCN_CMR_BCPC_MASK (3 << TCN_CMR_BCPC_SHIFT) +# define TCN_CMR_BCPC_NONE (0 << TCN_CMR_BCPC_SHIFT) +# define TCN_CMR_BCPC_SET (1 << TCN_CMR_BCPC_SHIFT) +# define TCN_CMR_BCPC_CLEAR (2 << TCN_CMR_BCPC_SHIFT) +# define TCN_CMR_BCPC_TOGGLE (3 << TCN_CMR_BCPC_SHIFT) +#define TCN_CMR_BEEVT_SHIFT (28) /* Bits 28-29: External Event Effect on TIOB (Waveform mode) */ +#define TCN_CMR_BEEVT_MASK (3 << TCN_CMR_BEEVT_SHIFT) +# define TCN_CMR_BEEVT_NONE (0 << TCN_CMR_BEEVT_SHIFT) +# define TCN_CMR_BEEVT_SET (1 << TCN_CMR_BEEVT_SHIFT) +# define TCN_CMR_BEEVT_CLEAR (2 << TCN_CMR_BEEVT_SHIFT) +# define TCN_CMR_BEEVT_TOGGLE (3 << TCN_CMR_BEEVT_SHIFT) +#define TCN_CMR_BSWTRG_SHIFT (30) /* Bits 30-31: Software Trigger Effect on TIOB (Waveform mode) */ +#define TCN_CMR_BSWTRG_MASK (3 << TCN_CMR_BSWTRG_SHIFT) +# define TCN_CMR_BSWTRG_NONE (0 << TCN_CMR_BSWTRG_SHIFT) +# define TCN_CMR_BSWTRG_SET (1 << TCN_CMR_BSWTRG_SHIFT) +# define TCN_CMR_BSWTRG_CLEAR (2 << TCN_CMR_BSWTRG_SHIFT) +# define TCN_CMR_BSWTRG_TOGGLE (3 << TCN_CMR_BSWTRG_SHIFT) + +/* TC Counter Value Register */ + +#define TCN_CV_SHIFT (0) /* Bits 0-15: Counter Value */ +#define TCN_CV_MASK (0xffff << TCN_CV_SHIFT) + +/* TC Register A, B, C */ + +#define TCN_RVALUE_SHIFT (0) /* Bits 0-15: Register A, B, or C value */ +#define TCN_RVALUE_MASK (0xffff << TCN_RVALUE_SHIFT) + +/* TC Status Register, TC Interrupt Enable Register, TC Interrupt Disable Register, and TC Interrupt Mask Register common bit-field definitions */ + +#define TCN_INT_COVFS (1 << 0) /* Bit 0: Counter Overflow */ +#define TCN_INT_LOVRS (1 << 1) /* Bit 1: Load Overrun */ +#define TCN_INT_CPAS (1 << 2) /* Bit 2: RA Compare */ +#define TCN_INT_CPBS (1 << 3) /* Bit 3: RB Compare */ +#define TCN_INT_CPCS (1 << 4) /* Bit 4: RC Compare */ +#define TCN_INT_LDRAS (1 << 5) /* Bit 5: RA Loading */ +#define TCN_INT_LDRBS (1 << 6) /* Bit 6: RB Loading */ +#define TCN_INT_ETRGS (1 << 7) /* Bit 7: External Trigger */ +#define TCN_INT_CLKSTA (1 << 16) /* Bit 16: Clock Enabling (SR only) */ +#define TCN_SR_MTIOA (1 << 17) /* Bit 17: TIOA Mirror (SR only) */ +#define TCN_SR_MTIOB (1 << 18) /* Bit 18: TIOB Mirror (SR only)*/ + +/************************************************************************************************ + * Public Types + ************************************************************************************************/ + +/************************************************************************************************ + * Public Data + ************************************************************************************************/ + +/************************************************************************************************ + * Public Functions + ************************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_TC_H */ diff --git a/nuttx/arch/arm/src/sam3u/sam3u_timerisr.c b/nuttx/arch/arm/src/sam3u/sam3u_timerisr.c index 225af25f6..5ff6dea69 100644 --- a/nuttx/arch/arm/src/sam3u/sam3u_timerisr.c +++ b/nuttx/arch/arm/src/sam3u/sam3u_timerisr.c @@ -2,7 +2,7 @@ * arch/arm/src/sam3u/sam3u_timerisr.c * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/sam3u/sam3u_twi.h b/nuttx/arch/arm/src/sam3u/sam3u_twi.h index 4a26ecdc4..66d1f23b3 100644 --- a/nuttx/arch/arm/src/sam3u/sam3u_twi.h +++ b/nuttx/arch/arm/src/sam3u/sam3u_twi.h @@ -1,192 +1,192 @@ -/****************************************************************************************
- * arch/arm/src/sam3u/sam3u_twi.h
- *
- * Copyright (C) 2009 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_TWI_H
-#define __ARCH_ARM_SRC_SAM3U_SAM3U_TWI_H
-
-/****************************************************************************************
- * Included Files
- ****************************************************************************************/
-
-#include <nuttx/config.h>
-
-#include "chip.h"
-#include "sam3u_memorymap.h"
-
-/****************************************************************************************
- * Pre-processor Definitions
- ****************************************************************************************/
-
-/* TWI register offsets *****************************************************************/
-
-#define SAM3U_TWI_CR_OFFSET 0x00 /* Control Register */
-#define SAM3U_TWI_MMR_OFFSET 0x04 /* Master Mode Register */
-#define SAM3U_TWI_SMR_OFFSET 0x08 /* Slave Mode Register */
-#define SAM3U_TWI_IADR_OFFSET 0x0c /* Internal Address Register */
-#define SAM3U_TWI_CWGR_OFFSET 0x10 /* Clock Waveform Generator Register */
-#define SAM3U_TWI_SR_OFFSET 0x20 /* Status Register */
-#define SAM3U_TWI_IER_OFFSET 0x24 /* Interrupt Enable Register */
-#define SAM3U_TWI_IDR_OFFSET 0x28 /* Interrupt Disable Register */
-#define SAM3U_TWI_IMR_OFFSET 0x2c /* Interrupt Mask Register */
-#define SAM3U_TWI_RHR_OFFSET 0x30 /* Receive Holding Register */
-#define SAM3U_TWI_THR_OFFSET 0x34 /* Transmit Holding Register */
- /* 0x38-0xfc: Reserved */
- /* 0x100-0x124: Reserved for the PDC */
-
-/* TWI register adresses ****************************************************************/
-
-#define SAM3U_TWI_CR(n) (SAM3U_TWIN_BASE(n)+SAM3U_TWI_CR_OFFSET)
-#define SAM3U_TWI_MMR(n) (SAM3U_TWIN_BASE(n)+SAM3U_TWI_MMR_OFFSET)
-#define SAM3U_TWI_SMR(n) (SAM3U_TWIN_BASE(n)+SAM3U_TWI_SMR_OFFSET)
-#define SAM3U_TWI_IADR(n) (SAM3U_TWIN_BASE(n)+SAM3U_TWI_IADR_OFFSET)
-#define SAM3U_TWI_CWGR(n) (SAM3U_TWIN_BASE(n)+SAM3U_TWI_CWGR_OFFSET)
-#define SAM3U_TWI_SR(n) (SAM3U_TWIN_BASE(n)+SAM3U_TWI_SR_OFFSET)
-#define SAM3U_TWI_IER(n) (SAM3U_TWIN_BASE(n)+SAM3U_TWI_IER_OFFSET)
-#define SAM3U_TWI_IDR(n) (SAM3U_TWIN_BASE(n)+SAM3U_TWI_IDR_OFFSET)
-#define SAM3U_TWI_IMR(n) (SAM3U_TWIN_BASE(n)+SAM3U_TWI_IMR_OFFSET)
-#define SAM3U_TWI_RHR(n) (SAM3U_TWIN_BASE(n)+SAM3U_TWI_RHR_OFFSET)
-#define SAM3U_TWI_THR(n) (SAM3U_TWIN_BASE(n)+SAM3U_TWI_THR_OFFSET)
-
-#define SAM3U_TWI0_CR (SAM3U_TWI0_BASE+SAM3U_TWI_CR_OFFSET)
-#define SAM3U_TWI0_MMR (SAM3U_TWI0_BASE+SAM3U_TWI_MMR_OFFSET)
-#define SAM3U_TWI0_SMR (SAM3U_TWI0_BASE+SAM3U_TWI_SMR_OFFSET)
-#define SAM3U_TWI0_IADR (SAM3U_TWI0_BASE+SAM3U_TWI_IADR_OFFSET)
-#define SAM3U_TWI0_CWGR (SAM3U_TWI0_BASE+SAM3U_TWI_CWGR_OFFSET)
-#define SAM3U_TWI0_SR (SAM3U_TWI0_BASE+SAM3U_TWI_SR_OFFSET)
-#define SAM3U_TWI0_IER (SAM3U_TWI0_BASE+SAM3U_TWI_IER_OFFSET)
-#define SAM3U_TWI0_IDR (SAM3U_TWI0_BASE+SAM3U_TWI_IDR_OFFSET)
-#define SAM3U_TWI0_IMR (SAM3U_TWI0_BASE+SAM3U_TWI_IMR_OFFSET)
-#define SAM3U_TWI0_RHR (SAM3U_TWI0_BASE+SAM3U_TWI_RHR_OFFSET)
-#define SAM3U_TWI0_THR (SAM3U_TWI0_BASE+SAM3U_TWI_THR_OFFSET)
-
-#define SAM3U_TWI1_CR (SAM3U_TWI1_BASE+SAM3U_TWI_CR_OFFSET)
-#define SAM3U_TWI1_MMR (SAM3U_TWI1_BASE+SAM3U_TWI_MMR_OFFSET)
-#define SAM3U_TWI1_SMR (SAM3U_TWI1_BASE+SAM3U_TWI_SMR_OFFSET)
-#define SAM3U_TWI1_IADR (SAM3U_TWI1_BASE+SAM3U_TWI_IADR_OFFSET)
-#define SAM3U_TWI1_CWGR (SAM3U_TWI1_BASE+SAM3U_TWI_CWGR_OFFSET)
-#define SAM3U_TWI1_SR (SAM3U_TWI1_BASE+SAM3U_TWI_SR_OFFSET)
-#define SAM3U_TWI1_IER (SAM3U_TWI1_BASE+SAM3U_TWI_IER_OFFSET)
-#define SAM3U_TWI1_IDR (SAM3U_TWI1_BASE+SAM3U_TWI_IDR_OFFSET)
-#define SAM3U_TWI1_IMR (SAM3U_TWI1_BASE+SAM3U_TWI_IMR_OFFSET)
-#define SAM3U_TWI1_RHR (SAM3U_TWI1_BASE+SAM3U_TWI_RHR_OFFSET)
-#define SAM3U_TWI1_THR (SAM3U_TWI1_BASE+SAM3U_TWI_THR_OFFSET)
-
-/* TWI register bit definitions *********************************************************/
-
-/* TWI Control Register */
-
-#define TWI_CR_START (1 << 0) /* Bit 0: Send a START Condition */
-#define TWI_CR_STOP (1 << 1) /* Bit 1: Send a STOP Condition */
-#define TWI_CR_MSEN (1 << 2) /* Bit 2: TWI Master Mode Enabled */
-#define TWI_CR_MSDIS (1 << 3) /* Bit 3: TWI Master Mode Disabled */
-#define TWI_CR_SVEN (1 << 4) /* Bit 4: TWI Slave Mode Enabled */
-#define TWI_CR_SVDIS (1 << 5) /* Bit 5: TWI Slave Mode Disabled */
-#define TWI_CR_QUICK (1 << 6) /* Bit 6: SMBUS Quick Command */
-#define TWI_CR_SWRST (1 << 7) /* Bit 7: Software Reset */
-
-/* TWI Master Mode Register */'
-
-#define TWI_MMR_IADRSZ_SHIFT (8) /* Bits 8-9: Internal Device Address Size */
-#define TWI_MMR_IADRSZ_MASK (3 << TWI_MMR_IADRSZ_SHIFT)
-# define TWI_MMR_IADRSZ_NONE (0 << TWI_MMR_IADRSZ_SHIFT) /* No internal device address */
-# define TWI_MMR_IADRSZ_1BYTE (1 << TWI_MMR_IADRSZ_SHIFT) /* One-byte internal device address */
-# define TWI_MMR_IADRSZ_3BYTE (2 << TWI_MMR_IADRSZ_SHIFT) /* Two-byte internal device address */
-# define TWI_MMR_IADRSZ_3BYTE (3 << TWI_MMR_IADRSZ_SHIFT) /* Three-byte internal device address */
-#define TWI_MMR_MREAD (1 << 12) /* Bit 12: Master Read Direction */
-#define TWI_MMR_DADR_SHIFT (16) /* Bits 16-23: Device Address */
-#define TWI_MMR_DADR_MASK (0xff << TWI_MMR_DADR_SHIFT)
-
-/* TWI Slave Mode Register */
-
-#define TWI_SMR_SADR_SHIFT (16) /* Bits 16-23: Slave Address */
-#define TWI_SMR_SADR_MASK (0xff << TWI_SMR_SADR_SHIFT)
-
-/* TWI Internal Address Register */
-
-#define TWI_IADR_SHIFT (0) /* Bits 0-23: Internal Address */
-#define TWI_IADR_MASK (0x00ffffff << TWI_IADR_SHIFT)
-
-/* TWI Clock Waveform Generator Register */
-
-#define TWI_CWGR_CLDIV_SHIFT (0) /* Bits 0-7: Clock Low Divider */
-#define TWI_CWGR_CLDIV_MASK (0xff << TWI_CWGR_CLDIV_SHIFT)
-#define TWI_CWGR_CHDIV_SHIFT (8) /* Bits 8-15: Clock High Divider */
-#define TWI_CWGR_CHDIV_MASK (0xff << TWI_CWGR_CLDIV_SHIFT)
-#define TWI_CWGR_CKDIV_SHIFT (16) /* Bits 16-18: Clock Divider */
-#define TWI_CWGR_CKDIV_MASK (7 << TWI_CWGR_CLDIV_SHIFT)
-
-/* TWI Status Register, TWI Interrupt Enable Register, TWI Interrupt Disable
- * Register, and TWI Interrupt Mask Register common bit fields.
- */
-
-#define TWI_INT_TXCOMP (1 << 0) /* Bit 0: Transmission Completed */
-#define TWI_INT_RXRDY (1 << 1) /* Bit 1: Receive Holding Register */
-#define TWI_INT_TXRDY (1 << 2) /* Bit 2: Transmit Holding Register Ready */
-#define TWI_SR_SVREAD (1 << 3) /* Bit 3: Slave Read (SR only) */
-#define TWI_INT_SVACC (1 << 4) /* Bit 4: Slave Access */
-#define TWI_INT_GACC (1 << 5) /* Bit 5: General Call Access */
-#define TWI_INT_OVRE (1 << 6) /* Bit 6: Overrun Error */
-#define TWI_INT_NACK (1 << 8) /* Bit 8: Not Acknowledged */
-#define TWI_INT_ARBLST (1 << 9) /* Bit 9: Arbitration Lost */
-#define TWI_INT_SCLWS (1 << 10) /* Bit 10: Clock Wait State */
-#define TWI_INT_EOSACC (1 << 11) /* Bit 11: End Of Slave Access */
-#define TWI_INT_ENDRX (1 << 12) /* Bit 12: End of RX buffer */
-#define TWI_INT_ENDTX (1 << 13) /* Bit 13: End of TX buffer */
-#define TWI_INT_RXBUFF (1 << 14) /* Bit 14: RX Buffer */
-#define TWI_INT_TXBUFE (1 << 15) /* Bit 15: TX Buffer Empty */
-
-/* TWI Receive Holding Register */
-
-#define TWI_RHR_RXDATA_SHIFT (0) /* Bits 0-7: Master or Slave Receive Holding Data */
-#define TWI_RHR_RXDATA_MASK (0xff << TWI_RHR_RXDATA_SHIFT)
-
-/* TWI Transmit Holding Register */
-
-#define TWI_THR_TXDATA_SHIFT (0) /* Bits 0-7: Master or Slave Transmit Holding Data */
-#define TWI_THR_TXDATA_MASK (0xff << TWI_THR_TXDATA_SHIFT)
-
-/****************************************************************************************
- * Public Types
- ****************************************************************************************/
-
-/****************************************************************************************
- * Public Data
- ****************************************************************************************/
-
-/****************************************************************************************
- * Public Functions
- ****************************************************************************************/
-
-#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_TWI_H */
+/**************************************************************************************** + * arch/arm/src/sam3u/sam3u_twi.h + * + * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_TWI_H +#define __ARCH_ARM_SRC_SAM3U_SAM3U_TWI_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +#include <nuttx/config.h> + +#include "chip.h" +#include "sam3u_memorymap.h" + +/**************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************/ + +/* TWI register offsets *****************************************************************/ + +#define SAM3U_TWI_CR_OFFSET 0x00 /* Control Register */ +#define SAM3U_TWI_MMR_OFFSET 0x04 /* Master Mode Register */ +#define SAM3U_TWI_SMR_OFFSET 0x08 /* Slave Mode Register */ +#define SAM3U_TWI_IADR_OFFSET 0x0c /* Internal Address Register */ +#define SAM3U_TWI_CWGR_OFFSET 0x10 /* Clock Waveform Generator Register */ +#define SAM3U_TWI_SR_OFFSET 0x20 /* Status Register */ +#define SAM3U_TWI_IER_OFFSET 0x24 /* Interrupt Enable Register */ +#define SAM3U_TWI_IDR_OFFSET 0x28 /* Interrupt Disable Register */ +#define SAM3U_TWI_IMR_OFFSET 0x2c /* Interrupt Mask Register */ +#define SAM3U_TWI_RHR_OFFSET 0x30 /* Receive Holding Register */ +#define SAM3U_TWI_THR_OFFSET 0x34 /* Transmit Holding Register */ + /* 0x38-0xfc: Reserved */ + /* 0x100-0x124: Reserved for the PDC */ + +/* TWI register adresses ****************************************************************/ + +#define SAM3U_TWI_CR(n) (SAM3U_TWIN_BASE(n)+SAM3U_TWI_CR_OFFSET) +#define SAM3U_TWI_MMR(n) (SAM3U_TWIN_BASE(n)+SAM3U_TWI_MMR_OFFSET) +#define SAM3U_TWI_SMR(n) (SAM3U_TWIN_BASE(n)+SAM3U_TWI_SMR_OFFSET) +#define SAM3U_TWI_IADR(n) (SAM3U_TWIN_BASE(n)+SAM3U_TWI_IADR_OFFSET) +#define SAM3U_TWI_CWGR(n) (SAM3U_TWIN_BASE(n)+SAM3U_TWI_CWGR_OFFSET) +#define SAM3U_TWI_SR(n) (SAM3U_TWIN_BASE(n)+SAM3U_TWI_SR_OFFSET) +#define SAM3U_TWI_IER(n) (SAM3U_TWIN_BASE(n)+SAM3U_TWI_IER_OFFSET) +#define SAM3U_TWI_IDR(n) (SAM3U_TWIN_BASE(n)+SAM3U_TWI_IDR_OFFSET) +#define SAM3U_TWI_IMR(n) (SAM3U_TWIN_BASE(n)+SAM3U_TWI_IMR_OFFSET) +#define SAM3U_TWI_RHR(n) (SAM3U_TWIN_BASE(n)+SAM3U_TWI_RHR_OFFSET) +#define SAM3U_TWI_THR(n) (SAM3U_TWIN_BASE(n)+SAM3U_TWI_THR_OFFSET) + +#define SAM3U_TWI0_CR (SAM3U_TWI0_BASE+SAM3U_TWI_CR_OFFSET) +#define SAM3U_TWI0_MMR (SAM3U_TWI0_BASE+SAM3U_TWI_MMR_OFFSET) +#define SAM3U_TWI0_SMR (SAM3U_TWI0_BASE+SAM3U_TWI_SMR_OFFSET) +#define SAM3U_TWI0_IADR (SAM3U_TWI0_BASE+SAM3U_TWI_IADR_OFFSET) +#define SAM3U_TWI0_CWGR (SAM3U_TWI0_BASE+SAM3U_TWI_CWGR_OFFSET) +#define SAM3U_TWI0_SR (SAM3U_TWI0_BASE+SAM3U_TWI_SR_OFFSET) +#define SAM3U_TWI0_IER (SAM3U_TWI0_BASE+SAM3U_TWI_IER_OFFSET) +#define SAM3U_TWI0_IDR (SAM3U_TWI0_BASE+SAM3U_TWI_IDR_OFFSET) +#define SAM3U_TWI0_IMR (SAM3U_TWI0_BASE+SAM3U_TWI_IMR_OFFSET) +#define SAM3U_TWI0_RHR (SAM3U_TWI0_BASE+SAM3U_TWI_RHR_OFFSET) +#define SAM3U_TWI0_THR (SAM3U_TWI0_BASE+SAM3U_TWI_THR_OFFSET) + +#define SAM3U_TWI1_CR (SAM3U_TWI1_BASE+SAM3U_TWI_CR_OFFSET) +#define SAM3U_TWI1_MMR (SAM3U_TWI1_BASE+SAM3U_TWI_MMR_OFFSET) +#define SAM3U_TWI1_SMR (SAM3U_TWI1_BASE+SAM3U_TWI_SMR_OFFSET) +#define SAM3U_TWI1_IADR (SAM3U_TWI1_BASE+SAM3U_TWI_IADR_OFFSET) +#define SAM3U_TWI1_CWGR (SAM3U_TWI1_BASE+SAM3U_TWI_CWGR_OFFSET) +#define SAM3U_TWI1_SR (SAM3U_TWI1_BASE+SAM3U_TWI_SR_OFFSET) +#define SAM3U_TWI1_IER (SAM3U_TWI1_BASE+SAM3U_TWI_IER_OFFSET) +#define SAM3U_TWI1_IDR (SAM3U_TWI1_BASE+SAM3U_TWI_IDR_OFFSET) +#define SAM3U_TWI1_IMR (SAM3U_TWI1_BASE+SAM3U_TWI_IMR_OFFSET) +#define SAM3U_TWI1_RHR (SAM3U_TWI1_BASE+SAM3U_TWI_RHR_OFFSET) +#define SAM3U_TWI1_THR (SAM3U_TWI1_BASE+SAM3U_TWI_THR_OFFSET) + +/* TWI register bit definitions *********************************************************/ + +/* TWI Control Register */ + +#define TWI_CR_START (1 << 0) /* Bit 0: Send a START Condition */ +#define TWI_CR_STOP (1 << 1) /* Bit 1: Send a STOP Condition */ +#define TWI_CR_MSEN (1 << 2) /* Bit 2: TWI Master Mode Enabled */ +#define TWI_CR_MSDIS (1 << 3) /* Bit 3: TWI Master Mode Disabled */ +#define TWI_CR_SVEN (1 << 4) /* Bit 4: TWI Slave Mode Enabled */ +#define TWI_CR_SVDIS (1 << 5) /* Bit 5: TWI Slave Mode Disabled */ +#define TWI_CR_QUICK (1 << 6) /* Bit 6: SMBUS Quick Command */ +#define TWI_CR_SWRST (1 << 7) /* Bit 7: Software Reset */ + +/* TWI Master Mode Register */' + +#define TWI_MMR_IADRSZ_SHIFT (8) /* Bits 8-9: Internal Device Address Size */ +#define TWI_MMR_IADRSZ_MASK (3 << TWI_MMR_IADRSZ_SHIFT) +# define TWI_MMR_IADRSZ_NONE (0 << TWI_MMR_IADRSZ_SHIFT) /* No internal device address */ +# define TWI_MMR_IADRSZ_1BYTE (1 << TWI_MMR_IADRSZ_SHIFT) /* One-byte internal device address */ +# define TWI_MMR_IADRSZ_3BYTE (2 << TWI_MMR_IADRSZ_SHIFT) /* Two-byte internal device address */ +# define TWI_MMR_IADRSZ_3BYTE (3 << TWI_MMR_IADRSZ_SHIFT) /* Three-byte internal device address */ +#define TWI_MMR_MREAD (1 << 12) /* Bit 12: Master Read Direction */ +#define TWI_MMR_DADR_SHIFT (16) /* Bits 16-23: Device Address */ +#define TWI_MMR_DADR_MASK (0xff << TWI_MMR_DADR_SHIFT) + +/* TWI Slave Mode Register */ + +#define TWI_SMR_SADR_SHIFT (16) /* Bits 16-23: Slave Address */ +#define TWI_SMR_SADR_MASK (0xff << TWI_SMR_SADR_SHIFT) + +/* TWI Internal Address Register */ + +#define TWI_IADR_SHIFT (0) /* Bits 0-23: Internal Address */ +#define TWI_IADR_MASK (0x00ffffff << TWI_IADR_SHIFT) + +/* TWI Clock Waveform Generator Register */ + +#define TWI_CWGR_CLDIV_SHIFT (0) /* Bits 0-7: Clock Low Divider */ +#define TWI_CWGR_CLDIV_MASK (0xff << TWI_CWGR_CLDIV_SHIFT) +#define TWI_CWGR_CHDIV_SHIFT (8) /* Bits 8-15: Clock High Divider */ +#define TWI_CWGR_CHDIV_MASK (0xff << TWI_CWGR_CLDIV_SHIFT) +#define TWI_CWGR_CKDIV_SHIFT (16) /* Bits 16-18: Clock Divider */ +#define TWI_CWGR_CKDIV_MASK (7 << TWI_CWGR_CLDIV_SHIFT) + +/* TWI Status Register, TWI Interrupt Enable Register, TWI Interrupt Disable + * Register, and TWI Interrupt Mask Register common bit fields. + */ + +#define TWI_INT_TXCOMP (1 << 0) /* Bit 0: Transmission Completed */ +#define TWI_INT_RXRDY (1 << 1) /* Bit 1: Receive Holding Register */ +#define TWI_INT_TXRDY (1 << 2) /* Bit 2: Transmit Holding Register Ready */ +#define TWI_SR_SVREAD (1 << 3) /* Bit 3: Slave Read (SR only) */ +#define TWI_INT_SVACC (1 << 4) /* Bit 4: Slave Access */ +#define TWI_INT_GACC (1 << 5) /* Bit 5: General Call Access */ +#define TWI_INT_OVRE (1 << 6) /* Bit 6: Overrun Error */ +#define TWI_INT_NACK (1 << 8) /* Bit 8: Not Acknowledged */ +#define TWI_INT_ARBLST (1 << 9) /* Bit 9: Arbitration Lost */ +#define TWI_INT_SCLWS (1 << 10) /* Bit 10: Clock Wait State */ +#define TWI_INT_EOSACC (1 << 11) /* Bit 11: End Of Slave Access */ +#define TWI_INT_ENDRX (1 << 12) /* Bit 12: End of RX buffer */ +#define TWI_INT_ENDTX (1 << 13) /* Bit 13: End of TX buffer */ +#define TWI_INT_RXBUFF (1 << 14) /* Bit 14: RX Buffer */ +#define TWI_INT_TXBUFE (1 << 15) /* Bit 15: TX Buffer Empty */ + +/* TWI Receive Holding Register */ + +#define TWI_RHR_RXDATA_SHIFT (0) /* Bits 0-7: Master or Slave Receive Holding Data */ +#define TWI_RHR_RXDATA_MASK (0xff << TWI_RHR_RXDATA_SHIFT) + +/* TWI Transmit Holding Register */ + +#define TWI_THR_TXDATA_SHIFT (0) /* Bits 0-7: Master or Slave Transmit Holding Data */ +#define TWI_THR_TXDATA_MASK (0xff << TWI_THR_TXDATA_SHIFT) + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +/**************************************************************************************** + * Public Data + ****************************************************************************************/ + +/**************************************************************************************** + * Public Functions + ****************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_TWI_H */ diff --git a/nuttx/arch/arm/src/sam3u/sam3u_uart.h b/nuttx/arch/arm/src/sam3u/sam3u_uart.h index b78467794..1103cbfad 100644 --- a/nuttx/arch/arm/src/sam3u/sam3u_uart.h +++ b/nuttx/arch/arm/src/sam3u/sam3u_uart.h @@ -1,391 +1,391 @@ -/************************************************************************************************
- * arch/arm/src/sam3u/sam3u_uart.h
- *
- * Copyright (C) 2009 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_UART_H
-#define __ARCH_ARM_SRC_SAM3U_SAM3U_UART_H
-
-/************************************************************************************************
- * Included Files
- ************************************************************************************************/
-
-#include <nuttx/config.h>
-
-#include "chip.h"
-#include "sam3u_memorymap.h"
-
-/************************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************************/
-
-/* UART register offsets ************************************************************************/
-
-#define SAM3U_UART_CR_OFFSET 0x0000 /* Control Register (Common) */
-#define SAM3U_UART_MR_OFFSET 0x0004 /* Mode Register (Common) */
-#define SAM3U_UART_IER_OFFSET 0x0008 /* Interrupt Enable Register (Common) */
-#define SAM3U_UART_IDR_OFFSET 0x000c /* Interrupt Disable Register (Common) */
-#define SAM3U_UART_IMR_OFFSET 0x0010 /* Interrupt Mask Register (Common) */
-#define SAM3U_UART_SR_OFFSET 0x0014 /* Status Register (Common) */
-#define SAM3U_UART_RHR_OFFSET 0x0018 /* Receive Holding Register (Common) */
-#define SAM3U_UART_THR_OFFSET 0x001c /* Transmit Holding Register (Common) */
-#define SAM3U_UART_BRGR_OFFSET 0x0020 /* Baud Rate Generator Register (Common) */
- /* 0x0024-0x003c: Reserved (UART) */
-#define SAM3U_USART_RTOR_OFFSET 0x0024 /* Receiver Time-out Register (USART only) */
-#define SAM3U_USART_TTGR_OFFSET 0x0028 /* Transmitter Timeguard Register (USART only) */
- /* 0x002c-0x003c: Reserved (UART) */
-#define SAM3U_USART_FIDI_OFFSET 0x0040 /* FI DI Ratio Register (USART only) */
-#define SAM3U_USART_NER_OFFSET 0x0044 /* Number of Errors Register ((USART only) */
- /* 0x0048: Reserved (USART) */
-#define SAM3U_USART_IF_OFFSET 0x004c /* IrDA Filter Register (USART only) */
-#define SAM3U_USART_MAN_OFFSET 0x0050 /* Manchester Encoder Decoder Register (USART only) */
-#define SAM3U_USART_WPMR_OFFSET 0x00e4 /* Write Protect Mode Register (USART only) */
-#define SAM3U_USART_WPSR_OFFSET 0x00e8 /* Write Protect Status Register (USART only) */
- /* 0x005c-0xf008: Reserved (USART) */
-#define SAM3U_USART_VERSION_OFFSET 0x00fc /* Version Register (USART only) */
- /* 0x0100-0x0124: PDC Area (Common) */
-
-/* UART register adresses ***********************************************************************/
-
-#define SAM3U_UART_CR (SAM3U_UART_BASE+SAM3U_UART_CR_OFFSET)
-#define SAM3U_UART_MR (SAM3U_UART_BASE+SAM3U_UART_MR_OFFSET)
-#define SAM3U_UART_IER (SAM3U_UART_BASE+SAM3U_UART_IER_OFFSET)
-#define SAM3U_UART_IDR (SAM3U_UART_BASE+SAM3U_UART_IDR_OFFSET)
-#define SAM3U_UART_IMR (SAM3U_UART_BASE+SAM3U_UART_IMR_OFFSET)
-#define SAM3U_UART_SR (SAM3U_UART_BASE+SAM3U_UART_SR_OFFSET)
-#define SAM3U_UART_RHR (SAM3U_UART_BASE+SAM3U_UART_RHR_OFFSET)
-#define SAM3U_UART_THR (SAM3U_UART_BASE+SAM3U_UART_THR_OFFSET)
-#define SAM3U_UART_BRGR (SAM3U_UART_BASE+SAM3U_UART_BRGR_OFFSET)
-
-#define SAM3U_USART_CR(n) (SAM3U_USARTN_BASE(n)+SAM3U_UART_CR_OFFSET)
-#define SAM3U_USART_MR(n) (SAM3U_USARTN_BASE(n)+SAM3U_UART_MR_OFFSET)
-#define SAM3U_USART_IER(n) (SAM3U_USARTN_BASE(n)+SAM3U_UART_IER_OFFSET)
-#define SAM3U_USART_IDR(n) (SAM3U_USARTN_BASE(n)+SAM3U_UART_IDR_OFFSET)
-#define SAM3U_USART_IMR(n) (SAM3U_USARTN_BASE(n)+SAM3U_UART_IMR_OFFSET)
-#define SAM3U_USART_SR(n) (SAM3U_USARTN_BASE(n)+SAM3U_UART_SR_OFFSET)
-#define SAM3U_USART_RHR(n) (SAM3U_USARTN_BASE(n)+SAM3U_UART_RHR_OFFSET)
-#define SAM3U_USART_THR(n) (SAM3U_USARTN_BASE(n)+SAM3U_UART_THR_OFFSET)
-#define SAM3U_USART_BRGR(n) (SAM3U_USARTN_BASE(n)+SAM3U_UART_BRGR_OFFSET)
-#define SAM3U_USART_RTOR(n) (SAM3U_USARTN_BASE(n)+SAM3U_USART_RTOR_OFFSET)
-#define SAM3U_USART_TTGR(n) (SAM3U_USARTN_BASE(n)+SAM3U_USART_TTGR_OFFSET)
-#define SAM3U_USART_FIDI(n) (SAM3U_USARTN_BASE(n)+SAM3U_USART_FIDI_OFFSET)
-#define SAM3U_USART_NER(n) (SAM3U_USARTN_BASE(n)+SAM3U_USART_NER_OFFSET)
-#define SAM3U_USART_IF(n) (SAM3U_USARTN_BASE(n)+SAM3U_USART_IF_OFFSET)
-#define SAM3U_USART_MAN(n) (SAM3U_USARTN_BASE(n)+SAM3U_USART_MAN_OFFSET)
-#define SAM3U_USART_WPMR(n) (SAM3U_USARTN_BASE(n)+SAM3U_USART_WPMR_OFFSET)
-#define SAM3U_USART_WPSR(n) (SAM3U_USARTN_BASE(n)+SAM3U_USART_WPSR_OFFSET)
-#define SAM3U_USART_VERSION(n) (SAM3U_USARTN_BASE(n)+SAM3U_USART_VERSION_OFFSET)
-
-#define SAM3U_USART0_CR (SAM3U_USART0_BASE+SAM3U_UART_CR_OFFSET)
-#define SAM3U_USART0_MR_ (SAM3U_USART0_BASE+SAM3U_UART_MR_OFFSET)
-#define SAM3U_USART0_IER (SAM3U_USART0_BASE+SAM3U_UART_IER_OFFSET)
-#define SAM3U_USART0_IDR (SAM3U_USART0_BASE+SAM3U_UART_IDR_OFFSET)
-#define SAM3U_USART0_IMR (SAM3U_USART0_BASE+SAM3U_UART_IMR_OFFSET)
-#define SAM3U_USART0_SR (SAM3U_USART0_BASE+SAM3U_UART_SR_OFFSET)
-#define SAM3U_USART0_RHR (SAM3U_USART0_BASE+SAM3U_UART_RHR_OFFSET)
-#define SAM3U_USART0_THR (SAM3U_USART0_BASE+SAM3U_UART_THR_OFFSET)
-#define SAM3U_USART0_BRGR (SAM3U_USART0_BASE+SAM3U_UART_BRGR_OFFSET)
-#define SAM3U_USART0_RTOR (SAM3U_USART0_BASE+SAM3U_USART_RTOR_OFFSET)
-#define SAM3U_USART0_TTGR (SAM3U_USART0_BASE+SAM3U_USART_TTGR_OFFSET)
-#define SAM3U_USART0_FIDI (SAM3U_USART0_BASE+SAM3U_USART_FIDI_OFFSET)
-#define SAM3U_USART0_NER (SAM3U_USART0_BASE+SAM3U_USART_NER_OFFSET)
-#define SAM3U_USART0_IF (SAM3U_USART0_BASE+SAM3U_USART_IF_OFFSET)
-#define SAM3U_USART0_MAN (SAM3U_USART0_BASE+SAM3U_USART_MAN_OFFSET)
-#define SAM3U_USART0_WPMR (SAM3U_USART0_BASE+SAM3U_USART_WPMR_OFFSET)
-#define SAM3U_USART0_WPSR (SAM3U_USART0_BASE+SAM3U_USART_WPSR_OFFSET)
-#define SAM3U_USART0_VERSION (SAM3U_USART0_BASE+SAM3U_USART_VERSION_OFFSET)
-
-#define SAM3U_USART1_CR (SAM3U_USART1_BASE+SAM3U_UART_CR_OFFSET)
-#define SAM3U_USART1_MR_ (SAM3U_USART1_BASE+SAM3U_UART_MR_OFFSET)
-#define SAM3U_USART1_IER (SAM3U_USART1_BASE+SAM3U_UART_IER_OFFSET)
-#define SAM3U_USART1_IDR (SAM3U_USART1_BASE+SAM3U_UART_IDR_OFFSET)
-#define SAM3U_USART1_IMR (SAM3U_USART1_BASE+SAM3U_UART_IMR_OFFSET)
-#define SAM3U_USART1_SR (SAM3U_USART1_BASE+SAM3U_UART_SR_OFFSET)
-#define SAM3U_USART1_RHR (SAM3U_USART1_BASE+SAM3U_UART_RHR_OFFSET)
-#define SAM3U_USART1_THR (SAM3U_USART1_BASE+SAM3U_UART_THR_OFFSET)
-#define SAM3U_USART1_BRGR (SAM3U_USART1_BASE+SAM3U_UART_BRGR_OFFSET)
-#define SAM3U_USART1_RTOR (SAM3U_USART1_BASE+SAM3U_USART_RTOR_OFFSET)
-#define SAM3U_USART1_TTGR (SAM3U_USART1_BASE+SAM3U_USART_TTGR_OFFSET)
-#define SAM3U_USART1_FIDI (SAM3U_USART1_BASE+SAM3U_USART_FIDI_OFFSET)
-#define SAM3U_USART1_NER (SAM3U_USART1_BASE+SAM3U_USART_NER_OFFSET)
-#define SAM3U_USART1_IF (SAM3U_USART1_BASE+SAM3U_USART_IF_OFFSET)
-#define SAM3U_USART1_MAN (SAM3U_USART1_BASE+SAM3U_USART_MAN_OFFSET)
-#define SAM3U_USART1_WPMR (SAM3U_USART1_BASE+SAM3U_USART_WPMR_OFFSET)
-#define SAM3U_USART1_WPSR (SAM3U_USART1_BASE+SAM3U_USART_WPSR_OFFSET)
-#define SAM3U_USART1_VERSION (SAM3U_USART1_BASE+SAM3U_USART_VERSION_OFFSET)
-
-#define SAM3U_USART2_CR (SAM3U_USART2_BASE+SAM3U_UART_CR_OFFSET)
-#define SAM3U_USART2_MR_ (SAM3U_USART2_BASE+SAM3U_UART_MR_OFFSET)
-#define SAM3U_USART2_IER (SAM3U_USART2_BASE+SAM3U_UART_IER_OFFSET)
-#define SAM3U_USART2_IDR (SAM3U_USART2_BASE+SAM3U_UART_IDR_OFFSET)
-#define SAM3U_USART2_IMR (SAM3U_USART2_BASE+SAM3U_UART_IMR_OFFSET)
-#define SAM3U_USART2_SR (SAM3U_USART2_BASE+SAM3U_UART_SR_OFFSET)
-#define SAM3U_USART2_RHR (SAM3U_USART2_BASE+SAM3U_UART_RHR_OFFSET)
-#define SAM3U_USART2_THR (SAM3U_USART2_BASE+SAM3U_UART_THR_OFFSET)
-#define SAM3U_USART2_BRGR (SAM3U_USART2_BASE+SAM3U_UART_BRGR_OFFSET)
-#define SAM3U_USART2_RTOR (SAM3U_USART2_BASE+SAM3U_USART_RTOR_OFFSET)
-#define SAM3U_USART2_TTGR (SAM3U_USART2_BASE+SAM3U_USART_TTGR_OFFSET)
-#define SAM3U_USART2_FIDI (SAM3U_USART2_BASE+SAM3U_USART_FIDI_OFFSET)
-#define SAM3U_USART2_NER (SAM3U_USART2_BASE+SAM3U_USART_NER_OFFSET)
-#define SAM3U_USART2_IF (SAM3U_USART2_BASE+SAM3U_USART_IF_OFFSET)
-#define SAM3U_USART2_MAN (SAM3U_USART2_BASE+SAM3U_USART_MAN_OFFSET)
-#define SAM3U_USART2_WPMR (SAM3U_USART2_BASE+SAM3U_USART_WPMR_OFFSET)
-#define SAM3U_USART2_WPSR (SAM3U_USART2_BASE+SAM3U_USART_WPSR_OFFSET)
-#define SAM3U_USART2_VERSION (SAM3U_USART2_BASE+SAM3U_USART_VERSION_OFFSET)
-
-#define SAM3U_USART3_CR (SAM3U_USART3_BASE+SAM3U_UART_CR_OFFSET)
-#define SAM3U_USART3_MR_ (SAM3U_USART3_BASE+SAM3U_UART_MR_OFFSET)
-#define SAM3U_USART3_IER (SAM3U_USART3_BASE+SAM3U_UART_IER_OFFSET)
-#define SAM3U_USART3_IDR (SAM3U_USART3_BASE+SAM3U_UART_IDR_OFFSET)
-#define SAM3U_USART3_IMR (SAM3U_USART3_BASE+SAM3U_UART_IMR_OFFSET)
-#define SAM3U_USART3_SR (SAM3U_USART3_BASE+SAM3U_UART_SR_OFFSET)
-#define SAM3U_USART3_RHR (SAM3U_USART3_BASE+SAM3U_UART_RHR_OFFSET)
-#define SAM3U_USART3_THR (SAM3U_USART3_BASE+SAM3U_UART_THR_OFFSET)
-#define SAM3U_USART3_BRGR (SAM3U_USART3_BASE+SAM3U_UART_BRGR_OFFSET)
-#define SAM3U_USART3_RTOR (SAM3U_USART3_BASE+SAM3U_USART_RTOR_OFFSET)
-#define SAM3U_USART3_TTGR (SAM3U_USART3_BASE+SAM3U_USART_TTGR_OFFSET)
-#define SAM3U_USART3_FIDI (SAM3U_USART3_BASE+SAM3U_USART_FIDI_OFFSET)
-#define SAM3U_USART3_NER (SAM3U_USART3_BASE+SAM3U_USART_NER_OFFSET)
-#define SAM3U_USART3_IF (SAM3U_USART3_BASE+SAM3U_USART_IF_OFFSET)
-#define SAM3U_USART3_MAN (SAM3U_USART3_BASE+SAM3U_USART_MAN_OFFSET)
-#define SAM3U_USART3_WPMR (SAM3U_USART3_BASE+SAM3U_USART_WPMR_OFFSET)
-#define SAM3U_USART3_WPSR (SAM3U_USART3_BASE+SAM3U_USART_WPSR_OFFSET)
-#define SAM3U_USART3_VERSION (SAM3U_USART3_BASE+SAM3U_USART_VERSION_OFFSET)
-
-/* UART register bit definitions ****************************************************************/
-
-/* UART Control Register */
-
-#define UART_CR_RSTRX (1 << 2) /* Bit 2: Reset Receiver (Common) */
-#define UART_CR_RSTTX (1 << 3) /* Bit 3: Reset Transmitter (Common) */
-#define UART_CR_RXEN (1 << 4) /* Bit 4: Receiver Enable (Common) */
-#define UART_CR_RXDIS (1 << 5) /* Bit 5: Receiver Disable (Common) */
-#define UART_CR_TXEN (1 << 6) /* Bit 6: Transmitter Enable (Common) */
-#define UART_CR_TXDIS (1 << 7) /* Bit 7: Transmitter Disable (Common) */
-#define UART_CR_RSTSTA (1 << 8) /* Bit 8: Reset Status Bits (Common) */
-#define USART_CR_STTBRK (1 << 9) /* Bit 9: Start Break (USART only) */
-#define USART_CR_STPBRK (1 << 10) /* Bit 10: Stop Break (USART only) */
-#define USART_CR_STTTO (1 << 11) /* Bit 11: Start Time-out (USART only) */
-#define USART_CR_SENDA (1 << 12) /* Bit 12: Send Address (USART only) */
-#define USART_CR_RSTIT (1 << 13) /* Bit 13: Reset Iterations (USART only) */
-#define USART_CR_RSTNACK (1 << 14) /* Bit 14: Reset Non Acknowledge (USART only) */
-#define USART_CR_RETTO (1 << 15) /* Bit 15: Rearm Time-out (USART only) */
-#define USART_CR_RTSEN (1 << 18) /* Bit 18: Request to Send Enable (USART only) */
-#define USART_CR_FCS (1 << 18) /* Bit 18: Force SPI Chip Select (USART only) */
-#define USART_CR_RTSDIS (1 << 19) /* Bit 19: Request to Send Disable (USART only) */
-#define USART_CR_RCS (1 << 19) /* Bit 19: Release SPI Chip Select (USART only) */
-
-/* UART Mode Register */
-
-#define USART_MR_MODE_SHIFT (0) /* Bits 0-3: (USART only) */
-#define USART_MR_MODE_MASK (15 << USART_MR_MODE_SHIFT)
-# define USART_MR_MODE_NORMAL (0 << USART_MR_MODE_SHIFT) /* Normal */
-# define USART_MR_MODE_RS485 (1 << USART_MR_MODE_SHIFT) /* RS485 */
-# define USART_MR_MODE_HWHS (2 << USART_MR_MODE_SHIFT) /* Hardware Handshaking */
-# define USART_MR_MODE_ISO7816_0 (4 << USART_MR_MODE_SHIFT) /* IS07816 Protocol: T = 0 */
-# define USART_MR_MODE_ISO7816_1 (6 << USART_MR_MODE_SHIFT) /* IS07816 Protocol: T = 1 */
-# define USART_MR_MODE_IRDA (8 << USART_MR_MODE_SHIFT) /* IrDA */
-# define USART_MR_MODE_SPIMSTR (14 << USART_MR_MODE_SHIFT) /* SPI Master */
-# define USART_MR_MODE_SPISLV (15 << USART_MR_MODE_SHIFT) /* SPI Slave */
-#define USART_MR_USCLKS_SHIFT (4) /* Bits 4-5: Clock Selection (USART only) */
-#define USART_MR_USCLKS_MASK (3 << USART_MR_USCLKS_SHIFT)
-# define USART_MR_USCLKS_MCK (0 << USART_MR_USCLKS_SHIFT) /* MCK */
-# define USART_MR_USCLKS_MCKDIV (1 << USART_MR_USCLKS_SHIFT) /* MCK/DIV (DIV = 8) */
-# define USART_MR_USCLKS_SCK (3 << USART_MR_USCLKS_SHIFT) /* SCK */
-#define USART_MR_CHRL_SHIFT (6) /* Bits 6-7: Character Length (USART only) */
-#define USART_MR_CHRL_MASK (3 << USART_MR_CHRL_SHIFT)
-# define USART_MR_CHRL_5BITS (0 << USART_MR_CHRL_SHIFT) /* 5 bits */
-# define USART_MR_CHRL_6BITS (1 << USART_MR_CHRL_SHIFT) /* 6 bits */
-# define USART_MR_CHRL_7BITS (2 << USART_MR_CHRL_SHIFT) /* 7 bits */
-# define USART_MR_CHRL_8BITS (3 << USART_MR_CHRL_SHIFT) /* 8 bits */
-#define USART_MR_YNC (1 << 8) /* Bit 8: Synchronous Mode Select (USART only) */
-#define USART_MR_CPHA (1 << 8) /* Bit 8: SPI Clock Phase (USART only) */
-#define UART_MR_PAR_SHIFT (9) /* Bits 9-11: Parity Type (Common) */
-#define UART_MR_PAR_MASK (7 << UART_MR_PAR_SHIFT)
-# define UART_MR_PAR_EVEN (0 << UART_MR_PAR_SHIFT) /* Even parity (Common) */
-# define UART_MR_PAR_ODD (1 << UART_MR_PAR_SHIFT) /* Odd parity (Common) */
-# define UART_MR_PAR_SPACE (2 << UART_MR_PAR_SHIFT) /* Space: parity forced to 0 (Common) */
-# define UART_MR_PAR_MARK (3 << UART_MR_PAR_SHIFT) /* Mark: parity forced to 1 (Common) */
-# define UART_MR_PAR_NONE (4 << UART_MR_PAR_SHIFT) /* No parity (Common) */
-# define UART_MR_PAR_MULTIDROP (6 << UART_MR_PAR_SHIFT) /* Multidrop mode (USART only) */
-#define USART_MR_NBSTOP_SHIFT (12) /* Bits 12-13: Number of Stop Bits (USART only) */
-#define USART_MR_NBSTOP_MASK (3 << USART_MR_NBSTOP_SHIFT)
-# define USART_MR_NBSTOP_1 (0 << USART_MR_NBSTOP_SHIFT) /* 1 stop bit 1 stop bit */
-# define USART_MR_NBSTOP_1p5 (1 << USART_MR_NBSTOP_SHIFT) /* 1.5 stop bits */
-# define USART_MR_NBSTOP_2 (2 << USART_MR_NBSTOP_SHIFT) /* 2 stop bits 2 stop bits */
-#define UART_MR_CHMODE_SHIFT (14) /* Bits 14-15: Channel Mode (Common) */
-#define UART_MR_CHMODE_MASK (3 << UART_MR_CHMODE_SHIFT)
-# define UART_MR_CHMODE_NORMAL (0 << UART_MR_CHMODE_SHIFT) /* Normal Mode */
-# define UART_MR_CHMODE_ECHO (1 << UART_MR_CHMODE_SHIFT) /* Automatic Echo */
-# define UART_MR_CHMODE_LLPBK (2 << UART_MR_CHMODE_SHIFT) /* Local Loopback */
-# define UART_MR_CHMODE_RLPBK (3 << UART_MR_CHMODE_SHIFT) /* Remote Loopback */
-#define USART_MR_MSBF (1 << 16) /* Bit 16: Bit Order or SPI Clock Polarity (USART only) */
-#define USART_MR_CPOL (1 << 16)
-#define USART_MR_MODE9 (1 << 17) /* Bit 17: 9-bit Character Length (USART only) */
-#define USART_MR_CLKO (1 << 18) /* Bit 18: Clock Output Select (USART only) */
-#define USART_MR_OVER (1 << 19) /* Bit 19: Oversampling Mode (USART only) */
-#define USART_MR_INACK (1 << 20) /* Bit 20: Inhibit Non Acknowledge (USART only) */
-#define USART_MR_DSNACK (1 << 21) /* Bit 21: Disable Successive NACK (USART only) */
-#define USART_MR_VARSYNC (1 << 22) /* Bit 22: Variable Synchronization of Command/Data Sync Start Frame Delimiter (USART only) */
-#define USART_MR_INVDATA (1 << 23) /* Bit 23: INverted Data (USART only) */
-#define USART_MR_MAXITER_SHIFT (24) /* Bits 24-26: Max iterations (ISO7816 T=0 (USART only) */
-#define USART_MR_MAXITER_MASK (7 << USART_MR_MAXITER_SHIFT)
-#define USART_MR_FILTER (1 << 28) /* Bit 28: Infrared Receive Line Filter (USART only) */
-#define USART_MR_MAN (1 << 29) /* Bit 29: Manchester Encoder/Decoder Enable (USART only) */
-#define USART_MR_MODSYNC (1 << 30) /* Bit 30: Manchester Synchronization Mode (USART only) */
-#define USART_MR_ONEBIT (1 << 31) /* Bit 31: Start Frame Delimiter Selector (USART only) */
-
-/* UART Interrupt Enable Register, UART Interrupt Disable Register, UART Interrupt Mask
- * Register, and UART Status Register common bit field definitions
- */
-
-#define UART_INT_RXRDY (1 << 0) /* Bit 0: RXRDY Interrupt (Common) */
-#define UART_INT_TXRDY (1 << 1) /* Bit 1: TXRDY Interrupt (Common) */
-#define UART_INT_RXBRK (1 << 2) /* Bit 2: Break Received/End of Break */
-#define UART_INT_ENDRX (1 << 3) /* Bit 3: End of Receive Transfer Interrupt (Common) */
-#define UART_INT_ENDTX (1 << 4) /* Bit 4: End of Transmit Interrupt (Common) */
-#define UART_INT_OVRE (1 << 5) /* Bit 5: Overrun Error Interrupt (Common) */
-#define UART_INT_FRAME (1 << 6) /* Bit 6: Framing Error Interrupt (Common) */
-#define UART_INT_PARE (1 << 7) /* Bit 7: Parity Error Interrupt (Common) */
-#define USART_INT_TIMEOUT (1 << 8) /* Bit 8: Time-out Interrupt (USART only) */
-#define UART_INT_TXEMPTY (1 << 9) /* Bit 9: TXEMPTY Interrupt (Common) */
-#define USART_INT_ITER (1 << 10) /* Bit 10: Iteration Interrupt (USART only) */
-#define USART_INT_UNRE (1 << 10) /* Bit 10: SPI Underrun Error Interrupt (USART only) */
-#define UART_INT_TXBUFE (1 << 11) /* Bit 11: Buffer Empty Interrupt (Common) */
-#define UART_INT_RXBUFF (1 << 12) /* Bit 12: Buffer Full Interrupt (Common) */
-#define USART_INT_NACK (1 << 13) /* Bit 13: Non Acknowledge Interrupt (USART only) */
-#define USART_INT_CTSIC (1 << 19) /* Bit 19: Clear to Send Input Change Interrupt (USART only) */
-#define USART_INT_MANE (1 << 24) /* Bit 24: Manchester Error Interrupt (USART only) */
-
-/* UART Receiver Holding Register */
-
-#define UART_RHR_RXCHR_SHIFT (0) /* Bits 0-7: Received Character (UART only) */
-#define UART_RHR_RXCHR_MASK (0xff << UART_RHR_RXCHR_SHIFT)
-#define USART_RHR_RXCHR_SHIFT (0) /* Bits 0-8: Received Character (USART only) */
-#define USART_RHR_RXCHR_MASK (0x1ff << UART_RHR_RXCHR_SHIFT)
-#define USART_RHR_RXSYNH (1 << 15) /* Bit 15: Received Sync (USART only) */
-
-/* UART Transmit Holding Register */
-
-#define UART_THR_TXCHR_SHIFT (0) /* Bits 0-7: Character to be Transmitted (UART only) */
-#define UART_THR_TXCHR_MASK (0xff << UART_THR_TXCHR_SHIFT)
-#define USART_THR_TXCHR_SHIFT (0) /* Bits 0-8: Character to be Transmitted (USART only) */
-#define USART_THR_TXCHR_MASK (0x1ff << USART_THR_TXCHR_SHIFT)
-#define USART_THR_TXSYNH (1 << 15) /* Bit 15: Sync Field to be tran (USART only) */
-
-/* UART Baud Rate Generator Register */
-
-#define UART_BRGR_CD_SHIFT (0) /* Bits 0-15: Clock Divisor (Common) */
-#define UART_BRGR_CD_MASK (0xffff << UART_BRGR_CD_SHIFT)
-#define UART_BRGR_FP_SHIFT (16) /* Bits 16-18: Fractional Part (USART only) */
-#define UART_BRGR_FP_MASK (7 << UART_BRGR_FP_SHIFT)
-
-/* USART Receiver Time-out Register (USART only) */
-
-#define USART_RTOR_TO_SHIFT (0) /* Bits 0-15: Time-out Value (USART only) */
-#define USART_RTOR_TO_MASK (0xffff << USART_RTOR_TO_SHIFT)
-
-/* USART Transmitter Timeguard Register (USART only) */
-
-#define USART_TTGR_TG_SHIFT (0) /* Bits 0-7: Timeguard Value (USART only) */
-#define USART_TTGR_TG_MASK (0xff << USART_TTGR_TG_SHIFT)
-
-/* USART FI DI RATIO Register (USART only) */
-
-#define USART_FIDI_RATIO_SHIFT (0) /* Bits 0-10: FI Over DI Ratio Value (USART only) */
-#define USART_FIDI_RATIO_MASK (0x7ff << USART_FIDI_RATIO_SHIFT)
-
-/* USART Number of Errors Register (USART only) */
-
-#define USART_NER_NBERRORS_SHIFT (0) /* Bits 0-7: Number of Errrors (USART only) */
-#define USART_NER_NBERRORS_MASK (0xff << USART_NER_NBERRORS_SHIFT)
-
-/* USART IrDA FILTER Register (USART only) */
-
-#define USART_IF_IRDAFILTER_SHIFT (0) /* Bits 0-7: IrDA Filter (USART only) */
-#define USART_IF_IRDAFILTER_MASK (0xff << USART_IF_IRDAFILTER_SHIFT)
-
-/* USART Manchester Configuration Register (USART only) */
-
-#define USART_MAN_TXPL_SHIFT (0) /* Bits 0-3: Transmitter Preamble Length (USART only) */
-#define USART_MAN_TXPL_MASK (15 << USART_MAN_TXPL_SHIFT)
-#define USART_MAN_TXPP_SHIFT (8) /* Bits 8-9: Transmitter Preamble Pattern (USART only) */
-#define USART_MAN_TXPP_MASK (3 << USART_MAN_TXPP_SHIFT)
-# define USART_MAN_TXPP_ALLONE (0 << USART_MAN_TXPP_SHIFT) /* ALL_ONE */
-# define USART_MAN_TXPP_ALLZERO (1 << USART_MAN_TXPP_SHIFT) /* ALL_ZERO */
-# define USART_MAN_TXPP_ZEROONE (2 << USART_MAN_TXPP_SHIFT) /* ZERO_ONE */
-# define USART_MAN_TXPP_ONEZERO (3 << USART_MAN_TXPP_SHIFT) /* ONE_ZERO */
-#define USART_MAN_TXMPOL (1 << 12) /* Bit 12: Transmitter Manchester Polarity (USART only) */
-#define USART_MAN_RXPL_SHIFT (16) /* Bits 16-19: Receiver Preamble Length (USART only) */
-#define USART_MAN_RXPL_MASK (15 << USART_MAN_RXPL_SHIFT)
-#define USART_MAN_RXPP_SHIFT (24) /* Bits 24-25: Receiver Preamble Pattern detected (USART only) */
-#define USART_MAN_RXPP_MASK (3 << USART_MAN_RXPP_SHIFT)
-# define USART_MAN_RXPP_ALLONE (0 << USART_MAN_RXPP_SHIFT) /* ALL_ONE */
-# define USART_MAN_RXPP_ALLZERO (1 << USART_MAN_RXPP_SHIFT) /* ALL_ZERO */
-# define USART_MAN_RXPP_ZEROONE (2 << USART_MAN_RXPP_SHIFT) /* ZERO_ONE */
-# define USART_MAN_RXPP_ONEZERO (3 << USART_MAN_RXPP_SHIFT) /* ONE_ZERO */
-#define USART_MAN_RXMPOL (1 << 28) /* Bit 28: Receiver Manchester Polarity (USART only) */
-#define USART_MAN_DRIFT (1 << 30) /* Bit 30: Drift compensation (USART only) */
-
-/* USART Write Protect Mode Register (USART only) */
-
-#define USART_WPMR_WPEN (1 << 0) /* Bit 0: Write Protect Enable (USART only) */
-#define USART_WPMR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protect KEY (USART only) */
-#define USART_WPMR_WPKEY_MASK (0x00ffffff << USART_WPMR_WPKEY_SHIFT)
-
-/* USART Write Protect Status Register (USART only) */
-
-#define USART_WPSR_WPVS (1 << 0) /* Bit 0: Write Protect Violation Status (USART only) */
-#define USART_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protect Violation Source (USART only) */
-#define USART_WPSR_WPVSRC_MASK (0xffff << USART_WPSR_WPVSRC_SHIFT)
-
-/* USART Version Register */
-
-#define USART_VERSION_VERSION_SHIFT (0) /* Bits 0-11: Macrocell version number (USART only) */
-#define USART_VERSION_VERSION_MASK (0xfff << USART_VERSION_VERSION_SHIFT)
-#define USART_VERSION_MFN_SHIFT (16) /* Bits 16-18: Reserved (USART only) */
-#define USART_VERSION_MFN_MASK (7 << USART_VERSION_MFN_SHIFT)
-
-/************************************************************************************************
- * Public Types
- ************************************************************************************************/
-
-/************************************************************************************************
- * Public Data
- ************************************************************************************************/
-
-/************************************************************************************************
- * Public Functions
- ************************************************************************************************/
-
-#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_UART_H */
+/************************************************************************************************ + * arch/arm/src/sam3u/sam3u_uart.h + * + * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_UART_H +#define __ARCH_ARM_SRC_SAM3U_SAM3U_UART_H + +/************************************************************************************************ + * Included Files + ************************************************************************************************/ + +#include <nuttx/config.h> + +#include "chip.h" +#include "sam3u_memorymap.h" + +/************************************************************************************************ + * Pre-processor Definitions + ************************************************************************************************/ + +/* UART register offsets ************************************************************************/ + +#define SAM3U_UART_CR_OFFSET 0x0000 /* Control Register (Common) */ +#define SAM3U_UART_MR_OFFSET 0x0004 /* Mode Register (Common) */ +#define SAM3U_UART_IER_OFFSET 0x0008 /* Interrupt Enable Register (Common) */ +#define SAM3U_UART_IDR_OFFSET 0x000c /* Interrupt Disable Register (Common) */ +#define SAM3U_UART_IMR_OFFSET 0x0010 /* Interrupt Mask Register (Common) */ +#define SAM3U_UART_SR_OFFSET 0x0014 /* Status Register (Common) */ +#define SAM3U_UART_RHR_OFFSET 0x0018 /* Receive Holding Register (Common) */ +#define SAM3U_UART_THR_OFFSET 0x001c /* Transmit Holding Register (Common) */ +#define SAM3U_UART_BRGR_OFFSET 0x0020 /* Baud Rate Generator Register (Common) */ + /* 0x0024-0x003c: Reserved (UART) */ +#define SAM3U_USART_RTOR_OFFSET 0x0024 /* Receiver Time-out Register (USART only) */ +#define SAM3U_USART_TTGR_OFFSET 0x0028 /* Transmitter Timeguard Register (USART only) */ + /* 0x002c-0x003c: Reserved (UART) */ +#define SAM3U_USART_FIDI_OFFSET 0x0040 /* FI DI Ratio Register (USART only) */ +#define SAM3U_USART_NER_OFFSET 0x0044 /* Number of Errors Register ((USART only) */ + /* 0x0048: Reserved (USART) */ +#define SAM3U_USART_IF_OFFSET 0x004c /* IrDA Filter Register (USART only) */ +#define SAM3U_USART_MAN_OFFSET 0x0050 /* Manchester Encoder Decoder Register (USART only) */ +#define SAM3U_USART_WPMR_OFFSET 0x00e4 /* Write Protect Mode Register (USART only) */ +#define SAM3U_USART_WPSR_OFFSET 0x00e8 /* Write Protect Status Register (USART only) */ + /* 0x005c-0xf008: Reserved (USART) */ +#define SAM3U_USART_VERSION_OFFSET 0x00fc /* Version Register (USART only) */ + /* 0x0100-0x0124: PDC Area (Common) */ + +/* UART register adresses ***********************************************************************/ + +#define SAM3U_UART_CR (SAM3U_UART_BASE+SAM3U_UART_CR_OFFSET) +#define SAM3U_UART_MR (SAM3U_UART_BASE+SAM3U_UART_MR_OFFSET) +#define SAM3U_UART_IER (SAM3U_UART_BASE+SAM3U_UART_IER_OFFSET) +#define SAM3U_UART_IDR (SAM3U_UART_BASE+SAM3U_UART_IDR_OFFSET) +#define SAM3U_UART_IMR (SAM3U_UART_BASE+SAM3U_UART_IMR_OFFSET) +#define SAM3U_UART_SR (SAM3U_UART_BASE+SAM3U_UART_SR_OFFSET) +#define SAM3U_UART_RHR (SAM3U_UART_BASE+SAM3U_UART_RHR_OFFSET) +#define SAM3U_UART_THR (SAM3U_UART_BASE+SAM3U_UART_THR_OFFSET) +#define SAM3U_UART_BRGR (SAM3U_UART_BASE+SAM3U_UART_BRGR_OFFSET) + +#define SAM3U_USART_CR(n) (SAM3U_USARTN_BASE(n)+SAM3U_UART_CR_OFFSET) +#define SAM3U_USART_MR(n) (SAM3U_USARTN_BASE(n)+SAM3U_UART_MR_OFFSET) +#define SAM3U_USART_IER(n) (SAM3U_USARTN_BASE(n)+SAM3U_UART_IER_OFFSET) +#define SAM3U_USART_IDR(n) (SAM3U_USARTN_BASE(n)+SAM3U_UART_IDR_OFFSET) +#define SAM3U_USART_IMR(n) (SAM3U_USARTN_BASE(n)+SAM3U_UART_IMR_OFFSET) +#define SAM3U_USART_SR(n) (SAM3U_USARTN_BASE(n)+SAM3U_UART_SR_OFFSET) +#define SAM3U_USART_RHR(n) (SAM3U_USARTN_BASE(n)+SAM3U_UART_RHR_OFFSET) +#define SAM3U_USART_THR(n) (SAM3U_USARTN_BASE(n)+SAM3U_UART_THR_OFFSET) +#define SAM3U_USART_BRGR(n) (SAM3U_USARTN_BASE(n)+SAM3U_UART_BRGR_OFFSET) +#define SAM3U_USART_RTOR(n) (SAM3U_USARTN_BASE(n)+SAM3U_USART_RTOR_OFFSET) +#define SAM3U_USART_TTGR(n) (SAM3U_USARTN_BASE(n)+SAM3U_USART_TTGR_OFFSET) +#define SAM3U_USART_FIDI(n) (SAM3U_USARTN_BASE(n)+SAM3U_USART_FIDI_OFFSET) +#define SAM3U_USART_NER(n) (SAM3U_USARTN_BASE(n)+SAM3U_USART_NER_OFFSET) +#define SAM3U_USART_IF(n) (SAM3U_USARTN_BASE(n)+SAM3U_USART_IF_OFFSET) +#define SAM3U_USART_MAN(n) (SAM3U_USARTN_BASE(n)+SAM3U_USART_MAN_OFFSET) +#define SAM3U_USART_WPMR(n) (SAM3U_USARTN_BASE(n)+SAM3U_USART_WPMR_OFFSET) +#define SAM3U_USART_WPSR(n) (SAM3U_USARTN_BASE(n)+SAM3U_USART_WPSR_OFFSET) +#define SAM3U_USART_VERSION(n) (SAM3U_USARTN_BASE(n)+SAM3U_USART_VERSION_OFFSET) + +#define SAM3U_USART0_CR (SAM3U_USART0_BASE+SAM3U_UART_CR_OFFSET) +#define SAM3U_USART0_MR_ (SAM3U_USART0_BASE+SAM3U_UART_MR_OFFSET) +#define SAM3U_USART0_IER (SAM3U_USART0_BASE+SAM3U_UART_IER_OFFSET) +#define SAM3U_USART0_IDR (SAM3U_USART0_BASE+SAM3U_UART_IDR_OFFSET) +#define SAM3U_USART0_IMR (SAM3U_USART0_BASE+SAM3U_UART_IMR_OFFSET) +#define SAM3U_USART0_SR (SAM3U_USART0_BASE+SAM3U_UART_SR_OFFSET) +#define SAM3U_USART0_RHR (SAM3U_USART0_BASE+SAM3U_UART_RHR_OFFSET) +#define SAM3U_USART0_THR (SAM3U_USART0_BASE+SAM3U_UART_THR_OFFSET) +#define SAM3U_USART0_BRGR (SAM3U_USART0_BASE+SAM3U_UART_BRGR_OFFSET) +#define SAM3U_USART0_RTOR (SAM3U_USART0_BASE+SAM3U_USART_RTOR_OFFSET) +#define SAM3U_USART0_TTGR (SAM3U_USART0_BASE+SAM3U_USART_TTGR_OFFSET) +#define SAM3U_USART0_FIDI (SAM3U_USART0_BASE+SAM3U_USART_FIDI_OFFSET) +#define SAM3U_USART0_NER (SAM3U_USART0_BASE+SAM3U_USART_NER_OFFSET) +#define SAM3U_USART0_IF (SAM3U_USART0_BASE+SAM3U_USART_IF_OFFSET) +#define SAM3U_USART0_MAN (SAM3U_USART0_BASE+SAM3U_USART_MAN_OFFSET) +#define SAM3U_USART0_WPMR (SAM3U_USART0_BASE+SAM3U_USART_WPMR_OFFSET) +#define SAM3U_USART0_WPSR (SAM3U_USART0_BASE+SAM3U_USART_WPSR_OFFSET) +#define SAM3U_USART0_VERSION (SAM3U_USART0_BASE+SAM3U_USART_VERSION_OFFSET) + +#define SAM3U_USART1_CR (SAM3U_USART1_BASE+SAM3U_UART_CR_OFFSET) +#define SAM3U_USART1_MR_ (SAM3U_USART1_BASE+SAM3U_UART_MR_OFFSET) +#define SAM3U_USART1_IER (SAM3U_USART1_BASE+SAM3U_UART_IER_OFFSET) +#define SAM3U_USART1_IDR (SAM3U_USART1_BASE+SAM3U_UART_IDR_OFFSET) +#define SAM3U_USART1_IMR (SAM3U_USART1_BASE+SAM3U_UART_IMR_OFFSET) +#define SAM3U_USART1_SR (SAM3U_USART1_BASE+SAM3U_UART_SR_OFFSET) +#define SAM3U_USART1_RHR (SAM3U_USART1_BASE+SAM3U_UART_RHR_OFFSET) +#define SAM3U_USART1_THR (SAM3U_USART1_BASE+SAM3U_UART_THR_OFFSET) +#define SAM3U_USART1_BRGR (SAM3U_USART1_BASE+SAM3U_UART_BRGR_OFFSET) +#define SAM3U_USART1_RTOR (SAM3U_USART1_BASE+SAM3U_USART_RTOR_OFFSET) +#define SAM3U_USART1_TTGR (SAM3U_USART1_BASE+SAM3U_USART_TTGR_OFFSET) +#define SAM3U_USART1_FIDI (SAM3U_USART1_BASE+SAM3U_USART_FIDI_OFFSET) +#define SAM3U_USART1_NER (SAM3U_USART1_BASE+SAM3U_USART_NER_OFFSET) +#define SAM3U_USART1_IF (SAM3U_USART1_BASE+SAM3U_USART_IF_OFFSET) +#define SAM3U_USART1_MAN (SAM3U_USART1_BASE+SAM3U_USART_MAN_OFFSET) +#define SAM3U_USART1_WPMR (SAM3U_USART1_BASE+SAM3U_USART_WPMR_OFFSET) +#define SAM3U_USART1_WPSR (SAM3U_USART1_BASE+SAM3U_USART_WPSR_OFFSET) +#define SAM3U_USART1_VERSION (SAM3U_USART1_BASE+SAM3U_USART_VERSION_OFFSET) + +#define SAM3U_USART2_CR (SAM3U_USART2_BASE+SAM3U_UART_CR_OFFSET) +#define SAM3U_USART2_MR_ (SAM3U_USART2_BASE+SAM3U_UART_MR_OFFSET) +#define SAM3U_USART2_IER (SAM3U_USART2_BASE+SAM3U_UART_IER_OFFSET) +#define SAM3U_USART2_IDR (SAM3U_USART2_BASE+SAM3U_UART_IDR_OFFSET) +#define SAM3U_USART2_IMR (SAM3U_USART2_BASE+SAM3U_UART_IMR_OFFSET) +#define SAM3U_USART2_SR (SAM3U_USART2_BASE+SAM3U_UART_SR_OFFSET) +#define SAM3U_USART2_RHR (SAM3U_USART2_BASE+SAM3U_UART_RHR_OFFSET) +#define SAM3U_USART2_THR (SAM3U_USART2_BASE+SAM3U_UART_THR_OFFSET) +#define SAM3U_USART2_BRGR (SAM3U_USART2_BASE+SAM3U_UART_BRGR_OFFSET) +#define SAM3U_USART2_RTOR (SAM3U_USART2_BASE+SAM3U_USART_RTOR_OFFSET) +#define SAM3U_USART2_TTGR (SAM3U_USART2_BASE+SAM3U_USART_TTGR_OFFSET) +#define SAM3U_USART2_FIDI (SAM3U_USART2_BASE+SAM3U_USART_FIDI_OFFSET) +#define SAM3U_USART2_NER (SAM3U_USART2_BASE+SAM3U_USART_NER_OFFSET) +#define SAM3U_USART2_IF (SAM3U_USART2_BASE+SAM3U_USART_IF_OFFSET) +#define SAM3U_USART2_MAN (SAM3U_USART2_BASE+SAM3U_USART_MAN_OFFSET) +#define SAM3U_USART2_WPMR (SAM3U_USART2_BASE+SAM3U_USART_WPMR_OFFSET) +#define SAM3U_USART2_WPSR (SAM3U_USART2_BASE+SAM3U_USART_WPSR_OFFSET) +#define SAM3U_USART2_VERSION (SAM3U_USART2_BASE+SAM3U_USART_VERSION_OFFSET) + +#define SAM3U_USART3_CR (SAM3U_USART3_BASE+SAM3U_UART_CR_OFFSET) +#define SAM3U_USART3_MR_ (SAM3U_USART3_BASE+SAM3U_UART_MR_OFFSET) +#define SAM3U_USART3_IER (SAM3U_USART3_BASE+SAM3U_UART_IER_OFFSET) +#define SAM3U_USART3_IDR (SAM3U_USART3_BASE+SAM3U_UART_IDR_OFFSET) +#define SAM3U_USART3_IMR (SAM3U_USART3_BASE+SAM3U_UART_IMR_OFFSET) +#define SAM3U_USART3_SR (SAM3U_USART3_BASE+SAM3U_UART_SR_OFFSET) +#define SAM3U_USART3_RHR (SAM3U_USART3_BASE+SAM3U_UART_RHR_OFFSET) +#define SAM3U_USART3_THR (SAM3U_USART3_BASE+SAM3U_UART_THR_OFFSET) +#define SAM3U_USART3_BRGR (SAM3U_USART3_BASE+SAM3U_UART_BRGR_OFFSET) +#define SAM3U_USART3_RTOR (SAM3U_USART3_BASE+SAM3U_USART_RTOR_OFFSET) +#define SAM3U_USART3_TTGR (SAM3U_USART3_BASE+SAM3U_USART_TTGR_OFFSET) +#define SAM3U_USART3_FIDI (SAM3U_USART3_BASE+SAM3U_USART_FIDI_OFFSET) +#define SAM3U_USART3_NER (SAM3U_USART3_BASE+SAM3U_USART_NER_OFFSET) +#define SAM3U_USART3_IF (SAM3U_USART3_BASE+SAM3U_USART_IF_OFFSET) +#define SAM3U_USART3_MAN (SAM3U_USART3_BASE+SAM3U_USART_MAN_OFFSET) +#define SAM3U_USART3_WPMR (SAM3U_USART3_BASE+SAM3U_USART_WPMR_OFFSET) +#define SAM3U_USART3_WPSR (SAM3U_USART3_BASE+SAM3U_USART_WPSR_OFFSET) +#define SAM3U_USART3_VERSION (SAM3U_USART3_BASE+SAM3U_USART_VERSION_OFFSET) + +/* UART register bit definitions ****************************************************************/ + +/* UART Control Register */ + +#define UART_CR_RSTRX (1 << 2) /* Bit 2: Reset Receiver (Common) */ +#define UART_CR_RSTTX (1 << 3) /* Bit 3: Reset Transmitter (Common) */ +#define UART_CR_RXEN (1 << 4) /* Bit 4: Receiver Enable (Common) */ +#define UART_CR_RXDIS (1 << 5) /* Bit 5: Receiver Disable (Common) */ +#define UART_CR_TXEN (1 << 6) /* Bit 6: Transmitter Enable (Common) */ +#define UART_CR_TXDIS (1 << 7) /* Bit 7: Transmitter Disable (Common) */ +#define UART_CR_RSTSTA (1 << 8) /* Bit 8: Reset Status Bits (Common) */ +#define USART_CR_STTBRK (1 << 9) /* Bit 9: Start Break (USART only) */ +#define USART_CR_STPBRK (1 << 10) /* Bit 10: Stop Break (USART only) */ +#define USART_CR_STTTO (1 << 11) /* Bit 11: Start Time-out (USART only) */ +#define USART_CR_SENDA (1 << 12) /* Bit 12: Send Address (USART only) */ +#define USART_CR_RSTIT (1 << 13) /* Bit 13: Reset Iterations (USART only) */ +#define USART_CR_RSTNACK (1 << 14) /* Bit 14: Reset Non Acknowledge (USART only) */ +#define USART_CR_RETTO (1 << 15) /* Bit 15: Rearm Time-out (USART only) */ +#define USART_CR_RTSEN (1 << 18) /* Bit 18: Request to Send Enable (USART only) */ +#define USART_CR_FCS (1 << 18) /* Bit 18: Force SPI Chip Select (USART only) */ +#define USART_CR_RTSDIS (1 << 19) /* Bit 19: Request to Send Disable (USART only) */ +#define USART_CR_RCS (1 << 19) /* Bit 19: Release SPI Chip Select (USART only) */ + +/* UART Mode Register */ + +#define USART_MR_MODE_SHIFT (0) /* Bits 0-3: (USART only) */ +#define USART_MR_MODE_MASK (15 << USART_MR_MODE_SHIFT) +# define USART_MR_MODE_NORMAL (0 << USART_MR_MODE_SHIFT) /* Normal */ +# define USART_MR_MODE_RS485 (1 << USART_MR_MODE_SHIFT) /* RS485 */ +# define USART_MR_MODE_HWHS (2 << USART_MR_MODE_SHIFT) /* Hardware Handshaking */ +# define USART_MR_MODE_ISO7816_0 (4 << USART_MR_MODE_SHIFT) /* IS07816 Protocol: T = 0 */ +# define USART_MR_MODE_ISO7816_1 (6 << USART_MR_MODE_SHIFT) /* IS07816 Protocol: T = 1 */ +# define USART_MR_MODE_IRDA (8 << USART_MR_MODE_SHIFT) /* IrDA */ +# define USART_MR_MODE_SPIMSTR (14 << USART_MR_MODE_SHIFT) /* SPI Master */ +# define USART_MR_MODE_SPISLV (15 << USART_MR_MODE_SHIFT) /* SPI Slave */ +#define USART_MR_USCLKS_SHIFT (4) /* Bits 4-5: Clock Selection (USART only) */ +#define USART_MR_USCLKS_MASK (3 << USART_MR_USCLKS_SHIFT) +# define USART_MR_USCLKS_MCK (0 << USART_MR_USCLKS_SHIFT) /* MCK */ +# define USART_MR_USCLKS_MCKDIV (1 << USART_MR_USCLKS_SHIFT) /* MCK/DIV (DIV = 8) */ +# define USART_MR_USCLKS_SCK (3 << USART_MR_USCLKS_SHIFT) /* SCK */ +#define USART_MR_CHRL_SHIFT (6) /* Bits 6-7: Character Length (USART only) */ +#define USART_MR_CHRL_MASK (3 << USART_MR_CHRL_SHIFT) +# define USART_MR_CHRL_5BITS (0 << USART_MR_CHRL_SHIFT) /* 5 bits */ +# define USART_MR_CHRL_6BITS (1 << USART_MR_CHRL_SHIFT) /* 6 bits */ +# define USART_MR_CHRL_7BITS (2 << USART_MR_CHRL_SHIFT) /* 7 bits */ +# define USART_MR_CHRL_8BITS (3 << USART_MR_CHRL_SHIFT) /* 8 bits */ +#define USART_MR_YNC (1 << 8) /* Bit 8: Synchronous Mode Select (USART only) */ +#define USART_MR_CPHA (1 << 8) /* Bit 8: SPI Clock Phase (USART only) */ +#define UART_MR_PAR_SHIFT (9) /* Bits 9-11: Parity Type (Common) */ +#define UART_MR_PAR_MASK (7 << UART_MR_PAR_SHIFT) +# define UART_MR_PAR_EVEN (0 << UART_MR_PAR_SHIFT) /* Even parity (Common) */ +# define UART_MR_PAR_ODD (1 << UART_MR_PAR_SHIFT) /* Odd parity (Common) */ +# define UART_MR_PAR_SPACE (2 << UART_MR_PAR_SHIFT) /* Space: parity forced to 0 (Common) */ +# define UART_MR_PAR_MARK (3 << UART_MR_PAR_SHIFT) /* Mark: parity forced to 1 (Common) */ +# define UART_MR_PAR_NONE (4 << UART_MR_PAR_SHIFT) /* No parity (Common) */ +# define UART_MR_PAR_MULTIDROP (6 << UART_MR_PAR_SHIFT) /* Multidrop mode (USART only) */ +#define USART_MR_NBSTOP_SHIFT (12) /* Bits 12-13: Number of Stop Bits (USART only) */ +#define USART_MR_NBSTOP_MASK (3 << USART_MR_NBSTOP_SHIFT) +# define USART_MR_NBSTOP_1 (0 << USART_MR_NBSTOP_SHIFT) /* 1 stop bit 1 stop bit */ +# define USART_MR_NBSTOP_1p5 (1 << USART_MR_NBSTOP_SHIFT) /* 1.5 stop bits */ +# define USART_MR_NBSTOP_2 (2 << USART_MR_NBSTOP_SHIFT) /* 2 stop bits 2 stop bits */ +#define UART_MR_CHMODE_SHIFT (14) /* Bits 14-15: Channel Mode (Common) */ +#define UART_MR_CHMODE_MASK (3 << UART_MR_CHMODE_SHIFT) +# define UART_MR_CHMODE_NORMAL (0 << UART_MR_CHMODE_SHIFT) /* Normal Mode */ +# define UART_MR_CHMODE_ECHO (1 << UART_MR_CHMODE_SHIFT) /* Automatic Echo */ +# define UART_MR_CHMODE_LLPBK (2 << UART_MR_CHMODE_SHIFT) /* Local Loopback */ +# define UART_MR_CHMODE_RLPBK (3 << UART_MR_CHMODE_SHIFT) /* Remote Loopback */ +#define USART_MR_MSBF (1 << 16) /* Bit 16: Bit Order or SPI Clock Polarity (USART only) */ +#define USART_MR_CPOL (1 << 16) +#define USART_MR_MODE9 (1 << 17) /* Bit 17: 9-bit Character Length (USART only) */ +#define USART_MR_CLKO (1 << 18) /* Bit 18: Clock Output Select (USART only) */ +#define USART_MR_OVER (1 << 19) /* Bit 19: Oversampling Mode (USART only) */ +#define USART_MR_INACK (1 << 20) /* Bit 20: Inhibit Non Acknowledge (USART only) */ +#define USART_MR_DSNACK (1 << 21) /* Bit 21: Disable Successive NACK (USART only) */ +#define USART_MR_VARSYNC (1 << 22) /* Bit 22: Variable Synchronization of Command/Data Sync Start Frame Delimiter (USART only) */ +#define USART_MR_INVDATA (1 << 23) /* Bit 23: INverted Data (USART only) */ +#define USART_MR_MAXITER_SHIFT (24) /* Bits 24-26: Max iterations (ISO7816 T=0 (USART only) */ +#define USART_MR_MAXITER_MASK (7 << USART_MR_MAXITER_SHIFT) +#define USART_MR_FILTER (1 << 28) /* Bit 28: Infrared Receive Line Filter (USART only) */ +#define USART_MR_MAN (1 << 29) /* Bit 29: Manchester Encoder/Decoder Enable (USART only) */ +#define USART_MR_MODSYNC (1 << 30) /* Bit 30: Manchester Synchronization Mode (USART only) */ +#define USART_MR_ONEBIT (1 << 31) /* Bit 31: Start Frame Delimiter Selector (USART only) */ + +/* UART Interrupt Enable Register, UART Interrupt Disable Register, UART Interrupt Mask + * Register, and UART Status Register common bit field definitions + */ + +#define UART_INT_RXRDY (1 << 0) /* Bit 0: RXRDY Interrupt (Common) */ +#define UART_INT_TXRDY (1 << 1) /* Bit 1: TXRDY Interrupt (Common) */ +#define UART_INT_RXBRK (1 << 2) /* Bit 2: Break Received/End of Break */ +#define UART_INT_ENDRX (1 << 3) /* Bit 3: End of Receive Transfer Interrupt (Common) */ +#define UART_INT_ENDTX (1 << 4) /* Bit 4: End of Transmit Interrupt (Common) */ +#define UART_INT_OVRE (1 << 5) /* Bit 5: Overrun Error Interrupt (Common) */ +#define UART_INT_FRAME (1 << 6) /* Bit 6: Framing Error Interrupt (Common) */ +#define UART_INT_PARE (1 << 7) /* Bit 7: Parity Error Interrupt (Common) */ +#define USART_INT_TIMEOUT (1 << 8) /* Bit 8: Time-out Interrupt (USART only) */ +#define UART_INT_TXEMPTY (1 << 9) /* Bit 9: TXEMPTY Interrupt (Common) */ +#define USART_INT_ITER (1 << 10) /* Bit 10: Iteration Interrupt (USART only) */ +#define USART_INT_UNRE (1 << 10) /* Bit 10: SPI Underrun Error Interrupt (USART only) */ +#define UART_INT_TXBUFE (1 << 11) /* Bit 11: Buffer Empty Interrupt (Common) */ +#define UART_INT_RXBUFF (1 << 12) /* Bit 12: Buffer Full Interrupt (Common) */ +#define USART_INT_NACK (1 << 13) /* Bit 13: Non Acknowledge Interrupt (USART only) */ +#define USART_INT_CTSIC (1 << 19) /* Bit 19: Clear to Send Input Change Interrupt (USART only) */ +#define USART_INT_MANE (1 << 24) /* Bit 24: Manchester Error Interrupt (USART only) */ + +/* UART Receiver Holding Register */ + +#define UART_RHR_RXCHR_SHIFT (0) /* Bits 0-7: Received Character (UART only) */ +#define UART_RHR_RXCHR_MASK (0xff << UART_RHR_RXCHR_SHIFT) +#define USART_RHR_RXCHR_SHIFT (0) /* Bits 0-8: Received Character (USART only) */ +#define USART_RHR_RXCHR_MASK (0x1ff << UART_RHR_RXCHR_SHIFT) +#define USART_RHR_RXSYNH (1 << 15) /* Bit 15: Received Sync (USART only) */ + +/* UART Transmit Holding Register */ + +#define UART_THR_TXCHR_SHIFT (0) /* Bits 0-7: Character to be Transmitted (UART only) */ +#define UART_THR_TXCHR_MASK (0xff << UART_THR_TXCHR_SHIFT) +#define USART_THR_TXCHR_SHIFT (0) /* Bits 0-8: Character to be Transmitted (USART only) */ +#define USART_THR_TXCHR_MASK (0x1ff << USART_THR_TXCHR_SHIFT) +#define USART_THR_TXSYNH (1 << 15) /* Bit 15: Sync Field to be tran (USART only) */ + +/* UART Baud Rate Generator Register */ + +#define UART_BRGR_CD_SHIFT (0) /* Bits 0-15: Clock Divisor (Common) */ +#define UART_BRGR_CD_MASK (0xffff << UART_BRGR_CD_SHIFT) +#define UART_BRGR_FP_SHIFT (16) /* Bits 16-18: Fractional Part (USART only) */ +#define UART_BRGR_FP_MASK (7 << UART_BRGR_FP_SHIFT) + +/* USART Receiver Time-out Register (USART only) */ + +#define USART_RTOR_TO_SHIFT (0) /* Bits 0-15: Time-out Value (USART only) */ +#define USART_RTOR_TO_MASK (0xffff << USART_RTOR_TO_SHIFT) + +/* USART Transmitter Timeguard Register (USART only) */ + +#define USART_TTGR_TG_SHIFT (0) /* Bits 0-7: Timeguard Value (USART only) */ +#define USART_TTGR_TG_MASK (0xff << USART_TTGR_TG_SHIFT) + +/* USART FI DI RATIO Register (USART only) */ + +#define USART_FIDI_RATIO_SHIFT (0) /* Bits 0-10: FI Over DI Ratio Value (USART only) */ +#define USART_FIDI_RATIO_MASK (0x7ff << USART_FIDI_RATIO_SHIFT) + +/* USART Number of Errors Register (USART only) */ + +#define USART_NER_NBERRORS_SHIFT (0) /* Bits 0-7: Number of Errrors (USART only) */ +#define USART_NER_NBERRORS_MASK (0xff << USART_NER_NBERRORS_SHIFT) + +/* USART IrDA FILTER Register (USART only) */ + +#define USART_IF_IRDAFILTER_SHIFT (0) /* Bits 0-7: IrDA Filter (USART only) */ +#define USART_IF_IRDAFILTER_MASK (0xff << USART_IF_IRDAFILTER_SHIFT) + +/* USART Manchester Configuration Register (USART only) */ + +#define USART_MAN_TXPL_SHIFT (0) /* Bits 0-3: Transmitter Preamble Length (USART only) */ +#define USART_MAN_TXPL_MASK (15 << USART_MAN_TXPL_SHIFT) +#define USART_MAN_TXPP_SHIFT (8) /* Bits 8-9: Transmitter Preamble Pattern (USART only) */ +#define USART_MAN_TXPP_MASK (3 << USART_MAN_TXPP_SHIFT) +# define USART_MAN_TXPP_ALLONE (0 << USART_MAN_TXPP_SHIFT) /* ALL_ONE */ +# define USART_MAN_TXPP_ALLZERO (1 << USART_MAN_TXPP_SHIFT) /* ALL_ZERO */ +# define USART_MAN_TXPP_ZEROONE (2 << USART_MAN_TXPP_SHIFT) /* ZERO_ONE */ +# define USART_MAN_TXPP_ONEZERO (3 << USART_MAN_TXPP_SHIFT) /* ONE_ZERO */ +#define USART_MAN_TXMPOL (1 << 12) /* Bit 12: Transmitter Manchester Polarity (USART only) */ +#define USART_MAN_RXPL_SHIFT (16) /* Bits 16-19: Receiver Preamble Length (USART only) */ +#define USART_MAN_RXPL_MASK (15 << USART_MAN_RXPL_SHIFT) +#define USART_MAN_RXPP_SHIFT (24) /* Bits 24-25: Receiver Preamble Pattern detected (USART only) */ +#define USART_MAN_RXPP_MASK (3 << USART_MAN_RXPP_SHIFT) +# define USART_MAN_RXPP_ALLONE (0 << USART_MAN_RXPP_SHIFT) /* ALL_ONE */ +# define USART_MAN_RXPP_ALLZERO (1 << USART_MAN_RXPP_SHIFT) /* ALL_ZERO */ +# define USART_MAN_RXPP_ZEROONE (2 << USART_MAN_RXPP_SHIFT) /* ZERO_ONE */ +# define USART_MAN_RXPP_ONEZERO (3 << USART_MAN_RXPP_SHIFT) /* ONE_ZERO */ +#define USART_MAN_RXMPOL (1 << 28) /* Bit 28: Receiver Manchester Polarity (USART only) */ +#define USART_MAN_DRIFT (1 << 30) /* Bit 30: Drift compensation (USART only) */ + +/* USART Write Protect Mode Register (USART only) */ + +#define USART_WPMR_WPEN (1 << 0) /* Bit 0: Write Protect Enable (USART only) */ +#define USART_WPMR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protect KEY (USART only) */ +#define USART_WPMR_WPKEY_MASK (0x00ffffff << USART_WPMR_WPKEY_SHIFT) + +/* USART Write Protect Status Register (USART only) */ + +#define USART_WPSR_WPVS (1 << 0) /* Bit 0: Write Protect Violation Status (USART only) */ +#define USART_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protect Violation Source (USART only) */ +#define USART_WPSR_WPVSRC_MASK (0xffff << USART_WPSR_WPVSRC_SHIFT) + +/* USART Version Register */ + +#define USART_VERSION_VERSION_SHIFT (0) /* Bits 0-11: Macrocell version number (USART only) */ +#define USART_VERSION_VERSION_MASK (0xfff << USART_VERSION_VERSION_SHIFT) +#define USART_VERSION_MFN_SHIFT (16) /* Bits 16-18: Reserved (USART only) */ +#define USART_VERSION_MFN_MASK (7 << USART_VERSION_MFN_SHIFT) + +/************************************************************************************************ + * Public Types + ************************************************************************************************/ + +/************************************************************************************************ + * Public Data + ************************************************************************************************/ + +/************************************************************************************************ + * Public Functions + ************************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_UART_H */ diff --git a/nuttx/arch/arm/src/sam3u/sam3u_udphs.h b/nuttx/arch/arm/src/sam3u/sam3u_udphs.h index 1ce901e1d..e6eb88c77 100644 --- a/nuttx/arch/arm/src/sam3u/sam3u_udphs.h +++ b/nuttx/arch/arm/src/sam3u/sam3u_udphs.h @@ -1,370 +1,371 @@ -/****************************************************************************************
- * arch/arm/src/sam3u/sam3u_udphs.h
- *
- * Copyright (C) 2009 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_UDPHS_H
-#define __ARCH_ARM_SRC_SAM3U_SAM3U_UDPHS_H
-
-/****************************************************************************************
- * Included Files
- ****************************************************************************************/
-
-#include <nuttx/config.h>
-
-#include "chip.h"
-#include "sam3u_memorymap.h"
-
-/****************************************************************************************
- * Pre-processor Definitions
- ****************************************************************************************/
-
-/* UDPHS register offsets ***************************************************************/
-
-#define SAM3U_UDPHS_CTRL_OFFSET 0x00 /* UDPHS Control Register */
-#define SAM3U_UDPHS_FNUM_OFFSET 0x04 /* UDPHS Frame Number Register */
- /* 0x08-0x0C: Reserved */
-#define SAM3U_UDPHS_IEN_OFFSET 0x10 /* UDPHS Interrupt Enable Register */
-#define SAM3U_UDPHS_INTSTA_OFFSET 0x14 /* UDPHS Interrupt Status Register */
-#define SAM3U_UDPHS_CLRINT_OFFSET 0x18 /* UDPHS Clear Interrupt Register */
-#define SAM3U_UDPHS_EPTRST_OFFSET 0x1c /* UDPHS Endpoints Reset Register */
- /* 0x20-0xcc: Reserved */
-#define SAM3U_UDPHS_TST_OFFSET 0xe0 /* UDPHS Test Register */
- /* 0xE4-0xE8: Reserved */
-#define SAM3U_UDPHS_IPNAME1_OFFSET 0xf0 /* UDPHS Name1 Register */
-#define SAM3U_UDPHS_IPNAME2_OFFSET 0xf4 /* UDPHS Name2 Register */
-#define SAM3U_UDPHS_IPFEATURES_OFFSET 0xf8 /* UDPHS Features Register */
-
-/* Endpoint registers: Offsets for Endpoints 0-6: 0x100, 0x120, 0x140, 0x160, 0x180,
- * 0x1a0, and 0x1c0
- */
-
-#define SAM3U_UDPHSEP_OFFSET(n) (0x100+((n)<<5))
-#define SAM3U_UDPHSEP_CFG_OFFSET 0x00 /* UDPHS Endpoint Configuration Register */
-#define SAM3U_UDPHSEP_CTLENB_OFFSET 0x04 /* UDPHS Endpoint Control Enable Register */
-#define SAM3U_UDPHSEP_CTLDIS_OFFSET 0x08 /* UDPHS Endpoint Control Disable Register */
-#define SAM3U_UDPHSEP_CTL_OFFSET 0x0c /* UDPHS Endpoint Control Register */
- /* 0x10: Reserved */
-#define SAM3U_UDPHSEP_SETSTA_OFFSET 0x14 /* UDPHS Endpoint Set Status Register */
-#define SAM3U_UDPHSEP_CLRSTA_OFFSET 0x18 /* UDPHS Endpoint Clear Status Register */
-#define SAM3U_UDPHSEP_STA_OFFSET 0x1c /* UDPHS Endpoint Status Register */
- /* 0x1e0-0x300: Reserved */
- /* 0x300-0x30c: Reserved */
-/* DMA Channel Registers: Offsets for DMA channels 1-6 0x320, 0x330, 0x340, 0x350, and
- * 0x360. NOTE that there is no DMA channel 0.
- */
-
-#define SAM3U_UDPHSDMA_OFFSET(n) (0x310+((n)<<4))
-#define SAM3U_UDPHSDMA_NXTDSC_OFFSET 0x00 /* UDPHS DMA Next Descriptor Address Register */
-#define SAM3U_UDPHSDMA_ADDRESS_OFFSET 0x04 /* UDPHS DMA Channel Address Register */
-#define SAM3U_UDPHSDMA_CONTROL_OFFSET 0x08 /* UDPHS DMA Channel Control Register */
-#define SAM3U_UDPHSDMA_STATUS_OFFSET) 0x0c /* UDPHS DMA Channel Status Register */
-
-/* UDPHS register adresses **************************************************************/
-
-#define SAM3U_UDPHS_CTRL (SAM3U_UDPHS_BASE+SAM3U_UDPHS_CTRL_OFFSET)
-#define SAM3U_UDPHS_FNUM (SAM3U_UDPHS_BASE+SAM3U_UDPHS_FNUM_OFFSET)
-#define SAM3U_UDPHS_IEN (SAM3U_UDPHS_BASE+SAM3U_UDPHS_IEN_OFFSET)
-#define SAM3U_UDPHS_INTSTA (SAM3U_UDPHS_BASE+SAM3U_UDPHS_INTSTA_OFFSET)
-#define SAM3U_UDPHS_CLRINT (SAM3U_UDPHS_BASE+ SAM3U_UDPHS_CLRINT_OFFSET)
-#define SAM3U_UDPHS_EPTRST (SAM3U_UDPHS_BASE+SAM3U_UDPHS_EPTRST_OFFSET)
-#define SAM3U_UDPHS_TST (SAM3U_UDPHS_BASE+SAM3U_UDPHS_TST_OFFSET)
-#define SAM3U_UDPHS_IPNAME1 (SAM3U_UDPHS_BASE+SAM3U_UDPHS_IPNAME1_OFFSET)
-#define SAM3U_UDPHS_IPNAME2 (SAM3U_UDPHS_BASE+SAM3U_UDPHS_IPNAME2_OFFSET)
-#define SAM3U_UDPHS_IPFEATURES (SAM3U_UDPHS_BASE+SAM3U_UDPHS_IPFEATURES_OFFSET)
-
-/* Endpoint registers */
-
-#define SAM3U_UDPHSEP_BASE(n)) (SAM3U_UDPHS_BASE+SAM3U_UDPHSEP_OFFSET(n))
-#define SAM3U_UDPHSEP_CFG(n) (SAM3U_UDPHSEP_BASE(n)+SAM3U_UDPHSEP_CFG_OFFSET)
-#define SAM3U_UDPHSEP_CTLENB(n) (SAM3U_UDPHSEP_BASE(n)+SAM3U_UDPHSEP_CTLENB_OFFSET)
-#define SAM3U_UDPHSEP_CTLDIS(n) (SAM3U_UDPHSEP_BASE(n)+SAM3U_UDPHSEP_CTLDIS_OFFSET)
-#define SAM3U_UDPHSEP_CTL(n) (SAM3U_UDPHSEP_BASE(n)+SAM3U_UDPHSEP_CTL_OFFSET)
-#define SAM3U_UDPHSEP_SETSTA(n) (SAM3U_UDPHSEP_BASE(n)+SAM3U_UDPHSEP_SETSTA_OFFSET)
-#define SAM3U_UDPHSEP_CLRSTA(n) (SAM3U_UDPHSEP_BASE(n)+SAM3U_UDPHSEP_CLRSTA_OFFSET)
-#define SAM3U_UDPHSEP_STA(n) (SAM3U_UDPHSEP_BASE(n)+SAM3U_UDPHSEP_STA_OFFSET)
-
-/* DMA Channel Registers*/
-
-#define SAM3U_UDPHSDMA_BASE(n) (SAM3U_UDPHS_BASE+SAM3U_UDPHSDMA_OFFSET(n))
-#define SAM3U_UDPHSDMA_NXTDSC(n) (SAM3U_UDPHSDMA_BASE(n)+SAM3U_UDPHSDMA_NXTDSC_OFFSET)
-#define SAM3U_UDPHSDMA_ADDRESS(n) (SAM3U_UDPHSDMA_BASE(n)+SAM3U_UDPHSDMA_ADDRESS_OFFSET)
-#define SAM3U_UDPHSDMA_CONTROL(n) (SAM3U_UDPHSDMA_BASE(n)+SAM3U_UDPHSDMA_CONTROL_OFFSET)
-#define SAM3U_UDPHSDMA_STATUS(n) (SAM3U_UDPHSDMA_BASE(n)+SAM3U_UDPHSDMA_STATUS_OFFSET)
-
-/* UDPHS register bit definitions *******************************************************/
-/* UDPHS Control Register */
-
-#define UDPHS_CTRL_DEVADDR_SHIFT (0) /* Bits 0-6: UDPHS Address */
-#define UDPHS_CTRL_DEVADDR_MASK (0x7f << UDPHS_CTRL_DEVADDR_SHIFT)
-#define UDPHS_CTRL_FADDREN (1 << 7) /* Bit 7: Function Address Enable */
-#define UDPHS_CTRL_ENUDPHS (1 << 8) /* Bit 8: UDPHS Enable */
-#define UDPHS_CTRL_DETACH (1 << 9) /* Bit 9: Detach Command */
-#define UDPHS_CTRL_REWAKEUP (1 << 10) /* Bit 10: Send Remote Wake Up */
-#define UDPHS_CTRL_PULLDDIS (1 << 11) /* Bit 11: Pull-Down Disable */
-
-/* UDPHS Frame Number Register */
-
-#define UDPHS_FNUM_MICROFRAMENUM_SHIFT (0) /* Bits 0-2: Microframe Num */
-#define UDPHS_FNUM_MICROFRAMENUM_MASK (7 << UDPHS_FNUM_MICROFRAMENUM_SHIFT)
-#define UDPHS_FNUM_FRAMENUMBER_SHIFT (3) /* Bits 3-7: Frame Number in Packet Field Formats */
-#define UDPHS_FNUM_FRAMENUMBER_MASK (31 << UDPHS_FNUM_FRAMENUMBER_SHIFT)
-#define UDPHS_FNUM_FNUMERR_SHIFT (8) /* Bits 8-13: Frame Number CRC Error */
-#define UDPHS_FNUM_FNUMERR_MASK (63 << UDPHS_FNUM_FNUMERR_SHIFT)
-
-/* UDPHS Interrupt Enable Register, UDPHS Interrupt Status Register, and UDPHS Clear
- * Interrupt Register common bit-field definitions
- */
-
-#define USBPHS_INT_DETSUSPD (1 << 1) /* Bit 1: Suspend Interrupt (Common) */
-#define USBPHS_INT_MICROSOF (1 << 2) /* Bit 2: Micro-SOF Interrupt (Common) */
-#define USBPHS_INT_INTSOF (1 << 3) /* Bit 3: SOF Interrupt (Common) */
-#define USBPHS_INT_ENDRESET (1 << 4) /* Bit 4: End Of Reset Interrupt (Common) */
-#define USBPHS_INT_WAKEUP (1 << 5) /* Bit 5: Wake Up CPU Interrupt (Common) */
-#define USBPHS_INT_ENDOFRSM (1 << 6) /* Bit 6: End Of Resume Interrupt (Common) */
-#define USBPHS_INT_UPSTRRES (1 << 7) /* Bit 7: Upstream Resume Interrupt (Common) */
-#define USBPHS_INT_EPT(n) (1 << ((n)+8))
-#define USBPHS_INT_EPT0 (1 << 8) /* Bit 8: Endpoint 0 Interrupt (not Clear) */
-#define USBPHS_INT_EPT1 (1 << 9) /* Bit 9: Endpoint 1 Interrupt (not Clear) */
-#define USBPHS_INT_EPT2 (1 << 10) /* Bit 10: Endpoint 2 Interrupt (not Clear) */
-#define USBPHS_INT_EPT3 (1 << 11) /* Bit 11: Endpoint 3 Interrupt (not Clear) */
-#define USBPHS_INT_EPT4 (1 << 12) /* Bit 12: Endpoint 4 Interrupt (not Clear) */
-#define USBPHS_INT_EPT5 (1 << 13) /* Bit 13: Endpoint 5 Interrupt (not Clear) */
-#define USBPHS_INT_EPT6 (1 << 13) /* Bit 14: Endpoint 6 Interrupt (not Clear) */
-#define USBPHS_INT_DMA(n) (1<<((n)+24))
-#define USBPHS_INT_DMA1 (1 << 25) /* Bit 25: DMA Channel 1 Interrupt (not Clear) */
-#define USBPHS_INT_DMA2 (1 << 26) /* Bit 26: DMA Channel 2 Interrupt (not Clear) */
-#define USBPHS_INT_DMA3 (1 << 27) /* Bit 27: DMA Channel 3 Interrupt (not Clear) */
-#define USBPHS_INT_DMA4 (1 << 28) /* Bit 28: DMA Channel 4 Interrupt (not Clear) */
-#define USBPHS_INT_DMA5 (1 << 29) /* Bit 29: DMA Channel 5 Interrupt (not Clear) */
-#define USBPHS_INT_DMA6 (1 << 30) /* Bit 30: DMA Channel 6 Interrupt (not Clear) */
-
-/* UDPHS Endpoints Reset Register */
-
-#define UDPHS_EPTRST_EPT(n) (1<<(n)) /* Bit 0-6: Endpoint n Reset */
-
-/* UDPHS Test Register */
-
-#define UDPHS_TST_SPEEDCFG_SHIFT (0) /* Bits 0-1: Speed Configuration */
-#define UDPHS_TST_SPEEDCFG_MASK (3 << UDPHS_TST_SPEEDCFG_SHIFT)
-00 Normal Mode
-10 Force High Speed
-11 Force Full Speed
-#define UDPHS_TST_TSTJ (1 << 2) /* Bit 2: Test J Mode */
-#define UDPHS_TST_TSTK (1 << 3) /* Bit 3: Test K Mode */
-#define UDPHS_TST_TSTPKT (1 << 4) /* Bit 4: Test Packet Mo */
-#define UDPHS_TST_OPMODE2 (1 << 5) /* Bit 5: OpMode2 */
-
-/* UDPHS Features Register */
-
-#define UDPHS_IPFEATURES_EPTNBRMAX_SHIFT (0) /* Bits 0-3: Max Number of Endpoints */
-#define UDPHS_IPFEATURES_EPTNBRMAX_MASK (15 << UDPHS_IPFEATURES_EPTNBRMAX_SHIFT)
-#define UDPHS_IPFEATURES_DMACHANNELNBR_SHIFT (4) /* Bits 4-6: Number of DMA Channels */
-#define UDPHS_IPFEATURES_DMACHANNELNBR_MASK (7 << UDPHS_IPFEATURES_DMACHANNELNBR_SHIFT)
-#define UDPHS_IPFEATURES_DMABSIZ (1 << 7) /* Bit 7: DMA Buffer Size */
-#define UDPHS_IPFEATURES_DMAFIFOWDDEPTH_SHIFT (8) /* Bits 8-11: DMA FIFO Depth in Words */
-#define UDPHS_IPFEATURES_DMAFIFOWDDEPTH_MASK (15 << UDPHS_IPFEATURES_DMAFIFOWDDEPTH_SHIFT)
-# define UDPHS_IPFEATURES_DMAFIFOWDDEPTH(n) ((n)&15)
-#define UDPHS_IPFEATURES_FIFOMAXSIZE_SHIFT (12) /* Bits 12-14: DPRAM Size */
-#define UDPHS_IPFEATURES_FIFOMAXSIZE_MASK (7 << UDPHS_IPFEATURES_FIFOMAXSIZE_SHIFT)
-# define UDPHS_IPFEATURES_FIFOMAXSIZE_128b (0 << UDPHS_IPFEATURES_FIFOMAXSIZE_SHIFT) /* DPRAM 128 bytes */
-# define UDPHS_IPFEATURES_FIFOMAXSIZE_256b (1 << UDPHS_IPFEATURES_FIFOMAXSIZE_SHIFT) /* DPRAM 256 bytes */
-# define UDPHS_IPFEATURES_FIFOMAXSIZE_512b (2 << UDPHS_IPFEATURES_FIFOMAXSIZE_SHIFT) /* DPRAM 512 bytes */
-# define UDPHS_IPFEATURES_FIFOMAXSIZE_1Kb (3 << UDPHS_IPFEATURES_FIFOMAXSIZE_SHIFT) /* DPRAM 1024 bytes */
-# define UDPHS_IPFEATURES_FIFOMAXSIZE_2Kb (4 << UDPHS_IPFEATURES_FIFOMAXSIZE_SHIFT) /* DPRAM 2048 bytes */
-# define UDPHS_IPFEATURES_FIFOMAXSIZE_4Kb (5 << UDPHS_IPFEATURES_FIFOMAXSIZE_SHIFT) /* DPRAM 4096 bytes */
-# define UDPHS_IPFEATURES_FIFOMAXSIZE_8Kb (6 << UDPHS_IPFEATURES_FIFOMAXSIZE_SHIFT) /* DPRAM 8192 bytes */
-# define UDPHS_IPFEATURES_FIFOMAXSIZE_16Kb (7 << UDPHS_IPFEATURES_FIFOMAXSIZE_SHIFT) /* DPRAM 16384 bytes */
-#define UDPHS_IPFEATURES_BWDPRAM (1 << 15) /* Bit 15: DPRAM Byte Write Capability */
-#define UDPHS_IPFEATURES_DATAB168 (1 << 15) /* Bit 15: UTMI DataBus16_8 */
-#define UDPHS_IPFEATURES_ISOEPT(n) (1<<((n)+16)
-#define UDPHS_IPFEATURES_ISOEPT1 (1 << 17) /* Bit 17: EP1 High B/W Isoc Capability */
-#define UDPHS_IPFEATURES_ISOEPT2 (1 << 18) /* Bit 18: EP2 High B/W Isoc Capability */
-#define UDPHS_IPFEATURES_ISOEPT3 (1 << 19) /* Bit 19: EP3 High B/W Isoc Capability */
-#define UDPHS_IPFEATURES_ISOEPT4 (1 << 20) /* Bit 20: EP4 High B/W Isoc Capability */
-#define UDPHS_IPFEATURES_ISOEPT5 (1 << 21) /* Bit 21: EP5 High B/W Isoc Capability */
-#define UDPHS_IPFEATURES_ISOEPT6 (1 << 22) /* Bit 22: EP6 High B/W Isoc Capability */
-#define UDPHS_IPFEATURES_ISOEPT7 (1 << 23) /* Bit 23: EP7 High B/W Isoc Capability */
-#define UDPHS_IPFEATURES_ISOEPT8 (1 << 24) /* Bit 24: EP8 High B/W Isoc Capability */
-#define UDPHS_IPFEATURES_ISOEPT9 (1 << 25) /* Bit 25: EP9 High B/W Isoc Capability */
-#define UDPHS_IPFEATURES_ISOEPT0 (1 << 26) /* Bit 26: EP10 High B/W Isoc Capability */
-#define UDPHS_IPFEATURES_ISOEPT1 (1 << 27) /* Bit 27: EP11 High B/W Isoc Capability */
-#define UDPHS_IPFEATURES_ISOEPT2 (1 << 28) /* Bit 28: EP12 High B/W Isoc Capability */
-#define UDPHS_IPFEATURES_ISOEPT3 (1 << 29) /* Bit 29: EP13 High B/W Isoc Capability */
-#define UDPHS_IPFEATURES_ISOEPT4 (1 << 30) /* Bit 30: EP14 High B/W Isoc Capability */
-#define UDPHS_IPFEATURES_ISOEPT5 (1 << 31) /* Bit 31: EP15 High B/W Isoc Capability */
-
-/* UDPHS Endpoint Configuration Register (0-6) */
-
-#define UDPHSEP_CFG_SIZE_SHIFT (0) /* Bits 0-2: Endpoint Size */
-#define UDPHSEP_CFG_SIZE_MASK (7 << UDPHSEP_CFG_SIZE_SHIFT)
-# define UDPHSEP_CFG_SIZE_8b (0 << UDPHSEP_CFG_SIZE_SHIFT) /* 8 bytes */
-# define UDPHSEP_CFG_SIZE_16b (1 << UDPHSEP_CFG_SIZE_SHIFT) /* 16 bytes */
-# define UDPHSEP_CFG_SIZE_32b (2 << UDPHSEP_CFG_SIZE_SHIFT) /* 32 bytes */
-# define UDPHSEP_CFG_SIZE_16b (3 << UDPHSEP_CFG_SIZE_SHIFT) /* 64 bytes */
-# define UDPHSEP_CFG_SIZE_128b (4 << UDPHSEP_CFG_SIZE_SHIFT) /* 128 bytes */
-# define UDPHSEP_CFG_SIZE_256b (5 << UDPHSEP_CFG_SIZE_SHIFT) /* 256 bytes */
-# define UDPHSEP_CFG_SIZE_512b (6 << UDPHSEP_CFG_SIZE_SHIFT) /* 512 bytes */
-# define UDPHSEP_CFG_SIZE_1Kb (7 << UDPHSEP_CFG_SIZE_SHIFT) /* 1024 bytes */
-#define UDPHSEP_CFG_DIR (1 << 3) /* Bit 3: Endpoint Direction */
-#define UDPHSEP_CFG_TYPE_SHIFT (4) /* Bits 4-5: Endpoint Type */
-#define UDPHSEP_CFG_TYPE_MASK (3 << UDPHSEP_CFG_TYPE_SHIFT)
-# define UDPHSEP_CFG_TYPE_CNTRL (0 << UDPHSEP_CFG_TYPE_SHIFT) /* Control endpoint */
-# define UDPHSEP_CFG_TYPE_ISOC (1 << UDPHSEP_CFG_TYPE_SHIFT) /* Isochronous endpoint */
-# define UDPHSEP_CFG_TYPE_BULK (2 << UDPHSEP_CFG_TYPE_SHIFT) /* Bulk endpoint */
-# define UDPHSEP_CFG_TYPE_INTR (3 << UDPHSEP_CFG_TYPE_SHIFT) /* Interrupt endpoint */
-#define UDPHSEP_CFG_BKNUMBER_SHIFT (6) /* Bits 6-7: Number of Banks */
-#define UDPHSEP_CFG_BKNUMBER_MASK (3 << UDPHSEP_CFG_BKNUMBER_SHIFT)
-# define UDPHSEP_CFG_BKNUMBER_0BANK (0 << UDPHSEP_CFG_BKNUMBER_SHIFT) /* Zero bank (unmapped) */
-# define UDPHSEP_CFG_BKNUMBER_1BANK (1 << UDPHSEP_CFG_BKNUMBER_SHIFT) /* One bank (bank 0) */
-# define UDPHSEP_CFG_BKNUMBER_2BANK (2 << UDPHSEP_CFG_BKNUMBER_SHIFT) /* Double bank (bank 0-1) */
-# define UDPHSEP_CFG_BKNUMBER_3BANK (3 << UDPHSEP_CFG_BKNUMBER_SHIFT) /* Triple bank (bank 0-2) */
-#define UDPHSEP_CFG_NBTRANS_SHIFT (8) /* Bits 8-9: Number Of Transaction per Microframe */
-#define UDPHSEP_CFG_NBTRANS_MASK (3 << UDPHSEP_CFG_NBTRANS_SHIFT)
-#define UDPHSEP_CFG_MAPD (1 << 31) /*Bit 31: Endpoint Mapped */
-
-/* UDPHS Endpoint Control Enable Register, UDPHS Endpoint Control Disable Register,
- * and UDPHS Endpoint Control Register common bit-field definitions
- */
-
-#define UDPHSEP_INT_EPT (1 << 0) /* Bit 0: Endpoint Enable/Disable */
-#define UDPHSEP_INT_AUTOVALID (1 << 1) /* Bit 1: Packet Auto-Valid */
-#define UDPHSEP_INT_INTDISDMA (1 << 3) /* Bit 3: Interrupts Disable DMA */
-#define UDPHSEP_INT_NYETDIS (1 << 4) /* Bit 4: NYET Disable (HS Bulk OUT EPs) */
-#define UDPHSEP_INT_DATAXRX (1 << 6) /* Bit 6: DATAx Interrupt Enable (High B/W Isoc OUT EPs) */
-#define UDPHSEP_INT_MDATARX (1 << 7) /* Bit 7: MDATA Interrupt Enable (High B/W Isoc OUT EPs) */
-#define UDPHSEP_INT_ERROVFLW (1 << 8) /* Bit 8: Overflow Error Interrupt */
-#define UDPHSEP_INT_RXBKRDY (1 << 9) /* Bit 9: Received OUT Data Interrupt */
-#define UDPHSEP_INT_TXCOMPLT (1 << 10) /* Bit 10: Transmitted IN Data Complete Interrupt */
-#define UDPHSEP_INT_TXPKRDY (1 << 11) /* Bit 11: TX Packet Ready Interrupt */
-#define UDPHSEP_INT_ERRTRANS (1 << 11) /* Bit 11: Transaction Error Interrupt */
-#define UDPHSEP_INT_RXSETUP (1 << 12) /* Bit 12: Received SETUP Interrupt */
-#define UDPHSEP_INT_ERRFLISO (1 << 12) /* Bit 12: Error Flow Interrupt */
-#define UDPHSEP_INT_STALLSNT (1 << 13) /* Bit 13: Stall Sent Interrupt */
-#define UDPHSEP_INT_ERRCRISO (1 << 13) /* Bit 13: ISO CRC Error Error Interrupt */
-#define UDPHSEP_INT_ERRNBTRA (1 << 13) /* Bit 13: Number of Transaction Error Interrupt */
-#define UDPHSEP_INT_NAKIN (1 << 14) /* Bit 14: NAKIN Interrupt */
-#define UDPHSEP_INT_ERRFLUSH (1 << 14) /* Bit 14: Bank Flush Error Interrupt */
-#define UDPHSEP_INT_NAKOUT (1 << 15) /* Bit 15: NAKOUT Interrupt */
-#define UDPHSEP_INT_BUSYBANK (1 << 18) /* Bit 18: Busy Bank Interrupt */
-#define UDPHSEP_INT_SHRTPCKT (1 << 31) /* Bit 31: Short Packet Send/Short Packet Interrupt */
-
-/* UDPHS Endpoint Set Status Register */
-
-#define UDPHSEP_SETSTA_FRCESTALL (1 << 5) /* Bit 5: Stall Handshake Request Set */
-#define UDPHSEP_SETSTA_KILLBANK (1 << 9) /* Bit 9: KILL Bank Set (for IN Endpoint) */
-#define UDPHSEP_SETSTA_TXPKRDY (1 << 11) /* Bit 11: TX Packet Ready Set */
-
-/* UDPHS Endpoint Clear Status Register */
-
-#define UDPHSEP_CLRSTA_FRCESTALL (1 << 5) /* Bit 5: Stall Handshake Request Clear */
-#define UDPHSEP_CLRSTA_TOGGLESQ (1 << 6) /* Bit 6: Data Toggle Clear */
-#define UDPHSEP_CLRSTA_RXBKRDY (1 << 9) /* Bit 9: Received OUT Data Clear */
-#define UDPHSEP_CLRSTA_TXCOMPLT (1 << 10) /* Bit 10: Transmitted IN Data Complete Clear */
-#define UDPHSEP_CLRSTA_RXSETUP (1 << 12) /* Bit 12: Received SETUP Clear */
-#define UDPHSEP_CLRSTA_ERRFLISO (1 << 12) /* Bit 12: Error Flow Clear */
-#define UDPHSEP_CLRSTA_STALL_NT (1 << 13) /* Bit 13: Stall Sent Clear */
-#define UDPHSEP_CLRSTA_ERRNBTRA (1 << 13) /* Bit 13: Number of Transaction Error Clear */
-#define UDPHSEP_CLRSTA_NAKIN (1 << 14) /* Bit 14: NAKIN Clear */
-#define UDPHSEP_CLRSTA_ERRFLUSH (1 << 14) /* Bit 14: Bank Flush Error Clear */
-#define UDPHSEP_CLRSTA_NAKOUT (1 << 15) /* Bit 15: NAKOUT Clear */
-
-/* UDPHS Endpoint Status Register */
-
-#define UDPHSEP_STA_FRCESTALL (1 << 5) /* Bit 5: Stall Handshake Request */
-#define UDPHSEP_STA_TOGGLESQSTA_SHIFT (6) /* Bits 6-7: Toggle Sequencing */
-#define UDPHSEP_STA_TOGGLESQSTA_MASK (3 << UDPHSEP_STA_TOGGLESQSTA_SHIFT)
-# define UDPHSEP_STA_TOGGLESQSTA_DATA0 (0 << UDPHSEP_STA_TOGGLESQSTA_SHIFT) /* Data0 */
-# define UDPHSEP_STA_TOGGLESQSTA_DATA1 (1 << UDPHSEP_STA_TOGGLESQSTA_SHIFT) /* Data1 */
-# define UDPHSEP_STA_TOGGLESQSTA_DATA2 (2 << UDPHSEP_STA_TOGGLESQSTA_SHIFT) /* Data2 (High B/W Isoc EP) */
-# define UDPHSEP_STA_TOGGLESQSTA_MDATA (3 << UDPHSEP_STA_TOGGLESQSTA_SHIFT) /* MData (High B/W Isoc EP) */
-#define UDPHSEP_STA_ERROVFLW (1 << 8) /* Bit 8: Overflow Error */
-#define UDPHSEP_STA_RXBKRDY (1 << 9) /* Bit 9: Received OUT Data */
-#define UDPHSEP_STA_KILLBANK (1 << 9) /* Bit 9: KILL Bank */
-#define UDPHSEP_STA_TXCOMPLT (1 << 10) /* Bit 10: Transmitted IN Data Complete */
-#define UDPHSEP_STA_TXPKRDY (1 << 11) /* Bit 11: TX Packet Ready */
-#define UDPHSEP_STA_ERRTRANS (1 << 11) /* Bit 11: Transaction Error */
-#define UDPHSEP_STA_RXSETUP (1 << 12) /* Bit 12: Received SETUP */
-#define UDPHSEP_STA_ERRFLISO (1 << 12) /* Bit 12: Error Flow */
-#define UDPHSEP_STA_STALLSNT (1 << 13) /* Bit 13: Stall Sent */
-#define UDPHSEP_STA_ERRCRISO (1 << 13) /* Bit 13: CRC ISO Error */
-#define UDPHSEP_STA_ERRNBTRA (1 << 13) /* Bit 13: Number of Transaction Error */
-#define UDPHSEP_STA_NAKIN (1 << 14) /* Bit 14: NAK IN */
-#define UDPHSEP_STA_ERRFLUSH (1 << 14) /* Bit 14: Bank Flush Error */
-#define UDPHSEP_STA_NAKOUT (1 << 15) /* Bit 15: NAK OUT */
-#define UDPHSEP_STA_CURRENTBANK_SHIFT (16) /* Bits 16-17: Current Bank */
-#define UDPHSEP_STA_CURRENTBANK_MASK (3 << UDPHSEP_STA_CURRENTBANK_MASK)
-#define UDPHSEP_STA_CONTROLDIR_SHIFT (16) /* Bits 16-17: Control Direction */
-#define UDPHSEP_STA_CONTROLDIR_MASK (3 << UDPHSEP_STA_CONTROLDIR_SHIFT)
-#define UDPHSEP_STA_BUSYBANKSTA_SHIFT (18) /* Bits 18-19: Busy Bank Number */
-#define UDPHSEP_STA_BUSYBANKSTA_MASK (3 << UDPHSEP_STA_BUSYBANKSTA_SHIFT)
-#define UDPHSEP_STA_BYTECOUNT_SHIFT (20) /* Bits 20-23: UDPHS Byte Count */
-#define UDPHSEP_STA_BYTECOUNT_MASK (15 << UDPHSEP_STA_BYTECOUNT_SHIFT)
-#define UDPHSEP_STA_SHRTPCKT (1 << 31) /* Bit 31: Short Packet
-
-/* UDPHS DMA Channel Control Register */
-
-#define UDPHSDMA_CONTROL_CHANNENB (1 << 0) /* Bit 0: Channel Enable Command */
-#define UDPHSDMA_CONTROL_LDNXTDSC (1 << 1) /* Bit 1: Load Next Channel Xfr Desc Enable (Command) */
-#define UDPHSDMA_CONTROL_ENDTREN (1 << 2) /* Bit 2: End of Transfer Enable (Control) */
-#define UDPHSDMA_CONTROL_ENDBEN (1 << 3) /* Bit 3: End of Buffer Enable (Control) */
-#define UDPHSDMA_CONTROL_ENDTRIT (1 << 4) /* Bit 4: End of Transfer Interrupt Enable */
-#define UDPHSDMA_CONTROL_ENDBUFFIT (1 << 5) /* Bit 5: End of Buffer Interrupt Enable */
-#define UDPHSDMA_CONTROL_DESCLDIT (1 << 6) /* Bit 6: Descriptor Loaded Interrupt Enab */
-#define UDPHSDMA_CONTROL_BURSTLCK (1 << 7) /* Bit 7: Burst Lock Ena */
-#define UDPHSDMA_CONTROL_BUFFLENGTH_SHIFT (16) /* Bits 16-31: Buffer Byte Length (Write-only) */
-#define UDPHSDMA_CONTROL_BUFFLENGTH_MASK (0xffff << UDPHSDMA_CONTROL_BUFFLENGTH_SHIFT)
-
-/* UDPHS DMA Channel Status Register */
-
-#define UDPHSDMA_STATUS_CHANNENB (1 << 0) /* Bit 0: Channel Enable Status */
-#define UDPHSDMA_STATUS_CHANNACT (1 << 1) /* Bit 1: Channel Active Status */
-#define UDPHSDMA_STATUS_ENDTRST (1 << 4) /* Bit 4: End of Channel Transfer Status */
-#define UDPHSDMA_STATUS_ENDBFST (1 << 5) /* Bit 5: End of Channel Buffer Status */
-#define UDPHSDMA_STATUS_DESCLDST (1 << 6) /* Bit 6: Descriptor Loaded Status */
-#define UDPHSDMA_STATUS_BUFFCOUNT_SHIFT (16) /* Bits 16-31: Buffer Byte Count */
-#define UDPHSDMA_STATUS_BUFFCOUNT_MASK (0xffff << UDPHSDMA_STATUS_BUFFCOUNT_SHIFT)
-
-/****************************************************************************************
- * Public Types
- ****************************************************************************************/
-
-/****************************************************************************************
- * Public Data
- ****************************************************************************************/
-
-/****************************************************************************************
- * Public Functions
- ****************************************************************************************/
-
-#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_UDPHS_H */
+/**************************************************************************************** + * arch/arm/src/sam3u/sam3u_udphs.h + * + * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_UDPHS_H +#define __ARCH_ARM_SRC_SAM3U_SAM3U_UDPHS_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +#include <nuttx/config.h> + +#include "chip.h" +#include "sam3u_memorymap.h" + +/**************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************/ + +/* UDPHS register offsets ***************************************************************/ + +#define SAM3U_UDPHS_CTRL_OFFSET 0x00 /* UDPHS Control Register */ +#define SAM3U_UDPHS_FNUM_OFFSET 0x04 /* UDPHS Frame Number Register */ + /* 0x08-0x0C: Reserved */ +#define SAM3U_UDPHS_IEN_OFFSET 0x10 /* UDPHS Interrupt Enable Register */ +#define SAM3U_UDPHS_INTSTA_OFFSET 0x14 /* UDPHS Interrupt Status Register */ +#define SAM3U_UDPHS_CLRINT_OFFSET 0x18 /* UDPHS Clear Interrupt Register */ +#define SAM3U_UDPHS_EPTRST_OFFSET 0x1c /* UDPHS Endpoints Reset Register */ + /* 0x20-0xcc: Reserved */ +#define SAM3U_UDPHS_TST_OFFSET 0xe0 /* UDPHS Test Register */ + /* 0xE4-0xE8: Reserved */ +#define SAM3U_UDPHS_IPNAME1_OFFSET 0xf0 /* UDPHS Name1 Register */ +#define SAM3U_UDPHS_IPNAME2_OFFSET 0xf4 /* UDPHS Name2 Register */ +#define SAM3U_UDPHS_IPFEATURES_OFFSET 0xf8 /* UDPHS Features Register */ + +/* Endpoint registers: Offsets for Endpoints 0-6: 0x100, 0x120, 0x140, 0x160, 0x180, + * 0x1a0, and 0x1c0 + */ + +#define SAM3U_UDPHSEP_OFFSET(n) (0x100+((n)<<5)) +#define SAM3U_UDPHSEP_CFG_OFFSET 0x00 /* UDPHS Endpoint Configuration Register */ +#define SAM3U_UDPHSEP_CTLENB_OFFSET 0x04 /* UDPHS Endpoint Control Enable Register */ +#define SAM3U_UDPHSEP_CTLDIS_OFFSET 0x08 /* UDPHS Endpoint Control Disable Register */ +#define SAM3U_UDPHSEP_CTL_OFFSET 0x0c /* UDPHS Endpoint Control Register */ + /* 0x10: Reserved */ +#define SAM3U_UDPHSEP_SETSTA_OFFSET 0x14 /* UDPHS Endpoint Set Status Register */ +#define SAM3U_UDPHSEP_CLRSTA_OFFSET 0x18 /* UDPHS Endpoint Clear Status Register */ +#define SAM3U_UDPHSEP_STA_OFFSET 0x1c /* UDPHS Endpoint Status Register */ + /* 0x1e0-0x300: Reserved */ + /* 0x300-0x30c: Reserved */ +/* DMA Channel Registers: Offsets for DMA channels 1-6 0x320, 0x330, 0x340, 0x350, and + * 0x360. NOTE that there is no DMA channel 0. + */ + +#define SAM3U_UDPHSDMA_OFFSET(n) (0x310+((n)<<4)) +#define SAM3U_UDPHSDMA_NXTDSC_OFFSET 0x00 /* UDPHS DMA Next Descriptor Address Register */ +#define SAM3U_UDPHSDMA_ADDRESS_OFFSET 0x04 /* UDPHS DMA Channel Address Register */ +#define SAM3U_UDPHSDMA_CONTROL_OFFSET 0x08 /* UDPHS DMA Channel Control Register */ +#define SAM3U_UDPHSDMA_STATUS_OFFSET) 0x0c /* UDPHS DMA Channel Status Register */ + +/* UDPHS register adresses **************************************************************/ + +#define SAM3U_UDPHS_CTRL (SAM3U_UDPHS_BASE+SAM3U_UDPHS_CTRL_OFFSET) +#define SAM3U_UDPHS_FNUM (SAM3U_UDPHS_BASE+SAM3U_UDPHS_FNUM_OFFSET) +#define SAM3U_UDPHS_IEN (SAM3U_UDPHS_BASE+SAM3U_UDPHS_IEN_OFFSET) +#define SAM3U_UDPHS_INTSTA (SAM3U_UDPHS_BASE+SAM3U_UDPHS_INTSTA_OFFSET) +#define SAM3U_UDPHS_CLRINT (SAM3U_UDPHS_BASE+ SAM3U_UDPHS_CLRINT_OFFSET) +#define SAM3U_UDPHS_EPTRST (SAM3U_UDPHS_BASE+SAM3U_UDPHS_EPTRST_OFFSET) +#define SAM3U_UDPHS_TST (SAM3U_UDPHS_BASE+SAM3U_UDPHS_TST_OFFSET) +#define SAM3U_UDPHS_IPNAME1 (SAM3U_UDPHS_BASE+SAM3U_UDPHS_IPNAME1_OFFSET) +#define SAM3U_UDPHS_IPNAME2 (SAM3U_UDPHS_BASE+SAM3U_UDPHS_IPNAME2_OFFSET) +#define SAM3U_UDPHS_IPFEATURES (SAM3U_UDPHS_BASE+SAM3U_UDPHS_IPFEATURES_OFFSET) + +/* Endpoint registers */ + +#define SAM3U_UDPHSEP_BASE(n)) (SAM3U_UDPHS_BASE+SAM3U_UDPHSEP_OFFSET(n)) +#define SAM3U_UDPHSEP_CFG(n) (SAM3U_UDPHSEP_BASE(n)+SAM3U_UDPHSEP_CFG_OFFSET) +#define SAM3U_UDPHSEP_CTLENB(n) (SAM3U_UDPHSEP_BASE(n)+SAM3U_UDPHSEP_CTLENB_OFFSET) +#define SAM3U_UDPHSEP_CTLDIS(n) (SAM3U_UDPHSEP_BASE(n)+SAM3U_UDPHSEP_CTLDIS_OFFSET) +#define SAM3U_UDPHSEP_CTL(n) (SAM3U_UDPHSEP_BASE(n)+SAM3U_UDPHSEP_CTL_OFFSET) +#define SAM3U_UDPHSEP_SETSTA(n) (SAM3U_UDPHSEP_BASE(n)+SAM3U_UDPHSEP_SETSTA_OFFSET) +#define SAM3U_UDPHSEP_CLRSTA(n) (SAM3U_UDPHSEP_BASE(n)+SAM3U_UDPHSEP_CLRSTA_OFFSET) +#define SAM3U_UDPHSEP_STA(n) (SAM3U_UDPHSEP_BASE(n)+SAM3U_UDPHSEP_STA_OFFSET) + +/* DMA Channel Registers*/ + +#define SAM3U_UDPHSDMA_BASE(n) (SAM3U_UDPHS_BASE+SAM3U_UDPHSDMA_OFFSET(n)) +#define SAM3U_UDPHSDMA_NXTDSC(n) (SAM3U_UDPHSDMA_BASE(n)+SAM3U_UDPHSDMA_NXTDSC_OFFSET) +#define SAM3U_UDPHSDMA_ADDRESS(n) (SAM3U_UDPHSDMA_BASE(n)+SAM3U_UDPHSDMA_ADDRESS_OFFSET) +#define SAM3U_UDPHSDMA_CONTROL(n) (SAM3U_UDPHSDMA_BASE(n)+SAM3U_UDPHSDMA_CONTROL_OFFSET) +#define SAM3U_UDPHSDMA_STATUS(n) (SAM3U_UDPHSDMA_BASE(n)+SAM3U_UDPHSDMA_STATUS_OFFSET) + +/* UDPHS register bit definitions *******************************************************/ +/* UDPHS Control Register */ + +#define UDPHS_CTRL_DEVADDR_SHIFT (0) /* Bits 0-6: UDPHS Address */ +#define UDPHS_CTRL_DEVADDR_MASK (0x7f << UDPHS_CTRL_DEVADDR_SHIFT) +#define UDPHS_CTRL_FADDREN (1 << 7) /* Bit 7: Function Address Enable */ +#define UDPHS_CTRL_ENUDPHS (1 << 8) /* Bit 8: UDPHS Enable */ +#define UDPHS_CTRL_DETACH (1 << 9) /* Bit 9: Detach Command */ +#define UDPHS_CTRL_REWAKEUP (1 << 10) /* Bit 10: Send Remote Wake Up */ +#define UDPHS_CTRL_PULLDDIS (1 << 11) /* Bit 11: Pull-Down Disable */ + +/* UDPHS Frame Number Register */ + +#define UDPHS_FNUM_MICROFRAMENUM_SHIFT (0) /* Bits 0-2: Microframe Num */ +#define UDPHS_FNUM_MICROFRAMENUM_MASK (7 << UDPHS_FNUM_MICROFRAMENUM_SHIFT) +#define UDPHS_FNUM_FRAMENUMBER_SHIFT (3) /* Bits 3-7: Frame Number in Packet Field Formats */ +#define UDPHS_FNUM_FRAMENUMBER_MASK (31 << UDPHS_FNUM_FRAMENUMBER_SHIFT) +#define UDPHS_FNUM_FNUMERR_SHIFT (8) /* Bits 8-13: Frame Number CRC Error */ +#define UDPHS_FNUM_FNUMERR_MASK (63 << UDPHS_FNUM_FNUMERR_SHIFT) + +/* UDPHS Interrupt Enable Register, UDPHS Interrupt Status Register, and UDPHS Clear + * Interrupt Register common bit-field definitions + */ + +#define USBPHS_INT_DETSUSPD (1 << 1) /* Bit 1: Suspend Interrupt (Common) */ +#define USBPHS_INT_MICROSOF (1 << 2) /* Bit 2: Micro-SOF Interrupt (Common) */ +#define USBPHS_INT_INTSOF (1 << 3) /* Bit 3: SOF Interrupt (Common) */ +#define USBPHS_INT_ENDRESET (1 << 4) /* Bit 4: End Of Reset Interrupt (Common) */ +#define USBPHS_INT_WAKEUP (1 << 5) /* Bit 5: Wake Up CPU Interrupt (Common) */ +#define USBPHS_INT_ENDOFRSM (1 << 6) /* Bit 6: End Of Resume Interrupt (Common) */ +#define USBPHS_INT_UPSTRRES (1 << 7) /* Bit 7: Upstream Resume Interrupt (Common) */ +#define USBPHS_INT_EPT(n) (1 << ((n)+8)) +#define USBPHS_INT_EPT0 (1 << 8) /* Bit 8: Endpoint 0 Interrupt (not Clear) */ +#define USBPHS_INT_EPT1 (1 << 9) /* Bit 9: Endpoint 1 Interrupt (not Clear) */ +#define USBPHS_INT_EPT2 (1 << 10) /* Bit 10: Endpoint 2 Interrupt (not Clear) */ +#define USBPHS_INT_EPT3 (1 << 11) /* Bit 11: Endpoint 3 Interrupt (not Clear) */ +#define USBPHS_INT_EPT4 (1 << 12) /* Bit 12: Endpoint 4 Interrupt (not Clear) */ +#define USBPHS_INT_EPT5 (1 << 13) /* Bit 13: Endpoint 5 Interrupt (not Clear) */ +#define USBPHS_INT_EPT6 (1 << 13) /* Bit 14: Endpoint 6 Interrupt (not Clear) */ +#define USBPHS_INT_DMA(n) (1<<((n)+24)) +#define USBPHS_INT_DMA1 (1 << 25) /* Bit 25: DMA Channel 1 Interrupt (not Clear) */ +#define USBPHS_INT_DMA2 (1 << 26) /* Bit 26: DMA Channel 2 Interrupt (not Clear) */ +#define USBPHS_INT_DMA3 (1 << 27) /* Bit 27: DMA Channel 3 Interrupt (not Clear) */ +#define USBPHS_INT_DMA4 (1 << 28) /* Bit 28: DMA Channel 4 Interrupt (not Clear) */ +#define USBPHS_INT_DMA5 (1 << 29) /* Bit 29: DMA Channel 5 Interrupt (not Clear) */ +#define USBPHS_INT_DMA6 (1 << 30) /* Bit 30: DMA Channel 6 Interrupt (not Clear) */ + +/* UDPHS Endpoints Reset Register */ + +#define UDPHS_EPTRST_EPT(n) (1<<(n)) /* Bit 0-6: Endpoint n Reset */ + +/* UDPHS Test Register */ + +#define UDPHS_TST_SPEEDCFG_SHIFT (0) /* Bits 0-1: Speed Configuration */ +#define UDPHS_TST_SPEEDCFG_MASK (3 << UDPHS_TST_SPEEDCFG_SHIFT) +# define UDPHS_TST_SPEEDCFG_NORMAL (0 << UDPHS_TST_SPEEDCFG_SHIFT) /* Normal Mode */ +# define UDPHS_TST_SPEEDCFG_HIGH (2 << UDPHS_TST_SPEEDCFG_SHIFT) /* Force High Speed */ +# define UDPHS_TST_SPEEDCFG_FULL (3 << UDPHS_TST_SPEEDCFG_SHIFT) /* Force Full Speed */ +#define UDPHS_TST_TSTJ (1 << 2) /* Bit 2: Test J Mode */ +#define UDPHS_TST_TSTK (1 << 3) /* Bit 3: Test K Mode */ +#define UDPHS_TST_TSTPKT (1 << 4) /* Bit 4: Test Packet Mo */ +#define UDPHS_TST_OPMODE2 (1 << 5) /* Bit 5: OpMode2 */ + +/* UDPHS Features Register */ + +#define UDPHS_IPFEATURES_EPTNBRMAX_SHIFT (0) /* Bits 0-3: Max Number of Endpoints */ +#define UDPHS_IPFEATURES_EPTNBRMAX_MASK (15 << UDPHS_IPFEATURES_EPTNBRMAX_SHIFT) +#define UDPHS_IPFEATURES_DMACHANNELNBR_SHIFT (4) /* Bits 4-6: Number of DMA Channels */ +#define UDPHS_IPFEATURES_DMACHANNELNBR_MASK (7 << UDPHS_IPFEATURES_DMACHANNELNBR_SHIFT) +#define UDPHS_IPFEATURES_DMABSIZ (1 << 7) /* Bit 7: DMA Buffer Size */ +#define UDPHS_IPFEATURES_DMAFIFOWDDEPTH_SHIFT (8) /* Bits 8-11: DMA FIFO Depth in Words */ +#define UDPHS_IPFEATURES_DMAFIFOWDDEPTH_MASK (15 << UDPHS_IPFEATURES_DMAFIFOWDDEPTH_SHIFT) +# define UDPHS_IPFEATURES_DMAFIFOWDDEPTH(n) ((n)&15) +#define UDPHS_IPFEATURES_FIFOMAXSIZE_SHIFT (12) /* Bits 12-14: DPRAM Size */ +#define UDPHS_IPFEATURES_FIFOMAXSIZE_MASK (7 << UDPHS_IPFEATURES_FIFOMAXSIZE_SHIFT) +# define UDPHS_IPFEATURES_FIFOMAXSIZE_128b (0 << UDPHS_IPFEATURES_FIFOMAXSIZE_SHIFT) /* DPRAM 128 bytes */ +# define UDPHS_IPFEATURES_FIFOMAXSIZE_256b (1 << UDPHS_IPFEATURES_FIFOMAXSIZE_SHIFT) /* DPRAM 256 bytes */ +# define UDPHS_IPFEATURES_FIFOMAXSIZE_512b (2 << UDPHS_IPFEATURES_FIFOMAXSIZE_SHIFT) /* DPRAM 512 bytes */ +# define UDPHS_IPFEATURES_FIFOMAXSIZE_1Kb (3 << UDPHS_IPFEATURES_FIFOMAXSIZE_SHIFT) /* DPRAM 1024 bytes */ +# define UDPHS_IPFEATURES_FIFOMAXSIZE_2Kb (4 << UDPHS_IPFEATURES_FIFOMAXSIZE_SHIFT) /* DPRAM 2048 bytes */ +# define UDPHS_IPFEATURES_FIFOMAXSIZE_4Kb (5 << UDPHS_IPFEATURES_FIFOMAXSIZE_SHIFT) /* DPRAM 4096 bytes */ +# define UDPHS_IPFEATURES_FIFOMAXSIZE_8Kb (6 << UDPHS_IPFEATURES_FIFOMAXSIZE_SHIFT) /* DPRAM 8192 bytes */ +# define UDPHS_IPFEATURES_FIFOMAXSIZE_16Kb (7 << UDPHS_IPFEATURES_FIFOMAXSIZE_SHIFT) /* DPRAM 16384 bytes */ +#define UDPHS_IPFEATURES_BWDPRAM (1 << 15) /* Bit 15: DPRAM Byte Write Capability */ +#define UDPHS_IPFEATURES_DATAB168 (1 << 15) /* Bit 15: UTMI DataBus16_8 */ +#define UDPHS_IPFEATURES_ISOEPT(n) (1<<((n)+16) +#define UDPHS_IPFEATURES_ISOEPT1 (1 << 17) /* Bit 17: EP1 High B/W Isoc Capability */ +#define UDPHS_IPFEATURES_ISOEPT2 (1 << 18) /* Bit 18: EP2 High B/W Isoc Capability */ +#define UDPHS_IPFEATURES_ISOEPT3 (1 << 19) /* Bit 19: EP3 High B/W Isoc Capability */ +#define UDPHS_IPFEATURES_ISOEPT4 (1 << 20) /* Bit 20: EP4 High B/W Isoc Capability */ +#define UDPHS_IPFEATURES_ISOEPT5 (1 << 21) /* Bit 21: EP5 High B/W Isoc Capability */ +#define UDPHS_IPFEATURES_ISOEPT6 (1 << 22) /* Bit 22: EP6 High B/W Isoc Capability */ +#define UDPHS_IPFEATURES_ISOEPT7 (1 << 23) /* Bit 23: EP7 High B/W Isoc Capability */ +#define UDPHS_IPFEATURES_ISOEPT8 (1 << 24) /* Bit 24: EP8 High B/W Isoc Capability */ +#define UDPHS_IPFEATURES_ISOEPT9 (1 << 25) /* Bit 25: EP9 High B/W Isoc Capability */ +#define UDPHS_IPFEATURES_ISOEPT0 (1 << 26) /* Bit 26: EP10 High B/W Isoc Capability */ +#define UDPHS_IPFEATURES_ISOEPT1 (1 << 27) /* Bit 27: EP11 High B/W Isoc Capability */ +#define UDPHS_IPFEATURES_ISOEPT2 (1 << 28) /* Bit 28: EP12 High B/W Isoc Capability */ +#define UDPHS_IPFEATURES_ISOEPT3 (1 << 29) /* Bit 29: EP13 High B/W Isoc Capability */ +#define UDPHS_IPFEATURES_ISOEPT4 (1 << 30) /* Bit 30: EP14 High B/W Isoc Capability */ +#define UDPHS_IPFEATURES_ISOEPT5 (1 << 31) /* Bit 31: EP15 High B/W Isoc Capability */ + +/* UDPHS Endpoint Configuration Register (0-6) */ + +#define UDPHSEP_CFG_SIZE_SHIFT (0) /* Bits 0-2: Endpoint Size */ +#define UDPHSEP_CFG_SIZE_MASK (7 << UDPHSEP_CFG_SIZE_SHIFT) +# define UDPHSEP_CFG_SIZE_8b (0 << UDPHSEP_CFG_SIZE_SHIFT) /* 8 bytes */ +# define UDPHSEP_CFG_SIZE_16b (1 << UDPHSEP_CFG_SIZE_SHIFT) /* 16 bytes */ +# define UDPHSEP_CFG_SIZE_32b (2 << UDPHSEP_CFG_SIZE_SHIFT) /* 32 bytes */ +# define UDPHSEP_CFG_SIZE_16b (3 << UDPHSEP_CFG_SIZE_SHIFT) /* 64 bytes */ +# define UDPHSEP_CFG_SIZE_128b (4 << UDPHSEP_CFG_SIZE_SHIFT) /* 128 bytes */ +# define UDPHSEP_CFG_SIZE_256b (5 << UDPHSEP_CFG_SIZE_SHIFT) /* 256 bytes */ +# define UDPHSEP_CFG_SIZE_512b (6 << UDPHSEP_CFG_SIZE_SHIFT) /* 512 bytes */ +# define UDPHSEP_CFG_SIZE_1Kb (7 << UDPHSEP_CFG_SIZE_SHIFT) /* 1024 bytes */ +#define UDPHSEP_CFG_DIR (1 << 3) /* Bit 3: Endpoint Direction */ +#define UDPHSEP_CFG_TYPE_SHIFT (4) /* Bits 4-5: Endpoint Type */ +#define UDPHSEP_CFG_TYPE_MASK (3 << UDPHSEP_CFG_TYPE_SHIFT) +# define UDPHSEP_CFG_TYPE_CNTRL (0 << UDPHSEP_CFG_TYPE_SHIFT) /* Control endpoint */ +# define UDPHSEP_CFG_TYPE_ISOC (1 << UDPHSEP_CFG_TYPE_SHIFT) /* Isochronous endpoint */ +# define UDPHSEP_CFG_TYPE_BULK (2 << UDPHSEP_CFG_TYPE_SHIFT) /* Bulk endpoint */ +# define UDPHSEP_CFG_TYPE_INTR (3 << UDPHSEP_CFG_TYPE_SHIFT) /* Interrupt endpoint */ +#define UDPHSEP_CFG_BKNUMBER_SHIFT (6) /* Bits 6-7: Number of Banks */ +#define UDPHSEP_CFG_BKNUMBER_MASK (3 << UDPHSEP_CFG_BKNUMBER_SHIFT) +# define UDPHSEP_CFG_BKNUMBER_0BANK (0 << UDPHSEP_CFG_BKNUMBER_SHIFT) /* Zero bank (unmapped) */ +# define UDPHSEP_CFG_BKNUMBER_1BANK (1 << UDPHSEP_CFG_BKNUMBER_SHIFT) /* One bank (bank 0) */ +# define UDPHSEP_CFG_BKNUMBER_2BANK (2 << UDPHSEP_CFG_BKNUMBER_SHIFT) /* Double bank (bank 0-1) */ +# define UDPHSEP_CFG_BKNUMBER_3BANK (3 << UDPHSEP_CFG_BKNUMBER_SHIFT) /* Triple bank (bank 0-2) */ +#define UDPHSEP_CFG_NBTRANS_SHIFT (8) /* Bits 8-9: Number Of Transaction per Microframe */ +#define UDPHSEP_CFG_NBTRANS_MASK (3 << UDPHSEP_CFG_NBTRANS_SHIFT) +#define UDPHSEP_CFG_MAPD (1 << 31) /*Bit 31: Endpoint Mapped */ + +/* UDPHS Endpoint Control Enable Register, UDPHS Endpoint Control Disable Register, + * and UDPHS Endpoint Control Register common bit-field definitions + */ + +#define UDPHSEP_INT_EPT (1 << 0) /* Bit 0: Endpoint Enable/Disable */ +#define UDPHSEP_INT_AUTOVALID (1 << 1) /* Bit 1: Packet Auto-Valid */ +#define UDPHSEP_INT_INTDISDMA (1 << 3) /* Bit 3: Interrupts Disable DMA */ +#define UDPHSEP_INT_NYETDIS (1 << 4) /* Bit 4: NYET Disable (HS Bulk OUT EPs) */ +#define UDPHSEP_INT_DATAXRX (1 << 6) /* Bit 6: DATAx Interrupt Enable (High B/W Isoc OUT EPs) */ +#define UDPHSEP_INT_MDATARX (1 << 7) /* Bit 7: MDATA Interrupt Enable (High B/W Isoc OUT EPs) */ +#define UDPHSEP_INT_ERROVFLW (1 << 8) /* Bit 8: Overflow Error Interrupt */ +#define UDPHSEP_INT_RXBKRDY (1 << 9) /* Bit 9: Received OUT Data Interrupt */ +#define UDPHSEP_INT_TXCOMPLT (1 << 10) /* Bit 10: Transmitted IN Data Complete Interrupt */ +#define UDPHSEP_INT_TXPKRDY (1 << 11) /* Bit 11: TX Packet Ready Interrupt */ +#define UDPHSEP_INT_ERRTRANS (1 << 11) /* Bit 11: Transaction Error Interrupt */ +#define UDPHSEP_INT_RXSETUP (1 << 12) /* Bit 12: Received SETUP Interrupt */ +#define UDPHSEP_INT_ERRFLISO (1 << 12) /* Bit 12: Error Flow Interrupt */ +#define UDPHSEP_INT_STALLSNT (1 << 13) /* Bit 13: Stall Sent Interrupt */ +#define UDPHSEP_INT_ERRCRISO (1 << 13) /* Bit 13: ISO CRC Error Error Interrupt */ +#define UDPHSEP_INT_ERRNBTRA (1 << 13) /* Bit 13: Number of Transaction Error Interrupt */ +#define UDPHSEP_INT_NAKIN (1 << 14) /* Bit 14: NAKIN Interrupt */ +#define UDPHSEP_INT_ERRFLUSH (1 << 14) /* Bit 14: Bank Flush Error Interrupt */ +#define UDPHSEP_INT_NAKOUT (1 << 15) /* Bit 15: NAKOUT Interrupt */ +#define UDPHSEP_INT_BUSYBANK (1 << 18) /* Bit 18: Busy Bank Interrupt */ +#define UDPHSEP_INT_SHRTPCKT (1 << 31) /* Bit 31: Short Packet Send/Short Packet Interrupt */ + +/* UDPHS Endpoint Set Status Register */ + +#define UDPHSEP_SETSTA_FRCESTALL (1 << 5) /* Bit 5: Stall Handshake Request Set */ +#define UDPHSEP_SETSTA_KILLBANK (1 << 9) /* Bit 9: KILL Bank Set (for IN Endpoint) */ +#define UDPHSEP_SETSTA_TXPKRDY (1 << 11) /* Bit 11: TX Packet Ready Set */ + +/* UDPHS Endpoint Clear Status Register */ + +#define UDPHSEP_CLRSTA_FRCESTALL (1 << 5) /* Bit 5: Stall Handshake Request Clear */ +#define UDPHSEP_CLRSTA_TOGGLESQ (1 << 6) /* Bit 6: Data Toggle Clear */ +#define UDPHSEP_CLRSTA_RXBKRDY (1 << 9) /* Bit 9: Received OUT Data Clear */ +#define UDPHSEP_CLRSTA_TXCOMPLT (1 << 10) /* Bit 10: Transmitted IN Data Complete Clear */ +#define UDPHSEP_CLRSTA_RXSETUP (1 << 12) /* Bit 12: Received SETUP Clear */ +#define UDPHSEP_CLRSTA_ERRFLISO (1 << 12) /* Bit 12: Error Flow Clear */ +#define UDPHSEP_CLRSTA_STALL_NT (1 << 13) /* Bit 13: Stall Sent Clear */ +#define UDPHSEP_CLRSTA_ERRNBTRA (1 << 13) /* Bit 13: Number of Transaction Error Clear */ +#define UDPHSEP_CLRSTA_NAKIN (1 << 14) /* Bit 14: NAKIN Clear */ +#define UDPHSEP_CLRSTA_ERRFLUSH (1 << 14) /* Bit 14: Bank Flush Error Clear */ +#define UDPHSEP_CLRSTA_NAKOUT (1 << 15) /* Bit 15: NAKOUT Clear */ + +/* UDPHS Endpoint Status Register */ + +#define UDPHSEP_STA_FRCESTALL (1 << 5) /* Bit 5: Stall Handshake Request */ +#define UDPHSEP_STA_TOGGLESQSTA_SHIFT (6) /* Bits 6-7: Toggle Sequencing */ +#define UDPHSEP_STA_TOGGLESQSTA_MASK (3 << UDPHSEP_STA_TOGGLESQSTA_SHIFT) +# define UDPHSEP_STA_TOGGLESQSTA_DATA0 (0 << UDPHSEP_STA_TOGGLESQSTA_SHIFT) /* Data0 */ +# define UDPHSEP_STA_TOGGLESQSTA_DATA1 (1 << UDPHSEP_STA_TOGGLESQSTA_SHIFT) /* Data1 */ +# define UDPHSEP_STA_TOGGLESQSTA_DATA2 (2 << UDPHSEP_STA_TOGGLESQSTA_SHIFT) /* Data2 (High B/W Isoc EP) */ +# define UDPHSEP_STA_TOGGLESQSTA_MDATA (3 << UDPHSEP_STA_TOGGLESQSTA_SHIFT) /* MData (High B/W Isoc EP) */ +#define UDPHSEP_STA_ERROVFLW (1 << 8) /* Bit 8: Overflow Error */ +#define UDPHSEP_STA_RXBKRDY (1 << 9) /* Bit 9: Received OUT Data */ +#define UDPHSEP_STA_KILLBANK (1 << 9) /* Bit 9: KILL Bank */ +#define UDPHSEP_STA_TXCOMPLT (1 << 10) /* Bit 10: Transmitted IN Data Complete */ +#define UDPHSEP_STA_TXPKRDY (1 << 11) /* Bit 11: TX Packet Ready */ +#define UDPHSEP_STA_ERRTRANS (1 << 11) /* Bit 11: Transaction Error */ +#define UDPHSEP_STA_RXSETUP (1 << 12) /* Bit 12: Received SETUP */ +#define UDPHSEP_STA_ERRFLISO (1 << 12) /* Bit 12: Error Flow */ +#define UDPHSEP_STA_STALLSNT (1 << 13) /* Bit 13: Stall Sent */ +#define UDPHSEP_STA_ERRCRISO (1 << 13) /* Bit 13: CRC ISO Error */ +#define UDPHSEP_STA_ERRNBTRA (1 << 13) /* Bit 13: Number of Transaction Error */ +#define UDPHSEP_STA_NAKIN (1 << 14) /* Bit 14: NAK IN */ +#define UDPHSEP_STA_ERRFLUSH (1 << 14) /* Bit 14: Bank Flush Error */ +#define UDPHSEP_STA_NAKOUT (1 << 15) /* Bit 15: NAK OUT */ +#define UDPHSEP_STA_CURRENTBANK_SHIFT (16) /* Bits 16-17: Current Bank */ +#define UDPHSEP_STA_CURRENTBANK_MASK (3 << UDPHSEP_STA_CURRENTBANK_MASK) +#define UDPHSEP_STA_CONTROLDIR_SHIFT (16) /* Bits 16-17: Control Direction */ +#define UDPHSEP_STA_CONTROLDIR_MASK (3 << UDPHSEP_STA_CONTROLDIR_SHIFT) +#define UDPHSEP_STA_BUSYBANKSTA_SHIFT (18) /* Bits 18-19: Busy Bank Number */ +#define UDPHSEP_STA_BUSYBANKSTA_MASK (3 << UDPHSEP_STA_BUSYBANKSTA_SHIFT) +#define UDPHSEP_STA_BYTECOUNT_SHIFT (20) /* Bits 20-23: UDPHS Byte Count */ +#define UDPHSEP_STA_BYTECOUNT_MASK (15 << UDPHSEP_STA_BYTECOUNT_SHIFT) +#define UDPHSEP_STA_SHRTPCKT (1 << 31) /* Bit 31: Short Packet + +/* UDPHS DMA Channel Control Register */ + +#define UDPHSDMA_CONTROL_CHANNENB (1 << 0) /* Bit 0: Channel Enable Command */ +#define UDPHSDMA_CONTROL_LDNXTDSC (1 << 1) /* Bit 1: Load Next Channel Xfr Desc Enable (Command) */ +#define UDPHSDMA_CONTROL_ENDTREN (1 << 2) /* Bit 2: End of Transfer Enable (Control) */ +#define UDPHSDMA_CONTROL_ENDBEN (1 << 3) /* Bit 3: End of Buffer Enable (Control) */ +#define UDPHSDMA_CONTROL_ENDTRIT (1 << 4) /* Bit 4: End of Transfer Interrupt Enable */ +#define UDPHSDMA_CONTROL_ENDBUFFIT (1 << 5) /* Bit 5: End of Buffer Interrupt Enable */ +#define UDPHSDMA_CONTROL_DESCLDIT (1 << 6) /* Bit 6: Descriptor Loaded Interrupt Enab */ +#define UDPHSDMA_CONTROL_BURSTLCK (1 << 7) /* Bit 7: Burst Lock Ena */ +#define UDPHSDMA_CONTROL_BUFFLENGTH_SHIFT (16) /* Bits 16-31: Buffer Byte Length (Write-only) */ +#define UDPHSDMA_CONTROL_BUFFLENGTH_MASK (0xffff << UDPHSDMA_CONTROL_BUFFLENGTH_SHIFT) + +/* UDPHS DMA Channel Status Register */ + +#define UDPHSDMA_STATUS_CHANNENB (1 << 0) /* Bit 0: Channel Enable Status */ +#define UDPHSDMA_STATUS_CHANNACT (1 << 1) /* Bit 1: Channel Active Status */ +#define UDPHSDMA_STATUS_ENDTRST (1 << 4) /* Bit 4: End of Channel Transfer Status */ +#define UDPHSDMA_STATUS_ENDBFST (1 << 5) /* Bit 5: End of Channel Buffer Status */ +#define UDPHSDMA_STATUS_DESCLDST (1 << 6) /* Bit 6: Descriptor Loaded Status */ +#define UDPHSDMA_STATUS_BUFFCOUNT_SHIFT (16) /* Bits 16-31: Buffer Byte Count */ +#define UDPHSDMA_STATUS_BUFFCOUNT_MASK (0xffff << UDPHSDMA_STATUS_BUFFCOUNT_SHIFT) + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +/**************************************************************************************** + * Public Data + ****************************************************************************************/ + +/**************************************************************************************** + * Public Functions + ****************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_UDPHS_H */ + diff --git a/nuttx/arch/arm/src/sam3u/sam3u_userspace.c b/nuttx/arch/arm/src/sam3u/sam3u_userspace.c index a62eee792..e59cc5619 100644 --- a/nuttx/arch/arm/src/sam3u/sam3u_userspace.c +++ b/nuttx/arch/arm/src/sam3u/sam3u_userspace.c @@ -2,7 +2,7 @@ * arch/arm/src/common/sam3u_userspace.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/sam3u/sam3u_vectors.S b/nuttx/arch/arm/src/sam3u/sam3u_vectors.S index 7e7ad188e..3ed17f767 100644 --- a/nuttx/arch/arm/src/sam3u/sam3u_vectors.S +++ b/nuttx/arch/arm/src/sam3u/sam3u_vectors.S @@ -3,7 +3,7 @@ * arch/arm/src/chip/sam3u_vectors.S * * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/sam3u/sam3u_wdt.h b/nuttx/arch/arm/src/sam3u/sam3u_wdt.h index b885608d7..50b16d2a8 100644 --- a/nuttx/arch/arm/src/sam3u/sam3u_wdt.h +++ b/nuttx/arch/arm/src/sam3u/sam3u_wdt.h @@ -1,96 +1,96 @@ -/****************************************************************************************
- * arch/arm/src/sam3u/sam3u_wdt.h
- *
- * Copyright (C) 2009 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_WDT_H
-#define __ARCH_ARM_SRC_SAM3U_SAM3U_WDT_H
-
-/****************************************************************************************
- * Included Files
- ****************************************************************************************/
-
-#include <nuttx/config.h>
-
-#include "chip.h"
-#include "sam3u_memorymap.h"
-
-/****************************************************************************************
- * Pre-processor Definitions
- ****************************************************************************************/
-
-/* WDT register offsets ****************************************************************/
-
-#define SAM3U_WDT_CR_OFFSET 0x00 /* Control Register */
-#define SAM3U_WDT_MR_OFFSET 0x04 /* Mode Register */
-#define SAM3U_WDT_SR_OFFSET 0x08 /* Status Register */
-
-/* WDT register adresses ***************************************************************/
-
-#define SAM3U_WDT_CR (SAM3U_WDT_BASE+SAM3U_WDT_CR_OFFSET)
-#define SAM3U_WDT_MR (SAM3U_WDT_BASE+SAM3U_WDT_MR_OFFSET)
-#define SAM3U_WDT_SR (SAM3U_WDT_BASE+SAM3U_WDT_SR_OFFSET)
-
-/* WDT register bit definitions ********************************************************/
-
-#define WDT_CR_WDRSTT (1 << 0) /* Bit 0: Watchdog Rest */
-#define WDT_CR_KEY_SHIFT (24) /* Bits 24-31: Password */
-#define WDT_CR_KEY_MASK (0xff << WDT_CR_KEY_SHIFT)
-
-#define WDT_MR_WDV_SHIFT (0) /* Bits 0-11: Watchdog Counter Value */
-#define WDT_MR_WDV_MASK (0xfff << WDT_MR_WDV_SHIFT)
-#define WDT_MR_WDFIEN (1 << 12) /* Bit 12: Watchdog Fault Interrupt Enable */
-#define WDT_MR_WDRSTEN (1 << 13) /* Bit 13: Watchdog Reset Enable */
-#define WDT_MR_WDRPROC (1 << 14) /* Bit 14: Watchdog Reset Processor */
-#define WDT_MR_WDDIS (1 << 15) /* Bit 15: Watchdog Disable */
-#define WDT_MR_WDD_SHIFT (16) /* Bits 16-17: Watchdog Delta Value */
-#define WDT_MR_WDD_MASK (0xfff << WDT_MR_WDD_SHIFT)
-#define WDT_MR_WDDBGHLT (1 << 28) /* Bit 28: Watchdog Debug Halt */
-#define WDT_MR_WDIDLEHLT (1 << 29) /* Bit 29: Watchdog Idle Halt */
-
-#define WDT_SR_WDUNF (1 << 0) /* Bit 0: Watchdog Underflow */
-#define WDT_SR_WDERR (1 << 1) /* Bit 1: Watchdog Error */
-
-/****************************************************************************************
- * Public Types
- ****************************************************************************************/
-
-/****************************************************************************************
- * Public Data
- ****************************************************************************************/
-
-/****************************************************************************************
- * Public Functions
- ****************************************************************************************/
-
-#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_WDT_H */
+/**************************************************************************************** + * arch/arm/src/sam3u/sam3u_wdt.h + * + * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_WDT_H +#define __ARCH_ARM_SRC_SAM3U_SAM3U_WDT_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +#include <nuttx/config.h> + +#include "chip.h" +#include "sam3u_memorymap.h" + +/**************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************/ + +/* WDT register offsets ****************************************************************/ + +#define SAM3U_WDT_CR_OFFSET 0x00 /* Control Register */ +#define SAM3U_WDT_MR_OFFSET 0x04 /* Mode Register */ +#define SAM3U_WDT_SR_OFFSET 0x08 /* Status Register */ + +/* WDT register adresses ***************************************************************/ + +#define SAM3U_WDT_CR (SAM3U_WDT_BASE+SAM3U_WDT_CR_OFFSET) +#define SAM3U_WDT_MR (SAM3U_WDT_BASE+SAM3U_WDT_MR_OFFSET) +#define SAM3U_WDT_SR (SAM3U_WDT_BASE+SAM3U_WDT_SR_OFFSET) + +/* WDT register bit definitions ********************************************************/ + +#define WDT_CR_WDRSTT (1 << 0) /* Bit 0: Watchdog Rest */ +#define WDT_CR_KEY_SHIFT (24) /* Bits 24-31: Password */ +#define WDT_CR_KEY_MASK (0xff << WDT_CR_KEY_SHIFT) + +#define WDT_MR_WDV_SHIFT (0) /* Bits 0-11: Watchdog Counter Value */ +#define WDT_MR_WDV_MASK (0xfff << WDT_MR_WDV_SHIFT) +#define WDT_MR_WDFIEN (1 << 12) /* Bit 12: Watchdog Fault Interrupt Enable */ +#define WDT_MR_WDRSTEN (1 << 13) /* Bit 13: Watchdog Reset Enable */ +#define WDT_MR_WDRPROC (1 << 14) /* Bit 14: Watchdog Reset Processor */ +#define WDT_MR_WDDIS (1 << 15) /* Bit 15: Watchdog Disable */ +#define WDT_MR_WDD_SHIFT (16) /* Bits 16-17: Watchdog Delta Value */ +#define WDT_MR_WDD_MASK (0xfff << WDT_MR_WDD_SHIFT) +#define WDT_MR_WDDBGHLT (1 << 28) /* Bit 28: Watchdog Debug Halt */ +#define WDT_MR_WDIDLEHLT (1 << 29) /* Bit 29: Watchdog Idle Halt */ + +#define WDT_SR_WDUNF (1 << 0) /* Bit 0: Watchdog Underflow */ +#define WDT_SR_WDERR (1 << 1) /* Bit 1: Watchdog Error */ + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +/**************************************************************************************** + * Public Data + ****************************************************************************************/ + +/**************************************************************************************** + * Public Functions + ****************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_WDT_H */ diff --git a/nuttx/arch/arm/src/stm32/chip/stm32_bkp.h b/nuttx/arch/arm/src/stm32/chip/stm32_bkp.h index 1788bdee0..5bda839a8 100644 --- a/nuttx/arch/arm/src/stm32/chip/stm32_bkp.h +++ b/nuttx/arch/arm/src/stm32/chip/stm32_bkp.h @@ -2,7 +2,7 @@ * arch/arm/src/stm32/chip/stm32_bkp.h * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/stm32/chip/stm32_exti.h b/nuttx/arch/arm/src/stm32/chip/stm32_exti.h index 82477db54..5386a260f 100644 --- a/nuttx/arch/arm/src/stm32/chip/stm32_exti.h +++ b/nuttx/arch/arm/src/stm32/chip/stm32_exti.h @@ -2,7 +2,7 @@ * arch/arm/src/stm32/chip/stm32_exti.h * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/stm32/chip/stm32_memorymap.h b/nuttx/arch/arm/src/stm32/chip/stm32_memorymap.h index a53c7441c..36813b565 100644 --- a/nuttx/arch/arm/src/stm32/chip/stm32_memorymap.h +++ b/nuttx/arch/arm/src/stm32/chip/stm32_memorymap.h @@ -2,7 +2,7 @@ * arch/arm/src/stm32/chip/stm32_memorymap.h * * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/stm32/chip/stm32f100_pinmap.h b/nuttx/arch/arm/src/stm32/chip/stm32f100_pinmap.h index 18e8435f7..01d6e1ce0 100644 --- a/nuttx/arch/arm/src/stm32/chip/stm32f100_pinmap.h +++ b/nuttx/arch/arm/src/stm32/chip/stm32f100_pinmap.h @@ -4,7 +4,7 @@ * Copyright (C) 2009 Gregory Nutt. All rights reserved. * Copyright (C) 2011 Uros Platise. All rights reserved. * Copyright (C) 2012 Michael Smith. All Rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * Uros Platise <uros.platise@isotel.eu> * * Redistribution and use in source and binary forms, with or without diff --git a/nuttx/arch/arm/src/stm32/chip/stm32f103re_pinmap.h b/nuttx/arch/arm/src/stm32/chip/stm32f103re_pinmap.h index d0b5a6386..042f57f74 100644 --- a/nuttx/arch/arm/src/stm32/chip/stm32f103re_pinmap.h +++ b/nuttx/arch/arm/src/stm32/chip/stm32f103re_pinmap.h @@ -3,7 +3,7 @@ * * Copyright (C) 2009 Gregory Nutt. All rights reserved. * Copyright (C) 2011 Uros Platise. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * Uros Platise <uros.platise@isotel.eu> * * Redistribution and use in source and binary forms, with or without diff --git a/nuttx/arch/arm/src/stm32/chip/stm32f105vb_pinmap.h b/nuttx/arch/arm/src/stm32/chip/stm32f105vb_pinmap.h index fde8dd935..7a5ec3381 100644 --- a/nuttx/arch/arm/src/stm32/chip/stm32f105vb_pinmap.h +++ b/nuttx/arch/arm/src/stm32/chip/stm32f105vb_pinmap.h @@ -2,7 +2,7 @@ * arch/arm/src/stm32/chip/stm32f105vb_pinmap.h * * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/stm32/chip/stm32f107vc_pinmap.h b/nuttx/arch/arm/src/stm32/chip/stm32f107vc_pinmap.h index a7438a70e..9bbc21479 100644 --- a/nuttx/arch/arm/src/stm32/chip/stm32f107vc_pinmap.h +++ b/nuttx/arch/arm/src/stm32/chip/stm32f107vc_pinmap.h @@ -2,7 +2,7 @@ * arch/arm/src/stm32/chip/stm32f107vc_pinmap.h * * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_memorymap.h b/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_memorymap.h index 88eb1ad67..ed1bc2625 100644 --- a/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_memorymap.h +++ b/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_memorymap.h @@ -2,7 +2,7 @@ * arch/arm/src/stm32/chip/stm32f10xxx_memorymap.h * * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/stm32/chip/stm32f20xxx_pinmap.h b/nuttx/arch/arm/src/stm32/chip/stm32f20xxx_pinmap.h index c59cd565a..817e747f7 100644 --- a/nuttx/arch/arm/src/stm32/chip/stm32f20xxx_pinmap.h +++ b/nuttx/arch/arm/src/stm32/chip/stm32f20xxx_pinmap.h @@ -2,7 +2,7 @@ * arch/arm/src/stm32/chip/stm32f20xxx_pinmap.h * * Copyright (C) 2012 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/stm32/chip/stm32f40xxx_gpio.h b/nuttx/arch/arm/src/stm32/chip/stm32f40xxx_gpio.h index aa7353ed9..3a5f8bc6a 100644 --- a/nuttx/arch/arm/src/stm32/chip/stm32f40xxx_gpio.h +++ b/nuttx/arch/arm/src/stm32/chip/stm32f40xxx_gpio.h @@ -2,7 +2,7 @@ * arch/arm/src/stm32/chip/stm32f40xxx_gpio.h * * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/stm32/chip/stm32f40xxx_rtc.h b/nuttx/arch/arm/src/stm32/chip/stm32f40xxx_rtc.h index fdfa9b323..a656cfda0 100644 --- a/nuttx/arch/arm/src/stm32/chip/stm32f40xxx_rtc.h +++ b/nuttx/arch/arm/src/stm32/chip/stm32f40xxx_rtc.h @@ -2,7 +2,7 @@ * arch/arm/src/stm32/chip/stm32f40xxx_rtc.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/stm32/stm32_dbgmcu.h b/nuttx/arch/arm/src/stm32/stm32_dbgmcu.h index 080f4bec5..5fb192186 100644 --- a/nuttx/arch/arm/src/stm32/stm32_dbgmcu.h +++ b/nuttx/arch/arm/src/stm32/stm32_dbgmcu.h @@ -2,7 +2,7 @@ * arch/arm/src/stm32/stm32_dbgmcu.h * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/stm32/stm32_eth.h b/nuttx/arch/arm/src/stm32/stm32_eth.h index 188dc10d3..f0c14b5b1 100644 --- a/nuttx/arch/arm/src/stm32/stm32_eth.h +++ b/nuttx/arch/arm/src/stm32/stm32_eth.h @@ -2,7 +2,7 @@ * arch/arm/src/stm32/stm32_eth.h * * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/stm32/stm32_gpio.h b/nuttx/arch/arm/src/stm32/stm32_gpio.h index 34623c525..fde564cbb 100644 --- a/nuttx/arch/arm/src/stm32/stm32_gpio.h +++ b/nuttx/arch/arm/src/stm32/stm32_gpio.h @@ -3,7 +3,7 @@ * * Copyright (C) 2009, 2011-2012 Gregory Nutt. All rights reserved. * Copyright (C) 2011 Uros Platise. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * Uros Platise <uros.platise@isotel.eu> * * Redistribution and use in source and binary forms, with or without diff --git a/nuttx/arch/arm/src/stm32/stm32_i2c.h b/nuttx/arch/arm/src/stm32/stm32_i2c.h index 23a06bc05..b914c4247 100644 --- a/nuttx/arch/arm/src/stm32/stm32_i2c.h +++ b/nuttx/arch/arm/src/stm32/stm32_i2c.h @@ -2,7 +2,7 @@ * arch/arm/src/stm32/stm32_i2c.h * * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/stm32/stm32_lowputc.h b/nuttx/arch/arm/src/stm32/stm32_lowputc.h index edcc78d8f..659de7b1c 100644 --- a/nuttx/arch/arm/src/stm32/stm32_lowputc.h +++ b/nuttx/arch/arm/src/stm32/stm32_lowputc.h @@ -2,7 +2,7 @@ * arch/arm/src/stm32/stm32_lowputc.h * * Copyright (C) 2009-2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/stm32/stm32_pwr.h b/nuttx/arch/arm/src/stm32/stm32_pwr.h index 56aee49b6..7a2751677 100644 --- a/nuttx/arch/arm/src/stm32/stm32_pwr.h +++ b/nuttx/arch/arm/src/stm32/stm32_pwr.h @@ -2,7 +2,7 @@ * arch/arm/src/stm32/stm32_pwr.h * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/stm32/stm32_spi.h b/nuttx/arch/arm/src/stm32/stm32_spi.h index 268589bf3..6030ddfdd 100644 --- a/nuttx/arch/arm/src/stm32/stm32_spi.h +++ b/nuttx/arch/arm/src/stm32/stm32_spi.h @@ -2,7 +2,7 @@ * arch/arm/src/stm32/stm32_spi.h * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/stm32/stm32_timerisr.c b/nuttx/arch/arm/src/stm32/stm32_timerisr.c index 93cca02ac..ff6499415 100644 --- a/nuttx/arch/arm/src/stm32/stm32_timerisr.c +++ b/nuttx/arch/arm/src/stm32/stm32_timerisr.c @@ -2,7 +2,7 @@ * arch/arm/src/stm32/stm32_timerisr.c * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/stm32/stm32_usbdev.h b/nuttx/arch/arm/src/stm32/stm32_usbdev.h index a1af471b2..587107dc8 100644 --- a/nuttx/arch/arm/src/stm32/stm32_usbdev.h +++ b/nuttx/arch/arm/src/stm32/stm32_usbdev.h @@ -2,7 +2,7 @@ * arch/arm/src/stm32/stm32_usbdev.h * * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/stm32/stm32_wdg.h b/nuttx/arch/arm/src/stm32/stm32_wdg.h index 38af388f9..fbb8128b5 100644 --- a/nuttx/arch/arm/src/stm32/stm32_wdg.h +++ b/nuttx/arch/arm/src/stm32/stm32_wdg.h @@ -2,7 +2,7 @@ * arch/arm/src/stm32/stm32_wdg.h * * Copyright (C) 2012 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/str71x/Make.defs b/nuttx/arch/arm/src/str71x/Make.defs index 4ca4edff4..545ce1735 100644 --- a/nuttx/arch/arm/src/str71x/Make.defs +++ b/nuttx/arch/arm/src/str71x/Make.defs @@ -2,7 +2,7 @@ # arch/arm/src/str71x/Make.defs # # Copyright (C) 2008 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt <spudmonkey@racsa.co.cr> +# Author: Gregory Nutt <gnutt@nuttx.org> # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/str71x/chip.h b/nuttx/arch/arm/src/str71x/chip.h index 945141993..af1da9ea8 100644 --- a/nuttx/arch/arm/src/str71x/chip.h +++ b/nuttx/arch/arm/src/str71x/chip.h @@ -2,7 +2,7 @@ * arch/arm/src/str71x/chip.h * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/str71x/str71x_adc12.h b/nuttx/arch/arm/src/str71x/str71x_adc12.h index 1f15adfb7..1b982e0b1 100644 --- a/nuttx/arch/arm/src/str71x/str71x_adc12.h +++ b/nuttx/arch/arm/src/str71x/str71x_adc12.h @@ -1,109 +1,109 @@ -/************************************************************************************
- * arch/arm/src/str71x/str71x_adc12.h
- *
- * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_STR71X_STR71X_ADC12_H
-#define __ARCH_ARM_SRC_STR71X_STR71X_ADC12_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-
-#include "str71x_map.h"
-
-/************************************************************************************
- * Pre-procesor Definitions
- ************************************************************************************/
-
-/* ADC12 registers ******************************************************************/
-
-#define STR71X_ADC12_DATA0 (STR71X_ADC12_BASE + 0x0000) /* 16-bits wide */
-#define STR71X_ADC12_DATA1 (STR71X_ADC12_BASE + 0x0008) /* 16-bits wide */
-#define STR71X_ADC12_DATA2 (STR71X_ADC12_BASE + 0x0010) /* 16-bits wide */
-#define STR71X_ADC12_DATA3 (STR71X_ADC12_BASE + 0x0018) /* 16-bits wide */
-#define STR71X_ADC12_CSR (STR71X_ADC12_BASE + 0x0020) /* 16-bits wide */
-#define STR71X_ADC12_CPR (STR71X_ADC12_BASE + 0x0030) /* 16-bits wide */
-
-/* Register bit settings ************************************************************/
-/* ADC12 Conversion modes */
-
-#define STR71X_ADC12_SINGLE (0)
-#define STR71X_ADC12_ROUND (1)
-
-/* ADC12 Channels */
-
-#define STR71X_ADC12_CHANNEL0 (0x00)
-#define STR71X_ADC12_CHANNEL1 (0x10)
-#define STR71X_ADC12_CHANNEL2 (0x20)
-#define STR71X_ADC12_CHANNEL3 (0x30)
-
-/* ADC12 control status register */
-
-#define STR71X_ADC12_DA0 (0x0001)
-#define STR71X_ADC12_DA1 (0x0002)
-#define STR71X_ADC12_DA2 (0x0004)
-#define STR71X_ADC12_DA3 (0x0008)
-#define STR71X_ADC12_OR (0x2000)
-
-/* Interrupt bits for channel n */
-
-#define STR71X_ADC12_IT0 (0x0100)
-#define STR71X_ADC12_IT1 (0x0200)
-#define STR71X_ADC12_IT2 (0x0400)
-#define STR71X_ADC12_IT3 (0x0800)
-#define STR71X_ADC12_ITALL (0x0f00)
-
-/* Mode selection */
-
-#define STR71X_ADC12_MODE (0x0040)
-
-/* Converter configuration */
-
-#define STR71X_ADC12_START (0x0020)
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-/************************************************************************************
- * Public Functions
- ************************************************************************************/
-
-#endif /* __ARCH_ARM_SRC_STR71X_STR71X_ADC12_H */
+/************************************************************************************ + * arch/arm/src/str71x/str71x_adc12.h + * + * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STR71X_STR71X_ADC12_H +#define __ARCH_ARM_SRC_STR71X_STR71X_ADC12_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +#include "str71x_map.h" + +/************************************************************************************ + * Pre-procesor Definitions + ************************************************************************************/ + +/* ADC12 registers ******************************************************************/ + +#define STR71X_ADC12_DATA0 (STR71X_ADC12_BASE + 0x0000) /* 16-bits wide */ +#define STR71X_ADC12_DATA1 (STR71X_ADC12_BASE + 0x0008) /* 16-bits wide */ +#define STR71X_ADC12_DATA2 (STR71X_ADC12_BASE + 0x0010) /* 16-bits wide */ +#define STR71X_ADC12_DATA3 (STR71X_ADC12_BASE + 0x0018) /* 16-bits wide */ +#define STR71X_ADC12_CSR (STR71X_ADC12_BASE + 0x0020) /* 16-bits wide */ +#define STR71X_ADC12_CPR (STR71X_ADC12_BASE + 0x0030) /* 16-bits wide */ + +/* Register bit settings ************************************************************/ +/* ADC12 Conversion modes */ + +#define STR71X_ADC12_SINGLE (0) +#define STR71X_ADC12_ROUND (1) + +/* ADC12 Channels */ + +#define STR71X_ADC12_CHANNEL0 (0x00) +#define STR71X_ADC12_CHANNEL1 (0x10) +#define STR71X_ADC12_CHANNEL2 (0x20) +#define STR71X_ADC12_CHANNEL3 (0x30) + +/* ADC12 control status register */ + +#define STR71X_ADC12_DA0 (0x0001) +#define STR71X_ADC12_DA1 (0x0002) +#define STR71X_ADC12_DA2 (0x0004) +#define STR71X_ADC12_DA3 (0x0008) +#define STR71X_ADC12_OR (0x2000) + +/* Interrupt bits for channel n */ + +#define STR71X_ADC12_IT0 (0x0100) +#define STR71X_ADC12_IT1 (0x0200) +#define STR71X_ADC12_IT2 (0x0400) +#define STR71X_ADC12_IT3 (0x0800) +#define STR71X_ADC12_ITALL (0x0f00) + +/* Mode selection */ + +#define STR71X_ADC12_MODE (0x0040) + +/* Converter configuration */ + +#define STR71X_ADC12_START (0x0020) + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_STR71X_STR71X_ADC12_H */ diff --git a/nuttx/arch/arm/src/str71x/str71x_apb.h b/nuttx/arch/arm/src/str71x/str71x_apb.h index 4b8efe2a9..5ceee8ec9 100644 --- a/nuttx/arch/arm/src/str71x/str71x_apb.h +++ b/nuttx/arch/arm/src/str71x/str71x_apb.h @@ -1,109 +1,109 @@ -/************************************************************************************
- * arch/arm/src/str71x/str71x_apb.h
- *
- * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_STR71X_STR71X_APB_H
-#define __ARCH_ARM_SRC_STR71X_STR71X_APB_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-
-#include "str71x_map.h"
-
-/************************************************************************************
- * Pre-procesor Definitions
- ************************************************************************************/
-
-/* APB register offsets *************************************************************/
-
-#define STR71X_APB_CKDIS_OFFSET (0x0010) /* 32-bits wide */
-#define STR71X_APB_SWRES_OFFSET (0x0014) /* 32-bits wide */
-
-/* APB register addresses ***********************************************************/
-
-#define STR71X_APB1_CKDIS (STR71X_APB1_BASE + STR71X_APB_CKDIS_OFFSET)
-#define STR71X_APB1_SWRES (STR71X_APB1_BASE + STR71X_APB_SWRES_OFFSET)
-
-#define STR71X_APB2_CKDIS (STR71X_APB2_BASE + STR71X_APB_CKDIS_OFFSET)
-#define STR71X_APB2_SWRES (STR71X_APB2_BASE + STR71X_APB_SWRES_OFFSET)
-
-/* Register bit settings ***********************************************************/
-
-/* APB1 periperals */
-
-#define STR71X_APB1_I2C0 (0x0001) /* Bit 0: I2C0 */
-#define STR71X_APB1_I2C1 (0x0002) /* Bit 1: I2C1 */
-#define STR71X_APB1_UART0 (0x0008) /* Bit 3: UART0 */
-#define STR71X_APB1_UART1 (0x0010) /* Bit 4: UART1 */
-#define STR71X_APB1_UART2 (0x0020) /* Bit 5: UART2 */
-#define STR71X_APB1_UART3 (0x0040) /* Bit 6: UART3 */
-#define STR71X_APB1_USB (0x0080) /* Bit 7: USB */
-#define STR71X_APB1_CAN (0x0100) /* Bit 8: CAN */
-#define STR71X_APB1_BSPI0 (0x0200) /* Bit 9: BSPI0 */
-#define STR71X_APB1_BSPI1 (0x0400) /* Bit 10: BSPI1 */
-#define STR71X_APB1_HDLC (0x2000) /* Bit 13: HDLC */
-#define STR71X_APB1_APB1ALL (0x27fb)
-
-/* APB2 Peripherals */
-
-#define STR71X_APB2_XTI (0x0001) /* Bit 0: XTI */
-#define STR71X_APB2_GPIO0 (0x0004) /* Bit 2: IOPORT0 */
-#define STR71X_APB2_GPIO1 (0x0008) /* Bit 3: IOPORT1 */
-#define STR71X_APB2_GPIO2 (0x0010) /* Bit 4: IOPORT2 */
-#define STR71X_APB2_ADC12 (0x0040) /* Bit 6: ADC */
-#define STR71X_APB2_CKOUT (0x0080) /* Bit 7: CKOUT */
-#define STR71X_APB2_TIM0 (0x0100) /* Bit 8: TIMER0 */
-#define STR71X_APB2_TIM1 (0x0200) /* Bit 9: TIMER1 */
-#define STR71X_APB2_TIM2 (0x0400) /* Bit 10: TIMER2 */
-#define STR71X_APB2_TIM3 (0x0800) /* Bit 11: TIMER3 */
-#define STR71X_APB2_RTC (0x1000) /* Bit 12: RTC */
-#define STR71X_APB2_EIC (0x4000) /* Bit 14: EIC */
-#define STR71X_APB2_APB2ALL (0x5fdd)
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-/************************************************************************************
- * Public Functions
- ************************************************************************************/
-
-#endif /* __ARCH_ARM_SRC_STR71X_STR71X_APB_H */
+/************************************************************************************ + * arch/arm/src/str71x/str71x_apb.h + * + * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STR71X_STR71X_APB_H +#define __ARCH_ARM_SRC_STR71X_STR71X_APB_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +#include "str71x_map.h" + +/************************************************************************************ + * Pre-procesor Definitions + ************************************************************************************/ + +/* APB register offsets *************************************************************/ + +#define STR71X_APB_CKDIS_OFFSET (0x0010) /* 32-bits wide */ +#define STR71X_APB_SWRES_OFFSET (0x0014) /* 32-bits wide */ + +/* APB register addresses ***********************************************************/ + +#define STR71X_APB1_CKDIS (STR71X_APB1_BASE + STR71X_APB_CKDIS_OFFSET) +#define STR71X_APB1_SWRES (STR71X_APB1_BASE + STR71X_APB_SWRES_OFFSET) + +#define STR71X_APB2_CKDIS (STR71X_APB2_BASE + STR71X_APB_CKDIS_OFFSET) +#define STR71X_APB2_SWRES (STR71X_APB2_BASE + STR71X_APB_SWRES_OFFSET) + +/* Register bit settings ***********************************************************/ + +/* APB1 periperals */ + +#define STR71X_APB1_I2C0 (0x0001) /* Bit 0: I2C0 */ +#define STR71X_APB1_I2C1 (0x0002) /* Bit 1: I2C1 */ +#define STR71X_APB1_UART0 (0x0008) /* Bit 3: UART0 */ +#define STR71X_APB1_UART1 (0x0010) /* Bit 4: UART1 */ +#define STR71X_APB1_UART2 (0x0020) /* Bit 5: UART2 */ +#define STR71X_APB1_UART3 (0x0040) /* Bit 6: UART3 */ +#define STR71X_APB1_USB (0x0080) /* Bit 7: USB */ +#define STR71X_APB1_CAN (0x0100) /* Bit 8: CAN */ +#define STR71X_APB1_BSPI0 (0x0200) /* Bit 9: BSPI0 */ +#define STR71X_APB1_BSPI1 (0x0400) /* Bit 10: BSPI1 */ +#define STR71X_APB1_HDLC (0x2000) /* Bit 13: HDLC */ +#define STR71X_APB1_APB1ALL (0x27fb) + +/* APB2 Peripherals */ + +#define STR71X_APB2_XTI (0x0001) /* Bit 0: XTI */ +#define STR71X_APB2_GPIO0 (0x0004) /* Bit 2: IOPORT0 */ +#define STR71X_APB2_GPIO1 (0x0008) /* Bit 3: IOPORT1 */ +#define STR71X_APB2_GPIO2 (0x0010) /* Bit 4: IOPORT2 */ +#define STR71X_APB2_ADC12 (0x0040) /* Bit 6: ADC */ +#define STR71X_APB2_CKOUT (0x0080) /* Bit 7: CKOUT */ +#define STR71X_APB2_TIM0 (0x0100) /* Bit 8: TIMER0 */ +#define STR71X_APB2_TIM1 (0x0200) /* Bit 9: TIMER1 */ +#define STR71X_APB2_TIM2 (0x0400) /* Bit 10: TIMER2 */ +#define STR71X_APB2_TIM3 (0x0800) /* Bit 11: TIMER3 */ +#define STR71X_APB2_RTC (0x1000) /* Bit 12: RTC */ +#define STR71X_APB2_EIC (0x4000) /* Bit 14: EIC */ +#define STR71X_APB2_APB2ALL (0x5fdd) + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_STR71X_STR71X_APB_H */ diff --git a/nuttx/arch/arm/src/str71x/str71x_bspi.h b/nuttx/arch/arm/src/str71x/str71x_bspi.h index 537563c3d..f876ebb2b 100644 --- a/nuttx/arch/arm/src/str71x/str71x_bspi.h +++ b/nuttx/arch/arm/src/str71x/str71x_bspi.h @@ -1,153 +1,153 @@ -/************************************************************************************
- * arch/arm/src/str71x/str71x_bspi.h
- *
- * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_STR71X_STR71X_BSPI_H
-#define __ARCH_ARM_SRC_STR71X_STR71X_BSPI_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-
-#include "str71x_map.h"
-
-/************************************************************************************
- * Pre-procesor Definitions
- ************************************************************************************/
-
-/* Register Offsets *****************************************************************/
-
-#define STR71X_BSPI_RXR_OFFSET (0x0000) /* 16-bits wide */
-#define STR71X_BSPI_TXR_OFFSET (0x0004) /* 16-bits wide */
-#define STR71X_BSPI_CSR1_OFFSET (0x0008) /* 16-bits wide */
-#define STR71X_BSPI_CSR2_OFFSET (0x000c) /* 16-bits wide */
-#define STR71X_BSPI_CLK_OFFSET (0x0010) /* 16-bits wide */
-
-/* Registers ************************************************************************/
-
-#define STR71X_BSPI_RXR(b) ((b) + STR71X_BSPI_RXR_OFFSET)
-#define STR71X_BSPI_TXR(b) ((b) + STR71X_BSPI_TXR_OFFSET)
-#define STR71X_BSPI_CSR1(b) ((b) + STR71X_BSPI_CSR1_OFFSET)
-#define STR71X_BSPI_CSR2(b) ((b) + STR71X_BSPI_CSR2_OFFSET)
-#define STR71X_BSPI_CLK(b) ((b) + STR71X_BSPI_CLK_OFFSET)
-
-#define STR71X_BSPI0_RXR (STR71X_BSPI0_BASE + STR71X_BSPI_RXR_OFFSET)
-#define STR71X_BSPI0_TXR (STR71X_BSPI0_BASE + STR71X_BSPI_TXR_OFFSET)
-#define STR71X_BSPI0_CSR1 (STR71X_BSPI0_BASE + STR71X_BSPI_CSR1_OFFSET)
-#define STR71X_BSPI0_CSR2 (STR71X_BSPI0_BASE + STR71X_BSPI_CSR2_OFFSET)
-#define STR71X_BSPI0_CLK (STR71X_BSPI0_BASE + STR71X_BSPI_CLK_OFFSET)
-
-#define STR71X_BSPI1_RXR (STR71X_BSPI1_BASE + STR71X_BSPI_RXR_OFFSET)
-#define STR71X_BSPI1_TXR (STR71X_BSPI1_BASE + STR71X_BSPI_TXR_OFFSET)
-#define STR71X_BSPI1_CSR1 (STR71X_BSPI1_BASE + STR71X_BSPI_CSR1_OFFSET)
-#define STR71X_BSPI1_CSR2 (STR71X_BSPI1_BASE + STR71X_BSPI_CSR2_OFFSET)
-#define STR71X_BSPI1_CLK (STR71X_BSPI1_BASE + STR71X_BSPI_CLK_OFFSET)
-
-/* Register bit settings ***********************************************************/
-
-/* BSPI control/status register 1 */
-
-#define STR71X_BSPICSR1_BSPE (1 << 0) /* Bit 0: BSPI enable */
-#define STR71X_BSPICSR1_MSTR (1 << 1) /* Bit 1: Master/Slave select */
-#define STR71X_BSPICSR1_RIESHIFT 2 /* Bit 2-3: BSPI receive interrupt enable */
-#define STR71X_BSPICSR1_RIEMASK (3 << STR71X_BSPICSR1_RIESHIFT)
-#define STR71X_BSPICSR1_RIEDISABLED (0 << STR71X_BSPICSR1_RIESHIFT) /* Disabled */
-#define STR71X_BSPICSR1_RIERFNE (1 << STR71X_BSPICSR1_RIESHIFT) /* Receive FIFO not empty */
-#define STR71X_BSPICSR1_RIERFF (3 << STR71X_BSPICSR1_RIESHIFT) /* Receive FIFO full */
-#define STR71X_BSPICSR1_REIE (1 << 4) /* Bit 4: Receive error interrupt enable */
-#define STR71X_BSPICSR1_BEIE (1 << 7) /* Bit 7: Bus error interrupt enable */
-#define STR71X_BSPICSR1_CPOL (1 << 8) /* Bit 8: Clock polarity select */
-#define STR71X_BSPICSR1_CPHA (1 << 9) /* Bit 9: Clock phase select */
-#define STR71X_BSPICSR1_WLSHIFT 10 /* Bits 10-11: Word length */
-#define STR71X_BSPICSR1_WLMASK (3 << STR71X_BSPICSR1_WLSHIFT)
-#define STR71X_BSPICSR1_WL8BIT (0 << STR71X_BSPICSR1_WLSHIFT) /* 8-bits */
-#define STR71X_BSPICSR1_WL16BIT (1 << STR71X_BSPICSR1_WLSHIFT) /* 16-bits */
-#define STR71X_BSPICSR1_RFESHIFT 12 /* Bits 12-15: Receive FIFO enable */
-#define STR71X_BSPICSR1_RFEMASK (15 << STR71X_BSPICSR1_RFESHIFT)
-#define STR71X_BSPICSR1_RFE1 (0 << STR71X_BSPICSR1_RFESHIFT) /* Word 1 enabled */
-#define STR71X_BSPICSR1_RFE12 (1 << STR71X_BSPICSR1_RFESHIFT) /* Word 1-2 enabled */
-#define STR71X_BSPICSR1_RFE13 (2 << STR71X_BSPICSR1_RFESHIFT) /* Word 1-3 enabled */
-#define STR71X_BSPICSR1_RFE14 (3 << STR71X_BSPICSR1_RFESHIFT) /* Word 1-4 enabled */
-#define STR71X_BSPICSR1_RFE15 (4 << STR71X_BSPICSR1_RFESHIFT) /* Word 1-5 enabled */
-#define STR71X_BSPICSR1_RFE16 (5 << STR71X_BSPICSR1_RFESHIFT) /* Word 1-6 enabled */
-#define STR71X_BSPICSR1_RFE17 (6 << STR71X_BSPICSR1_RFESHIFT) /* Word 1-7 enabled */
-#define STR71X_BSPICSR1_RFE18 (7 << STR71X_BSPICSR1_RFESHIFT) /* Word 1-8 enabled */
-#define STR71X_BSPICSR1_RFE19 (8 << STR71X_BSPICSR1_RFESHIFT) /* Word 1-9 enabled */
-#define STR71X_BSPICSR1_RFE110 (9 << STR71X_BSPICSR1_RFESHIFT) /* Word 1-10 enabled */
-
-/* BSPI control/status register 2 */
-
-#define STR71X_BSPICSR2_DFIFO (1 << 0) /* Bit 0: FIFO disable */
-#define STR71X_BSPICSR2_BERR (1 << 2) /* Bit 2: Bus error */
-#define STR71X_BSPICSR2_RFNE (1 << 3) /* Bit 3: Receiver FIFO not empty */
-#define STR71X_BSPICSR2_RFF (1 << 4) /* Bit 4: Receiver FIFO full */
-#define STR71X_BSPICSR2_ROFL (1 << 5) /* Bit 5: Receiver overflow */
-#define STR71X_BSPICSR2_TFE (1 << 6) /* Bit 6: Transmit FIFO empty */
-#define STR71X_BSPICSR2_TUFL (1 << 7) /* Bit 7: Transmit FIFO underflow */
-#define STR71X_BSPICSR2_TFF (1 << 8) /* Bit 8: Transmit FIFO full */
-#define STR71X_BSPICSR2_TFNE (1 << 9) /* Bit 9: Transmit FIFO not empty */
-#define STR71X_BSPICSR2_TFESHIFT 10 /* Bits 10-13: Transmit FIFO enable*/
-#define STR71X_BSPICSR2_TFEMASK (15 << STR71X_BSPICSR2_TFESHIFT)
-#define STR71X_BSPICSR2_TFE1 (0 << STR71X_BSPICSR2_TFESHIFT) /* Word 1 enabled */
-#define STR71X_BSPICSR2_TFE12 (1 << STR71X_BSPICSR2_TFESHIFT) /* Word 1-2 enabled */
-#define STR71X_BSPICSR2_TFE13 (2 << STR71X_BSPICSR2_TFESHIFT) /* Word 1-3 enabled */
-#define STR71X_BSPICSR2_TFE14 (3 << STR71X_BSPICSR2_TFESHIFT) /* Word 1-4 enabled */
-#define STR71X_BSPICSR2_TFE15 (4 << STR71X_BSPICSR2_TFESHIFT) /* Word 1-5 enabled */
-#define STR71X_BSPICSR2_TFE16 (5 << STR71X_BSPICSR2_TFESHIFT) /* Word 1-6 enabled */
-#define STR71X_BSPICSR2_TFE17 (6 << STR71X_BSPICSR2_TFESHIFT) /* Word 1-7 enabled */
-#define STR71X_BSPICSR2_TFE18 (7 << STR71X_BSPICSR2_TFESHIFT) /* Word 1-8 enabled */
-#define STR71X_BSPICSR2_TFE19 (8 << STR71X_BSPICSR2_TFESHIFT) /* Word 1-9 enabled */
-#define STR71X_BSPICSR2_TFE110 (9 << STR71X_BSPICSR2_TFESHIFT) /* Word 1-10 enabled */
-#define STR71X_BSPICSR2_TIESHIFT 14 /* Bit 14-15: BSPI transmit interrupt enable */
-#define STR71X_BSPICSR2_TIEMASK (3 << STR71X_BSPICSR2_TIESHIFT)
-#define STR71X_BSPICSR2_TIEDISABLED (0 << STR71X_BSPICSR2_TIESHIFT) /* Disabled */
-#define STR71X_BSPICSR2_TIETFE (1 << STR71X_BSPICSR2_TIESHIFT) /* Interrupt on transmit FIFO empty */
-#define STR71X_BSPICSR2_TIETUFL (2 << STR71X_BSPICSR2_TIESHIFT) /* Interrupt on transmit underlow */
-#define STR71X_BSPICSR2_TIETFF (3 << STR71X_BSPICSR2_TIESHIFT) /* Interrupt on transmit FIFO full */
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-/************************************************************************************
- * Public Functions
- ************************************************************************************/
-
-#endif /* __ARCH_ARM_SRC_STR71X_STR71X_BSPI_H */
+/************************************************************************************ + * arch/arm/src/str71x/str71x_bspi.h + * + * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STR71X_STR71X_BSPI_H +#define __ARCH_ARM_SRC_STR71X_STR71X_BSPI_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +#include "str71x_map.h" + +/************************************************************************************ + * Pre-procesor Definitions + ************************************************************************************/ + +/* Register Offsets *****************************************************************/ + +#define STR71X_BSPI_RXR_OFFSET (0x0000) /* 16-bits wide */ +#define STR71X_BSPI_TXR_OFFSET (0x0004) /* 16-bits wide */ +#define STR71X_BSPI_CSR1_OFFSET (0x0008) /* 16-bits wide */ +#define STR71X_BSPI_CSR2_OFFSET (0x000c) /* 16-bits wide */ +#define STR71X_BSPI_CLK_OFFSET (0x0010) /* 16-bits wide */ + +/* Registers ************************************************************************/ + +#define STR71X_BSPI_RXR(b) ((b) + STR71X_BSPI_RXR_OFFSET) +#define STR71X_BSPI_TXR(b) ((b) + STR71X_BSPI_TXR_OFFSET) +#define STR71X_BSPI_CSR1(b) ((b) + STR71X_BSPI_CSR1_OFFSET) +#define STR71X_BSPI_CSR2(b) ((b) + STR71X_BSPI_CSR2_OFFSET) +#define STR71X_BSPI_CLK(b) ((b) + STR71X_BSPI_CLK_OFFSET) + +#define STR71X_BSPI0_RXR (STR71X_BSPI0_BASE + STR71X_BSPI_RXR_OFFSET) +#define STR71X_BSPI0_TXR (STR71X_BSPI0_BASE + STR71X_BSPI_TXR_OFFSET) +#define STR71X_BSPI0_CSR1 (STR71X_BSPI0_BASE + STR71X_BSPI_CSR1_OFFSET) +#define STR71X_BSPI0_CSR2 (STR71X_BSPI0_BASE + STR71X_BSPI_CSR2_OFFSET) +#define STR71X_BSPI0_CLK (STR71X_BSPI0_BASE + STR71X_BSPI_CLK_OFFSET) + +#define STR71X_BSPI1_RXR (STR71X_BSPI1_BASE + STR71X_BSPI_RXR_OFFSET) +#define STR71X_BSPI1_TXR (STR71X_BSPI1_BASE + STR71X_BSPI_TXR_OFFSET) +#define STR71X_BSPI1_CSR1 (STR71X_BSPI1_BASE + STR71X_BSPI_CSR1_OFFSET) +#define STR71X_BSPI1_CSR2 (STR71X_BSPI1_BASE + STR71X_BSPI_CSR2_OFFSET) +#define STR71X_BSPI1_CLK (STR71X_BSPI1_BASE + STR71X_BSPI_CLK_OFFSET) + +/* Register bit settings ***********************************************************/ + +/* BSPI control/status register 1 */ + +#define STR71X_BSPICSR1_BSPE (1 << 0) /* Bit 0: BSPI enable */ +#define STR71X_BSPICSR1_MSTR (1 << 1) /* Bit 1: Master/Slave select */ +#define STR71X_BSPICSR1_RIESHIFT 2 /* Bit 2-3: BSPI receive interrupt enable */ +#define STR71X_BSPICSR1_RIEMASK (3 << STR71X_BSPICSR1_RIESHIFT) +#define STR71X_BSPICSR1_RIEDISABLED (0 << STR71X_BSPICSR1_RIESHIFT) /* Disabled */ +#define STR71X_BSPICSR1_RIERFNE (1 << STR71X_BSPICSR1_RIESHIFT) /* Receive FIFO not empty */ +#define STR71X_BSPICSR1_RIERFF (3 << STR71X_BSPICSR1_RIESHIFT) /* Receive FIFO full */ +#define STR71X_BSPICSR1_REIE (1 << 4) /* Bit 4: Receive error interrupt enable */ +#define STR71X_BSPICSR1_BEIE (1 << 7) /* Bit 7: Bus error interrupt enable */ +#define STR71X_BSPICSR1_CPOL (1 << 8) /* Bit 8: Clock polarity select */ +#define STR71X_BSPICSR1_CPHA (1 << 9) /* Bit 9: Clock phase select */ +#define STR71X_BSPICSR1_WLSHIFT 10 /* Bits 10-11: Word length */ +#define STR71X_BSPICSR1_WLMASK (3 << STR71X_BSPICSR1_WLSHIFT) +#define STR71X_BSPICSR1_WL8BIT (0 << STR71X_BSPICSR1_WLSHIFT) /* 8-bits */ +#define STR71X_BSPICSR1_WL16BIT (1 << STR71X_BSPICSR1_WLSHIFT) /* 16-bits */ +#define STR71X_BSPICSR1_RFESHIFT 12 /* Bits 12-15: Receive FIFO enable */ +#define STR71X_BSPICSR1_RFEMASK (15 << STR71X_BSPICSR1_RFESHIFT) +#define STR71X_BSPICSR1_RFE1 (0 << STR71X_BSPICSR1_RFESHIFT) /* Word 1 enabled */ +#define STR71X_BSPICSR1_RFE12 (1 << STR71X_BSPICSR1_RFESHIFT) /* Word 1-2 enabled */ +#define STR71X_BSPICSR1_RFE13 (2 << STR71X_BSPICSR1_RFESHIFT) /* Word 1-3 enabled */ +#define STR71X_BSPICSR1_RFE14 (3 << STR71X_BSPICSR1_RFESHIFT) /* Word 1-4 enabled */ +#define STR71X_BSPICSR1_RFE15 (4 << STR71X_BSPICSR1_RFESHIFT) /* Word 1-5 enabled */ +#define STR71X_BSPICSR1_RFE16 (5 << STR71X_BSPICSR1_RFESHIFT) /* Word 1-6 enabled */ +#define STR71X_BSPICSR1_RFE17 (6 << STR71X_BSPICSR1_RFESHIFT) /* Word 1-7 enabled */ +#define STR71X_BSPICSR1_RFE18 (7 << STR71X_BSPICSR1_RFESHIFT) /* Word 1-8 enabled */ +#define STR71X_BSPICSR1_RFE19 (8 << STR71X_BSPICSR1_RFESHIFT) /* Word 1-9 enabled */ +#define STR71X_BSPICSR1_RFE110 (9 << STR71X_BSPICSR1_RFESHIFT) /* Word 1-10 enabled */ + +/* BSPI control/status register 2 */ + +#define STR71X_BSPICSR2_DFIFO (1 << 0) /* Bit 0: FIFO disable */ +#define STR71X_BSPICSR2_BERR (1 << 2) /* Bit 2: Bus error */ +#define STR71X_BSPICSR2_RFNE (1 << 3) /* Bit 3: Receiver FIFO not empty */ +#define STR71X_BSPICSR2_RFF (1 << 4) /* Bit 4: Receiver FIFO full */ +#define STR71X_BSPICSR2_ROFL (1 << 5) /* Bit 5: Receiver overflow */ +#define STR71X_BSPICSR2_TFE (1 << 6) /* Bit 6: Transmit FIFO empty */ +#define STR71X_BSPICSR2_TUFL (1 << 7) /* Bit 7: Transmit FIFO underflow */ +#define STR71X_BSPICSR2_TFF (1 << 8) /* Bit 8: Transmit FIFO full */ +#define STR71X_BSPICSR2_TFNE (1 << 9) /* Bit 9: Transmit FIFO not empty */ +#define STR71X_BSPICSR2_TFESHIFT 10 /* Bits 10-13: Transmit FIFO enable*/ +#define STR71X_BSPICSR2_TFEMASK (15 << STR71X_BSPICSR2_TFESHIFT) +#define STR71X_BSPICSR2_TFE1 (0 << STR71X_BSPICSR2_TFESHIFT) /* Word 1 enabled */ +#define STR71X_BSPICSR2_TFE12 (1 << STR71X_BSPICSR2_TFESHIFT) /* Word 1-2 enabled */ +#define STR71X_BSPICSR2_TFE13 (2 << STR71X_BSPICSR2_TFESHIFT) /* Word 1-3 enabled */ +#define STR71X_BSPICSR2_TFE14 (3 << STR71X_BSPICSR2_TFESHIFT) /* Word 1-4 enabled */ +#define STR71X_BSPICSR2_TFE15 (4 << STR71X_BSPICSR2_TFESHIFT) /* Word 1-5 enabled */ +#define STR71X_BSPICSR2_TFE16 (5 << STR71X_BSPICSR2_TFESHIFT) /* Word 1-6 enabled */ +#define STR71X_BSPICSR2_TFE17 (6 << STR71X_BSPICSR2_TFESHIFT) /* Word 1-7 enabled */ +#define STR71X_BSPICSR2_TFE18 (7 << STR71X_BSPICSR2_TFESHIFT) /* Word 1-8 enabled */ +#define STR71X_BSPICSR2_TFE19 (8 << STR71X_BSPICSR2_TFESHIFT) /* Word 1-9 enabled */ +#define STR71X_BSPICSR2_TFE110 (9 << STR71X_BSPICSR2_TFESHIFT) /* Word 1-10 enabled */ +#define STR71X_BSPICSR2_TIESHIFT 14 /* Bit 14-15: BSPI transmit interrupt enable */ +#define STR71X_BSPICSR2_TIEMASK (3 << STR71X_BSPICSR2_TIESHIFT) +#define STR71X_BSPICSR2_TIEDISABLED (0 << STR71X_BSPICSR2_TIESHIFT) /* Disabled */ +#define STR71X_BSPICSR2_TIETFE (1 << STR71X_BSPICSR2_TIESHIFT) /* Interrupt on transmit FIFO empty */ +#define STR71X_BSPICSR2_TIETUFL (2 << STR71X_BSPICSR2_TIESHIFT) /* Interrupt on transmit underlow */ +#define STR71X_BSPICSR2_TIETFF (3 << STR71X_BSPICSR2_TIESHIFT) /* Interrupt on transmit FIFO full */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_STR71X_STR71X_BSPI_H */ diff --git a/nuttx/arch/arm/src/str71x/str71x_can.h b/nuttx/arch/arm/src/str71x/str71x_can.h index a38630d66..a891b60dc 100644 --- a/nuttx/arch/arm/src/str71x/str71x_can.h +++ b/nuttx/arch/arm/src/str71x/str71x_can.h @@ -1,207 +1,207 @@ -/************************************************************************************
- * arch/arm/src/str71x/str71x_can.h
- *
- * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_STR71X_STR71X_CAN_H
-#define __ARCH_ARM_SRC_STR71X_STR71X_CAN_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-
-#include "str71x_map.h"
-
-/************************************************************************************
- * Pre-procesor Definitions
- ************************************************************************************/
-
-/* Registers ************************************************************************/
-
-#define STR71X_CAN_CR (STR71X_CAN_BASE + 0x0000) /* 16-bits wide */
-#define STR71X_CAN_SR (STR71X_CAN_BASE + 0x0004) /* 16-bits wide */
-#define STR71X_CAN_ERR (STR71X_CAN_BASE + 0x0008) /* 16-bits wide */
-#define STR71X_CAN_BTR (STR71X_CAN_BASE + 0x000c) /* 16-bits wide */
-#define STR71X_CAN_IDR (STR71X_CAN_BASE + 0x0010) /* 16-bits wide */
-#define STR71X_CAN_TESTR (STR71X_CAN_BASE + 0x0014) /* 16-bits wide */
-#define STR71X_CAN_BRPR (STR71X_CAN_BASE + 0x0018) /* 16-bits wide */
-
-#define STR71X_CAN_IF1BASE (STR71X_CAN_BASE + 0x0020)
-#define STR71X_CAN_IF2BASE (STR71X_CAN_BASE + 0x0080)
-
-#define STR71X_CAN_CRR_OFFSET (0x0000) /* 16-bits wide */
-#define STR71X_CAN_CMR_OFFSET (0x0004) /* 16-bits wide */
-#define STR71X_CAN_M1R_OFFSET (0x0008) /* 16-bits wide */
-#define STR71X_CAN_M2R_OFFSET (0x000c) /* 16-bits wide */
-#define STR71X_CAN_A1R_OFFSET (0x0010) /* 16-bits wide */
-#define STR71X_CAN_A2R_OFFSET (0x0014) /* 16-bits wide */
-#define STR71X_CAN_MCR_OFFSET (0x0018) /* 16-bits wide */
-#define STR71X_CAN_DA1R_OFFSET (0x001c) /* 16-bits wide */
-#define STR71X_CAN_DA2R_OFFSET (0x0020) /* 16-bits wide */
-#define STR71X_CAN_DB1R_OFFSET (0x0024) /* 16-bits wide */
-#define STR71X_CAN_DB2R_OFFSET (0x0028) /* 16-bits wide */
-
-#define STR71X_CAN_CRR(b) ((b) + STR71X_CAN_CRR_OFFSET)
-#define STR71X_CAN_CMR(b) ((b) + STR71X_CAN_CMR_OFFSET)
-#define STR71X_CAN_M1R(b) ((b) + STR71X_CAN_M1R_OFFSET)
-#define STR71X_CAN_M2R(b) ((b) + STR71X_CAN_M2R_OFFSET)
-#define STR71X_CAN_A1R(b) ((b) + STR71X_CAN_A1R_OFFSET)
-#define STR71X_CAN_A2R(b) ((b) + STR71X_CAN_A2R_OFFSET)
-#define STR71X_CAN_MCR(b) ((b) + STR71X_CAN_MCR_OFFSET)
-#define STR71X_CAN_DA1R(b) ((b) + STR71X_CAN_DA1R_OFFSET)
-#define STR71X_CAN_DA2R(b) ((b) + STR71X_CAN_DA2R_OFFSET)
-#define STR71X_CAN_DB1R(b) ((b) + STR71X_CAN_DB1R_OFFSET)
-#define STR71X_CAN_DB2R(b) ((b) + STR71X_CAN_DB2R_OFFSET)
-
-#define STR71X_CAN_IF1CRR (STR71X_CAN_IF1BASE + STR71X_CAN_CRR_OFFSET)
-#define STR71X_CAN_IF1CMR (STR71X_CAN_IF1BASE + STR71X_CAN_CMR_OFFSET)
-#define STR71X_CAN_IF1M1R (STR71X_CAN_IF1BASE + STR71X_CAN_M1R_OFFSET)
-#define STR71X_CAN_IF1M2R (STR71X_CAN_IF1BASE + STR71X_CAN_M2R_OFFSET)
-#define STR71X_CAN_IF1A1R (STR71X_CAN_IF1BASE + STR71X_CAN_A1R_OFFSET)
-#define STR71X_CAN_IF1A2R (STR71X_CAN_IF1BASE + STR71X_CAN_A2R_OFFSET)
-#define STR71X_CAN_IF1MCR (STR71X_CAN_IF1BASE + STR71X_CAN_MCR_OFFSET)
-#define STR71X_CAN_IF1DA1R (STR71X_CAN_IF1BASE + STR71X_CAN_DA1R_OFFSET)
-#define STR71X_CAN_IF1DA2R (STR71X_CAN_IF1BASE + STR71X_CAN_DA2R_OFFSET)
-#define STR71X_CAN_IF1DB1R (STR71X_CAN_IF1BASE + STR71X_CAN_DB1R_OFFSET)
-#define STR71X_CAN_IF1DB2R (STR71X_CAN_IF1BASE + STR71X_CAN_DB2R_OFFSET)
-
-#define STR71X_CAN_IF2CRR (STR71X_CAN_IF2BASE + STR71X_CAN_CRR_OFFSET)
-#define STR71X_CAN_IF2CMR (STR71X_CAN_IF2BASE + STR71X_CAN_CMR_OFFSET)
-#define STR71X_CAN_IF2M1R (STR71X_CAN_IF2BASE + STR71X_CAN_M1R_OFFSET)
-#define STR71X_CAN_IF2M2R (STR71X_CAN_IF2BASE + STR71X_CAN_M2R_OFFSET)
-#define STR71X_CAN_IF2A1R (STR71X_CAN_IF2BASE + STR71X_CAN_A1R_OFFSET)
-#define STR71X_CAN_IF2A2R (STR71X_CAN_IF2BASE + STR71X_CAN_A2R_OFFSET)
-#define STR71X_CAN_IF2MCR (STR71X_CAN_IF2BASE + STR71X_CAN_MCR_OFFSET)
-#define STR71X_CAN_IF2DA1R (STR71X_CAN_IF2BASE + STR71X_CAN_DA1R_OFFSET)
-#define STR71X_CAN_IF2DA2R (STR71X_CAN_IF2BASE + STR71X_CAN_DA2R_OFFSET)
-#define STR71X_CAN_IF2DB1R (STR71X_CAN_IF2BASE + STR71X_CAN_DB1R_OFFSET)
-#define STR71X_CAN_IF2DB2R (STR71X_CAN_IF2BASE + STR71X_CAN_DB2R_OFFSET)
-
-#define STR71X_CAN_TR1R (STR71X_CAN_BASE + 0x0100) /* 16-bits wide */
-#define STR71X_CAN_TR2R (STR71X_CAN_BASE + 0x0104) /* 16-bits wide */
-#define STR71X_CAN_ND1R (STR71X_CAN_BASE + 0x0120) /* 16-bits wide */
-#define STR71X_CAN_ND2R (STR71X_CAN_BASE + 0x0124) /* 16-bits wide */
-#define STR71X_CAN_IP1R (STR71X_CAN_BASE + 0x0140) /* 16-bits wide */
-#define STR71X_CAN_IP2R (STR71X_CAN_BASE + 0x0144) /* 16-bits wide */
-#define STR71X_CAN_MV1R (STR71X_CAN_BASE + 0x0160) /* 16-bits wide */
-#define STR71X_CAN_MV2R (STR71X_CAN_BASE + 0x0164) /* 16-bits wide */
-
-/* Register bit settings ***********************************************************/
-
-/* Control register */
-
-#define STR41X_CANCR_INIT (0x0001)
-#define STR41X_CANCR_IE (0x0002)
-#define STR41X_CANCR_SIE (0x0004)
-#define STR41X_CANCR_EIE (0x0008)
-#define STR41X_CANCR_DAR (0x0020)
-#define STR41X_CANCR_CCE (0x0040)
-#define STR41X_CANCR_TEST (0x0080)
-
-/* Status register */
-
-#define STR41X_CANSR_LEC (0x0007)
-#define STR41X_CANSR_TXOK (0x0008)
-#define STR41X_CANSR_RXOK (0x0010)
-#define STR41X_CANSR_EPASS (0x0020)
-#define STR41X_CANSR_EWARN (0x0040)
-#define STR41X_CANSR_BOFF (0x0080)
-
-/* Test register */
-
-#define STR41X_CANTESTR_BASIC (0x0004)
-#define STR41X_CANTESTR_SILENT (0x0008)
-#define STR41X_CANTESTR_LBACK (0x0010)
-#define STR41X_CANTESTR_TX0 (0x0020)
-#define STR41X_CANTESTR_TX1 (0x0040)
-#define STR41X_CANTESTR_RX (0x0080)
-
-/* IFn / Command Request register */
-
-#define STR41X_CANCRR_BUSY (0x8000)
-
-/* IFn / Command Mask register */
-
-#define STR41X_CANCMR_DATAB (0x0001)
-#define STR41X_CANCMR_DATAA (0x0002)
-#define STR41X_CANCMR_TXRQST (0x0004)
-#define STR41X_CANCMR_CLRINTPND (0x0008)
-#define STR41X_CANCMR_CONTROL (0x0010)
-#define STR41X_CANCMR_ARB (0x0020)
-#define STR41X_CANCMR_MASK (0x0040)
-#define STR41X_CANCMR_WRRD (0x0080)
-
-/* IFn / Mask 2 register */
-
-#define STR41X_CANM2R_MXTD (0x8000)
-#define STR41X_CANM2R_MDIR (0x4000)
-
-/* IFn / Arbitration 2 register */
-
-#define STR41X_CANA2R_DIR (0x2000)
-#define STR41X_CANA2R_XTD (0x4000)
-#define STR41X_CANA2R_MSGVAL (0x8000)
-
-/* IFn / Message Control register */
-
-#define STR41X_CANMCR_EOB (0x0080)
-#define STR41X_CANMCR_TXRQST (0x0100)
-#define STR41X_CANMCR_RMTEN (0x0200)
-#define STR41X_CANMCR_RXIE (0x0400)
-#define STR41X_CANMCR_TXIE (0x0800)
-#define STR41X_CANMCR_UMASK (0x1000)
-#define STR41X_CANMCR_INTPND (0x2000)
-#define STR41X_CANMCR_MSGLST (0x4000)
-#define STR41X_CANMCR_NEWDAT (0x8000)
-
-/* Message ID limits */
-
-#define STR41X_CAN_LASTSTDID ((1 << 11) - 1)
-#define STR41X_CAN_LASTEXTID ((1 << 29) - 1)
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-/************************************************************************************
- * Public Functions
- ************************************************************************************/
-
-#endif /* __ARCH_ARM_SRC_STR71X_STR71X_CAN_H */
-
+/************************************************************************************ + * arch/arm/src/str71x/str71x_can.h + * + * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STR71X_STR71X_CAN_H +#define __ARCH_ARM_SRC_STR71X_STR71X_CAN_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +#include "str71x_map.h" + +/************************************************************************************ + * Pre-procesor Definitions + ************************************************************************************/ + +/* Registers ************************************************************************/ + +#define STR71X_CAN_CR (STR71X_CAN_BASE + 0x0000) /* 16-bits wide */ +#define STR71X_CAN_SR (STR71X_CAN_BASE + 0x0004) /* 16-bits wide */ +#define STR71X_CAN_ERR (STR71X_CAN_BASE + 0x0008) /* 16-bits wide */ +#define STR71X_CAN_BTR (STR71X_CAN_BASE + 0x000c) /* 16-bits wide */ +#define STR71X_CAN_IDR (STR71X_CAN_BASE + 0x0010) /* 16-bits wide */ +#define STR71X_CAN_TESTR (STR71X_CAN_BASE + 0x0014) /* 16-bits wide */ +#define STR71X_CAN_BRPR (STR71X_CAN_BASE + 0x0018) /* 16-bits wide */ + +#define STR71X_CAN_IF1BASE (STR71X_CAN_BASE + 0x0020) +#define STR71X_CAN_IF2BASE (STR71X_CAN_BASE + 0x0080) + +#define STR71X_CAN_CRR_OFFSET (0x0000) /* 16-bits wide */ +#define STR71X_CAN_CMR_OFFSET (0x0004) /* 16-bits wide */ +#define STR71X_CAN_M1R_OFFSET (0x0008) /* 16-bits wide */ +#define STR71X_CAN_M2R_OFFSET (0x000c) /* 16-bits wide */ +#define STR71X_CAN_A1R_OFFSET (0x0010) /* 16-bits wide */ +#define STR71X_CAN_A2R_OFFSET (0x0014) /* 16-bits wide */ +#define STR71X_CAN_MCR_OFFSET (0x0018) /* 16-bits wide */ +#define STR71X_CAN_DA1R_OFFSET (0x001c) /* 16-bits wide */ +#define STR71X_CAN_DA2R_OFFSET (0x0020) /* 16-bits wide */ +#define STR71X_CAN_DB1R_OFFSET (0x0024) /* 16-bits wide */ +#define STR71X_CAN_DB2R_OFFSET (0x0028) /* 16-bits wide */ + +#define STR71X_CAN_CRR(b) ((b) + STR71X_CAN_CRR_OFFSET) +#define STR71X_CAN_CMR(b) ((b) + STR71X_CAN_CMR_OFFSET) +#define STR71X_CAN_M1R(b) ((b) + STR71X_CAN_M1R_OFFSET) +#define STR71X_CAN_M2R(b) ((b) + STR71X_CAN_M2R_OFFSET) +#define STR71X_CAN_A1R(b) ((b) + STR71X_CAN_A1R_OFFSET) +#define STR71X_CAN_A2R(b) ((b) + STR71X_CAN_A2R_OFFSET) +#define STR71X_CAN_MCR(b) ((b) + STR71X_CAN_MCR_OFFSET) +#define STR71X_CAN_DA1R(b) ((b) + STR71X_CAN_DA1R_OFFSET) +#define STR71X_CAN_DA2R(b) ((b) + STR71X_CAN_DA2R_OFFSET) +#define STR71X_CAN_DB1R(b) ((b) + STR71X_CAN_DB1R_OFFSET) +#define STR71X_CAN_DB2R(b) ((b) + STR71X_CAN_DB2R_OFFSET) + +#define STR71X_CAN_IF1CRR (STR71X_CAN_IF1BASE + STR71X_CAN_CRR_OFFSET) +#define STR71X_CAN_IF1CMR (STR71X_CAN_IF1BASE + STR71X_CAN_CMR_OFFSET) +#define STR71X_CAN_IF1M1R (STR71X_CAN_IF1BASE + STR71X_CAN_M1R_OFFSET) +#define STR71X_CAN_IF1M2R (STR71X_CAN_IF1BASE + STR71X_CAN_M2R_OFFSET) +#define STR71X_CAN_IF1A1R (STR71X_CAN_IF1BASE + STR71X_CAN_A1R_OFFSET) +#define STR71X_CAN_IF1A2R (STR71X_CAN_IF1BASE + STR71X_CAN_A2R_OFFSET) +#define STR71X_CAN_IF1MCR (STR71X_CAN_IF1BASE + STR71X_CAN_MCR_OFFSET) +#define STR71X_CAN_IF1DA1R (STR71X_CAN_IF1BASE + STR71X_CAN_DA1R_OFFSET) +#define STR71X_CAN_IF1DA2R (STR71X_CAN_IF1BASE + STR71X_CAN_DA2R_OFFSET) +#define STR71X_CAN_IF1DB1R (STR71X_CAN_IF1BASE + STR71X_CAN_DB1R_OFFSET) +#define STR71X_CAN_IF1DB2R (STR71X_CAN_IF1BASE + STR71X_CAN_DB2R_OFFSET) + +#define STR71X_CAN_IF2CRR (STR71X_CAN_IF2BASE + STR71X_CAN_CRR_OFFSET) +#define STR71X_CAN_IF2CMR (STR71X_CAN_IF2BASE + STR71X_CAN_CMR_OFFSET) +#define STR71X_CAN_IF2M1R (STR71X_CAN_IF2BASE + STR71X_CAN_M1R_OFFSET) +#define STR71X_CAN_IF2M2R (STR71X_CAN_IF2BASE + STR71X_CAN_M2R_OFFSET) +#define STR71X_CAN_IF2A1R (STR71X_CAN_IF2BASE + STR71X_CAN_A1R_OFFSET) +#define STR71X_CAN_IF2A2R (STR71X_CAN_IF2BASE + STR71X_CAN_A2R_OFFSET) +#define STR71X_CAN_IF2MCR (STR71X_CAN_IF2BASE + STR71X_CAN_MCR_OFFSET) +#define STR71X_CAN_IF2DA1R (STR71X_CAN_IF2BASE + STR71X_CAN_DA1R_OFFSET) +#define STR71X_CAN_IF2DA2R (STR71X_CAN_IF2BASE + STR71X_CAN_DA2R_OFFSET) +#define STR71X_CAN_IF2DB1R (STR71X_CAN_IF2BASE + STR71X_CAN_DB1R_OFFSET) +#define STR71X_CAN_IF2DB2R (STR71X_CAN_IF2BASE + STR71X_CAN_DB2R_OFFSET) + +#define STR71X_CAN_TR1R (STR71X_CAN_BASE + 0x0100) /* 16-bits wide */ +#define STR71X_CAN_TR2R (STR71X_CAN_BASE + 0x0104) /* 16-bits wide */ +#define STR71X_CAN_ND1R (STR71X_CAN_BASE + 0x0120) /* 16-bits wide */ +#define STR71X_CAN_ND2R (STR71X_CAN_BASE + 0x0124) /* 16-bits wide */ +#define STR71X_CAN_IP1R (STR71X_CAN_BASE + 0x0140) /* 16-bits wide */ +#define STR71X_CAN_IP2R (STR71X_CAN_BASE + 0x0144) /* 16-bits wide */ +#define STR71X_CAN_MV1R (STR71X_CAN_BASE + 0x0160) /* 16-bits wide */ +#define STR71X_CAN_MV2R (STR71X_CAN_BASE + 0x0164) /* 16-bits wide */ + +/* Register bit settings ***********************************************************/ + +/* Control register */ + +#define STR41X_CANCR_INIT (0x0001) +#define STR41X_CANCR_IE (0x0002) +#define STR41X_CANCR_SIE (0x0004) +#define STR41X_CANCR_EIE (0x0008) +#define STR41X_CANCR_DAR (0x0020) +#define STR41X_CANCR_CCE (0x0040) +#define STR41X_CANCR_TEST (0x0080) + +/* Status register */ + +#define STR41X_CANSR_LEC (0x0007) +#define STR41X_CANSR_TXOK (0x0008) +#define STR41X_CANSR_RXOK (0x0010) +#define STR41X_CANSR_EPASS (0x0020) +#define STR41X_CANSR_EWARN (0x0040) +#define STR41X_CANSR_BOFF (0x0080) + +/* Test register */ + +#define STR41X_CANTESTR_BASIC (0x0004) +#define STR41X_CANTESTR_SILENT (0x0008) +#define STR41X_CANTESTR_LBACK (0x0010) +#define STR41X_CANTESTR_TX0 (0x0020) +#define STR41X_CANTESTR_TX1 (0x0040) +#define STR41X_CANTESTR_RX (0x0080) + +/* IFn / Command Request register */ + +#define STR41X_CANCRR_BUSY (0x8000) + +/* IFn / Command Mask register */ + +#define STR41X_CANCMR_DATAB (0x0001) +#define STR41X_CANCMR_DATAA (0x0002) +#define STR41X_CANCMR_TXRQST (0x0004) +#define STR41X_CANCMR_CLRINTPND (0x0008) +#define STR41X_CANCMR_CONTROL (0x0010) +#define STR41X_CANCMR_ARB (0x0020) +#define STR41X_CANCMR_MASK (0x0040) +#define STR41X_CANCMR_WRRD (0x0080) + +/* IFn / Mask 2 register */ + +#define STR41X_CANM2R_MXTD (0x8000) +#define STR41X_CANM2R_MDIR (0x4000) + +/* IFn / Arbitration 2 register */ + +#define STR41X_CANA2R_DIR (0x2000) +#define STR41X_CANA2R_XTD (0x4000) +#define STR41X_CANA2R_MSGVAL (0x8000) + +/* IFn / Message Control register */ + +#define STR41X_CANMCR_EOB (0x0080) +#define STR41X_CANMCR_TXRQST (0x0100) +#define STR41X_CANMCR_RMTEN (0x0200) +#define STR41X_CANMCR_RXIE (0x0400) +#define STR41X_CANMCR_TXIE (0x0800) +#define STR41X_CANMCR_UMASK (0x1000) +#define STR41X_CANMCR_INTPND (0x2000) +#define STR41X_CANMCR_MSGLST (0x4000) +#define STR41X_CANMCR_NEWDAT (0x8000) + +/* Message ID limits */ + +#define STR41X_CAN_LASTSTDID ((1 << 11) - 1) +#define STR41X_CAN_LASTEXTID ((1 << 29) - 1) + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_STR71X_STR71X_CAN_H */ + diff --git a/nuttx/arch/arm/src/str71x/str71x_decodeirq.c b/nuttx/arch/arm/src/str71x/str71x_decodeirq.c index 8a24ea44d..326abd763 100644 --- a/nuttx/arch/arm/src/str71x/str71x_decodeirq.c +++ b/nuttx/arch/arm/src/str71x/str71x_decodeirq.c @@ -2,7 +2,7 @@ * arch/arm/src/str71x/str71x_decodeirq.c * * Copyright (C) 2008-2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/str71x/str71x_eic.h b/nuttx/arch/arm/src/str71x/str71x_eic.h index 7b0301695..c45cfaa6b 100644 --- a/nuttx/arch/arm/src/str71x/str71x_eic.h +++ b/nuttx/arch/arm/src/str71x/str71x_eic.h @@ -1,176 +1,176 @@ -/************************************************************************************
- * arch/arm/src/str71x/str71x_eic.h
- *
- * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_STR71X_STR71X_EIC_H
-#define __ARCH_ARM_SRC_STR71X_STR71X_EIC_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-
-#include <arch/irq.h>
-
-/************************************************************************************
- * Pre-procesor Definitions
- ************************************************************************************/
-
-/* Enhanced Interupt Controller (EIC) register offsets ******************************/
-
-#define STR71X_EIC_ICR_OFFSET (0x0000) /* 32-bits wide */
-#define STR71X_EIC_CICR_OFFSET (0x0004) /* 32-bits wide */
-#define STR71X_EIC_CIPR_OFFSET (0x0008) /* 32-bits wide */
-#define STR71X_EIC_IVR_OFFSET (0x0018) /* 32-bits wide */
-#define STR71X_EIC_FIR_OFFSET (0x001c) /* 32-bits wide */
-#define STR71X_EIC_IER_OFFSET (0x0020) /* 32-bits wide */
-#define STR71X_EIC_IPR_OFFSET (0x0040) /* 32-bits wide */
-
-#define STR71X_EIC_SIR_OFFSET (0x0060) /* 32 x 32-bits */
-#define STR71X_EIC_SIR0_OFFSET (0x0060) /* 32-bits wide */
-#define STR71X_EIC_SIR1_OFFSET (0x0064) /* 32-bits wide */
-#define STR71X_EIC_SIR2_OFFSET (0x0068) /* 32-bits wide */
-#define STR71X_EIC_SIR3_OFFSET (0x006c) /* 32-bits wide */
-#define STR71X_EIC_SIR4_OFFSET (0x0070) /* 32-bits wide */
-#define STR71X_EIC_SIR5_OFFSET (0x0074) /* 32-bits wide */
-#define STR71X_EIC_SIR6_OFFSET (0x0078) /* 32-bits wide */
-#define STR71X_EIC_SIR7_OFFSET (0x007c) /* 32-bits wide */
-#define STR71X_EIC_SIR8_OFFSET (0x0080) /* 32-bits wide */
-#define STR71X_EIC_SIR9_OFFSET (0x0084) /* 32-bits wide */
-#define STR71X_EIC_SIR10_OFFSET (0x0088) /* 32-bits wide */
-#define STR71X_EIC_SIR11_OFFSET (0x008c) /* 32-bits wide */
-#define STR71X_EIC_SIR12_OFFSET (0x0090) /* 32-bits wide */
-#define STR71X_EIC_SIR13_OFFSET (0x0094) /* 32-bits wide */
-#define STR71X_EIC_SIR14_OFFSET (0x0098) /* 32-bits wide */
-#define STR71X_EIC_SIR15_OFFSET (0x009c) /* 32-bits wide */
-#define STR71X_EIC_SIR16_OFFSET (0x00a0) /* 32-bits wide */
-#define STR71X_EIC_SIR17_OFFSET (0x00a4) /* 32-bits wide */
-#define STR71X_EIC_SIR18_OFFSET (0x00a8) /* 32-bits wide */
-#define STR71X_EIC_SIR19_OFFSET (0x00ac) /* 32-bits wide */
-#define STR71X_EIC_SIR20_OFFSET (0x00b0) /* 32-bits wide */
-#define STR71X_EIC_SIR21_OFFSET (0x00b4) /* 32-bits wide */
-#define STR71X_EIC_SIR22_OFFSET (0x00b8) /* 32-bits wide */
-#define STR71X_EIC_SIR23_OFFSET (0x00bc) /* 32-bits wide */
-#define STR71X_EIC_SIR24_OFFSET (0x00c0) /* 32-bits wide */
-#define STR71X_EIC_SIR25_OFFSET (0x00c4) /* 32-bits wide */
-#define STR71X_EIC_SIR26_OFFSET (0x00c8) /* 32-bits wide */
-#define STR71X_EIC_SIR27_OFFSET (0x00cc) /* 32-bits wide */
-#define STR71X_EIC_SIR28_OFFSET (0x00d0) /* 32-bits wide */
-#define STR71X_EIC_SIR29_OFFSET (0x00d4) /* 32-bits wide */
-#define STR71X_EIC_SIR30_OFFSET (0x00d8) /* 32-bits wide */
-#define STR71X_EIC_SIR31_OFFSET (0x00dc) /* 32-bits wide */
-
-#define STR71X_EIC_NCHANNELS (32)
-#define STR71X_EIC_SIR_BASE (STR71X_EIC_BASE + STR71X_EIC_SIR_OFFSET)
-
-/* Enhanced Interupt Controller (EIC) registers *************************************/
-
-#define STR71X_EIC_ICR (STR71X_EIC_BASE + STR71X_EIC_ICR_OFFSET)
-#define STR71X_EIC_CICR (STR71X_EIC_BASE + STR71X_EIC_CICR_OFFSET)
-#define STR71X_EIC_CIPR (STR71X_EIC_BASE + STR71X_EIC_CIPR_OFFSET)
-#define STR71X_EIC_IVR (STR71X_EIC_BASE + STR71X_EIC_IVR_OFFSET)
-#define STR71X_EIC_FIR (STR71X_EIC_BASE + STR71X_EIC_FIR_OFFSET)
-#define STR71X_EIC_IER (STR71X_EIC_BASE + STR71X_EIC_IER_OFFSET)
-#define STR71X_EIC_IPR (STR71X_EIC_BASE + STR71X_EIC_IPR_OFFSET)
-
-#define STR71X_EIC_SIR(n) (STR71X_EIC_SIR_BASE + ((n) << 2))
-
-#define STR71X_EIC_SIR0 (STR71X_EIC_BASE + STR71X_EIC_SIR0_OFFSET)
-#define STR71X_EIC_SIR1 (STR71X_EIC_BASE + STR71X_EIC_SIR1_OFFSET)
-#define STR71X_EIC_SIR2 (STR71X_EIC_BASE + STR71X_EIC_SIR2_OFFSET)
-#define STR71X_EIC_SIR3 (STR71X_EIC_BASE + STR71X_EIC_SIR3_OFFSET)
-#define STR71X_EIC_SIR4 (STR71X_EIC_BASE + STR71X_EIC_SIR4_OFFSET)
-#define STR71X_EIC_SIR5 (STR71X_EIC_BASE + STR71X_EIC_SIR5_OFFSET)
-#define STR71X_EIC_SIR6 (STR71X_EIC_BASE + STR71X_EIC_SIR6_OFFSET)
-#define STR71X_EIC_SIR7 (STR71X_EIC_BASE + STR71X_EIC_SIR7_OFFSET)
-#define STR71X_EIC_SIR8 (STR71X_EIC_BASE + STR71X_EIC_SIR8_OFFSET)
-#define STR71X_EIC_SIR9 (STR71X_EIC_BASE + STR71X_EIC_SIR9_OFFSET)
-#define STR71X_EIC_SIR10 (STR71X_EIC_BASE + STR71X_EIC_SIR10_OFFSET)
-#define STR71X_EIC_SIR11 (STR71X_EIC_BASE + STR71X_EIC_SIR11_OFFSET)
-#define STR71X_EIC_SIR12 (STR71X_EIC_BASE + STR71X_EIC_SIR12_OFFSET)
-#define STR71X_EIC_SIR13 (STR71X_EIC_BASE + STR71X_EIC_SIR13_OFFSET)
-#define STR71X_EIC_SIR14 (STR71X_EIC_BASE + STR71X_EIC_SIR14_OFFSET)
-#define STR71X_EIC_SIR15 (STR71X_EIC_BASE + STR71X_EIC_SIR15_OFFSET)
-#define STR71X_EIC_SIR16 (STR71X_EIC_BASE + STR71X_EIC_SIR16_OFFSET)
-#define STR71X_EIC_SIR17 (STR71X_EIC_BASE + STR71X_EIC_SIR17_OFFSET)
-#define STR71X_EIC_SIR18 (STR71X_EIC_BASE + STR71X_EIC_SIR18_OFFSET)
-#define STR71X_EIC_SIR19 (STR71X_EIC_BASE + STR71X_EIC_SIR19_OFFSET)
-#define STR71X_EIC_SIR20 (STR71X_EIC_BASE + STR71X_EIC_SIR20_OFFSET)
-#define STR71X_EIC_SIR21 (STR71X_EIC_BASE + STR71X_EIC_SIR21_OFFSET)
-#define STR71X_EIC_SIR22 (STR71X_EIC_BASE + STR71X_EIC_SIR22_OFFSET)
-#define STR71X_EIC_SIR23 (STR71X_EIC_BASE + STR71X_EIC_SIR23_OFFSET)
-#define STR71X_EIC_SIR24 (STR71X_EIC_BASE + STR71X_EIC_SIR24_OFFSET)
-#define STR71X_EIC_SIR25 (STR71X_EIC_BASE + STR71X_EIC_SIR25_OFFSET)
-#define STR71X_EIC_SIR26 (STR71X_EIC_BASE + STR71X_EIC_SIR26_OFFSET)
-#define STR71X_EIC_SIR27 (STR71X_EIC_BASE + STR71X_EIC_SIR27_OFFSET)
-#define STR71X_EIC_SIR28 (STR71X_EIC_BASE + STR71X_EIC_SIR28_OFFSET)
-#define STR71X_EIC_SIR29 (STR71X_EIC_BASE + STR71X_EIC_SIR29_OFFSET)
-#define STR71X_EIC_SIR30 (STR71X_EIC_BASE + STR71X_EIC_SIR30_OFFSET)
-#define STR71X_EIC_SIR31 (STR71X_EIC_BASE + STR71X_EIC_SIR31_OFFSET)
-
-/* Register bit settings ************************************************************/
-
-/* Interrupt control register (ICR) bit definitions */
-
-#define STR71X_EICICR_IRQEN (0x00000001) /* Bit 0: IRQ output enable */
-#define STR71X_EICICR_FIQEN (0x00000002) /* Bit 1: FIQ output enable */
-
-/* Current interrupt channel register (CICR) bit definitions */
-
-#define STR71X_EICCICR_MASK 0x1f /* Bits: 0-4: CIC */
-
-/* Fast interrupt register (FIR) bit definitions */
-
-#define STR71X_EICFIR_FIE (0x00000001) /* Bit 0: FIQ channel 1/0 enable */
-#define STR71X_EICFIR_FIP (0x00000002) /* Bit 1: channel 1/0 FIQ pending */
-
-/* Source interrrupt register definitions */
-
-#define STR71X_EICSIR_SIPLMASK (0x0000000f) /* Bits 0-3: Source interrupt priority level */
-#define STR71X_EICSIR_SIVMASK (0xffff0000) /* Bits 16-31: Source interrupt vector */
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-/************************************************************************************
- * Public Functions
- ************************************************************************************/
-
-#endif /* __ARCH_ARM_SRC_STR71X_STR71X_EIC_H */
+/************************************************************************************ + * arch/arm/src/str71x/str71x_eic.h + * + * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STR71X_STR71X_EIC_H +#define __ARCH_ARM_SRC_STR71X_STR71X_EIC_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +#include <arch/irq.h> + +/************************************************************************************ + * Pre-procesor Definitions + ************************************************************************************/ + +/* Enhanced Interupt Controller (EIC) register offsets ******************************/ + +#define STR71X_EIC_ICR_OFFSET (0x0000) /* 32-bits wide */ +#define STR71X_EIC_CICR_OFFSET (0x0004) /* 32-bits wide */ +#define STR71X_EIC_CIPR_OFFSET (0x0008) /* 32-bits wide */ +#define STR71X_EIC_IVR_OFFSET (0x0018) /* 32-bits wide */ +#define STR71X_EIC_FIR_OFFSET (0x001c) /* 32-bits wide */ +#define STR71X_EIC_IER_OFFSET (0x0020) /* 32-bits wide */ +#define STR71X_EIC_IPR_OFFSET (0x0040) /* 32-bits wide */ + +#define STR71X_EIC_SIR_OFFSET (0x0060) /* 32 x 32-bits */ +#define STR71X_EIC_SIR0_OFFSET (0x0060) /* 32-bits wide */ +#define STR71X_EIC_SIR1_OFFSET (0x0064) /* 32-bits wide */ +#define STR71X_EIC_SIR2_OFFSET (0x0068) /* 32-bits wide */ +#define STR71X_EIC_SIR3_OFFSET (0x006c) /* 32-bits wide */ +#define STR71X_EIC_SIR4_OFFSET (0x0070) /* 32-bits wide */ +#define STR71X_EIC_SIR5_OFFSET (0x0074) /* 32-bits wide */ +#define STR71X_EIC_SIR6_OFFSET (0x0078) /* 32-bits wide */ +#define STR71X_EIC_SIR7_OFFSET (0x007c) /* 32-bits wide */ +#define STR71X_EIC_SIR8_OFFSET (0x0080) /* 32-bits wide */ +#define STR71X_EIC_SIR9_OFFSET (0x0084) /* 32-bits wide */ +#define STR71X_EIC_SIR10_OFFSET (0x0088) /* 32-bits wide */ +#define STR71X_EIC_SIR11_OFFSET (0x008c) /* 32-bits wide */ +#define STR71X_EIC_SIR12_OFFSET (0x0090) /* 32-bits wide */ +#define STR71X_EIC_SIR13_OFFSET (0x0094) /* 32-bits wide */ +#define STR71X_EIC_SIR14_OFFSET (0x0098) /* 32-bits wide */ +#define STR71X_EIC_SIR15_OFFSET (0x009c) /* 32-bits wide */ +#define STR71X_EIC_SIR16_OFFSET (0x00a0) /* 32-bits wide */ +#define STR71X_EIC_SIR17_OFFSET (0x00a4) /* 32-bits wide */ +#define STR71X_EIC_SIR18_OFFSET (0x00a8) /* 32-bits wide */ +#define STR71X_EIC_SIR19_OFFSET (0x00ac) /* 32-bits wide */ +#define STR71X_EIC_SIR20_OFFSET (0x00b0) /* 32-bits wide */ +#define STR71X_EIC_SIR21_OFFSET (0x00b4) /* 32-bits wide */ +#define STR71X_EIC_SIR22_OFFSET (0x00b8) /* 32-bits wide */ +#define STR71X_EIC_SIR23_OFFSET (0x00bc) /* 32-bits wide */ +#define STR71X_EIC_SIR24_OFFSET (0x00c0) /* 32-bits wide */ +#define STR71X_EIC_SIR25_OFFSET (0x00c4) /* 32-bits wide */ +#define STR71X_EIC_SIR26_OFFSET (0x00c8) /* 32-bits wide */ +#define STR71X_EIC_SIR27_OFFSET (0x00cc) /* 32-bits wide */ +#define STR71X_EIC_SIR28_OFFSET (0x00d0) /* 32-bits wide */ +#define STR71X_EIC_SIR29_OFFSET (0x00d4) /* 32-bits wide */ +#define STR71X_EIC_SIR30_OFFSET (0x00d8) /* 32-bits wide */ +#define STR71X_EIC_SIR31_OFFSET (0x00dc) /* 32-bits wide */ + +#define STR71X_EIC_NCHANNELS (32) +#define STR71X_EIC_SIR_BASE (STR71X_EIC_BASE + STR71X_EIC_SIR_OFFSET) + +/* Enhanced Interupt Controller (EIC) registers *************************************/ + +#define STR71X_EIC_ICR (STR71X_EIC_BASE + STR71X_EIC_ICR_OFFSET) +#define STR71X_EIC_CICR (STR71X_EIC_BASE + STR71X_EIC_CICR_OFFSET) +#define STR71X_EIC_CIPR (STR71X_EIC_BASE + STR71X_EIC_CIPR_OFFSET) +#define STR71X_EIC_IVR (STR71X_EIC_BASE + STR71X_EIC_IVR_OFFSET) +#define STR71X_EIC_FIR (STR71X_EIC_BASE + STR71X_EIC_FIR_OFFSET) +#define STR71X_EIC_IER (STR71X_EIC_BASE + STR71X_EIC_IER_OFFSET) +#define STR71X_EIC_IPR (STR71X_EIC_BASE + STR71X_EIC_IPR_OFFSET) + +#define STR71X_EIC_SIR(n) (STR71X_EIC_SIR_BASE + ((n) << 2)) + +#define STR71X_EIC_SIR0 (STR71X_EIC_BASE + STR71X_EIC_SIR0_OFFSET) +#define STR71X_EIC_SIR1 (STR71X_EIC_BASE + STR71X_EIC_SIR1_OFFSET) +#define STR71X_EIC_SIR2 (STR71X_EIC_BASE + STR71X_EIC_SIR2_OFFSET) +#define STR71X_EIC_SIR3 (STR71X_EIC_BASE + STR71X_EIC_SIR3_OFFSET) +#define STR71X_EIC_SIR4 (STR71X_EIC_BASE + STR71X_EIC_SIR4_OFFSET) +#define STR71X_EIC_SIR5 (STR71X_EIC_BASE + STR71X_EIC_SIR5_OFFSET) +#define STR71X_EIC_SIR6 (STR71X_EIC_BASE + STR71X_EIC_SIR6_OFFSET) +#define STR71X_EIC_SIR7 (STR71X_EIC_BASE + STR71X_EIC_SIR7_OFFSET) +#define STR71X_EIC_SIR8 (STR71X_EIC_BASE + STR71X_EIC_SIR8_OFFSET) +#define STR71X_EIC_SIR9 (STR71X_EIC_BASE + STR71X_EIC_SIR9_OFFSET) +#define STR71X_EIC_SIR10 (STR71X_EIC_BASE + STR71X_EIC_SIR10_OFFSET) +#define STR71X_EIC_SIR11 (STR71X_EIC_BASE + STR71X_EIC_SIR11_OFFSET) +#define STR71X_EIC_SIR12 (STR71X_EIC_BASE + STR71X_EIC_SIR12_OFFSET) +#define STR71X_EIC_SIR13 (STR71X_EIC_BASE + STR71X_EIC_SIR13_OFFSET) +#define STR71X_EIC_SIR14 (STR71X_EIC_BASE + STR71X_EIC_SIR14_OFFSET) +#define STR71X_EIC_SIR15 (STR71X_EIC_BASE + STR71X_EIC_SIR15_OFFSET) +#define STR71X_EIC_SIR16 (STR71X_EIC_BASE + STR71X_EIC_SIR16_OFFSET) +#define STR71X_EIC_SIR17 (STR71X_EIC_BASE + STR71X_EIC_SIR17_OFFSET) +#define STR71X_EIC_SIR18 (STR71X_EIC_BASE + STR71X_EIC_SIR18_OFFSET) +#define STR71X_EIC_SIR19 (STR71X_EIC_BASE + STR71X_EIC_SIR19_OFFSET) +#define STR71X_EIC_SIR20 (STR71X_EIC_BASE + STR71X_EIC_SIR20_OFFSET) +#define STR71X_EIC_SIR21 (STR71X_EIC_BASE + STR71X_EIC_SIR21_OFFSET) +#define STR71X_EIC_SIR22 (STR71X_EIC_BASE + STR71X_EIC_SIR22_OFFSET) +#define STR71X_EIC_SIR23 (STR71X_EIC_BASE + STR71X_EIC_SIR23_OFFSET) +#define STR71X_EIC_SIR24 (STR71X_EIC_BASE + STR71X_EIC_SIR24_OFFSET) +#define STR71X_EIC_SIR25 (STR71X_EIC_BASE + STR71X_EIC_SIR25_OFFSET) +#define STR71X_EIC_SIR26 (STR71X_EIC_BASE + STR71X_EIC_SIR26_OFFSET) +#define STR71X_EIC_SIR27 (STR71X_EIC_BASE + STR71X_EIC_SIR27_OFFSET) +#define STR71X_EIC_SIR28 (STR71X_EIC_BASE + STR71X_EIC_SIR28_OFFSET) +#define STR71X_EIC_SIR29 (STR71X_EIC_BASE + STR71X_EIC_SIR29_OFFSET) +#define STR71X_EIC_SIR30 (STR71X_EIC_BASE + STR71X_EIC_SIR30_OFFSET) +#define STR71X_EIC_SIR31 (STR71X_EIC_BASE + STR71X_EIC_SIR31_OFFSET) + +/* Register bit settings ************************************************************/ + +/* Interrupt control register (ICR) bit definitions */ + +#define STR71X_EICICR_IRQEN (0x00000001) /* Bit 0: IRQ output enable */ +#define STR71X_EICICR_FIQEN (0x00000002) /* Bit 1: FIQ output enable */ + +/* Current interrupt channel register (CICR) bit definitions */ + +#define STR71X_EICCICR_MASK 0x1f /* Bits: 0-4: CIC */ + +/* Fast interrupt register (FIR) bit definitions */ + +#define STR71X_EICFIR_FIE (0x00000001) /* Bit 0: FIQ channel 1/0 enable */ +#define STR71X_EICFIR_FIP (0x00000002) /* Bit 1: channel 1/0 FIQ pending */ + +/* Source interrrupt register definitions */ + +#define STR71X_EICSIR_SIPLMASK (0x0000000f) /* Bits 0-3: Source interrupt priority level */ +#define STR71X_EICSIR_SIVMASK (0xffff0000) /* Bits 16-31: Source interrupt vector */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_STR71X_STR71X_EIC_H */ diff --git a/nuttx/arch/arm/src/str71x/str71x_emi.h b/nuttx/arch/arm/src/str71x/str71x_emi.h index 68c35cd07..ade4d1145 100644 --- a/nuttx/arch/arm/src/str71x/str71x_emi.h +++ b/nuttx/arch/arm/src/str71x/str71x_emi.h @@ -1,103 +1,103 @@ -/************************************************************************************
- * arch/arm/src/str71x/str71x_emi.h
- *
- * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_STR71X_STR71X_EMI_H
-#define __ARCH_ARM_SRC_STR71X_STR71X_EMI_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-
-#include "str71x_map.h"
-
-/************************************************************************************
- * Pre-procesor Definitions
- ************************************************************************************/
-
-/* External Memory Interfac (EMI) register offset ***********************************/
-
-#define STR71X_EMI_BCON0_OFFSET (0x0000) /* 16-bits wide */
-#define STR71X_EMI_BCON1_OFFSET (0x0004) /* 16-bits wide */
-#define STR71X_EMI_BCON2_OFFSET (0x0008) /* 16-bits wide */
-#define STR71X_EMI_BCON3_OFFSET (0x000c) /* 16-bits wide */
-
-/* External Memory Interfac (EMI) register addresses ********************************/
-
-#define STR71X_EMI_BCON0 (STR71X_EMI_BASE + STR71X_EMI_BCON0_OFFSET)
-#define STR71X_EMI_BCON1 (STR71X_EMI_BASE + STR71X_EMI_BCON1_OFFSET)
-#define STR71X_EMI_BCON2 (STR71X_EMI_BASE + STR71X_EMI_BCON2_OFFSET)
-#define STR71X_EMI_BCON3 (STR71X_EMI_BASE + STR71X_EMI_BCON3_OFFSET)
-
-/* Register bit settings ***********************************************************/
-
-/* Bank-N configuration register (BCONn) bit definitions */
-
-#define STR71X_EMIBCON_BSIZEMASK (0x0003) /* Bits 0-1: Bank size */
-#define STR71X_EMIBCON_BSIZE8 (0x0000) /* 8-bit */
-#define STR71X_EMIBCON_BSIZE16 (0x0001) /* 16-bit */
-#define STR71X_EMIBCON_WSMASK (0x003c) /* Bits 2-5: Wait states */
-#define STR71X_EMIBCON_WS0 (0x0000) /* 0 waitstates */
-#define STR71X_EMIBCON_WS1 (0x0004) /* 1 waitstates */
-#define STR71X_EMIBCON_WS2 (0x0008) /* 2 waitstates */
-#define STR71X_EMIBCON_WS3 (0x000c) /* 3 waitstates */
-#define STR71X_EMIBCON_WS4 (0x0010) /* 4 waitstates */
-#define STR71X_EMIBCON_WS5 (0x0014) /* 5 waitstates */
-#define STR71X_EMIBCON_WS6 (0x0018) /* 6 waitstates */
-#define STR71X_EMIBCON_WS7 (0x001c) /* 7 waitstates */
-#define STR71X_EMIBCON_WS8 (0x0020) /* 8 waitstates */
-#define STR71X_EMIBCON_WS9 (0x0024) /* 9 waitstates */
-#define STR71X_EMIBCON_WS10 (0x0028) /* 10 waitstates */
-#define STR71X_EMIBCON_WS11 (0x002c) /* 11 waitstates */
-#define STR71X_EMIBCON_WS12 (0x0030) /* 12 waitstates */
-#define STR71X_EMIBCON_WS13 (0x0034) /* 13 waitstates */
-#define STR71X_EMIBCON_WS14 (0x0038) /* 14 waitstates */
-#define STR71X_EMIBCON_WS15 (0x003c) /* 15 waitstates */
-#define STR71X_EMIBCON_ENABLE (0x8000) /* Bit 15: Bank enable */
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-/************************************************************************************
- * Public Functions
- ************************************************************************************/
-
-#endif /* __ARCH_ARM_SRC_STR71X_STR71X_EMI_H */
+/************************************************************************************ + * arch/arm/src/str71x/str71x_emi.h + * + * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STR71X_STR71X_EMI_H +#define __ARCH_ARM_SRC_STR71X_STR71X_EMI_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +#include "str71x_map.h" + +/************************************************************************************ + * Pre-procesor Definitions + ************************************************************************************/ + +/* External Memory Interfac (EMI) register offset ***********************************/ + +#define STR71X_EMI_BCON0_OFFSET (0x0000) /* 16-bits wide */ +#define STR71X_EMI_BCON1_OFFSET (0x0004) /* 16-bits wide */ +#define STR71X_EMI_BCON2_OFFSET (0x0008) /* 16-bits wide */ +#define STR71X_EMI_BCON3_OFFSET (0x000c) /* 16-bits wide */ + +/* External Memory Interfac (EMI) register addresses ********************************/ + +#define STR71X_EMI_BCON0 (STR71X_EMI_BASE + STR71X_EMI_BCON0_OFFSET) +#define STR71X_EMI_BCON1 (STR71X_EMI_BASE + STR71X_EMI_BCON1_OFFSET) +#define STR71X_EMI_BCON2 (STR71X_EMI_BASE + STR71X_EMI_BCON2_OFFSET) +#define STR71X_EMI_BCON3 (STR71X_EMI_BASE + STR71X_EMI_BCON3_OFFSET) + +/* Register bit settings ***********************************************************/ + +/* Bank-N configuration register (BCONn) bit definitions */ + +#define STR71X_EMIBCON_BSIZEMASK (0x0003) /* Bits 0-1: Bank size */ +#define STR71X_EMIBCON_BSIZE8 (0x0000) /* 8-bit */ +#define STR71X_EMIBCON_BSIZE16 (0x0001) /* 16-bit */ +#define STR71X_EMIBCON_WSMASK (0x003c) /* Bits 2-5: Wait states */ +#define STR71X_EMIBCON_WS0 (0x0000) /* 0 waitstates */ +#define STR71X_EMIBCON_WS1 (0x0004) /* 1 waitstates */ +#define STR71X_EMIBCON_WS2 (0x0008) /* 2 waitstates */ +#define STR71X_EMIBCON_WS3 (0x000c) /* 3 waitstates */ +#define STR71X_EMIBCON_WS4 (0x0010) /* 4 waitstates */ +#define STR71X_EMIBCON_WS5 (0x0014) /* 5 waitstates */ +#define STR71X_EMIBCON_WS6 (0x0018) /* 6 waitstates */ +#define STR71X_EMIBCON_WS7 (0x001c) /* 7 waitstates */ +#define STR71X_EMIBCON_WS8 (0x0020) /* 8 waitstates */ +#define STR71X_EMIBCON_WS9 (0x0024) /* 9 waitstates */ +#define STR71X_EMIBCON_WS10 (0x0028) /* 10 waitstates */ +#define STR71X_EMIBCON_WS11 (0x002c) /* 11 waitstates */ +#define STR71X_EMIBCON_WS12 (0x0030) /* 12 waitstates */ +#define STR71X_EMIBCON_WS13 (0x0034) /* 13 waitstates */ +#define STR71X_EMIBCON_WS14 (0x0038) /* 14 waitstates */ +#define STR71X_EMIBCON_WS15 (0x003c) /* 15 waitstates */ +#define STR71X_EMIBCON_ENABLE (0x8000) /* Bit 15: Bank enable */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_STR71X_STR71X_EMI_H */ diff --git a/nuttx/arch/arm/src/str71x/str71x_flash.h b/nuttx/arch/arm/src/str71x/str71x_flash.h index 352972d48..9b45fa3e9 100644 --- a/nuttx/arch/arm/src/str71x/str71x_flash.h +++ b/nuttx/arch/arm/src/str71x/str71x_flash.h @@ -1,123 +1,123 @@ -/************************************************************************************
- * arch/arm/src/str71x/str71x_flash.h
- *
- * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_STR71X_STR71X_FLASH_H
-#define __ARCH_ARM_SRC_STR71X_STR71X_FLASH_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-
-#include "str71x_map.h"
-
-/************************************************************************************
- * Pre-procesor Definitions
- ************************************************************************************/
-
-/* Flash registers ******************************************************************/
-
-#define STR71X_FLASH_CR0 (STR71X_FLASHREG_BASE + 0x0000) /* 32-bits wide */
-#define STR71X_FLASH_CR1 (STR71X_FLASHREG_BASE + 0x0004) /* 32-bits wide */
-#define STR71X_FLASH_DR0 (STR71X_FLASHREG_BASE + 0x0008) /* 32-bits wide */
-#define STR71X_FLASH_DR1 (STR71X_FLASHREG_BASE + 0x000c) /* 32-bits wide */
-#define STR71X_FLASH_AR (STR71X_FLASHREG_BASE + 0x0010) /* 32-bits wide */
-#define STR71X_FLASH_ER (STR71X_FLASHREG_BASE + 0x0014) /* 32-bits wide */
-
-/* Register bit settings ************************************************************/
-
-#define STR71X_FLASH_B0F0 (0x00000001)
-#define STR71X_FLASH_B0F1 (0x00000002)
-#define STR71X_FLASH_B0F2 (0x00000004)
-#define STR71X_FLASH_B0F3 (0x00000008)
-#define STR71X_FLASH_B0F4 (0x00000010)
-#define STR71X_FLASH_B0F5 (0x00000020)
-#define STR71X_FLASH_B0F6 (0x00000040)
-#define STR71X_FLASH_B0F7 (0x00000080)
-
-#define STR71X_FLASH_B1F0 (0x00010000)
-#define STR71X_FLASH_B1F1 (0x00020000)
-
-#define STR71X_FLASH_B0 (STR71X_FLASH_B0F0|STR71X_FLASH_B0F1|\
- STR71X_FLASH_B0F2|STR71X_FLASH_B0F3|\
- STR71X_FLASH_B0F4|STR71X_FLASH_B0F5|\
- STR71X_FLASH_B0F6| STR71X_FLASH_B0F7)
-#define STR71X_FLASH_B1 (STR71X_FLASH_B1F0|STR71X_FLASH_B1F1)
-
-#define STR71X_FLASH_BANK0 (0x1000000)
-#define STR71X_FLASH_BANK1 (0x2000000)
-
-#define STR71X_FLASH_BSYA0 (0x01) /* 000-00001 (0000 0001 (0x01 */ /* STR71X_FLASH_CR0.1 */
-#define STR71X_FLASH_BSYA1 (0x02) /* 000-00010 (0000 0010 (0x02 */ /* STR71X_FLASH_CR0.2 */
-#define STR71X_FLASH_LOCK (0x04) /* 000-00100 (0000 0100 (0x04 */ /* STR71X_FLASH_CR0.4 */
-#define STR71X_FLASH_INTP (0x14) /* 000-10100 (0001 0100 (0x14 */ /* STR71X_FLASH_CR0.20 */
-#define STR71X_FLASH_B0S (0x38) /* 001-11000 (0011 1000 (0x38 */ /* STR71X_FLASH_CR1.24 */
-#define STR71X_FLASH_B1S (0x39) /* 001-11001 (0011 1001 (0x39 */ /* STR71X_FLASH_CR1.25 */
-#define STR71X_FLASH_ERR (0xa0) /* 101-00000 (1010 0000 (0xA0 */ /* STR71X_FLASH_ER.0 */
-#define STR71X_FLASH_ERER (0xa1) /* 101-00001 (1010 0001 (0xA1 */ /* STR71X_FLASH_ER.1 */
-#define STR71X_FLASH_PGER (0xa2) /* 101-00010 (1010 0010 (0xA2 */ /* STR71X_FLASH_ER.2 */
-#define STR71X_FLASH_10ER (0xa3) /* 101-00011 (1010 0011 (0xA3 */ /* STR71X_FLASH_ER.3 */
-#define STR71X_FLASH_SEQER (0xa6) /* 101-00110 (1010 0110 (0xA6 */ /* STR71X_FLASH_ER.6 */
-#define STR71X_FLASH_RESER (0xa7) /* 101-00111 (1010 0111 (0xA7 */ /* STR71X_FLASH_ER.7 */
-#define STR71X_FLASH_WPF (0xa8) /* 101-01000 (1010 1000 (0xA8 */ /* STR71X_FLASH_ER.8 */
-
-#define STR71X_FLASH_WMS_MASK (0x80000000)
-#define STR71X_FLASH_SUSP_MASK (0x40000000)
-#define STR71X_FLASH_WPG_MASK (0x20000000)
-#define STR71X_FLASH_DWPG_MASK (0x10000000)
-#define STR71X_FLASH_SER_MASK (0x08000000)
-#define STR71X_FLASH_SPR_MASK (0x01000000)
-#define STR71X_FLASH_DBGP_MASK (0x00000002)
-#define STR71X_FLASH_ACCP_MASK (0x00000001)
-
-#define STR71X_FLASH_Reg_Mask (0xe0)
-#define STR71X_FLASH_Flag_Mask (0x1f)
-
-#define STR71X_FLASH_INTM_Mask (0x00200000)
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-/************************************************************************************
- * Public Functions
- ************************************************************************************/
-
-#endif /* __ARCH_ARM_SRC_STR71X_STR71X_FLASH_H */
+/************************************************************************************ + * arch/arm/src/str71x/str71x_flash.h + * + * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STR71X_STR71X_FLASH_H +#define __ARCH_ARM_SRC_STR71X_STR71X_FLASH_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +#include "str71x_map.h" + +/************************************************************************************ + * Pre-procesor Definitions + ************************************************************************************/ + +/* Flash registers ******************************************************************/ + +#define STR71X_FLASH_CR0 (STR71X_FLASHREG_BASE + 0x0000) /* 32-bits wide */ +#define STR71X_FLASH_CR1 (STR71X_FLASHREG_BASE + 0x0004) /* 32-bits wide */ +#define STR71X_FLASH_DR0 (STR71X_FLASHREG_BASE + 0x0008) /* 32-bits wide */ +#define STR71X_FLASH_DR1 (STR71X_FLASHREG_BASE + 0x000c) /* 32-bits wide */ +#define STR71X_FLASH_AR (STR71X_FLASHREG_BASE + 0x0010) /* 32-bits wide */ +#define STR71X_FLASH_ER (STR71X_FLASHREG_BASE + 0x0014) /* 32-bits wide */ + +/* Register bit settings ************************************************************/ + +#define STR71X_FLASH_B0F0 (0x00000001) +#define STR71X_FLASH_B0F1 (0x00000002) +#define STR71X_FLASH_B0F2 (0x00000004) +#define STR71X_FLASH_B0F3 (0x00000008) +#define STR71X_FLASH_B0F4 (0x00000010) +#define STR71X_FLASH_B0F5 (0x00000020) +#define STR71X_FLASH_B0F6 (0x00000040) +#define STR71X_FLASH_B0F7 (0x00000080) + +#define STR71X_FLASH_B1F0 (0x00010000) +#define STR71X_FLASH_B1F1 (0x00020000) + +#define STR71X_FLASH_B0 (STR71X_FLASH_B0F0|STR71X_FLASH_B0F1|\ + STR71X_FLASH_B0F2|STR71X_FLASH_B0F3|\ + STR71X_FLASH_B0F4|STR71X_FLASH_B0F5|\ + STR71X_FLASH_B0F6| STR71X_FLASH_B0F7) +#define STR71X_FLASH_B1 (STR71X_FLASH_B1F0|STR71X_FLASH_B1F1) + +#define STR71X_FLASH_BANK0 (0x1000000) +#define STR71X_FLASH_BANK1 (0x2000000) + +#define STR71X_FLASH_BSYA0 (0x01) /* 000-00001 (0000 0001 (0x01 */ /* STR71X_FLASH_CR0.1 */ +#define STR71X_FLASH_BSYA1 (0x02) /* 000-00010 (0000 0010 (0x02 */ /* STR71X_FLASH_CR0.2 */ +#define STR71X_FLASH_LOCK (0x04) /* 000-00100 (0000 0100 (0x04 */ /* STR71X_FLASH_CR0.4 */ +#define STR71X_FLASH_INTP (0x14) /* 000-10100 (0001 0100 (0x14 */ /* STR71X_FLASH_CR0.20 */ +#define STR71X_FLASH_B0S (0x38) /* 001-11000 (0011 1000 (0x38 */ /* STR71X_FLASH_CR1.24 */ +#define STR71X_FLASH_B1S (0x39) /* 001-11001 (0011 1001 (0x39 */ /* STR71X_FLASH_CR1.25 */ +#define STR71X_FLASH_ERR (0xa0) /* 101-00000 (1010 0000 (0xA0 */ /* STR71X_FLASH_ER.0 */ +#define STR71X_FLASH_ERER (0xa1) /* 101-00001 (1010 0001 (0xA1 */ /* STR71X_FLASH_ER.1 */ +#define STR71X_FLASH_PGER (0xa2) /* 101-00010 (1010 0010 (0xA2 */ /* STR71X_FLASH_ER.2 */ +#define STR71X_FLASH_10ER (0xa3) /* 101-00011 (1010 0011 (0xA3 */ /* STR71X_FLASH_ER.3 */ +#define STR71X_FLASH_SEQER (0xa6) /* 101-00110 (1010 0110 (0xA6 */ /* STR71X_FLASH_ER.6 */ +#define STR71X_FLASH_RESER (0xa7) /* 101-00111 (1010 0111 (0xA7 */ /* STR71X_FLASH_ER.7 */ +#define STR71X_FLASH_WPF (0xa8) /* 101-01000 (1010 1000 (0xA8 */ /* STR71X_FLASH_ER.8 */ + +#define STR71X_FLASH_WMS_MASK (0x80000000) +#define STR71X_FLASH_SUSP_MASK (0x40000000) +#define STR71X_FLASH_WPG_MASK (0x20000000) +#define STR71X_FLASH_DWPG_MASK (0x10000000) +#define STR71X_FLASH_SER_MASK (0x08000000) +#define STR71X_FLASH_SPR_MASK (0x01000000) +#define STR71X_FLASH_DBGP_MASK (0x00000002) +#define STR71X_FLASH_ACCP_MASK (0x00000001) + +#define STR71X_FLASH_Reg_Mask (0xe0) +#define STR71X_FLASH_Flag_Mask (0x1f) + +#define STR71X_FLASH_INTM_Mask (0x00200000) + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_STR71X_STR71X_FLASH_H */ diff --git a/nuttx/arch/arm/src/str71x/str71x_gpio.h b/nuttx/arch/arm/src/str71x/str71x_gpio.h index dbcd3cdeb..16b325613 100644 --- a/nuttx/arch/arm/src/str71x/str71x_gpio.h +++ b/nuttx/arch/arm/src/str71x/str71x_gpio.h @@ -1,94 +1,94 @@ -/************************************************************************************
- * arch/arm/src/str71x/str71x_gpio.h
- *
- * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_STR71X_STR71X_GPIO_H
-#define __ARCH_ARM_SRC_STR71X_STR71X_GPIO_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-
-#include "str71x_map.h"
-
-/************************************************************************************
- * Pre-procesor Definitions
- ************************************************************************************/
-
-/* GPIO register offsets ************************************************************/
-
-#define STR71X_GPIO_PC0_OFFSET (0x0000) /* 16-bits wide */
-#define STR71X_GPIO_PC1_OFFSET (0x0004) /* 16-bits wide */
-#define STR71X_GPIO_PC2_OFFSET (0x0008) /* 16-bits wide */
-#define STR71X_GPIO_PD_OFFSET (0x000c) /* 16-bits wide */
-
-/* GPIO register addresses **********************************************************/
-
-#define STR71X_GPIO_PC0(b) ((b) + STR71X_GPIO_PC0_OFFSET)
-#define STR71X_GPIO_PC1(b) ((b) + STR71X_GPIO_PC1_OFFSET)
-#define STR71X_GPIO_PC2(b) ((b) + STR71X_GPIO_PC2_OFFSET)
-#define STR71X_GPIO_PD(b) ((b) + STR71X_GPIO_PD_OFFSET)
-
-#define STR71X_GPIO0_PC0 (STR71X_GPIO0_BASE + STR71X_GPIO_PC0_OFFSET)
-#define STR71X_GPIO0_PC1 (STR71X_GPIO0_BASE + STR71X_GPIO_PC1_OFFSET)
-#define STR71X_GPIO0_PC2 (STR71X_GPIO0_BASE + STR71X_GPIO_PC2_OFFSET)
-#define STR71X_GPIO0_PD (STR71X_GPIO0_BASE + STR71X_GPIO_PD_OFFSET)
-
-#define STR71X_GPIO1_PC0 (STR71X_GPIO1_BASE + STR71X_GPIO_PC0_OFFSET)
-#define STR71X_GPIO1_PC1 (STR71X_GPIO1_BASE + STR71X_GPIO_PC1_OFFSET)
-#define STR71X_GPIO1_PC2 (STR71X_GPIO1_BASE + STR71X_GPIO_PC2_OFFSET)
-#define STR71X_GPIO1_PD (STR71X_GPIO1_BASE + STR71X_GPIO_PD_OFFSET)
-
-#define STR71X_GPIO2_PC0 (STR71X_GPIO2_BASE + STR71X_GPIO_PC0_OFFSET)
-#define STR71X_GPIO2_PC1 (STR71X_GPIO2_BASE + STR71X_GPIO_PC1_OFFSET)
-#define STR71X_GPIO2_PC2 (STR71X_GPIO2_BASE + STR71X_GPIO_PC2_OFFSET)
-#define STR71X_GPIO2_PD (STR71X_GPIO2_BASE + STR71X_GPIO_PD_OFFSET)
-
-/* Register bit settings ************************************************************/
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-/************************************************************************************
- * Public Functions
- ************************************************************************************/
-
-#endif /* __ARCH_ARM_SRC_STR71X_STR71X_GPIO_H */
+/************************************************************************************ + * arch/arm/src/str71x/str71x_gpio.h + * + * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STR71X_STR71X_GPIO_H +#define __ARCH_ARM_SRC_STR71X_STR71X_GPIO_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +#include "str71x_map.h" + +/************************************************************************************ + * Pre-procesor Definitions + ************************************************************************************/ + +/* GPIO register offsets ************************************************************/ + +#define STR71X_GPIO_PC0_OFFSET (0x0000) /* 16-bits wide */ +#define STR71X_GPIO_PC1_OFFSET (0x0004) /* 16-bits wide */ +#define STR71X_GPIO_PC2_OFFSET (0x0008) /* 16-bits wide */ +#define STR71X_GPIO_PD_OFFSET (0x000c) /* 16-bits wide */ + +/* GPIO register addresses **********************************************************/ + +#define STR71X_GPIO_PC0(b) ((b) + STR71X_GPIO_PC0_OFFSET) +#define STR71X_GPIO_PC1(b) ((b) + STR71X_GPIO_PC1_OFFSET) +#define STR71X_GPIO_PC2(b) ((b) + STR71X_GPIO_PC2_OFFSET) +#define STR71X_GPIO_PD(b) ((b) + STR71X_GPIO_PD_OFFSET) + +#define STR71X_GPIO0_PC0 (STR71X_GPIO0_BASE + STR71X_GPIO_PC0_OFFSET) +#define STR71X_GPIO0_PC1 (STR71X_GPIO0_BASE + STR71X_GPIO_PC1_OFFSET) +#define STR71X_GPIO0_PC2 (STR71X_GPIO0_BASE + STR71X_GPIO_PC2_OFFSET) +#define STR71X_GPIO0_PD (STR71X_GPIO0_BASE + STR71X_GPIO_PD_OFFSET) + +#define STR71X_GPIO1_PC0 (STR71X_GPIO1_BASE + STR71X_GPIO_PC0_OFFSET) +#define STR71X_GPIO1_PC1 (STR71X_GPIO1_BASE + STR71X_GPIO_PC1_OFFSET) +#define STR71X_GPIO1_PC2 (STR71X_GPIO1_BASE + STR71X_GPIO_PC2_OFFSET) +#define STR71X_GPIO1_PD (STR71X_GPIO1_BASE + STR71X_GPIO_PD_OFFSET) + +#define STR71X_GPIO2_PC0 (STR71X_GPIO2_BASE + STR71X_GPIO_PC0_OFFSET) +#define STR71X_GPIO2_PC1 (STR71X_GPIO2_BASE + STR71X_GPIO_PC1_OFFSET) +#define STR71X_GPIO2_PC2 (STR71X_GPIO2_BASE + STR71X_GPIO_PC2_OFFSET) +#define STR71X_GPIO2_PD (STR71X_GPIO2_BASE + STR71X_GPIO_PD_OFFSET) + +/* Register bit settings ************************************************************/ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_STR71X_STR71X_GPIO_H */ diff --git a/nuttx/arch/arm/src/str71x/str71x_i2c.h b/nuttx/arch/arm/src/str71x/str71x_i2c.h index 8a0cd498f..759c75e7e 100644 --- a/nuttx/arch/arm/src/str71x/str71x_i2c.h +++ b/nuttx/arch/arm/src/str71x/str71x_i2c.h @@ -1,153 +1,153 @@ -/************************************************************************************
- * arch/arm/src/str71x/str71x_i2c.h
- *
- * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_STR71X_STR71X_I2C_H
-#define __ARCH_ARM_SRC_STR71X_STR71X_I2C_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-
-#include "str71x_map.h"
-
-/************************************************************************************
- * Pre-procesor Definitions
- ************************************************************************************/
-
-/* Register offets ******************************************************************/
-
-#define STR71X_I2C_CR_OFFSET (0x0000) /* 8-bits wide */
-#define STR71X_I2C_SR1_OFFSET (0x0004) /* 8-bits wide */
-#define STR71X_I2C_SR2_OFFSET (0x0008) /* 8-bits wide */
-#define STR71X_I2C_CCR_OFFSET (0x000c) /* 8-bits wide */
-#define STR71X_I2C_OAR1_OFFSET (0x0010) /* 8-bits wide */
-#define STR71X_I2C_OAR2_OFFSET (0x0014) /* 8-bits wide */
-#define STR71X_I2C_DR_OFFSET (0x0018) /* 8-bits wide */
-#define STR71X_I2C_ECCR_OFFSET (0x001c) /* 8-bits wide */
-
-/* Registers ************************************************************************/
-
-#define STR71X_I2C_CR(b) ((b) + STR71X_I2C_SR_OFFSET)
-#define STR71X_I2C_SR1(b) ((b) + STR71X_I2C_SR1_OFFSET)
-#define STR71X_I2C_SR2(b) ((b) + STR71X_I2C_SR2_OFFSET)
-#define STR71X_I2C_CCR(b) ((b) + STR71X_I2C_CCR_OFFSET)
-#define STR71X_I2C_OAR1(b) ((b) + STR71X_I2C_OAR1_OFFSET)
-#define STR71X_I2C_OAR2(b) ((b) + STR71X_I2C_OAR2_OFFSET)
-#define STR71X_I2C_DR(b) ((b) + STR71X_I2C_DR_OFFSET)
-#define STR71X_I2C_ECCR(b) ((b) + STR71X_I2C_ECCR_OFFSET)
-
-#define STR71X_I2C0_CR (STR71X_I2C0_BASE + STR71X_I2C_SR_OFFSET)
-#define STR71X_I2C0_SR1 (STR71X_I2C0_BASE + STR71X_I2C_SR1_OFFSET)
-#define STR71X_I2C0_SR2 (STR71X_I2C0_BASE + STR71X_I2C_SR2_OFFSET)
-#define STR71X_I2C0_CCR (STR71X_I2C0_BASE + STR71X_I2C_CCR_OFFSET)
-#define STR71X_I2C0_OAR1 (STR71X_I2C0_BASE + STR71X_I2C_OAR1_OFFSET)
-#define STR71X_I2C0_OAR2 (STR71X_I2C0_BASE + STR71X_I2C_OAR2_OFFSET)
-#define STR71X_I2C0_DR (STR71X_I2C0_BASE + STR71X_I2C_DR_OFFSET)
-#define STR71X_I2C0_ECCR (STR71X_I2C0_BASE + STR71X_I2C_ECCR_OFFSET)
-
-#define STR71X_I2C1_CR (STR71X_I2C1_BASE + STR71X_I2C_SR_OFFSET)
-#define STR71X_I2C1_SR1 (STR71X_I2C1_BASE + STR71X_I2C_SR1_OFFSET)
-#define STR71X_I2C1_SR2 (STR71X_I2C1_BASE + STR71X_I2C_SR2_OFFSET)
-#define STR71X_I2C1_CCR (STR71X_I2C1_BASE + STR71X_I2C_CCR_OFFSET)
-#define STR71X_I2C1_OAR1 (STR71X_I2C1_BASE + STR71X_I2C_OAR1_OFFSET)
-#define STR71X_I2C1_OAR2 (STR71X_I2C1_BASE + STR71X_I2C_OAR2_OFFSET)
-#define STR71X_I2C1_DR (STR71X_I2C1_BASE + STR71X_I2C_DR_OFFSET)
-#define STR71X_I2C1_ECCR (STR71X_I2C1_BASE + STR71X_I2C_ECCR_OFFSET)
-
-/* Register bit settings ***********************************************************/
-
-/* I2C Control Register (CR) */
-
-#define STR71X_I2CCR_ITE (0x01) /* Bit 0: Interrupt enable */
-#define STR71X_I2CCR_STOP (0x02) /* Bit 1: Generation of a stop condition */
-#define STR71X_I2CCR_ACK (0x04) /* Bit 2: Acknowledge enable */
-#define STR71X_I2CCR_START (0x08) /* Bit 3: Generation of a start condition */
-#define STR71X_I2CCR_ENGC (0x10) /* Bit 4: Enable general call */
-#define STR71X_I2CCR_PE (0x20) /* Bit 5: Peripheral enable */
-
-/* I2C Status Register 1 (SR1) */
-
-#define STR71X_I2CSR1_SB (0x01) /* Bit 0: Start bit (master mode) */
-#define STR71X_I2CSR1_MSL (0x02) /* Bit 1: Master/slave */
-#define STR71X_I2CSR1_ADSL (0x04) /* Bit 2: Address matched */
-#define STR71X_I2CSR1_BTF (0x08) /* Bit 3: Byte transfer finished */
-#define STR71X_I2CSR1_BUSY (0x10) /* Bit 4: Bus busy */
-#define STR71X_I2CSR1_TRA (0x20) /* Bit 5: Transmitter/receiver */
-#define STR71X_I2CSR1_ADD10 (0x40) /* Bit 6: 10-bit addressing in master mode */
-#define STR71X_I2CSR1_EVF (0x80) /* Bit 7: Event flag */
-
-/* I2C Status Register 2 (SR2) */
-
-#define STR71X_I2CSR2_GCAL (0x01) /* Bit 0: General call (slave mode) */
-#define STR71X_I2CSR2_BERR (0x02) /* Bit 1: Bus error */
-#define STR71X_I2CSR2_ARLO (0x04) /* Bit 2: Arbitration lost */
-#define STR71X_I2CSR2_STOPF (0x08) /* Bit 3: Stop detection (slave mode) */
-#define STR71X_I2CSR2_AF (0x10) /* Bit 4: Acknowledge failure */
-#define STR71X_I2CSR2_ENDAD (0x20) /* Bit 5: End of address transmission */
-
-/* I2C Clock Control Register (CCR) */
-
-#define STR71X_I2CCCR_DIVMASK (0x7f) /* Bits 0-6: 7 bits of the 12-bit clock divider */
-#define STR71X_I2CCCR_FMSM (0x80) /* Bit 7: Fast/standard I2C mode */
-
-/* I2C Extended Clock Control Register (ECCR) */
-
-#define STR71X_I2CECCR_DIVMASK (0x1f) /* Bits 0-5: 5 bits of the 12-bit clock divider */
-
-/* I2C Own Address Register 2 (OAR2) */
-
-#define STR71X_I2COAR2_ADDRMASK (0x06) /* Bits 1-2: 2 bits of the 10-bit interface address */
-#define STR71X_I2COAR2_FREQMASK (0xe0) /* Bits 5-7: Frequency */
-#define STR71X_I2COAR2_5_10 (0x00) /* FPCLK1 = 5 to 10 */
-#define STR71X_I2COAR2_10_16 (0x20) /* FPCLK1 = 10 to 16.67 */
-#define STR71X_I2COAR2_16_26 (0x40) /* FPCLK1 = 16.67 to 26.67 */
-#define STR71X_I2COAR2_26_40 (0x60) /* FPCLK1 = 26.67 to 40 */
-#define STR71X_I2COAR2_40_53 (0x80) /* FPCLK1 = 40 to 53.33 */
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-/************************************************************************************
- * Public Functions
- ************************************************************************************/
-
-#endif /* __ARCH_ARM_SRC_STR71X_STR71X_I2C_H */
+/************************************************************************************ + * arch/arm/src/str71x/str71x_i2c.h + * + * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STR71X_STR71X_I2C_H +#define __ARCH_ARM_SRC_STR71X_STR71X_I2C_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +#include "str71x_map.h" + +/************************************************************************************ + * Pre-procesor Definitions + ************************************************************************************/ + +/* Register offets ******************************************************************/ + +#define STR71X_I2C_CR_OFFSET (0x0000) /* 8-bits wide */ +#define STR71X_I2C_SR1_OFFSET (0x0004) /* 8-bits wide */ +#define STR71X_I2C_SR2_OFFSET (0x0008) /* 8-bits wide */ +#define STR71X_I2C_CCR_OFFSET (0x000c) /* 8-bits wide */ +#define STR71X_I2C_OAR1_OFFSET (0x0010) /* 8-bits wide */ +#define STR71X_I2C_OAR2_OFFSET (0x0014) /* 8-bits wide */ +#define STR71X_I2C_DR_OFFSET (0x0018) /* 8-bits wide */ +#define STR71X_I2C_ECCR_OFFSET (0x001c) /* 8-bits wide */ + +/* Registers ************************************************************************/ + +#define STR71X_I2C_CR(b) ((b) + STR71X_I2C_SR_OFFSET) +#define STR71X_I2C_SR1(b) ((b) + STR71X_I2C_SR1_OFFSET) +#define STR71X_I2C_SR2(b) ((b) + STR71X_I2C_SR2_OFFSET) +#define STR71X_I2C_CCR(b) ((b) + STR71X_I2C_CCR_OFFSET) +#define STR71X_I2C_OAR1(b) ((b) + STR71X_I2C_OAR1_OFFSET) +#define STR71X_I2C_OAR2(b) ((b) + STR71X_I2C_OAR2_OFFSET) +#define STR71X_I2C_DR(b) ((b) + STR71X_I2C_DR_OFFSET) +#define STR71X_I2C_ECCR(b) ((b) + STR71X_I2C_ECCR_OFFSET) + +#define STR71X_I2C0_CR (STR71X_I2C0_BASE + STR71X_I2C_SR_OFFSET) +#define STR71X_I2C0_SR1 (STR71X_I2C0_BASE + STR71X_I2C_SR1_OFFSET) +#define STR71X_I2C0_SR2 (STR71X_I2C0_BASE + STR71X_I2C_SR2_OFFSET) +#define STR71X_I2C0_CCR (STR71X_I2C0_BASE + STR71X_I2C_CCR_OFFSET) +#define STR71X_I2C0_OAR1 (STR71X_I2C0_BASE + STR71X_I2C_OAR1_OFFSET) +#define STR71X_I2C0_OAR2 (STR71X_I2C0_BASE + STR71X_I2C_OAR2_OFFSET) +#define STR71X_I2C0_DR (STR71X_I2C0_BASE + STR71X_I2C_DR_OFFSET) +#define STR71X_I2C0_ECCR (STR71X_I2C0_BASE + STR71X_I2C_ECCR_OFFSET) + +#define STR71X_I2C1_CR (STR71X_I2C1_BASE + STR71X_I2C_SR_OFFSET) +#define STR71X_I2C1_SR1 (STR71X_I2C1_BASE + STR71X_I2C_SR1_OFFSET) +#define STR71X_I2C1_SR2 (STR71X_I2C1_BASE + STR71X_I2C_SR2_OFFSET) +#define STR71X_I2C1_CCR (STR71X_I2C1_BASE + STR71X_I2C_CCR_OFFSET) +#define STR71X_I2C1_OAR1 (STR71X_I2C1_BASE + STR71X_I2C_OAR1_OFFSET) +#define STR71X_I2C1_OAR2 (STR71X_I2C1_BASE + STR71X_I2C_OAR2_OFFSET) +#define STR71X_I2C1_DR (STR71X_I2C1_BASE + STR71X_I2C_DR_OFFSET) +#define STR71X_I2C1_ECCR (STR71X_I2C1_BASE + STR71X_I2C_ECCR_OFFSET) + +/* Register bit settings ***********************************************************/ + +/* I2C Control Register (CR) */ + +#define STR71X_I2CCR_ITE (0x01) /* Bit 0: Interrupt enable */ +#define STR71X_I2CCR_STOP (0x02) /* Bit 1: Generation of a stop condition */ +#define STR71X_I2CCR_ACK (0x04) /* Bit 2: Acknowledge enable */ +#define STR71X_I2CCR_START (0x08) /* Bit 3: Generation of a start condition */ +#define STR71X_I2CCR_ENGC (0x10) /* Bit 4: Enable general call */ +#define STR71X_I2CCR_PE (0x20) /* Bit 5: Peripheral enable */ + +/* I2C Status Register 1 (SR1) */ + +#define STR71X_I2CSR1_SB (0x01) /* Bit 0: Start bit (master mode) */ +#define STR71X_I2CSR1_MSL (0x02) /* Bit 1: Master/slave */ +#define STR71X_I2CSR1_ADSL (0x04) /* Bit 2: Address matched */ +#define STR71X_I2CSR1_BTF (0x08) /* Bit 3: Byte transfer finished */ +#define STR71X_I2CSR1_BUSY (0x10) /* Bit 4: Bus busy */ +#define STR71X_I2CSR1_TRA (0x20) /* Bit 5: Transmitter/receiver */ +#define STR71X_I2CSR1_ADD10 (0x40) /* Bit 6: 10-bit addressing in master mode */ +#define STR71X_I2CSR1_EVF (0x80) /* Bit 7: Event flag */ + +/* I2C Status Register 2 (SR2) */ + +#define STR71X_I2CSR2_GCAL (0x01) /* Bit 0: General call (slave mode) */ +#define STR71X_I2CSR2_BERR (0x02) /* Bit 1: Bus error */ +#define STR71X_I2CSR2_ARLO (0x04) /* Bit 2: Arbitration lost */ +#define STR71X_I2CSR2_STOPF (0x08) /* Bit 3: Stop detection (slave mode) */ +#define STR71X_I2CSR2_AF (0x10) /* Bit 4: Acknowledge failure */ +#define STR71X_I2CSR2_ENDAD (0x20) /* Bit 5: End of address transmission */ + +/* I2C Clock Control Register (CCR) */ + +#define STR71X_I2CCCR_DIVMASK (0x7f) /* Bits 0-6: 7 bits of the 12-bit clock divider */ +#define STR71X_I2CCCR_FMSM (0x80) /* Bit 7: Fast/standard I2C mode */ + +/* I2C Extended Clock Control Register (ECCR) */ + +#define STR71X_I2CECCR_DIVMASK (0x1f) /* Bits 0-5: 5 bits of the 12-bit clock divider */ + +/* I2C Own Address Register 2 (OAR2) */ + +#define STR71X_I2COAR2_ADDRMASK (0x06) /* Bits 1-2: 2 bits of the 10-bit interface address */ +#define STR71X_I2COAR2_FREQMASK (0xe0) /* Bits 5-7: Frequency */ +#define STR71X_I2COAR2_5_10 (0x00) /* FPCLK1 = 5 to 10 */ +#define STR71X_I2COAR2_10_16 (0x20) /* FPCLK1 = 10 to 16.67 */ +#define STR71X_I2COAR2_16_26 (0x40) /* FPCLK1 = 16.67 to 26.67 */ +#define STR71X_I2COAR2_26_40 (0x60) /* FPCLK1 = 26.67 to 40 */ +#define STR71X_I2COAR2_40_53 (0x80) /* FPCLK1 = 40 to 53.33 */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_STR71X_STR71X_I2C_H */ diff --git a/nuttx/arch/arm/src/str71x/str71x_internal.h b/nuttx/arch/arm/src/str71x/str71x_internal.h index 99012ca9c..6e60a671c 100644 --- a/nuttx/arch/arm/src/str71x/str71x_internal.h +++ b/nuttx/arch/arm/src/str71x/str71x_internal.h @@ -1,156 +1,156 @@ -/************************************************************************************
- * arch/arm/src/str71x/str71x_internal.h
- *
- * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_STR71X_STR71X_INTERNAL_H
-#define __ARCH_ARM_SRC_STR71X_STR71X_INTERNAL_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-
-#include <stdbool.h>
-
-#include <arch/board/board.h>
-
-/************************************************************************************
- * Pre-procesor Definitions
- ************************************************************************************/
-
-/* Calculate the values of PCLK1 and PCLK2 from settings in board.h.
- *
- * Example:
- * STR71X_RCCU_MAIN_OSC = 4MHz (not divided by 2)
- * STR71X_CLK2 = 4MHz
- * STR71X_PLL1OUT = 16 * STR71X_CLK2 / 2 = 32MHz
- * CLK3 = 32MHz
- * RCLK = 32MHz
- * PCLK1 = 32MHz / 1 = 32MHz
- */
-
-/* PLL1OUT derives from Main OSC->CLK2 */
-
-#ifdef STR71X_PLL1IN_DIV2 /* CLK2 is input to PLL1 */
-# define STR71X_CLK2 (STR71X_RCCU_MAIN_OSC/2) /* CLK2 is OSC/2 */
-#else
-# define STR71X_CLK2 STR71X_RCCU_MAIN_OSC /* CLK2 is OSC */
-#endif
-
-#define STR71X_PLL1OUT ((STR71X_PLL1OUT_MUL * STR71X_CLK2) / STR71X_PLL1OUT_DIV)
-
-/* PLL2 OUT derives from HCLK */
-
-#define STR71X_PLL2OUT ((STR71X_PLL2OUT_MUL * STR71X_HCLK) / STR71X_PLL2OUT_DIV)
-
-/* Peripheral clocks derive from PLL1OUT->CLK3->RCLK->PCLK1/2 */
-
-#define STR71X_CLK3 STR71X_PLL1OUT /* CLK3 hard coded to be PLL1OUT */
-#define STR71X_RCLK STR71X_CLK3 /* RCLK hard coded to be CLK3 */
-#define STR71X_PCLK1 (STR71X_RCLK / STR71X_APB1_DIV) /* PCLK1 derives from RCLK */
-#define STR71X_PCLK2 (STR71X_RCLK / STR71X_APB2_DIV) /* PCLK2 derives from RCLK */
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-/************************************************************************************
- * Public Functions
- ************************************************************************************/
-
-/********************************************************************************
- * Name: str7x_xtiinitialize
- *
- * Description:
- * Configure XTI for operation. Note that the lines are not used as wake-up
- * sources in this implementation. Some extensions would be required for that
- * capability.
- *
- ********************************************************************************/
-
-#ifdef CONFIG_STR71X_XTI
-extern int str71x_xtiinitialize(void);
-#else
-# define str71x_xtiinitialize()
-#endif /* CONFIG_STR71X_XTI */
-
-/********************************************************************************
- * Name: str7x_xticonfig
- *
- * Description:
- * Configure an external line to provide interrupts. Interrupt is configured,
- * but disabled on return.
- *
- ********************************************************************************/
-
-#ifdef CONFIG_STR71X_XTI
-extern int str71x_xticonfig(int irq, bool rising);
-#else
-# define str71x_xticonfig(irq,rising)
-#endif /* CONFIG_STR71X_XTI */
-
-/****************************************************************************
- * Name: str71x_enable_xtiirq
- *
- * Description:
- * Enable an external interrupt.
- *
- ****************************************************************************/
-
-#ifdef CONFIG_STR71X_XTI
-extern void str71x_enable_xtiirq(int irq);
-#else
-# define str71x_enable_xtiirq(irq)
-#endif /* CONFIG_STR71X_XTI */
-
-/****************************************************************************
- * Name: str71x_disable_xtiirq
- *
- * Description:
- * Disable an external interrupt.
- *
- ****************************************************************************/
-
-#ifdef CONFIG_STR71X_XTI
-extern void str71x_disable_xtiirq(int irq);
-#else
-# define str71x_disable_xtiirq(irq)
-#endif /* CONFIG_STR71X_XTI */
-
-#endif /* __ARCH_ARM_SRC_STR71X_STR71X_INTERNAL_H */
+/************************************************************************************ + * arch/arm/src/str71x/str71x_internal.h + * + * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STR71X_STR71X_INTERNAL_H +#define __ARCH_ARM_SRC_STR71X_STR71X_INTERNAL_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +#include <stdbool.h> + +#include <arch/board/board.h> + +/************************************************************************************ + * Pre-procesor Definitions + ************************************************************************************/ + +/* Calculate the values of PCLK1 and PCLK2 from settings in board.h. + * + * Example: + * STR71X_RCCU_MAIN_OSC = 4MHz (not divided by 2) + * STR71X_CLK2 = 4MHz + * STR71X_PLL1OUT = 16 * STR71X_CLK2 / 2 = 32MHz + * CLK3 = 32MHz + * RCLK = 32MHz + * PCLK1 = 32MHz / 1 = 32MHz + */ + +/* PLL1OUT derives from Main OSC->CLK2 */ + +#ifdef STR71X_PLL1IN_DIV2 /* CLK2 is input to PLL1 */ +# define STR71X_CLK2 (STR71X_RCCU_MAIN_OSC/2) /* CLK2 is OSC/2 */ +#else +# define STR71X_CLK2 STR71X_RCCU_MAIN_OSC /* CLK2 is OSC */ +#endif + +#define STR71X_PLL1OUT ((STR71X_PLL1OUT_MUL * STR71X_CLK2) / STR71X_PLL1OUT_DIV) + +/* PLL2 OUT derives from HCLK */ + +#define STR71X_PLL2OUT ((STR71X_PLL2OUT_MUL * STR71X_HCLK) / STR71X_PLL2OUT_DIV) + +/* Peripheral clocks derive from PLL1OUT->CLK3->RCLK->PCLK1/2 */ + +#define STR71X_CLK3 STR71X_PLL1OUT /* CLK3 hard coded to be PLL1OUT */ +#define STR71X_RCLK STR71X_CLK3 /* RCLK hard coded to be CLK3 */ +#define STR71X_PCLK1 (STR71X_RCLK / STR71X_APB1_DIV) /* PCLK1 derives from RCLK */ +#define STR71X_PCLK2 (STR71X_RCLK / STR71X_APB2_DIV) /* PCLK2 derives from RCLK */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/******************************************************************************** + * Name: str7x_xtiinitialize + * + * Description: + * Configure XTI for operation. Note that the lines are not used as wake-up + * sources in this implementation. Some extensions would be required for that + * capability. + * + ********************************************************************************/ + +#ifdef CONFIG_STR71X_XTI +extern int str71x_xtiinitialize(void); +#else +# define str71x_xtiinitialize() +#endif /* CONFIG_STR71X_XTI */ + +/******************************************************************************** + * Name: str7x_xticonfig + * + * Description: + * Configure an external line to provide interrupts. Interrupt is configured, + * but disabled on return. + * + ********************************************************************************/ + +#ifdef CONFIG_STR71X_XTI +extern int str71x_xticonfig(int irq, bool rising); +#else +# define str71x_xticonfig(irq,rising) +#endif /* CONFIG_STR71X_XTI */ + +/**************************************************************************** + * Name: str71x_enable_xtiirq + * + * Description: + * Enable an external interrupt. + * + ****************************************************************************/ + +#ifdef CONFIG_STR71X_XTI +extern void str71x_enable_xtiirq(int irq); +#else +# define str71x_enable_xtiirq(irq) +#endif /* CONFIG_STR71X_XTI */ + +/**************************************************************************** + * Name: str71x_disable_xtiirq + * + * Description: + * Disable an external interrupt. + * + ****************************************************************************/ + +#ifdef CONFIG_STR71X_XTI +extern void str71x_disable_xtiirq(int irq); +#else +# define str71x_disable_xtiirq(irq) +#endif /* CONFIG_STR71X_XTI */ + +#endif /* __ARCH_ARM_SRC_STR71X_STR71X_INTERNAL_H */ diff --git a/nuttx/arch/arm/src/str71x/str71x_irq.c b/nuttx/arch/arm/src/str71x/str71x_irq.c index c5c359cdf..3bf870668 100644 --- a/nuttx/arch/arm/src/str71x/str71x_irq.c +++ b/nuttx/arch/arm/src/str71x/str71x_irq.c @@ -2,7 +2,7 @@ * arch/arm/src/st71x/st71x_irq.c * * Copyright (C) 2008-2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/str71x/str71x_lowputc.c b/nuttx/arch/arm/src/str71x/str71x_lowputc.c index a34b185c8..fde33adb4 100644 --- a/nuttx/arch/arm/src/str71x/str71x_lowputc.c +++ b/nuttx/arch/arm/src/str71x/str71x_lowputc.c @@ -2,7 +2,7 @@ * arch/arm/src/str71x/str71x_lowputc.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/str71x/str71x_map.h b/nuttx/arch/arm/src/str71x/str71x_map.h index ad29e4d8d..e61be9e3e 100644 --- a/nuttx/arch/arm/src/str71x/str71x_map.h +++ b/nuttx/arch/arm/src/str71x/str71x_map.h @@ -1,99 +1,99 @@ -/************************************************************************************
- * arch/arm/src/str71x/str71x_map.h
- *
- * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_STR71X_STR71X_MAP_H
-#define __ARCH_ARM_SRC_STR71X_STR71X_MAP_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-
-/************************************************************************************
- * Pre-procesor Definitions
- ************************************************************************************/
-
-/* Memory Map ***********************************************************************/
-
-#define STR71X_FLASHRAMEMI_BASE (0x00000000) /* Flash alias for booting */
-#define STR71X_RAM_BASE (0x20000000)
-#define STR71X_FLASH_BASE (0x40000000)
-#define STR71X_FLASHREG_BASE (0x40100000)
-#define STR71X_EXTMEM_BASE (0x60000000)
-#define STR71X_EMI_BASE (STR71X_EXTMEM_BASE + 0x0c000000)
-#define STR71X_RCCU_BASE (0xa0000000)
-#define STR71X_PCU_BASE (0xa0000040)
-#define STR71X_APB1_BASE (0xc0000000)
-#define STR71X_I2C0_BASE (STR71X_APB1_BASE + 0x1000)
-#define STR71X_I2C1_BASE (STR71X_APB1_BASE + 0x2000)
-#define STR71X_UART0_BASE (STR71X_APB1_BASE + 0x4000)
-#define STR71X_UART1_BASE (STR71X_APB1_BASE + 0x5000)
-#define STR71X_UART2_BASE (STR71X_APB1_BASE + 0x6000)
-#define STR71X_UART3_BASE (STR71X_APB1_BASE + 0x7000)
-#define STR71X_USBRAM_BASE (STR71X_APB1_BASE + 0x8000)
-#define STR71X_USB_BASE (STR71X_APB1_BASE + 0x8800)
-#define STR71X_CAN_BASE (STR71X_APB1_BASE + 0x9000)
-#define STR71X_BSPI0_BASE (STR71X_APB1_BASE + 0xa000)
-#define STR71X_BSPI1_BASE (STR71X_APB1_BASE + 0xb000)
-#define STR71X_HDLCRAM_BASE (STR71X_APB1_BASE + 0xe000)
-#define STR71X_APB2_BASE (0xe0000000)
-#define STR71X_XTI_BASE (STR71X_APB2_BASE + 0x1000)
-#define STR71X_GPIO0_BASE (STR71X_APB2_BASE + 0x3000)
-#define STR71X_GPIO1_BASE (STR71X_APB2_BASE + 0x4000)
-#define STR71X_GPIO2_BASE (STR71X_APB2_BASE + 0x5000)
-#define STR71X_ADC12_BASE (STR71X_APB2_BASE + 0x7000)
-#define STR71X_CLKOUT_BASE (STR71X_APB2_BASE + 0x8000)
-#define STR71X_TIMER0_BASE (STR71X_APB2_BASE + 0x9000)
-#define STR71X_TIMER1_BASE (STR71X_APB2_BASE + 0xa000)
-#define STR71X_TIMER2_BASE (STR71X_APB2_BASE + 0xb000)
-#define STR71X_TIMER3_BASE (STR71X_APB2_BASE + 0xc000)
-#define STR71X_RTC_BASE (STR71X_APB2_BASE + 0xd000)
-#define STR71X_WDOG_BASE (STR71X_APB2_BASE + 0xe000)
-#define STR71X_EIC_BASE (0xfffff800)
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-/************************************************************************************
- * Public Functions
- ************************************************************************************/
-
-#endif // __ARCH_ARM_SRC_STR71X_STR71X_MAP_H
+/************************************************************************************ + * arch/arm/src/str71x/str71x_map.h + * + * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STR71X_STR71X_MAP_H +#define __ARCH_ARM_SRC_STR71X_STR71X_MAP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +/************************************************************************************ + * Pre-procesor Definitions + ************************************************************************************/ + +/* Memory Map ***********************************************************************/ + +#define STR71X_FLASHRAMEMI_BASE (0x00000000) /* Flash alias for booting */ +#define STR71X_RAM_BASE (0x20000000) +#define STR71X_FLASH_BASE (0x40000000) +#define STR71X_FLASHREG_BASE (0x40100000) +#define STR71X_EXTMEM_BASE (0x60000000) +#define STR71X_EMI_BASE (STR71X_EXTMEM_BASE + 0x0c000000) +#define STR71X_RCCU_BASE (0xa0000000) +#define STR71X_PCU_BASE (0xa0000040) +#define STR71X_APB1_BASE (0xc0000000) +#define STR71X_I2C0_BASE (STR71X_APB1_BASE + 0x1000) +#define STR71X_I2C1_BASE (STR71X_APB1_BASE + 0x2000) +#define STR71X_UART0_BASE (STR71X_APB1_BASE + 0x4000) +#define STR71X_UART1_BASE (STR71X_APB1_BASE + 0x5000) +#define STR71X_UART2_BASE (STR71X_APB1_BASE + 0x6000) +#define STR71X_UART3_BASE (STR71X_APB1_BASE + 0x7000) +#define STR71X_USBRAM_BASE (STR71X_APB1_BASE + 0x8000) +#define STR71X_USB_BASE (STR71X_APB1_BASE + 0x8800) +#define STR71X_CAN_BASE (STR71X_APB1_BASE + 0x9000) +#define STR71X_BSPI0_BASE (STR71X_APB1_BASE + 0xa000) +#define STR71X_BSPI1_BASE (STR71X_APB1_BASE + 0xb000) +#define STR71X_HDLCRAM_BASE (STR71X_APB1_BASE + 0xe000) +#define STR71X_APB2_BASE (0xe0000000) +#define STR71X_XTI_BASE (STR71X_APB2_BASE + 0x1000) +#define STR71X_GPIO0_BASE (STR71X_APB2_BASE + 0x3000) +#define STR71X_GPIO1_BASE (STR71X_APB2_BASE + 0x4000) +#define STR71X_GPIO2_BASE (STR71X_APB2_BASE + 0x5000) +#define STR71X_ADC12_BASE (STR71X_APB2_BASE + 0x7000) +#define STR71X_CLKOUT_BASE (STR71X_APB2_BASE + 0x8000) +#define STR71X_TIMER0_BASE (STR71X_APB2_BASE + 0x9000) +#define STR71X_TIMER1_BASE (STR71X_APB2_BASE + 0xa000) +#define STR71X_TIMER2_BASE (STR71X_APB2_BASE + 0xb000) +#define STR71X_TIMER3_BASE (STR71X_APB2_BASE + 0xc000) +#define STR71X_RTC_BASE (STR71X_APB2_BASE + 0xd000) +#define STR71X_WDOG_BASE (STR71X_APB2_BASE + 0xe000) +#define STR71X_EIC_BASE (0xfffff800) + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif // __ARCH_ARM_SRC_STR71X_STR71X_MAP_H diff --git a/nuttx/arch/arm/src/str71x/str71x_pcu.h b/nuttx/arch/arm/src/str71x/str71x_pcu.h index 19050253e..5e23204f0 100644 --- a/nuttx/arch/arm/src/str71x/str71x_pcu.h +++ b/nuttx/arch/arm/src/str71x/str71x_pcu.h @@ -1,159 +1,159 @@ -/************************************************************************************
- * arch/arm/src/str71x/str71x_pcu.h
- *
- * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_STR71X_STR71X_PCU_H
-#define __ARCH_ARM_SRC_STR71X_STR71X_PCU_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-
-#include "str71x_map.h"
-
-/************************************************************************************
- * Pre-procesor Definitions
- ************************************************************************************/
-
-/* Power Control Unit (PCU) register offsets ****************************************/
-
-#define STR71X_PCU_MDIVR_OFFSET (0x0000) /* 16-bits wide */
-#define STR71X_PCU_PDIVR_OFFSET (0x0004) /* 16-bits wide */
-#define STR71X_PCU_RSTR_OFFSET (0x0008) /* 16-bits wide */
-#define STR71X_PCU_PLL2CR_OFFSET (0x000c) /* 16-bits wide */
-#define STR71X_PCU_BOOTCR_OFFSET (0x0010) /* 16-bits wide */
-#define STR71X_PCU_PWRCR_OFFSET (0x0014) /* 16-bits wide */
-
-/* Power Control Unit (PCU) register addresses **************************************/
-
-#define STR71X_PCU_MDIVR (STR71X_PCU_BASE + STR71X_PCU_MDIVR_OFFSET)
-#define STR71X_PCU_PDIVR (STR71X_PCU_BASE + STR71X_PCU_PDIVR_OFFSET)
-#define STR71X_PCU_RSTR (STR71X_PCU_BASE + STR71X_PCU_RSTR_OFFSET)
-#define STR71X_PCU_PLL2CR (STR71X_PCU_BASE + STR71X_PCU_PLL2CR_OFFSET)
-#define STR71X_PCU_BOOTCR (STR71X_PCU_BASE + STR71X_PCU_BOOTCR_OFFSET)
-#define STR71X_PCU_PWRCR (STR71X_PCU_BASE + STR71X_PCU_PWRCR_OFFSET)
-
-/* Register bit settings ************************************************************/
-
-/* PCU MDIVR register bit definitions */
-
-#define STR71X_PCUMDIVR_FACTMASK (0x0003) /* Bits 0-1: Division factor for main system clock */
-#define STR71X_PCUMDIVR_DIV1 (0x0000) /* MCLK = RCLK */
-#define STR71X_PCUMDIVR_DIV2 (0x0001) /* MCLK = RCLK / 2 */
-#define STR71X_PCUMDIVR_DIV4 (0x0002) /* MCLK = RCLK / 4 */
-#define STR71X_PCUMDIVR_DIV8 (0x0003) /* MCLK = RCLK / 8 */
-
-/* PCU PDIVR register bit definitions */
-
-#define STR71X_PCUPDIVR_FACT1MASK (0x0003) /* Bits 0-1: Division factor for APB1 peripherals */
-#define STR71X_PCUPDIVR_APB1DIV1 (0x0000) /* PCLK1 = RCLK */
-#define STR71X_PCUPDIVR_APB1DIV2 (0x0001) /* PCLK1 = RCLK / 2 */
-#define STR71X_PCUPDIVR_APB1DIV4 (0x0002) /* PCLK1 = RCLK / 4 */
-#define STR71X_PCUPDIVR_APB1DIV8 (0x0003) /* PCLK1 = RCLK / 8 */
-#define STR71X_PCUPDIVR_FACT2MASK (0x0300) /* Bits 8-9: Division factor for APB2 peripherals */
-#define STR71X_PCUPDIVR_APB2DIV1 (0x0000) /* PCLK2 = RCLK */
-#define STR71X_PCUPDIVR_APB2DIV2 (0x0100) /* PCLK2 = RCLK / 2 */
-#define STR71X_PCUPDIVR_APB2DIV4 (0x0200) /* PCLK2 = RCLK / 4 */
-#define STR71X_PCUPDIVR_APB2DIV8 (0x0300) /* PCLK2 = RCLK / 8 */
-
-/* PCU RSTR register bit definitions */
-
-#define STR71X_PCURSTR_EMIRESET (0x0004) /* Bit 2: EMI reset */
-
-/* PCU PLL2CR register bit definitions */
-
-#define STR71X_PCUPPL2CR_DXMASK (0x0007) /* Bits 0-2: PLL2 output clock divider */
-#define STR71X_PCUPPL2CR_DIV1 (0x0000) /* PLL2 / 1 */
-#define STR71X_PCUPPL2CR_DIV2 (0x0001) /* PLL2 / 2 */
-#define STR71X_PCUPPL2CR_DIV3 (0x0002) /* PLL2 / 3 */
-#define STR71X_PCUPPL2CR_DIV4 (0x0003) /* PLL2 / 4 */
-#define STR71X_PCUPPL2CR_DIV5 (0x0004) /* PLL2 / 5 */
-#define STR71X_PCUPPL2CR_DIV6 (0x0005) /* PLL2 / 6 */
-#define STR71X_PCUPPL2CR_DIV7 (0x0006) /* PLL2 / 7 */
-#define STR71X_PCUPPL2CR_OFF (0x0007) /* PLL2 OFF */
-#define STR71X_PCUPPL2CR_MXMASK (0x0030) /* Bits 4-5: PLL2 multiplier */
-#define STR71X_PCUPPL2CR_MUL20 (0x0000) /* CLK2 * 20 */
-#define STR71X_PCUPPL2CR_MUL12 (0x0010) /* CLK2 * 12 */
-#define STR71X_PCUPPL2CR_MUL28 (0x0020) /* CLK2 * 28 */
-#define STR71X_PCUPPL2CR_MUL16 (0x0030) /* CLK2 * 16 */
-#define STR71X_PCUPPL2CR_FRQRNG (0x0040) /* Bit 6: PLL2 frequency range selection */
-#define STR71X_PCUPPL2CR_PLLEN (0x0080) /* Bit 7: PLL2 enable */
-#define STR71X_PCUPPL2CR_USBEN (0x0100) /* Bit 8: Enable PLL clock to USB */
-#define STR71X_PCUPPL2CR_IRQMASK (0x0200) /* Bit 9: Enable interrupt request CPU on lock transition */
-#define STR71X_PCUPPL2CR_IRQPEND (0x0400) /* Bit 10: Interrtup request to CPU on lock transition pending */
-#define STR71X_PCUPPL2CR_LOCK (0x8000) /* Bit 15: PLL2 locked */
-
-/* PCU BOOTCR register bit definitions */
-
-#define STR71X_PCUBOOTCR_BOOTMASK (0x0003) /* Bits 0-1: Boot mode */
-#define STR71X_PCUBOOTCR_BMFLASH (0x0000) /* FLASH */
-#define STR71X_PCUBOOTCR_BMRAM (0x0002) /* RAM */
-#define STR71X_PCUBOOTCR_BMEXTMEM (0x0003) /* FLASH */
-#define STR71X_PCUBOOTCR_BSPIOEN (0x0004) /* Bit 2: Enable BSPI0 */
-#define STR71X_PCUBOOTCR_USBFILTEN (0x0008) /* Bit 3: Enable USB standby filtering */
-#define STR71X_PCUBOOTCR_LPOWDBGEN (0x0010) /* Bit 4: Enable reserved features for STOP mode */
-#define STR71X_PCUBOOTCR_ACDEN (0x0020) /* Bit 5: Enable ADC */
-#define STR71X_PCUBOOTCR_CANACTIVE (0x0040) /* Bit 6: CAN active */
-#define STR71X_PCUBOOTCR_HDLCACTIVE (0x0080) /* Bit 7: HDLC active */
-#define STR71X_PCUBOOTCR_PKG64 (0x0200) /* Bit 9: Die is hosted in 64-pin package */
-
-/* PCU PWRCR register bit definitions */
-
-#define STR71X_PCUPWRCR_VRBYP (0x0008) /* Bit 3: Main regulator bypass */
-#define STR71X_PCUPWRCR_LPRWFI (0x0010) /* Bit 4: Low power regulator in wait-for-interrupt mode */
-#define STR71X_PCUPWRCR_LPRBYP (0x0020) /* Bit 5: Low power regulator bypass */
-#define STR71X_PCUPWRCR_PWRDWN (0x0040) /* Bit 6: Activate standby mode */
-#define STR71X_PCUPWRCR_OSCBYP (0x0080) /* Bit 7: 32KHz oscillator bypass */
-#define STR71X_PCUPWRCR_LVDDIS (0x0100) /* Bit 8: Low voltage detector disable */
-#define STR71X_PCUPWRCR_FLASHLP (0x0200) /* Bit 9: FLASH low speed (low power) select */
-#define STR71X_PCUPWRCR_VROK (0x1000) /* Bit 12: Voltage regulator OK */
-#define STR71X_PCUPWRCR_WKUPALRM (0x2000) /* Bit 13: Wakeup or alarm active */
-#define STR71X_PCUPWRCR_BUSY (0x4000) /* Bit 14: PCU register backup logic busy */
-#define STR71X_PCUPWRCR_WREN (0x8000) /* Bit 15: PCU register write enable */
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-/************************************************************************************
- * Public Functions
- ************************************************************************************/
-
-#endif /* __ARCH_ARM_SRC_STR71X_STR71X_PCU_H */
+/************************************************************************************ + * arch/arm/src/str71x/str71x_pcu.h + * + * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STR71X_STR71X_PCU_H +#define __ARCH_ARM_SRC_STR71X_STR71X_PCU_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +#include "str71x_map.h" + +/************************************************************************************ + * Pre-procesor Definitions + ************************************************************************************/ + +/* Power Control Unit (PCU) register offsets ****************************************/ + +#define STR71X_PCU_MDIVR_OFFSET (0x0000) /* 16-bits wide */ +#define STR71X_PCU_PDIVR_OFFSET (0x0004) /* 16-bits wide */ +#define STR71X_PCU_RSTR_OFFSET (0x0008) /* 16-bits wide */ +#define STR71X_PCU_PLL2CR_OFFSET (0x000c) /* 16-bits wide */ +#define STR71X_PCU_BOOTCR_OFFSET (0x0010) /* 16-bits wide */ +#define STR71X_PCU_PWRCR_OFFSET (0x0014) /* 16-bits wide */ + +/* Power Control Unit (PCU) register addresses **************************************/ + +#define STR71X_PCU_MDIVR (STR71X_PCU_BASE + STR71X_PCU_MDIVR_OFFSET) +#define STR71X_PCU_PDIVR (STR71X_PCU_BASE + STR71X_PCU_PDIVR_OFFSET) +#define STR71X_PCU_RSTR (STR71X_PCU_BASE + STR71X_PCU_RSTR_OFFSET) +#define STR71X_PCU_PLL2CR (STR71X_PCU_BASE + STR71X_PCU_PLL2CR_OFFSET) +#define STR71X_PCU_BOOTCR (STR71X_PCU_BASE + STR71X_PCU_BOOTCR_OFFSET) +#define STR71X_PCU_PWRCR (STR71X_PCU_BASE + STR71X_PCU_PWRCR_OFFSET) + +/* Register bit settings ************************************************************/ + +/* PCU MDIVR register bit definitions */ + +#define STR71X_PCUMDIVR_FACTMASK (0x0003) /* Bits 0-1: Division factor for main system clock */ +#define STR71X_PCUMDIVR_DIV1 (0x0000) /* MCLK = RCLK */ +#define STR71X_PCUMDIVR_DIV2 (0x0001) /* MCLK = RCLK / 2 */ +#define STR71X_PCUMDIVR_DIV4 (0x0002) /* MCLK = RCLK / 4 */ +#define STR71X_PCUMDIVR_DIV8 (0x0003) /* MCLK = RCLK / 8 */ + +/* PCU PDIVR register bit definitions */ + +#define STR71X_PCUPDIVR_FACT1MASK (0x0003) /* Bits 0-1: Division factor for APB1 peripherals */ +#define STR71X_PCUPDIVR_APB1DIV1 (0x0000) /* PCLK1 = RCLK */ +#define STR71X_PCUPDIVR_APB1DIV2 (0x0001) /* PCLK1 = RCLK / 2 */ +#define STR71X_PCUPDIVR_APB1DIV4 (0x0002) /* PCLK1 = RCLK / 4 */ +#define STR71X_PCUPDIVR_APB1DIV8 (0x0003) /* PCLK1 = RCLK / 8 */ +#define STR71X_PCUPDIVR_FACT2MASK (0x0300) /* Bits 8-9: Division factor for APB2 peripherals */ +#define STR71X_PCUPDIVR_APB2DIV1 (0x0000) /* PCLK2 = RCLK */ +#define STR71X_PCUPDIVR_APB2DIV2 (0x0100) /* PCLK2 = RCLK / 2 */ +#define STR71X_PCUPDIVR_APB2DIV4 (0x0200) /* PCLK2 = RCLK / 4 */ +#define STR71X_PCUPDIVR_APB2DIV8 (0x0300) /* PCLK2 = RCLK / 8 */ + +/* PCU RSTR register bit definitions */ + +#define STR71X_PCURSTR_EMIRESET (0x0004) /* Bit 2: EMI reset */ + +/* PCU PLL2CR register bit definitions */ + +#define STR71X_PCUPPL2CR_DXMASK (0x0007) /* Bits 0-2: PLL2 output clock divider */ +#define STR71X_PCUPPL2CR_DIV1 (0x0000) /* PLL2 / 1 */ +#define STR71X_PCUPPL2CR_DIV2 (0x0001) /* PLL2 / 2 */ +#define STR71X_PCUPPL2CR_DIV3 (0x0002) /* PLL2 / 3 */ +#define STR71X_PCUPPL2CR_DIV4 (0x0003) /* PLL2 / 4 */ +#define STR71X_PCUPPL2CR_DIV5 (0x0004) /* PLL2 / 5 */ +#define STR71X_PCUPPL2CR_DIV6 (0x0005) /* PLL2 / 6 */ +#define STR71X_PCUPPL2CR_DIV7 (0x0006) /* PLL2 / 7 */ +#define STR71X_PCUPPL2CR_OFF (0x0007) /* PLL2 OFF */ +#define STR71X_PCUPPL2CR_MXMASK (0x0030) /* Bits 4-5: PLL2 multiplier */ +#define STR71X_PCUPPL2CR_MUL20 (0x0000) /* CLK2 * 20 */ +#define STR71X_PCUPPL2CR_MUL12 (0x0010) /* CLK2 * 12 */ +#define STR71X_PCUPPL2CR_MUL28 (0x0020) /* CLK2 * 28 */ +#define STR71X_PCUPPL2CR_MUL16 (0x0030) /* CLK2 * 16 */ +#define STR71X_PCUPPL2CR_FRQRNG (0x0040) /* Bit 6: PLL2 frequency range selection */ +#define STR71X_PCUPPL2CR_PLLEN (0x0080) /* Bit 7: PLL2 enable */ +#define STR71X_PCUPPL2CR_USBEN (0x0100) /* Bit 8: Enable PLL clock to USB */ +#define STR71X_PCUPPL2CR_IRQMASK (0x0200) /* Bit 9: Enable interrupt request CPU on lock transition */ +#define STR71X_PCUPPL2CR_IRQPEND (0x0400) /* Bit 10: Interrtup request to CPU on lock transition pending */ +#define STR71X_PCUPPL2CR_LOCK (0x8000) /* Bit 15: PLL2 locked */ + +/* PCU BOOTCR register bit definitions */ + +#define STR71X_PCUBOOTCR_BOOTMASK (0x0003) /* Bits 0-1: Boot mode */ +#define STR71X_PCUBOOTCR_BMFLASH (0x0000) /* FLASH */ +#define STR71X_PCUBOOTCR_BMRAM (0x0002) /* RAM */ +#define STR71X_PCUBOOTCR_BMEXTMEM (0x0003) /* FLASH */ +#define STR71X_PCUBOOTCR_BSPIOEN (0x0004) /* Bit 2: Enable BSPI0 */ +#define STR71X_PCUBOOTCR_USBFILTEN (0x0008) /* Bit 3: Enable USB standby filtering */ +#define STR71X_PCUBOOTCR_LPOWDBGEN (0x0010) /* Bit 4: Enable reserved features for STOP mode */ +#define STR71X_PCUBOOTCR_ACDEN (0x0020) /* Bit 5: Enable ADC */ +#define STR71X_PCUBOOTCR_CANACTIVE (0x0040) /* Bit 6: CAN active */ +#define STR71X_PCUBOOTCR_HDLCACTIVE (0x0080) /* Bit 7: HDLC active */ +#define STR71X_PCUBOOTCR_PKG64 (0x0200) /* Bit 9: Die is hosted in 64-pin package */ + +/* PCU PWRCR register bit definitions */ + +#define STR71X_PCUPWRCR_VRBYP (0x0008) /* Bit 3: Main regulator bypass */ +#define STR71X_PCUPWRCR_LPRWFI (0x0010) /* Bit 4: Low power regulator in wait-for-interrupt mode */ +#define STR71X_PCUPWRCR_LPRBYP (0x0020) /* Bit 5: Low power regulator bypass */ +#define STR71X_PCUPWRCR_PWRDWN (0x0040) /* Bit 6: Activate standby mode */ +#define STR71X_PCUPWRCR_OSCBYP (0x0080) /* Bit 7: 32KHz oscillator bypass */ +#define STR71X_PCUPWRCR_LVDDIS (0x0100) /* Bit 8: Low voltage detector disable */ +#define STR71X_PCUPWRCR_FLASHLP (0x0200) /* Bit 9: FLASH low speed (low power) select */ +#define STR71X_PCUPWRCR_VROK (0x1000) /* Bit 12: Voltage regulator OK */ +#define STR71X_PCUPWRCR_WKUPALRM (0x2000) /* Bit 13: Wakeup or alarm active */ +#define STR71X_PCUPWRCR_BUSY (0x4000) /* Bit 14: PCU register backup logic busy */ +#define STR71X_PCUPWRCR_WREN (0x8000) /* Bit 15: PCU register write enable */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_STR71X_STR71X_PCU_H */ diff --git a/nuttx/arch/arm/src/str71x/str71x_prccu.c b/nuttx/arch/arm/src/str71x/str71x_prccu.c index 61cee03dd..5379b1164 100644 --- a/nuttx/arch/arm/src/str71x/str71x_prccu.c +++ b/nuttx/arch/arm/src/str71x/str71x_prccu.c @@ -2,7 +2,7 @@ * arch/arm/src/str71x/str71x_prccu.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/str71x/str71x_rccu.h b/nuttx/arch/arm/src/str71x/str71x_rccu.h index 858bd8089..ed3114c2c 100644 --- a/nuttx/arch/arm/src/str71x/str71x_rccu.h +++ b/nuttx/arch/arm/src/str71x/str71x_rccu.h @@ -1,143 +1,143 @@ -/************************************************************************************
- * arch/arm/src/str71x/str71x_rccu.h
- *
- * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_STR71X_STR71X_RCCU_H
-#define __ARCH_ARM_SRC_STR71X_STR71X_RCCU_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-
-#include "str71x_map.h"
-
-/************************************************************************************
- * Pre-procesor Definitions
- ************************************************************************************/
-
-/* Reset and Clock Control Unit (RCCU) register offsets *****************************/
-
-/* All registers are 32-bits wide, but with the top 16 bits "reserved" */
-
-#define STR71X_RCCU_CCR_OFFSET (0x0000) /* 32-bits wide */
-#define STR71X_RCCU_CFR_OFFSET (0x0008) /* 32-bits wide */
-#define STR71X_RCCU_PLL1CR_OFFSET (0x0018) /* 32-bits wide */
-#define STR71X_RCCU_PER_OFFSET (0x001c) /* 32-bits wide */
-#define STR71X_RCCU_SMR_OFFSET (0x0020) /* 32-bits wide */
-
-/* Reset and Clock Control Unit (RCCU) register addresses ***************************/
-
-#define STR71X_RCCU_CCR (STR71X_RCCU_BASE + STR71X_RCCU_CCR_OFFSET)
-#define STR71X_RCCU_CFR (STR71X_RCCU_BASE + STR71X_RCCU_CFR_OFFSET)
-#define STR71X_RCCU_PLL1CR (STR71X_RCCU_BASE + STR71X_RCCU_PLL1CR_OFFSET)
-#define STR71X_RCCU_PER (STR71X_RCCU_BASE + STR71X_RCCU_PER_OFFSET)
-#define STR71X_RCCU_SMR (STR71X_RCCU_BASE + STR71X_RCCU_SMR_OFFSET)
-
-/* Register bit settings ************************************************************/
-
-/* RCCU CCR register bit definitions */
-
-#define STR71X_RCCUCCR_LPOWFI (0x00000001) /* Bit 0: Low power mode in wait-for-interrupt mode */
-#define STR71X_RCCUCCR_WFICLKSEL (0x00000002) /* Bit 1: WFI clock select */
-#define STR71X_RCCUCCR_CKAFSEL (0x00000004) /* Bit 2: Alternate function clock select */
-#define STR71X_RCCUCCR_SRESEN (0x00000008) /* Bit 3: Software reset enable */
-#define STR71X_RCCUCCR_ENCLOCK (0x00000080) /* Bit 7: Lock interrupt enable */
-#define STR71X_RCCUCCR_ENCKAF (0x00000100) /* Bit 8: CKAF interrupt enable */
-#define STR71X_RCCUCCR_ENCK216 (0x00000200) /* Bit 9: CK2_16 interrupt enable */
-#define STR71X_RCCUCCR_ENSTOP (0x00000400) /* Bit 10: Stop interrupt enable */
-#define STR71X_RCCUCCR_ENHALT (0x00000800) /* Bit 11: Enable halt */
-
-/* RCCU CFR register bit definitions */
-
-#define STR71X_RCCUCFR_CSUCKSEL (0x00000001) /* Bit 0: CSU clock select */
-#define STR71X_RCCUCFR_LOCK (0x00000002) /* Bit 1: PLL locked-in */
-#define STR71X_RCCUCFR_CKAFST (0x00000004) /* Bit 2: CK_AF status */
-#define STR71X_RCCUCFR_CK216 (0x00000008) /* Bit 3: CLK2/16 selection */
-#define STR71X_RCCUCFR_CKSTOPEN (0x00000010) /* Bit 4: Clock stop enable */
-#define STR71X_RCCUCFR_SOFTRES (0x00000020) /* Bit 5: Software reset */
-#define STR71X_RCCUCFR_WDGRES (0x00000040) /* Bit 6: Watchdog reset */
-#define STR71X_RCCUCFR_RTCALARM (0x00000080) /* Bit 7: RTC alarm reset */
-#define STR71X_RCCUCFR_LVDRES (0x00000200) /* Bit 9: Voltage regulator low voltage detector reset */
-#define STR71X_RCCUCFR_WKPRES (0x00000400) /* Bit 10: External wakeup */
-#define STR71X_RCCUCFR_LOCKI (0x00000800) /* Bit 11: Lock interrupt pending */
-#define STR71X_RCCUCFR_CKAFI (0x00001000) /* Bit 12: CK_AF switching interrupt pending */
-#define STR71X_RCCUCFR_CK216I (0x00002000) /* Bit 13: CK2_16 switching interrupt pending */
-#define STR71X_RCCUCFR_STOPI (0x00004000) /* Bit 14: Stop interrupt pending */
-#define STR71X_RCCUCFR_DIV2 (0x00008000) /* Bit 15: OSCIN divided by 2 */
-
-/* RCCU PPL1CR register bit definitions */
-
-#define STR71X_RCCUPLL1CR_DXMASK (0x00000003) /* Bit 0-2: PLL1 clock divisor */
-#define STR71X_RCCUPLL1CR_DIV1 (0x00000000) /* PLLCK / 1 */
-#define STR71X_RCCUPLL1CR_DIV2 (0x00000001) /* PLLCK / 2 */
-#define STR71X_RCCUPLL1CR_DIV3 (0x00000002) /* PLLCK / 3 */
-#define STR71X_RCCUPLL1CR_DIV4 (0x00000003) /* PLLCK / 4 */
-#define STR71X_RCCUPLL1CR_DIV5 (0x00000004) /* PLLCK / 5 */
-#define STR71X_RCCUPLL1CR_DIV6 (0x00000005) /* PLLCK / 6 */
-#define STR71X_RCCUPLL1CR_DIV7 (0x00000006) /* PLLCK / 7 */
-#define STR71X_RCCUPLL1CR_CLK2 (0x00000007) /* FREEN==0: CLK2 */
-#define STR71X_RCCUPLL1CR_FREERM (0x00000007) /* FREEN==1: PLL1 in free running mode */
-#define STR71X_RCCUPLL1CR_MXMASK (0x00000030) /* Bit 4-5: PLL1 clock multiplier */
-#define STR71X_RCCUPLL1CR_MUL20 (0x00000000) /* CLK2 * 20 */
-#define STR71X_RCCUPLL1CR_MUL12 (0x00000010) /* CLK2 * 12 */
-#define STR71X_RCCUPLL1CR_MUL24 (0x00000020) /* CLK2 * 24 */
-#define STR71X_RCCUPLL1CR_MUL16 (0x00000030) /* CLK2 * 16 */
-#define STR71X_RCCUPLL1CR_FREFRANGE (0x00000040) /* Bit 6: Reference frequency range select */
-#define STR71X_RCCUPLL1CR_FREEN (0x00000080) /* Bit 7: PKL free running mode */
-
-/* RCCU PER register bit definitions */
-
-#define STR71X_RCCUPER_EMI (0x00000004) /* Bit 2: EMI */
-#define STR71X_RCCUPER_USBKERNEL (0x00000010) /* Bit 4: USB Kernel */
-
-/* RCCU SMR register bit definitions */
-
-#define STR71X_RCCUSMR_WFI (0x00000001) /* Bit 0: Wait for interrupt */
-#define STR71X_RCCUSMR_HALT (0x00000000) /* Bit 1: Halt */
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-/************************************************************************************
- * Public Functions
- ************************************************************************************/
-
-#endif /* __ARCH_ARM_SRC_STR71X_STR71X_RCCU_H */
+/************************************************************************************ + * arch/arm/src/str71x/str71x_rccu.h + * + * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STR71X_STR71X_RCCU_H +#define __ARCH_ARM_SRC_STR71X_STR71X_RCCU_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +#include "str71x_map.h" + +/************************************************************************************ + * Pre-procesor Definitions + ************************************************************************************/ + +/* Reset and Clock Control Unit (RCCU) register offsets *****************************/ + +/* All registers are 32-bits wide, but with the top 16 bits "reserved" */ + +#define STR71X_RCCU_CCR_OFFSET (0x0000) /* 32-bits wide */ +#define STR71X_RCCU_CFR_OFFSET (0x0008) /* 32-bits wide */ +#define STR71X_RCCU_PLL1CR_OFFSET (0x0018) /* 32-bits wide */ +#define STR71X_RCCU_PER_OFFSET (0x001c) /* 32-bits wide */ +#define STR71X_RCCU_SMR_OFFSET (0x0020) /* 32-bits wide */ + +/* Reset and Clock Control Unit (RCCU) register addresses ***************************/ + +#define STR71X_RCCU_CCR (STR71X_RCCU_BASE + STR71X_RCCU_CCR_OFFSET) +#define STR71X_RCCU_CFR (STR71X_RCCU_BASE + STR71X_RCCU_CFR_OFFSET) +#define STR71X_RCCU_PLL1CR (STR71X_RCCU_BASE + STR71X_RCCU_PLL1CR_OFFSET) +#define STR71X_RCCU_PER (STR71X_RCCU_BASE + STR71X_RCCU_PER_OFFSET) +#define STR71X_RCCU_SMR (STR71X_RCCU_BASE + STR71X_RCCU_SMR_OFFSET) + +/* Register bit settings ************************************************************/ + +/* RCCU CCR register bit definitions */ + +#define STR71X_RCCUCCR_LPOWFI (0x00000001) /* Bit 0: Low power mode in wait-for-interrupt mode */ +#define STR71X_RCCUCCR_WFICLKSEL (0x00000002) /* Bit 1: WFI clock select */ +#define STR71X_RCCUCCR_CKAFSEL (0x00000004) /* Bit 2: Alternate function clock select */ +#define STR71X_RCCUCCR_SRESEN (0x00000008) /* Bit 3: Software reset enable */ +#define STR71X_RCCUCCR_ENCLOCK (0x00000080) /* Bit 7: Lock interrupt enable */ +#define STR71X_RCCUCCR_ENCKAF (0x00000100) /* Bit 8: CKAF interrupt enable */ +#define STR71X_RCCUCCR_ENCK216 (0x00000200) /* Bit 9: CK2_16 interrupt enable */ +#define STR71X_RCCUCCR_ENSTOP (0x00000400) /* Bit 10: Stop interrupt enable */ +#define STR71X_RCCUCCR_ENHALT (0x00000800) /* Bit 11: Enable halt */ + +/* RCCU CFR register bit definitions */ + +#define STR71X_RCCUCFR_CSUCKSEL (0x00000001) /* Bit 0: CSU clock select */ +#define STR71X_RCCUCFR_LOCK (0x00000002) /* Bit 1: PLL locked-in */ +#define STR71X_RCCUCFR_CKAFST (0x00000004) /* Bit 2: CK_AF status */ +#define STR71X_RCCUCFR_CK216 (0x00000008) /* Bit 3: CLK2/16 selection */ +#define STR71X_RCCUCFR_CKSTOPEN (0x00000010) /* Bit 4: Clock stop enable */ +#define STR71X_RCCUCFR_SOFTRES (0x00000020) /* Bit 5: Software reset */ +#define STR71X_RCCUCFR_WDGRES (0x00000040) /* Bit 6: Watchdog reset */ +#define STR71X_RCCUCFR_RTCALARM (0x00000080) /* Bit 7: RTC alarm reset */ +#define STR71X_RCCUCFR_LVDRES (0x00000200) /* Bit 9: Voltage regulator low voltage detector reset */ +#define STR71X_RCCUCFR_WKPRES (0x00000400) /* Bit 10: External wakeup */ +#define STR71X_RCCUCFR_LOCKI (0x00000800) /* Bit 11: Lock interrupt pending */ +#define STR71X_RCCUCFR_CKAFI (0x00001000) /* Bit 12: CK_AF switching interrupt pending */ +#define STR71X_RCCUCFR_CK216I (0x00002000) /* Bit 13: CK2_16 switching interrupt pending */ +#define STR71X_RCCUCFR_STOPI (0x00004000) /* Bit 14: Stop interrupt pending */ +#define STR71X_RCCUCFR_DIV2 (0x00008000) /* Bit 15: OSCIN divided by 2 */ + +/* RCCU PPL1CR register bit definitions */ + +#define STR71X_RCCUPLL1CR_DXMASK (0x00000003) /* Bit 0-2: PLL1 clock divisor */ +#define STR71X_RCCUPLL1CR_DIV1 (0x00000000) /* PLLCK / 1 */ +#define STR71X_RCCUPLL1CR_DIV2 (0x00000001) /* PLLCK / 2 */ +#define STR71X_RCCUPLL1CR_DIV3 (0x00000002) /* PLLCK / 3 */ +#define STR71X_RCCUPLL1CR_DIV4 (0x00000003) /* PLLCK / 4 */ +#define STR71X_RCCUPLL1CR_DIV5 (0x00000004) /* PLLCK / 5 */ +#define STR71X_RCCUPLL1CR_DIV6 (0x00000005) /* PLLCK / 6 */ +#define STR71X_RCCUPLL1CR_DIV7 (0x00000006) /* PLLCK / 7 */ +#define STR71X_RCCUPLL1CR_CLK2 (0x00000007) /* FREEN==0: CLK2 */ +#define STR71X_RCCUPLL1CR_FREERM (0x00000007) /* FREEN==1: PLL1 in free running mode */ +#define STR71X_RCCUPLL1CR_MXMASK (0x00000030) /* Bit 4-5: PLL1 clock multiplier */ +#define STR71X_RCCUPLL1CR_MUL20 (0x00000000) /* CLK2 * 20 */ +#define STR71X_RCCUPLL1CR_MUL12 (0x00000010) /* CLK2 * 12 */ +#define STR71X_RCCUPLL1CR_MUL24 (0x00000020) /* CLK2 * 24 */ +#define STR71X_RCCUPLL1CR_MUL16 (0x00000030) /* CLK2 * 16 */ +#define STR71X_RCCUPLL1CR_FREFRANGE (0x00000040) /* Bit 6: Reference frequency range select */ +#define STR71X_RCCUPLL1CR_FREEN (0x00000080) /* Bit 7: PKL free running mode */ + +/* RCCU PER register bit definitions */ + +#define STR71X_RCCUPER_EMI (0x00000004) /* Bit 2: EMI */ +#define STR71X_RCCUPER_USBKERNEL (0x00000010) /* Bit 4: USB Kernel */ + +/* RCCU SMR register bit definitions */ + +#define STR71X_RCCUSMR_WFI (0x00000001) /* Bit 0: Wait for interrupt */ +#define STR71X_RCCUSMR_HALT (0x00000000) /* Bit 1: Halt */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_STR71X_STR71X_RCCU_H */ diff --git a/nuttx/arch/arm/src/str71x/str71x_rtc.h b/nuttx/arch/arm/src/str71x/str71x_rtc.h index 634638f7e..554123ff6 100644 --- a/nuttx/arch/arm/src/str71x/str71x_rtc.h +++ b/nuttx/arch/arm/src/str71x/str71x_rtc.h @@ -1,92 +1,92 @@ -/************************************************************************************
- * arch/arm/src/str71x/str71x_rtc.h
- *
- * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_STR71X_STR71X_RTC_H
-#define __ARCH_ARM_SRC_STR71X_STR71X_RTC_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-
-#include "str71x_map.h"
-
-/************************************************************************************
- * Pre-procesor Definitions
- ************************************************************************************/
-
-/* RTC Registers ********************************************************************/
-
-#define STR71X_RTC_CRH (STR71X_RTC_BASE + 0x0000) /* 16-bits wide */
-#define STR71X_RTC_CRL (STR71X_RTC_BASE + 0x0004) /* 16-bits wide */
-#define STR71X_RTC_PRLH (STR71X_RTC_BASE + 0x0008) /* 16-bits wide */
-#define STR71X_RTC_PRLL (STR71X_RTC_BASE + 0x000c) /* 16-bits wide */
-#define STR71X_RTC_DIVH (STR71X_RTC_BASE + 0x0010) /* 16-bits wide */
-#define STR71X_RTC_DIVL (STR71X_RTC_BASE + 0x0014) /* 16-bits wide */
-#define STR71X_RTC_CNTH (STR71X_RTC_BASE + 0x0018) /* 16-bits wide */
-#define STR71X_RTC_CNTL (STR71X_RTC_BASE + 0x001c) /* 16-bits wide */
-#define STR71X_RTC_ALRH (STR71X_RTC_BASE + 0x0020) /* 16-bits wide */
-#define STR71X_RTC_ALRL (STR71X_RTC_BASE + 0x0024) /* 16-bits wide */
-
-/* Register bit settings ***********************************************************/
-
-/* RTC control register */
-
-#define STR71X_RTCCRH_SEN (0x0001) /* Bit 0: Second interrupt enable */
-#define STR71X_RTCCRH_AEN (0x0002) /* Bit 1: Alarm interrupt enable */
-#define STR71X_RTCCRH_OWEN (0x0004) /* Bit 2: Overflow interrupt enable */
-#define STR71X_RTCCRH_GEN (0x0008) /* Bit 3: Global interrupt enable */
-
-#define STR71X_RTCCRL_SIR (0x0001) /* Bit 0: Second interrupt request */
-#define STR71X_RTCCRL_AIR (0x0002) /* Bit 1: Alarm interrupt request */
-#define STR71X_RTCCRL_OWIR (0x0004) /* Bit 2: Overflow interrupt request */
-#define STR71X_RTCCRL_GIR (0x0008) /* Bit 3: Global interrupt request */
-#define STR71X_RTCCRL_CNF (0x0010) /* Bit 4: Enter configuration mode */
-#define STR71X_RTCCRL_RTOFF (0x0020) /* Bit 5: RTC Operation Off */
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-/************************************************************************************
- * Public Functions
- ************************************************************************************/
-
-#endif /* __ARCH_ARM_SRC_STR71X_STR71X_RTC_H */
+/************************************************************************************ + * arch/arm/src/str71x/str71x_rtc.h + * + * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STR71X_STR71X_RTC_H +#define __ARCH_ARM_SRC_STR71X_STR71X_RTC_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +#include "str71x_map.h" + +/************************************************************************************ + * Pre-procesor Definitions + ************************************************************************************/ + +/* RTC Registers ********************************************************************/ + +#define STR71X_RTC_CRH (STR71X_RTC_BASE + 0x0000) /* 16-bits wide */ +#define STR71X_RTC_CRL (STR71X_RTC_BASE + 0x0004) /* 16-bits wide */ +#define STR71X_RTC_PRLH (STR71X_RTC_BASE + 0x0008) /* 16-bits wide */ +#define STR71X_RTC_PRLL (STR71X_RTC_BASE + 0x000c) /* 16-bits wide */ +#define STR71X_RTC_DIVH (STR71X_RTC_BASE + 0x0010) /* 16-bits wide */ +#define STR71X_RTC_DIVL (STR71X_RTC_BASE + 0x0014) /* 16-bits wide */ +#define STR71X_RTC_CNTH (STR71X_RTC_BASE + 0x0018) /* 16-bits wide */ +#define STR71X_RTC_CNTL (STR71X_RTC_BASE + 0x001c) /* 16-bits wide */ +#define STR71X_RTC_ALRH (STR71X_RTC_BASE + 0x0020) /* 16-bits wide */ +#define STR71X_RTC_ALRL (STR71X_RTC_BASE + 0x0024) /* 16-bits wide */ + +/* Register bit settings ***********************************************************/ + +/* RTC control register */ + +#define STR71X_RTCCRH_SEN (0x0001) /* Bit 0: Second interrupt enable */ +#define STR71X_RTCCRH_AEN (0x0002) /* Bit 1: Alarm interrupt enable */ +#define STR71X_RTCCRH_OWEN (0x0004) /* Bit 2: Overflow interrupt enable */ +#define STR71X_RTCCRH_GEN (0x0008) /* Bit 3: Global interrupt enable */ + +#define STR71X_RTCCRL_SIR (0x0001) /* Bit 0: Second interrupt request */ +#define STR71X_RTCCRL_AIR (0x0002) /* Bit 1: Alarm interrupt request */ +#define STR71X_RTCCRL_OWIR (0x0004) /* Bit 2: Overflow interrupt request */ +#define STR71X_RTCCRL_GIR (0x0008) /* Bit 3: Global interrupt request */ +#define STR71X_RTCCRL_CNF (0x0010) /* Bit 4: Enter configuration mode */ +#define STR71X_RTCCRL_RTOFF (0x0020) /* Bit 5: RTC Operation Off */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_STR71X_STR71X_RTC_H */ diff --git a/nuttx/arch/arm/src/str71x/str71x_timer.h b/nuttx/arch/arm/src/str71x/str71x_timer.h index 2076a1d1d..7712009c2 100644 --- a/nuttx/arch/arm/src/str71x/str71x_timer.h +++ b/nuttx/arch/arm/src/str71x/str71x_timer.h @@ -1,155 +1,155 @@ -/************************************************************************************
- * arch/arm/src/str71x/str71x_timer.h
- *
- * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_STR71X_STR71X_TIMER_H
-#define __ARCH_ARM_SRC_STR71X_STR71X_TIMER_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-
-#include "str71x_map.h"
-
-/************************************************************************************
- * Pre-procesor Definitions
- ************************************************************************************/
-
-/* Register offsets *****************************************************************/
-
-#define STR71X_TIMER_ICAR_OFFSET (0x0000) /* 16-bits wide */
-#define STR71X_TIMER_ICBR_OFFSET (0x0004) /* 16-bits wide */
-#define STR71X_TIMER_OCAR_OFFSET (0x0008) /* 16-bits wide */
-#define STR71X_TIMER_OCBR_OFFSET (0x000c) /* 16-bits wide */
-#define STR71X_TIMER_CNTR_OFFSET (0x0010) /* 16-bits wide */
-#define STR71X_TIMER_CR1_OFFSET (0x0014) /* 16-bits wide */
-#define STR71X_TIMER_CR2_OFFSET (0x0018) /* 16-bits wide */
-#define STR71X_TIMER_SR_OFFSET (0x001c) /* 16-bits wide */
-
-/* Register Addresses ***************************************************************/
-
-#define STR71X_TIMER_ICAR(b) ((b) + STR71X_TIMER_ICAR_OFFSET)
-#define STR71X_TIMER_ICBR(b) ((b) + STR71X_TIMER_ICBR_OFFSET)
-#define STR71X_TIMER_OCAR(b) ((b) + STR71X_TIMER_OCAR_OFFSET)
-#define STR71X_TIMER_OCBR(b) ((b) + STR71X_TIMER_OCBR_OFFSET)
-#define STR71X_TIMER_CNTR(b) ((b) + STR71X_TIMER_CNTR_OFFSET)
-#define STR71X_TIMER_CR1(b) ((b) + STR71X_TIMER_CR1_OFFSET)
-#define STR71X_TIMER_CR2(b) ((b) + STR71X_TIMER_CR2_OFFSET)
-#define STR71X_TIMER_SR(b) ((b) + STR71X_TIMER_SR_OFFSET)
-
-#define STR71X_TIMER0_ICAR (STR71X_TIMER0_BASE + STR71X_TIMER_ICAR_OFFSET)
-#define STR71X_TIMER0_ICBR (STR71X_TIMER0_BASE + STR71X_TIMER_ICBR_OFFSET)
-#define STR71X_TIMER0_OCAR (STR71X_TIMER0_BASE + STR71X_TIMER_OCAR_OFFSET)
-#define STR71X_TIMER0_OCBR (STR71X_TIMER0_BASE + STR71X_TIMER_OCBR_OFFSET)
-#define STR71X_TIMER0_CNTR (STR71X_TIMER0_BASE + STR71X_TIMER_CNTR_OFFSET)
-#define STR71X_TIMER0_CR1 (STR71X_TIMER0_BASE + STR71X_TIMER_CR1_OFFSET)
-#define STR71X_TIMER0_CR2 (STR71X_TIMER0_BASE + STR71X_TIMER_CR2_OFFSET)
-#define STR71X_TIMER0_SR (STR71X_TIMER0_BASE + STR71X_TIMER_SR_OFFSET)
-
-#define STR71X_TIMER1_ICAR (STR71X_TIMER1_BASE + STR71X_TIMER_ICAR_OFFSET)
-#define STR71X_TIMER1_ICBR (STR71X_TIMER1_BASE + STR71X_TIMER_ICBR_OFFSET)
-#define STR71X_TIMER1_OCAR (STR71X_TIMER1_BASE + STR71X_TIMER_OCAR_OFFSET)
-#define STR71X_TIMER1_OCBR (STR71X_TIMER1_BASE + STR71X_TIMER_OCBR_OFFSET)
-#define STR71X_TIMER1_CNTR (STR71X_TIMER1_BASE + STR71X_TIMER_CNTR_OFFSET)
-#define STR71X_TIMER1_CR1 (STR71X_TIMER1_BASE + STR71X_TIMER_CR1_OFFSET)
-#define STR71X_TIMER1_CR2 (STR71X_TIMER1_BASE + STR71X_TIMER_CR2_OFFSET)
-#define STR71X_TIMER1_SR (STR71X_TIMER1_BASE + STR71X_TIMER_SR_OFFSET)
-
-#define STR71X_TIMER2_ICAR (STR71X_TIMER2_BASE + STR71X_TIMER_ICAR_OFFSET)
-#define STR71X_TIMER2_ICBR (STR71X_TIMER2_BASE + STR71X_TIMER_ICBR_OFFSET)
-#define STR71X_TIMER2_OCAR (STR71X_TIMER2_BASE + STR71X_TIMER_OCAR_OFFSET)
-#define STR71X_TIMER2_OCBR (STR71X_TIMER2_BASE + STR71X_TIMER_OCBR_OFFSET)
-#define STR71X_TIMER2_CNTR (STR71X_TIMER2_BASE + STR71X_TIMER_CNTR_OFFSET)
-#define STR71X_TIMER2_CR1 (STR71X_TIMER2_BASE + STR71X_TIMER_CR1_OFFSET)
-#define STR71X_TIMER2_CR2 (STR71X_TIMER2_BASE + STR71X_TIMER_CR2_OFFSET)
-#define STR71X_TIMER2_SR (STR71X_TIMER2_BASE + STR71X_TIMER_SR_OFFSET)
-
-#define STR71X_TIMER3_ICAR (STR71X_TIMER3_BASE + STR71X_TIMER_ICAR_OFFSET)
-#define STR71X_TIMER3_ICBR (STR71X_TIMER3_BASE + STR71X_TIMER_ICBR_OFFSET)
-#define STR71X_TIMER3_OCAR (STR71X_TIMER3_BASE + STR71X_TIMER_OCAR_OFFSET)
-#define STR71X_TIMER3_OCBR (STR71X_TIMER3_BASE + STR71X_TIMER_OCBR_OFFSET)
-#define STR71X_TIMER3_CNTR (STR71X_TIMER3_BASE + STR71X_TIMER_CNTR_OFFSET)
-#define STR71X_TIMER3_CR1 (STR71X_TIMER3_BASE + STR71X_TIMER_CR1_OFFSET)
-#define STR71X_TIMER3_CR2 (STR71X_TIMER3_BASE + STR71X_TIMER_CR2_OFFSET)
-#define STR71X_TIMER3_SR (STR71X_TIMER3_BASE + STR71X_TIMER_SR_OFFSET)
-
-/* Register bit settings ***********************************************************/
-
-/* Timer control register (CR1 and CR2) */
-
-#define STR71X_TIMERCR1_ECKEN (0x0001) /* Bit 0: External clock enable */
-#define STR71X_TIMERCR1_EXEDG (0x0002) /* Bit 1: External clock edge */
-#define STR71X_TIMERCR1_IEDGA (0x0004) /* Bit 2: Input edge A */
-#define STR71X_TIMERCR1_IEDGB (0x0008) /* Bit 3: Input edge B */
-#define STR71X_TIMERCR1_PWM (0x0010) /* Bit 4: Pulse width modulation */
-#define STR71X_TIMERCR1_OPM (0x0020) /* Bit 5: One pulse mode */
-#define STR71X_TIMERCR1_OCAE (0x0040) /* Bit 6: Output compare A enable */
-#define STR71X_TIMERCR1_OCBE (0x0080) /* Bit 7: Output compare B enable */
-#define STR71X_TIMERCR1_OLVLA (0x0100) /* Bit 8: Output level A */
-#define STR71X_TIMERCR1_OLVLB (0x0200) /* Bit 9: Output level B */
-#define STR71X_TIMERCR1_FOLVA (0x0400) /* Bit 10: Forced output compare A */
-#define STR71X_TIMERCR1_FOLVB (0x0800) /* Bit 11: Forced output compare B */
-#define STR71X_TIMERCR1_PWMI (0x4000) /* Bit 14: Pulse width modulation input */
-#define STR71X_TIMERCR1_EN (0x8000) /* Bit 15: Timer count enable */
-
-#define STR71X_TIMERCR2_DIVMASK (0x00ff) /* Bits 0-7: Timer prescaler value */
-#define STR71X_TIMERCR2_OCBIE (0x0800) /* Bit 11: Output capture B enable */
-#define STR71X_TIMERCR2_ICBIE (0x1000) /* Bit 12: Input capture B enable */
-#define STR71X_TIMERCR2_TOIE (0x2000) /* Bit 13: Timer overflow enable */
-#define STR71X_TIMERCR2_OCAIE (0x4000) /* Bit 14: Output capture A enable */
-#define STR71X_TIMERCR2_ICAIE (0x8000) /* Bit 15: Input capture B enable */
-
-/* Timer status register (SR) */
-
-#define STR71X_TIMERSR_OCFB (0x0800) /* Bit 11: Output capture flag B */
-#define STR71X_TIMERSR_ICFB (0x1000) /* Bit 12: Input capture flag B */
-#define STR71X_TIMERSR_TOF (0x2000) /* Bit 13: Timer overflow */
-#define STR71X_TIMERSR_OCFA (0x4000) /* Bit 14: Output capture flag A */
-#define STR71X_TIMERSR_ICFA (0x8000) /* Bit 15: Input capture flag A */
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-/************************************************************************************
- * Public Functions
- ************************************************************************************/
-
-#endif /* __ARCH_ARM_SRC_STR71X_STR71X_TIMER_H */
+/************************************************************************************ + * arch/arm/src/str71x/str71x_timer.h + * + * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STR71X_STR71X_TIMER_H +#define __ARCH_ARM_SRC_STR71X_STR71X_TIMER_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +#include "str71x_map.h" + +/************************************************************************************ + * Pre-procesor Definitions + ************************************************************************************/ + +/* Register offsets *****************************************************************/ + +#define STR71X_TIMER_ICAR_OFFSET (0x0000) /* 16-bits wide */ +#define STR71X_TIMER_ICBR_OFFSET (0x0004) /* 16-bits wide */ +#define STR71X_TIMER_OCAR_OFFSET (0x0008) /* 16-bits wide */ +#define STR71X_TIMER_OCBR_OFFSET (0x000c) /* 16-bits wide */ +#define STR71X_TIMER_CNTR_OFFSET (0x0010) /* 16-bits wide */ +#define STR71X_TIMER_CR1_OFFSET (0x0014) /* 16-bits wide */ +#define STR71X_TIMER_CR2_OFFSET (0x0018) /* 16-bits wide */ +#define STR71X_TIMER_SR_OFFSET (0x001c) /* 16-bits wide */ + +/* Register Addresses ***************************************************************/ + +#define STR71X_TIMER_ICAR(b) ((b) + STR71X_TIMER_ICAR_OFFSET) +#define STR71X_TIMER_ICBR(b) ((b) + STR71X_TIMER_ICBR_OFFSET) +#define STR71X_TIMER_OCAR(b) ((b) + STR71X_TIMER_OCAR_OFFSET) +#define STR71X_TIMER_OCBR(b) ((b) + STR71X_TIMER_OCBR_OFFSET) +#define STR71X_TIMER_CNTR(b) ((b) + STR71X_TIMER_CNTR_OFFSET) +#define STR71X_TIMER_CR1(b) ((b) + STR71X_TIMER_CR1_OFFSET) +#define STR71X_TIMER_CR2(b) ((b) + STR71X_TIMER_CR2_OFFSET) +#define STR71X_TIMER_SR(b) ((b) + STR71X_TIMER_SR_OFFSET) + +#define STR71X_TIMER0_ICAR (STR71X_TIMER0_BASE + STR71X_TIMER_ICAR_OFFSET) +#define STR71X_TIMER0_ICBR (STR71X_TIMER0_BASE + STR71X_TIMER_ICBR_OFFSET) +#define STR71X_TIMER0_OCAR (STR71X_TIMER0_BASE + STR71X_TIMER_OCAR_OFFSET) +#define STR71X_TIMER0_OCBR (STR71X_TIMER0_BASE + STR71X_TIMER_OCBR_OFFSET) +#define STR71X_TIMER0_CNTR (STR71X_TIMER0_BASE + STR71X_TIMER_CNTR_OFFSET) +#define STR71X_TIMER0_CR1 (STR71X_TIMER0_BASE + STR71X_TIMER_CR1_OFFSET) +#define STR71X_TIMER0_CR2 (STR71X_TIMER0_BASE + STR71X_TIMER_CR2_OFFSET) +#define STR71X_TIMER0_SR (STR71X_TIMER0_BASE + STR71X_TIMER_SR_OFFSET) + +#define STR71X_TIMER1_ICAR (STR71X_TIMER1_BASE + STR71X_TIMER_ICAR_OFFSET) +#define STR71X_TIMER1_ICBR (STR71X_TIMER1_BASE + STR71X_TIMER_ICBR_OFFSET) +#define STR71X_TIMER1_OCAR (STR71X_TIMER1_BASE + STR71X_TIMER_OCAR_OFFSET) +#define STR71X_TIMER1_OCBR (STR71X_TIMER1_BASE + STR71X_TIMER_OCBR_OFFSET) +#define STR71X_TIMER1_CNTR (STR71X_TIMER1_BASE + STR71X_TIMER_CNTR_OFFSET) +#define STR71X_TIMER1_CR1 (STR71X_TIMER1_BASE + STR71X_TIMER_CR1_OFFSET) +#define STR71X_TIMER1_CR2 (STR71X_TIMER1_BASE + STR71X_TIMER_CR2_OFFSET) +#define STR71X_TIMER1_SR (STR71X_TIMER1_BASE + STR71X_TIMER_SR_OFFSET) + +#define STR71X_TIMER2_ICAR (STR71X_TIMER2_BASE + STR71X_TIMER_ICAR_OFFSET) +#define STR71X_TIMER2_ICBR (STR71X_TIMER2_BASE + STR71X_TIMER_ICBR_OFFSET) +#define STR71X_TIMER2_OCAR (STR71X_TIMER2_BASE + STR71X_TIMER_OCAR_OFFSET) +#define STR71X_TIMER2_OCBR (STR71X_TIMER2_BASE + STR71X_TIMER_OCBR_OFFSET) +#define STR71X_TIMER2_CNTR (STR71X_TIMER2_BASE + STR71X_TIMER_CNTR_OFFSET) +#define STR71X_TIMER2_CR1 (STR71X_TIMER2_BASE + STR71X_TIMER_CR1_OFFSET) +#define STR71X_TIMER2_CR2 (STR71X_TIMER2_BASE + STR71X_TIMER_CR2_OFFSET) +#define STR71X_TIMER2_SR (STR71X_TIMER2_BASE + STR71X_TIMER_SR_OFFSET) + +#define STR71X_TIMER3_ICAR (STR71X_TIMER3_BASE + STR71X_TIMER_ICAR_OFFSET) +#define STR71X_TIMER3_ICBR (STR71X_TIMER3_BASE + STR71X_TIMER_ICBR_OFFSET) +#define STR71X_TIMER3_OCAR (STR71X_TIMER3_BASE + STR71X_TIMER_OCAR_OFFSET) +#define STR71X_TIMER3_OCBR (STR71X_TIMER3_BASE + STR71X_TIMER_OCBR_OFFSET) +#define STR71X_TIMER3_CNTR (STR71X_TIMER3_BASE + STR71X_TIMER_CNTR_OFFSET) +#define STR71X_TIMER3_CR1 (STR71X_TIMER3_BASE + STR71X_TIMER_CR1_OFFSET) +#define STR71X_TIMER3_CR2 (STR71X_TIMER3_BASE + STR71X_TIMER_CR2_OFFSET) +#define STR71X_TIMER3_SR (STR71X_TIMER3_BASE + STR71X_TIMER_SR_OFFSET) + +/* Register bit settings ***********************************************************/ + +/* Timer control register (CR1 and CR2) */ + +#define STR71X_TIMERCR1_ECKEN (0x0001) /* Bit 0: External clock enable */ +#define STR71X_TIMERCR1_EXEDG (0x0002) /* Bit 1: External clock edge */ +#define STR71X_TIMERCR1_IEDGA (0x0004) /* Bit 2: Input edge A */ +#define STR71X_TIMERCR1_IEDGB (0x0008) /* Bit 3: Input edge B */ +#define STR71X_TIMERCR1_PWM (0x0010) /* Bit 4: Pulse width modulation */ +#define STR71X_TIMERCR1_OPM (0x0020) /* Bit 5: One pulse mode */ +#define STR71X_TIMERCR1_OCAE (0x0040) /* Bit 6: Output compare A enable */ +#define STR71X_TIMERCR1_OCBE (0x0080) /* Bit 7: Output compare B enable */ +#define STR71X_TIMERCR1_OLVLA (0x0100) /* Bit 8: Output level A */ +#define STR71X_TIMERCR1_OLVLB (0x0200) /* Bit 9: Output level B */ +#define STR71X_TIMERCR1_FOLVA (0x0400) /* Bit 10: Forced output compare A */ +#define STR71X_TIMERCR1_FOLVB (0x0800) /* Bit 11: Forced output compare B */ +#define STR71X_TIMERCR1_PWMI (0x4000) /* Bit 14: Pulse width modulation input */ +#define STR71X_TIMERCR1_EN (0x8000) /* Bit 15: Timer count enable */ + +#define STR71X_TIMERCR2_DIVMASK (0x00ff) /* Bits 0-7: Timer prescaler value */ +#define STR71X_TIMERCR2_OCBIE (0x0800) /* Bit 11: Output capture B enable */ +#define STR71X_TIMERCR2_ICBIE (0x1000) /* Bit 12: Input capture B enable */ +#define STR71X_TIMERCR2_TOIE (0x2000) /* Bit 13: Timer overflow enable */ +#define STR71X_TIMERCR2_OCAIE (0x4000) /* Bit 14: Output capture A enable */ +#define STR71X_TIMERCR2_ICAIE (0x8000) /* Bit 15: Input capture B enable */ + +/* Timer status register (SR) */ + +#define STR71X_TIMERSR_OCFB (0x0800) /* Bit 11: Output capture flag B */ +#define STR71X_TIMERSR_ICFB (0x1000) /* Bit 12: Input capture flag B */ +#define STR71X_TIMERSR_TOF (0x2000) /* Bit 13: Timer overflow */ +#define STR71X_TIMERSR_OCFA (0x4000) /* Bit 14: Output capture flag A */ +#define STR71X_TIMERSR_ICFA (0x8000) /* Bit 15: Input capture flag A */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_STR71X_STR71X_TIMER_H */ diff --git a/nuttx/arch/arm/src/str71x/str71x_timerisr.c b/nuttx/arch/arm/src/str71x/str71x_timerisr.c index 8f41b9291..e55e1f21a 100644 --- a/nuttx/arch/arm/src/str71x/str71x_timerisr.c +++ b/nuttx/arch/arm/src/str71x/str71x_timerisr.c @@ -2,7 +2,7 @@ * arch/arm/src/str71x/str71x_timerisr.c * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/str71x/str71x_uart.h b/nuttx/arch/arm/src/str71x/str71x_uart.h index 9178062c4..3073e0053 100644 --- a/nuttx/arch/arm/src/str71x/str71x_uart.h +++ b/nuttx/arch/arm/src/str71x/str71x_uart.h @@ -1,181 +1,181 @@ -/************************************************************************************
- * arch/arm/src/str71x/str71x_uart.h
- *
- * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_STR71X_STR71X_UART_H
-#define __ARCH_ARM_SRC_STR71X_STR71X_UART_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-
-#include "str71x_map.h"
-
-/************************************************************************************
- * Pre-procesor Definitions
- ************************************************************************************/
-
-/* Registers offsets ****************************************************************/
-
-#define STR71X_UART_BR_OFFSET (0x0000) /* 16-bits wide */
-#define STR71X_UART_TXBUFR_OFFSET (0x0004) /* 16-bits wide */
-#define STR71X_UART_RXBUFR_OFFSET (0x0008) /* 16-bits wide */
-#define STR71X_UART_CR_OFFSET (0x000c) /* 16-bits wide */
-#define STR71X_UART_IER_OFFSET (0x0010) /* 16-bits wide */
-#define STR71X_UART_SR_OFFSET (0x0014) /* 16-bits wide */
-#define STR71X_UART_GTR_OFFSET (0x0018) /* 16-bits wide */
-#define STR71X_UART_TOR_OFFSET (0x001c) /* 16-bits wide */
-#define STR71X_UART_TXRSTR_OFFSET (0x0020) /* 16-bits wide */
-#define STR71X_UART_RXRSTR_OFFSET (0x0024) /* 16-bits wide */
-
-/* Registers addresses **************************************************************/
-
-#define STR71X_UART_BR(b) ((b) + STR71X_UART_BR_OFFSET)
-#define STR71X_UART_TXBUFR(b) ((b) + STR71X_UART_TXBUFR_OFFSET)
-#define STR71X_UART_RXBUFR(b) ((b) + STR71X_UART_RXBUFR_OFFSET)
-#define STR71X_UART_CR(b) ((b) + STR71X_UART_CR_OFFSET)
-#define STR71X_UART_IER(b) ((b) + STR71X_UART_IER_OFFSET)
-#define STR71X_UART_SR(b) ((b) + STR71X_UART_SR_OFFSET)
-#define STR71X_UART_GTR(b) ((b) + STR71X_UART_GTR_OFFSET)
-#define STR71X_UART_TOR(b) ((b) + STR71X_UART_TOR_OFFSET)
-#define STR71X_UART_TXRSTR(b) ((b) + STR71X_UART_TXRSTR_OFFSET)
-#define STR71X_UART_RXRSTR(b) ((b) + STR71X_UART_RXRSTR_OFFSET)
-
-#define STR71X_UART0_BR (STR71X_UART0_BASE + STR71X_UART_BR_OFFSET)
-#define STR71X_UART0_TXBUFR (STR71X_UART0_BASE + STR71X_UART_TXBUFR_OFFSET)
-#define STR71X_UART0_RXBUFR (STR71X_UART0_BASE + STR71X_UART_RXBUFR_OFFSET)
-#define STR71X_UART0_CR (STR71X_UART0_BASE + STR71X_UART_CR_OFFSET)
-#define STR71X_UART0_IER (STR71X_UART0_BASE + STR71X_UART_IER_OFFSET)
-#define STR71X_UART0_SR (STR71X_UART0_BASE + STR71X_UART_SR_OFFSET)
-#define STR71X_UART0_GTR (STR71X_UART0_BASE + STR71X_UART_GTR_OFFSET)
-#define STR71X_UART0_TOR (STR71X_UART0_BASE + STR71X_UART_TOR_OFFSET)
-#define STR71X_UART0_TXRSTR (STR71X_UART0_BASE + STR71X_UART_TXRSTR_OFFSET)
-#define STR71X_UART0_RXRSTR (STR71X_UART0_BASE + STR71X_UART_RXRSTR_OFFSET)
-
-#define STR71X_UART1_BR (STR71X_UART1_BASE + STR71X_UART_BR_OFFSET)
-#define STR71X_UART1_TXBUFR (STR71X_UART1_BASE + STR71X_UART_TXBUFR_OFFSET)
-#define STR71X_UART1_RXBUFR (STR71X_UART1_BASE + STR71X_UART_RXBUFR_OFFSET)
-#define STR71X_UART1_CR (STR71X_UART1_BASE + STR71X_UART_CR_OFFSET)
-#define STR71X_UART1_IER (STR71X_UART1_BASE + STR71X_UART_IER_OFFSET)
-#define STR71X_UART1_SR (STR71X_UART1_BASE + STR71X_UART_SR_OFFSET)
-#define STR71X_UART1_GTR (STR71X_UART1_BASE + STR71X_UART_GTR_OFFSET)
-#define STR71X_UART1_TOR (STR71X_UART1_BASE + STR71X_UART_TOR_OFFSET)
-#define STR71X_UART1_TXRSTR (STR71X_UART1_BASE + STR71X_UART_TXRSTR_OFFSET)
-#define STR71X_UART1_RXRSTR (STR71X_UART1_BASE + STR71X_UART_RXRSTR_OFFSET)
-
-#define STR71X_UART2_BR (STR71X_UART2_BASE + STR71X_UART_BR_OFFSET)
-#define STR71X_UART2_TXBUFR (STR71X_UART2_BASE + STR71X_UART_TXBUFR_OFFSET)
-#define STR71X_UART2_RXBUFR (STR71X_UART2_BASE + STR71X_UART_RXBUFR_OFFSET)
-#define STR71X_UART2_CR (STR71X_UART2_BASE + STR71X_UART_CR_OFFSET)
-#define STR71X_UART2_IER (STR71X_UART2_BASE + STR71X_UART_IER_OFFSET)
-#define STR71X_UART2_SR (STR71X_UART2_BASE + STR71X_UART_SR_OFFSET)
-#define STR71X_UART2_GTR (STR71X_UART2_BASE + STR71X_UART_GTR_OFFSET)
-#define STR71X_UART2_TOR (STR71X_UART2_BASE + STR71X_UART_TOR_OFFSET)
-#define STR71X_UART2_TXRSTR (STR71X_UART2_BASE + STR71X_UART_TXRSTR_OFFSET)
-#define STR71X_UART2_RXRSTR (STR71X_UART2_BASE + STR71X_UART_RXRSTR_OFFSET)
-
-#define STR71X_UART3_BR (STR71X_UART3_BASE + STR71X_UART_BR_OFFSET)
-#define STR71X_UART3_TXBUFR (STR71X_UART3_BASE + STR71X_UART_TXBUFR_OFFSET)
-#define STR71X_UART3_RXBUFR (STR71X_UART3_BASE + STR71X_UART_RXBUFR_OFFSET)
-#define STR71X_UART3_CR (STR71X_UART3_BASE + STR71X_UART_CR_OFFSET)
-#define STR71X_UART3_IER (STR71X_UART3_BASE + STR71X_UART_IER_OFFSET)
-#define STR71X_UART3_SR (STR71X_UART3_BASE + STR71X_UART_SR_OFFSET)
-#define STR71X_UART3_GTR (STR71X_UART3_BASE + STR71X_UART_GTR_OFFSET)
-#define STR71X_UART3_TOR (STR71X_UART3_BASE + STR71X_UART_TOR_OFFSET)
-#define STR71X_UART3_TXRSTR (STR71X_UART3_BASE + STR71X_UART_TXRSTR_OFFSET)
-#define STR71X_UART3_RXRSTR (STR71X_UART3_BASE + STR71X_UART_RXRSTR_OFFSET)
-
-/* Register bit settings ***********************************************************/
-
-/* UART control register (CR) */
-
-#define STR71X_UARTCR_MODEMASK (0x0007) /* Bits 0-2: Mode */
-#define STR71X_UARTCR_MODE8BIT (0x0001) /* 8-bit */
-#define STR71X_UARTCR_MODE7BITP (0x0003) /* 7-bit with parity bit */
-#define STR71X_UARTCR_MODE9BIT (0x0004) /* 9-bit */
-#define STR71X_UARTCR_MODE8BITWU (0x0005) /* 8-bit with wakeup bit */
-#define STR71X_UARTCR_MODE8BITP (0x0007) /* 8-bit with parity bit */
-#define STR71X_UARTCR_STOPBITSMASK (0x0018) /* Bits 3-4: Stop bits */
-#define STR71X_UARTCR_STOPBIT05 (0x0000) /* 0.5 stop bits */
-#define STR71X_UARTCR_STOPBIT10 (0x0008) /* 1.0 stop bit */
-#define STR71X_UARTCR_STOPBIT15 (0x0010) /* 1.5 stop bits */
-#define STR71X_UARTCR_STOPBIT20 (0x0018) /* 2.0 stop bits */
-#define STR71X_UARTCR_PARITYODD (0x0020) /* Bit 5: Parity selection */
-#define STR71X_UARTCR_LOOPBACK (0x0040) /* Bit 6: Loopback mode enable */
-#define STR71X_UARTCR_RUN (0x0080) /* Bit 7: Baudrate generator run bit */
-#define STR71X_UARTCR_RXENABLE (0x0100) /* Bit 8: Receiver enable */
-#define STR71X_UARTCR_SCENABLE (0x0200) /* Bit 9: SmartCard mode enable */
-#define STR71X_UARTCR_FIFOENABLE (0x0400) /* Bit 10: FIFO enable */
-
-/* UART interrupt enable (IER) register */
-
-#define STR71X_UARTIER_RNE (0x0001) /* Bit 0: Rx buffer not empty */
-#define STR71X_UARTIER_TE (0x0002) /* Bit 1: Tx empty */
-#define STR71X_UARTIER_THE (0x0004) /* Bit 2: Tx half empty */
-#define STR71X_UARTIER_PERROR (0x0008) /* Bit 3: Parity error */
-#define STR71X_UARTIER_FRERROR (0x0010) /* Bit 4: Frame error */
-#define STR71X_UARTIER_OVERRUN (0x0020) /* Bit 5: Overrun error */
-#define STR71X_UARTIER_TIMEOUTNE (0x0040) /* Bit 6: Time out not empty*/
-#define STR71X_UARTIER_TIMEOUTIDLE (0x0080) /* Bit 7: Timeout out idle */
-#define STR71X_UARTIER_RHF (0x0100) /* Bit 8: Rx half full */
-#define STR71X_UARTIER_ALL (0x01ff) /* All interrupt bits */
-
-/* UART status register (SR) */
-
-#define STR71X_UARTSR_RNE (0x0001) /* Bit 0: Rx buffer not empty */
-#define STR71X_UARTSR_TE (0x0002) /* Bit 1: Tx empty */
-#define STR71X_UARTSR_THE (0x0004) /* Bit 2: Tx half empty */
-#define STR71X_UARTSR_PERR (0x0008) /* Bit 3: Parity error */
-#define STR71X_UARTSR_FRERROR (0x0010) /* Bit 4: Frame error */
-#define STR71X_UARTSR_OVERRUN (0x0020) /* Bit 5: Overrun error */
-#define STR71X_UARTSR_TIMEOUTNE (0x0040) /* Bit 6: Time out not empty */
-#define STR71X_UARTSR_TIMEOUTIDLE (0x0080) /* Bit 7: Timeout out idle */
-#define STR71X_UARTSR_RHF (0x0100) /* Bit 8: Rx half full */
-#define STR71X_UARTSR_TF (0x0200) /* Bit 9: Tx full */
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-/************************************************************************************
- * Public Functions
- ************************************************************************************/
-
-#endif /* __ARCH_ARM_SRC_STR71X_STR71X_UART_H */
+/************************************************************************************ + * arch/arm/src/str71x/str71x_uart.h + * + * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STR71X_STR71X_UART_H +#define __ARCH_ARM_SRC_STR71X_STR71X_UART_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +#include "str71x_map.h" + +/************************************************************************************ + * Pre-procesor Definitions + ************************************************************************************/ + +/* Registers offsets ****************************************************************/ + +#define STR71X_UART_BR_OFFSET (0x0000) /* 16-bits wide */ +#define STR71X_UART_TXBUFR_OFFSET (0x0004) /* 16-bits wide */ +#define STR71X_UART_RXBUFR_OFFSET (0x0008) /* 16-bits wide */ +#define STR71X_UART_CR_OFFSET (0x000c) /* 16-bits wide */ +#define STR71X_UART_IER_OFFSET (0x0010) /* 16-bits wide */ +#define STR71X_UART_SR_OFFSET (0x0014) /* 16-bits wide */ +#define STR71X_UART_GTR_OFFSET (0x0018) /* 16-bits wide */ +#define STR71X_UART_TOR_OFFSET (0x001c) /* 16-bits wide */ +#define STR71X_UART_TXRSTR_OFFSET (0x0020) /* 16-bits wide */ +#define STR71X_UART_RXRSTR_OFFSET (0x0024) /* 16-bits wide */ + +/* Registers addresses **************************************************************/ + +#define STR71X_UART_BR(b) ((b) + STR71X_UART_BR_OFFSET) +#define STR71X_UART_TXBUFR(b) ((b) + STR71X_UART_TXBUFR_OFFSET) +#define STR71X_UART_RXBUFR(b) ((b) + STR71X_UART_RXBUFR_OFFSET) +#define STR71X_UART_CR(b) ((b) + STR71X_UART_CR_OFFSET) +#define STR71X_UART_IER(b) ((b) + STR71X_UART_IER_OFFSET) +#define STR71X_UART_SR(b) ((b) + STR71X_UART_SR_OFFSET) +#define STR71X_UART_GTR(b) ((b) + STR71X_UART_GTR_OFFSET) +#define STR71X_UART_TOR(b) ((b) + STR71X_UART_TOR_OFFSET) +#define STR71X_UART_TXRSTR(b) ((b) + STR71X_UART_TXRSTR_OFFSET) +#define STR71X_UART_RXRSTR(b) ((b) + STR71X_UART_RXRSTR_OFFSET) + +#define STR71X_UART0_BR (STR71X_UART0_BASE + STR71X_UART_BR_OFFSET) +#define STR71X_UART0_TXBUFR (STR71X_UART0_BASE + STR71X_UART_TXBUFR_OFFSET) +#define STR71X_UART0_RXBUFR (STR71X_UART0_BASE + STR71X_UART_RXBUFR_OFFSET) +#define STR71X_UART0_CR (STR71X_UART0_BASE + STR71X_UART_CR_OFFSET) +#define STR71X_UART0_IER (STR71X_UART0_BASE + STR71X_UART_IER_OFFSET) +#define STR71X_UART0_SR (STR71X_UART0_BASE + STR71X_UART_SR_OFFSET) +#define STR71X_UART0_GTR (STR71X_UART0_BASE + STR71X_UART_GTR_OFFSET) +#define STR71X_UART0_TOR (STR71X_UART0_BASE + STR71X_UART_TOR_OFFSET) +#define STR71X_UART0_TXRSTR (STR71X_UART0_BASE + STR71X_UART_TXRSTR_OFFSET) +#define STR71X_UART0_RXRSTR (STR71X_UART0_BASE + STR71X_UART_RXRSTR_OFFSET) + +#define STR71X_UART1_BR (STR71X_UART1_BASE + STR71X_UART_BR_OFFSET) +#define STR71X_UART1_TXBUFR (STR71X_UART1_BASE + STR71X_UART_TXBUFR_OFFSET) +#define STR71X_UART1_RXBUFR (STR71X_UART1_BASE + STR71X_UART_RXBUFR_OFFSET) +#define STR71X_UART1_CR (STR71X_UART1_BASE + STR71X_UART_CR_OFFSET) +#define STR71X_UART1_IER (STR71X_UART1_BASE + STR71X_UART_IER_OFFSET) +#define STR71X_UART1_SR (STR71X_UART1_BASE + STR71X_UART_SR_OFFSET) +#define STR71X_UART1_GTR (STR71X_UART1_BASE + STR71X_UART_GTR_OFFSET) +#define STR71X_UART1_TOR (STR71X_UART1_BASE + STR71X_UART_TOR_OFFSET) +#define STR71X_UART1_TXRSTR (STR71X_UART1_BASE + STR71X_UART_TXRSTR_OFFSET) +#define STR71X_UART1_RXRSTR (STR71X_UART1_BASE + STR71X_UART_RXRSTR_OFFSET) + +#define STR71X_UART2_BR (STR71X_UART2_BASE + STR71X_UART_BR_OFFSET) +#define STR71X_UART2_TXBUFR (STR71X_UART2_BASE + STR71X_UART_TXBUFR_OFFSET) +#define STR71X_UART2_RXBUFR (STR71X_UART2_BASE + STR71X_UART_RXBUFR_OFFSET) +#define STR71X_UART2_CR (STR71X_UART2_BASE + STR71X_UART_CR_OFFSET) +#define STR71X_UART2_IER (STR71X_UART2_BASE + STR71X_UART_IER_OFFSET) +#define STR71X_UART2_SR (STR71X_UART2_BASE + STR71X_UART_SR_OFFSET) +#define STR71X_UART2_GTR (STR71X_UART2_BASE + STR71X_UART_GTR_OFFSET) +#define STR71X_UART2_TOR (STR71X_UART2_BASE + STR71X_UART_TOR_OFFSET) +#define STR71X_UART2_TXRSTR (STR71X_UART2_BASE + STR71X_UART_TXRSTR_OFFSET) +#define STR71X_UART2_RXRSTR (STR71X_UART2_BASE + STR71X_UART_RXRSTR_OFFSET) + +#define STR71X_UART3_BR (STR71X_UART3_BASE + STR71X_UART_BR_OFFSET) +#define STR71X_UART3_TXBUFR (STR71X_UART3_BASE + STR71X_UART_TXBUFR_OFFSET) +#define STR71X_UART3_RXBUFR (STR71X_UART3_BASE + STR71X_UART_RXBUFR_OFFSET) +#define STR71X_UART3_CR (STR71X_UART3_BASE + STR71X_UART_CR_OFFSET) +#define STR71X_UART3_IER (STR71X_UART3_BASE + STR71X_UART_IER_OFFSET) +#define STR71X_UART3_SR (STR71X_UART3_BASE + STR71X_UART_SR_OFFSET) +#define STR71X_UART3_GTR (STR71X_UART3_BASE + STR71X_UART_GTR_OFFSET) +#define STR71X_UART3_TOR (STR71X_UART3_BASE + STR71X_UART_TOR_OFFSET) +#define STR71X_UART3_TXRSTR (STR71X_UART3_BASE + STR71X_UART_TXRSTR_OFFSET) +#define STR71X_UART3_RXRSTR (STR71X_UART3_BASE + STR71X_UART_RXRSTR_OFFSET) + +/* Register bit settings ***********************************************************/ + +/* UART control register (CR) */ + +#define STR71X_UARTCR_MODEMASK (0x0007) /* Bits 0-2: Mode */ +#define STR71X_UARTCR_MODE8BIT (0x0001) /* 8-bit */ +#define STR71X_UARTCR_MODE7BITP (0x0003) /* 7-bit with parity bit */ +#define STR71X_UARTCR_MODE9BIT (0x0004) /* 9-bit */ +#define STR71X_UARTCR_MODE8BITWU (0x0005) /* 8-bit with wakeup bit */ +#define STR71X_UARTCR_MODE8BITP (0x0007) /* 8-bit with parity bit */ +#define STR71X_UARTCR_STOPBITSMASK (0x0018) /* Bits 3-4: Stop bits */ +#define STR71X_UARTCR_STOPBIT05 (0x0000) /* 0.5 stop bits */ +#define STR71X_UARTCR_STOPBIT10 (0x0008) /* 1.0 stop bit */ +#define STR71X_UARTCR_STOPBIT15 (0x0010) /* 1.5 stop bits */ +#define STR71X_UARTCR_STOPBIT20 (0x0018) /* 2.0 stop bits */ +#define STR71X_UARTCR_PARITYODD (0x0020) /* Bit 5: Parity selection */ +#define STR71X_UARTCR_LOOPBACK (0x0040) /* Bit 6: Loopback mode enable */ +#define STR71X_UARTCR_RUN (0x0080) /* Bit 7: Baudrate generator run bit */ +#define STR71X_UARTCR_RXENABLE (0x0100) /* Bit 8: Receiver enable */ +#define STR71X_UARTCR_SCENABLE (0x0200) /* Bit 9: SmartCard mode enable */ +#define STR71X_UARTCR_FIFOENABLE (0x0400) /* Bit 10: FIFO enable */ + +/* UART interrupt enable (IER) register */ + +#define STR71X_UARTIER_RNE (0x0001) /* Bit 0: Rx buffer not empty */ +#define STR71X_UARTIER_TE (0x0002) /* Bit 1: Tx empty */ +#define STR71X_UARTIER_THE (0x0004) /* Bit 2: Tx half empty */ +#define STR71X_UARTIER_PERROR (0x0008) /* Bit 3: Parity error */ +#define STR71X_UARTIER_FRERROR (0x0010) /* Bit 4: Frame error */ +#define STR71X_UARTIER_OVERRUN (0x0020) /* Bit 5: Overrun error */ +#define STR71X_UARTIER_TIMEOUTNE (0x0040) /* Bit 6: Time out not empty*/ +#define STR71X_UARTIER_TIMEOUTIDLE (0x0080) /* Bit 7: Timeout out idle */ +#define STR71X_UARTIER_RHF (0x0100) /* Bit 8: Rx half full */ +#define STR71X_UARTIER_ALL (0x01ff) /* All interrupt bits */ + +/* UART status register (SR) */ + +#define STR71X_UARTSR_RNE (0x0001) /* Bit 0: Rx buffer not empty */ +#define STR71X_UARTSR_TE (0x0002) /* Bit 1: Tx empty */ +#define STR71X_UARTSR_THE (0x0004) /* Bit 2: Tx half empty */ +#define STR71X_UARTSR_PERR (0x0008) /* Bit 3: Parity error */ +#define STR71X_UARTSR_FRERROR (0x0010) /* Bit 4: Frame error */ +#define STR71X_UARTSR_OVERRUN (0x0020) /* Bit 5: Overrun error */ +#define STR71X_UARTSR_TIMEOUTNE (0x0040) /* Bit 6: Time out not empty */ +#define STR71X_UARTSR_TIMEOUTIDLE (0x0080) /* Bit 7: Timeout out idle */ +#define STR71X_UARTSR_RHF (0x0100) /* Bit 8: Rx half full */ +#define STR71X_UARTSR_TF (0x0200) /* Bit 9: Tx full */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_STR71X_STR71X_UART_H */ diff --git a/nuttx/arch/arm/src/str71x/str71x_usb.h b/nuttx/arch/arm/src/str71x/str71x_usb.h index 7fcbf5727..24ddd8a6b 100644 --- a/nuttx/arch/arm/src/str71x/str71x_usb.h +++ b/nuttx/arch/arm/src/str71x/str71x_usb.h @@ -1,180 +1,180 @@ -/************************************************************************************
- * arch/arm/src/str71x/str71x_usb.h
- *
- * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_STR71X_STR71X_USB_H
-#define __ARCH_ARM_SRC_STR71X_STR71X_USB_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-
-#include "str71x_map.h"
-
-/************************************************************************************
- * Pre-procesor Definitions
- ************************************************************************************/
-
-/* USB registers ********************************************************************/
-
-#define STR71X_USB_NENDPNTS (16)
-#define STR71X_USB_EPR(ep) (STR71X_USB_BASE + ((ep) << 4))
-#define STR71X_USB_EP0R (STR71X_USB_BASE + 0x0000) /* Endpoint 0 */
-#define STR71X_USB_EP1R (STR71X_USB_BASE + 0x0004) /* Endpoint 1 */
-#define STR71X_USB_EP2R (STR71X_USB_BASE + 0x0008) /* Endpoint 2 */
-#define STR71X_USB_EP3R (STR71X_USB_BASE + 0x000c) /* Endpoint 3 */
-#define STR71X_USB_EP4R (STR71X_USB_BASE + 0x0010) /* Endpoint 4 */
-#define STR71X_USB_EP5R (STR71X_USB_BASE + 0x0014) /* Endpoint 5 */
-#define STR71X_USB_EP6R (STR71X_USB_BASE + 0x0018) /* Endpoint 6 */
-#define STR71X_USB_EP7R (STR71X_USB_BASE + 0x001c) /* Endpoint 7 */
-#define STR71X_USB_EP8R (STR71X_USB_BASE + 0x0020) /* Endpoint 8 */
-#define STR71X_USB_EP9R (STR71X_USB_BASE + 0x0024) /* Endpoint 9 */
-#define STR71X_USB_EP10R (STR71X_USB_BASE + 0x0028) /* Endpoint 10 */
-#define STR71X_USB_EP11R (STR71X_USB_BASE + 0x002c) /* Endpoint 11 */
-#define STR71X_USB_EP12R (STR71X_USB_BASE + 0x0030) /* Endpoint 12 */
-#define STR71X_USB_EP13R (STR71X_USB_BASE + 0x0034) /* Endpoint 13 */
-#define STR71X_USB_EP14R (STR71X_USB_BASE + 0x0038) /* Endpoint 14 */
-#define STR71X_USB_EP15R (STR71X_USB_BASE + 0x003c) /* Endpoint 15 */
-#define STR71X_USB_CNTR (STR71X_USB_BASE + 0x0040) /* Control register */
-#define STR71X_USB_ISTR (STR71X_USB_BASE + 0x0044) /* Interrupt status register */
-#define STR71X_USB_FNR (STR71X_USB_BASE + 0x0048) /* Frame number register */
-#define STR71X_USB_DADDR (STR71X_USB_BASE + 0x004C) /* Device address register */
-#define STR71X_USB_BTABLE (STR71X_USB_BASE + 0x0050) /* Buffer Table address register */
-
-/* Register bit settings ***********************************************************/
-
-/* Control Register (CNTR) */
-
-#define USB_CNTR_FRES (1 << 0) /* Bit 0: Force usb reset */
-#define USB_CNTR_PDWN (1 << 1) /* Bit 1: Power down */
-#define USB_CNTR_LPMODE (1 << 2) /* Bit 2: Low-power mode */
-#define USB_CNTR_FSUSP (1 << 3) /* Bit 3: Force suspend */
-#define USB_CNTR_RESUME (1 << 4) /* Bit 4: Resume request */
-#define USB_CNTR_ESOFM (1 << 8) /* Bit 8: Expected start of frame */
-#define USB_CNTR_SOFM (1 << 9) /* Bit 9: Start of frame */
-#define USB_CNTR_RESETM (1 << 10) /* Bit 10: Reset */
-#define USB_CNTR_SUSPM (1 << 11) /* Bit 11: Suspend */
-#define USB_CNTR_WKUPM (1 << 12) /* Bit 12: Wake up */
-#define USB_CNTR_ERRM (1 << 13) /* Bit 13: Error */
-#define USB_CNTR_DOVRM (1 << 14) /* Bit 14: DMA over/underrun */
-#define USB_CNTR_CTRM (1 << 15) /* Bit 15: Correct transfer */
-
-/* Interrupt status register (ISTR) */
-
-#define USB_ISTR_EPID_SHIFT 0 /* Bits 0-3: Endpoint Identifier */
-#define USB_ISTR_EPID_MASK (0x0f << USB_ISTR_EPID_SHIFT)
-#define USB_ISTR_DIR (1 << 4) /* Bit 4: DIRection of transaction */
-#define USB_ISTR_ESOF (1 << 8) /* Bit 8: Expected start of frame */
-#define USB_ISTR_SOF (1 << 9) /* Bit 9: Start of frame */
-#define USB_ISTR_RESET (1 << 10) /* Bit 10: Reset */
-#define USB_ISTR_SUSP (1 << 11) /* Bit 11: Suspend */
-#define USB_ISTR_WKUP (1 << 12) /* Bit 12: Wakeup */
-#define USB_ISTR_ERR (1 << 13) /* Bit 13: Error */
-#define USB_ISTR_DOVR (1 << 14) /* Bit 14: DMA Over/underrun */
-#define USB_ISTR_CTR (1 << 15) /* Bit 15: Correct Transfer */
-
-/* Frame number register (FNR) */
-
-#define USB_FNR_FN_SHIFT 0 /* Bit 0-10: Frame number */
-#define USB_FNR_LSOF_SHIFT 11 /* Bits 11-12 : Lost SOF */
-#define USB_FNR_LSOF_MASK (3 << USB_FNR_LSOF_SHIFT)
-#define USB_FNR_FN_MASK (0x07ff << USB_FNR_FN_SHIFT)
-#define USB_FNR_LCK (1 << 13) /* Bit 13: Locked */
-#define USB_FNR_RXDM (1 << 14) /* Bit 14: Status of D- data line */
-#define USB_FNR_RXDP (1 << 15) /* Bit 15: Status of D+ data line */
-
-/* Device address register (DADDR) */
-
-#define USB_DADDR_ADD_SHIFT 0 /* Bits 0-7: Device address */
-#define USB_DADDR_ADD_MASK (0x7f << USB_DADDR_ADD_SHIFT)
-#define USB_DADDR_EF (1 << 7) /* Bit 8: Enable function */
-
-/* Endpoint registers (EPR) */
-
-#define USB_EPR_ADDRFIELD_SHIFT 0 /* Bits 0-3: Endpoint address */
-#define USB_EPR_ADDRFIELD_MASK (0x0f << USB_EPR_ADDRFIELD_SHIFT)
-#define USB_EPR_TXSTAT_SHIFT 4 /* Bits 4-5: Endpoint TX status bit */
-#define USB_EPR_TXSTAT_MASK (3 << USB_EPR_TXSTAT_SHIFT)
-# define USB_EPR_TXDIS (0 << USB_EPR_TXSTAT_SHIFT) /* Endpoint TX disabled */
-# define USB_EPR_TXSTALL (1 << USB_EPR_TXSTAT_SHIFT) /* Endpoint TX stalled */
-# define USB_EPR_TXNAK (2 << USB_EPR_TXSTAT_SHIFT) /* Endpoint TX NAKed */
-# define USB_EPR_TXVALID (3 << USB_EPR_TXSTAT_SHIFT) /* Endpoint TX valid */
-# define USB_EPR_TXDTOG1 (1 << USB_EPR_TXSTAT_SHIFT) /* Bit : Endpoint TX data toggle bit1 */
-# define USB_EPR_TXDTOG2 (2 << USB_EPR_TXSTAT_SHIFT) /* Bit : Endpoint TX data toggle bit2 */
-#define USB_EPR_DTOGTX (1 << 6) /* Bit 6: Endpoint data toggle TX */
-#define USB_EPR_CTRTX (1 << 7) /* Bit 7: Endpoint correct transfer TX */
-#define USB_EPR_KIND (1 << 8) /* Bit 8: Endpoint kind */
-#define USB_EPR_EPTYPE_SHIFT 9 /* Bits 9-10: Endpoint type */
-#define USB_EPR_EPTYPE_MASK (3 << USB_EPR_EPTYPE_SHIFT)
-# define USB_EPR_BULK (0 << USB_EPR_EPTYPE_SHIFT) /* Endpoint BULK */
-# define USB_EPR_CONTROL (1 << USB_EPR_EPTYPE_SHIFT) /* Endpoint CONTROL */
-# define USB_EPR_ISOC (2 << USB_EPR_EPTYPE_SHIFT)) /* Endpoint ISOCHRONOUS */
-# define USB_EPR_INTERRUPT (3 << USB_EPR_EPTYPE_SHIFT) /* Endpoint INTERRUPT */
-#define USB_EPR_SETUP (1 << 11) /* Bit 11: Endpoint setup */
-#define USB_EPR_RXSTAT_SHIFT 12 /* Bits 12-13: Endpoint RX status bit */
-#define USB_EPR_RXSTAT_MASK (3 << USB_EPR_RXSTAT_SHIFT)
-# define USB_EPR_RXDIS (0 << USB_EPR_RXSTAT_SHIFT) /* Endpoint RX disabled */
-# define USB_EPR_RXSTALL (1 << USB_EPR_RXSTAT_SHIFT) /* Endpoint RX stalled */
-# define USB_EPR_RXNAK (2 << USB_EPR_RXSTAT_SHIFT) /* Endpoint RX NAKed */
-# define USB_EPR_RXVALID (3 << USB_EPR_RXSTAT_SHIFT) /* Endpoint RX valid */
-# define USB_EPR_RXDTOG1 (1 << USB_EPR_RXSTAT_SHIFT) /* Endpoint RX data toggle bit1 */
-# define USB_EPR_RXDTOG2 (2 << USB_EPR_RXSTAT_SHIFT) /* Endpoint RX data toggle bit2 */
-#define USB_EPR_DTOGRX (1 << 14) /* Bit 14: Endpoint data toggle RX */
-#define USB_EPR_CTRRX (1 << 15) /* Bit 15: Endpoint correct transfer RX */
-
-/* Endpoint register mask (no toggle fields) */
-
-#define USB_EPR_NOTOGGLE_MASK (USB_EPR_CTRRX|USB_EPR_SETUP|USB_EPR_TFIELD|\
- USB_EPR_KIND|USB_EPR_CTRTX|USB_EPR_ADDRFIELD)
-
-/* Toggles only */
-
-#define USB_EPR_TXDTOG_MASK (USB_EPR_TXSTAT_MASK|USB_EPR_NOTOGGLE_MASK)
-#define USB_EPR_RXDTOG_MASK (USB_EPR_RXSTAT_MASK|USB_EPR_NOTOGGLE_MASK)
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-/************************************************************************************
- * Public Functions
- ************************************************************************************/
-
-#endif /* __ARCH_ARM_SRC_STR71X_STR71X_USB_H */
+/************************************************************************************ + * arch/arm/src/str71x/str71x_usb.h + * + * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STR71X_STR71X_USB_H +#define __ARCH_ARM_SRC_STR71X_STR71X_USB_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +#include "str71x_map.h" + +/************************************************************************************ + * Pre-procesor Definitions + ************************************************************************************/ + +/* USB registers ********************************************************************/ + +#define STR71X_USB_NENDPNTS (16) +#define STR71X_USB_EPR(ep) (STR71X_USB_BASE + ((ep) << 4)) +#define STR71X_USB_EP0R (STR71X_USB_BASE + 0x0000) /* Endpoint 0 */ +#define STR71X_USB_EP1R (STR71X_USB_BASE + 0x0004) /* Endpoint 1 */ +#define STR71X_USB_EP2R (STR71X_USB_BASE + 0x0008) /* Endpoint 2 */ +#define STR71X_USB_EP3R (STR71X_USB_BASE + 0x000c) /* Endpoint 3 */ +#define STR71X_USB_EP4R (STR71X_USB_BASE + 0x0010) /* Endpoint 4 */ +#define STR71X_USB_EP5R (STR71X_USB_BASE + 0x0014) /* Endpoint 5 */ +#define STR71X_USB_EP6R (STR71X_USB_BASE + 0x0018) /* Endpoint 6 */ +#define STR71X_USB_EP7R (STR71X_USB_BASE + 0x001c) /* Endpoint 7 */ +#define STR71X_USB_EP8R (STR71X_USB_BASE + 0x0020) /* Endpoint 8 */ +#define STR71X_USB_EP9R (STR71X_USB_BASE + 0x0024) /* Endpoint 9 */ +#define STR71X_USB_EP10R (STR71X_USB_BASE + 0x0028) /* Endpoint 10 */ +#define STR71X_USB_EP11R (STR71X_USB_BASE + 0x002c) /* Endpoint 11 */ +#define STR71X_USB_EP12R (STR71X_USB_BASE + 0x0030) /* Endpoint 12 */ +#define STR71X_USB_EP13R (STR71X_USB_BASE + 0x0034) /* Endpoint 13 */ +#define STR71X_USB_EP14R (STR71X_USB_BASE + 0x0038) /* Endpoint 14 */ +#define STR71X_USB_EP15R (STR71X_USB_BASE + 0x003c) /* Endpoint 15 */ +#define STR71X_USB_CNTR (STR71X_USB_BASE + 0x0040) /* Control register */ +#define STR71X_USB_ISTR (STR71X_USB_BASE + 0x0044) /* Interrupt status register */ +#define STR71X_USB_FNR (STR71X_USB_BASE + 0x0048) /* Frame number register */ +#define STR71X_USB_DADDR (STR71X_USB_BASE + 0x004C) /* Device address register */ +#define STR71X_USB_BTABLE (STR71X_USB_BASE + 0x0050) /* Buffer Table address register */ + +/* Register bit settings ***********************************************************/ + +/* Control Register (CNTR) */ + +#define USB_CNTR_FRES (1 << 0) /* Bit 0: Force usb reset */ +#define USB_CNTR_PDWN (1 << 1) /* Bit 1: Power down */ +#define USB_CNTR_LPMODE (1 << 2) /* Bit 2: Low-power mode */ +#define USB_CNTR_FSUSP (1 << 3) /* Bit 3: Force suspend */ +#define USB_CNTR_RESUME (1 << 4) /* Bit 4: Resume request */ +#define USB_CNTR_ESOFM (1 << 8) /* Bit 8: Expected start of frame */ +#define USB_CNTR_SOFM (1 << 9) /* Bit 9: Start of frame */ +#define USB_CNTR_RESETM (1 << 10) /* Bit 10: Reset */ +#define USB_CNTR_SUSPM (1 << 11) /* Bit 11: Suspend */ +#define USB_CNTR_WKUPM (1 << 12) /* Bit 12: Wake up */ +#define USB_CNTR_ERRM (1 << 13) /* Bit 13: Error */ +#define USB_CNTR_DOVRM (1 << 14) /* Bit 14: DMA over/underrun */ +#define USB_CNTR_CTRM (1 << 15) /* Bit 15: Correct transfer */ + +/* Interrupt status register (ISTR) */ + +#define USB_ISTR_EPID_SHIFT 0 /* Bits 0-3: Endpoint Identifier */ +#define USB_ISTR_EPID_MASK (0x0f << USB_ISTR_EPID_SHIFT) +#define USB_ISTR_DIR (1 << 4) /* Bit 4: DIRection of transaction */ +#define USB_ISTR_ESOF (1 << 8) /* Bit 8: Expected start of frame */ +#define USB_ISTR_SOF (1 << 9) /* Bit 9: Start of frame */ +#define USB_ISTR_RESET (1 << 10) /* Bit 10: Reset */ +#define USB_ISTR_SUSP (1 << 11) /* Bit 11: Suspend */ +#define USB_ISTR_WKUP (1 << 12) /* Bit 12: Wakeup */ +#define USB_ISTR_ERR (1 << 13) /* Bit 13: Error */ +#define USB_ISTR_DOVR (1 << 14) /* Bit 14: DMA Over/underrun */ +#define USB_ISTR_CTR (1 << 15) /* Bit 15: Correct Transfer */ + +/* Frame number register (FNR) */ + +#define USB_FNR_FN_SHIFT 0 /* Bit 0-10: Frame number */ +#define USB_FNR_LSOF_SHIFT 11 /* Bits 11-12 : Lost SOF */ +#define USB_FNR_LSOF_MASK (3 << USB_FNR_LSOF_SHIFT) +#define USB_FNR_FN_MASK (0x07ff << USB_FNR_FN_SHIFT) +#define USB_FNR_LCK (1 << 13) /* Bit 13: Locked */ +#define USB_FNR_RXDM (1 << 14) /* Bit 14: Status of D- data line */ +#define USB_FNR_RXDP (1 << 15) /* Bit 15: Status of D+ data line */ + +/* Device address register (DADDR) */ + +#define USB_DADDR_ADD_SHIFT 0 /* Bits 0-7: Device address */ +#define USB_DADDR_ADD_MASK (0x7f << USB_DADDR_ADD_SHIFT) +#define USB_DADDR_EF (1 << 7) /* Bit 8: Enable function */ + +/* Endpoint registers (EPR) */ + +#define USB_EPR_ADDRFIELD_SHIFT 0 /* Bits 0-3: Endpoint address */ +#define USB_EPR_ADDRFIELD_MASK (0x0f << USB_EPR_ADDRFIELD_SHIFT) +#define USB_EPR_TXSTAT_SHIFT 4 /* Bits 4-5: Endpoint TX status bit */ +#define USB_EPR_TXSTAT_MASK (3 << USB_EPR_TXSTAT_SHIFT) +# define USB_EPR_TXDIS (0 << USB_EPR_TXSTAT_SHIFT) /* Endpoint TX disabled */ +# define USB_EPR_TXSTALL (1 << USB_EPR_TXSTAT_SHIFT) /* Endpoint TX stalled */ +# define USB_EPR_TXNAK (2 << USB_EPR_TXSTAT_SHIFT) /* Endpoint TX NAKed */ +# define USB_EPR_TXVALID (3 << USB_EPR_TXSTAT_SHIFT) /* Endpoint TX valid */ +# define USB_EPR_TXDTOG1 (1 << USB_EPR_TXSTAT_SHIFT) /* Bit : Endpoint TX data toggle bit1 */ +# define USB_EPR_TXDTOG2 (2 << USB_EPR_TXSTAT_SHIFT) /* Bit : Endpoint TX data toggle bit2 */ +#define USB_EPR_DTOGTX (1 << 6) /* Bit 6: Endpoint data toggle TX */ +#define USB_EPR_CTRTX (1 << 7) /* Bit 7: Endpoint correct transfer TX */ +#define USB_EPR_KIND (1 << 8) /* Bit 8: Endpoint kind */ +#define USB_EPR_EPTYPE_SHIFT 9 /* Bits 9-10: Endpoint type */ +#define USB_EPR_EPTYPE_MASK (3 << USB_EPR_EPTYPE_SHIFT) +# define USB_EPR_BULK (0 << USB_EPR_EPTYPE_SHIFT) /* Endpoint BULK */ +# define USB_EPR_CONTROL (1 << USB_EPR_EPTYPE_SHIFT) /* Endpoint CONTROL */ +# define USB_EPR_ISOC (2 << USB_EPR_EPTYPE_SHIFT)) /* Endpoint ISOCHRONOUS */ +# define USB_EPR_INTERRUPT (3 << USB_EPR_EPTYPE_SHIFT) /* Endpoint INTERRUPT */ +#define USB_EPR_SETUP (1 << 11) /* Bit 11: Endpoint setup */ +#define USB_EPR_RXSTAT_SHIFT 12 /* Bits 12-13: Endpoint RX status bit */ +#define USB_EPR_RXSTAT_MASK (3 << USB_EPR_RXSTAT_SHIFT) +# define USB_EPR_RXDIS (0 << USB_EPR_RXSTAT_SHIFT) /* Endpoint RX disabled */ +# define USB_EPR_RXSTALL (1 << USB_EPR_RXSTAT_SHIFT) /* Endpoint RX stalled */ +# define USB_EPR_RXNAK (2 << USB_EPR_RXSTAT_SHIFT) /* Endpoint RX NAKed */ +# define USB_EPR_RXVALID (3 << USB_EPR_RXSTAT_SHIFT) /* Endpoint RX valid */ +# define USB_EPR_RXDTOG1 (1 << USB_EPR_RXSTAT_SHIFT) /* Endpoint RX data toggle bit1 */ +# define USB_EPR_RXDTOG2 (2 << USB_EPR_RXSTAT_SHIFT) /* Endpoint RX data toggle bit2 */ +#define USB_EPR_DTOGRX (1 << 14) /* Bit 14: Endpoint data toggle RX */ +#define USB_EPR_CTRRX (1 << 15) /* Bit 15: Endpoint correct transfer RX */ + +/* Endpoint register mask (no toggle fields) */ + +#define USB_EPR_NOTOGGLE_MASK (USB_EPR_CTRRX|USB_EPR_SETUP|USB_EPR_TFIELD|\ + USB_EPR_KIND|USB_EPR_CTRTX|USB_EPR_ADDRFIELD) + +/* Toggles only */ + +#define USB_EPR_TXDTOG_MASK (USB_EPR_TXSTAT_MASK|USB_EPR_NOTOGGLE_MASK) +#define USB_EPR_RXDTOG_MASK (USB_EPR_RXSTAT_MASK|USB_EPR_NOTOGGLE_MASK) + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_STR71X_STR71X_USB_H */ diff --git a/nuttx/arch/arm/src/str71x/str71x_wdog.h b/nuttx/arch/arm/src/str71x/str71x_wdog.h index 75b89ab89..81caf6a25 100644 --- a/nuttx/arch/arm/src/str71x/str71x_wdog.h +++ b/nuttx/arch/arm/src/str71x/str71x_wdog.h @@ -1,75 +1,75 @@ -/************************************************************************************
- * arch/arm/src/str71x/str71x_wdog.h
- *
- * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_STR71X_STR71X_WDOG_H
-#define __ARCH_ARM_SRC_STR71X_STR71X_WDOG_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-
-#include "str71x_map.h"
-
-/************************************************************************************
- * Pre-procesor Definitions
- ************************************************************************************/
-
-/* Registers ************************************************************************/
-
-#define STR71X_WDOG_CR (STR71X_WDOG_BASE + 0x0000) /* 16-bits wide */
-#define STR71X_WDOG_PR (STR71X_WDOG_BASE + 0x0004) /* 16-bits wide */
-#define STR71X_WDOG_VR (STR71X_WDOG_BASE + 0x0008) /* 16-bits wide */
-#define STR71X_WDOG_CNT (STR71X_WDOG_BASE + 0x000c) /* 16-bits wide */
-#define STR71X_WDOG_SR (STR71X_WDOG_BASE + 0x0010) /* 16-bits wide */
-#define STR71X_WDOG_MR (STR71X_WDOG_BASE + 0x0014) /* 16-bits wide */
-#define STR71X_WDOG_KR (STR71X_WDOG_BASE + 0x00018 /* 16-bits wide */
-
-/* Register bit settings ***********************************************************/
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-/************************************************************************************
- * Public Functions
- ************************************************************************************/
-
-#endif /* __ARCH_ARM_SRC_STR71X_STR71X_WDOG_H */
+/************************************************************************************ + * arch/arm/src/str71x/str71x_wdog.h + * + * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STR71X_STR71X_WDOG_H +#define __ARCH_ARM_SRC_STR71X_STR71X_WDOG_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +#include "str71x_map.h" + +/************************************************************************************ + * Pre-procesor Definitions + ************************************************************************************/ + +/* Registers ************************************************************************/ + +#define STR71X_WDOG_CR (STR71X_WDOG_BASE + 0x0000) /* 16-bits wide */ +#define STR71X_WDOG_PR (STR71X_WDOG_BASE + 0x0004) /* 16-bits wide */ +#define STR71X_WDOG_VR (STR71X_WDOG_BASE + 0x0008) /* 16-bits wide */ +#define STR71X_WDOG_CNT (STR71X_WDOG_BASE + 0x000c) /* 16-bits wide */ +#define STR71X_WDOG_SR (STR71X_WDOG_BASE + 0x0010) /* 16-bits wide */ +#define STR71X_WDOG_MR (STR71X_WDOG_BASE + 0x0014) /* 16-bits wide */ +#define STR71X_WDOG_KR (STR71X_WDOG_BASE + 0x00018 /* 16-bits wide */ + +/* Register bit settings ***********************************************************/ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_STR71X_STR71X_WDOG_H */ diff --git a/nuttx/arch/arm/src/str71x/str71x_xti.c b/nuttx/arch/arm/src/str71x/str71x_xti.c index 3143ad76f..3ef0a803d 100755 --- a/nuttx/arch/arm/src/str71x/str71x_xti.c +++ b/nuttx/arch/arm/src/str71x/str71x_xti.c @@ -2,7 +2,7 @@ * arch/arm/src/str71x/str71x_xti.c * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/str71x/str71x_xti.h b/nuttx/arch/arm/src/str71x/str71x_xti.h index d9458c196..638ab4f87 100644 --- a/nuttx/arch/arm/src/str71x/str71x_xti.h +++ b/nuttx/arch/arm/src/str71x/str71x_xti.h @@ -1,105 +1,105 @@ -/************************************************************************************
- * arch/arm/src/str71x/str71x_xti.h
- *
- * Copyright (C) 2008-2010 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_STR71X_STR71X_XTI_H
-#define __ARCH_ARM_SRC_STR71X_STR71X_XTI_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-
-#include "str71x_map.h"
-
-/************************************************************************************
- * Pre-procesor Definitions
- ************************************************************************************/
-
-/* External Interupt Controller (XTI) registers *************************************/
-
-#define STR71X_XTI_SR (STR71X_XTI_BASE + 0x001c) /* 8-bits wide */
-#define STR71X_XTI_CTRL (STR71X_XTI_BASE + 0x0024) /* 8-bits wide */
-#define STR71X_XTI_MRH (STR71X_XTI_BASE + 0x0028) /* 8-bits wide */
-#define STR71X_XTI_MRL (STR71X_XTI_BASE + 0x002c) /* 8-bits wide */
-#define STR71X_XTI_TRH (STR71X_XTI_BASE + 0x0030) /* 8-bits wide */
-#define STR71X_XTI_TRL (STR71X_XTI_BASE + 0x0034) /* 8-bits wide */
-#define STR71X_XTI_PRH (STR71X_XTI_BASE + 0x0038) /* 8-bits wide */
-#define STR71X_XTI_PRL (STR71X_XTI_BASE + 0x003c) /* 8-bits wide */
-
-/* Register bit settings ************************************************************/
-
-/* Control register (CTRL) */
-
-#define STR71X_XTICTRL_WKUPINT (0x01)
-#define STR71X_XTICTRL_ID1S (0x02)
-#define STR71X_XTICTRL_STOP (0x04)
-
-/* Most registers are address by external interrupt line in two 8-bit high and low
- * registers
- */
-
-#define STR71X_XTI_LINE(n) (1 << (n))
-#define STR71X_XTI_LINE0 STR71X_XTI_LINE(0) /* Low register */
-#define STR71X_XTI_LINE1 STR71X_XTI_LINE(1)
-#define STR71X_XTI_LINE2 STR71X_XTI_LINE(2)
-#define STR71X_XTI_LINE3 STR71X_XTI_LINE(3)
-#define STR71X_XTI_LINE4 STR71X_XTI_LINE(4)
-#define STR71X_XTI_LINE5 STR71X_XTI_LINE(5)
-#define STR71X_XTI_LINE6 STR71X_XTI_LINE(6)
-#define STR71X_XTI_LINE7 STR71X_XTI_LINE(7)
-
-#define STR71X_XTI_LINE8 STR71X_XTI_LINE(8) /* High register */
-#define STR71X_XTI_LINE9 STR71X_XTI_LINE(9)
-#define STR71X_XTI_LINE10 STR71X_XTI_LINE(10)
-#define STR71X_XTI_LINE11 STR71X_XTI_LINE(11)
-#define STR71X_XTI_LINE12 STR71X_XTI_LINE(12)
-#define STR71X_XTI_LINE13 STR71X_XTI_LINE(13)
-#define STR71X_XTI_LINE14 STR71X_XTI_LINE(14)
-#define STR71X_XTI_LINE15 STR71X_XTI_LINE(15)
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-/************************************************************************************
- * Public Functions
- ************************************************************************************/
-
-#endif /* _ARCH_ARM_SRC_STR71X_STR71X_XTI_H */
+/************************************************************************************ + * arch/arm/src/str71x/str71x_xti.h + * + * Copyright (C) 2008-2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STR71X_STR71X_XTI_H +#define __ARCH_ARM_SRC_STR71X_STR71X_XTI_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +#include "str71x_map.h" + +/************************************************************************************ + * Pre-procesor Definitions + ************************************************************************************/ + +/* External Interupt Controller (XTI) registers *************************************/ + +#define STR71X_XTI_SR (STR71X_XTI_BASE + 0x001c) /* 8-bits wide */ +#define STR71X_XTI_CTRL (STR71X_XTI_BASE + 0x0024) /* 8-bits wide */ +#define STR71X_XTI_MRH (STR71X_XTI_BASE + 0x0028) /* 8-bits wide */ +#define STR71X_XTI_MRL (STR71X_XTI_BASE + 0x002c) /* 8-bits wide */ +#define STR71X_XTI_TRH (STR71X_XTI_BASE + 0x0030) /* 8-bits wide */ +#define STR71X_XTI_TRL (STR71X_XTI_BASE + 0x0034) /* 8-bits wide */ +#define STR71X_XTI_PRH (STR71X_XTI_BASE + 0x0038) /* 8-bits wide */ +#define STR71X_XTI_PRL (STR71X_XTI_BASE + 0x003c) /* 8-bits wide */ + +/* Register bit settings ************************************************************/ + +/* Control register (CTRL) */ + +#define STR71X_XTICTRL_WKUPINT (0x01) +#define STR71X_XTICTRL_ID1S (0x02) +#define STR71X_XTICTRL_STOP (0x04) + +/* Most registers are address by external interrupt line in two 8-bit high and low + * registers + */ + +#define STR71X_XTI_LINE(n) (1 << (n)) +#define STR71X_XTI_LINE0 STR71X_XTI_LINE(0) /* Low register */ +#define STR71X_XTI_LINE1 STR71X_XTI_LINE(1) +#define STR71X_XTI_LINE2 STR71X_XTI_LINE(2) +#define STR71X_XTI_LINE3 STR71X_XTI_LINE(3) +#define STR71X_XTI_LINE4 STR71X_XTI_LINE(4) +#define STR71X_XTI_LINE5 STR71X_XTI_LINE(5) +#define STR71X_XTI_LINE6 STR71X_XTI_LINE(6) +#define STR71X_XTI_LINE7 STR71X_XTI_LINE(7) + +#define STR71X_XTI_LINE8 STR71X_XTI_LINE(8) /* High register */ +#define STR71X_XTI_LINE9 STR71X_XTI_LINE(9) +#define STR71X_XTI_LINE10 STR71X_XTI_LINE(10) +#define STR71X_XTI_LINE11 STR71X_XTI_LINE(11) +#define STR71X_XTI_LINE12 STR71X_XTI_LINE(12) +#define STR71X_XTI_LINE13 STR71X_XTI_LINE(13) +#define STR71X_XTI_LINE14 STR71X_XTI_LINE(14) +#define STR71X_XTI_LINE15 STR71X_XTI_LINE(15) + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* _ARCH_ARM_SRC_STR71X_STR71X_XTI_H */ |