summaryrefslogtreecommitdiff
path: root/nuttx/arch/mips/src/pic32mz/chip/pic32mz-uart.h
blob: 9b3dc3286bf76ed3fe9b81da291e474342c783c7 (plain) (blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
/************************************************************************************
 * arch/mips/src/pic32mx/pic32mx-uart.h
 *
 *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
 *   Author: Gregory Nutt <gnutt@nuttx.org>
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 * 3. Neither the name NuttX nor the names of its contributors may be
 *    used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 *
 ************************************************************************************/

#ifndef __ARCH_MIPS_SRC_PIC32MZ_PIC32MZ_CHIP_UART_H
#define __ARCH_MIPS_SRC_PIC32MZ_PIC32MZ_CHIP_UART_H

/************************************************************************************
 * Included Files
 ************************************************************************************/

#include <nuttx/config.h>

#include <arch/pic32mz/chip.h>
#include "pic32mx-memorymap.h"

/************************************************************************************
 * Pre-processor Definitions
 ************************************************************************************/
/* Register Offsets *****************************************************************/

#define PIC32MZ_UART_MODE_OFFSET    0x0000 /* UARTx mode register */
#define PIC32MZ_UART_MODECLR_OFFSET 0x0004 /* UARTx mode clear register */
#define PIC32MZ_UART_MODESET_OFFSET 0x0008 /* UARTx mode set register */
#define PIC32MZ_UART_MODEINV_OFFSET 0x000c /* UARTx mode invert register */

#define PIC32MZ_UART_STA_OFFSET     0x0010 /* UARTx status and control register */
#define PIC32MZ_UART_STACLR_OFFSET  0x0014 /* UARTx status and control clear register */
#define PIC32MZ_UART_STASET_OFFSET  0x0018 /* UARTx status and control set register */
#define PIC32MZ_UART_STAINV_OFFSET  0x001c /* UARTx status and control invert register */

#define PIC32MZ_UART_TXREG_OFFSET   0x0020 /* UARTx transmit register */
#define PIC32MZ_UART_RXREG_OFFSET   0x0030 /* UARTx receive register */

#define PIC32MZ_UART_BRG_OFFSET     0x0040 /* UARTx baud rate register */
#define PIC32MZ_UART_BRGCLR_OFFSET  0x0044 /* UARTx baud rate clear register */
#define PIC32MZ_UART_BRGSET_OFFSET  0x0048 /* UARTx baud rate set register */
#define PIC32MZ_UART_BRGINV_OFFSET  0x004c /* UARTx baud rate invert register */

/* Register Addresses ****************************************************************/

#if CHIP_NUARTS > 0
#  define PIC32MZ_UART1_MODE        (PIC32MZ_UART1_K1BASE+PIC32MZ_UART_MODE_OFFSET)
#  define PIC32MZ_UART1_MODECLR     (PIC32MZ_UART1_K1BASE+PIC32MZ_UART_MODECLR_OFFSET)
#  define PIC32MZ_UART1_MODESET     (PIC32MZ_UART1_K1BASE+PIC32MZ_UART_MODESET_OFFSET)
#  define PIC32MZ_UART1_MODEINV     (PIC32MZ_UART1_K1BASE+PIC32MZ_UART_MODEINV_OFFSET)
#  define PIC32MZ_UART1_STA         (PIC32MZ_UART1_K1BASE+PIC32MZ_UART_STA_OFFSET)
#  define PIC32MZ_UART1_STACLR      (PIC32MZ_UART1_K1BASE+PIC32MZ_UART_STACLR_OFFSET)
#  define PIC32MZ_UART1_STASET      (PIC32MZ_UART1_K1BASE+PIC32MZ_UART_STASET_OFFSET)
#  define PIC32MZ_UART1_STAINV      (PIC32MZ_UART1_K1BASE+PIC32MZ_UART_STAINV_OFFSET)
#  define PIC32MZ_UART1_TXREG       (PIC32MZ_UART1_K1BASE+PIC32MZ_UART_TXREG_OFFSET)
#  define PIC32MZ_UART1_RXREG       (PIC32MZ_UART1_K1BASE+PIC32MZ_UART_RXREG_OFFSET)
#  define PIC32MZ_UART1_BRG         (PIC32MZ_UART1_K1BASE+PIC32MZ_UART_BRG_OFFSET)
#  define PIC32MZ_UART1_BRGCLR      (PIC32MZ_UART1_K1BASE+PIC32MZ_UART_BRGCLR_OFFSET)
#  define PIC32MZ_UART1_BRGSET      (PIC32MZ_UART1_K1BASE+PIC32MZ_UART_BRGSET_OFFSET)
#  define PIC32MZ_UART1_BRGINV      (PIC32MZ_UART1_K1BASE+PIC32MZ_UART_BRGINV_OFFSET)
#endif

#if CHIP_NUARTS > 1
#  define PIC32MZ_UART2_MODE        (PIC32MZ_UART2_K1BASE+PIC32MZ_UART_MODE_OFFSET)
#  define PIC32MZ_UART2_MODECLR     (PIC32MZ_UART2_K1BASE+PIC32MZ_UART_MODECLR_OFFSET)
#  define PIC32MZ_UART2_MODESET     (PIC32MZ_UART2_K1BASE+PIC32MZ_UART_MODESET_OFFSET)
#  define PIC32MZ_UART2_MODEINV     (PIC32MZ_UART2_K1BASE+PIC32MZ_UART_MODEINV_OFFSET)
#  define PIC32MZ_UART2_STA         (PIC32MZ_UART2_K1BASE+PIC32MZ_UART_STA_OFFSET)
#  define PIC32MZ_UART2_STACLR      (PIC32MZ_UART2_K1BASE+PIC32MZ_UART_STACLR_OFFSET)
#  define PIC32MZ_UART2_STASET      (PIC32MZ_UART2_K1BASE+PIC32MZ_UART_STASET_OFFSET)
#  define PIC32MZ_UART2_STAINV      (PIC32MZ_UART2_K1BASE+PIC32MZ_UART_STAINV_OFFSET)
#  define PIC32MZ_UART2_TXREG       (PIC32MZ_UART2_K1BASE+PIC32MZ_UART_TXREG_OFFSET)
#  define PIC32MZ_UART2_RXREG       (PIC32MZ_UART2_K1BASE+PIC32MZ_UART_RXREG_OFFSET)
#  define PIC32MZ_UART2_BRG         (PIC32MZ_UART2_K1BASE+PIC32MZ_UART_BRG_OFFSET)
#  define PIC32MZ_UART2_BRGCLR      (PIC32MZ_UART2_K1BASE+PIC32MZ_UART_BRGCLR_OFFSET)
#  define PIC32MZ_UART2_BRGSET      (PIC32MZ_UART2_K1BASE+PIC32MZ_UART_BRGSET_OFFSET)
#  define PIC32MZ_UART2_BRGINV      (PIC32MZ_UART2_K1BASE+PIC32MZ_UART_BRGINV_OFFSET)
#endif

#if CHIP_NUARTS > 2
#  define PIC32MZ_UART3_MODE        (PIC32MZ_UART3_K1BASE+PIC32MZ_UART_MODE_OFFSET)
#  define PIC32MZ_UART3_MODECLR     (PIC32MZ_UART3_K1BASE+PIC32MZ_UART_MODECLR_OFFSET)
#  define PIC32MZ_UART3_MODESET     (PIC32MZ_UART3_K1BASE+PIC32MZ_UART_MODESET_OFFSET)
#  define PIC32MZ_UART3_MODEINV     (PIC32MZ_UART3_K1BASE+PIC32MZ_UART_MODEINV_OFFSET)
#  define PIC32MZ_UART3_STA         (PIC32MZ_UART3_K1BASE+PIC32MZ_UART_STA_OFFSET)
#  define PIC32MZ_UART3_STACLR      (PIC32MZ_UART3_K1BASE+PIC32MZ_UART_STACLR_OFFSET)
#  define PIC32MZ_UART3_STASET      (PIC32MZ_UART3_K1BASE+PIC32MZ_UART_STASET_OFFSET)
#  define PIC32MZ_UART3_STAINV      (PIC32MZ_UART3_K1BASE+PIC32MZ_UART_STAINV_OFFSET)
#  define PIC32MZ_UART3_TXREG       (PIC32MZ_UART3_K1BASE+PIC32MZ_UART_TXREG_OFFSET)
#  define PIC32MZ_UART3_RXREG       (PIC32MZ_UART3_K1BASE+PIC32MZ_UART_RXREG_OFFSET)
#  define PIC32MZ_UART3_BRG         (PIC32MZ_UART3_K1BASE+PIC32MZ_UART_BRG_OFFSET)
#  define PIC32MZ_UART3_BRGCLR      (PIC32MZ_UART3_K1BASE+PIC32MZ_UART_BRGCLR_OFFSET)
#  define PIC32MZ_UART3_BRGSET      (PIC32MZ_UART3_K1BASE+PIC32MZ_UART_BRGSET_OFFSET)
#  define PIC32MZ_UART3_BRGINV      (PIC32MZ_UART3_K1BASE+PIC32MZ_UART_BRGINV_OFFSET)
#endif

#if CHIP_NUARTS > 3
#  define PIC32MZ_UART4_MODE        (PIC32MZ_UART4_K1BASE+PIC32MZ_UART_MODE_OFFSET)
#  define PIC32MZ_UART4_MODECLR     (PIC32MZ_UART4_K1BASE+PIC32MZ_UART_MODECLR_OFFSET)
#  define PIC32MZ_UART4_MODESET     (PIC32MZ_UART4_K1BASE+PIC32MZ_UART_MODESET_OFFSET)
#  define PIC32MZ_UART4_MODEINV     (PIC32MZ_UART4_K1BASE+PIC32MZ_UART_MODEINV_OFFSET)
#  define PIC32MZ_UART4_STA         (PIC32MZ_UART4_K1BASE+PIC32MZ_UART_STA_OFFSET)
#  define PIC32MZ_UART4_STACLR      (PIC32MZ_UART4_K1BASE+PIC32MZ_UART_STACLR_OFFSET)
#  define PIC32MZ_UART4_STASET      (PIC32MZ_UART4_K1BASE+PIC32MZ_UART_STASET_OFFSET)
#  define PIC32MZ_UART4_STAINV      (PIC32MZ_UART4_K1BASE+PIC32MZ_UART_STAINV_OFFSET)
#  define PIC32MZ_UART4_TXREG       (PIC32MZ_UART4_K1BASE+PIC32MZ_UART_TXREG_OFFSET)
#  define PIC32MZ_UART4_RXREG       (PIC32MZ_UART4_K1BASE+PIC32MZ_UART_RXREG_OFFSET)
#  define PIC32MZ_UART4_BRG         (PIC32MZ_UART4_K1BASE+PIC32MZ_UART_BRG_OFFSET)
#  define PIC32MZ_UART4_BRGCLR      (PIC32MZ_UART4_K1BASE+PIC32MZ_UART_BRGCLR_OFFSET)
#  define PIC32MZ_UART4_BRGSET      (PIC32MZ_UART4_K1BASE+PIC32MZ_UART_BRGSET_OFFSET)
#  define PIC32MZ_UART4_BRGINV      (PIC32MZ_UART4_K1BASE+PIC32MZ_UART_BRGINV_OFFSET)
#endif

#if CHIP_NUARTS > 4
#  define PIC32MZ_UART5_MODE        (PIC32MZ_UART5_K1BASE+PIC32MZ_UART_MODE_OFFSET)
#  define PIC32MZ_UART5_MODECLR     (PIC32MZ_UART5_K1BASE+PIC32MZ_UART_MODECLR_OFFSET)
#  define PIC32MZ_UART5_MODESET     (PIC32MZ_UART5_K1BASE+PIC32MZ_UART_MODESET_OFFSET)
#  define PIC32MZ_UART5_MODEINV     (PIC32MZ_UART5_K1BASE+PIC32MZ_UART_MODEINV_OFFSET)
#  define PIC32MZ_UART5_STA         (PIC32MZ_UART5_K1BASE+PIC32MZ_UART_STA_OFFSET)
#  define PIC32MZ_UART5_STACLR      (PIC32MZ_UART5_K1BASE+PIC32MZ_UART_STACLR_OFFSET)
#  define PIC32MZ_UART5_STASET      (PIC32MZ_UART5_K1BASE+PIC32MZ_UART_STASET_OFFSET)
#  define PIC32MZ_UART5_STAINV      (PIC32MZ_UART5_K1BASE+PIC32MZ_UART_STAINV_OFFSET)
#  define PIC32MZ_UART5_TXREG       (PIC32MZ_UART5_K1BASE+PIC32MZ_UART_TXREG_OFFSET)
#  define PIC32MZ_UART5_RXREG       (PIC32MZ_UART5_K1BASE+PIC32MZ_UART_RXREG_OFFSET)
#  define PIC32MZ_UART5_BRG         (PIC32MZ_UART5_K1BASE+PIC32MZ_UART_BRG_OFFSET)
#  define PIC32MZ_UART5_BRGCLR      (PIC32MZ_UART5_K1BASE+PIC32MZ_UART_BRGCLR_OFFSET)
#  define PIC32MZ_UART5_BRGSET      (PIC32MZ_UART5_K1BASE+PIC32MZ_UART_BRGSET_OFFSET)
#  define PIC32MZ_UART5_BRGINV      (PIC32MZ_UART5_K1BASE+PIC32MZ_UART_BRGINV_OFFSET)
#endif

#if CHIP_NUARTS > 5
#  define PIC32MZ_UART6_MODE        (PIC32MZ_UART6_K1BASE+PIC32MZ_UART_MODE_OFFSET)
#  define PIC32MZ_UART6_MODECLR     (PIC32MZ_UART6_K1BASE+PIC32MZ_UART_MODECLR_OFFSET)
#  define PIC32MZ_UART6_MODESET     (PIC32MZ_UART6_K1BASE+PIC32MZ_UART_MODESET_OFFSET)
#  define PIC32MZ_UART6_MODEINV     (PIC32MZ_UART6_K1BASE+PIC32MZ_UART_MODEINV_OFFSET)
#  define PIC32MZ_UART6_STA         (PIC32MZ_UART6_K1BASE+PIC32MZ_UART_STA_OFFSET)
#  define PIC32MZ_UART6_STACLR      (PIC32MZ_UART6_K1BASE+PIC32MZ_UART_STACLR_OFFSET)
#  define PIC32MZ_UART6_STASET      (PIC32MZ_UART6_K1BASE+PIC32MZ_UART_STASET_OFFSET)
#  define PIC32MZ_UART6_STAINV      (PIC32MZ_UART6_K1BASE+PIC32MZ_UART_STAINV_OFFSET)
#  define PIC32MZ_UART6_TXREG       (PIC32MZ_UART6_K1BASE+PIC32MZ_UART_TXREG_OFFSET)
#  define PIC32MZ_UART6_RXREG       (PIC32MZ_UART6_K1BASE+PIC32MZ_UART_RXREG_OFFSET)
#  define PIC32MZ_UART6_BRG         (PIC32MZ_UART6_K1BASE+PIC32MZ_UART_BRG_OFFSET)
#  define PIC32MZ_UART6_BRGCLR      (PIC32MZ_UART6_K1BASE+PIC32MZ_UART_BRGCLR_OFFSET)
#  define PIC32MZ_UART6_BRGSET      (PIC32MZ_UART6_K1BASE+PIC32MZ_UART_BRGSET_OFFSET)
#  define PIC32MZ_UART6_BRGINV      (PIC32MZ_UART6_K1BASE+PIC32MZ_UART_BRGINV_OFFSET)
#endif

/* Register Bit-Field Definitions ****************************************************/

/* UARTx mode register */

#define UART_MODE_STSEL             (1 << 0)  /* Bit 0:  Stop selection 1=2 stop bits */
#define UART_MODE_PDSEL_SHIFT       (1)       /* Bits: 1-2: Parity and data selection */
#define UART_MODE_PDSEL_MASK        (3 << UART_MODE_PDSEL_SHIFT)
#  define UART_MODE_PDSEL_8NONE     (0 << UART_MODE_PDSEL_SHIFT) /* 8-bit data, no parity */
#  define UART_MODE_PDSEL_8EVEN     (1 << UART_MODE_PDSEL_SHIFT) /* 8-bit data, even parity */
#  define UART_MODE_PDSEL_8ODD      (2 << UART_MODE_PDSEL_SHIFT) /* 8-bit data, odd parity */
#  define UART_MODE_PDSEL_9NONE     (3 << UART_MODE_PDSEL_SHIFT) /* 9-bit data, no parity */
#define UART_MODE_BRGH              (1 << 3)  /* Bit 3:  High baud rate enable */
#define UART_MODE_RXINV             (1 << 4)  /* Bit 4:  Receive polarity inversion */
#define UART_MODE_ABAUD             (1 << 5)  /* Bit 5:  Auto-baud enable */
#define UART_MODE_LPBACK            (1 << 6)  /* Bit 6:  UARTx loopback mode select */
#define UART_MODE_WAKE              (1 << 7)  /* Bit 7:  Enable wake-up on start bit detect during sleep mode */
#define UART_MODE_UEN_SHIFT         (8)       /* Bits: 8-9: UARTx enable */
#define UART_MODE_UEN_MASK          (3 << UART_MODE_UEN_SHIFT)
#  define UART_MODE_UEN_PORT        (0 << UART_MODE_UEN_SHIFT) /* UxCTS+UxRTS/UxBCLK=PORTx register */
#  define UART_MODE_UEN_ENR_CPORT   (1 << UART_MODE_UEN_SHIFT) /* UxRTS=enabled; UxCTS=PORTx register */
#  define UART_MODE_UEN_ENCR        (2 << UART_MODE_UEN_SHIFT) /* UxCTS+UxRTS=enabled */
#  define UART_MODE_UEN_CPORT       (3 << UART_MODE_UEN_SHIFT) /* UxCTS=PORTx register */
#define UART_MODE_RTSMD             (1 << 11) /* Bit 11: Mode selection for ~UxRTS pin */
#define UART_MODE_IREN              (1 << 12) /* Bit 12: IrDA encoder and decoder enable */
#define UART_MODE_SIDL              (1 << 13) /* Bit 13: Stop in idle mode */
#define UART_MODE_ON                (1 << 15) /* Bit 15: UARTx enable */

/* UARTx status and control register */

#define UART_STA_URXDA              (1 << 0)  /* Bit 0: Receive buffer data available */
#define UART_STA_OERR               (1 << 1)  /* Bit 1: Receive buffer overrun error status */
#define UART_STA_FERR               (1 << 2)  /* Bit 2: Framing error status */
#define UART_STA_PERR               (1 << 3)  /* Bit 3: Parity error status */
#define UART_STA_RIDLE              (1 << 4)  /* Bit 4: Receiver idle */
#define UART_STA_ADDEN              (1 << 5)  /* Bit 5: Address character detect */
#define UART_STA_URXISEL_SHIFT      (6)       /* Bits: 6-7: Receive interrupt mode selection */
#define UART_STA_URXISEL_MASK       (3 << UART_STA_URXISEL_SHIFT)
#define UART_STA_URXISEL_RECVD      (0 << UART_STA_URXISEL_SHIFT) /* Character received */
#define UART_STA_URXISEL_RXB50      (1 << UART_STA_URXISEL_SHIFT) /* RX buffer 1/2 full */
#define UART_STA_URXISEL_RXB75      (2 << UART_STA_URXISEL_SHIFT) /* RX buffer 3/4 full */
#define UART_STA_UTRMT              (1 << 8)  /* Bit 8: Transmit shift register is empty */
#define UART_STA_UTXBF              (1 << 9)  /* Bit 9: Transmit buffer full status */
#define UART_STA_UTXEN              (1 << 10) /* Bit 10: Transmit enable */
#define UART_STA_UTXBRK             (1 << 11) /* Bit 11: Transmit break */
#define UART_STA_URXEN              (1 << 12) /* Bit 12: Receiver enable */
#define UART_STA_UTXINV             (1 << 13) /* Bit 13: Transmit polarity inversion */
#define UART_STA_UTXISEL_SHIFT      (14)      /* Bits:  14-15: TX interrupt mode selection bi */
#define UART_STA_UTXISEL_MASK       (3 << UART_STA_UTXISEL_SHIFT)
#  define UART_STA_UTXISEL_TXBNF    (0 << UART_STA_UTXISEL_SHIFT) /* TX buffer not full */
#  define UART_STA_UTXISEL_DRAINED  (1 << UART_STA_UTXISEL_SHIFT) /* All characters sent */
#  define UART_STA_UTXISEL_TXBE     (2 << UART_STA_UTXISEL_SHIFT) /* TX buffer empty */
#define UART_STA_ADDR_SHIFT         (16)      /* Bits:16-23: Automatic address mask */
#define UART_STA_ADDR_MASK          (0xff << UART_STA_ADDR_SHIFT)
#define UART_STA_ADM_EN             (1 << 24) /* Bit 24: Automatic address detect mode enable */

/* UARTx transmit register */

#define UART_TXREG_MASK             0x1ff

/* UARTx receive register */

#define UART_RXREG_MASK             0x1ff

/* UARTx baud rate register */

#define UART_BRG_MASK               0xffff

/************************************************************************************
 * Public Types
 ************************************************************************************/

#ifndef __ASSEMBLY__

/************************************************************************************
 * Inline Functions
 ************************************************************************************/

/************************************************************************************
 * Public Function Prototypes
 ************************************************************************************/

#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif

#undef EXTERN
#ifdef __cplusplus
}
#endif

#endif /* __ASSEMBLY__ */
#endif /* __ARCH_MIPS_SRC_PIC32MZ_PIC32MZ_CHIP_UART_H */