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author | Jason Zaugg <jzaugg@gmail.com> | 2014-05-27 15:37:35 +0200 |
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committer | Jason Zaugg <jzaugg@gmail.com> | 2014-05-27 15:37:35 +0200 |
commit | b20bb5587fbd36b212027a04a62f65d6709d05af (patch) | |
tree | e26453ca05c5e12cc0e61881fde068ea0cb478d6 /src/compiler | |
parent | 159bade707f006a10745f58871806400b6a76166 (diff) | |
parent | 7ecd98bca6a4aa28de4e406bd27712007768647a (diff) | |
download | scala-b20bb5587fbd36b212027a04a62f65d6709d05af.tar.gz scala-b20bb5587fbd36b212027a04a62f65d6709d05af.tar.bz2 scala-b20bb5587fbd36b212027a04a62f65d6709d05af.zip |
Merge pull request #3794 from lrytz/t8625
SI-8625 fix unreachability analysis for boolean expressions
Diffstat (limited to 'src/compiler')
-rw-r--r-- | src/compiler/scala/tools/nsc/backend/icode/GenICode.scala | 13 |
1 files changed, 10 insertions, 3 deletions
diff --git a/src/compiler/scala/tools/nsc/backend/icode/GenICode.scala b/src/compiler/scala/tools/nsc/backend/icode/GenICode.scala index 0da66d43f7..0ad3c2c76b 100644 --- a/src/compiler/scala/tools/nsc/backend/icode/GenICode.scala +++ b/src/compiler/scala/tools/nsc/backend/icode/GenICode.scala @@ -1424,11 +1424,18 @@ abstract class GenICode extends SubComponent { def genZandOrZor(and: Boolean): Boolean = { val ctxInterm = ctx.newBlock() - val branchesReachable = if (and) genCond(lhs, ctx, ctxInterm, elseCtx) + val lhsBranchesReachable = if (and) genCond(lhs, ctx, ctxInterm, elseCtx) else genCond(lhs, ctx, thenCtx, ctxInterm) - ctxInterm.bb killUnless branchesReachable + // If lhs is known to throw, we can kill the just created ctxInterm. + ctxInterm.bb killUnless lhsBranchesReachable - genCond(rhs, ctxInterm, thenCtx, elseCtx) + val rhsBranchesReachable = genCond(rhs, ctxInterm, thenCtx, elseCtx) + + // Reachable means "it does not always throw", i.e. "it might not throw". + // In an expression (a && b) or (a || b), the b branch might not be evaluated. + // Such an expression is therefore known to throw only if both expressions throw. Or, + // successors are reachable if either of the two is reachable (SI-8625). + lhsBranchesReachable || rhsBranchesReachable } def genRefEq(isEq: Boolean) = { val f = genEqEqPrimitive(lhs, rhs, ctx) _ |