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author | Adriaan Moors <adriaan.moors@typesafe.com> | 2016-07-28 15:08:43 -0700 |
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committer | Lukas Rytz <lukas.rytz@gmail.com> | 2016-08-10 13:51:56 +0200 |
commit | 43ba65fa11456899b3c45be14bd3895d8d6b6b5a (patch) | |
tree | af6f3122e7f8dbb12431840c5a440e763269f478 /test/files/run/Course-2002-08.scala | |
parent | 2b172be8c83c3146d3fd5ab01546c171ab18fa46 (diff) | |
download | scala-43ba65fa11456899b3c45be14bd3895d8d6b6b5a.tar.gz scala-43ba65fa11456899b3c45be14bd3895d8d6b6b5a.tar.bz2 scala-43ba65fa11456899b3c45be14bd3895d8d6b6b5a.zip |
SI-7187 deprecate eta-expansion of zero-arg method values
For backwards compatiblity with 2.11, we already
don't adapt a zero-arg method value to a SAM.
In 2.13, we won't do any eta-expansion for zero-arg method values,
but we should deprecate first.
Diffstat (limited to 'test/files/run/Course-2002-08.scala')
-rw-r--r-- | test/files/run/Course-2002-08.scala | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/test/files/run/Course-2002-08.scala b/test/files/run/Course-2002-08.scala index 5e21edaba3..1d0e02262d 100644 --- a/test/files/run/Course-2002-08.scala +++ b/test/files/run/Course-2002-08.scala @@ -205,7 +205,7 @@ object M5 { val inputSig = input.getSignal; afterDelay(InverterDelay) {() => output.setSignal(!inputSig) }; } - input addAction invertAction + input addAction invertAction _ } def andGate(a1: Wire, a2: Wire, output: Wire): Unit = { @@ -214,8 +214,8 @@ object M5 { val a2Sig = a2.getSignal; afterDelay(AndGateDelay) {() => output.setSignal(a1Sig & a2Sig) }; } - a1 addAction andAction; - a2 addAction andAction; + a1 addAction andAction _ + a2 addAction andAction _ } def orGate(o1: Wire, o2: Wire, output: Wire): Unit = { @@ -224,8 +224,8 @@ object M5 { val o2Sig = o2.getSignal; afterDelay(OrGateDelay) {() => output.setSignal(o1Sig | o2Sig) }; } - o1 addAction orAction; - o2 addAction orAction; + o1 addAction orAction _ + o2 addAction orAction _ } def probe(name: String, wire: Wire): Unit = { @@ -479,7 +479,7 @@ abstract class BasicCircuitSimulator() extends Simulator() { val inputSig = input.getSignal; afterDelay(InverterDelay) {() => output.setSignal(!inputSig) }; } - input addAction invertAction + input addAction invertAction _ } def andGate(a1: Wire, a2: Wire, output: Wire) = { @@ -488,8 +488,8 @@ abstract class BasicCircuitSimulator() extends Simulator() { val a2Sig = a2.getSignal; afterDelay(AndGateDelay) {() => output.setSignal(a1Sig & a2Sig) }; } - a1 addAction andAction; - a2 addAction andAction + a1 addAction andAction _ + a2 addAction andAction _ } def orGate(a1: Wire, a2: Wire, output: Wire) = { @@ -498,8 +498,8 @@ abstract class BasicCircuitSimulator() extends Simulator() { val a2Sig = a2.getSignal; afterDelay(OrGateDelay) {() => output.setSignal(a1Sig | a2Sig) }; } - a1 addAction orAction; - a2 addAction orAction + a1 addAction orAction _ + a2 addAction orAction _ } def orGate2(a1: Wire, a2: Wire, output: Wire) = { |