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authorSeth Tisue <seth@tisue.net>2015-07-01 15:56:17 -0400
committerSeth Tisue <seth@tisue.net>2015-07-01 15:56:17 -0400
commit495fdb8119c1941bc210a9b0a186d63971002e22 (patch)
tree2067bf5985fc138577fa7251b0ab7e4a23236a88 /test/files/run/t6146b.check
parentc8fbc41631da0a860f749479a610312814c0e88f (diff)
parentfac81d705ff0bfdeb3320fd9e46b6d3d34e47ddf (diff)
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Merge pull request #4576 from som-snytt/issue/9206-more
SI-9206 REPL custom bits
Diffstat (limited to 'test/files/run/t6146b.check')
-rw-r--r--test/files/run/t6146b.check2
1 files changed, 0 insertions, 2 deletions
diff --git a/test/files/run/t6146b.check b/test/files/run/t6146b.check
index 6998873fb7..0e0c216cd7 100644
--- a/test/files/run/t6146b.check
+++ b/test/files/run/t6146b.check
@@ -2,8 +2,6 @@ t6146b.scala:15: warning: match may not be exhaustive.
It would fail on the following inputs: S2(), S3()
def foo(f: F[Int]) = f match { case X.S1 => }
^
-Type in expressions to have them evaluated.
-Type :help for more information.
scala> :power
** Power User mode enabled - BEEP WHIR GYVE **