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author | Matthias Zenger <mzenger@gmail.com> | 2004-02-10 21:44:56 +0000 |
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committer | Matthias Zenger <mzenger@gmail.com> | 2004-02-10 21:44:56 +0000 |
commit | 2629b94686f6ccecefe2ac80424a7bbd4e6fc4e9 (patch) | |
tree | 1c6491de87a0ddb7caa53f0636854bd30e4dc818 /test/files/run | |
parent | 0b38cbc3c5d5f18c56a0cf9b08ac913a3f21d611 (diff) | |
download | scala-2629b94686f6ccecefe2ac80424a7bbd4e6fc4e9.tar.gz scala-2629b94686f6ccecefe2ac80424a7bbd4e6fc4e9.tar.bz2 scala-2629b94686f6ccecefe2ac80424a7bbd4e6fc4e9.zip |
- Updated files to the new syntax.
Diffstat (limited to 'test/files/run')
-rw-r--r-- | test/files/run/Course-2002-04.scala | 3 | ||||
-rw-r--r-- | test/files/run/Course-2002-08.scala | 6 |
2 files changed, 5 insertions, 4 deletions
diff --git a/test/files/run/Course-2002-04.scala b/test/files/run/Course-2002-04.scala index 733a290db2..e74711d454 100644 --- a/test/files/run/Course-2002-04.scala +++ b/test/files/run/Course-2002-04.scala @@ -59,7 +59,8 @@ object M1 { def sort1(l: Int, r: Int): Unit = { val pivot = xs((l + r) / 2); - var i = l, j = r; + var i = l; + var j = r; While (i <= j) { While (less(xs(i), pivot)) { i = i + 1 } While (less(pivot, xs(j))) { j = j - 1 } diff --git a/test/files/run/Course-2002-08.scala b/test/files/run/Course-2002-08.scala index f155689385..d50d98ffc6 100644 --- a/test/files/run/Course-2002-08.scala +++ b/test/files/run/Course-2002-08.scala @@ -506,7 +506,7 @@ abstract class BasicCircuitSimulator() extends Simulator() { } def orGate2(a1: Wire, a2: Wire, output: Wire) = { - val w1 = new Wire(), w2 = new Wire(), w3 = new Wire(); + val w1, w2, w3 = new Wire(); inverter(a1, w1); inverter(a2, w2); andGate(w1, w2, w3); @@ -517,7 +517,7 @@ abstract class BasicCircuitSimulator() extends Simulator() { abstract class CircuitSimulator() extends BasicCircuitSimulator() { def demux2(in: Wire, ctrl: List[Wire], out: List[Wire]) : Unit = { val ctrlN = ctrl.map(w => { val iw = new Wire(); inverter(w,iw); iw}); - val w0 = new Wire(), w1 = new Wire(), w2 = new Wire(), w3 = new Wire(); + val w0, w1, w2, w3 = new Wire(); andGate(in, ctrl(1), w3); andGate(in, ctrl(1), w2); @@ -537,7 +537,7 @@ abstract class CircuitSimulator() extends BasicCircuitSimulator() { def demux(in: Wire, ctrl: List[Wire], out: List[Wire]): Unit = ctrl match { case List() => connect(in, out.head); case c :: rest => - val c_ = new Wire(), w1 = new Wire(), w2 = new Wire(); + val c_, w1, w2 = new Wire(); inverter(c, c_); andGate(in, c_, w1); andGate(in, c, w2); |