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author | Adriaan Moors <adriaan.moors@typesafe.com> | 2013-01-14 15:51:01 -0800 |
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committer | Adriaan Moors <adriaan.moors@typesafe.com> | 2013-01-14 15:51:01 -0800 |
commit | a3e85a54d6227cbc89e4999e838343b53b2a704c (patch) | |
tree | c054ebfc6aa8015270b94a29163c12b47f1f078a /test | |
parent | a49722990655633c2c97ddf5699adf25bc8bea76 (diff) | |
parent | 58bfa19332c4aac8b7250d5866cfb153ae78c9ad (diff) | |
download | scala-a3e85a54d6227cbc89e4999e838343b53b2a704c.tar.gz scala-a3e85a54d6227cbc89e4999e838343b53b2a704c.tar.bz2 scala-a3e85a54d6227cbc89e4999e838343b53b2a704c.zip |
Merge pull request #1886 from retronym/ticket/6966
SI-6966 Fix regression in implicit resolution
Diffstat (limited to 'test')
-rw-r--r-- | test/files/pos/t6966.scala | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/test/files/pos/t6966.scala b/test/files/pos/t6966.scala new file mode 100644 index 0000000000..23adc6d0d2 --- /dev/null +++ b/test/files/pos/t6966.scala @@ -0,0 +1,17 @@ +import Ordering.{Byte, comparatorToOrdering} +trait Format[T] +trait InputCache[T] +object CacheIvy { + implicit def basicInputCache[I](implicit fmt: Format[I], eqv: Equiv[I]): InputCache[I] = null + implicit def arrEquiv[T](implicit t: Equiv[T]): Equiv[Array[T]] = null + implicit def hNilCache: InputCache[HNil] = null + implicit def ByteArrayFormat: Format[Array[Byte]] = null + type :+:[H, T <: HList] = HCons[H,T] + implicit def hConsCache[H, T <: HList](implicit head: InputCache[H], tail: InputCache[T]): InputCache[H :+: T] = null + hConsCache[Array[Byte], HNil] +} + +sealed trait HList +sealed trait HNil extends HList +object HNil extends HNil +final class HCons[H, T <: HList](head : H, tail : T) extends HList
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