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author | px4dev <px4@purgatory.org> | 2013-01-10 10:00:47 -0800 |
---|---|---|
committer | px4dev <px4@purgatory.org> | 2013-01-13 19:05:01 -0800 |
commit | 5e91a36623ed9e267be18ad8e348fdc5fc7a887f (patch) | |
tree | ec0efb8634560e1d626b278da17f4f76fc469205 | |
parent | 1cecba2a86520b042600b7194e8f7166560d1fdd (diff) | |
download | px4-firmware-5e91a36623ed9e267be18ad8e348fdc5fc7a887f.tar.gz px4-firmware-5e91a36623ed9e267be18ad8e348fdc5fc7a887f.tar.bz2 px4-firmware-5e91a36623ed9e267be18ad8e348fdc5fc7a887f.zip |
Drop the 'nonstop' flag since we can infer it when we need it. Submitted this version of the serial DMA changes for integration into mainline NuttX.
-rw-r--r-- | nuttx/arch/arm/src/stm32/stm32_uart.h | 5 | ||||
-rw-r--r-- | nuttx/arch/arm/src/stm32/stm32f10xxx_dma.c | 8 | ||||
-rw-r--r-- | nuttx/arch/arm/src/stm32/stm32f40xxx_dma.c | 11 |
3 files changed, 13 insertions, 11 deletions
diff --git a/nuttx/arch/arm/src/stm32/stm32_uart.h b/nuttx/arch/arm/src/stm32/stm32_uart.h index 194701a3f..13d49249c 100644 --- a/nuttx/arch/arm/src/stm32/stm32_uart.h +++ b/nuttx/arch/arm/src/stm32/stm32_uart.h @@ -140,10 +140,7 @@ # undef HAVE_CONSOLE #endif -/* DMA support is only provided if CONFIG_ARCH_DMA is in the NuttX configuration. - * Furthermore, DMA support is currently only implemented for the F4 (but could be - * extended to the F1 and F2 with a little effort in the DMA code. - */ +/* DMA support is only provided if CONFIG_ARCH_DMA is in the NuttX configuration */ #if !defined(HAVE_UART) || !defined(CONFIG_ARCH_DMA) # undef CONFIG_USART1_RXDMA diff --git a/nuttx/arch/arm/src/stm32/stm32f10xxx_dma.c b/nuttx/arch/arm/src/stm32/stm32f10xxx_dma.c index a02ceb230..13324b8ac 100644 --- a/nuttx/arch/arm/src/stm32/stm32f10xxx_dma.c +++ b/nuttx/arch/arm/src/stm32/stm32f10xxx_dma.c @@ -90,7 +90,6 @@ struct stm32_dma_s { uint8_t chan; /* DMA channel number (0-6) */ uint8_t irq; /* DMA channel IRQ number */ - bool nonstop; /* Stream is configured in non-stopping mode */ sem_t sem; /* Used to wait for DMA channel to become available */ uint32_t base; /* DMA register channel base address */ dma_callback_t callback; /* Callback invoked when the DMA completes */ @@ -494,7 +493,6 @@ void stm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, size_t nt ccr &= (DMA_CCR_MEM2MEM|DMA_CCR_PL_MASK|DMA_CCR_MSIZE_MASK|DMA_CCR_PSIZE_MASK| DMA_CCR_MINC|DMA_CCR_PINC|DMA_CCR_CIRC|DMA_CCR_DIR); regval |= ccr; - dmach->nonstop = (ccr & DMA_CCR_CIRC) != 0; dmachan_putreg(dmach, STM32_DMACHAN_CCR_OFFSET, regval); } @@ -530,7 +528,11 @@ void stm32_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, bool ccr = dmachan_getreg(dmach, STM32_DMACHAN_CCR_OFFSET); ccr |= DMA_CCR_EN; - if (!dmach->nonstop) + /* In normal mode, interrupt at either half or full completion. In circular mode, + * always interrupt on buffer wrap, and optionally interrupt at the halfway point. + */ + + if ((ccr & DMA_CCR_CIRC) == 0) { /* Once half of the bytes are transferred, the half-transfer flag (HTIF) is * set and an interrupt is generated if the Half-Transfer Interrupt Enable diff --git a/nuttx/arch/arm/src/stm32/stm32f40xxx_dma.c b/nuttx/arch/arm/src/stm32/stm32f40xxx_dma.c index dcbbf1856..40fce8cb5 100644 --- a/nuttx/arch/arm/src/stm32/stm32f40xxx_dma.c +++ b/nuttx/arch/arm/src/stm32/stm32f40xxx_dma.c @@ -94,7 +94,6 @@ struct stm32_dma_s uint8_t irq; /* DMA stream IRQ number */ uint8_t shift; /* ISR/IFCR bit shift value */ uint8_t channel; /* DMA channel number (0-7) */ - bool nonstop; /* Stream is configured in a non-stopping mode. */ sem_t sem; /* Used to wait for DMA channel to become available */ uint32_t base; /* DMA register channel base address */ dma_callback_t callback; /* Callback invoked when the DMA completes */ @@ -728,7 +727,6 @@ void stm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, DMA_SCR_DBM|DMA_SCR_CIRC| DMA_SCR_PBURST_MASK|DMA_SCR_MBURST_MASK); regval |= scr; - dmast->nonstop = (scr & (DMA_SCR_DBM|DMA_SCR_CIRC)) != 0; dmast_putreg(dmast, STM32_DMA_SCR_OFFSET, regval); } @@ -764,7 +762,12 @@ void stm32_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, bool scr = dmast_getreg(dmast, STM32_DMA_SCR_OFFSET); scr |= DMA_SCR_EN; - if (!dmast->nonstop) + /* In normal mode, interrupt at either half or full completion. In circular + * and double-buffered modes, always interrupt on buffer wrap, and optionally + * interrupt at the halfway point. + */ + + if ((scr & (DMA_SCR_DBM|DMA_SCR_CIRC)) == 0) { /* Once half of the bytes are transferred, the half-transfer flag (HTIF) is * set and an interrupt is generated if the Half-Transfer Interrupt Enable @@ -777,7 +780,7 @@ void stm32_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, bool } else { - /* In nonstop mode, when the transfer completes it immediately resets + /* In non-stop modes, when the transfer completes it immediately resets * and starts again. The transfer-complete interrupt is thus always * enabled, and the half-complete interrupt can be used in circular * mode to determine when the buffer is half-full, or in double-buffered |