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author | px4dev <px4@purgatory.org> | 2013-06-12 23:58:06 -0700 |
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committer | px4dev <px4@purgatory.org> | 2013-06-12 23:58:22 -0700 |
commit | 8eb4a03274b3012f5631f9a25f3a3f98f4d19159 (patch) | |
tree | 9b86331f301513d4d87e94d6a4ed66decc35acc5 | |
parent | d1782764381b61717656aafbebd3f3591fcc7dd8 (diff) | |
download | px4-firmware-8eb4a03274b3012f5631f9a25f3a3f98f4d19159.tar.gz px4-firmware-8eb4a03274b3012f5631f9a25f3a3f98f4d19159.tar.bz2 px4-firmware-8eb4a03274b3012f5631f9a25f3a3f98f4d19159.zip |
Use a better way of guessing whether we can use both-edges mode.
-rw-r--r-- | src/drivers/stm32/drv_hrt.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/drivers/stm32/drv_hrt.c b/src/drivers/stm32/drv_hrt.c index 05e1cd8ec..7ef3db970 100644 --- a/src/drivers/stm32/drv_hrt.c +++ b/src/drivers/stm32/drv_hrt.c @@ -278,8 +278,10 @@ static void hrt_call_invoke(void); #ifdef CONFIG_HRT_PPM /* * If the timer hardware doesn't support GTIM_CCER_CCxNP, then we will work around it. + * + * Note that we assume that M3 means STM32F1 (since we don't really care about the F2). */ -# ifndef GTIM_CCER_CC1NP +# ifdef CONFIG_ARCH_CORTEXM3 # define GTIM_CCER_CC1NP 0 # define GTIM_CCER_CC2NP 0 # define GTIM_CCER_CC3NP 0 |