Resync new repository with old repo r5166

git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5153 42af7a65-404d-4744-a932-0658087f49c3

85 files changed, 29681 insertions, 0 deletions

diff --git a/nuttx/arch/arm/src/lpc43xx/Kconfig b/nuttx/arch/arm/src/lpc43xx/Kconfig
new file mode 100644
index 000000000..4653b2ee3
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/Kconfig
@@ -0,0 +1,318 @@
+#
+# For a description of the syntax of this configuration file,
+# see misc/tools/kconfig-language.txt.
+#
+
+comment "LPC43xx Configuration Options"
+
+choice
+	prompt "LPC43XX Chip Selection"
+	default ARCH_CHIP_LPC4330FET100
+	depends on ARCH_CHIP_LPC43XX
+
+config ARCH_CHIP_LPC4310FBD144
+	bool "LPC4310FBD144"
+
+config ARCH_CHIP_LPC4310FET100
+	bool "LPC4310FET100"
+
+config ARCH_CHIP_LPC4320FBD144
+	bool "LPC4320FBD144"
+
+config ARCH_CHIP_LPC4320FET100
+	bool "LPC4320FET100"
+
+config ARCH_CHIP_LPC4330FBD144
+	bool "LPC4330FBD144"
+
+config ARCH_CHIP_LPC4330FET100
+	bool "LPC4330FET100"
+
+config ARCH_CHIP_LPC4330FET180
+	bool "LPC4330FET180"
+
+config ARCH_CHIP_LPC4330FET256
+	bool "LPC4330FET256"
+
+config ARCH_CHIP_LPC4350FBD208
+	bool "LPC4350FBD208"
+
+config ARCH_CHIP_LPC4350FET180
+	bool "LPC4350FET180"
+
+config ARCH_CHIP_LPC4350FET256
+	bool "LPC4350FET256"
+
+config ARCH_CHIP_LPC4353FBD208
+	bool "LPC4353FBD208"
+
+config ARCH_CHIP_LPC4353FET180
+	bool "LPC4353FET180"
+
+config ARCH_CHIP_LPC4353FET256
+	bool "LPC4353FET256"
+
+config ARCH_CHIP_LPC4357FET180
+	bool "LPC4357FET180"
+
+config ARCH_CHIP_LPC4357FBD208
+	bool "LPC4357FBD208"
+
+config ARCH_CHIP_LPC4357FET256
+	bool "LPC4357FET256"
+
+endchoice
+
+config ARCH_FAMILY_LPC4310
+	bool
+	default y if ARCH_CHIP_LPC4310FBD144 || ARCH_CHIP_LPC4310FET100
+
+config ARCH_FAMILY_LPC4320
+	bool
+	default y if ARCH_CHIP_LPC4320FBD144 || ARCH_CHIP_LPC4320FET100
+
+config ARCH_FAMILY_LPC4330
+	bool
+	default y if ARCH_CHIP_LPC4330FBD144 || ARCH_CHIP_LPC4330FET100 || ARCH_CHIP_LPC4330FET180 || ARCH_CHIP_LPC4330FET256
+
+config ARCH_FAMILY_LPC4350
+	bool
+	default y if ARCH_CHIP_LPC4350FBD208 || ARCH_CHIP_LPC4350FET180 || ARCH_CHIP_LPC4350FET256
+
+config ARCH_FAMILY_LPC4353
+	bool
+	default y if ARCH_CHIP_LPC4353FBD208 || ARCH_CHIP_LPC4353FET180 || ARCH_CHIP_LPC4353FET256
+
+config ARCH_FAMILY_LPC4357
+	bool
+	default y if ARCH_CHIP_LPC4357FET180 || ARCH_CHIP_LPC4357FBD208 || ARCH_CHIP_LPC4357FET256
+
+choice
+	prompt "Toolchain Selection"
+	default LPC43_CODEREDW
+	depends on ARCH_CHIP_LPC43XX
+
+config LPC43_CODEREDW
+	bool "CodeRed for Windows"
+
+config LPC43_CODESOURCERYW
+	bool "CodeSourcery for Windows"
+
+config LPC43_CODESOURCERYL
+	bool "CodeSourcery for Linux"
+
+config LPC43_ATOLLIC_LITE
+	bool "Atollic Lite for Windows"
+
+config LPC43_ATOLLIC_PRO
+	bool "Atollic Pro for Windows"
+
+config LPC43_DEVKITARM
+	bool "DevkitARM (Windows)"
+
+config LPC43_BUILDROOT
+	bool "NuttX buildroot (Cygwin or Linux)"
+
+endchoice
+
+choice
+	prompt "LPC43XX Boot Configuration"
+	default BOOT_SRAM
+	depends on ARCH_CHIP_LPC43XX
+	---help---
+		The startup code needs to know if the code is running from internal FLASH,
+		external FLASH, SPIFI, or SRAM in order to initialize properly.  Note that
+		a boot device is not specified for cases where the code is copied into SRAM;
+		those cases are all covered by BOOT_SRAM.
+
+config BOOT_SRAM
+	bool "Running from SRAM"
+
+config BOOT_SPIFI
+	bool "Running from QuadFLASH"
+
+config BOOT_FLASHA
+	bool "Running in internal FLASHA"
+
+config BOOT_FLASHB
+	bool "Running in internal FLASHA"
+
+config BOOT_CS0FLASH
+	bool "Running in external FLASH CS0"
+
+config BOOT_CS1FLASH
+	bool "Running in external FLASH CS1"
+
+config BOOT_CS2FLASH
+	bool "Running in external FLASH CS2"
+
+config BOOT_CS3FLASH
+	bool "Running in external FLASH CS3"
+
+endchoice
+
+menu "LPC43xx Peripheral Support"
+
+config LPC43_ADC0
+	bool "ADC0"
+	default n
+
+config LPC43_ADC1
+	bool "ADC1"
+	default n
+
+config LPC43_ATIMER
+	bool "Alarm timer"
+	default n
+
+config LPC43_CAN1
+	bool "C_CAN1"
+	default n
+
+config LPC43_CAN2
+	bool "C_CAN1"
+	default n
+
+config LPC43_DAC
+	bool "DAC"
+	default n
+
+config LPC43_EMC
+	bool "External Memory Controller (EMC)"
+	default n
+
+config LPC43_ETHERNET
+	bool "Ethernet"
+	default n
+
+config LPC43_EVNTMNTR
+	bool "Event Monitor"
+	default n
+
+config LPC43_GPDMA
+	bool "GPDMA"
+	default n
+
+config LPC43_I2C0
+	bool "I2C0"
+	default n
+
+config LPC43_I2C1
+	bool "I2C1"
+	default n
+
+config LPC43_I2S0
+	bool "I2S0"
+	default n
+
+config LPC43_I2S1
+	bool "I2S1"
+	default n
+
+config LPC43_LCD
+	bool "LCD"
+	default n
+
+config LPC43_MCPWM
+	bool "Motor Control PWM (MCPWM)"
+	default n
+
+config LPC43_QEI
+	bool "Quadrature Controller Interface (QEI)"
+	default n
+
+config LPC43_RIT
+	bool "Repetitive Interrupt Timer (RIT)"
+	default n
+
+config LPC43_RTC
+	bool "Real Time Clock (RTC)"
+	default n
+
+config LPC43_SCT
+	bool "State Configurable Timer (SCT)"
+	default n
+
+config LPC43_SDMMC
+	bool "SD/MMC"
+	default n
+
+config LPC43_SPI
+	bool "SPI"
+	default n
+
+config LPC43_SPIFI
+	bool "SPI Flash Interface (SPIFI)"
+	default n
+
+config LPC43_SSP0
+	bool "SSP0"
+	default n
+
+config LPC43_SSP1
+	bool "SSP1"
+	default n
+
+config LPC43_TMR0
+	bool "ADC1"
+	default n
+
+config LPC43_TMR1
+	bool "Timer 1"
+	default n
+
+config LPC43_TMR2
+	bool "Timer 2"
+	default n
+
+config LPC43_TMR3
+	bool "Timer 3"
+	default n
+
+config LPC43_USART0
+	bool "USART0"
+	select ARCH_HAVE_USART0
+	default n
+
+config LPC43_UART1
+	bool "UART1"
+	select ARCH_HAVE_UART1
+	default n
+
+config LPC43_USART2
+	bool "USART2"
+	select ARCH_HAVE_USART2
+	default n
+
+config LPC43_USART3
+	bool "USART3"
+	select ARCH_HAVE_USART3
+	default n
+
+config LPC43_USB0
+	bool "USB0"
+	default n
+
+config LPC43_USB1
+	bool "USB1"
+	default n
+
+config LPC43_USB1_ULPI
+	bool "USB1 with ULPI"
+	default n
+	depends on LPC43_USB1
+
+config LPC43_WWDT
+	bool "Windowing Watchdog Timer (WWDT)"
+	default n
+
+endmenu
+
+config SERIAL_TERMIOS
+	bool "Serial driver TERMIOS supported"
+	depends on LPC43_USART0 || LPC43_UART1 || LPC43_USART2 || LPC43_USART3
+	default n
+	---help---
+		Serial driver supports termios.h interfaces (tcsetattr, tcflush, etc.).
+		If this is not defined, then the terminal settings (baud, parity, etc).
+		are not configurable at runtime; serial streams cannot be flushed, etc..
diff --git a/nuttx/arch/arm/src/lpc43xx/Make.defs b/nuttx/arch/arm/src/lpc43xx/Make.defs
new file mode 100644
index 000000000..cc8de3b32
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/Make.defs
@@ -0,0 +1,126 @@
+############################################################################
+# arch/arm/src/lpc43xx/Make.defs
+#
+#   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+#   Author: Gregory Nutt <gnutt@nuttx.org>
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+#    notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in
+#    the documentation and/or other materials provided with the
+#    distribution.
+# 3. Neither the name NuttX nor the names of its contributors may be
+#    used to endorse or promote products derived from this software
+#    without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+############################################################################
+
+HEAD_ASRC  = 
+
+CMN_ASRCS  = up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S
+CMN_CSRCS += up_assert.c up_blocktask.c up_copystate.c
+CMN_CSRCS += up_createstack.c up_mdelay.c up_udelay.c up_exit.c
+CMN_CSRCS += up_initialize.c up_initialstate.c up_interruptcontext.c
+CMN_CSRCS += up_memfault.c up_modifyreg8.c up_modifyreg16.c up_modifyreg32.c
+CMN_CSRCS += up_releasepending.c up_releasestack.c up_reprioritizertr.c
+CMN_CSRCS += up_schedulesigaction.c up_sigdeliver.c up_unblocktask.c
+CMN_CSRCS += up_usestack.c up_doirq.c up_hardfault.c up_svcall.c
+
+ifeq ($(CONFIG_ARMV7M_CMNVECTOR),y)
+CMN_ASRCS += up_exception.S
+CMN_CSRCS += up_vectors.c
+endif
+
+ifeq ($(CONFIG_DEBUG_STACK),y)
+CMN_CSRCS += up_checkstack.c
+endif
+
+ifeq ($(CONFIG_ARCH_FPU),y)
+CMN_ASRCS += up_fpu.S
+endif
+
+CHIP_ASRCS  = 
+CHIP_CSRCS  = lpc43_allocateheap.c lpc43_cgu.c lpc43_clrpend.c lpc43_gpio.c
+CHIP_CSRCS += lpc43_irq.c lpc43_pinconfig.c lpc43_rgu.c lpc43_serial.c
+CHIP_CSRCS += lpc43_start.c lpc43_timerisr.c lpc43_uart.c
+
+ifneq ($(CONFIG_IDLE_CUSTOM),y)
+CHIP_CSRCS += lpc43_idle.c
+endif
+
+ifeq ($(CONFIG_DEBUG),y)
+CHIP_CSRCS += lpc43_debug.c
+endif
+
+ifeq ($(CONFIG_LPC43_GPDMA),y)
+CHIP_CSRCS += lpc43_gpdma.c
+endif
+
+ifeq ($(CONFIG_GPIO_IRQ),y)
+CHIP_CSRCS += lpc43_gpioint.c
+endif
+
+ifeq ($(CONFIG_LPC43_SPI),y)
+CHIP_CSRCS += lpc43_spi.c
+endif
+
+ifeq ($(CONFIG_LPC43_SPIFI),y)
+CHIP_CSRCS += lpc43_spifi.c
+endif
+
+ifeq ($(CONFIG_LPC43_SSP0),y)
+CHIP_CSRCS += lpc43_ssp.c
+else
+ifeq ($(CONFIG_LPC43_SSP1),y)
+CHIP_CSRCS += lpc43_ssp.c
+endif
+endif
+
+ifeq ($(CONFIG_LPC43_I2C0),y)
+CHIP_CSRCS += lpc43_i2c.c
+else
+ifeq ($(CONFIG_LPC43_I2C1),y)
+CHIP_CSRCS += lpc43_i2c.c
+endif
+endif
+
+ifeq ($(CONFIG_LPC43_ADC0),y)
+CHIP_CSRCS += lpc43_acc.c
+else
+ifeq ($(CONFIG_LPC43_ADC1),y)
+CHIP_CSRCS += lpc43_adc.c
+endif
+endif
+
+ifeq ($(CONFIG_LPC43_DAC),y)
+CHIP_CSRCS += lpc43_acc.c
+else
+ifeq ($(CONFIG_LPC43_DAC),y)
+CHIP_CSRCS += lpc43_adc.c
+endif
+endif
+
+ifeq ($(CONFIG_LPC43_USB0),y)
+ifeq ($(CONFIG_USBDEV),y)
+CHIP_CSRCS	+= lpc31_usb0dev.c
+endif
+endif
+
diff --git a/nuttx/arch/arm/src/lpc43xx/chip.h b/nuttx/arch/arm/src/lpc43xx/chip.h
new file mode 100644
index 000000000..35150d08c
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/chip.h
@@ -0,0 +1,173 @@
+/************************************************************************************
+ * arch/arm/src/lpc43xx/chip.h
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_H
+#define __ARCH_ARM_SRC_LPC43XX_CHIP_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+/* Include the chip capabilities file */
+
+#include <arch/lpc43xx/chip.h>
+
+/* For each chip supported in chip.h, the following are provided to customize the
+ * environment for the specific LPC43XX chip:
+ *
+ * Define ARMV7M_PERIPHERAL_INTERRUPTS - This is needed by common/up_vectors.c.  This
+ *   definition provides the number of "external" interrupt vectors supported by
+ *   the specific LPC43 chip.
+ *
+ *   For the Cortex-M3 core, this should always be equal to the value
+ *   LPC43M4_IRQ_NEXTINT defined in include/lpc43xx/irq.h.  For the Cortex-M0
+ *   core, this should always be equal to the value LPC43M0_IRQ_NEXTINT defined
+ *   in include/lpc43xx/irq.h (At present, only the Cortex-M4 core is supported)
+ *
+ * Include the chip-specific memory map header file, and
+ * Include the chip-specific pin configuration.
+ *
+ * These header files may or may not be shared between different chips.  That decisions
+ * depends on the similarity of the chip peripheral.
+ */
+
+#if defined(CONFIG_ARCH_CHIP_LPC4310FBD144)
+#  define  ARMV7M_PERIPHERAL_INTERRUPTS 53
+#  include "chip/lpc4310203050_memorymap.h"
+#  include "chip/lpc4310203050_pinconfig.h"
+#elif defined(CONFIG_ARCH_CHIP_LPC4310FET100)
+#  define  ARMV7M_PERIPHERAL_INTERRUPTS 53
+#  include "chip/lpc4310203050_memorymap.h"
+#  include "chip/lpc4310203050_pinconfig.h"
+#elif defined(CONFIG_ARCH_CHIP_LPC4320FBD144)
+#  define  ARMV7M_PERIPHERAL_INTERRUPTS 53
+#  include "chip/lpc4310203050_memorymap.h"
+#  include "chip/lpc4310203050_pinconfig.h"
+#elif defined(CONFIG_ARCH_CHIP_LPC4320FET100)
+#  define  ARMV7M_PERIPHERAL_INTERRUPTS 53
+#  include "chip/lpc4310203050_memorymap.h"
+#  include "chip/lpc4310203050_pinconfig.h"
+#elif defined(CONFIG_ARCH_CHIP_LPC4330FBD144)
+#  define  ARMV7M_PERIPHERAL_INTERRUPTS 53
+#  include "chip/lpc4310203050_memorymap.h"
+#  include "chip/lpc4310203050_pinconfig.h"
+#elif defined(CONFIG_ARCH_CHIP_LPC4330FET100)
+#  define  ARMV7M_PERIPHERAL_INTERRUPTS 53
+#  include "chip/lpc4310203050_memorymap.h"
+#  include "chip/lpc4310203050_pinconfig.h"
+#elif defined(CONFIG_ARCH_CHIP_LPC4330FET180)
+#  define  ARMV7M_PERIPHERAL_INTERRUPTS 53
+#  include "chip/lpc4310203050_memorymap.h"
+#  include "chip/lpc4310203050_pinconfig.h"
+#elif defined(CONFIG_ARCH_CHIP_LPC4330FET256)
+#  define  ARMV7M_PERIPHERAL_INTERRUPTS 53
+#  include "chip/lpc4310203050_memorymap.h"
+#  include "chip/lpc4310203050_pinconfig.h"
+#elif defined(CONFIG_ARCH_CHIP_LPC4350FBD208)
+#  define  ARMV7M_PERIPHERAL_INTERRUPTS 53
+#  include "chip/lpc4310203050_memorymap.h"
+#  include "chip/lpc4310203050_pinconfig.h"
+#elif defined(CONFIG_ARCH_CHIP_LPC4350FET180)
+#  define  ARMV7M_PERIPHERAL_INTERRUPTS 53
+#  include "chip/lpc4310203050_memorymap.h"
+#  include "chip/lpc4310203050_pinconfig.h"
+#elif defined(CONFIG_ARCH_CHIP_LPC4350FET256)
+#  define  ARMV7M_PERIPHERAL_INTERRUPTS 53
+#  include "chip/lpc4310203050_memorymap.h"
+#  include "chip/lpc4310203050_pinconfig.h"
+#elif defined(CONFIG_ARCH_CHIP_LPC4353FBD208)
+#  define  ARMV7M_PERIPHERAL_INTERRUPTS 53
+#  include "chip/lpc435357_memorymap.h"
+#  include "chip/lpc4353fbd208_pinconfig.h"
+#elif defined(CONFIG_ARCH_CHIP_LPC4353FET180)
+#  define  ARMV7M_PERIPHERAL_INTERRUPTS 53
+#  include "chip/lpc435357_memorymap.h"
+#  include "chip/lpc4353fet180_pinconfig.h"
+#elif defined(CONFIG_ARCH_CHIP_LPC4353FET256)
+#  define  ARMV7M_PERIPHERAL_INTERRUPTS 53
+#  include "chip/lpc435357_memorymap.h"
+#  include "chip/lpc4353fet256_pinconfig.h"
+#elif defined(CONFIG_ARCH_CHIP_LPC4357FET180)
+#  define  ARMV7M_PERIPHERAL_INTERRUPTS 53
+#  include "chip/lpc435357_memorymap.h"
+#  include "chip/lpc4357fet180_pinconfig.h"
+#elif defined(CONFIG_ARCH_CHIP_LPC4357FBD208)
+#  define  ARMV7M_PERIPHERAL_INTERRUPTS 53
+#  include "chip/lpc435357_memorymap.h"
+#  include "chip/lpc4357fbd208_pinconfig.h"
+#elif defined(CONFIG_ARCH_CHIP_LPC4357FET256)
+#  define  ARMV7M_PERIPHERAL_INTERRUPTS 53
+#  include "chip/lpc435357_memorymap.h"
+#  include "chip/lpc4357fet256_pinconfig.h"
+#else
+#  error "Unsupported LPC43xx chip"
+#endif
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* NVIC priority levels *************************************************************/
+/* Each priority field holds a priority value, 0-31. The lower the value, the greater
+ * the priority of the corresponding interrupt.
+ *
+ * The Cortex-M4 core supports up to 53 interrupts an 8 prgrammable interrupt
+ * priority levels; The Cortex-M0 core supports up to 32 interrupts with 4
+ * programmable interrupt priorities.
+ */
+
+#define LPC43M4_SYSH_PRIORITY_MIN     0xe0 /* All bits[7:5] set is minimum priority */
+#define LPC43M4_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
+#define LPC43M4_SYSH_PRIORITY_MAX     0x00 /* Zero is maximum priority */
+
+#define LPC43M0_SYSH_PRIORITY_MIN     0xc0 /* All bits[7:6] set is minimum priority */
+#define LPC43M0_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
+#define LPC43M0_SYSH_PRIORITY_MAX     0x00 /* Zero is maximum priority */
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_H */
diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc4310203050_memorymap.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc4310203050_memorymap.h
new file mode 100644
index 000000000..882444c05
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc4310203050_memorymap.h
@@ -0,0 +1,196 @@
+/************************************************************************************
+ * arch/arm/src/lpc43xx/chip/lpc4310203050_memorymap.h
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC4310203050_MEMORYMAP_H
+#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC4310203050_MEMORYMAP_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Memory Map ***********************************************************************/
+/* See arch/arm/include/lpc43xx/chip.h for the actual sizes of FLASH and SRAM
+ * regions
+ */
+
+#define LPC43_SHADOW_BASE          0x00000000 /* -0x0fffffff: 256Mb shadow area */
+#define LPC43_LOCSRAM_BASE         0x10000000 /* -0x1fffffff: Local SRAM and external memory */
+#define LPC43_AHBSRAM_BASE         0x20000000 /* -0x27ffffff: AHB SRAM */
+#define LPC43_DYCS0_BASE           0x28000000 /* -0x2fffffff: 128Mb dynamic external memory */
+#define LPC43_DYCS1_BASE           0x30000000 /* -0x2fffffff: 256Mb dynamic external memory */
+#define LPC43_PERIPH_BASE          0x40000000 /* -0x5fffffff: Peripherals */
+#define LPC43_DYCS2_BASE           0x60000000 /* -0x6fffffff: 256Mb dynamic external memory */
+#define LPC43_DYCS3_BASE           0x70000000 /* -0x7fffffff: 256Mb dynamic external memory */
+#define LPC43_SPIFI_DATA_BASE      0x80000000 /* -0x87ffffff: 256Mb dynamic external memory */
+#define LPC43_ARM_BASE             0xe0000000 /* -0xe00fffff: ARM private */
+
+/* Local SRAM Banks and external memory */
+
+#define LPC43_LOCSRAM_BANK0_BASE   (LPC43_LOCSRAM_BASE + 0x00000000)
+#define LPC43_LOCSRAM_BANK1_BASE   (LPC43_LOCSRAM_BASE + 0x00080000)
+#define LPC43_ROM_BASE             (LPC43_LOCSRAM_BASE + 0x00400000)
+#define LPC43_LOCSRAM_SPIFI_BASE   (LPC43_LOCSRAM_BASE + 0x04000000)
+#define LPC43_EXTMEM_CS0_BASE      (LPC43_LOCSRAM_BASE + 0x0c000000)
+#define LPC43_EXTMEM_CS1_BASE      (LPC43_LOCSRAM_BASE + 0x0d000000)
+#define LPC43_EXTMEM_CS2_BASE      (LPC43_LOCSRAM_BASE + 0x0e000000)
+#define LPC43_EXTMEM_CS3_BASE      (LPC43_LOCSRAM_BASE + 0x0f000000)
+
+/* ROM Driver Table */
+
+#define LPC43_ROM_DRIVER_TABLE     (LPC43_ROM_BASE+0x00000100)
+#define LPC43_ROM_DRIVER_TABLE0    (LPC43_ROM_DRIVER_TABLE+0x0000)
+#define LPC43_ROM_DRIVER_TABLE1    (LPC43_ROM_DRIVER_TABLE+0x0004)
+#define LPC43_ROM_DRIVER_TABLE2    (LPC43_ROM_DRIVER_TABLE+0x0008)
+#define LPC43_ROM_DRIVER_TABLE3    (LPC43_ROM_DRIVER_TABLE+0x000c)
+#define LPC43_ROM_DRIVER_TABLE4    (LPC43_ROM_DRIVER_TABLE+0x0010)
+#define LPC43_ROM_DRIVER_TABLE5    (LPC43_ROM_DRIVER_TABLE+0x0014)
+#define LPC43_ROM_DRIVER_TABLE6    (LPC43_ROM_DRIVER_TABLE+0x0018)
+#define LPC43_ROM_DRIVER_TABLE7    (LPC43_ROM_DRIVER_TABLE+0x001c)
+
+/* AHB SRAM */
+
+#define LPC43_AHBSRAM_BANK0_BASE   (LPC43_AHBSRAM_BASE)
+#define LPC43_AHBSRAM_BANK1_BASE   (LPC43_AHBSRAM_BASE + 0x00008000)
+#define LPC43_AHBSRAM_BANK2_BASE   (LPC43_AHBSRAM_BASE + 0x0000c000)
+#define LPC43_AHBSRAM_BITBAND_BASE (LPC43_AHBSRAM_BASE + 0x0000c000)
+
+/* Peripherals */
+
+#define LPC43_AHBPERIPH_BASE       (LPC43_PERIPH_BASE + 0x00000000)
+#define LPC43_RTCPERIPH_BASE       (LPC43_PERIPH_BASE + 0x00040000)
+#define LPC43_CLKPERIPH_BASE       (LPC43_PERIPH_BASE + 0x00050000)
+#define LPC43_APB0PERIPH_BASE      (LPC43_PERIPH_BASE + 0x00080000)
+#define LPC43_APB1PERIPH_BASE      (LPC43_PERIPH_BASE + 0x000a0000)
+#define LPC43_APB2PERIPH_BASE      (LPC43_PERIPH_BASE + 0x000c0000)
+#define LPC43_APB3PERIPH_BASE      (LPC43_PERIPH_BASE + 0x000e0000)
+#define LPC43_GPIO_BASE            (LPC43_PERIPH_BASE + 0x000f4000)
+#define LPC43_SPI_BASE             (LPC43_PERIPH_BASE + 0x00100000)
+#define LPC43_SGPIO_BASE           (LPC43_PERIPH_BASE + 0x00101000)
+#define LPC43_PERIPH_BITBAND_BASE  (LPC43_PERIPH_BASE + 0x02000000)
+
+/* AHB Peripherals */
+
+#define LPC43_SCT_BASE             (LPC43_AHBPERIPH_BASE + 0x00000000)
+#define LPC43_DMA_BASE             (LPC43_AHBPERIPH_BASE + 0x00002000)
+#define LPC43_SPIFI_PERIPH_BASE    (LPC43_AHBPERIPH_BASE + 0x00003000)
+#define LPC43_SDMMC_BASE           (LPC43_AHBPERIPH_BASE + 0x00004000)
+#define LPC43_EMC_BASE             (LPC43_AHBPERIPH_BASE + 0x00005000)
+#define LPC43_USB0_BASE            (LPC43_AHBPERIPH_BASE + 0x00006000)
+#define LPC43_USB1_BASE            (LPC43_AHBPERIPH_BASE + 0x00007000)
+#define LPC43_LCD_BASE             (LPC43_AHBPERIPH_BASE + 0x00008000)
+#define LPC43_ETHERNET_BASE        (LPC43_AHBPERIPH_BASE + 0x00010000)
+
+/* RTC Domain Peripherals */
+
+#define LPC43_ATIMER_BASE          (LPC43_RTCPERIPH_BASE + 0x00000000)
+#define LPC43_BACKUP_BASE          (LPC43_RTCPERIPH_BASE + 0x00001000)
+#define LPC43_PMC_BASE             (LPC43_RTCPERIPH_BASE + 0x00002000)
+#define LPC43_CREG_BASE            (LPC43_RTCPERIPH_BASE + 0x00003000)
+#define LPC43_EVNTRTR_BASE         (LPC43_RTCPERIPH_BASE + 0x00004000)
+#define LPC43_OTPC_BASE            (LPC43_RTCPERIPH_BASE + 0x00005000)
+#define LPC43_RTC_BASE             (LPC43_RTCPERIPH_BASE + 0x00006000)
+#define LPC43_EVNTMNTR_BASE        (LPC43_RTC_BASE       + 0x00000080)
+
+/* Clocking and Reset Peripherals */
+
+#define LPC43_CGU_BASE             (LPC43_CLKPERIPH_BASE + 0x00000000)
+#define LPC43_CCU1_BASE            (LPC43_CLKPERIPH_BASE + 0x00001000)
+#define LPC43_CCU2_BASE            (LPC43_CLKPERIPH_BASE + 0x00002000)
+#define LPC43_RGU_BASE             (LPC43_CLKPERIPH_BASE + 0x00003000)
+
+/* APB0 Peripherals */
+
+#define LPC43_WWDT_BASE            (LPC43_APB0PERIPH_BASE + 0x00000000)
+#define LPC43_USART0_BASE          (LPC43_APB0PERIPH_BASE + 0x00001000)
+#define LPC43_UART1_BASE           (LPC43_APB0PERIPH_BASE + 0x00002000)
+#define LPC43_SSP0_BASE            (LPC43_APB0PERIPH_BASE + 0x00003000)
+#define LPC43_TIMER0_BASE          (LPC43_APB0PERIPH_BASE + 0x00004000)
+#define LPC43_TIMER1_BASE          (LPC43_APB0PERIPH_BASE + 0x00005000)
+#define LPC43_SCU_BASE             (LPC43_APB0PERIPH_BASE + 0x00006000)
+#define LPC43_GPIOINT_BASE         (LPC43_APB0PERIPH_BASE + 0x00007000)
+#define LPC43_GRP0INT_BASE         (LPC43_APB0PERIPH_BASE + 0x00008000)
+#define LPC43_GRP1INT_BASE         (LPC43_APB0PERIPH_BASE + 0x00009000)
+
+/* APB1 Peripherals */
+
+#define LPC43_MCPWM_BASE           (LPC43_APB1PERIPH_BASE + 0x00000000)
+#define LPC43_I2C0_BASE            (LPC43_APB1PERIPH_BASE + 0x00001000)
+#define LPC43_I2S0_BASE            (LPC43_APB1PERIPH_BASE + 0x00002000)
+#define LPC43_I2S1_BASE            (LPC43_APB1PERIPH_BASE + 0x00003000)
+#define LPC43_CAN1_BASE            (LPC43_APB1PERIPH_BASE + 0x00004000)
+
+/* APB2 Peripherals */
+
+#define LPC43_RIT_BASE             (LPC43_APB2PERIPH_BASE + 0x00000000)
+#define LPC43_USART2_BASE          (LPC43_APB2PERIPH_BASE + 0x00001000)
+#define LPC43_USART3_BASE          (LPC43_APB2PERIPH_BASE + 0x00002000)
+#define LPC43_TIMER2_BASE          (LPC43_APB2PERIPH_BASE + 0x00003000)
+#define LPC43_TIMER3_BASE          (LPC43_APB2PERIPH_BASE + 0x00004000)
+#define LPC43_SSP1_BASE            (LPC43_APB2PERIPH_BASE + 0x00005000)
+#define LPC43_QEI_BASE             (LPC43_APB2PERIPH_BASE + 0x00006000)
+#define LPC43_GIMA_BASE            (LPC43_APB2PERIPH_BASE + 0x00007000)
+
+/* APB3 Peripherals */
+
+#define LPC43_I2C1_BASE            (LPC43_APB3PERIPH_BASE + 0x00000000)
+#define LPC43_DAC_BASE             (LPC43_APB3PERIPH_BASE + 0x00001000)
+#define LPC43_CAN0_BASE            (LPC43_APB3PERIPH_BASE + 0x00002000)
+#define LPC43_ADC0_BASE            (LPC43_APB3PERIPH_BASE + 0x00003000)
+#define LPC43_ADC1_BASE            (LPC43_APB3PERIPH_BASE + 0x00004000)
+
+/* ARM Private */
+
+#define LPC43_SCS_BASE             (LPC43_ARM_BASE + 0x0000e000)
+#define LPC43_DEBUGMCU_BASE        (LPC43_ARM_BASE + 0x00042000)
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC4310203050_MEMORYMAP_H */
diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc4310203050_pinconfig.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc4310203050_pinconfig.h
new file mode 100644
index 000000000..c1c710e0c
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc4310203050_pinconfig.h
@@ -0,0 +1,982 @@
+/****************************************************************************************************
+ * arch/arm/src/lpc43xx/chip/lpc4310203050_pinconfig.h
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC4310203050_PINCONF_H
+#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC4310203050_PINCONF_H
+
+/****************************************************************************************************
+ * Included Files
+ ****************************************************************************************************/
+
+#include <nuttx/config.h>
+
+/****************************************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************************************/
+/* NOTES:
+ *
+ * 1. These settings were taken from the LPC43_10_20_30_50 data sheet and may not be applicable to
+ *    any other family members.
+ *
+ * 2. Settings taken from the data sheet include only function, pin set, and pin number.  Additional
+ *    settings must be verfied before using these pin configurations (like pull-ups, open-drain,
+ *    drive strength, input buffering, etc.).
+ *
+ * 3. Alternative pin selections are provided with a numeric suffix like _1, _2, etc. Drivers,
+ *    however, will use the pin selection without the numeric suffix.  Additional definitions are
+ *    required in the board.h file to select between the alternative pins.  For example, if CAN1_RD
+ *    connects via Pins1[18], then the following definition should appear inthe board.h header file
+ *    for that board:
+ *
+ * 4. For ADC pins (PINCONF_ADCNpM), the pin must first be configured configured as a GPIO input.
+ *    Then SCU's ADC function select register can be used to select the ADC.
+ *
+ *    #define PINCONF_CAN1_RD PINCONF_CAN1_RD_1
+ *
+ *    The driver will then automatically configre Pins1[18] as the CAN1 RD pin.
+ */
+
+#define PINCONF_ADC0p0           (PINCONF_FUNC0|PINCONF_PINS4|PINCONF_PIN_3)
+#define PINCONF_ADC0p1           (PINCONF_FUNC0|PINCONF_PINS4|PINCONF_PIN_1)
+#define PINCONF_ADC0p2           (PINCONF_FUNC4|PINCONF_PINSF|PINCONF_PIN_8)
+#define PINCONF_ADC0p3           (PINCONF_FUNC0|PINCONF_PINS7|PINCONF_PIN_5)
+#define PINCONF_ADC0p4           (PINCONF_FUNC0|PINCONF_PINS7|PINCONF_PIN_4)
+#define PINCONF_ADC0p5           (PINCONF_FUNC4|PINCONF_PINSF|PINCONF_PIN_10)
+#define PINCONF_ADC0p6           (PINCONF_FUNC0|PINCONF_PINSB|PINCONF_PIN_6)
+
+#define PINCONF_ADC1p0           (PINCONF_FUNC4|PINCONF_PINSC|PINCONF_PIN_3)
+#define PINCONF_ADC1p1           (PINCONF_FUNC0|PINCONF_PINSC|PINCONF_PIN_0)
+#define PINCONF_ADC1p2           (PINCONF_FUNC4|PINCONF_PINSF|PINCONF_PIN_9)
+#define PINCONF_ADC1p3           (PINCONF_FUNC4|PINCONF_PINSF|PINCONF_PIN_6)
+#define PINCONF_ADC1p4           (PINCONF_FUNC4|PINCONF_PINSF|PINCONF_PIN_5)
+#define PINCONF_ADC1p5           (PINCONF_FUNC4|PINCONF_PINSF|PINCONF_PIN_11)
+#define PINCONF_ADC1p6           (PINCONF_FUNC0|PINCONF_PINS7|PINCONF_PIN_7)
+#define PINCONF_ADC1p7           (PINCONF_FUNC4|PINCONF_PINSF|PINCONF_PIN_7)
+
+#define PINCONF_ADCTRIG0         (PINCONF_FUNC0|PINCONF_PINSE|PINCONF_PIN_2)
+#define PINCONF_ADCTRIG1_1       (PINCONF_FUNC2|PINCONF_PINSE|PINCONF_PIN_3)
+#define PINCONF_ADCTRIG1_2       (PINCONF_FUNC3|PINCONF_PINS2|PINCONF_PIN_5)
+
+#define PINCONF_CAN0_RD_1        (PINCONF_FUNC1|PINCONF_PINSE|PINCONF_PIN_2)
+#define PINCONF_CAN0_RD_2        (PINCONF_FUNC2|PINCONF_PINS3|PINCONF_PIN_1)
+#define PINCONF_CAN0_TD_1        (PINCONF_FUNC1|PINCONF_PINSE|PINCONF_PIN_3)
+#define PINCONF_CAN0_TD_2        (PINCONF_FUNC2|PINCONF_PINS3|PINCONF_PIN_2)
+
+#define PINCONF_CAN1_RD_1        (PINCONF_FUNC5|PINCONF_PINS1|PINCONF_PIN_18)
+#define PINCONF_CAN1_RD_2        (PINCONF_FUNC5|PINCONF_PINSE|PINCONF_PIN_1)
+#define PINCONF_CAN1_RD_3        (PINCONF_FUNC6|PINCONF_PINS4|PINCONF_PIN_9)
+#define PINCONF_CAN1_TD_1        (PINCONF_FUNC5|PINCONF_PINS1|PINCONF_PIN_17)
+#define PINCONF_CAN1_TD_2        (PINCONF_FUNC5|PINCONF_PINSE|PINCONF_PIN_0)
+#define PINCONF_CAN1_TD_3        (PINCONF_FUNC6|PINCONF_PINS4|PINCONF_PIN_8)
+
+#define PINCONF_CGU_OUT0         (PINCONF_FUNC6|PINCONF_PINS8|PINCONF_PIN_8)
+#define PINCONF_CGU_OUT1_1       (PINCONF_FUNC4|PINCONF_PINS3|PINCONF_PIN_3)
+#define PINCONF_CGU_OUT1_2       (PINCONF_FUNC6|PINCONF_PINSA|PINCONF_PIN_0)
+
+#define PINCONF_CLKOUT           (PINCONF_FUNC4|PINCONF_PINS1|PINCONF_PIN_19)
+
+#define PINCONF_CTIN0_1          (PINCONF_FUNC1|PINCONF_PINSD|PINCONF_PIN_13)
+#define PINCONF_CTIN0_2          (PINCONF_FUNC3|PINCONF_PINS2|PINCONF_PIN_4)
+#define PINCONF_CTIN1_1          (PINCONF_FUNC1|PINCONF_PINSD|PINCONF_PIN_10)
+#define PINCONF_CTIN1_2          (PINCONF_FUNC3|PINCONF_PINS2|PINCONF_PIN_3)
+#define PINCONF_CTIN2_1          (PINCONF_FUNC1|PINCONF_PINS2|PINCONF_PIN_5)
+#define PINCONF_CTIN2_2          (PINCONF_FUNC1|PINCONF_PINS4|PINCONF_PIN_10)
+#define PINCONF_CTIN2_3          (PINCONF_FUNC2|PINCONF_PINSF|PINCONF_PIN_8)
+#define PINCONF_CTIN3_1          (PINCONF_FUNC1|PINCONF_PINS1|PINCONF_PIN_0)
+#define PINCONF_CTIN3_2          (PINCONF_FUNC1|PINCONF_PINS7|PINCONF_PIN_3)
+#define PINCONF_CTIN3_3          (PINCONF_FUNC1|PINCONF_PINSE|PINCONF_PIN_10)
+#define PINCONF_CTIN4_1          (PINCONF_FUNC1|PINCONF_PINS2|PINCONF_PIN_13)
+#define PINCONF_CTIN4_2          (PINCONF_FUNC1|PINCONF_PINS7|PINCONF_PIN_2)
+#define PINCONF_CTIN4_3          (PINCONF_FUNC1|PINCONF_PINSE|PINCONF_PIN_9)
+#define PINCONF_CTIN5_1          (PINCONF_FUNC1|PINCONF_PINS1|PINCONF_PIN_6)
+#define PINCONF_CTIN5_2          (PINCONF_FUNC1|PINCONF_PINS4|PINCONF_PIN_8)
+#define PINCONF_CTIN5_3          (PINCONF_FUNC1|PINCONF_PINSD|PINCONF_PIN_7)
+#define PINCONF_CTIN5_4          (PINCONF_FUNC5|PINCONF_PINSB|PINCONF_PIN_4)
+#define PINCONF_CTIN6_1          (PINCONF_FUNC1|PINCONF_PINS4|PINCONF_PIN_9)
+#define PINCONF_CTIN6_2          (PINCONF_FUNC1|PINCONF_PINS6|PINCONF_PIN_4)
+#define PINCONF_CTIN6_3          (PINCONF_FUNC1|PINCONF_PINSD|PINCONF_PIN_8)
+#define PINCONF_CTIN6_4          (PINCONF_FUNC5|PINCONF_PINS2|PINCONF_PIN_2)
+#define PINCONF_CTIN6_5          (PINCONF_FUNC5|PINCONF_PINSB|PINCONF_PIN_6)
+#define PINCONF_CTIN7_1          (PINCONF_FUNC5|PINCONF_PINS2|PINCONF_PIN_6)
+#define PINCONF_CTIN7_2          (PINCONF_FUNC5|PINCONF_PINSB|PINCONF_PIN_5)
+
+#define PINCONF_CTOUT0_1         (PINCONF_FUNC1|PINCONF_PINS2|PINCONF_PIN_8)
+#define PINCONF_CTOUT0_2         (PINCONF_FUNC1|PINCONF_PINS4|PINCONF_PIN_2)
+#define PINCONF_CTOUT0_3         (PINCONF_FUNC1|PINCONF_PINSE|PINCONF_PIN_15)
+#define PINCONF_CTOUT1_1         (PINCONF_FUNC1|PINCONF_PINS2|PINCONF_PIN_7)
+#define PINCONF_CTOUT1_2         (PINCONF_FUNC1|PINCONF_PINS4|PINCONF_PIN_1)
+#define PINCONF_CTOUT1_3         (PINCONF_FUNC2|PINCONF_PINSF|PINCONF_PIN_9)
+#define PINCONF_CTOUT2_1         (PINCONF_FUNC1|PINCONF_PINS2|PINCONF_PIN_10)
+#define PINCONF_CTOUT2_2         (PINCONF_FUNC1|PINCONF_PINS4|PINCONF_PIN_4)
+#define PINCONF_CTOUT2_3         (PINCONF_FUNC1|PINCONF_PINSE|PINCONF_PIN_6)
+#define PINCONF_CTOUT3_1         (PINCONF_FUNC1|PINCONF_PINS2|PINCONF_PIN_9)
+#define PINCONF_CTOUT3_2         (PINCONF_FUNC1|PINCONF_PINS4|PINCONF_PIN_3)
+#define PINCONF_CTOUT3_3         (PINCONF_FUNC1|PINCONF_PINSE|PINCONF_PIN_5)
+#define PINCONF_CTOUT4_1         (PINCONF_FUNC1|PINCONF_PINS2|PINCONF_PIN_12)
+#define PINCONF_CTOUT4_2         (PINCONF_FUNC1|PINCONF_PINS4|PINCONF_PIN_6)
+#define PINCONF_CTOUT4_3         (PINCONF_FUNC1|PINCONF_PINSE|PINCONF_PIN_8)
+#define PINCONF_CTOUT5_1         (PINCONF_FUNC1|PINCONF_PINS2|PINCONF_PIN_11)
+#define PINCONF_CTOUT5_2         (PINCONF_FUNC1|PINCONF_PINS4|PINCONF_PIN_5)
+#define PINCONF_CTOUT5_3         (PINCONF_FUNC1|PINCONF_PINSE|PINCONF_PIN_7)
+#define PINCONF_CTOUT6_1         (PINCONF_FUNC1|PINCONF_PINS1|PINCONF_PIN_2)
+#define PINCONF_CTOUT6_2         (PINCONF_FUNC1|PINCONF_PINS6|PINCONF_PIN_5)
+#define PINCONF_CTOUT6_3         (PINCONF_FUNC1|PINCONF_PINSD|PINCONF_PIN_3)
+#define PINCONF_CTOUT6_4         (PINCONF_FUNC5|PINCONF_PINSB|PINCONF_PIN_1)
+#define PINCONF_CTOUT7_1         (PINCONF_FUNC1|PINCONF_PINS1|PINCONF_PIN_1)
+#define PINCONF_CTOUT7_2         (PINCONF_FUNC1|PINCONF_PINS6|PINCONF_PIN_12)
+#define PINCONF_CTOUT7_3         (PINCONF_FUNC1|PINCONF_PINSD|PINCONF_PIN_2)
+#define PINCONF_CTOUT7_4         (PINCONF_FUNC5|PINCONF_PINSB|PINCONF_PIN_2)
+#define PINCONF_CTOUT8_1         (PINCONF_FUNC1|PINCONF_PINS1|PINCONF_PIN_3)
+#define PINCONF_CTOUT8_2         (PINCONF_FUNC1|PINCONF_PINS7|PINCONF_PIN_7)
+#define PINCONF_CTOUT8_3         (PINCONF_FUNC1|PINCONF_PINSD|PINCONF_PIN_4)
+#define PINCONF_CTOUT8_4         (PINCONF_FUNC5|PINCONF_PINSB|PINCONF_PIN_3)
+#define PINCONF_CTOUT8_5         (PINCONF_FUNC6|PINCONF_PINSD|PINCONF_PIN_15)
+#define PINCONF_CTOUT9_1         (PINCONF_FUNC1|PINCONF_PINS1|PINCONF_PIN_4)
+#define PINCONF_CTOUT9_2         (PINCONF_FUNC1|PINCONF_PINSA|PINCONF_PIN_4)
+#define PINCONF_CTOUT9_3         (PINCONF_FUNC1|PINCONF_PINSD|PINCONF_PIN_5)
+#define PINCONF_CTOUT10_1        (PINCONF_FUNC1|PINCONF_PINS1|PINCONF_PIN_5)
+#define PINCONF_CTOUT10_2        (PINCONF_FUNC1|PINCONF_PINSB|PINCONF_PIN_0)
+#define PINCONF_CTOUT10_3        (PINCONF_FUNC1|PINCONF_PINSD|PINCONF_PIN_6)
+#define PINCONF_CTOUT10_4        (PINCONF_FUNC6|PINCONF_PINSD|PINCONF_PIN_12)
+#define PINCONF_CTOUT11_1        (PINCONF_FUNC1|PINCONF_PINS7|PINCONF_PIN_6)
+#define PINCONF_CTOUT11_2        (PINCONF_FUNC1|PINCONF_PINSE|PINCONF_PIN_12)
+#define PINCONF_CTOUT11_3        (PINCONF_FUNC2|PINCONF_PINS1|PINCONF_PIN_9)
+#define PINCONF_CTOUT11_4        (PINCONF_FUNC6|PINCONF_PINSD|PINCONF_PIN_14)
+#define PINCONF_CTOUT12_1        (PINCONF_FUNC1|PINCONF_PINS7|PINCONF_PIN_5)
+#define PINCONF_CTOUT12_2        (PINCONF_FUNC1|PINCONF_PINSE|PINCONF_PIN_11)
+#define PINCONF_CTOUT12_3        (PINCONF_FUNC2|PINCONF_PINS1|PINCONF_PIN_8)
+#define PINCONF_CTOUT12_4        (PINCONF_FUNC6|PINCONF_PINSD|PINCONF_PIN_16)
+#define PINCONF_CTOUT13_1        (PINCONF_FUNC1|PINCONF_PINS7|PINCONF_PIN_4)
+#define PINCONF_CTOUT13_2        (PINCONF_FUNC1|PINCONF_PINSD|PINCONF_PIN_9)
+#define PINCONF_CTOUT13_3        (PINCONF_FUNC2|PINCONF_PINS1|PINCONF_PIN_7)
+#define PINCONF_CTOUT13_4        (PINCONF_FUNC6|PINCONF_PINSD|PINCONF_PIN_13)
+#define PINCONF_CTOUT14_1        (PINCONF_FUNC1|PINCONF_PINS7|PINCONF_PIN_0)
+#define PINCONF_CTOUT14_2        (PINCONF_FUNC1|PINCONF_PINSE|PINCONF_PIN_13)
+#define PINCONF_CTOUT14_3        (PINCONF_FUNC2|PINCONF_PINS1|PINCONF_PIN_10)
+#define PINCONF_CTOUT14_4        (PINCONF_FUNC6|PINCONF_PINSD|PINCONF_PIN_11)
+#define PINCONF_CTOUT15_1        (PINCONF_FUNC1|PINCONF_PINS7|PINCONF_PIN_1)
+#define PINCONF_CTOUT15_2        (PINCONF_FUNC1|PINCONF_PINSD|PINCONF_PIN_0)
+#define PINCONF_CTOUT15_3        (PINCONF_FUNC2|PINCONF_PINS1|PINCONF_PIN_11)
+
+#define PINCONF_EMC_A0           (PINCONF_FUNC3|PINCONF_PINS2|PINCONF_PIN_9)
+#define PINCONF_EMC_A1           (PINCONF_FUNC3|PINCONF_PINS2|PINCONF_PIN_10)
+#define PINCONF_EMC_A2           (PINCONF_FUNC3|PINCONF_PINS2|PINCONF_PIN_11)
+#define PINCONF_EMC_A3           (PINCONF_FUNC3|PINCONF_PINS2|PINCONF_PIN_12)
+#define PINCONF_EMC_A4           (PINCONF_FUNC3|PINCONF_PINS2|PINCONF_PIN_13)
+#define PINCONF_EMC_A5           (PINCONF_FUNC2|PINCONF_PINS1|PINCONF_PIN_0)
+#define PINCONF_EMC_A6           (PINCONF_FUNC2|PINCONF_PINS1|PINCONF_PIN_1)
+#define PINCONF_EMC_A7           (PINCONF_FUNC2|PINCONF_PINS1|PINCONF_PIN_2)
+#define PINCONF_EMC_A8           (PINCONF_FUNC3|PINCONF_PINS2|PINCONF_PIN_8)
+#define PINCONF_EMC_A9           (PINCONF_FUNC3|PINCONF_PINS2|PINCONF_PIN_7)
+#define PINCONF_EMC_A10          (PINCONF_FUNC2|PINCONF_PINS2|PINCONF_PIN_6)
+#define PINCONF_EMC_A11          (PINCONF_FUNC2|PINCONF_PINS2|PINCONF_PIN_2)
+#define PINCONF_EMC_A12          (PINCONF_FUNC2|PINCONF_PINS2|PINCONF_PIN_1)
+#define PINCONF_EMC_A13          (PINCONF_FUNC2|PINCONF_PINS2|PINCONF_PIN_0)
+#define PINCONF_EMC_A14          (PINCONF_FUNC1|PINCONF_PINS6|PINCONF_PIN_8)
+#define PINCONF_EMC_A15          (PINCONF_FUNC1|PINCONF_PINS6|PINCONF_PIN_7)
+#define PINCONF_EMC_A16          (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_16)
+#define PINCONF_EMC_A17          (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_15)
+#define PINCONF_EMC_A18          (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_0)
+#define PINCONF_EMC_A19          (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_1)
+#define PINCONF_EMC_A20          (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_2)
+#define PINCONF_EMC_A21          (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_3)
+#define PINCONF_EMC_A22          (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_4)
+#define PINCONF_EMC_A23          (PINCONF_FUNC3|PINCONF_PINSA|PINCONF_PIN_4)
+#define PINCONF_EMC_BLS0         (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_4)
+#define PINCONF_EMC_BLS1         (PINCONF_FUNC1|PINCONF_PINS6|PINCONF_PIN_6)
+#define PINCONF_EMC_BLS2         (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_13)
+#define PINCONF_EMC_BLS3         (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_10)
+#define PINCONF_EMC_CAS          (PINCONF_FUNC3|PINCONF_PINS6|PINCONF_PIN_4)
+#define PINCONF_EMC_CKEOUT0      (PINCONF_FUNC3|PINCONF_PINS6|PINCONF_PIN_11)
+#define PINCONF_EMC_CKEOUT1      (PINCONF_FUNC1|PINCONF_PINS6|PINCONF_PIN_2)
+#define PINCONF_EMC_CKEOUT2      (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_1)
+#define PINCONF_EMC_CKEOUT3      (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_15)
+#define PINCONF_EMC_CS0          (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_5)
+#define PINCONF_EMC_CS1          (PINCONF_FUNC3|PINCONF_PINS6|PINCONF_PIN_3)
+#define PINCONF_EMC_CS2          (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_12)
+#define PINCONF_EMC_CS3          (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_11)
+#define PINCONF_EMC_D0           (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_7)
+#define PINCONF_EMC_D1           (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_8)
+#define PINCONF_EMC_D2           (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_9)
+#define PINCONF_EMC_D3           (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_10)
+#define PINCONF_EMC_D4           (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_11)
+#define PINCONF_EMC_D5           (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_12)
+#define PINCONF_EMC_D6           (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_13)
+#define PINCONF_EMC_D7           (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_14)
+#define PINCONF_EMC_D8           (PINCONF_FUNC2|PINCONF_PINS5|PINCONF_PIN_4)
+#define PINCONF_EMC_D9           (PINCONF_FUNC2|PINCONF_PINS5|PINCONF_PIN_5)
+#define PINCONF_EMC_D10          (PINCONF_FUNC2|PINCONF_PINS5|PINCONF_PIN_6)
+#define PINCONF_EMC_D11          (PINCONF_FUNC2|PINCONF_PINS5|PINCONF_PIN_7)
+#define PINCONF_EMC_D12          (PINCONF_FUNC2|PINCONF_PINS5|PINCONF_PIN_0)
+#define PINCONF_EMC_D13          (PINCONF_FUNC2|PINCONF_PINS5|PINCONF_PIN_1)
+#define PINCONF_EMC_D14          (PINCONF_FUNC2|PINCONF_PINS5|PINCONF_PIN_2)
+#define PINCONF_EMC_D15          (PINCONF_FUNC2|PINCONF_PINS5|PINCONF_PIN_3)
+#define PINCONF_EMC_D16          (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_2)
+#define PINCONF_EMC_D17          (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_3)
+#define PINCONF_EMC_D18          (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_4)
+#define PINCONF_EMC_D19          (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_5)
+#define PINCONF_EMC_D20          (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_6)
+#define PINCONF_EMC_D21          (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_7)
+#define PINCONF_EMC_D22          (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_8)
+#define PINCONF_EMC_D23          (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_9)
+#define PINCONF_EMC_D24          (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_5)
+#define PINCONF_EMC_D25          (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_6)
+#define PINCONF_EMC_D26          (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_7)
+#define PINCONF_EMC_D27          (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_8)
+#define PINCONF_EMC_D28          (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_9)
+#define PINCONF_EMC_D29          (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_10)
+#define PINCONF_EMC_D30          (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_11)
+#define PINCONF_EMC_D31          (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_12)
+#define PINCONF_EMC_DQMOUT0      (PINCONF_FUNC3|PINCONF_PINS6|PINCONF_PIN_12)
+#define PINCONF_EMC_DQMOUT1      (PINCONF_FUNC3|PINCONF_PINS6|PINCONF_PIN_10)
+#define PINCONF_EMC_DQMOUT2      (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_0)
+#define PINCONF_EMC_DQMOUT3      (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_13)
+#define PINCONF_EMC_DYCS0        (PINCONF_FUNC3|PINCONF_PINS6|PINCONF_PIN_9)
+#define PINCONF_EMC_DYCS1        (PINCONF_FUNC1|PINCONF_PINS6|PINCONF_PIN_1)
+#define PINCONF_EMC_DYCS2        (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_14)
+#define PINCONF_EMC_DYCS3        (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_14)
+#define PINCONF_EMC_OE           (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_3)
+#define PINCONF_EMC_RAS          (PINCONF_FUNC3|PINCONF_PINS6|PINCONF_PIN_5)
+#define PINCONF_EMC_WE           (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_6)
+
+#define PINCONF_ENET_COL_1       (PINCONF_FUNC2|PINCONF_PINS0|PINCONF_PIN_1)
+#define PINCONF_ENET_COL_2       (PINCONF_FUNC5|PINCONF_PINS9|PINCONF_PIN_6)
+#define PINCONF_ENET_COL_3       (PINCONF_FUNC7|PINCONF_PINS4|PINCONF_PIN_1)
+#define PINCONF_ENET_CRS_1       (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_16)
+#define PINCONF_ENET_CRS_2       (PINCONF_FUNC5|PINCONF_PINS9|PINCONF_PIN_0)
+#define PINCONF_ENET_MDC_1       (PINCONF_FUNC3|PINCONF_PINSC|PINCONF_PIN_1)
+#define PINCONF_ENET_MDC_2       (PINCONF_FUNC6|PINCONF_PINS7|PINCONF_PIN_7)
+#define PINCONF_ENET_MDC_3       (PINCONF_FUNC7|PINCONF_PINS2|PINCONF_PIN_0)
+#define PINCONF_ENET_MDIO        (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_17)
+#define PINCONF_ENET_REF_CLK     (PINCONF_FUNC0|PINCONF_PINS1|PINCONF_PIN_19)
+#define PINCONF_ENET_RXD0        (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_15)
+#define PINCONF_ENET_RXD1        (PINCONF_FUNC2|PINCONF_PINS0|PINCONF_PIN_0)
+#define PINCONF_ENET_RXD2_1      (PINCONF_FUNC3|PINCONF_PINSC|PINCONF_PIN_6)
+#define PINCONF_ENET_RXD2_2      (PINCONF_FUNC5|PINCONF_PINS9|PINCONF_PIN_3)
+#define PINCONF_ENET_RXD3_1      (PINCONF_FUNC3|PINCONF_PINSC|PINCONF_PIN_7)
+#define PINCONF_ENET_RXD3_2      (PINCONF_FUNC5|PINCONF_PINS9|PINCONF_PIN_2)
+#define PINCONF_ENET_RX_CLK      (PINCONF_FUNC3|PINCONF_PINSC|PINCONF_PIN_0)
+#define PINCONF_ENET_RX_DV_1     (PINCONF_FUNC3|PINCONF_PINSC|PINCONF_PIN_8)
+#define PINCONF_ENET_RX_DV_2     (PINCONF_FUNC7|PINCONF_PINS1|PINCONF_PIN_16)
+#define PINCONF_ENET_RX_ER_1     (PINCONF_FUNC3|PINCONF_PINSC|PINCONF_PIN_9)
+#define PINCONF_ENET_RX_ER_2     (PINCONF_FUNC5|PINCONF_PINS9|PINCONF_PIN_1)
+#define PINCONF_ENET_TXD0        (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_18)
+#define PINCONF_ENET_TXD1        (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_20)
+#define PINCONF_ENET_TXD2_1      (PINCONF_FUNC3|PINCONF_PINSC|PINCONF_PIN_2)
+#define PINCONF_ENET_TXD2_2      (PINCONF_FUNC5|PINCONF_PINS9|PINCONF_PIN_4)
+#define PINCONF_ENET_TXD3_1      (PINCONF_FUNC3|PINCONF_PINSC|PINCONF_PIN_3)
+#define PINCONF_ENET_TXD3_2      (PINCONF_FUNC5|PINCONF_PINS9|PINCONF_PIN_5)
+#define PINCONF_ENET_TXEN        (PINCONF_FUNC6|PINCONF_PINS0|PINCONF_PIN_1)
+#define PINCONF_ENET_TX_CLK      (PINCONF_FUNC0|PINCONF_PINS1|PINCONF_PIN_19)
+#define PINCONF_ENET_TX_EN       (PINCONF_FUNC3|PINCONF_PINSC|PINCONF_PIN_4)
+#define PINCONF_ENET_TX_ER_1     (PINCONF_FUNC3|PINCONF_PINSC|PINCONF_PIN_5)
+#define PINCONF_ENET_TX_ER_2     (PINCONF_FUNC6|PINCONF_PINSC|PINCONF_PIN_14)
+
+#define PINCONF_GPIO0p0          (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS0|PINCONF_PIN_0)
+#define PINCONF_GPIO0p1          (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS0|PINCONF_PIN_1)
+#define PINCONF_GPIO0p2          (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS1|PINCONF_PIN_15)
+#define PINCONF_GPIO0p3          (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS1|PINCONF_PIN_16)
+#define PINCONF_GPIO0p4          (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS1|PINCONF_PIN_0)
+#define PINCONF_GPIO0p5          (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS6|PINCONF_PIN_6)
+#define PINCONF_GPIO0p6          (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS3|PINCONF_PIN_6)
+#define PINCONF_GPIO0p7          (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS2|PINCONF_PIN_7)
+#define PINCONF_GPIO0p8          (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS1|PINCONF_PIN_1)
+#define PINCONF_GPIO0p9          (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS1|PINCONF_PIN_2)
+#define PINCONF_GPIO0p10         (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS1|PINCONF_PIN_3)
+#define PINCONF_GPIO0p11         (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS1|PINCONF_PIN_4)
+#define PINCONF_GPIO0p12         (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS1|PINCONF_PIN_17)
+#define PINCONF_GPIO0p13         (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS1|PINCONF_PIN_18)
+#define PINCONF_GPIO0p14         (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS2|PINCONF_PIN_10)
+#define PINCONF_GPIO0p15         (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS1|PINCONF_PIN_20)
+#define PINCONF_GPIO1p0          (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS1|PINCONF_PIN_7)
+#define PINCONF_GPIO1p1          (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS1|PINCONF_PIN_8)
+#define PINCONF_GPIO1p2          (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS1|PINCONF_PIN_9)
+#define PINCONF_GPIO1p3          (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS1|PINCONF_PIN_10)
+#define PINCONF_GPIO1p4          (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS1|PINCONF_PIN_11)
+#define PINCONF_GPIO1p5          (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS1|PINCONF_PIN_12)
+#define PINCONF_GPIO1p6          (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS1|PINCONF_PIN_13)
+#define PINCONF_GPIO1p7          (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS1|PINCONF_PIN_14)
+#define PINCONF_GPIO1p8          (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS1|PINCONF_PIN_5)
+#define PINCONF_GPIO1p9          (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS1|PINCONF_PIN_6)
+#define PINCONF_GPIO1p10         (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS2|PINCONF_PIN_9)
+#define PINCONF_GPIO1p11         (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS2|PINCONF_PIN_11)
+#define PINCONF_GPIO1p12         (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS2|PINCONF_PIN_12)
+#define PINCONF_GPIO1p13         (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS2|PINCONF_PIN_13)
+#define PINCONF_GPIO1p14         (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS3|PINCONF_PIN_4)
+#define PINCONF_GPIO1p15         (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS3|PINCONF_PIN_5)
+#define PINCONF_GPIO2p0          (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS4|PINCONF_PIN_0)
+#define PINCONF_GPIO2p1          (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS4|PINCONF_PIN_1)
+#define PINCONF_GPIO2p2          (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS4|PINCONF_PIN_2)
+#define PINCONF_GPIO2p3          (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS4|PINCONF_PIN_3)
+#define PINCONF_GPIO2p4          (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS4|PINCONF_PIN_4)
+#define PINCONF_GPIO2p5          (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS4|PINCONF_PIN_5)
+#define PINCONF_GPIO2p6          (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS4|PINCONF_PIN_6)
+#define PINCONF_GPIO2p7          (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS5|PINCONF_PIN_7)
+#define PINCONF_GPIO2p8          (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS6|PINCONF_PIN_12)
+#define PINCONF_GPIO2p9          (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS5|PINCONF_PIN_0)
+#define PINCONF_GPIO2p10         (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS5|PINCONF_PIN_1)
+#define PINCONF_GPIO2p11         (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS5|PINCONF_PIN_2)
+#define PINCONF_GPIO2p12         (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS5|PINCONF_PIN_3)
+#define PINCONF_GPIO2p13         (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS5|PINCONF_PIN_4)
+#define PINCONF_GPIO2p14         (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS5|PINCONF_PIN_5)
+#define PINCONF_GPIO2p15         (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS5|PINCONF_PIN_6)
+#define PINCONF_GPIO3p0          (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS6|PINCONF_PIN_1)
+#define PINCONF_GPIO3p1          (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS6|PINCONF_PIN_2)
+#define PINCONF_GPIO3p2          (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS6|PINCONF_PIN_3)
+#define PINCONF_GPIO3p3          (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS6|PINCONF_PIN_4)
+#define PINCONF_GPIO3p4          (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS6|PINCONF_PIN_5)
+#define PINCONF_GPIO3p5          (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS6|PINCONF_PIN_9)
+#define PINCONF_GPIO3p6          (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS6|PINCONF_PIN_10)
+#define PINCONF_GPIO3p7          (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS6|PINCONF_PIN_11)
+#define PINCONF_GPIO3p8          (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS7|PINCONF_PIN_0)
+#define PINCONF_GPIO3p9          (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS7|PINCONF_PIN_1)
+#define PINCONF_GPIO3p10         (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS7|PINCONF_PIN_2)
+#define PINCONF_GPIO3p11         (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS7|PINCONF_PIN_3)
+#define PINCONF_GPIO3p12         (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS7|PINCONF_PIN_4)
+#define PINCONF_GPIO3p13         (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS7|PINCONF_PIN_5)
+#define PINCONF_GPIO3p14         (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS7|PINCONF_PIN_6)
+#define PINCONF_GPIO3p15         (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS7|PINCONF_PIN_7)
+#define PINCONF_GPIO4p0          (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS8|PINCONF_PIN_0)
+#define PINCONF_GPIO4p1          (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS8|PINCONF_PIN_1)
+#define PINCONF_GPIO4p2          (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS8|PINCONF_PIN_2)
+#define PINCONF_GPIO4p3          (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS8|PINCONF_PIN_3)
+#define PINCONF_GPIO4p4          (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS8|PINCONF_PIN_4)
+#define PINCONF_GPIO4p5          (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS8|PINCONF_PIN_5)
+#define PINCONF_GPIO4p6          (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS8|PINCONF_PIN_6)
+#define PINCONF_GPIO4p7          (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS8|PINCONF_PIN_7)
+#define PINCONF_GPIO4p8          (PINCONF_FUNC0|PINCONF_PINSA|PINCONF_PIN_1)
+#define PINCONF_GPIO4p9          (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINSA|PINCONF_PIN_2)
+#define PINCONF_GPIO4p10         (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINSA|PINCONF_PIN_3)
+#define PINCONF_GPIO4p11         (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS9|PINCONF_PIN_6)
+#define PINCONF_GPIO4p12         (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS9|PINCONF_PIN_0)
+#define PINCONF_GPIO4p13         (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS9|PINCONF_PIN_1)
+#define PINCONF_GPIO4p14         (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS9|PINCONF_PIN_2)
+#define PINCONF_GPIO4p15         (PINCONF_FUNC0|PINCONF_INBUFFER|PINCONF_PINS9|PINCONF_PIN_3)
+#define PINCONF_GPIO5p0          (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINS2|PINCONF_PIN_0)
+#define PINCONF_GPIO5p1          (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINS2|PINCONF_PIN_1)
+#define PINCONF_GPIO5p2          (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINS2|PINCONF_PIN_2)
+#define PINCONF_GPIO5p3          (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINS2|PINCONF_PIN_3)
+#define PINCONF_GPIO5p4          (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINS2|PINCONF_PIN_4)
+#define PINCONF_GPIO5p5          (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINS2|PINCONF_PIN_5)
+#define PINCONF_GPIO5p6          (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINS2|PINCONF_PIN_6)
+#define PINCONF_GPIO5p7          (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINS2|PINCONF_PIN_8)
+#define PINCONF_GPIO5p8          (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINS3|PINCONF_PIN_1)
+#define PINCONF_GPIO5p9          (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINS3|PINCONF_PIN_2)
+#define PINCONF_GPIO5p10         (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINS3|PINCONF_PIN_7)
+#define PINCONF_GPIO5p11         (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINS3|PINCONF_PIN_8)
+#define PINCONF_GPIO5p12         (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINS4|PINCONF_PIN_8)
+#define PINCONF_GPIO5p13         (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINS4|PINCONF_PIN_9)
+#define PINCONF_GPIO5p14         (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINS4|PINCONF_PIN_10)
+#define PINCONF_GPIO5p15         (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINS6|PINCONF_PIN_7)
+#define PINCONF_GPIO5p16         (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINS6|PINCONF_PIN_8)
+#define PINCONF_GPIO5p17         (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINS9|PINCONF_PIN_4)
+#define PINCONF_GPIO5p18         (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINS9|PINCONF_PIN_5)
+#define PINCONF_GPIO5p19         (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSA|PINCONF_PIN_4)
+#define PINCONF_GPIO5p20         (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSB|PINCONF_PIN_0)
+#define PINCONF_GPIO5p21         (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSB|PINCONF_PIN_1)
+#define PINCONF_GPIO5p22         (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSB|PINCONF_PIN_2)
+#define PINCONF_GPIO5p23         (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSB|PINCONF_PIN_3)
+#define PINCONF_GPIO5p24         (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSB|PINCONF_PIN_4)
+#define PINCONF_GPIO5p25         (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSB|PINCONF_PIN_5)
+#define PINCONF_GPIO5p26         (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSB|PINCONF_PIN_6)
+#define PINCONF_GPIO6p0          (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSC|PINCONF_PIN_1)
+#define PINCONF_GPIO6p1          (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSC|PINCONF_PIN_2)
+#define PINCONF_GPIO6p2          (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSC|PINCONF_PIN_3)
+#define PINCONF_GPIO6p3          (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSC|PINCONF_PIN_4)
+#define PINCONF_GPIO6p4          (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSC|PINCONF_PIN_5)
+#define PINCONF_GPIO6p5          (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSC|PINCONF_PIN_6)
+#define PINCONF_GPIO6p6          (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSC|PINCONF_PIN_7)
+#define PINCONF_GPIO6p7          (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSC|PINCONF_PIN_8)
+#define PINCONF_GPIO6p8          (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSC|PINCONF_PIN_9)
+#define PINCONF_GPIO6p9          (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSC|PINCONF_PIN_10)
+#define PINCONF_GPIO6p10         (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSC|PINCONF_PIN_11)
+#define PINCONF_GPIO6p11         (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSC|PINCONF_PIN_12)
+#define PINCONF_GPIO6p12         (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSC|PINCONF_PIN_13)
+#define PINCONF_GPIO6p13         (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSC|PINCONF_PIN_14)
+#define PINCONF_GPIO6p14         (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSD|PINCONF_PIN_0)
+#define PINCONF_GPIO6p15         (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSD|PINCONF_PIN_1)
+#define PINCONF_GPIO6p16         (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSD|PINCONF_PIN_2)
+#define PINCONF_GPIO6p17         (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSD|PINCONF_PIN_3)
+#define PINCONF_GPIO6p18         (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSD|PINCONF_PIN_4)
+#define PINCONF_GPIO6p19         (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSD|PINCONF_PIN_5)
+#define PINCONF_GPIO6p20         (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSD|PINCONF_PIN_6)
+#define PINCONF_GPIO6p21         (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSD|PINCONF_PIN_7)
+#define PINCONF_GPIO6p22         (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSD|PINCONF_PIN_8)
+#define PINCONF_GPIO6p23         (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSD|PINCONF_PIN_9)
+#define PINCONF_GPIO6p24         (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSD|PINCONF_PIN_10)
+#define PINCONF_GPIO6p25         (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSD|PINCONF_PIN_11)
+#define PINCONF_GPIO6p26         (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSD|PINCONF_PIN_12)
+#define PINCONF_GPIO6p27         (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSD|PINCONF_PIN_13)
+#define PINCONF_GPIO6p28         (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSD|PINCONF_PIN_14)
+#define PINCONF_GPIO6p29         (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSD|PINCONF_PIN_15)
+#define PINCONF_GPIO6p30         (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSD|PINCONF_PIN_16)
+#define PINCONF_GPIO7p0          (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSE|PINCONF_PIN_0)
+#define PINCONF_GPIO7p1          (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSE|PINCONF_PIN_1)
+#define PINCONF_GPIO7p2          (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSE|PINCONF_PIN_2)
+#define PINCONF_GPIO7p3          (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSE|PINCONF_PIN_3)
+#define PINCONF_GPIO7p4          (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSE|PINCONF_PIN_4)
+#define PINCONF_GPIO7p5          (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSE|PINCONF_PIN_5)
+#define PINCONF_GPIO7p6          (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSE|PINCONF_PIN_6)
+#define PINCONF_GPIO7p7          (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSE|PINCONF_PIN_7)
+#define PINCONF_GPIO7p8          (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSE|PINCONF_PIN_8)
+#define PINCONF_GPIO7p9          (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSE|PINCONF_PIN_9)
+#define PINCONF_GPIO7p10         (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSE|PINCONF_PIN_10)
+#define PINCONF_GPIO7p11         (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSE|PINCONF_PIN_11)
+#define PINCONF_GPIO7p12         (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSE|PINCONF_PIN_12)
+#define PINCONF_GPIO7p13         (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSE|PINCONF_PIN_13)
+#define PINCONF_GPIO7p14         (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSE|PINCONF_PIN_14)
+#define PINCONF_GPIO7p15         (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSE|PINCONF_PIN_15)
+#define PINCONF_GPIO7p16         (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSF|PINCONF_PIN_1)
+#define PINCONF_GPIO7p17         (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSF|PINCONF_PIN_2)
+#define PINCONF_GPIO7p18         (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSF|PINCONF_PIN_3)
+#define PINCONF_GPIO7p19         (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSF|PINCONF_PIN_5)
+#define PINCONF_GPIO7p20         (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSF|PINCONF_PIN_6)
+#define PINCONF_GPIO7p21         (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSF|PINCONF_PIN_7)
+#define PINCONF_GPIO7p22         (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSF|PINCONF_PIN_8)
+#define PINCONF_GPIO7p23         (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSF|PINCONF_PIN_9)
+#define PINCONF_GPIO7p24         (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSF|PINCONF_PIN_10)
+#define PINCONF_GPIO7p25         (PINCONF_FUNC4|PINCONF_INBUFFER|PINCONF_PINSF|PINCONF_PIN_11)
+
+#define PINCONF_GP_CLKIN_1       (PINCONF_FUNC1|PINCONF_PINS4|PINCONF_PIN_7)
+#define PINCONF_GP_CLKIN_2       (PINCONF_FUNC1|PINCONF_PINSF|PINCONF_PIN_0)
+#define PINCONF_GP_CLKIN_3       (PINCONF_FUNC1|PINCONF_PINSF|PINCONF_PIN_4)
+
+#define PINCONF_I2C1_SCL_1       (PINCONF_FUNC1|PINCONF_PINS2|PINCONF_PIN_4)
+#define PINCONF_I2C1_SCL_2       (PINCONF_FUNC2|PINCONF_PINSE|PINCONF_PIN_15)
+#define PINCONF_I2C1_SDA_1       (PINCONF_FUNC1|PINCONF_PINS2|PINCONF_PIN_3)
+#define PINCONF_I2C1_SDA_2       (PINCONF_FUNC2|PINCONF_PINSE|PINCONF_PIN_13)
+
+#define PINCONF_I2S0_RX_MCLK_1   (PINCONF_FUNC1|PINCONF_PINS3|PINCONF_PIN_0)
+#define PINCONF_I2S0_RX_MCLK_2   (PINCONF_FUNC1|PINCONF_PINS6|PINCONF_PIN_0)
+#define PINCONF_I2S0_RX_MCLK_3   (PINCONF_FUNC6|PINCONF_PINS1|PINCONF_PIN_19)
+#define PINCONF_I2S0_RX_SCK_1    (PINCONF_FUNC0|PINCONF_PINS3|PINCONF_PIN_0)
+#define PINCONF_I2S0_RX_SCK_2    (PINCONF_FUNC4|PINCONF_PINS6|PINCONF_PIN_0)
+#define PINCONF_I2S0_RX_SCK_3    (PINCONF_FUNC7|PINCONF_PINSF|PINCONF_PIN_4)
+#define PINCONF_I2S0_RX_SDA_1    (PINCONF_FUNC1|PINCONF_PINS3|PINCONF_PIN_2)
+#define PINCONF_I2S0_RX_SDA_2    (PINCONF_FUNC3|PINCONF_PINS6|PINCONF_PIN_2)
+#define PINCONF_I2S0_RX_WS_1     (PINCONF_FUNC1|PINCONF_PINS3|PINCONF_PIN_1)
+#define PINCONF_I2S0_RX_WS_2     (PINCONF_FUNC3|PINCONF_PINS6|PINCONF_PIN_1)
+#define PINCONF_I2S0_TXWS        (PINCONF_FUNC6|PINCONF_PINS0|PINCONF_PIN_0)
+#define PINCONF_I2S0_TX_MCLK_1   (PINCONF_FUNC3|PINCONF_PINS3|PINCONF_PIN_0)
+#define PINCONF_I2S0_TX_MCLK_2   (PINCONF_FUNC6|PINCONF_PINS3|PINCONF_PIN_3)
+#define PINCONF_I2S0_TX_MCLK_3   (PINCONF_FUNC6|PINCONF_PINSF|PINCONF_PIN_4)
+#define PINCONF_I2S0_TX_SCK_1    (PINCONF_FUNC2|PINCONF_PINS3|PINCONF_PIN_0)
+#define PINCONF_I2S0_TX_SCK_2    (PINCONF_FUNC7|PINCONF_PINS4|PINCONF_PIN_7)
+#define PINCONF_I2S0_TX_SDA_1    (PINCONF_FUNC0|PINCONF_PINS3|PINCONF_PIN_2)
+#define PINCONF_I2S0_TX_SDA_2    (PINCONF_FUNC2|PINCONF_PINS7|PINCONF_PIN_2)
+#define PINCONF_I2S0_TX_SDA_3    (PINCONF_FUNC4|PINCONF_PINS9|PINCONF_PIN_2)
+#define PINCONF_I2S0_TX_SDA_4    (PINCONF_FUNC5|PINCONF_PINS3|PINCONF_PIN_5)
+#define PINCONF_I2S0_TX_SDA_5    (PINCONF_FUNC6|PINCONF_PINSC|PINCONF_PIN_12)
+#define PINCONF_I2S0_TX_WS_1     (PINCONF_FUNC0|PINCONF_PINS3|PINCONF_PIN_1)
+#define PINCONF_I2S0_TX_WS_2     (PINCONF_FUNC2|PINCONF_PINS7|PINCONF_PIN_1)
+#define PINCONF_I2S0_TX_WS_3     (PINCONF_FUNC4|PINCONF_PINS9|PINCONF_PIN_1)
+#define PINCONF_I2S0_TX_WS_4     (PINCONF_FUNC5|PINCONF_PINS3|PINCONF_PIN_4)
+#define PINCONF_I2S0_TX_WS_5     (PINCONF_FUNC6|PINCONF_PINSC|PINCONF_PIN_13)
+
+#define PINCONF_I2S1_RX_MCLK     (PINCONF_FUNC5|PINCONF_PINSA|PINCONF_PIN_0)
+#define PINCONF_I2S1_RX_SDA      (PINCONF_FUNC6|PINCONF_PINS3|PINCONF_PIN_4)
+#define PINCONF_I2S1_RX_WS       (PINCONF_FUNC6|PINCONF_PINS3|PINCONF_PIN_5)
+#define PINCONF_I2S1_TXSDA       (PINCONF_FUNC7|PINCONF_PINS0|PINCONF_PIN_1)
+#define PINCONF_I2S1_TXWS        (PINCONF_FUNC7|PINCONF_PINS0|PINCONF_PIN_0)
+#define PINCONF_I2S1_TX_MCLK_1   (PINCONF_FUNC7|PINCONF_PINS8|PINCONF_PIN_8)
+#define PINCONF_I2S1_TX_MCLK_2   (PINCONF_FUNC7|PINCONF_PINSF|PINCONF_PIN_0)
+#define PINCONF_I2S1_TX_SCK_1    (PINCONF_FUNC6|PINCONF_PINS4|PINCONF_PIN_7)
+#define PINCONF_I2S1_TX_SCK_2    (PINCONF_FUNC7|PINCONF_PINS1|PINCONF_PIN_19)
+#define PINCONF_I2S1_TX_SCK_3    (PINCONF_FUNC7|PINCONF_PINS3|PINCONF_PIN_3)
+#define PINCONF_I2S1_TX_SDA      (PINCONF_FUNC7|PINCONF_PINSF|PINCONF_PIN_6)
+#define PINCONF_I2S1_TX_WS       (PINCONF_FUNC7|PINCONF_PINSF|PINCONF_PIN_7)
+
+#define PINCONF_LCD_DCLK_1       (PINCONF_FUNC0|PINCONF_PINS4|PINCONF_PIN_7)
+#define PINCONF_LCD_DCLK_2       (PINCONF_FUNC4|PINCONF_PINSC|PINCONF_PIN_0)
+#define PINCONF_LCD_ENAB         (PINCONF_FUNC2|PINCONF_PINS4|PINCONF_PIN_6)
+#define PINCONF_LCD_FP           (PINCONF_FUNC2|PINCONF_PINS4|PINCONF_PIN_5)
+#define PINCONF_LCD_LCDM         (PINCONF_FUNC2|PINCONF_PINS4|PINCONF_PIN_6)
+#define PINCONF_LCD_LE           (PINCONF_FUNC3|PINCONF_PINS7|PINCONF_PIN_0)
+#define PINCONF_LCD_LP_1         (PINCONF_FUNC3|PINCONF_PINS7|PINCONF_PIN_6)
+#define PINCONF_LCD_LP_2         (PINCONF_FUNC4|PINCONF_PINS8|PINCONF_PIN_6)
+#define PINCONF_LCD_PWR_1        (PINCONF_FUNC3|PINCONF_PINS7|PINCONF_PIN_7)
+#define PINCONF_LCD_PWR_2        (PINCONF_FUNC4|PINCONF_PINS8|PINCONF_PIN_7)
+#define PINCONF_LCD_PWR_3        (PINCONF_FUNC6|PINCONF_PINSB|PINCONF_PIN_5)
+#define PINCONF_LCD_VD0          (PINCONF_FUNC2|PINCONF_PINS4|PINCONF_PIN_1)
+#define PINCONF_LCD_VD1          (PINCONF_FUNC2|PINCONF_PINS4|PINCONF_PIN_4)
+#define PINCONF_LCD_VD2          (PINCONF_FUNC2|PINCONF_PINS4|PINCONF_PIN_3)
+#define PINCONF_LCD_VD3          (PINCONF_FUNC2|PINCONF_PINS4|PINCONF_PIN_2)
+#define PINCONF_LCD_VD4_1        (PINCONF_FUNC3|PINCONF_PINS8|PINCONF_PIN_7)
+#define PINCONF_LCD_VD4_2        (PINCONF_FUNC4|PINCONF_PINS7|PINCONF_PIN_4)
+#define PINCONF_LCD_VD5_1        (PINCONF_FUNC3|PINCONF_PINS8|PINCONF_PIN_6)
+#define PINCONF_LCD_VD5_2        (PINCONF_FUNC4|PINCONF_PINS7|PINCONF_PIN_3)
+#define PINCONF_LCD_VD6_1        (PINCONF_FUNC3|PINCONF_PINS8|PINCONF_PIN_5)
+#define PINCONF_LCD_VD6_2        (PINCONF_FUNC4|PINCONF_PINS7|PINCONF_PIN_2)
+#define PINCONF_LCD_VD7_1        (PINCONF_FUNC3|PINCONF_PINS8|PINCONF_PIN_4)
+#define PINCONF_LCD_VD7_2        (PINCONF_FUNC4|PINCONF_PINS7|PINCONF_PIN_1)
+#define PINCONF_LCD_VD8_1        (PINCONF_FUNC3|PINCONF_PINS7|PINCONF_PIN_5)
+#define PINCONF_LCD_VD8_2        (PINCONF_FUNC4|PINCONF_PINS8|PINCONF_PIN_5)
+#define PINCONF_LCD_VD9          (PINCONF_FUNC2|PINCONF_PINS4|PINCONF_PIN_8)
+#define PINCONF_LCD_VD10         (PINCONF_FUNC2|PINCONF_PINS4|PINCONF_PIN_10)
+#define PINCONF_LCD_VD11         (PINCONF_FUNC2|PINCONF_PINS4|PINCONF_PIN_9)
+#define PINCONF_LCD_VD12_1       (PINCONF_FUNC3|PINCONF_PINS8|PINCONF_PIN_3)
+#define PINCONF_LCD_VD12_2       (PINCONF_FUNC5|PINCONF_PINS4|PINCONF_PIN_2)
+#define PINCONF_LCD_VD12_3       (PINCONF_FUNC7|PINCONF_PINS3|PINCONF_PIN_5)
+#define PINCONF_LCD_VD13_1       (PINCONF_FUNC2|PINCONF_PINSB|PINCONF_PIN_6)
+#define PINCONF_LCD_VD13_2       (PINCONF_FUNC5|PINCONF_PINS4|PINCONF_PIN_0)
+#define PINCONF_LCD_VD13_3       (PINCONF_FUNC7|PINCONF_PINS3|PINCONF_PIN_4)
+#define PINCONF_LCD_VD14_1       (PINCONF_FUNC2|PINCONF_PINSB|PINCONF_PIN_5)
+#define PINCONF_LCD_VD14_2       (PINCONF_FUNC5|PINCONF_PINS4|PINCONF_PIN_10)
+#define PINCONF_LCD_VD14_3       (PINCONF_FUNC6|PINCONF_PINS3|PINCONF_PIN_2)
+#define PINCONF_LCD_VD15_1       (PINCONF_FUNC2|PINCONF_PINSB|PINCONF_PIN_4)
+#define PINCONF_LCD_VD15_2       (PINCONF_FUNC5|PINCONF_PINS4|PINCONF_PIN_9)
+#define PINCONF_LCD_VD15_3       (PINCONF_FUNC6|PINCONF_PINS3|PINCONF_PIN_1)
+#define PINCONF_LCD_VD16_1       (PINCONF_FUNC3|PINCONF_PINS7|PINCONF_PIN_4)
+#define PINCONF_LCD_VD16_2       (PINCONF_FUNC4|PINCONF_PINS8|PINCONF_PIN_4)
+#define PINCONF_LCD_VD17         (PINCONF_FUNC3|PINCONF_PINS7|PINCONF_PIN_3)
+#define PINCONF_LCD_VD18         (PINCONF_FUNC3|PINCONF_PINS7|PINCONF_PIN_2)
+#define PINCONF_LCD_VD19_1       (PINCONF_FUNC3|PINCONF_PINS7|PINCONF_PIN_1)
+#define PINCONF_LCD_VD19_2       (PINCONF_FUNC4|PINCONF_PINS8|PINCONF_PIN_3)
+#define PINCONF_LCD_VD19_3       (PINCONF_FUNC5|PINCONF_PINS4|PINCONF_PIN_1)
+#define PINCONF_LCD_VD19_4       (PINCONF_FUNC6|PINCONF_PINSB|PINCONF_PIN_6)
+#define PINCONF_LCD_VD20_1       (PINCONF_FUNC2|PINCONF_PINSB|PINCONF_PIN_3)
+#define PINCONF_LCD_VD20_2       (PINCONF_FUNC5|PINCONF_PINS4|PINCONF_PIN_4)
+#define PINCONF_LCD_VD21_1       (PINCONF_FUNC2|PINCONF_PINSB|PINCONF_PIN_2)
+#define PINCONF_LCD_VD21_2       (PINCONF_FUNC5|PINCONF_PINS4|PINCONF_PIN_3)
+#define PINCONF_LCD_VD22_1       (PINCONF_FUNC2|PINCONF_PINSB|PINCONF_PIN_1)
+#define PINCONF_LCD_VD22_2       (PINCONF_FUNC5|PINCONF_PINS4|PINCONF_PIN_8)
+#define PINCONF_LCD_VD23_1       (PINCONF_FUNC2|PINCONF_PINSB|PINCONF_PIN_0)
+#define PINCONF_LCD_VD23_2       (PINCONF_FUNC4|PINCONF_PINS7|PINCONF_PIN_5)
+
+#define PINCONF_MCABORT_1        (PINCONF_FUNC1|PINCONF_PINS6|PINCONF_PIN_10)
+#define PINCONF_MCABORT_2        (PINCONF_FUNC1|PINCONF_PINS9|PINCONF_PIN_0)
+#define PINCONF_MCI0_1           (PINCONF_FUNC1|PINCONF_PINS5|PINCONF_PIN_3)
+#define PINCONF_MCI0_2           (PINCONF_FUNC3|PINCONF_PINS8|PINCONF_PIN_2)
+#define PINCONF_MCI1_1           (PINCONF_FUNC1|PINCONF_PINS5|PINCONF_PIN_2)
+#define PINCONF_MCI1_2           (PINCONF_FUNC3|PINCONF_PINS8|PINCONF_PIN_1)
+#define PINCONF_MCI2_1           (PINCONF_FUNC1|PINCONF_PINS5|PINCONF_PIN_1)
+#define PINCONF_MCI2_2           (PINCONF_FUNC3|PINCONF_PINS8|PINCONF_PIN_0)
+#define PINCONF_MCOA0_1          (PINCONF_FUNC1|PINCONF_PINS4|PINCONF_PIN_0)
+#define PINCONF_MCOA0_2          (PINCONF_FUNC1|PINCONF_PINS9|PINCONF_PIN_3)
+#define PINCONF_MCOA1_1          (PINCONF_FUNC1|PINCONF_PINS5|PINCONF_PIN_5)
+#define PINCONF_MCOA1_2          (PINCONF_FUNC1|PINCONF_PINS9|PINCONF_PIN_5)
+#define PINCONF_MCOA2_1          (PINCONF_FUNC1|PINCONF_PINS5|PINCONF_PIN_7)
+#define PINCONF_MCOA2_2          (PINCONF_FUNC1|PINCONF_PINS9|PINCONF_PIN_1)
+#define PINCONF_MCOB0_1          (PINCONF_FUNC1|PINCONF_PINS5|PINCONF_PIN_4)
+#define PINCONF_MCOB0_2          (PINCONF_FUNC1|PINCONF_PINS9|PINCONF_PIN_4)
+#define PINCONF_MCOB1_1          (PINCONF_FUNC1|PINCONF_PINS5|PINCONF_PIN_6)
+#define PINCONF_MCOB1_2          (PINCONF_FUNC1|PINCONF_PINS9|PINCONF_PIN_6)
+#define PINCONF_MCOB2_1          (PINCONF_FUNC1|PINCONF_PINS5|PINCONF_PIN_0)
+#define PINCONF_MCOB2_2          (PINCONF_FUNC1|PINCONF_PINS9|PINCONF_PIN_2)
+
+#define PINCONF_NMI_1            (PINCONF_FUNC1|PINCONF_PINSE|PINCONF_PIN_4)
+#define PINCONF_NMI_2            (PINCONF_FUNC2|PINCONF_PINS4|PINCONF_PIN_0)
+
+#define PINCONF_QEI_IDX          (PINCONF_FUNC1|PINCONF_PINSA|PINCONF_PIN_1)
+#define PINCONF_QEI_PHA          (PINCONF_FUNC1|PINCONF_PINSA|PINCONF_PIN_3)
+#define PINCONF_QEI_PHB          (PINCONF_FUNC1|PINCONF_PINSA|PINCONF_PIN_2)
+
+#define PINCONF_SD_CD_1          (PINCONF_FUNC7|PINCONF_PINS1|PINCONF_PIN_13)
+#define PINCONF_SD_CD_2          (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_8)
+#define PINCONF_SD_CLK           (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_0)
+#define PINCONF_SD_CMD_1         (PINCONF_FUNC7|PINCONF_PINS1|PINCONF_PIN_6)
+#define PINCONF_SD_CMD_2         (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_10)
+#define PINCONF_SD_DAT0_1        (PINCONF_FUNC7|PINCONF_PINS1|PINCONF_PIN_9)
+#define PINCONF_SD_DAT0_2        (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_4)
+#define PINCONF_SD_DAT1_1        (PINCONF_FUNC7|PINCONF_PINS1|PINCONF_PIN_10)
+#define PINCONF_SD_DAT1_2        (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_5)
+#define PINCONF_SD_DAT2_1        (PINCONF_FUNC7|PINCONF_PINS1|PINCONF_PIN_11)
+#define PINCONF_SD_DAT2_2        (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_6)
+#define PINCONF_SD_DAT3_1        (PINCONF_FUNC7|PINCONF_PINS1|PINCONF_PIN_12)
+#define PINCONF_SD_DAT3_2        (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_7)
+#define PINCONF_SD_DAT4          (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_11)
+#define PINCONF_SD_DAT5          (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_12)
+#define PINCONF_SD_DAT6          (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_13)
+#define PINCONF_SD_DAT7          (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_14)
+#define PINCONF_SD_POW_1         (PINCONF_FUNC5|PINCONF_PINSD|PINCONF_PIN_1)
+#define PINCONF_SD_POW_2         (PINCONF_FUNC7|PINCONF_PINS1|PINCONF_PIN_5)
+#define PINCONF_SD_POW_3         (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_9)
+#define PINCONF_SD_RST_1         (PINCONF_FUNC7|PINCONF_PINS1|PINCONF_PIN_3)
+#define PINCONF_SD_RST_2         (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_2)
+#define PINCONF_SD_VOLT0_1       (PINCONF_FUNC7|PINCONF_PINS1|PINCONF_PIN_8)
+#define PINCONF_SD_VOLT0_2       (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_1)
+#define PINCONF_SD_VOLT1_1       (PINCONF_FUNC7|PINCONF_PINS1|PINCONF_PIN_4)
+#define PINCONF_SD_VOLT1_2       (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_3)
+#define PINCONF_SD_VOLT2_1       (PINCONF_FUNC5|PINCONF_PINSD|PINCONF_PIN_16)
+#define PINCONF_SD_VOLT2_2       (PINCONF_FUNC6|PINCONF_PINSF|PINCONF_PIN_11)
+#define PINCONF_SD_WP_1          (PINCONF_FUNC5|PINCONF_PINSD|PINCONF_PIN_15)
+#define PINCONF_SD_WP_2          (PINCONF_FUNC6|PINCONF_PINSF|PINCONF_PIN_10)
+
+#define PINCONF_SGPIO0_1         (PINCONF_FUNC3|PINCONF_PINS0|PINCONF_PIN_0)
+#define PINCONF_SGPIO0_2         (PINCONF_FUNC6|PINCONF_PINS9|PINCONF_PIN_0)
+#define PINCONF_SGPIO0_3         (PINCONF_FUNC6|PINCONF_PINSF|PINCONF_PIN_1)
+#define PINCONF_SGPIO1_1         (PINCONF_FUNC3|PINCONF_PINS0|PINCONF_PIN_1)
+#define PINCONF_SGPIO1_2         (PINCONF_FUNC6|PINCONF_PINS9|PINCONF_PIN_1)
+#define PINCONF_SGPIO1_3         (PINCONF_FUNC6|PINCONF_PINSF|PINCONF_PIN_2)
+#define PINCONF_SGPIO2_1         (PINCONF_FUNC2|PINCONF_PINS1|PINCONF_PIN_15)
+#define PINCONF_SGPIO2_2         (PINCONF_FUNC6|PINCONF_PINS9|PINCONF_PIN_2)
+#define PINCONF_SGPIO2_3         (PINCONF_FUNC6|PINCONF_PINSF|PINCONF_PIN_3)
+#define PINCONF_SGPIO3_1         (PINCONF_FUNC2|PINCONF_PINS1|PINCONF_PIN_16)
+#define PINCONF_SGPIO3_2         (PINCONF_FUNC6|PINCONF_PINS9|PINCONF_PIN_5)
+#define PINCONF_SGPIO3_3         (PINCONF_FUNC6|PINCONF_PINSF|PINCONF_PIN_9)
+#define PINCONF_SGPIO4_1         (PINCONF_FUNC0|PINCONF_PINS2|PINCONF_PIN_0)
+#define PINCONF_SGPIO4_2         (PINCONF_FUNC2|PINCONF_PINS6|PINCONF_PIN_3)
+#define PINCONF_SGPIO4_3         (PINCONF_FUNC6|PINCONF_PINS9|PINCONF_PIN_4)
+#define PINCONF_SGPIO4_4         (PINCONF_FUNC6|PINCONF_PINSF|PINCONF_PIN_5)
+#define PINCONF_SGPIO4_5         (PINCONF_FUNC7|PINCONF_PINS7|PINCONF_PIN_0)
+#define PINCONF_SGPIO4_6         (PINCONF_FUNC7|PINCONF_PINSD|PINCONF_PIN_0)
+#define PINCONF_SGPIO5_1         (PINCONF_FUNC0|PINCONF_PINS2|PINCONF_PIN_1)
+#define PINCONF_SGPIO5_2         (PINCONF_FUNC2|PINCONF_PINS6|PINCONF_PIN_6)
+#define PINCONF_SGPIO5_3         (PINCONF_FUNC6|PINCONF_PINSF|PINCONF_PIN_6)
+#define PINCONF_SGPIO5_4         (PINCONF_FUNC7|PINCONF_PINS7|PINCONF_PIN_1)
+#define PINCONF_SGPIO5_5         (PINCONF_FUNC7|PINCONF_PINSD|PINCONF_PIN_1)
+#define PINCONF_SGPIO6_1         (PINCONF_FUNC0|PINCONF_PINS2|PINCONF_PIN_2)
+#define PINCONF_SGPIO6_2         (PINCONF_FUNC2|PINCONF_PINS6|PINCONF_PIN_7)
+#define PINCONF_SGPIO6_3         (PINCONF_FUNC6|PINCONF_PINSF|PINCONF_PIN_7)
+#define PINCONF_SGPIO6_4         (PINCONF_FUNC7|PINCONF_PINS7|PINCONF_PIN_2)
+#define PINCONF_SGPIO6_5         (PINCONF_FUNC7|PINCONF_PINSD|PINCONF_PIN_2)
+#define PINCONF_SGPIO7_1         (PINCONF_FUNC0|PINCONF_PINS2|PINCONF_PIN_6)
+#define PINCONF_SGPIO7_2         (PINCONF_FUNC2|PINCONF_PINS6|PINCONF_PIN_8)
+#define PINCONF_SGPIO7_3         (PINCONF_FUNC6|PINCONF_PINS1|PINCONF_PIN_0)
+#define PINCONF_SGPIO7_4         (PINCONF_FUNC6|PINCONF_PINSF|PINCONF_PIN_8)
+#define PINCONF_SGPIO7_5         (PINCONF_FUNC7|PINCONF_PINS7|PINCONF_PIN_7)
+#define PINCONF_SGPIO7_6         (PINCONF_FUNC7|PINCONF_PINSD|PINCONF_PIN_3)
+#define PINCONF_SGPIO8_1         (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_1)
+#define PINCONF_SGPIO8_2         (PINCONF_FUNC4|PINCONF_PINS8|PINCONF_PIN_0)
+#define PINCONF_SGPIO8_3         (PINCONF_FUNC6|PINCONF_PINS1|PINCONF_PIN_12)
+#define PINCONF_SGPIO8_4         (PINCONF_FUNC6|PINCONF_PINS9|PINCONF_PIN_6)
+#define PINCONF_SGPIO8_5         (PINCONF_FUNC7|PINCONF_PINS4|PINCONF_PIN_2)
+#define PINCONF_SGPIO8_6         (PINCONF_FUNC7|PINCONF_PINSD|PINCONF_PIN_4)
+#define PINCONF_SGPIO9_1         (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_2)
+#define PINCONF_SGPIO9_2         (PINCONF_FUNC4|PINCONF_PINS8|PINCONF_PIN_1)
+#define PINCONF_SGPIO9_3         (PINCONF_FUNC6|PINCONF_PINS1|PINCONF_PIN_13)
+#define PINCONF_SGPIO9_4         (PINCONF_FUNC6|PINCONF_PINS9|PINCONF_PIN_3)
+#define PINCONF_SGPIO9_5         (PINCONF_FUNC7|PINCONF_PINS4|PINCONF_PIN_3)
+#define PINCONF_SGPIO9_6         (PINCONF_FUNC7|PINCONF_PINSD|PINCONF_PIN_5)
+#define PINCONF_SGPIO10_1        (PINCONF_FUNC2|PINCONF_PINS1|PINCONF_PIN_3)
+#define PINCONF_SGPIO10_2        (PINCONF_FUNC4|PINCONF_PINS8|PINCONF_PIN_2)
+#define PINCONF_SGPIO10_3        (PINCONF_FUNC6|PINCONF_PINS1|PINCONF_PIN_14)
+#define PINCONF_SGPIO10_4        (PINCONF_FUNC7|PINCONF_PINS4|PINCONF_PIN_4)
+#define PINCONF_SGPIO10_5        (PINCONF_FUNC7|PINCONF_PINSD|PINCONF_PIN_6)
+#define PINCONF_SGPIO11_1        (PINCONF_FUNC2|PINCONF_PINS1|PINCONF_PIN_4)
+#define PINCONF_SGPIO11_2        (PINCONF_FUNC5|PINCONF_PINSC|PINCONF_PIN_12)
+#define PINCONF_SGPIO11_3        (PINCONF_FUNC6|PINCONF_PINS1|PINCONF_PIN_17)
+#define PINCONF_SGPIO11_4        (PINCONF_FUNC7|PINCONF_PINS4|PINCONF_PIN_5)
+#define PINCONF_SGPIO11_5        (PINCONF_FUNC7|PINCONF_PINSD|PINCONF_PIN_7)
+#define PINCONF_SGPIO12_1        (PINCONF_FUNC0|PINCONF_PINS2|PINCONF_PIN_3)
+#define PINCONF_SGPIO12_2        (PINCONF_FUNC5|PINCONF_PINSC|PINCONF_PIN_13)
+#define PINCONF_SGPIO12_3        (PINCONF_FUNC6|PINCONF_PINS1|PINCONF_PIN_18)
+#define PINCONF_SGPIO12_4        (PINCONF_FUNC7|PINCONF_PINS4|PINCONF_PIN_6)
+#define PINCONF_SGPIO12_5        (PINCONF_FUNC7|PINCONF_PINSD|PINCONF_PIN_8)
+#define PINCONF_SGPIO13_1        (PINCONF_FUNC0|PINCONF_PINS2|PINCONF_PIN_4)
+#define PINCONF_SGPIO13_2        (PINCONF_FUNC5|PINCONF_PINSC|PINCONF_PIN_14)
+#define PINCONF_SGPIO13_3        (PINCONF_FUNC6|PINCONF_PINS1|PINCONF_PIN_20)
+#define PINCONF_SGPIO13_4        (PINCONF_FUNC7|PINCONF_PINS4|PINCONF_PIN_8)
+#define PINCONF_SGPIO13_5        (PINCONF_FUNC7|PINCONF_PINSD|PINCONF_PIN_9)
+#define PINCONF_SGPIO14_1        (PINCONF_FUNC0|PINCONF_PINS2|PINCONF_PIN_5)
+#define PINCONF_SGPIO14_2        (PINCONF_FUNC6|PINCONF_PINS1|PINCONF_PIN_6)
+#define PINCONF_SGPIO14_3        (PINCONF_FUNC7|PINCONF_PINS4|PINCONF_PIN_9)
+#define PINCONF_SGPIO15_1        (PINCONF_FUNC0|PINCONF_PINS2|PINCONF_PIN_8)
+#define PINCONF_SGPIO15_2        (PINCONF_FUNC6|PINCONF_PINS1|PINCONF_PIN_5)
+#define PINCONF_SGPIO15_3        (PINCONF_FUNC7|PINCONF_PINS4|PINCONF_PIN_10)
+
+#define PINCONF_SPIFI_CS         (PINCONF_FUNC3|PINCONF_SLEW_FAST|PINCONF_PINS3|PINCONF_PIN_8)
+#define PINCONF_SPIFI_MISO       (PINCONF_FUNC3|PINCONF_SLEW_FAST|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_PINS3|PINCONF_PIN_6)
+#define PINCONF_SPIFI_MOSI       (PINCONF_FUNC3|PINCONF_SLEW_FAST|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_PINS3|PINCONF_PIN_7)
+#define PINCONF_SPIFI_SCK        (PINCONF_FUNC3|PINCONF_SLEW_FAST|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_PINS3|PINCONF_PIN_3)
+#define PINCONF_SPIFI_SIO2       (PINCONF_FUNC3|PINCONF_SLEW_FAST|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_PINS3|PINCONF_PIN_5)
+#define PINCONF_SPIFI_SIO3       (PINCONF_FUNC3|PINCONF_SLEW_FAST|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_PINS3|PINCONF_PIN_4)
+
+#define PINCONF_SPI_MISO         (PINCONF_FUNC1|PINCONF_PINS3|PINCONF_PIN_6)
+#define PINCONF_SPI_MOSI         (PINCONF_FUNC1|PINCONF_PINS3|PINCONF_PIN_7)
+#define PINCONF_SPI_SCK          (PINCONF_FUNC1|PINCONF_PINS3|PINCONF_PIN_3)
+#define PINCONF_SPI_SSEL         (PINCONF_FUNC1|PINCONF_PINS3|PINCONF_PIN_8)
+
+#define PINCONF_SSP0_MISO_1      (PINCONF_FUNC2|PINCONF_PINS3|PINCONF_PIN_7)
+#define PINCONF_SSP0_MISO_2      (PINCONF_FUNC2|PINCONF_PINSF|PINCONF_PIN_2)
+#define PINCONF_SSP0_MISO_3      (PINCONF_FUNC5|PINCONF_PINS1|PINCONF_PIN_1)
+#define PINCONF_SSP0_MISO_4      (PINCONF_FUNC5|PINCONF_PINS3|PINCONF_PIN_6)
+#define PINCONF_SSP0_MISO_5      (PINCONF_FUNC7|PINCONF_PINS9|PINCONF_PIN_1)
+#define PINCONF_SSP0_MOSI_1      (PINCONF_FUNC2|PINCONF_PINS3|PINCONF_PIN_8)
+#define PINCONF_SSP0_MOSI_2      (PINCONF_FUNC2|PINCONF_PINSF|PINCONF_PIN_3)
+#define PINCONF_SSP0_MOSI_3      (PINCONF_FUNC5|PINCONF_PINS1|PINCONF_PIN_2)
+#define PINCONF_SSP0_MOSI_4      (PINCONF_FUNC5|PINCONF_PINS3|PINCONF_PIN_7)
+#define PINCONF_SSP0_MOSI_5      (PINCONF_FUNC7|PINCONF_PINS9|PINCONF_PIN_2)
+#define PINCONF_SSP0_SCK_1       (PINCONF_FUNC0|PINCONF_PINSF|PINCONF_PIN_0)
+#define PINCONF_SSP0_SCK_2       (PINCONF_FUNC2|PINCONF_PINS3|PINCONF_PIN_3)
+#define PINCONF_SSP0_SCK_3       (PINCONF_FUNC4|PINCONF_PINS3|PINCONF_PIN_0)
+#define PINCONF_SSP0_SSEL_1      (PINCONF_FUNC2|PINCONF_PINS3|PINCONF_PIN_6)
+#define PINCONF_SSP0_SSEL_2      (PINCONF_FUNC2|PINCONF_PINSF|PINCONF_PIN_1)
+#define PINCONF_SSP0_SSEL_3      (PINCONF_FUNC5|PINCONF_PINS1|PINCONF_PIN_0)
+#define PINCONF_SSP0_SSEL_4      (PINCONF_FUNC5|PINCONF_PINS3|PINCONF_PIN_8)
+#define PINCONF_SSP0_SSEL_5      (PINCONF_FUNC7|PINCONF_PINS9|PINCONF_PIN_0)
+
+#define PINCONF_SSP1_MISO_1      (PINCONF_FUNC1|PINCONF_PINS0|PINCONF_PIN_0)
+#define PINCONF_SSP1_MISO_2      (PINCONF_FUNC2|PINCONF_PINSF|PINCONF_PIN_6)
+#define PINCONF_SSP1_MISO_3      (PINCONF_FUNC5|PINCONF_PINS1|PINCONF_PIN_3)
+#define PINCONF_SSP1_MOSI_1      (PINCONF_FUNC1|PINCONF_PINS0|PINCONF_PIN_1)
+#define PINCONF_SSP1_MOSI_2      (PINCONF_FUNC2|PINCONF_PINSF|PINCONF_PIN_7)
+#define PINCONF_SSP1_MOSI_3      (PINCONF_FUNC5|PINCONF_PINS1|PINCONF_PIN_4)
+#define PINCONF_SSP1_SCK_1       (PINCONF_FUNC0|PINCONF_PINSF|PINCONF_PIN_4)
+#define PINCONF_SSP1_SCK_2       (PINCONF_FUNC1|PINCONF_PINS1|PINCONF_PIN_19)
+#define PINCONF_SSP1_SSEL_1      (PINCONF_FUNC1|PINCONF_PINS1|PINCONF_PIN_20)
+#define PINCONF_SSP1_SSEL_2      (PINCONF_FUNC2|PINCONF_PINSF|PINCONF_PIN_5)
+#define PINCONF_SSP1_SSEL_3      (PINCONF_FUNC5|PINCONF_PINS1|PINCONF_PIN_5)
+
+#define PINCONF_T0_CAP0_1        (PINCONF_FUNC4|PINCONF_PINS1|PINCONF_PIN_13)
+#define PINCONF_T0_CAP0_2        (PINCONF_FUNC7|PINCONF_PINS8|PINCONF_PIN_4)
+#define PINCONF_T0_CAP1_1        (PINCONF_FUNC4|PINCONF_PINS1|PINCONF_PIN_12)
+#define PINCONF_T0_CAP1_2        (PINCONF_FUNC7|PINCONF_PINS8|PINCONF_PIN_5)
+#define PINCONF_T0_CAP2_1        (PINCONF_FUNC4|PINCONF_PINS1|PINCONF_PIN_20)
+#define PINCONF_T0_CAP2_2        (PINCONF_FUNC7|PINCONF_PINS8|PINCONF_PIN_6)
+#define PINCONF_T0_CAP3_1        (PINCONF_FUNC4|PINCONF_PINS1|PINCONF_PIN_17)
+#define PINCONF_T0_CAP3_2        (PINCONF_FUNC7|PINCONF_PINS8|PINCONF_PIN_7)
+#define PINCONF_T0_MAT0_1        (PINCONF_FUNC4|PINCONF_PINS1|PINCONF_PIN_16)
+#define PINCONF_T0_MAT0_2        (PINCONF_FUNC7|PINCONF_PINS8|PINCONF_PIN_0)
+#define PINCONF_T0_MAT1_1        (PINCONF_FUNC4|PINCONF_PINS1|PINCONF_PIN_15)
+#define PINCONF_T0_MAT1_2        (PINCONF_FUNC7|PINCONF_PINS8|PINCONF_PIN_1)
+#define PINCONF_T0_MAT2_1        (PINCONF_FUNC4|PINCONF_PINS1|PINCONF_PIN_14)
+#define PINCONF_T0_MAT2_2        (PINCONF_FUNC7|PINCONF_PINS8|PINCONF_PIN_2)
+#define PINCONF_T0_MAT3_1        (PINCONF_FUNC4|PINCONF_PINS1|PINCONF_PIN_18)
+#define PINCONF_T0_MAT3_2        (PINCONF_FUNC7|PINCONF_PINS8|PINCONF_PIN_3)
+
+#define PINCONF_T1_CAP0          (PINCONF_FUNC5|PINCONF_PINS5|PINCONF_PIN_0)
+#define PINCONF_T1_CAP1          (PINCONF_FUNC5|PINCONF_PINS5|PINCONF_PIN_1)
+#define PINCONF_T1_CAP2          (PINCONF_FUNC5|PINCONF_PINS5|PINCONF_PIN_2)
+#define PINCONF_T1_CAP3          (PINCONF_FUNC5|PINCONF_PINS5|PINCONF_PIN_3)
+#define PINCONF_T1_MAT0          (PINCONF_FUNC5|PINCONF_PINS5|PINCONF_PIN_4)
+#define PINCONF_T1_MAT1          (PINCONF_FUNC5|PINCONF_PINS5|PINCONF_PIN_5)
+#define PINCONF_T1_MAT2          (PINCONF_FUNC5|PINCONF_PINS5|PINCONF_PIN_6)
+#define PINCONF_T1_MAT3          (PINCONF_FUNC5|PINCONF_PINS5|PINCONF_PIN_7)
+
+#define PINCONF_T2_CAP0          (PINCONF_FUNC5|PINCONF_PINS6|PINCONF_PIN_1)
+#define PINCONF_T2_CAP1          (PINCONF_FUNC5|PINCONF_PINS6|PINCONF_PIN_2)
+#define PINCONF_T2_CAP2          (PINCONF_FUNC5|PINCONF_PINS6|PINCONF_PIN_3)
+#define PINCONF_T2_CAP3          (PINCONF_FUNC5|PINCONF_PINS6|PINCONF_PIN_6)
+#define PINCONF_T2_MAT0          (PINCONF_FUNC5|PINCONF_PINS6|PINCONF_PIN_7)
+#define PINCONF_T2_MAT1          (PINCONF_FUNC5|PINCONF_PINS6|PINCONF_PIN_8)
+#define PINCONF_T2_MAT2          (PINCONF_FUNC5|PINCONF_PINS6|PINCONF_PIN_9)
+#define PINCONF_T2_MAT3          (PINCONF_FUNC5|PINCONF_PINS6|PINCONF_PIN_11)
+
+#define PINCONF_T3_CAP0_1        (PINCONF_FUNC6|PINCONF_PINS2|PINCONF_PIN_0)
+#define PINCONF_T3_CAP0_2        (PINCONF_FUNC6|PINCONF_PINSC|PINCONF_PIN_1)
+#define PINCONF_T3_CAP1_1        (PINCONF_FUNC6|PINCONF_PINS2|PINCONF_PIN_1)
+#define PINCONF_T3_CAP1_2        (PINCONF_FUNC6|PINCONF_PINSC|PINCONF_PIN_4)
+#define PINCONF_T3_CAP2_1        (PINCONF_FUNC6|PINCONF_PINS2|PINCONF_PIN_2)
+#define PINCONF_T3_CAP2_2        (PINCONF_FUNC6|PINCONF_PINSC|PINCONF_PIN_5)
+#define PINCONF_T3_CAP3_1        (PINCONF_FUNC6|PINCONF_PINS2|PINCONF_PIN_6)
+#define PINCONF_T3_CAP3_2        (PINCONF_FUNC6|PINCONF_PINSC|PINCONF_PIN_6)
+#define PINCONF_T3_MAT0_1        (PINCONF_FUNC6|PINCONF_PINS2|PINCONF_PIN_3)
+#define PINCONF_T3_MAT0_2        (PINCONF_FUNC6|PINCONF_PINSC|PINCONF_PIN_7)
+#define PINCONF_T3_MAT1_1        (PINCONF_FUNC6|PINCONF_PINS2|PINCONF_PIN_4)
+#define PINCONF_T3_MAT1_2        (PINCONF_FUNC6|PINCONF_PINSC|PINCONF_PIN_8)
+#define PINCONF_T3_MAT2_1        (PINCONF_FUNC6|PINCONF_PINS2|PINCONF_PIN_5)
+#define PINCONF_T3_MAT2_2        (PINCONF_FUNC6|PINCONF_PINSC|PINCONF_PIN_9)
+#define PINCONF_T3_MAT3_1        (PINCONF_FUNC6|PINCONF_PINS2|PINCONF_PIN_7)
+#define PINCONF_T3_MAT3_2        (PINCONF_FUNC6|PINCONF_PINSC|PINCONF_PIN_10)
+
+#define PINCONF_TRACECLK         (PINCONF_FUNC2|PINCONF_PINSF|PINCONF_PIN_4)
+#define PINCONF_TRACEDATA0_1     (PINCONF_FUNC3|PINCONF_PINSF|PINCONF_PIN_5)
+#define PINCONF_TRACEDATA0_2     (PINCONF_FUNC5|PINCONF_PINS7|PINCONF_PIN_4)
+#define PINCONF_TRACEDATA1_1     (PINCONF_FUNC3|PINCONF_PINSF|PINCONF_PIN_6)
+#define PINCONF_TRACEDATA1_2     (PINCONF_FUNC5|PINCONF_PINS7|PINCONF_PIN_5)
+#define PINCONF_TRACEDATA2_1     (PINCONF_FUNC3|PINCONF_PINSF|PINCONF_PIN_7)
+#define PINCONF_TRACEDATA2_2     (PINCONF_FUNC5|PINCONF_PINS7|PINCONF_PIN_6)
+#define PINCONF_TRACEDATA3_1     (PINCONF_FUNC3|PINCONF_PINSF|PINCONF_PIN_8)
+#define PINCONF_TRACEDATA3_2     (PINCONF_FUNC5|PINCONF_PINS7|PINCONF_PIN_7)
+
+#define PINCONF_U0_DIR_1         (PINCONF_FUNC1|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINS2|PINCONF_PIN_6)
+#define PINCONF_U0_DIR_2         (PINCONF_FUNC1|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINSF|PINCONF_PIN_9)
+#define PINCONF_U0_DIR_3         (PINCONF_FUNC2|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINS6|PINCONF_PIN_2)
+#define PINCONF_U0_RXD_1         (PINCONF_FUNC1|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINS2|PINCONF_PIN_1)
+#define PINCONF_U0_RXD_2         (PINCONF_FUNC1|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINSF|PINCONF_PIN_11)
+#define PINCONF_U0_RXD_3         (PINCONF_FUNC2|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINS6|PINCONF_PIN_5)
+#define PINCONF_U0_RXD_4         (PINCONF_FUNC7|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINS9|PINCONF_PIN_6)
+#define PINCONF_U0_TXD_1         (PINCONF_FUNC1|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINS2|PINCONF_PIN_0)
+#define PINCONF_U0_TXD_2         (PINCONF_FUNC1|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINSF|PINCONF_PIN_10)
+#define PINCONF_U0_TXD_3         (PINCONF_FUNC2|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINS6|PINCONF_PIN_4)
+#define PINCONF_U0_TXD_4         (PINCONF_FUNC7|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINS9|PINCONF_PIN_5)
+#define PINCONF_U0_UCLK_1        (PINCONF_FUNC1|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINS2|PINCONF_PIN_2)
+#define PINCONF_U0_UCLK_2        (PINCONF_FUNC1|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINSF|PINCONF_PIN_8)
+#define PINCONF_U0_UCLK_3        (PINCONF_FUNC2|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINS6|PINCONF_PIN_1)
+
+#define PINCONF_U1_CTS_1         (PINCONF_FUNC1|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINS1|PINCONF_PIN_11)
+#define PINCONF_U1_CTS_2         (PINCONF_FUNC2|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINSC|PINCONF_PIN_2)
+#define PINCONF_U1_CTS_3         (PINCONF_FUNC2|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINSE|PINCONF_PIN_7)
+#define PINCONF_U1_CTS_4         (PINCONF_FUNC4|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINS5|PINCONF_PIN_4)
+#define PINCONF_U1_DCD_1         (PINCONF_FUNC1|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINS1|PINCONF_PIN_12)
+#define PINCONF_U1_DCD_2         (PINCONF_FUNC2|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINSC|PINCONF_PIN_11)
+#define PINCONF_U1_DCD_3         (PINCONF_FUNC2|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINSE|PINCONF_PIN_9)
+#define PINCONF_U1_DCD_4         (PINCONF_FUNC4|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINS5|PINCONF_PIN_5)
+#define PINCONF_U1_DSR_1         (PINCONF_FUNC1|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINS1|PINCONF_PIN_7)
+#define PINCONF_U1_DSR_2         (PINCONF_FUNC2|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINSC|PINCONF_PIN_10)
+#define PINCONF_U1_DSR_3         (PINCONF_FUNC2|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINSE|PINCONF_PIN_8)
+#define PINCONF_U1_DSR_4         (PINCONF_FUNC4|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINS5|PINCONF_PIN_0)
+#define PINCONF_U1_DTR_1         (PINCONF_FUNC1|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINS1|PINCONF_PIN_8)
+#define PINCONF_U1_DTR_2         (PINCONF_FUNC2|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINSC|PINCONF_PIN_12)
+#define PINCONF_U1_DTR_3         (PINCONF_FUNC2|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINSE|PINCONF_PIN_10)
+#define PINCONF_U1_DTR_4         (PINCONF_FUNC4|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINS5|PINCONF_PIN_1)
+#define PINCONF_U1_RI_1          (PINCONF_FUNC1|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINS1|PINCONF_PIN_10)
+#define PINCONF_U1_RI_2          (PINCONF_FUNC2|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINSC|PINCONF_PIN_1)
+#define PINCONF_U1_RI_3          (PINCONF_FUNC2|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINSE|PINCONF_PIN_6)
+#define PINCONF_U1_RI_4          (PINCONF_FUNC4|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINS5|PINCONF_PIN_3)
+#define PINCONF_U1_RTS_1         (PINCONF_FUNC1|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINS1|PINCONF_PIN_9)
+#define PINCONF_U1_RTS_2         (PINCONF_FUNC2|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINSC|PINCONF_PIN_3)
+#define PINCONF_U1_RTS_3         (PINCONF_FUNC2|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINSE|PINCONF_PIN_5)
+#define PINCONF_U1_RTS_4         (PINCONF_FUNC4|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINS5|PINCONF_PIN_2)
+#define PINCONF_U1_RXD_1         (PINCONF_FUNC1|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINS1|PINCONF_PIN_14)
+#define PINCONF_U1_RXD_2         (PINCONF_FUNC2|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINSC|PINCONF_PIN_14)
+#define PINCONF_U1_RXD_3         (PINCONF_FUNC2|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINSE|PINCONF_PIN_12)
+#define PINCONF_U1_RXD_4         (PINCONF_FUNC4|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINS3|PINCONF_PIN_5)
+#define PINCONF_U1_RXD_5         (PINCONF_FUNC4|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINS5|PINCONF_PIN_7)
+#define PINCONF_U1_TXD_1         (PINCONF_FUNC1|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINS1|PINCONF_PIN_13)
+#define PINCONF_U1_TXD_2         (PINCONF_FUNC2|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINSC|PINCONF_PIN_13)
+#define PINCONF_U1_TXD_3         (PINCONF_FUNC2|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINSE|PINCONF_PIN_11)
+#define PINCONF_U1_TXD_4         (PINCONF_FUNC4|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINS3|PINCONF_PIN_4)
+#define PINCONF_U1_TXD_5         (PINCONF_FUNC4|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINS5|PINCONF_PIN_6)
+
+#define PINCONF_U2_DIR_1         (PINCONF_FUNC1|PINCONF_PINS1|PINCONF_PIN_18)
+#define PINCONF_U2_DIR_2         (PINCONF_FUNC7|PINCONF_PINS2|PINCONF_PIN_13)
+#define PINCONF_U2_RXD_1         (PINCONF_FUNC1|PINCONF_PINS1|PINCONF_PIN_16)
+#define PINCONF_U2_RXD_2         (PINCONF_FUNC2|PINCONF_PINS2|PINCONF_PIN_11)
+#define PINCONF_U2_RXD_3         (PINCONF_FUNC3|PINCONF_PINSA|PINCONF_PIN_2)
+#define PINCONF_U2_RXD_4         (PINCONF_FUNC6|PINCONF_PINS7|PINCONF_PIN_2)
+#define PINCONF_U2_TXD_1         (PINCONF_FUNC1|PINCONF_PINS1|PINCONF_PIN_15)
+#define PINCONF_U2_TXD_2         (PINCONF_FUNC2|PINCONF_PINS2|PINCONF_PIN_10)
+#define PINCONF_U2_TXD_3         (PINCONF_FUNC3|PINCONF_PINSA|PINCONF_PIN_1)
+#define PINCONF_U2_TXD_4         (PINCONF_FUNC6|PINCONF_PINS7|PINCONF_PIN_1)
+#define PINCONF_U2_UCLK_1        (PINCONF_FUNC1|PINCONF_PINS1|PINCONF_PIN_17)
+#define PINCONF_U2_UCLK_2        (PINCONF_FUNC7|PINCONF_PINS2|PINCONF_PIN_12)
+
+#define PINCONF_U3_BAUD_1        (PINCONF_FUNC1|PINCONF_PINSF|PINCONF_PIN_7)
+#define PINCONF_U3_BAUD_2        (PINCONF_FUNC2|PINCONF_PINS2|PINCONF_PIN_9)
+#define PINCONF_U3_BAUD_3        (PINCONF_FUNC6|PINCONF_PINS4|PINCONF_PIN_3)
+#define PINCONF_U3_DIR_1         (PINCONF_FUNC1|PINCONF_PINSF|PINCONF_PIN_6)
+#define PINCONF_U3_DIR_2         (PINCONF_FUNC2|PINCONF_PINS2|PINCONF_PIN_8)
+#define PINCONF_U3_DIR_3         (PINCONF_FUNC6|PINCONF_PINS4|PINCONF_PIN_4)
+#define PINCONF_U3_RXD_1         (PINCONF_FUNC1|PINCONF_PINSF|PINCONF_PIN_3)
+#define PINCONF_U3_RXD_2         (PINCONF_FUNC2|PINCONF_PINS2|PINCONF_PIN_4)
+#define PINCONF_U3_RXD_3         (PINCONF_FUNC6|PINCONF_PINS4|PINCONF_PIN_2)
+#define PINCONF_U3_RXD_4         (PINCONF_FUNC7|PINCONF_PINS9|PINCONF_PIN_4)
+#define PINCONF_U3_TXD_1         (PINCONF_FUNC1|PINCONF_PINSF|PINCONF_PIN_2)
+#define PINCONF_U3_TXD_2         (PINCONF_FUNC2|PINCONF_PINS2|PINCONF_PIN_3)
+#define PINCONF_U3_TXD_3         (PINCONF_FUNC6|PINCONF_PINS4|PINCONF_PIN_1)
+#define PINCONF_U3_TXD_4         (PINCONF_FUNC7|PINCONF_PINS9|PINCONF_PIN_3)
+#define PINCONF_U3_UCLK_1        (PINCONF_FUNC1|PINCONF_PINSF|PINCONF_PIN_5)
+#define PINCONF_U3_UCLK_2        (PINCONF_FUNC2|PINCONF_PINS2|PINCONF_PIN_7)
+#define PINCONF_U3_UCLK_3        (PINCONF_FUNC6|PINCONF_PINS4|PINCONF_PIN_0)
+
+#define PINCONF_USB0_IND0_1      (PINCONF_FUNC1|PINCONF_PINS8|PINCONF_PIN_2)
+#define PINCONF_USB0_IND0_2      (PINCONF_FUNC3|PINCONF_PINS2|PINCONF_PIN_6)
+#define PINCONF_USB0_IND0_3      (PINCONF_FUNC3|PINCONF_PINS6|PINCONF_PIN_8)
+#define PINCONF_USB0_IND0_4      (PINCONF_FUNC4|PINCONF_PINS1|PINCONF_PIN_4)
+#define PINCONF_USB0_IND0_5      (PINCONF_FUNC7|PINCONF_PINS2|PINCONF_PIN_5)
+#define PINCONF_USB0_IND1_1      (PINCONF_FUNC1|PINCONF_PINS8|PINCONF_PIN_1)
+#define PINCONF_USB0_IND1_2      (PINCONF_FUNC3|PINCONF_PINS2|PINCONF_PIN_2)
+#define PINCONF_USB0_IND1_3      (PINCONF_FUNC3|PINCONF_PINS6|PINCONF_PIN_7)
+#define PINCONF_USB0_IND1_4      (PINCONF_FUNC4|PINCONF_PINS1|PINCONF_PIN_3)
+#define PINCONF_USB0_PPWR_1      (PINCONF_FUNC1|PINCONF_PINS6|PINCONF_PIN_3)
+#define PINCONF_USB0_PPWR_2      (PINCONF_FUNC3|PINCONF_PINS2|PINCONF_PIN_0)
+#define PINCONF_USB0_PPWR_3      (PINCONF_FUNC4|PINCONF_PINS1|PINCONF_PIN_7)
+#define PINCONF_USB0_PPWR_4      (PINCONF_FUNC7|PINCONF_PINS2|PINCONF_PIN_3)
+#define PINCONF_USB0_PWR_FAULT_1 (PINCONF_FUNC1|PINCONF_PINS8|PINCONF_PIN_0)
+#define PINCONF_USB0_PWR_FAULT_2 (PINCONF_FUNC3|PINCONF_PINS2|PINCONF_PIN_1)
+#define PINCONF_USB0_PWR_FAULT_3 (PINCONF_FUNC3|PINCONF_PINS6|PINCONF_PIN_6)
+#define PINCONF_USB0_PWR_FAULT_4 (PINCONF_FUNC4|PINCONF_PINS1|PINCONF_PIN_5)
+#define PINCONF_USB0_PWR_FAULT_5 (PINCONF_FUNC7|PINCONF_PINS2|PINCONF_PIN_4)
+
+#define PINCONF_USB1_IND0_1      (PINCONF_FUNC2|PINCONF_PINS9|PINCONF_PIN_4)
+#define PINCONF_USB1_IND0_2      (PINCONF_FUNC3|PINCONF_PINS3|PINCONF_PIN_2)
+#define PINCONF_USB1_IND1_1      (PINCONF_FUNC2|PINCONF_PINS9|PINCONF_PIN_3)
+#define PINCONF_USB1_IND1_2      (PINCONF_FUNC3|PINCONF_PINS3|PINCONF_PIN_1)
+#define PINCONF_USB1_PPWR        (PINCONF_FUNC2|PINCONF_PINS9|PINCONF_PIN_5)
+#define PINCONF_USB1_PWR_FAULT   (PINCONF_FUNC2|PINCONF_PINS9|PINCONF_PIN_6)
+#define PINCONF_USB1_ULPI_CLK_1  (PINCONF_FUNC1|PINCONF_PINS8|PINCONF_PIN_8)
+#define PINCONF_USB1_ULPI_CLK_2  (PINCONF_FUNC1|PINCONF_PINSC|PINCONF_PIN_0)
+#define PINCONF_USB1_ULPI_D0_1   (PINCONF_FUNC1|PINCONF_PINS8|PINCONF_PIN_5)
+#define PINCONF_USB1_ULPI_D0_2   (PINCONF_FUNC1|PINCONF_PINSC|PINCONF_PIN_8)
+#define PINCONF_USB1_ULPI_D0_3   (PINCONF_FUNC5|PINCONF_PINSD|PINCONF_PIN_11)
+#define PINCONF_USB1_ULPI_D1_1   (PINCONF_FUNC1|PINCONF_PINS8|PINCONF_PIN_4)
+#define PINCONF_USB1_ULPI_D1_2   (PINCONF_FUNC1|PINCONF_PINSC|PINCONF_PIN_7)
+#define PINCONF_USB1_ULPI_D2_1   (PINCONF_FUNC1|PINCONF_PINS8|PINCONF_PIN_3)
+#define PINCONF_USB1_ULPI_D2_2   (PINCONF_FUNC1|PINCONF_PINSC|PINCONF_PIN_6)
+#define PINCONF_USB1_ULPI_D3_1   (PINCONF_FUNC1|PINCONF_PINSB|PINCONF_PIN_6)
+#define PINCONF_USB1_ULPI_D3_2   (PINCONF_FUNC1|PINCONF_PINSC|PINCONF_PIN_5)
+#define PINCONF_USB1_ULPI_D4_1   (PINCONF_FUNC1|PINCONF_PINSB|PINCONF_PIN_5)
+#define PINCONF_USB1_ULPI_D4_2   (PINCONF_FUNC1|PINCONF_PINSC|PINCONF_PIN_4)
+#define PINCONF_USB1_ULPI_D5_1   (PINCONF_FUNC0|PINCONF_PINSC|PINCONF_PIN_3)
+#define PINCONF_USB1_ULPI_D5_2   (PINCONF_FUNC1|PINCONF_PINSB|PINCONF_PIN_4)
+#define PINCONF_USB1_ULPI_D6_1   (PINCONF_FUNC0|PINCONF_PINSC|PINCONF_PIN_2)
+#define PINCONF_USB1_ULPI_D6_2   (PINCONF_FUNC1|PINCONF_PINSB|PINCONF_PIN_3)
+#define PINCONF_USB1_ULPI_D7_1   (PINCONF_FUNC0|PINCONF_PINSC|PINCONF_PIN_1)
+#define PINCONF_USB1_ULPI_D7_2   (PINCONF_FUNC1|PINCONF_PINSB|PINCONF_PIN_2)
+#define PINCONF_USB1_ULPI_DIR_1  (PINCONF_FUNC1|PINCONF_PINSB|PINCONF_PIN_1)
+#define PINCONF_USB1_ULPI_DIR_2  (PINCONF_FUNC1|PINCONF_PINSC|PINCONF_PIN_11)
+#define PINCONF_USB1_ULPI_NXT_1  (PINCONF_FUNC1|PINCONF_PINS8|PINCONF_PIN_6)
+#define PINCONF_USB1_ULPI_NXT_2  (PINCONF_FUNC1|PINCONF_PINSC|PINCONF_PIN_9)
+#define PINCONF_USB1_ULPI_STP_1  (PINCONF_FUNC1|PINCONF_PINS8|PINCONF_PIN_7)
+#define PINCONF_USB1_ULPI_STP_2  (PINCONF_FUNC1|PINCONF_PINSC|PINCONF_PIN_10)
+#define PINCONF_USB1_VBUS        (PINCONF_FUNC2|PINCONF_PINS2|PINCONF_PIN_5)
+
+#define CLKCONF_CGU_OUT0         (PINCONFIG_DIGITAL|PINCONF_FUNC5|PINCONF_CLK1)
+#define CLKCONF_CGU_OUT1         (PINCONFIG_DIGITAL|PINCONF_FUNC5|PINCONF_CLK3)
+#define CLKCONF_CLKOUT_1         (PINCONFIG_DIGITAL|PINCONF_FUNC1|PINCONF_CLK0)
+#define CLKCONF_CLKOUT_2         (PINCONFIG_DIGITAL|PINCONF_FUNC1|PINCONF_CLK1)
+#define CLKCONF_CLKOUT_3         (PINCONFIG_DIGITAL|PINCONF_FUNC1|PINCONF_CLK2)
+#define CLKCONF_CLKOUT_4         (PINCONFIG_DIGITAL|PINCONF_FUNC1|PINCONF_CLK3)
+#define CLKCONF_EMC_CLK0         (PINCONFIG_DIGITAL|PINCONF_FUNC0|PINCONF_CLK0)
+#define CLKCONF_EMC_CLK01        (PINCONFIG_DIGITAL|PINCONF_FUNC5|PINCONF_CLK0)
+#define CLKCONF_EMC_CLK1         (PINCONFIG_DIGITAL|PINCONF_FUNC0|PINCONF_CLK1)
+#define CLKCONF_EMC_CLK2         (PINCONFIG_DIGITAL|PINCONF_FUNC0|PINCONF_CLK3)
+#define CLKCONF_EMC_CLK23        (PINCONFIG_DIGITAL|PINCONF_FUNC5|PINCONF_CLK2)
+#define CLKCONF_EMC_CLK3         (PINCONFIG_DIGITAL|PINCONF_FUNC0|PINCONF_CLK2)
+#define CLKCONF_ENET_REF_CLK     (PINCONFIG_DIGITAL|PINCONF_FUNC7|PINCONF_CLK0)
+#define CLKCONF_ENET_TX_CLK      (PINCONFIG_DIGITAL|PINCONF_FUNC7|PINCONF_CLK0)
+#define CLKCONF_I2S0_TX_MCLK     (PINCONFIG_DIGITAL|PINCONF_FUNC6|PINCONF_CLK2)
+#define CLKCONF_I2S1_RX_SCK_1    (PINCONFIG_DIGITAL|PINCONF_FUNC7|PINCONF_CLK2)
+#define CLKCONF_I2S1_RX_SCK_2    (PINCONFIG_DIGITAL|PINCONF_FUNC7|PINCONF_CLK3)
+#define CLKCONF_I2S1_TX_MCLK     (PINCONFIG_DIGITAL|PINCONF_FUNC7|PINCONF_CLK1)
+#define CLKCONF_SD_CLK_1         (PINCONFIG_DIGITAL|PINCONF_FUNC4|PINCONF_CLK0)
+#define CLKCONF_SD_CLK_2         (PINCONFIG_DIGITAL|PINCONF_FUNC4|PINCONF_CLK2)
+#define CLKCONF_SSP1_SCK         (PINCONFIG_DIGITAL|PINCONF_FUNC6|PINCONF_CLK0)
+
+/****************************************************************************************************
+ * Public Types
+ ****************************************************************************************************/
+
+/****************************************************************************************************
+ * Public Data
+ ****************************************************************************************************/
+
+/****************************************************************************************************
+ * Public Functions
+ ****************************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC4310203050_PINCONF_H */
diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc435357_memorymap.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc435357_memorymap.h
new file mode 100644
index 000000000..2cc96fb8e
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc435357_memorymap.h
@@ -0,0 +1,200 @@
+/************************************************************************************
+ * arch/arm/src/lpc43xx/chip/lpc435357_memorymap.h
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC435357_MEMORYMAP_H
+#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC435357_MEMORYMAP_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Memory Map ***********************************************************************/
+/* See arch/arm/include/lpc43xx/chip.h for the actual sizes of FLASH and SRAM
+ * regions
+ */
+
+#define LPC43_SHADOW_BASE          0x00000000 /* -0x0fffffff: 256Mb shadow area */
+#define LPC43_LOCSRAM_BASE         0x10000000 /* -0x1fffffff: Local SRAM and external memory */
+#define LPC43_AHBSRAM_BASE         0x20000000 /* -0x27ffffff: AHB SRAM */
+#define LPC43_DYCS0_BASE           0x28000000 /* -0x2fffffff: 128Mb dynamic external memory */
+#define LPC43_DYCS1_BASE           0x30000000 /* -0x2fffffff: 256Mb dynamic external memory */
+#define LPC43_PERIPH_BASE          0x40000000 /* -0x5fffffff: Peripherals */
+#define LPC43_DYCS2_BASE           0x60000000 /* -0x6fffffff: 256Mb dynamic external memory */
+#define LPC43_DYCS3_BASE           0x70000000 /* -0x7fffffff: 256Mb dynamic external memory */
+#define LPC43_SPIFI_DATA_BASE      0x80000000 /* -0x87ffffff: 256Mb dynamic external memory */
+#define LPC43_ARM_BASE             0xe0000000 /* -0xe00fffff: ARM private */
+
+/* Local SRAM Banks and external memory */
+
+#define LPC43_LOCSRAM_BANK0_BASE   (LPC43_LOCSRAM_BASE + 0x00000000)
+#define LPC43_LOCSRAM_BANK1_BASE   (LPC43_LOCSRAM_BASE + 0x00080000)
+#define LPC43_ROM_BASE             (LPC43_LOCSRAM_BASE + 0x00400000)
+#define LPC43_LOCSRAM_SPIFI_BASE   (LPC43_LOCSRAM_BASE + 0x04000000)
+#define LPC43_LOCSRAM_FLASHA_BASE  (LPC43_LOCSRAM_BASE + 0x0a000000)
+#define LPC43_LOCSRAM_FLASHB_BASE  (LPC43_LOCSRAM_BASE + 0x0b000000)
+#define LPC43_EXTMEM_CS0_BASE      (LPC43_LOCSRAM_BASE + 0x0c000000)
+#define LPC43_EXTMEM_CS1_BASE      (LPC43_LOCSRAM_BASE + 0x0d000000)
+#define LPC43_EXTMEM_CS2_BASE      (LPC43_LOCSRAM_BASE + 0x0e000000)
+#define LPC43_EXTMEM_CS3_BASE      (LPC43_LOCSRAM_BASE + 0x0f000000)
+
+/* ROM Driver Table */
+
+#define LPC43_ROM_DRIVER_TABLE     (LPC43_ROM_BASE+0x00000100)
+#define LPC43_ROM_DRIVER_TABLE0    (LPC43_ROM_DRIVER_TABLE+0x0000)
+#define LPC43_ROM_DRIVER_TABLE1    (LPC43_ROM_DRIVER_TABLE+0x0004)
+#define LPC43_ROM_DRIVER_TABLE2    (LPC43_ROM_DRIVER_TABLE+0x0008)
+#define LPC43_ROM_DRIVER_TABLE3    (LPC43_ROM_DRIVER_TABLE+0x000c)
+#define LPC43_ROM_DRIVER_TABLE4    (LPC43_ROM_DRIVER_TABLE+0x0010)
+#define LPC43_ROM_DRIVER_TABLE5    (LPC43_ROM_DRIVER_TABLE+0x0014)
+#define LPC43_ROM_DRIVER_TABLE6    (LPC43_ROM_DRIVER_TABLE+0x0018)
+#define LPC43_ROM_DRIVER_TABLE7    (LPC43_ROM_DRIVER_TABLE+0x001c)
+
+/* AHB SRAM */
+
+#define LPC43_AHBSRAM_BANK0_BASE   (LPC43_AHBSRAM_BASE)
+#define LPC43_EEPROM_BASE          (LPC43_AHBSRAM_BASE + 0x00004000)
+#define LPC43_AHBSRAM_BITBAND_BASE (LPC43_AHBSRAM_BASE + 0x02000000)
+
+/* Peripherals */
+
+#define LPC43_AHBPERIPH_BASE       (LPC43_PERIPH_BASE + 0x00000000)
+#define LPC43_RTCPERIPH_BASE       (LPC43_PERIPH_BASE + 0x00040000)
+#define LPC43_CLKPERIPH_BASE       (LPC43_PERIPH_BASE + 0x00050000)
+#define LPC43_APB0PERIPH_BASE      (LPC43_PERIPH_BASE + 0x00080000)
+#define LPC43_APB1PERIPH_BASE      (LPC43_PERIPH_BASE + 0x000a0000)
+#define LPC43_APB2PERIPH_BASE      (LPC43_PERIPH_BASE + 0x000c0000)
+#define LPC43_APB3PERIPH_BASE      (LPC43_PERIPH_BASE + 0x000e0000)
+#define LPC43_GPIO_BASE            (LPC43_PERIPH_BASE + 0x000f4000)
+#define LPC43_SPI_BASE             (LPC43_PERIPH_BASE + 0x00100000)
+#define LPC43_SGPIO_BASE           (LPC43_PERIPH_BASE + 0x00101000)
+#define LPC43_PERIPH_BITBAND_BASE  (LPC43_PERIPH_BASE + 0x02000000)
+
+/* AHB Peripherals */
+
+#define LPC43_SCT_BASE             (LPC43_AHBPERIPH_BASE + 0x00000000)
+#define LPC43_DMA_BASE             (LPC43_AHBPERIPH_BASE + 0x00002000)
+#define LPC43_SPIFI_PERIPH_BASE    (LPC43_AHBPERIPH_BASE + 0x00003000)
+#define LPC43_SDMMC_BASE           (LPC43_AHBPERIPH_BASE + 0x00004000)
+#define LPC43_EMC_BASE             (LPC43_AHBPERIPH_BASE + 0x00005000)
+#define LPC43_USB0_BASE            (LPC43_AHBPERIPH_BASE + 0x00006000)
+#define LPC43_USB1_BASE            (LPC43_AHBPERIPH_BASE + 0x00007000)
+#define LPC43_LCD_BASE             (LPC43_AHBPERIPH_BASE + 0x00008000)
+#define LPC43_FLASHA_BASE          (LPC43_AHBPERIPH_BASE + 0x0000c000)
+#define LPC43_FLASHB_BASE          (LPC43_AHBPERIPH_BASE + 0x0000d000)
+#define LPC43_EEPROMC_BASE         (LPC43_AHBPERIPH_BASE + 0x0000e000)
+#define LPC43_ETHERNET_BASE        (LPC43_AHBPERIPH_BASE + 0x00010000)
+
+/* RTC Domain Peripherals */
+
+#define LPC43_ATIMER_BASE          (LPC43_RTCPERIPH_BASE + 0x00000000)
+#define LPC43_BACKUP_BASE          (LPC43_RTCPERIPH_BASE + 0x00001000)
+#define LPC43_PMC_BASE             (LPC43_RTCPERIPH_BASE + 0x00002000)
+#define LPC43_CREG_BASE            (LPC43_RTCPERIPH_BASE + 0x00003000)
+#define LPC43_EVNTRTR_BASE         (LPC43_RTCPERIPH_BASE + 0x00004000)
+#define LPC43_OTPC_BASE            (LPC43_RTCPERIPH_BASE + 0x00005000)
+#define LPC43_RTC_BASE             (LPC43_RTCPERIPH_BASE + 0x00006000)
+#define LPC43_EVNTMNTR_BASE        (LPC43_RTC_BASE       + 0x00000080)
+
+/* Clocking and Reset Peripherals */
+
+#define LPC43_CGU_BASE             (LPC43_CLKPERIPH_BASE + 0x00000000)
+#define LPC43_CCU1_BASE            (LPC43_CLKPERIPH_BASE + 0x00001000)
+#define LPC43_CCU2_BASE            (LPC43_CLKPERIPH_BASE + 0x00002000)
+#define LPC43_RGU_BASE             (LPC43_CLKPERIPH_BASE + 0x00003000)
+
+/* APB0 Peripherals */
+
+#define LPC43_WWDT_BASE            (LPC43_APB0PERIPH_BASE + 0x00000000)
+#define LPC43_USART0_BASE          (LPC43_APB0PERIPH_BASE + 0x00001000)
+#define LPC43_UART1_BASE           (LPC43_APB0PERIPH_BASE + 0x00002000)
+#define LPC43_SSP0_BASE            (LPC43_APB0PERIPH_BASE + 0x00003000)
+#define LPC43_TIMER0_BASE          (LPC43_APB0PERIPH_BASE + 0x00004000)
+#define LPC43_TIMER1_BASE          (LPC43_APB0PERIPH_BASE + 0x00005000)
+#define LPC43_SCU_BASE             (LPC43_APB0PERIPH_BASE + 0x00006000)
+#define LPC43_GPIOINT_BASE         (LPC43_APB0PERIPH_BASE + 0x00007000)
+#define LPC43_GRP0INT_BASE         (LPC43_APB0PERIPH_BASE + 0x00008000)
+#define LPC43_GRP1INT_BASE         (LPC43_APB0PERIPH_BASE + 0x00009000)
+
+/* APB1 Peripherals */
+
+#define LPC43_MCPWM_BASE           (LPC43_APB1PERIPH_BASE + 0x00000000)
+#define LPC43_I2C0_BASE            (LPC43_APB1PERIPH_BASE + 0x00001000)
+#define LPC43_I2S0_BASE            (LPC43_APB1PERIPH_BASE + 0x00002000)
+#define LPC43_I2S1_BASE            (LPC43_APB1PERIPH_BASE + 0x00003000)
+#define LPC43_CAN1_BASE            (LPC43_APB1PERIPH_BASE + 0x00004000)
+
+/* APB2 Peripherals */
+
+#define LPC43_RIT_BASE             (LPC43_APB2PERIPH_BASE + 0x00000000)
+#define LPC43_USART2_BASE          (LPC43_APB2PERIPH_BASE + 0x00001000)
+#define LPC43_USART3_BASE          (LPC43_APB2PERIPH_BASE + 0x00002000)
+#define LPC43_TIMER2_BASE          (LPC43_APB2PERIPH_BASE + 0x00003000)
+#define LPC43_TIMER3_BASE          (LPC43_APB2PERIPH_BASE + 0x00004000)
+#define LPC43_SSP1_BASE            (LPC43_APB2PERIPH_BASE + 0x00005000)
+#define LPC43_QEI_BASE             (LPC43_APB2PERIPH_BASE + 0x00006000)
+#define LPC43_GIMA_BASE            (LPC43_APB2PERIPH_BASE + 0x00007000)
+
+/* APB3 Peripherals */
+
+#define LPC43_I2C1_BASE            (LPC43_APB3PERIPH_BASE + 0x00000000)
+#define LPC43_DAC_BASE             (LPC43_APB3PERIPH_BASE + 0x00001000)
+#define LPC43_CAN0_BASE            (LPC43_APB3PERIPH_BASE + 0x00002000)
+#define LPC43_ADC0_BASE            (LPC43_APB3PERIPH_BASE + 0x00003000)
+#define LPC43_ADC1_BASE            (LPC43_APB3PERIPH_BASE + 0x00004000)
+
+/* ARM Private */
+
+#define LPC43_SCS_BASE             (LPC43_ARM_BASE + 0x0000e000)
+#define LPC43_DEBUGMCU_BASE        (LPC43_ARM_BASE + 0x00042000)
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC435357_MEMORYMAP_H */
diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_adc.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_adc.h
new file mode 100644
index 000000000..bd2c31c08
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_adc.h
@@ -0,0 +1,198 @@
+/************************************************************************************
+ * arch/arm/src/lpc43xx/lpc43_adc.h
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_ADC_H
+#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_ADC_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Register offsets *****************************************************************/
+
+#define LPC43_ADC_CR_OFFSET      0x0000  /* A/D Control Register */
+#define LPC43_ADC_GDR_OFFSET     0x0004  /* A/D Global Data Register */
+#define LPC43_ADC_INTEN_OFFSET   0x000c  /* A/D Interrupt Enable Register */
+
+#define LPC43_ADC_DR_OFFSET(n)   (0x0010+((n) << 2))
+#define LPC43_ADC_DR0_OFFSET     0x0010  /* A/D Channel 0 Data Register */
+#define LPC43_ADC_DR1_OFFSET     0x0014  /* A/D Channel 1 Data Register */
+#define LPC43_ADC_DR2_OFFSET     0x0018  /* A/D Channel 2 Data Register */
+#define LPC43_ADC_DR3_OFFSET     0x001c  /* A/D Channel 3 Data Register */
+#define LPC43_ADC_DR4_OFFSET     0x0020  /* A/D Channel 4 Data Register */
+#define LPC43_ADC_DR5_OFFSET     0x0024  /* A/D Channel 5 Data Register */
+#define LPC43_ADC_DR6_OFFSET     0x0028  /* A/D Channel 6 Data Register */
+#define LPC43_ADC_DR7_OFFSET     0x002c  /* A/D Channel 7 Data Register */
+
+#define LPC43_ADC_STAT_OFFSET    0x0030  /* A/D Status Register */
+
+/* Register addresses ***************************************************************/
+
+#define LPC43_ADC0_CR            (LPC43_ADC0_BASE+LPC43_ADC_CR_OFFSET)
+#define LPC43_ADC0_GDR           (LPC43_ADC0_BASE+LPC43_ADC_GDR_OFFSET)
+#define LPC43_ADC0_INTEN         (LPC43_ADC0_BASE+LPC43_ADC_INTEN_OFFSET)
+#define LPC43_ADC0_DR(n)         (LPC43_ADC0_BASE+LPC43_ADC_DR_OFFSET(n))
+#define LPC43_ADC0_DR0           (LPC43_ADC0_BASE+LPC43_ADC_DR0_OFFSET)
+#define LPC43_ADC0_DR1           (LPC43_ADC0_BASE+LPC43_ADC_DR1_OFFSET)
+#define LPC43_ADC0_DR2           (LPC43_ADC0_BASE+LPC43_ADC_DR2_OFFSET)
+#define LPC43_ADC0_DR3           (LPC43_ADC0_BASE+LPC43_ADC_DR3_OFFSET)
+#define LPC43_ADC0_DR4           (LPC43_ADC0_BASE+LPC43_ADC_DR4_OFFSET)
+#define LPC43_ADC0_DR5           (LPC43_ADC0_BASE+LPC43_ADC_DR5_OFFSET)
+#define LPC43_ADC0_DR6           (LPC43_ADC0_BASE+LPC43_ADC_DR6_OFFSET)
+#define LPC43_ADC0_DR7           (LPC43_ADC0_BASE+LPC43_ADC_DR7_OFFSET)
+#define LPC43_ADC0_STAT          (LPC43_ADC0_BASE+LPC43_ADC_STAT_OFFSET)
+
+#define LPC43_ADC1_CR            (LPC43_ADC1_BASE+LPC43_ADC_CR_OFFSET)
+#define LPC43_ADC1_GDR           (LPC43_ADC1_BASE+LPC43_ADC_GDR_OFFSET)
+#define LPC43_ADC1_INTEN         (LPC43_ADC1_BASE+LPC43_ADC_INTEN_OFFSET)
+#define LPC43_ADC1_DR(n)         (LPC43_ADC1_BASE+LPC43_ADC_DR_OFFSET(n))
+#define LPC43_ADC1_DR0           (LPC43_ADC1_BASE+LPC43_ADC_DR0_OFFSET)
+#define LPC43_ADC1_DR1           (LPC43_ADC1_BASE+LPC43_ADC_DR1_OFFSET)
+#define LPC43_ADC1_DR2           (LPC43_ADC1_BASE+LPC43_ADC_DR2_OFFSET)
+#define LPC43_ADC1_DR3           (LPC43_ADC1_BASE+LPC43_ADC_DR3_OFFSET)
+#define LPC43_ADC1_DR4           (LPC43_ADC1_BASE+LPC43_ADC_DR4_OFFSET)
+#define LPC43_ADC1_DR5           (LPC43_ADC1_BASE+LPC43_ADC_DR5_OFFSET)
+#define LPC43_ADC1_DR6           (LPC43_ADC1_BASE+LPC43_ADC_DR6_OFFSET)
+#define LPC43_ADC1_DR7           (LPC43_ADC1_BASE+LPC43_ADC_DR7_OFFSET)
+#define LPC43_ADC1_STAT          (LPC43_ADC1_BASE+LPC43_ADC_STAT_OFFSET)
+
+/* Register bit definitions *********************************************************/
+
+/* A/D Control Register */
+
+#define ADC_CR_SEL_SHIFT         (0)       /* Bits 0-7: Selects pins to be sampled */
+#define ADC_CR_SEL_MASK          (0xff << ADC_CR_SEL_MASK)
+#define ADC_CR_CLKDIV_SHIFT      (8)       /* Bits 8-15: APB clock (PCLK_ADC0) divisor */
+#define ADC_CR_CLKDIV_MASK       (0xff << ADC_CR_CLKDIV_SHIFT)
+#define ADC_CR_BURST             (1 << 16) /* Bit 16: A/D Repeated conversions */
+
+#define ADC_CR_CLKS_SHIFT        (17)      /* Bits 17-19: Number of clocks in conversion */
+#define ADC_CR_CLKS_MASK         (7 << ADC_CR_CLKS_SHIFT)
+#  define ADC_CR_CLKS_11         (0 << ADC_CR_CLKS_SHIFT) /* 11 clocks / 10 bits */
+#  define ADC_CR_CLKS_10         (1 << ADC_CR_CLKS_SHIFT) /* 10 clocks / 9 bits */
+#  define ADC_CR_CLKS_9          (2 << ADC_CR_CLKS_SHIFT) /* 9 clocks / 8 bits */
+#  define ADC_CR_CLKS_8          (3 << ADC_CR_CLKS_SHIFT) /* 8 clocks / 7 bits */
+#  define ADC_CR_CLKS_7          (4 << ADC_CR_CLKS_SHIFT) /* 7 clocks / 6 bits */
+#  define ADC_CR_CLKS_6          (5 << ADC_CR_CLKS_SHIFT) /* 6 clocks / 5 bits */
+#  define ADC_CR_CLKS_5          (6 << ADC_CR_CLKS_SHIFT) /* 5 clocks / 4 bits */
+#  define ADC_CR_CLKS_4          (7 << ADC_CR_CLKS_SHIFT) /* 4 clocks / 3 bits */
+                                           /* Bit 20: Reserved */
+#define ADC_CR_PDN               (1 << 21) /* Bit 21: A/D converter power-down mode */
+                                           /* Bits 22-23: Reserved */
+#define ADC_CR_START_SHIFT       (24)      /* Bits 24-26: Control A/D conversion start */
+#define ADC_CR_START_MASK        (7 << ADC_CR_START_SHIFT)
+#  define ADC_CR_START_NOSTART   (0 << ADC_CR_START_SHIFT) /* No start */
+#  define ADC_CR_START_NOW       (1 << ADC_CR_START_SHIFT) /* Start now */
+#  define ADC_CR_START_CTOUT15   (2 << ADC_CR_START_SHIFT) /* Start when edge on CTOUT_15 */
+#  define ADC_CR_START_CTOUT8    (3 << ADC_CR_START_SHIFT) /* Start when edge on CTOUT_8 */
+#  define ADC_CR_START_ADCTRIG0  (4 << ADC_CR_START_SHIFT) /* Start when edge on ADCTRIG0 */
+#  define ADC_CR_START_ADCTRIG1  (5 << ADC_CR_START_SHIFT) /* Start when edge on ADCTRIG1 */
+#  define ADC_CR_START_MCPWM     (6 << ADC_CR_START_SHIFT) /* Start when edge on MCPWM */
+#define ADC_CR_EDGE              (1 << 27) /* Bit 27: Start on falling edge  */
+                                           /* Bits 28-31: Reserved */
+/* A/D Global Data Register */
+                                           /* Bits 0-3: Reserved */
+#define ADC_GDR_VVREF_SHIFT      (6)       /* Bits 6-15: Result of conversion (DONE==1) */
+#define ADC_GDR_VVREF_MASK       (0x03ff << ADC_GDR_VVREF_SHIFT)
+                                           /* Bits 16-23: Reserved */
+#define ADC_GDR_CHAN_SHIFT       (24)      /* Bits 24-26: Channel converted */
+#define ADC_GDR_CHAN_MASK        (3 << ADC_GDR_CHN_SHIFT)
+                                           /* Bits 27-29: Reserved */
+#define ADC_GDR_OVERRUN          (1 << 30) /* Bit 30: Conversion(s) lost/overwritten*/
+#define ADC_GDR_DONE             (1 << 31) /* Bit 31: A/D conversion complete*/
+
+/* A/D Interrupt Enable Register */
+
+#define ADC_INTEN_CHAN(n)        (1 << (n))
+#define ADC_INTEN_CHAN0          (1 << 0)  /* Bit 0:  Enable ADC chan 0 complete intterrupt */
+#define ADC_INTEN_CHAN1          (1 << 1)  /* Bit 1:  Enable ADC chan 1 complete interrupt */
+#define ADC_INTEN_CHAN2          (1 << 2)  /* Bit 2:  Enable ADC chan 2 complete interrupt */
+#define ADC_INTEN_CHAN3          (1 << 3)  /* Bit 3:  Enable ADC chan 3 complete interrupt */
+#define ADC_INTEN_CHAN4          (1 << 4)  /* Bit 4:  Enable ADC chan 4 complete interrupt */
+#define ADC_INTEN_CHAN5          (1 << 5)  /* Bit 5:  Enable ADC chan 5 complete interrupt */
+#define ADC_INTEN_CHAN6          (1 << 6)  /* Bit 6:  Enable ADC chan 6 complete interrupt */
+#define ADC_INTEN_CHAN7          (1 << 7)  /* Bit 7:  Enable ADC chan 7 complete interrupt */
+#define ADC_INTEN_GLOBAL         (1 << 8)  /* Bit 8:  Only the global DONE generates interrupt */
+                                           /* Bits 9-31: Reserved */
+/* Channel 0-7 A/D Data Register */
+                                           /* Bits 0-3: Reserved */
+#define ADC_DR_VVREF_SHIFT       (6)       /* Bits 6-15: Result of conversion (DONE==1) */
+#define ADC_DR_VVREF_MASK        (0x03ff << ADC_DR_VVREF_SHIFT)
+                                           /* Bits 16-29: Reserved */
+#define ADC_DR_OVERRUN           (1 << 30) /* Bit 30: Conversion(s) lost/overwritten*/
+#define ADC_DR_DONE              (1 << 31) /* Bit 31: A/D conversion complete*/
+
+/* A/D Status Register */
+
+#define ADC_STAT_DONE(n)         (1 << (n))
+#define ADC_STAT_DONE0           (1 << 0)  /* Bit 0:  A/D chan 0 DONE */
+#define ADC_STAT_DONE1           (1 << 1)  /* Bit 1:  A/D chan 1 DONE */
+#define ADC_STAT_DONE2           (1 << 2)  /* Bit 2:  A/D chan 2 DONE */
+#define ADC_STAT_DONE3           (1 << 3)  /* Bit 3:  A/D chan 3 DONE */
+#define ADC_STAT_DONE4           (1 << 4)  /* Bit 4:  A/D chan 4 DONE */
+#define ADC_STAT_DONE5           (1 << 5)  /* Bit 5:  A/D chan 5 DONE */
+#define ADC_STAT_DONE6           (1 << 6)  /* Bit 6:  A/D chan 6 DONE */
+#define ADC_STAT_DONE7           (1 << 7)  /* Bit 7:  A/D chan 7 DONE */
+#define ADC_STAT_OVERRUN(n)      ((1 << (n)) + 8)
+#define ADC_STAT_OVERRUN0        (1 << 8)  /* Bit 8:  A/D chan 0 OVERRUN */
+#define ADC_STAT_OVERRUN1        (1 << 9)  /* Bit 9:  A/D chan 1 OVERRUN */
+#define ADC_STAT_OVERRUN2        (1 << 10) /* Bit 10: A/D chan 2 OVERRUN */
+#define ADC_STAT_OVERRUN3        (1 << 11) /* Bit 11: A/D chan 3 OVERRUN */
+#define ADC_STAT_OVERRUN4        (1 << 12) /* Bit 12: A/D chan 4 OVERRUN */
+#define ADC_STAT_OVERRUN5        (1 << 13) /* Bit 13: A/D chan 5 OVERRUN */
+#define ADC_STAT_OVERRUN6        (1 << 14) /* Bit 14: A/D chan 6 OVERRUN */
+#define ADC_STAT_OVERRUN7        (1 << 15) /* Bit 15: A/D chan 7 OVERRUN */
+#define ADC_STAT_INT             (1 << 16) /* Bit 15: A/D interrupt */
+                                           /* Bits 17-31: Reserved */
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_ADC_H */
diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_aes.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_aes.h
new file mode 100644
index 000000000..74e53d616
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_aes.h
@@ -0,0 +1,110 @@
+/************************************************************************************
+ * arch/arm/src/lpc43xx/chip/lpc43_aes.h
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_AES_H
+#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_AES_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+/* The AES is controlled through a set of simple API calls located in the LPC43xx
+ * ROM.  This value holds the pointer to the AES driver table.
+ */
+
+#define LPC43_ROM_AES_DRIVER_TABLE LPC43_ROM_DRIVER_TABLE2
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+enum lpc43_aescmd_e
+{
+  AES_API_CMD_ENCODE_ECB = 0,
+  AES_API_CMD_DECODE_ECB = 1, 
+  AES_API_CMD_ENCODE_CBC = 2, 
+  AES_API_CMD_DECODE_CBC = 3 
+};
+
+struct lpc43_aes_s
+{
+  /* Initialize the AES engine */
+
+  void (*aes_Init)(void);
+
+  /* Offset 0x04 -- Defines AES engine operation mode.  See enum lpc43_aescmd_e */
+
+  unsigned int (*aes_SetMode)(unsigned int cmd);
+
+  /* Load 128-bit AES user keys */
+
+  void (*aes_LoadKey1)(void);
+  void (*aes_LoadKey2)(void);
+
+  /* Loads randomly generated key in AES engine. To update the RNG and load a new
+   * random number, use the API call otp_GenRand before aes_LoadKeyRNG.
+   */
+
+  void (*aes_LoadKeyRNG)(void);
+
+  /* Loads 128-bit AES software defined user key (16 bytes) */
+
+  void (*aes_LoadKeySW)(unsigned char *key);
+
+  /* Loads 128-bit AES initialization vector (16 bytes) */
+ 
+  void (*aes_LoadIV_SW)(unsigned char *iv);
+
+  /* Loads 128-bit AES IC specific initialization vector, which is used to decrypt
+   * a boot image.
+   */
+
+  void (*aes_LoadIV_IC)(void);
+};
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_AES_H */
diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_atimer.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_atimer.h
new file mode 100644
index 000000000..1a5ef8602
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_atimer.h
@@ -0,0 +1,117 @@
+/************************************************************************************
+ * arch/arm/src/lpc43xx/chip/lpc43_atimer.h
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_ATIMER_H
+#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_ATIMER_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+/* Register Offsets *****************************************************************/
+
+#define LPC43_ATIMER_COUNT_OFFSET    0x0000 /* Downcounter register */
+#define LPC43_ATIMER_PRESET_OFFSET   0x0004 /* Preset value register */
+#define LPC43_ATIMER_CLREN_OFFSET    0x0fd8 /* Interrupt clear enable register */
+#define LPC43_ATIMER_SETEN_OFFSET    0x0fdc /* Interrupt set enable register */
+#define LPC43_ATIMER_STATUS_OFFSET   0x0fe0 /* Status register */
+#define LPC43_ATIMER_ENABLE_OFFSET   0x0fe4 /* Enable register */
+#define LPC43_ATIMER_CLRSTAT_OFFSET  0x0fe8 /* Clear register */
+#define LPC43_ATIMER_SETSTAT_OFFSET  0x0fec /* Set register */
+
+/* Register Addresses ***************************************************************/
+
+#define LPC43_ATIMER_COUNT           (LPC43_ATIMER_BASE+LPC43_ATIMER_COUNT_OFFSET)
+#define LPC43_ATIMER_PRESET          (LPC43_ATIMER_BASE+LPC43_ATIMER_PRESET_OFFSET)
+#define LPC43_ATIMER_CLREN           (LPC43_ATIMER_BASE+LPC43_ATIMER_CLREN_OFFSET)
+#define LPC43_ATIMER_SETEN           (LPC43_ATIMER_BASE+LPC43_ATIMER_SETEN_OFFSET)
+#define LPC43_ATIMER_STATUS          (LPC43_ATIMER_BASE+LPC43_ATIMER_STATUS_OFFSET)
+#define LPC43_ATIMER_ENABLE          (LPC43_ATIMER_BASE+LPC43_ATIMER_ENABLE_OFFSET)
+#define LPC43_ATIMER_CLRSTAT         (LPC43_ATIMER_BASE+LPC43_ATIMER_CLRSTAT_OFFSET)
+#define LPC43_ATIMER_SETSTAT         (LPC43_ATIMER_BASE+LPC43_ATIMER_SETSTAT_OFFSET)
+
+/* Register Bit Definitions *********************************************************/
+
+/* Downcounter register */
+
+#define ATIMER_COUNT_MASK            0xffff    /* Bits 0-15: Down counter */
+                                               /* Bits 16-31: Reserved */
+/* Preset value register */
+
+#define ATIMER_PRESET_MASK           0xffff    /* Bits 0-15: Counter reload value */
+                                               /* Bits 16-31: Reserved */
+/* Interrupt clear enable register */
+
+#define ATIMER_CLREN                 (1 << 0)  /* Bit 0:  Clear interrupt enable */
+                                               /* Bits 1-31: Reserved */
+/* Interrupt set enable register */
+
+#define ATIMER_SETEN                 (1 << 0)  /* Bit 0:  Set interrupt enable */
+                                               /* Bits 1-31: Reserved */
+/* Status register */
+
+#define ATIMER_STATUS                (1 << 0)  /* Bit 0:  Interrupt status */
+                                               /* Bits 1-31: Reserved */
+/* Enable register */
+
+#define ATIMER_ENABLE                (1 << 0)  /* Bit 0:  Interrupt enable status */
+                                               /* Bits 1-31: Reserved */
+/* Clear register */
+
+#define ATIMER_CLRSTAT               (1 << 0)  /* Bit 0:  Clear interrupt status */
+                                               /* Bits 1-31: Reserved */
+/* Set register */
+
+#define ATIMER_SETSTAT               (1 << 0)  /* Bit 0:  Set interrupt status */
+                                               /* Bits 1-31: Reserved */
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_ATIMER_H */
diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_can.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_can.h
new file mode 100644
index 000000000..cebeaccd8
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_can.h
@@ -0,0 +1,458 @@
+/************************************************************************************
+ * arch/arm/src/lpc43xx/chip/lpc43_can.h
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_CAN_H
+#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_CAN_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+/* Register Offsets *****************************************************************/
+
+#define LPC43_CAN_CNTL_OFFSET        0x0000 /* CAN control register */
+#define LPC43_CAN_STAT_OFFSET        0x0004 /* Status register */
+#define LPC43_CAN_EC_OFFSET          0x0008 /* Error counter register */
+#define LPC43_CAN_BT_OFFSET          0x000c /* Bit timing register */
+#define LPC43_CAN_INT_OFFSET         0x0010 /* Interrupt register */
+#define LPC43_CAN_TEST_OFFSET        0x0014 /* Test register */
+#define LPC43_CAN_BRPE_OFFSET        0x0018 /* Baud rate prescaler extension register */
+
+#define LPC43_CAN_IF1_CMDREQ_OFFSET  0x0020 /* Message interface 1 command request */
+#define LPC43_CAN_IF1_CMDMSKW_OFFSET 0x0024 /* Message interface 1 command mask (write) */
+#define LPC43_CAN_IF1_CMDMSKR_OFFSET 0x0024 /* Message interface 1 command mask (read) */
+#define LPC43_CAN_IF1_MSK1_OFFSET    0x0028 /* Message interface 1 mask 1 */
+#define LPC43_CAN_IF1_MSK2_OFFSET    0x002c /* Message interface 1 mask 2 */
+#define LPC43_CAN_IF1_ARB1_OFFSET    0x0030 /* Message interface 1 arbitration */
+#define LPC43_CAN_IF1_ARB2_OFFSET    0x0034 /* Message interface 1 arbitration */
+#define LPC43_CAN_IF1_MCTRL_OFFSET   0x0038 /* Message interface 1 message control */
+#define LPC43_CAN_IF1_DA1_OFFSET     0x003c /* Message interface 1 data A1 */
+#define LPC43_CAN_IF1_DA2_OFFSET     0x0040 /* Message interface 1 data A2 */
+#define LPC43_CAN_IF1_DB1_OFFSET     0x0044 /* Message interface 1 data B1 */
+#define LPC43_CAN_IF1_DB2_OFFSET     0x0048 /* Message interface 1 data B2 */
+
+#define LPC43_CAN_IF2_CMDREQ_OFFSET  0x0080 /* Message interface 2 command request */
+#define LPC43_CAN_IF2_CMDMSKW_OFFSET 0x0084 /* Message interface 2 command mask (write) */
+#define LPC43_CAN_IF2_CMDMSKR_OFFSET 0x0084 /* Message interface 2 command mask (read) */
+#define LPC43_CAN_IF2_MSK1_OFFSET    0x0088 /* Message interface 2 mask 1 */
+#define LPC43_CAN_IF2_MSK2_OFFSET    0x008c /* Message interface 2 mask 2 */
+#define LPC43_CAN_IF2_ARB1_OFFSET    0x0090 /* Message interface 2 arbitration 1 */
+#define LPC43_CAN_IF2_ARB2_OFFSET    0x0094 /* Message interface 2 arbitration 2 */
+#define LPC43_CAN_IF2_MCTRL_OFFSET   0x0098 /* Message interface 2 message control */
+#define LPC43_CAN_IF2_DA1_OFFSET     0x009c /* Message interface 2 data A1 */
+#define LPC43_CAN_IF2_DA2_OFFSET     0x00a0 /* Message interface 2 data A2 */
+#define LPC43_CAN_IF2_DB1_OFFSET     0x00a4 /* Message interface 2 data B1 */
+#define LPC43_CAN_IF2_DB2_OFFSET     0x00a8 /* Message interface 2 data B2 */
+
+#define LPC43_CAN_TXREQ1_OFFSET      0x0100 /* Transmission request 1 */
+#define LPC43_CAN_TXREQ2_OFFSET      0x0104 /* Transmission request 2 */
+#define LPC43_CAN_ND1_OFFSET         0x0120 /* New data 1 */
+#define LPC43_CAN_ND2_OFFSET         0x0124 /* New data 2 */
+#define LPC43_CAN_IR1_OFFSET         0x0140 /* Interrupt pending 1 */
+#define LPC43_CAN_IR2_OFFSET         0x0144 /* Interrupt pending 2 */
+#define LPC43_CAN_MSGV1_OFFSET       0x0160 /* Message valid 1 */
+#define LPC43_CAN_MSGV2_OFFSET       0x0164 /* Message valid 2 */
+#define LPC43_CAN_CLKDIV_OFFSET      0x0180 /* CAN clock divider register */
+
+/* Register Addresses ***************************************************************/
+
+#define LPC43_CAN1_CNTL              (LPC43_CAN1_BASE+LPC43_CAN_CNTL_OFFSET)
+#define LPC43_CAN1_STAT              (LPC43_CAN1_BASE+LPC43_CAN_STAT_OFFSET)
+#define LPC43_CAN1_EC                (LPC43_CAN1_BASE+LPC43_CAN_EC_OFFSET)
+#define LPC43_CAN1_BT                (LPC43_CAN1_BASE+LPC43_CAN_BT_OFFSET)
+#define LPC43_CAN1_INT               (LPC43_CAN1_BASE+LPC43_CAN_INT_OFFSET)
+#define LPC43_CAN1_TEST              (LPC43_CAN1_BASE+LPC43_CAN_TEST_OFFSET)
+#define LPC43_CAN1_BRPE              (LPC43_CAN1_BASE+LPC43_CAN_BRPE_OFFSET)
+
+#define LPC43_CAN1_IF1_CMDREQ        (LPC43_CAN1_BASE+LPC43_CAN_IF1_CMDREQ_OFFSET)
+#define LPC43_CAN1_IF1_CMDMSKW       (LPC43_CAN1_BASE+LPC43_CAN_IF1_CMDMSKW_OFFSET)
+#define LPC43_CAN1_IF1_CMDMSKR       (LPC43_CAN1_BASE+LPC43_CAN_IF1_CMDMSKR_OFFSET)
+#define LPC43_CAN1_IF1_MSK1          (LPC43_CAN1_BASE+LPC43_CAN_IF1_MSK1_OFFSET)
+#define LPC43_CAN1_IF1_MSK2          (LPC43_CAN1_BASE+LPC43_CAN_IF1_MSK2_OFFSET)
+#define LPC43_CAN1_IF1_ARB1          (LPC43_CAN1_BASE+LPC43_CAN_IF1_ARB1_OFFSET)
+#define LPC43_CAN1_IF1_ARB2          (LPC43_CAN1_BASE+LPC43_CAN_IF1_ARB2_OFFSET)
+#define LPC43_CAN1_IF1_MCTRL         (LPC43_CAN1_BASE+LPC43_CAN_IF1_MCTRL_OFFSET)
+#define LPC43_CAN1_IF1_DA1           (LPC43_CAN1_BASE+LPC43_CAN_IF1_DA1_OFFSET)
+#define LPC43_CAN1_IF1_DA2           (LPC43_CAN1_BASE+LPC43_CAN_IF1_DA2_OFFSET)
+#define LPC43_CAN1_IF1_DB1           (LPC43_CAN1_BASE+LPC43_CAN_IF1_DB1_OFFSET)
+#define LPC43_CAN1_IF1_DB2           (LPC43_CAN1_BASE+LPC43_CAN_IF1_DB2_OFFSET)
+
+#define LPC43_CAN1_IF2_CMDREQ        (LPC43_CAN1_BASE+LPC43_CAN_IF2_CMDREQ_OFFSET)
+#define LPC43_CAN1_IF2_CMDMSKW       (LPC43_CAN1_BASE+LPC43_CAN_IF2_CMDMSKW_OFFSET)
+#define LPC43_CAN1_IF2_CMDMSKR       (LPC43_CAN1_BASE+LPC43_CAN_IF2_CMDMSKR_OFFSET)
+#define LPC43_CAN1_IF2_MSK1          (LPC43_CAN1_BASE+LPC43_CAN_IF2_MSK1_OFFSET)
+#define LPC43_CAN1_IF2_MSK2          (LPC43_CAN1_BASE+LPC43_CAN_IF2_MSK2_OFFSET)
+#define LPC43_CAN1_IF2_ARB1          (LPC43_CAN1_BASE+LPC43_CAN_IF2_ARB1_OFFSET)
+#define LPC43_CAN1_IF2_ARB2          (LPC43_CAN1_BASE+LPC43_CAN_IF2_ARB2_OFFSET)
+#define LPC43_CAN1_IF2_MCTRL         (LPC43_CAN1_BASE+LPC43_CAN_IF2_MCTRL_OFFSET)
+#define LPC43_CAN1_IF2_DA1           (LPC43_CAN1_BASE+LPC43_CAN_IF2_DA1_OFFSET)
+#define LPC43_CAN1_IF2_DA2           (LPC43_CAN1_BASE+LPC43_CAN_IF2_DA2_OFFSET)
+#define LPC43_CAN1_IF2_DB1           (LPC43_CAN1_BASE+LPC43_CAN_IF2_DB1_OFFSET)
+#define LPC43_CAN1_IF2_DB2           (LPC43_CAN1_BASE+LPC43_CAN_IF2_DB2_OFFSET)
+
+#define LPC43_CAN1_TXREQ1            (LPC43_CAN1_BASE+LPC43_CAN_TXREQ1_OFFSET)
+#define LPC43_CAN1_TXREQ2            (LPC43_CAN1_BASE+LPC43_CAN_TXREQ2_OFFSET)
+#define LPC43_CAN1_ND1               (LPC43_CAN1_BASE+LPC43_CAN_ND1_OFFSET)
+#define LPC43_CAN1_ND2               (LPC43_CAN1_BASE+LPC43_CAN_ND2_OFFSET)
+#define LPC43_CAN1_IR1               (LPC43_CAN1_BASE+LPC43_CAN_IR1_OFFSET)
+#define LPC43_CAN1_IR2               (LPC43_CAN1_BASE+LPC43_CAN_IR2_OFFSET)
+#define LPC43_CAN1_MSGV1             (LPC43_CAN1_BASE+LPC43_CAN_MSGV1_OFFSET)
+#define LPC43_CAN1_MSGV2             (LPC43_CAN1_BASE+LPC43_CAN_MSGV2_OFFSET)
+#define LPC43_CAN1_CLKDIV            (LPC43_CAN1_BASE+LPC43_CAN_CLKDIV_OFFSET)
+
+#define LPC43_CAN2_CNTL              (LPC43_CAN2_BASE+LPC43_CAN_CNTL_OFFSET)
+#define LPC43_CAN2_STAT              (LPC43_CAN2_BASE+LPC43_CAN_STAT_OFFSET)
+#define LPC43_CAN2_EC                (LPC43_CAN2_BASE+LPC43_CAN_EC_OFFSET)
+#define LPC43_CAN2_BT                (LPC43_CAN2_BASE+LPC43_CAN_BT_OFFSET)
+#define LPC43_CAN2_INT               (LPC43_CAN2_BASE+LPC43_CAN_INT_OFFSET)
+#define LPC43_CAN2_TEST              (LPC43_CAN2_BASE+LPC43_CAN_TEST_OFFSET)
+#define LPC43_CAN2_BRPE              (LPC43_CAN2_BASE+LPC43_CAN_BRPE_OFFSET)
+
+#define LPC43_CAN2_IF1_CMDREQ        (LPC43_CAN2_BASE+LPC43_CAN_IF1_CMDREQ_OFFSET)
+#define LPC43_CAN2_IF1_CMDMSKW       (LPC43_CAN2_BASE+LPC43_CAN_IF1_CMDMSKW_OFFSET)
+#define LPC43_CAN2_IF1_CMDMSKR       (LPC43_CAN2_BASE+LPC43_CAN_IF1_CMDMSKR_OFFSET)
+#define LPC43_CAN2_IF1_MSK1          (LPC43_CAN2_BASE+LPC43_CAN_IF1_MSK1_OFFSET)
+#define LPC43_CAN2_IF1_MSK2          (LPC43_CAN2_BASE+LPC43_CAN_IF1_MSK2_OFFSET)
+#define LPC43_CAN2_IF1_ARB1          (LPC43_CAN2_BASE+LPC43_CAN_IF1_ARB1_OFFSET)
+#define LPC43_CAN2_IF1_ARB2          (LPC43_CAN2_BASE+LPC43_CAN_IF1_ARB2_OFFSET)
+#define LPC43_CAN2_IF1_MCTRL         (LPC43_CAN2_BASE+LPC43_CAN_IF1_MCTRL_OFFSET)
+#define LPC43_CAN2_IF1_DA1           (LPC43_CAN2_BASE+LPC43_CAN_IF1_DA1_OFFSET)
+#define LPC43_CAN2_IF1_DA2           (LPC43_CAN2_BASE+LPC43_CAN_IF1_DA2_OFFSET)
+#define LPC43_CAN2_IF1_DB1           (LPC43_CAN2_BASE+LPC43_CAN_IF1_DB1_OFFSET)
+#define LPC43_CAN2_IF1_DB2           (LPC43_CAN2_BASE+LPC43_CAN_IF1_DB2_OFFSET)
+
+#define LPC43_CAN2_IF2_CMDREQ        (LPC43_CAN2_BASE+LPC43_CAN_IF2_CMDREQ_OFFSET)
+#define LPC43_CAN2_IF2_CMDMSKW       (LPC43_CAN2_BASE+LPC43_CAN_IF2_CMDMSKW_OFFSET)
+#define LPC43_CAN2_IF2_CMDMSKR       (LPC43_CAN2_BASE+LPC43_CAN_IF2_CMDMSKR_OFFSET)
+#define LPC43_CAN2_IF2_MSK1          (LPC43_CAN2_BASE+LPC43_CAN_IF2_MSK1_OFFSET)
+#define LPC43_CAN2_IF2_MSK2          (LPC43_CAN2_BASE+LPC43_CAN_IF2_MSK2_OFFSET)
+#define LPC43_CAN2_IF2_ARB1          (LPC43_CAN2_BASE+LPC43_CAN_IF2_ARB1_OFFSET)
+#define LPC43_CAN2_IF2_ARB2          (LPC43_CAN2_BASE+LPC43_CAN_IF2_ARB2_OFFSET)
+#define LPC43_CAN2_IF2_MCTRL         (LPC43_CAN2_BASE+LPC43_CAN_IF2_MCTRL_OFFSET)
+#define LPC43_CAN2_IF2_DA1           (LPC43_CAN2_BASE+LPC43_CAN_IF2_DA1_OFFSET)
+#define LPC43_CAN2_IF2_DA2           (LPC43_CAN2_BASE+LPC43_CAN_IF2_DA2_OFFSET)
+#define LPC43_CAN2_IF2_DB1           (LPC43_CAN2_BASE+LPC43_CAN_IF2_DB1_OFFSET)
+#define LPC43_CAN2_IF2_DB2           (LPC43_CAN2_BASE+LPC43_CAN_IF2_DB2_OFFSET)
+
+#define LPC43_CAN2_TXREQ1            (LPC43_CAN2_BASE+LPC43_CAN_TXREQ1_OFFSET)
+#define LPC43_CAN2_TXREQ2            (LPC43_CAN2_BASE+LPC43_CAN_TXREQ2_OFFSET)
+#define LPC43_CAN2_ND1               (LPC43_CAN2_BASE+LPC43_CAN_ND1_OFFSET)
+#define LPC43_CAN2_ND2               (LPC43_CAN2_BASE+LPC43_CAN_ND2_OFFSET)
+#define LPC43_CAN2_IR1               (LPC43_CAN2_BASE+LPC43_CAN_IR1_OFFSET)
+#define LPC43_CAN2_IR2               (LPC43_CAN2_BASE+LPC43_CAN_IR2_OFFSET)
+#define LPC43_CAN2_MSGV1             (LPC43_CAN2_BASE+LPC43_CAN_MSGV1_OFFSET)
+#define LPC43_CAN2_MSGV2             (LPC43_CAN2_BASE+LPC43_CAN_MSGV2_OFFSET)
+#define LPC43_CAN2_CLKDIV            (LPC43_CAN2_BASE+LPC43_CAN_CLKDIV_OFFSET)
+
+/* Register Bit Definitions *********************************************************/
+
+/* CAN control register */
+
+#define CAN_CNTL_INIT                (1 << 0)  /* Bit 0:  Initialization */
+#define CAN_CNTL_IE                  (1 << 1)  /* Bit 1:  Module interrupt enable */
+#define CAN_CNTL_SIE                 (1 << 2)  /* Bit 2:  Status change interrupt enable */
+#define CAN_CNTL_EIE                 (1 << 3)  /* Bit 3:  Error interrupt enable */
+                                               /* Bit 4:  Reserved */
+#define CAN_CNTL_DAR                 (1 << 5)  /* Bit 5:  Disable automatic retransmission */
+#define CAN_CNTL_CCE                 (1 << 6)  /* Bit 6:  Configuration change enable */
+#define CAN_CNTL_TEST                (1 << 7)  /* Bit 7:  Test mode enable */
+                                               /* Bits 8-31: Reserved */
+/* Status register */
+
+#define CAN_STAT_LEC_SHIFT           (0)       /* Bits 0-2: Last error code */
+#define CAN_STAT_LEC_MASK            (7 << CAN_STAT_LEC_SHIFT)
+#define CAN_STAT_LEC_NOE             (0 << CAN_STAT_LEC_SHIFT) /* No error */
+#define CAN_STAT_LEC_STUFFE          (1 << CAN_STAT_LEC_SHIFT) /* Stuff error */
+#define CAN_STAT_LEC_FORME           (2 << CAN_STAT_LEC_SHIFT) /* Form error */
+#define CAN_STAT_LEC_ACKE            (3 << CAN_STAT_LEC_SHIFT) /* AckError */
+#define CAN_STAT_LEC_BI1E            (4 << CAN_STAT_LEC_SHIFT) /* Bit1Error */
+#define CAN_STAT_LEC_BIT0E           (5 << CAN_STAT_LEC_SHIFT) /* Bit0Error */
+#define CAN_STAT_LEC_CRCE            (6 << CAN_STAT_LEC_SHIFT) /* CRCError */
+#define CAN_STAT_TXOK                (1 << 3)  /* Bit 3:  Transmitted a message successfully */
+#define CAN_STAT_RXOK                (1 << 4)  /* Bit 4:  Received a message successfully */
+#define CAN_STAT_EPASS               (1 << 5)  /* Bit 5:  Error passive */
+#define CAN_STAT_EWARN               (1 << 6)  /* Bit 6:  Warning status */
+#define CAN_STAT_BOFF                (1 << 7)  /* Bit 7:  Busoff status */
+                                               /* Bits 8-31: Reserved */
+/* Error counter register */
+
+#define CAN_EC_TEC_SHIFT             (0)       /* Bits 0-7: Transmit error counter */
+#define CAN_EC_TEC_MASK              (0xff << CAN_EC_TEC_SHIFT)
+#define CAN_EC_REC_SHIFT             (8)       /* Bits 8-14: Receive error counter */
+#define CAN_EC_REC_MASK              (0x7f << CAN_EC_REC_SHIFT)
+#define CAN_EC_RP                    (1 << 15)  /* Bit 15:  Receive error passive */
+                                                /* Bits 16-31: Reserved */
+/* Bit timing register */
+
+#define CAN_BT_BRP_SHIFT             (0)        /* Bits 0-5: Baud rate prescaler */
+#define CAN_BT_BRP_MASK              (0x3f << CAN_BT_BRP_SHIFT)
+#define CAN_BT_SJW_SHIFT             (6)        /* Bits 6-7: (Re)synchronization jump width */
+#define CAN_BT_SJW_MASK              (3 << CAN_BT_SJW_SHIFT)
+#define CAN_BT_TSEG1_SHIFT           (8)        /* Bits 8-11: Time segment after the sample point */
+#define CAN_BT_TSEG1_MASK            (15 << CAN_BT_TSEG1_SHIFT)
+#define CAN_BT_TSEG2_SHIFT           (12)       /* Bits 12-14: Time segment before the sample point */
+#define CAN_BT_TSEG2_MASK            (7 << CAN_BT_TSEG2_SHIFT)
+                                                /* Bits 15-31: Reserved */
+/* Interrupt register */
+
+#define CAN_INT_SHIFT                (0)       /* Bits 0-15: Interrupt ID */
+#define CAN_INT_MASK                 (0xffff << CAN_INT_SHIFT)
+#  define CAN_INT_NONE               (0 << CAN_INT_SHIFT)  /* No interrupt pending */
+#  define CAN_INT_MSG1               (1 << CAN_INT_SHIFT)  /* Message 1 */
+#  define CAN_INT_MSG2               (2 << CAN_INT_SHIFT)  /* Message 2 */
+#  define CAN_INT_MSG3               (3 << CAN_INT_SHIFT)  /* Message 3 */
+#  define CAN_INT_MSG4               (4 << CAN_INT_SHIFT)  /* Message 4 */
+#  define CAN_INT_MSG5               (5 << CAN_INT_SHIFT)  /* Message 5 */
+#  define CAN_INT_MSG6               (6 << CAN_INT_SHIFT)  /* Message 6 */
+#  define CAN_INT_MSG7               (7 << CAN_INT_SHIFT)  /* Message 7 */
+#  define CAN_INT_MSG8               (8 << CAN_INT_SHIFT)  /* Message 8 */
+#  define CAN_INT_MSG9               (9 << CAN_INT_SHIFT)  /* Message 9 */
+#  define CAN_INT_MSG10              (10 << CAN_INT_SHIFT) /* Message 10 */
+#  define CAN_INT_MSG11              (11 << CAN_INT_SHIFT) /* Message 11 */
+#  define CAN_INT_MSG12              (12 << CAN_INT_SHIFT) /* Message 12 */
+#  define CAN_INT_MSG13              (13 << CAN_INT_SHIFT) /* Message 13 */
+#  define CAN_INT_MSG14              (14 << CAN_INT_SHIFT) /* Message 14 */
+#  define CAN_INT_MSG15              (15 << CAN_INT_SHIFT) /* Message 15 */
+#  define CAN_INT_MSG16              (16 << CAN_INT_SHIFT) /* Message 16 */
+#  define CAN_INT_MSG17              (17 << CAN_INT_SHIFT) /* Message 17 */
+#  define CAN_INT_MSG18              (18 << CAN_INT_SHIFT) /* Message 18 */
+#  define CAN_INT_MSG19              (19 << CAN_INT_SHIFT) /* Message 19 */
+#  define CAN_INT_MSG20              (20 << CAN_INT_SHIFT) /* Message 20 */
+#  define CAN_INT_MSG21              (21 << CAN_INT_SHIFT) /* Message 21 */
+#  define CAN_INT_MSG22              (22 << CAN_INT_SHIFT) /* Message 22 */
+#  define CAN_INT_MSG23              (23 << CAN_INT_SHIFT) /* Message 23 */
+#  define CAN_INT_MSG24              (24 << CAN_INT_SHIFT) /* Message 24 */
+#  define CAN_INT_MSG25              (25 << CAN_INT_SHIFT) /* Message 25 */
+#  define CAN_INT_MSG26              (26 << CAN_INT_SHIFT) /* Message 26 */
+#  define CAN_INT_MSG27              (27 << CAN_INT_SHIFT) /* Message 27 */
+#  define CAN_INT_MSG28              (28 << CAN_INT_SHIFT) /* Message 28 */
+#  define CAN_INT_MSG29              (29 << CAN_INT_SHIFT) /* Message 29 */
+#  define CAN_INT_MSG30              (30 << CAN_INT_SHIFT) /* Message 30 */
+#  define CAN_INT_MSG31              (31 << CAN_INT_SHIFT) /* Message 31 */
+#  define CAN_INT_MSG32              (32 << CAN_INT_SHIFT) /* Message 32 */
+#  define CAN_INT_MSG32              (0x8000 << CAN_INT_SHIFT) /* Status interrupt */
+                                               /* Bits 16-31: Reserved */
+/* Test register */
+                                               /* Bits 0-1: Reserved */
+#define CAN_TEST_BASIC               (1 << 2)  /* Bit 2:  Basic mode */
+#define CAN_TEST_SILENT              (1 << 3)  /* Bit 3:  Silent mode */
+#define CAN_TEST_LBACK               (1 << 4)  /* Bit 4:  Loop back mode */
+#define CAN_TEST_TX_SHIFT            (5)       /* Bits 5-6: Control of TD pins */
+#define CAN_TEST_TX_MASK             (3 << CAN_TEST_TX_SHIFT)
+#  define CAN_TEST_TX_CAN            (0 << CAN_TEST_TX_SHIFT) /* Level controlled CAN controller */
+#  define CAN_TEST_TX_MONITOR        (1 << CAN_TEST_TX_SHIFT) /* Sample point monitored TD pin */
+#  define CAN_TEST_TX_DOMINANT       (2 << CAN_TEST_TX_SHIFT) /* TD pin LOW/dominant */
+#  define CAN_TEST_TX_RECESSIVE      (3 << CAN_TEST_TX_SHIFT) /* TD pin HIGH/recessive */
+#define CAN_TEST_RX                  (1 << 7)  /* Bit 7:  Monitors actual value of RD Pin */
+                                               /* Bits 8-31: Reserved */
+/* Baud rate prescaler extension register */
+
+#define CAN_BRPE_SHIFT               (0)       /* Bits 0-3: Baud rate prescaler extension */
+#define CAN_BRPE_MASK                (15 << CAN_BRPE_SHIFT)
+                                               /* Bits 4-31: Reserved */
+/* Message interface 1/2 command request */
+
+#define CAN_CMDREQ_MSGNO_SHIFT       (0)       /* Bits 0-5: Message number */
+#define CAN_CMDREQ_MSGNO_MASK        (0x3f << CAN_CMDREQ_MSGNO_SHIFT)
+                                               /* Bits 6-14: Reserved */
+#define CAN_CMDREQ_BUSY              (1 << 15) /* Bit 15: BUSY flag */
+                                               /* Bits 16-31: Reserved */
+/* Message interface 1/2 command mask (write) */
+
+#define CAN_CMDMSKW_DATAB            (1 << 0)  /* Bit 0:  Access data bytes 4-7 */
+#define CAN_CMDMSKW_DATAA            (1 << 1)  /* Bit 1:  Access data bytes 0-3 */
+#define CAN_CMDMSKW_TXRQST           (1 << 2)  /* Bit 2:  Access transmission request bit */
+#define CAN_CMDMSKW_CLRINTPND        (1 << 3)  /* Bit 3:  Ignored in the write direction */
+#define CAN_CMDMSKW_CTRL             (1 << 4)  /* Bit 4:  Access control bits */
+#define CAN_CMDMSKW_ARB              (1 << 5)  /* Bit 5:  Access arbitration bits */
+#define CAN_CMDMSKW_MASK             (1 << 6)  /* Bit 6:  Access mask bits */
+#define CAN_CMDMSKW_WRRD             (1 << 7)  /* Bit 7:  Write transfer (1) */
+                                               /* Bits 8-31: Reserved */
+/* Message interface 1/2 command mask (read) */
+
+#define CAN_CMDMSKR_DATAB            (1 << 0)  /* Bit 0:  Access data bytes 4-7 */
+#define CAN_CMDMSKR_DATAA            (1 << 1)  /* Bit 1:  Access data bytes 0-3 */
+#define CAN_CMDMSKR_NEWDAT           (1 << 2)  /* Bit 2:  Access new data bit */
+#define CAN_CMDMSKR_CLRINTPND        (1 << 3)  /* Bit 3:  Clear interrupt pending bit */
+#define CAN_CMDMSKR_CTRL             (1 << 4)  /* Bit 4:  Access control bits */
+#define CAN_CMDMSKR_ARB              (1 << 5)  /* Bit 5:  Access arbitration bits */
+#define CAN_CMDMSKR_MASK             (1 << 6)  /* Bit 6:  Access mask bits */
+#define CAN_CMDMSKR_WRRD             (1 << 7)  /* Bit 7:  Read transfer (0) */
+                                               /* Bits 8-31: Reserved */
+/* Message interface 1/2 mask 1 */
+
+#define CAN_MSK1                     0xffff    /* Bits 0-15: Identifier mask 0-15 */
+                                               /* Bits 16-31: Reserved */
+/* Message interface 1/2 mask 2 */
+
+#define CAN_MSK2                     0x1fff    /* Bits 0-12: Identifier mask 16-28 */
+                                               /* Bit 13: Reserved */
+#define CAN_MSK2_MDIR                (1 << 14) /* Bit 14: Mask message direction */
+#define CAN_MSK2_MXTD                (1 << 15) /* Bit 15: Mask extend identifier */
+                                               /* Bits 16-31: Reserved */
+/* Message interface 1/2 arbitration */
+
+#define CAN_ARB1                     0xffff    /* Bits 0-15: Identifier mask 0-15 */
+                                               /* Bits 16-31: Reserved */
+/* Message interface 1/2 arbitration */
+
+#define CAN_MSK2                     0x1fff    /* Bits 0-12: Identifier mask 16-28 */
+#define CAN_MSK2_DIR                 (1 << 13) /* Bit 13: Message direction */
+#define CAN_MSK2_XTD                 (1 << 14) /* Bit 14: Extend identifier */
+#define CAN_MSK2_MSGVAL              (1 << 15) /* Bit 15: Message valid */
+                                               /* Bits 16-31: Reserved */
+/* Message interface 1 message control */
+
+#define CAN_MCTRL_DLC_SHIFT          (0)       /* Bits 0-3: Data length code */
+#define CAN_MCTRL_DLC_MASK           (15 << CAN_MCTRL_DLC_SHIFT)
+                                               /* Bits 4-6: Reserved */
+#define CAN_MCTRL_EOB                (1 << 7)  /* Bit 7:  End of buffer */
+#define CAN_MCTRL_TXRQST             (1 << 8)  /* Bit 8:  Transmit request */
+#define CAN_MCTRL_RMTEN              (1 << 9)  /* Bit 9:  Remote enable */
+#define CAN_MCTRL_RXIE               (1 << 10) /* Bit 10: Receive interrupt enable */
+#define CAN_MCTRL_TXIE               (1 << 11) /* Bit 11: Transmit interrupt enable */
+#define CAN_MCTRL_UMASK              (1 << 12) /* Bit 12: Use acceptance mask */
+#define CAN_MCTRL_INTPND             (1 << 13) /* Bit 13: Interrupt pending */
+#define CAN_MCTRL_MSGLST             (1 << 14) /* Bit 14: Message lost */
+#define CAN_MCTRL_NEWDAT             (1 << 15) /* Bit 15: New data */
+                                               /* Bits 16-31: Reserved */
+/* Message interface 1/2 data A1 */
+
+#define CAN_DA1_DATA0_SHIFT          (0)       /* Bits 0-7: Data byte 0 */
+#define CAN_DA1_DATA0_MASK           (0xff << CAN_DA1_DATA0_SHIFT)
+#define CAN_DA1_DATA1_SHIFT          (8)       /* Bits 8-15: Data byte 1 */
+#define CAN_DA1_DATA1_MASK           (0xff << CAN_DA1_DATA1_SHIFT)
+                                               /* Bits 16-31: Reserved */
+/* Message interface 1/2 data A2 */
+
+#define CAN_DA2_DATA2_SHIFT          (0)       /* Bits 0-7: Data byte 2 */
+#define CAN_DA2_DATA2_MASK           (0xff << CAN_DA2_DATA2_SHIFT)
+#define CAN_DA2_DATA3_SHIFT          (8)       /* Bits 8-15: Data byte 3 */
+#define CAN_DA2_DATA3_MASK           (0xff << CAN_DA2_DATA3_SHIFT)
+                                               /* Bits 16-31: Reserved */
+/* Message interface 1/2 data B1 */
+
+#define CAN_DB1_DATA4_SHIFT          (0)       /* Bits 0-7: Data byte 4 */
+#define CAN_DB1_DATA4_MASK           (0xff << CAN_DB1_DATA4_SHIFT)
+#define CAN_DB1_DATA5_SHIFT          (8)       /* Bits 8-15: Data byte 5 */
+#define CAN_DB1_DATA5_MASK           (0xff << CAN_DB1_DATA5_SHIFT)
+                                               /* Bits 16-31: Reserved */
+/* Message interface 1/2 data B2 */
+
+#define CAN_DB2_DATA6_SHIFT          (0)       /* Bits 0-7: Data byte 6 */
+#define CAN_DB2_DATA6_MASK           (0xff << CAN_DB2_DATA6_SHIFT)
+#define CAN_DB2_DATA7_SHIFT          (8)       /* Bits 8-15: Data byte 7 */
+#define CAN_DB2_DATA7_MASK           (0xff << CAN_DB2_DATA6_SHIFT)
+                                               /* Bits 16-31: Reserved */
+/* Transmission request 1 */
+
+#define CAN_TXREQ1_MASK              0xffff    /* Bits 0-15: TX request bit msg 1-16 */
+#define CAN_TXREQ1(n)                (1 << ((n)-1)
+                                               /* Bits 16-31: Reserved */
+/* Transmission request 2 */
+
+#define CAN_TXREQ2_MASK              0xffff    /* Bits 0-15: TX request bit msg 17-32 */
+#define CAN_TXREQ2(n)                (1 << ((n)-17)
+                                               /* Bits 16-31: Reserved */
+/* New data 1 */
+
+#define CAN_ND1_MASK                 0xffff    /* Bits 0-15: New data bits msg 1-16 */
+#define CAN_ND1(n)                   (1 << ((n)-1)
+                                               /* Bits 16-31: Reserved */
+/* New data 2 */
+
+#define CAN_ND2_MASK                 0xffff    /* Bits 0-15: New data bits msg 17-32 */
+#define CAN_ND2(n)                   (1 << ((n)-17)
+                                               /* Bits 16-31: Reserved */
+/* Interrupt pending 1 */
+
+#define CAN_IR1_MASK                 0xffff    /* Bits 0-15: Interrup pending msg 1-16 */
+#define CAN_IR1(n)                   (1 << ((n)-1)
+                                               /* Bits 16-31: Reserved */
+/* Interrupt pending 2 */
+
+#define CAN_IR2_MASK                 0xffff    /* Bits 0-15: Interrup pending msg 17-32 */
+#define CAN_IR2(n)                   (1 << ((n)-17)
+                                               /* Bits 16-31: Reserved */
+/* Message valid 1 */
+
+#define CAN_MSGV1_MASK               0xffff    /* Bits 0-15: Interrup pending msg 1-16 */
+#define CAN_MSGV1(n)                 (1 << ((n)-1)
+                                               /* Bits 16-31: Reserved */
+/* Message valid 2 */
+
+#define CAN_MSGV2_MASK               0xffff    /* Bits 0-15: Interrup pending msg 17-32 */
+#define CAN_MSGV2(n)                 (1 << ((n)-17)
+                                               /* Bits 16-31: Reserved */
+/* CAN clock divider register */
+
+#define CAN_CLKDIV_SHIFT            (0)       /* Bits 0-3: Clock divider value */
+#define CAN_CLKDIV_MASK             (15 << CAN_CLKDIV_SHIFT)
+#  define CAN_CLKDIV_DIV1           (0 << CAN_CLKDIV_SHIFT) /* CAN_CLK = PCLK / 1 */
+#  define CAN_CLKDIV_DIV2           (1 << CAN_CLKDIV_SHIFT) /* CAN_CLK = PCLK / 2 */
+#  define CAN_CLKDIV_DIV3           (2 << CAN_CLKDIV_SHIFT) /* CAN_CLK = PCLK / 3 */
+#  define CAN_CLKDIV_DIV5           (3 << CAN_CLKDIV_SHIFT) /* CAN_CLK = PCLK / 5 */
+#  define CAN_CLKDIV_DIV9           (4 << CAN_CLKDIV_SHIFT) /* CAN_CLK = PCLK / 9 */
+#  define CAN_CLKDIV_DIV 17         (5 << CAN_CLKDIV_SHIFT) /* CAN_CLK = PCLK / 17 */
+#  define CAN_CLKDIV_DIV33          (6 << CAN_CLKDIV_SHIFT) /* CAN_CLK = PCLK / 33 */
+#  define CAN_CLKDIV_DIV65          (7 << CAN_CLKDIV_SHIFT) /* CAN_CLK = PCLK / 65 */
+#  define CAN_CLKDIV_DIV129         (8 << CAN_CLKDIV_SHIFT) /* CAN_CLK = PCLK / 129 */
+#  define CAN_CLKDIV_DIV257         (9 << CAN_CLKDIV_SHIFT) /* CAN_CLK = PCLK / 257 */
+#  define CAN_CLKDIV_DIV513         (10 << CAN_CLKDIV_SHIFT) /* CAN_CLK = PCLK / 513 */
+#  define CAN_CLKDIV_DIV1025        (11 << CAN_CLKDIV_SHIFT) /* CAN_CLK = PCLK / 1025 */
+#  define CAN_CLKDIV_DIV2049        (12 << CAN_CLKDIV_SHIFT) /* CAN_CLK = PCLK / 2049 */
+#  define CAN_CLKDIV_DIV4097        (13 << CAN_CLKDIV_SHIFT) /* CAN_CLK = PCLK / 4097 */
+#  define CAN_CLKDIV_DIV8093        (14 << CAN_CLKDIV_SHIFT) /* CAN_CLK = PCLK / 8093 */
+#  define CAN_CLKDIV_DIV16385       (15 << CAN_CLKDIV_SHIFT) /* CAN_CLK = PCLK / 16385 */
+                                               /* Bits 4-31: Reserved */
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_CAN_H */
diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_ccu.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_ccu.h
new file mode 100644
index 000000000..ff7b4c9ab
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_ccu.h
@@ -0,0 +1,356 @@
+/****************************************************************************************************
+ * arch/arm/src/lpc43xx/chip/lpc43_ccu.h
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_CCU_H
+#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_CCU_H
+
+/****************************************************************************************************
+ * Included Files
+ ****************************************************************************************************/
+
+#include <nuttx/config.h>
+
+/****************************************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************************************/
+/* Register Offsets *********************************************************************************/
+
+#define LPC43_CCU1_PM_OFFSET                0x0000 /* CCU1 power mode register */
+#define LPC43_CCU1_BASE_STAT_OFFSET         0x0004 /* CCU1 base clock status register */
+#define LPC43_CCU1_APB3_BUS_CFG_OFFSET      0x0100  /* CLK_APB3_BUS clock configuration register */
+#define LPC43_CCU1_APB3_BUS_STAT_OFFSET     0x0104  /* CLK_APB3_BUS clock status register */
+#define LPC43_CCU1_APB3_I2C1_CFG_OFFSET     0x0108  /* CLK_APB3_I2C1 configuration register */
+#define LPC43_CCU1_APB3_I2C1_STAT_OFFSET    0x010c  /* CLK_APB3_I2C1 status register */
+#define LPC43_CCU1_APB3_DAC_CFG_OFFSET      0x0110  /* CLK_APB3_DAC configuration register */
+#define LPC43_CCU1_APB3_DAC_STAT_OFFSET     0x0114  /* CLK_APB3_DAC status register */
+#define LPC43_CCU1_APB3_ADC0_CFG_OFFSET     0x0118  /* CLK_APB3_ADC0 configuration register */
+#define LPC43_CCU1_APB3_ADC0_STAT_OFFSET    0x011c  /* CLK_APB3_ADC0 status register */
+#define LPC43_CCU1_APB3_ADC1_CFG_OFFSET     0x0120  /* CLK_APB3_ADC1 configuration register */
+#define LPC43_CCU1_APB3_ADC1_STAT_OFFSET    0x0124  /* CLK_APB3_ADC1 status register */
+#define LPC43_CCU1_APB3_CAN0_CFG_OFFSET     0x0128  /* CLK_APB3_CAN0 configuration register */
+#define LPC43_CCU1_APB3_CAN0_STAT_OFFSET    0x012c  /* CLK_APB3_CAN0 status register */
+#define LPC43_CCU1_APB1_BUS_CFG_OFFSET      0x0200  /* CLK_APB1_BUS configuration register */
+#define LPC43_CCU1_APB1_BUS_STAT_OFFSET     0x0204  /* CLK_APB1_BUS status register */
+#define LPC43_CCU1_APB1_MCPWM_CFG_OFFSET    0x0208  /* CLK_APB1_MOTOCON configuration register */
+#define LPC43_CCU1_APB1_MCPWM_STAT_OFFSET   0x020c  /* CLK_APB1_MOTOCON status register */
+#define LPC43_CCU1_APB1_I2C0_CFG_OFFSET     0x0210  /* CLK_APB1_I2C0 configuration register */
+#define LPC43_CCU1_APB1_I2C0_STAT_OFFSET    0x0214  /* CLK_APB1_I2C0 status register */
+#define LPC43_CCU1_APB1_I2S_CFG_OFFSET      0x0218  /* CLK_APB1_I2S configuration register */
+#define LPC43_CCU1_APB1_I2S_STAT_OFFSET     0x021c  /* CLK_APB1_I2S status register */
+#define LPC43_CCU1_APB1_CAN1_CFG_OFFSET     0x0220  /* CLK_APB3_CAN1 configuration register */
+#define LPC43_CCU1_APB1_CAN1_STAT_OFFSET    0x0224  /* CLK_APB3_CAN1 status register */
+#define LPC43_CCU1_SPIFI_CFG_OFFSET         0x0300  /* CLK_SPIFI configuration register */
+#define LPC43_CCU1_SPIFI_STAT_OFFSET        0x0304  /* CLK_SPIFI status register */
+#define LPC43_CCU1_M4_BUS_CFG_OFFSET        0x0400  /* CLK_M4_BUS configuration register */
+#define LPC43_CCU1_M4_BUS_STAT_OFFSET       0x0404  /* CLK_M4_BUS status register */
+#define LPC43_CCU1_M4_SPIFI_CFG_OFFSET      0x0408  /* CLK_M4_SPIFI configuration register */
+#define LPC43_CCU1_M4_SPIFI_STAT_OFFSET     0x040c  /* CLK_M4_SPIFI status register */
+#define LPC43_CCU1_M4_GPIO_CFG_OFFSET       0x0410  /* CLK_M4_GPIO configuration register */
+#define LPC43_CCU1_M4_GPIO_STAT_OFFSET      0x0414  /* CLK_M4_GPIO status register */
+#define LPC43_CCU1_M4_LCD_CFG_OFFSET        0x0418  /* CLK_M4_LCD configuration register */
+#define LPC43_CCU1_M4_LCD_STAT_OFFSET       0x041c  /* CLK_M4_LCD status register */
+#define LPC43_CCU1_M4_ETHERNET_CFG_OFFSET   0x0420  /* CLK_M4_ETHERNET configuration register */
+#define LPC43_CCU1_M4_ETHERNET_STAT_OFFSET  0x0424  /* CLK_M4_ETHERNET status register */
+#define LPC43_CCU1_M4_USB0_CFG_OFFSET       0x0428  /* CLK_M4_USB0 configuration register */
+#define LPC43_CCU1_M4_USB0_STAT_OFFSET      0x042c  /* CLK_M4_USB0 status register */
+#define LPC43_CCU1_M4_EMC_CFG_OFFSET        0x0430  /* CLK_M4_EMC configuration register */
+#define LPC43_CCU1_M4_EMC_STAT_OFFSET       0x0434  /* CLK_M4_EMC status register */
+#define LPC43_CCU1_M4_SDIO_CFG_OFFSET       0x0438  /* CLK_M4_SDIO configuration register */
+#define LPC43_CCU1_M4_SDIO_STAT_OFFSET      0x043c  /* CLK_M4_SDIO status register */
+#define LPC43_CCU1_M4_DMA_CFG_OFFSET        0x0440  /* CLK_M4_DMA configuration register */
+#define LPC43_CCU1_M4_DMA_STAT_OFFSET       0x0444  /* CLK_M4_DMA status register */
+#define LPC43_CCU1_M4_M4CORE_CFG_OFFSET     0x0448  /* CLK_M4_M4CORE configuration register */
+#define LPC43_CCU1_M4_M4CORE_STAT_OFFSET    0x044c  /* CLK_M4_M4CORE status register */
+#define LPC43_CCU1_M4_SCT_CFG_OFFSET        0x0468  /* CLK_M4_SCT configuration register */
+#define LPC43_CCU1_M4_SCT_STAT_OFFSET       0x046c  /* CLK_M4_SCT status register */
+#define LPC43_CCU1_M4_USB1_CFG_OFFSET       0x0470  /* CLK_M4_USB1 configuration register */
+#define LPC43_CCU1_M4_USB1_STAT_OFFSET      0x0474  /* CLK_M4_USB1 status register */
+#define LPC43_CCU1_M4_EMCDIV_CFG_OFFSET     0x0478  /* CLK_M4_EMCDIV configuration register */
+#define LPC43_CCU1_M4_EMCDIV_STAT_OFFSET    0x047c  /* CLK_M4_EMCDIV status register */
+#define LPC43_CCU1_M4_FLASHA_CFG_OFFSET     0x0480  /* CLK_M4_FLASHA configuration register */
+#define LPC43_CCU1_M4_FLASHA_STAT_OFFSET    0x0484  /* CLK_M4_FLASHA status register */
+#define LPC43_CCU1_M4_FLASHB_CFG_OFFSET     0x0488  /* CLK_M4_FLASHB configuration register */
+#define LPC43_CCU1_M4_FLASHB_STAT_OFFSET    0x048c  /* CLK_M4_FLASHB status register */
+#define LPC43_CCU1_M4_M0APP_CFG_OFFSET      0x0490  /* CLK_M4_M0_CFG configuration register */
+#define LPC43_CCU1_M4_M0APP_STAT_OFFSET     0x0494  /* CLK_M4_M0_STAT status register */
+#define LPC43_CCU1_M4_VADC_CFG_OFFSET       0x0498  /* CLK_M4_VADC_CFG configuration register */
+#define LPC43_CCU1_M4_VADC_STAT_OFFSET      0x049c  /* CLK_M4_VADC_STAT configuration register */
+#define LPC43_CCU1_M4_EEPROM_CFG_OFFSET     0x04a0  /* CLK_M4_EEPROM configuration register */
+#define LPC43_CCU1_M4_EEPROM_STAT_OFFSET    0x04a4  /* CLK_M4_EEPROM status register */
+#define LPC43_CCU1_M4_WWDT_CFG_OFFSET       0x0500  /* CLK_M4_WWDT configuration register */
+#define LPC43_CCU1_M4_WWDT_STAT_OFFSET      0x0504  /* CLK_M4_WWDT status register */
+#define LPC43_CCU1_M4_USART0_CFG_OFFSET     0x0508  /* CLK_M4_USART0 configuration register */
+#define LPC43_CCU1_M4_USART0_STAT_OFFSET    0x050c  /* CLK_M4_USART0 status register */
+#define LPC43_CCU1_M4_UART1_CFG_OFFSET      0x0510  /* CLK_M4_UART1 configuration register */
+#define LPC43_CCU1_M4_UART1_STAT_OFFSET     0x0514  /* CLK_M4_UART1 status register */
+#define LPC43_CCU1_M4_SSP0_CFG_OFFSET       0x0518  /* CLK_M4_SSP0 configuration register */
+#define LPC43_CCU1_M4_SSP0_STAT_OFFSET      0x051c  /* CLK_M4_SSP0 status register */
+#define LPC43_CCU1_M4_TIMER0_CFG_OFFSET     0x0520  /* CLK_M4_TIMER0 configuration register */
+#define LPC43_CCU1_M4_TIMER0_STAT_OFFSET    0x0524  /* CLK_M4_TIMER0 status register */
+#define LPC43_CCU1_M4_TIMER1_CFG_OFFSET     0x0528  /* CLK_M4_TIMER1 configuration register */
+#define LPC43_CCU1_M4_TIMER1_STAT_OFFSET    0x052c  /* CLK_M4_TIMER1 status register */
+#define LPC43_CCU1_M4_SCU_CFG_OFFSET        0x0530  /* CLK_M4_SCU configuration register */
+#define LPC43_CCU1_M4_SCU_STAT_OFFSET       0x0534  /* CLK_M4_SCU status register */
+#define LPC43_CCU1_M4_CREG_CFG_OFFSET       0x0538  /* CLK_M4_CREG configuration register */
+#define LPC43_CCU1_M4_CREG_STAT_OFFSET      0x053c  /* CLK_M4_CREG status register */
+#define LPC43_CCU1_M4_RITIMER_CFG_OFFSET    0x0600  /* CLK_M4_RITIMER configuration register */
+#define LPC43_CCU1_M4_RITIMER_STAT_OFFSET   0x0604  /* CLK_M4_RITIMER status register */
+#define LPC43_CCU1_M4_USART2_CFG_OFFSET     0x0608  /* CLK_M4_USART2 configuration register */
+#define LPC43_CCU1_M4_USART2_STAT_OFFSET    0x060c  /* CLK_M4_USART2 status register */
+#define LPC43_CCU1_M4_USART3_CFG_OFFSET     0x0610  /* CLK_M4_USART3 configuration register */
+#define LPC43_CCU1_M4_USART3_STAT_OFFSET    0x0614  /* CLK_M4_USART3 status register */
+#define LPC43_CCU1_M4_TIMER2_CFG_OFFSET     0x0618  /* CLK_M4_TIMER2 configuration register */
+#define LPC43_CCU1_M4_TIMER2_STAT_OFFSET    0x061c  /* CLK_M4_TIMER2 status register */
+#define LPC43_CCU1_M4_TIMER3_CFG_OFFSET     0x0620  /* CLK_M4_TIMER3 configuration register */
+#define LPC43_CCU1_M4_TIMER3_STAT_OFFSET    0x0624  /* CLK_M4_TIMER3 status register */
+#define LPC43_CCU1_M4_SSP1_CFG_OFFSET       0x0628  /* CLK_M4_SSP1 configuration register */
+#define LPC43_CCU1_M4_SSP1_STAT_OFFSET      0x062c  /* CLK_M4_SSP1 status register */
+#define LPC43_CCU1_M4_QEI_CFG_OFFSET        0x0630  /* CLK_M4_QEI configuration register */
+#define LPC43_CCU1_M4_QEI_STAT_OFFSET       0x0634  /* CLK_M4_QEI status register */
+#define LPC43_CCU1_PERIPH_BUS_CFG_OFFSET    0x0700  /* CLK_PERIPH_BUS configuration register */
+#define LPC43_CCU1_PERIPH_BUS_STAT_OFFSET   0x0704  /* CLK_PERIPH_BUS status register */
+#define LPC43_CCU1_PERIPH_CORE_CFG_OFFSET   0x0710  /* CLK_PERIPH_CORE configuration register */
+#define LPC43_CCU1_PERIPH_CORE_STAT_OFFSET  0x0714  /* CLK_PERIPH_CORE status register */
+#define LPC43_CCU1_PERIPH_SGPIO_CFG_OFFSET  0x0718  /* CLK_PERIPH_SGPIO configuration register */
+#define LPC43_CCU1_PERIPH_SGPIO_STAT_OFFSET 0x071c  /* CLK_PERIPH_SGPIO status register */
+#define LPC43_CCU1_USB0_CFG_OFFSET          0x0800  /* CLK_USB0 configuration register */
+#define LPC43_CCU1_USB0_STAT_OFFSET         0x0804  /* CLK_USB0 status register */
+#define LPC43_CCU1_USB1_CFG_OFFSET          0x0900  /* CLK_USB1 configuration register */
+#define LPC43_CCU1_USB1_STAT_OFFSET         0x0904  /* CLK_USB1 status register */
+#define LPC43_CCU1_SPI_CFG_OFFSET           0x0a00  /* CLK_SPI configuration register */
+#define LPC43_CCU1_SPI_STAT_OFFSET          0x0a04  /* CLK_SPI status register */
+#define LPC43_CCU1_VADC_CFG_OFFSET          0x0b00  /* CLK_VADC configuration register */
+#define LPC43_CCU1_VADC_STAT_OFFSET         0x0b04  /* CLK_VADC status register */
+
+#define LPC43_CCU2_PM_OFFSET                0x0000 /* CCU2 power mode register */
+#define LPC43_CCU2_BASE_STAT_OFFSET         0x0004 /* CCU2 base clocks status register */
+#define LPC43_CCU2_APLL_CFG_OFFSET          0x0100  /* CLK_APLL configuration register */
+#define LPC43_CCU2_APLL_STAT_OFFSET         0x0104  /* CLK_APLL status register */
+#define LPC43_CCU2_APB2_USART3_CFG_OFFSET   0x0200  /* CLK_APB2_USART3 configuration register */
+#define LPC43_CCU2_APB2_USART3_STAT_OFFSET  0x0204  /* CLK_APB2_USART3 status register */
+#define LPC43_CCU2_APB2_USART2_CFG_OFFSET   0x0300  /* CLK_APB2_USART2 configuration register */
+#define LPC43_CCU2_APB2_USART2_STAT_OFFSET  0x0304  /* CLK_APB2_USART2 status register */
+#define LPC43_CCU2_APB0_UART1_CFG_OFFSET    0x0400  /* CLK_APB0_UART1 configuration register */
+#define LPC43_CCU2_APB0_UART1_STAT_OFFSET   0x0404  /* CLK_APB0_UART1 status register */
+#define LPC43_CCU2_APB0_USART0_CFG_OFFSET   0x0500  /* CLK_APB0_USART0 configuration register */
+#define LPC43_CCU2_APB0_USART0_STAT_OFFSET  0x0504  /* CLK_APB0_USART0 status register */
+#define LPC43_CCU2_APB2_SSP1_CFG_OFFSET     0x0600  /* CLK_APB2_SSP1 configuration register */
+#define LPC43_CCU2_APB2_SSP1_STAT_OFFSET    0x0604  /* CLK_APB2_SSP1 status register */
+#define LPC43_CCU2_APB0_SSP0_CFG_OFFSET     0x0700  /* CLK_APB0_SSP0 configuration register */
+#define LPC43_CCU2_APB0_SSP0_STAT_OFFSET    0x0704  /* CLK_APB0_SSP0 status register */
+#define LPC43_CCU2_SDIO_CFG_OFFSET          0x0800  /* CLK_SDIO configuration register (for SD/MMC) */
+#define LPC43_CCU2_SDIO_STAT_OFFSET         0x0804  /* CLK_SDIO status register (for SD/MMC) */
+
+/* Register Addresses *******************************************************************************/
+
+#define LPC43_CCU1_PM                       (LPC43_CCU1_BASE+LPC43_CCU1_PM_OFFSET)
+#define LPC43_CCU1_BASE_STAT                (LPC43_CCU1_BASE+LPC43_CCU1_BASE_STAT_OFFSET)
+#define LPC43_CCU1_APB3_BUS_CFG             (LPC43_CCU1_BASE+LPC43_CCU1_APB3_BUS_CFG_OFFSET)
+#define LPC43_CCU1_APB3_BUS_STAT            (LPC43_CCU1_BASE+LPC43_CCU1_APB3_BUS_STAT_OFFSET)
+#define LPC43_CCU1_APB3_I2C1_CFG            (LPC43_CCU1_BASE+LPC43_CCU1_APB3_I2C1_CFG_OFFSET)
+#define LPC43_CCU1_APB3_I2C1_STAT           (LPC43_CCU1_BASE+LPC43_CCU1_APB3_I2C1_STAT_OFFSET)
+#define LPC43_CCU1_APB3_DAC_CFG             (LPC43_CCU1_BASE+LPC43_CCU1_APB3_DAC_CFG_OFFSET)
+#define LPC43_CCU1_APB3_DAC_STAT            (LPC43_CCU1_BASE+LPC43_CCU1_APB3_DAC_STAT_OFFSET)
+#define LPC43_CCU1_APB3_ADC0_CFG            (LPC43_CCU1_BASE+LPC43_CCU1_APB3_ADC0_CFG_OFFSET)
+#define LPC43_CCU1_APB3_ADC0_STAT           (LPC43_CCU1_BASE+LPC43_CCU1_APB3_ADC0_STAT_OFFSET)
+#define LPC43_CCU1_APB3_ADC1_CFG            (LPC43_CCU1_BASE+LPC43_CCU1_APB3_ADC1_CFG_OFFSET)
+#define LPC43_CCU1_APB3_ADC1_STAT           (LPC43_CCU1_BASE+LPC43_CCU1_APB3_ADC1_STAT_OFFSET)
+#define LPC43_CCU1_APB3_CAN0_CFG            (LPC43_CCU1_BASE+LPC43_CCU1_APB3_CAN0_CFG_OFFSET)
+#define LPC43_CCU1_APB3_CAN0_STAT           (LPC43_CCU1_BASE+LPC43_CCU1_APB3_CAN0_STAT_OFFSET)
+#define LPC43_CCU1_APB1_BUS_CFG             (LPC43_CCU1_BASE+LPC43_CCU1_APB1_BUS_CFG_OFFSET)
+#define LPC43_CCU1_APB1_BUS_STAT            (LPC43_CCU1_BASE+LPC43_CCU1_APB1_BUS_STAT_OFFSET)
+#define LPC43_CCU1_APB1_MCPWM_CFG           (LPC43_CCU1_BASE+LPC43_CCU1_APB1_MCPWM_CFG_OFFSET)
+#define LPC43_CCU1_APB1_MCPWM_STAT          (LPC43_CCU1_BASE+LPC43_CCU1_APB1_MCPWM_STAT_OFFSET)
+#define LPC43_CCU1_APB1_I2C0_CFG            (LPC43_CCU1_BASE+LPC43_CCU1_APB1_I2C0_CFG_OFFSET)
+#define LPC43_CCU1_APB1_I2C0_STAT           (LPC43_CCU1_BASE+LPC43_CCU1_APB1_I2C0_STAT_OFFSET)
+#define LPC43_CCU1_APB1_I2S_CFG             (LPC43_CCU1_BASE+LPC43_CCU1_APB1_I2S_CFG_OFFSET)
+#define LPC43_CCU1_APB1_I2S_STAT            (LPC43_CCU1_BASE+LPC43_CCU1_APB1_I2S_STAT_OFFSET)
+#define LPC43_CCU1_APB1_CAN1_CFG            (LPC43_CCU1_BASE+LPC43_CCU1_APB1_CAN1_CFG_OFFSET)
+#define LPC43_CCU1_APB1_CAN1_STAT           (LPC43_CCU1_BASE+LPC43_CCU1_APB1_CAN1_STAT_OFFSET)
+#define LPC43_CCU1_SPIFI_CFG                (LPC43_CCU1_BASE+LPC43_CCU1_SPIFI_CFG_OFFSET)
+#define LPC43_CCU1_SPIFI_STAT               (LPC43_CCU1_BASE+LPC43_CCU1_SPIFI_STAT_OFFSET)
+#define LPC43_CCU1_M4_BUS_CFG               (LPC43_CCU1_BASE+LPC43_CCU1_M4_BUS_CFG_OFFSET)
+#define LPC43_CCU1_M4_BUS_STAT              (LPC43_CCU1_BASE+LPC43_CCU1_M4_BUS_STAT_OFFSET)
+#define LPC43_CCU1_M4_SPIFI_CFG             (LPC43_CCU1_BASE+LPC43_CCU1_M4_SPIFI_CFG_OFFSET)
+#define LPC43_CCU1_M4_SPIFI_STAT            (LPC43_CCU1_BASE+LPC43_CCU1_M4_SPIFI_STAT_OFFSET)
+#define LPC43_CCU1_M4_GPIO_CFG              (LPC43_CCU1_BASE+LPC43_CCU1_M4_GPIO_CFG_OFFSET)
+#define LPC43_CCU1_M4_GPIO_STAT             (LPC43_CCU1_BASE+LPC43_CCU1_M4_GPIO_STAT_OFFSET)
+#define LPC43_CCU1_M4_LCD_CFG               (LPC43_CCU1_BASE+LPC43_CCU1_M4_LCD_CFG_OFFSET)
+#define LPC43_CCU1_M4_LCD_STAT              (LPC43_CCU1_BASE+LPC43_CCU1_M4_LCD_STAT_OFFSET)
+#define LPC43_CCU1_M4_ETHERNET_CFG          (LPC43_CCU1_BASE+LPC43_CCU1_M4_ETHERNET_CFG_OFFSET)
+#define LPC43_CCU1_M4_ETHERNET_STAT         (LPC43_CCU1_BASE+LPC43_CCU1_M4_ETHERNET_STAT_OFFSET)
+#define LPC43_CCU1_M4_USB0_CFG              (LPC43_CCU1_BASE+LPC43_CCU1_M4_USB0_CFG_OFFSET)
+#define LPC43_CCU1_M4_USB0_STAT             (LPC43_CCU1_BASE+LPC43_CCU1_M4_USB0_STAT_OFFSET)
+#define LPC43_CCU1_M4_EMC_CFG               (LPC43_CCU1_BASE+LPC43_CCU1_M4_EMC_CFG_OFFSET)
+#define LPC43_CCU1_M4_EMC_STAT              (LPC43_CCU1_BASE+LPC43_CCU1_M4_EMC_STAT_OFFSET)
+#define LPC43_CCU1_M4_SDIO_CFG              (LPC43_CCU1_BASE+LPC43_CCU1_M4_SDIO_CFG_OFFSET)
+#define LPC43_CCU1_M4_SDIO_STAT             (LPC43_CCU1_BASE+LPC43_CCU1_M4_SDIO_STAT_OFFSET)
+#define LPC43_CCU1_M4_DMA_CFG               (LPC43_CCU1_BASE+LPC43_CCU1_M4_DMA_CFG_OFFSET)
+#define LPC43_CCU1_M4_DMA_STAT              (LPC43_CCU1_BASE+LPC43_CCU1_M4_DMA_STAT_OFFSET)
+#define LPC43_CCU1_M4_M4CORE_CFG            (LPC43_CCU1_BASE+LPC43_CCU1_M4_M4CORE_CFG_OFFSET)
+#define LPC43_CCU1_M4_M4CORE_STAT           (LPC43_CCU1_BASE+LPC43_CCU1_M4_M4CORE_STAT_OFFSET)
+#define LPC43_CCU1_M4_SCT_CFG               (LPC43_CCU1_BASE+LPC43_CCU1_M4_SCT_CFG_OFFSET)
+#define LPC43_CCU1_M4_SCT_STAT              (LPC43_CCU1_BASE+LPC43_CCU1_M4_SCT_STAT_OFFSET)
+#define LPC43_CCU1_M4_USB1_CFG              (LPC43_CCU1_BASE+LPC43_CCU1_M4_USB1_CFG_OFFSET)
+#define LPC43_CCU1_M4_USB1_STAT             (LPC43_CCU1_BASE+LPC43_CCU1_M4_USB1_STAT_OFFSET)
+#define LPC43_CCU1_M4_EMCDIV_CFG            (LPC43_CCU1_BASE+LPC43_CCU1_M4_EMCDIV_CFG_OFFSET)
+#define LPC43_CCU1_M4_EMCDIV_STAT           (LPC43_CCU1_BASE+LPC43_CCU1_M4_EMCDIV_STAT_OFFSET)
+#define LPC43_CCU1_M4_FLASHA_CFG            (LPC43_CCU1_BASE+LPC43_CCU1_M4_FLASHA_CFG_OFFSET)
+#define LPC43_CCU1_M4_FLASHA_STAT           (LPC43_CCU1_BASE+LPC43_CCU1_M4_FLASHA_STAT_OFFSET)
+#define LPC43_CCU1_M4_FLASHB_CFG            (LPC43_CCU1_BASE+LPC43_CCU1_M4_FLASHB_CFG_OFFSET)
+#define LPC43_CCU1_M4_FLASHB_STAT           (LPC43_CCU1_BASE+LPC43_CCU1_M4_FLASHB_STAT_OFFSET)
+#define LPC43_CCU1_M4_M0APP_CFG             (LPC43_CCU1_BASE+LPC43_CCU1_M4_M0APP_CFG_OFFSET)
+#define LPC43_CCU1_M4_M0APP_STAT            (LPC43_CCU1_BASE+LPC43_CCU1_M4_M0APP_STAT_OFFSET)
+#define LPC43_CCU1_M4_VADC_CFG              (LPC43_CCU1_BASE+LPC43_CCU1_M4_VADC_CFG_OFFSET)
+#define LPC43_CCU1_M4_VADC_STAT             (LPC43_CCU1_BASE+LPC43_CCU1_M4_VADC_STAT_OFFSET)
+#define LPC43_CCU1_M4_EEPROM_CFG            (LPC43_CCU1_BASE+LPC43_CCU1_M4_EEPROM_CFG_OFFSET)
+#define LPC43_CCU1_M4_EEPROM_STAT           (LPC43_CCU1_BASE+LPC43_CCU1_M4_EEPROM_STAT_OFFSET)
+#define LPC43_CCU1_M4_WWDT_CFG              (LPC43_CCU1_BASE+LPC43_CCU1_M4_WWDT_CFG_OFFSET)
+#define LPC43_CCU1_M4_WWDT_STAT             (LPC43_CCU1_BASE+LPC43_CCU1_M4_WWDT_STAT_OFFSET)
+#define LPC43_CCU1_M4_USART0_CFG            (LPC43_CCU1_BASE+LPC43_CCU1_M4_USART0_CFG_OFFSET)
+#define LPC43_CCU1_M4_USART0_STAT           (LPC43_CCU1_BASE+LPC43_CCU1_M4_USART0_STAT_OFFSET)
+#define LPC43_CCU1_M4_UART1_CFG             (LPC43_CCU1_BASE+LPC43_CCU1_M4_UART1_CFG_OFFSET)
+#define LPC43_CCU1_M4_UART1_STAT            (LPC43_CCU1_BASE+LPC43_CCU1_M4_UART1_STAT_OFFSET)
+#define LPC43_CCU1_M4_SSP0_CFG              (LPC43_CCU1_BASE+LPC43_CCU1_M4_SSP0_CFG_OFFSET)
+#define LPC43_CCU1_M4_SSP0_STAT             (LPC43_CCU1_BASE+LPC43_CCU1_M4_SSP0_STAT_OFFSET)
+#define LPC43_CCU1_M4_TIMER0_CFG            (LPC43_CCU1_BASE+LPC43_CCU1_M4_TIMER0_CFG_OFFSET)
+#define LPC43_CCU1_M4_TIMER0_STAT           (LPC43_CCU1_BASE+LPC43_CCU1_M4_TIMER0_STAT_OFFSET)
+#define LPC43_CCU1_M4_TIMER1_CFG            (LPC43_CCU1_BASE+LPC43_CCU1_M4_TIMER1_CFG_OFFSET)
+#define LPC43_CCU1_M4_TIMER1_STAT           (LPC43_CCU1_BASE+LPC43_CCU1_M4_TIMER1_STAT_OFFSET)
+#define LPC43_CCU1_M4_SCU_CFG               (LPC43_CCU1_BASE+LPC43_CCU1_M4_SCU_CFG_OFFSET)
+#define LPC43_CCU1_M4_SCU_STAT              (LPC43_CCU1_BASE+LPC43_CCU1_M4_SCU_STAT_OFFSET)
+#define LPC43_CCU1_M4_CREG_CFG              (LPC43_CCU1_BASE+LPC43_CCU1_M4_CREG_CFG_OFFSET)
+#define LPC43_CCU1_M4_CREG_STAT             (LPC43_CCU1_BASE+LPC43_CCU1_M4_CREG_STAT_OFFSET)
+#define LPC43_CCU1_M4_RITIMER_CFG           (LPC43_CCU1_BASE+LPC43_CCU1_M4_RITIMER_CFG_OFFSET)
+#define LPC43_CCU1_M4_RITIMER_STAT          (LPC43_CCU1_BASE+LPC43_CCU1_M4_RITIMER_STAT_OFFSET)
+#define LPC43_CCU1_M4_USART2_CFG            (LPC43_CCU1_BASE+LPC43_CCU1_M4_USART2_CFG_OFFSET)
+#define LPC43_CCU1_M4_USART2_STAT           (LPC43_CCU1_BASE+LPC43_CCU1_M4_USART2_STAT_OFFSET)
+#define LPC43_CCU1_M4_USART3_CFG            (LPC43_CCU1_BASE+LPC43_CCU1_M4_USART3_CFG_OFFSET)
+#define LPC43_CCU1_M4_USART3_STAT           (LPC43_CCU1_BASE+LPC43_CCU1_M4_USART3_STAT_OFFSET)
+#define LPC43_CCU1_M4_TIMER2_CFG            (LPC43_CCU1_BASE+LPC43_CCU1_M4_TIMER2_CFG_OFFSET)
+#define LPC43_CCU1_M4_TIMER2_STAT           (LPC43_CCU1_BASE+LPC43_CCU1_M4_TIMER2_STAT_OFFSET)
+#define LPC43_CCU1_M4_TIMER3_CFG            (LPC43_CCU1_BASE+LPC43_CCU1_M4_TIMER3_CFG_OFFSET)
+#define LPC43_CCU1_M4_TIMER3_STAT           (LPC43_CCU1_BASE+LPC43_CCU1_M4_TIMER3_STAT_OFFSET)
+#define LPC43_CCU1_M4_SSP1_CFG              (LPC43_CCU1_BASE+LPC43_CCU1_M4_SSP1_CFG_OFFSET)
+#define LPC43_CCU1_M4_SSP1_STAT             (LPC43_CCU1_BASE+LPC43_CCU1_M4_SSP1_STAT_OFFSET)
+#define LPC43_CCU1_M4_QEI_CFG               (LPC43_CCU1_BASE+LPC43_CCU1_M4_QEI_CFG_OFFSET)
+#define LPC43_CCU1_M4_QEI_STAT              (LPC43_CCU1_BASE+LPC43_CCU1_M4_QEI_STAT_OFFSET)
+#define LPC43_CCU1_PERIPH_BUS_CFG           (LPC43_CCU1_BASE+LPC43_CCU1_PERIPH_BUS_CFG_OFFSET)
+#define LPC43_CCU1_PERIPH_BUS_STAT          (LPC43_CCU1_BASE+LPC43_CCU1_PERIPH_BUS_STAT_OFFSET)
+#define LPC43_CCU1_PERIPH_CORE_CFG          (LPC43_CCU1_BASE+LPC43_CCU1_PERIPH_CORE_CFG_OFFSET)
+#define LPC43_CCU1_PERIPH_CORE_STAT         (LPC43_CCU1_BASE+LPC43_CCU1_PERIPH_CORE_STAT_OFFSET)
+#define LPC43_CCU1_PERIPH_SGPIO_CFG         (LPC43_CCU1_BASE+LPC43_CCU1_PERIPH_SGPIO_CFG_OFFSET)
+#define LPC43_CCU1_PERIPH_SGPIO_STAT        (LPC43_CCU1_BASE+LPC43_CCU1_PERIPH_SGPIO_STAT_OFFSET)
+#define LPC43_CCU1_USB0_CFG                 (LPC43_CCU1_BASE+LPC43_CCU1_USB0_CFG_OFFSET)
+#define LPC43_CCU1_USB0_STAT                (LPC43_CCU1_BASE+LPC43_CCU1_USB0_STAT_OFFSET)
+#define LPC43_CCU1_USB1_CFG                 (LPC43_CCU1_BASE+LPC43_CCU1_USB1_CFG_OFFSET)
+#define LPC43_CCU1_USB1_STAT                (LPC43_CCU1_BASE+LPC43_CCU1_USB1_STAT_OFFSET)
+#define LPC43_CCU1_SPI_CFG                  (LPC43_CCU1_BASE+LPC43_CCU1_SPI_CFG_OFFSET)
+#define LPC43_CCU1_SPI_STAT                 (LPC43_CCU1_BASE+LPC43_CCU1_SPI_STAT_OFFSET)
+#define LPC43_CCU1_VADC_CFG                 (LPC43_CCU1_BASE+LPC43_CCU1_VADC_CFG_OFFSET)
+#define LPC43_CCU1_VADC_STAT                (LPC43_CCU1_BASE+LPC43_CCU1_VADC_STAT_OFFSET)
+
+#define LPC43_CCU2_PM                       (LPC43_CCU2_BASE+LPC43_CCU2_PM_OFFSET)
+#define LPC43_CCU2_BASE_STAT                (LPC43_CCU2_BASE+LPC43_CCU2_BASE_STAT_OFFSET)
+#define LPC43_CCU2_APLL_CFG                 (LPC43_CCU2_BASE+LPC43_CCU2_APLL_CFG_OFFSET)
+#define LPC43_CCU2_APLL_STAT                (LPC43_CCU2_BASE+LPC43_CCU2_APLL_STAT_OFFSET)
+#define LPC43_CCU2_APB2_USART3_CFG          (LPC43_CCU2_BASE+LPC43_CCU2_APB2_USART3_CFG_OFFSET)
+#define LPC43_CCU2_APB2_USART3_STAT         (LPC43_CCU2_BASE+LPC43_CCU2_APB2_USART3_STAT_OFFSET)
+#define LPC43_CCU2_APB2_USART2_CFG          (LPC43_CCU2_BASE+LPC43_CCU2_APB2_USART2_CFG_OFFSET)
+#define LPC43_CCU2_APB2_USART2_STAT         (LPC43_CCU2_BASE+LPC43_CCU2_APB2_USART2_STAT_OFFSET)
+#define LPC43_CCU2_APB0_UART1_CFG           (LPC43_CCU2_BASE+LPC43_CCU2_APB0_UART1_CFG_OFFSET)
+#define LPC43_CCU2_APB0_UART1_STAT          (LPC43_CCU2_BASE+LPC43_CCU2_APB0_UART1_STAT_OFFSET)
+#define LPC43_CCU2_APB0_USART0_CFG          (LPC43_CCU2_BASE+LPC43_CCU2_APB0_USART0_CFG_OFFSET)
+#define LPC43_CCU2_APB0_USART0_STAT         (LPC43_CCU2_BASE+LPC43_CCU2_APB0_USART0_STAT_OFFSET)
+#define LPC43_CCU2_APB2_SSP1_CFG            (LPC43_CCU2_BASE+LPC43_CCU2_APB2_SSP1_CFG_OFFSET)
+#define LPC43_CCU2_APB2_SSP1_STAT           (LPC43_CCU2_BASE+LPC43_CCU2_APB2_SSP1_STAT_OFFSET)
+#define LPC43_CCU2_APB0_SSP0_CFG            (LPC43_CCU2_BASE+LPC43_CCU2_APB0_SSP0_CFG_OFFSET)
+#define LPC43_CCU2_APB0_SSP0_STAT           (LPC43_CCU2_BASE+LPC43_CCU2_APB0_SSP0_STAT_OFFSET)
+#define LPC43_CCU2_SDIO_CFG                 (LPC43_CCU2_BASE+LPC43_CCU2_SDIO_CFG_OFFSET)
+#define LPC43_CCU2_SDIO_STAT                (LPC43_CCU2_BASE+LPC43_CCU2_SDIO_STAT_OFFSET)
+
+/* Register Bit Definitions *************************************************************************/
+
+/* CCU1/2 Power Mode Register */
+
+#define CCU_PM_PD                           (1 << 0)  /* Bit 0: Initiate power-down mode */
+                                                      /* Bits 1-31:  Reserved */
+/* CCU1 Base Clock Status Register */
+
+#define CCU1_BASE_STAT_AB3                  (1 << 0)  /* Bit 0:  Base clock indicator for BASE_APB3_CLK */
+#define CCU1_BASE_STAT_APB1                 (1 << 1)  /* Bit 1:  Base clock indicator for BASE_APB1_CLK */
+#define CCU1_BASE_STAT_SPIFI                (1 << 2)  /* Bit 2:  Base clock indicator for BASE_SPIFI_CLK */
+#define CCU1_BASE_STAT_M4                   (1 << 3)  /* Bit 3:  Base clock indicator for BASE_M4_CLK */
+                                                      /* Bits 4-5:  Reserved */
+#define CCU1_BASE_STAT_PERIPH               (1 << 6)  /* Bit 6:  Base clock indicator for BASE_PERIPH_CLK */
+#define CCU1_BASE_STAT_USB0                 (1 << 7)  /* Bit 7:  Base clock indicator for BASE_USB0_CLK */
+#define CCU1_BASE_STAT_USB1                 (1 << 8)  /* Bit 8:  Base clock indicator for BASE_USB1_CLK */
+#define CCU1_BASE_STAT_SPI                  (1 << 9)  /* Bit 9:  Base clock indicator for BASE_SPI_CLK */
+                                                      /* Bits 10-31:  Reserved */
+/* CCU2 Base Clock Status Register */
+                                                      /* Bit 0:  Reserved */
+#define CCU2_BASE_STAT_USART3               (1 << 1)  /* Bit 1:  Base clock indicator for BASE_USART3_CLK */
+#define CCU2_BASE_STAT_USART2               (1 << 2)  /* Bit 2:  Base clock indicator for BASE_USART2_CLK */
+#define CCU2_BASE_STAT_UART1                (1 << 3)  /* Bit 3:  Base clock indicator for BASE_UART1_CLK */
+#define CCU2_BASE_STAT_USART0               (1 << 4)  /* Bit 4:  Base clock indicator for BASE_USART0_CLK */
+#define CCU2_BASE_STAT_SSP1                 (1 << 5)  /* Bit 5:  Base clock indicator for BASE_SSP1_CLK */
+#define CCU2_BASE_STAT_SSP0                 (1 << 6)  /* Bit 6:  Base clock indicator for BASE_SSP0_CLK */
+                                                      /* Bits 7-31:  Reserved */
+/* CCU1/2 Branch Clock Configuration/Status Registers */
+
+#define CCU_CLK_CFG_RUN                     (1 << 0)  /* Bit 0:  Run enable */
+#define CCU_CLK_CFG_AUTO                    (1 << 1)  /* Bit 1:  Auto (AHB disable mechanism) enable */
+#define CCU_CLK_CFG_WAKEUP                  (1 << 2)  /* Bit 2:  Wake-up mechanism enable */
+                                                      /* Bits 3-31:  Reserved */
+/* CCU1/2 Branch Clock Status Registers */
+
+#define CCU_CLK_STAT_RUN                    (1 << 0)  /* Bit 0:  Run enable status */
+#define CCU_CLK_STAT_AUTO                   (1 << 1)  /* Bit 1:  Auto (AHB disable mechanism) enable status */
+#define CCU_CLK_STAT_WAKEUP                 (1 << 2)  /* Bit 2:  Wake-up mechanism enable status */
+                                                      /* Bits 3-31:  Reserved */
+
+/****************************************************************************************************
+ * Public Types
+ ****************************************************************************************************/
+
+/****************************************************************************************************
+ * Public Data
+ ****************************************************************************************************/
+
+/****************************************************************************************************
+ * Public Functions
+ ****************************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_CCU_H */
diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_cgu.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_cgu.h
new file mode 100644
index 000000000..61fa3be0b
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_cgu.h
@@ -0,0 +1,866 @@
+/****************************************************************************************************
+ * arch/arm/src/lpc43xx/chip/lpc43_cgu.h
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_CGU_H
+#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_CGU_H
+
+/****************************************************************************************************
+ * Included Files
+ ****************************************************************************************************/
+
+#include <nuttx/config.h>
+
+/****************************************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************************************/
+/* Register Offsets *********************************************************************************/
+
+#define LPC43_FREQ_MON_OFFSET           0x0014  /* Frequency monitor register */
+#define LPC43_XTAL_OSC_CTRL_OFFSET      0x0018  /* Crystal oscillator control register */
+#define LPC43_PLL0USB_STAT_OFFSET       0x001c  /* PLL0USB status register */
+#define LPC43_PLL0USB_CTRL_OFFSET       0x0020  /* PLL0USB control register */
+#define LPC43_PLL0USB_MDIV_OFFSET       0x0024  /* PLL0USB M-divider register */
+#define LPC43_PLL0USB_NP_DIV_OFFSET     0x0028  /* PLL0USB N/P-divider register */
+#define LPC43_PLL0AUDIO_STAT_OFFSET     0x002c  /* PLL0AUDIO status register */
+#define LPC43_PLL0AUDIO_CTRL_OFFSET     0x0030  /* PLL0AUDIO control register */
+#define LPC43_PLL0AUDIO_MDIV_OFFSET     0x0034  /* PLL0AUDIO M-divider */
+#define LPC43_PLL0AUDIO_NP_DIV_OFFSET   0x0038  /* PLL0AUDIO N/P-divider */
+#define LPC43_PLL0AUDIO_FRAC_OFFSET     0x003c  /* PLL0AUDIO fractional */
+#define LPC43_PLL1_STAT_OFFSET          0x0040  /* PLL1 status register */
+#define LPC43_PLL1_CTRL_OFFSET          0x0044  /* PLL1 control register */
+#define LPC43_IDIVA_CTRL_OFFSET         0x0048  /* Integer divider A control register */
+#define LPC43_IDIVB_CTRL_OFFSET         0x004c  /* Integer divider B control register */
+#define LPC43_IDIVC_CTRL_OFFSET         0x0050  /* Integer divider C control register */
+#define LPC43_IDIVD_CTRL_OFFSET         0x0054  /* Integer divider D control register */
+#define LPC43_IDIVE_CTRL_OFFSET         0x0058  /* Integer divider E control register */
+#define LPC43_BASE_SAFE_CLK_OFFSET      0x005c  /* Output stage 0 control register (BASE_SAFE_CLK) */
+#define LPC43_BASE_USB0_CLK_OFFSET      0x0060  /* Output stage 1 control register (BASE_USB0_CLK) */
+#define LPC43_BASE_PERIPH_CLK_OFFSET    0x0064  /* Output stage 2 control register (BASE_PERIPH_CLK) */
+#define LPC43_BASE_USB1_CLK_OFFSET      0x0068  /* Output stage 3 control register (BASE_USB1_CLK) */
+#define LPC43_BASE_M4_CLK_OFFSET        0x006c  /* Output stage 4 control register (BASE_M4_CLK) */
+#define LPC43_BASE_SPIFI_CLK_OFFSET     0x0070  /* Output stage 5 control register (BASE_SPIFI_CLK) */
+#define LPC43_BASE_SPI_CLK_OFFSET       0x0074  /* Output stage 6 control register (BASE_SPI_CLK) */
+#define LPC43_BASE_PHYRX_CLK_OFFSET     0x0078  /* Output stage 7 control register (BASE_PHY_RX_CLK) */
+#define LPC43_BASE_PHYTX_CLK_OFFSET     0x007c  /* Output stage 8 control register (BASE_PHY_TX_CLK) */
+#define LPC43_BASE_APB1_CLK_OFFSET      0x0080  /* Output stage 9 control register (BASE_APB1_CLK) */
+#define LPC43_BASE_APB3_CLK_OFFSET      0x0084  /* Output stage 10 control register (BASE_APB3_CLK) */
+#define LPC43_BASE_LCD_CLK_OFFSET       0x0088  /* Output stage 11 control register (BASE_LCD_CLK) */
+#define LPC43_BASE_VADC_CLK_OFFSET      0x008c  /* Output stage 12 control register (BASE_VADC_CLK) */
+#define LPC43_BASE_SDIO_CLK_OFFSET      0x0090  /* Output stage 13 control register (BASE_SDIO_CLK) */
+#define LPC43_BASE_SSP0_CLK_OFFSET      0x0094  /* Output stage 14 control register (BASE_SSP0_CLK) */
+#define LPC43_BASE_SSP1_CLK_OFFSET      0x0098  /* Output stage 15 control register (BASE_SSP1_CLK) */
+#define LPC43_BASE_USART0_CLK_OFFSET    0x009c  /* Output stage 16 control register (BASE_USART0_CLK) */
+#define LPC43_BASE_UART1_CLK_OFFSET     0x00a0  /* Output stage 17 control register (BASE_UART1_CLK) */
+#define LPC43_BASE_USART2_CLK_OFFSET    0x00a4  /* Output stage 18 control register (BASE_USART2_CLK) */
+#define LPC43_BASE_USART3_CLK_OFFSET    0x00a8  /* Output stage 19 control register (BASE_USART3_CLK) */
+#define LPC43_BASE_OUT_CLK_OFFSET       0x00ac  /* Output stage 20 control register (BASE_OUT_CLK) */
+#define LPC43_BASE_APLL_CLK_OFFSET      0x00c0  /* Output stage 25 control register (BASE_APLL_CLK) */
+#define LPC43_BASE_CGU_OUT0_CLK_OFFSET  0x00c4  /* Output stage 26 control register (BASE_CGU_OUT0_CLK) */
+#define LPC43_BASE_CGU_OUT1_CLK_OFFSET  0x00c8  /* Output stage 27 control register (BASE_CGU_OUT1_CLK) */
+
+/* Register Addresses *******************************************************************************/
+
+#define LPC43_FREQ_MON                  (LPC43_CGU_BASE+LPC43_FREQ_MON_OFFSET)
+#define LPC43_XTAL_OSC_CTRL             (LPC43_CGU_BASE+LPC43_XTAL_OSC_CTRL_OFFSET)
+#define LPC43_PLL0USB_STAT              (LPC43_CGU_BASE+LPC43_PLL0USB_STAT_OFFSET)
+#define LPC43_PLL0USB_CTRL              (LPC43_CGU_BASE+LPC43_PLL0USB_CTRL_OFFSET)
+#define LPC43_PLL0USB_MDIV              (LPC43_CGU_BASE+LPC43_PLL0USB_MDIV_OFFSET)
+#define LPC43_PLL0USB_NP_DIV            (LPC43_CGU_BASE+LPC43_PLL0USB_NP_DIV_OFFSET)
+#define LPC43_PLL0AUDIO_STAT            (LPC43_CGU_BASE+LPC43_PLL0AUDIO_STAT_OFFSET)
+#define LPC43_PLL0AUDIO_CTRL            (LPC43_CGU_BASE+LPC43_PLL0AUDIO_CTRL_OFFSET)
+#define LPC43_PLL0AUDIO_MDIV            (LPC43_CGU_BASE+LPC43_PLL0AUDIO_MDIV_OFFSET)
+#define LPC43_PLL0AUDIO_NP_DIV          (LPC43_CGU_BASE+LPC43_PLL0AUDIO_NP_DIV_OFFSET)
+#define LPC43_PLL0AUDIO_FRAC            (LPC43_CGU_BASE+LPC43_PLL0AUDIO_FRAC_OFFSET)
+#define LPC43_PLL1_STAT                 (LPC43_CGU_BASE+LPC43_PLL1_STAT_OFFSET)
+#define LPC43_PLL1_CTRL                 (LPC43_CGU_BASE+LPC43_PLL1_CTRL_OFFSET)
+#define LPC43_IDIVA_CTRL                (LPC43_CGU_BASE+LPC43_IDIVA_CTRL_OFFSET)
+#define LPC43_IDIVB_CTRL                (LPC43_CGU_BASE+LPC43_IDIVB_CTRL_OFFSET)
+#define LPC43_IDIVC_CTRL                (LPC43_CGU_BASE+LPC43_IDIVC_CTRL_OFFSET)
+#define LPC43_IDIVD_CTRL                (LPC43_CGU_BASE+LPC43_IDIVD_CTRL_OFFSET)
+#define LPC43_IDIVE_CTRL                (LPC43_CGU_BASE+LPC43_IDIVE_CTRL_OFFSET)
+#define LPC43_BASE_SAFE_CLK             (LPC43_CGU_BASE+LPC43_BASE_SAFE_CLK_OFFSET)
+#define LPC43_BASE_USB0_CLK             (LPC43_CGU_BASE+LPC43_BASE_USB0_CLK_OFFSET)
+#define LPC43_BASE_PERIPH_CLK           (LPC43_CGU_BASE+LPC43_BASE_PERIPH_CLK_OFFSET)
+#define LPC43_BASE_USB1_CLK             (LPC43_CGU_BASE+LPC43_BASE_USB1_CLK_OFFSET)
+#define LPC43_BASE_M4_CLK               (LPC43_CGU_BASE+LPC43_BASE_M4_CLK_OFFSET)
+#define LPC43_BASE_SPIFI_CLK            (LPC43_CGU_BASE+LPC43_BASE_SPIFI_CLK_OFFSET)
+#define LPC43_BASE_SPI_CLK              (LPC43_CGU_BASE+LPC43_BASE_SPI_CLK_OFFSET)
+#define LPC43_BASE_PHYRX_CLK            (LPC43_CGU_BASE+LPC43_BASE_PHYRX_CLK_OFFSET)
+#define LPC43_BASE_PHYTX_CLK            (LPC43_CGU_BASE+LPC43_BASE_PHYTX_CLK_OFFSET)
+#define LPC43_BASE_APB1_CLK             (LPC43_CGU_BASE+LPC43_BASE_APB1_CLK_OFFSET)
+#define LPC43_BASE_APB3_CLK             (LPC43_CGU_BASE+LPC43_BASE_APB3_CLK_OFFSET)
+#define LPC43_BASE_LCD_CLK              (LPC43_CGU_BASE+LPC43_BASE_LCD_CLK_OFFSET)
+#define LPC43_BASE_VADC_CLK             (LPC43_CGU_BASE+LPC43_BASE_VADC_CLK_OFFSET)
+#define LPC43_BASE_SDIO_CLK             (LPC43_CGU_BASE+LPC43_BASE_SDIO_CLK_OFFSET)
+#define LPC43_BASE_SSP0_CLK             (LPC43_CGU_BASE+LPC43_BASE_SSP0_CLK_OFFSET)
+#define LPC43_BASE_SSP1_CLK             (LPC43_CGU_BASE+LPC43_BASE_SSP1_CLK_OFFSET)
+#define LPC43_BASE_USART0_CLK           (LPC43_CGU_BASE+LPC43_BASE_USART0_CLK_OFFSET)
+#define LPC43_BASE_UART1_CLK            (LPC43_CGU_BASE+LPC43_BASE_UART1_CLK_OFFSET)
+#define LPC43_BASE_USART2_CLK           (LPC43_CGU_BASE+LPC43_BASE_USART2_CLK_OFFSET)
+#define LPC43_BASE_USART3_CLK           (LPC43_CGU_BASE+LPC43_BASE_USART3_CLK_OFFSET)
+#define LPC43_BASE_OUT_CLK              (LPC43_CGU_BASE+LPC43_BASE_OUT_CLK_OFFSET)
+#define LPC43_BASE_APLL_CLK             (LPC43_CGU_BASE+LPC43_BASE_APLL_CLK_OFFSET)
+#define LPC43_BASE_CGU_OUT0_CLK         (LPC43_CGU_BASE+LPC43_BASE_CGU_OUT0_CLK_OFFSET)
+#define LPC43_BASE_CGU_OUT1_CLK         (LPC43_CGU_BASE+LPC43_BASE_CGU_OUT1_CLK_OFFSET)
+
+/* Register Bit Definitions *************************************************************************/
+
+/* Frequency monitor register */
+
+#define FREQ_MON_RCNT_SHIFT             (0)       /* Bits 0-8: 9-bit reference clock-counter value */
+#define FREQ_MON_RCNT_MASK              (0x1ff << FREQ_MON_RCNT_SHIFT)
+#define FREQ_MON_FCNT_SHIFT             (9)       /* Bits 9-22: 14-bit selected clock-counter value */
+#define FREQ_MON_FCNT_MASK              (0x3fff << FREQ_MON_FCNT_SHIFT)
+#define FREQ_MON_MEAS                   (1 << 23) /* Bit 23: Measure frequency */
+#define FREQ_MON_CLKSEL_SHIFT           (24)      /* Bits 24-28: Clock-source selection */
+#define FREQ_MON_CLKSEL_MASK            (31 << FREQ_MON_CLKSEL_SHIFT)
+#  define FREQ_MON_CLKSEL_32KHZOSC      (0 << FREQ_MON_CLKSEL_SHIFT)  /* 32 kHz oscillator (default) */
+#  define FREQ_MON_CLKSEL_IRQ           (1 << FREQ_MON_CLKSEL_SHIFT)  /* IRC */
+#  define FREQ_MON_CLKSEL_ENET_RXCLK    (2 << FREQ_MON_CLKSEL_SHIFT)  /* ENET_RX_CLK */
+#  define FREQ_MON_CLKSEL_ENET_TXCLK    (3 << FREQ_MON_CLKSEL_SHIFT)  /* ENET_TX_CLK */
+#  define FREQ_MON_CLKSEL_GPCLKIN       (4 << FREQ_MON_CLKSEL_SHIFT)  /* GP_CLKIN */
+#  define FREQ_MON_CLKSEL_XTAL          (6 << FREQ_MON_CLKSEL_SHIFT)  /* Crystal oscillator */
+#  define FREQ_MON_CLKSEL_PLL0USB       (7 << FREQ_MON_CLKSEL_SHIFT)  /* PLL0USB */
+#  define FREQ_MON_CLKSEL_PLL0AUDIO     (8 << FREQ_MON_CLKSEL_SHIFT)  /* PLL0AUDIO */
+#  define FREQ_MON_CLKSEL_PLL1          (9 << FREQ_MON_CLKSEL_SHIFT)  /* PLL1 */
+#  define FREQ_MON_CLKSEL_IDIVA         (12 << FREQ_MON_CLKSEL_SHIFT) /* IDIVA */
+#  define FREQ_MON_CLKSEL_IDIVB         (13 << FREQ_MON_CLKSEL_SHIFT) /* IDIVB */
+#  define FREQ_MON_CLKSEL_IDIVC         (14 << FREQ_MON_CLKSEL_SHIFT) /* IDIVC */
+#  define FREQ_MON_CLKSEL_IDIVD         (15 << FREQ_MON_CLKSEL_SHIFT) /* IDIVD */
+#  define FREQ_MON_CLKSEL_IDIVE         (16 << FREQ_MON_CLKSEL_SHIFT) /* IDIVE */
+                                                 /* Bits 29-31:  Reserved */
+/* Crystal oscillator control register */
+
+#define XTAL_OSC_CTRL_ENABLE            (1 << 0)  /* Bit 0:  Oscillator-pad enable */
+#define XTAL_OSC_CTRL_BYPASS            (1 << 1)  /* Bit 1:  Configure crystal or external-clock input */
+#define XTAL_OSC_CTRL_HF                (1 << 2)  /* Bit 2:  Select frequency range */
+                                                  /* Bits 3-31: Reserved */
+/* PLL0USB status register */
+
+#define PLL0USB_STAT_LOCK               (1 << 0)  /* Bit 0:  PLL0 lock indicator */
+#define PLL0USB_STAT_FR                 (1 << 1)  /* Bit 1:  PLL0 free running indicator */
+                                                  /* Bits 2-31: Reserved */
+/* PLL0USB control register */
+
+#define PLL0USB_CTRL_PD                 (1 << 0)  /* Bit 0:  PLL0 power down */
+#define PLL0USB_CTRL_BYPASS             (1 << 1)  /* Bit 1:  Input clock bypass control */
+#define PLL0USB_CTRL_DIRECTI            (1 << 2)  /* Bit 2:  PLL0 direct input */
+#define PLL0USB_CTRL_DIRECTO            (1 << 3)  /* Bit 3:  PLL0 direct output */
+#define PLL0USB_CTRL_CLKEN              (1 << 4)  /* Bit 4:  PLL0 clock enable */
+                                                  /* Bit 5:  Reserved */
+#define PLL0USB_CTRL_FRM                (1 << 6)  /* Bit 6:  Free running mode */
+                                                  /* Bits 7-10: Reserved */
+#define PLL0USB_CTRL_AUTOBLOCK          (1 << 11) /* Bit 11: Block clock during frequency change */
+                                                  /* Bits 12-23: Reserved */
+#define PLL0USB_CTRL_CLKSEL_SHIFT       (24)      /* Bits 24-28: Clock source selection */
+#define PLL0USB_CTRL_CLKSEL_MASK        (31 << PLL0USB_CTRL_CLKSEL_SHIFT)
+#  define PLL0USB_CLKSEL_32KHZOSC       (0 << PLL0USB_CTRL_CLKSEL_SHIFT)  /* 32 kHz oscillator */
+#  define PLL0USB_CLKSEL_IRC            (1 << PLL0USB_CTRL_CLKSEL_SHIFT)  /* IRC (default) */
+#  define PLL0USB_CLKSEL_ENET_RXCLK     (2 << PLL0USB_CTRL_CLKSEL_SHIFT)  /* ENET_RX_CLK */
+#  define PLL0USB_CLKSEL_ENET_TXCLK     (3 << PLL0USB_CTRL_CLKSEL_SHIFT)  /* ENET_TX_CLK */
+#  define PLL0USB_CLKSEL_GPCLKIN        (4 << PLL0USB_CTRL_CLKSEL_SHIFT)  /* GP_CLKIN */
+#  define PLL0USB_CLKSEL_XTAL           (6 << PLL0USB_CTRL_CLKSEL_SHIFT)  /* Crystal oscillator */
+#  define PLL0USB_CLKSEL_PLL1           (9 << PLL0USB_CTRL_CLKSEL_SHIFT)  /* PLL1 */
+#  define PLL0USB_CLKSEL_IDIVA          (12 << PLL0USB_CTRL_CLKSEL_SHIFT) /* IDIVA */
+#  define PLL0USB_CLKSEL_IDIVB          (13 << PLL0USB_CTRL_CLKSEL_SHIFT) /* IDIVB */
+#  define PLL0USB_CLKSEL_IDIVC          (14 << PLL0USB_CTRL_CLKSEL_SHIFT) /* IDIVC */
+#  define PLL0USB_CLKSEL_IDIVD          (15 << PLL0USB_CTRL_CLKSEL_SHIFT) /* IDIVD */
+#  define PLL0USB_CLKSEL_IDIVE          (16 << PLL0USB_CTRL_CLKSEL_SHIFT) /* IDIVE */
+                                                 /* Bits 29-31:  Reserved */
+/* PLL0USB M-divider register */
+
+#define PLL0USB_MDIV_MDEC_SHIFT         (0)      /* Bits 0-16: Decoded M-divider coefficient value (1-131071) */
+#define PLL0USB_MDIV_MDEC_MASK          (0x1ffff << PLL0USB_MDIV_MDEC_SHIFT)
+#  define PLL0USB_MDIV_MDEC(n)          ((n) << PLL0USB_MDIV_MDEC_SHIFT)
+#define PLL0USB_MDIV_SELP_SHIFT         (17)     /* Bits 17-21: Bandwidth select P value */
+#define PLL0USB_MDIV_SELP_MASK          (0x1f << PLL0USB_MDIV_SELP_SHIFT)
+#  define PLL0USB_MDIV_SELP(n)          ((n) << PLL0USB_MDIV_SELP_SHIFT)
+#define PLL0USB_MDIV_SELI_SHIFT         (22)     /* Bits 22-27: Bandwidth select I value */
+#define PLL0USB_MDIV_SELI_MASK          (0x3f << PLL0USB_MDIV_SELI_SHIFT)
+#  define PLL0USB_MDIV_SELI(n)          ((n) << PLL0USB_MDIV_SELI_SHIFT)
+#define PLL0USB_MDIV_SELR_SHIFT         (28)     /* Bits 28-31: Bandwidth select R value */
+#define PLL0USB_MDIV_SELR_MASK          (15 << PLL0USB_MDIV_SELR_SHIFT)
+#  define PLL0USB_MDIV_SELR(n)          ((n) << PLL0USB_MDIV_SELR_SHIFT)
+
+/* PLL0USB N/P-divider register */
+
+#define PLL0USB_NP_DIV_PDEC_SHIFT       (0)      /* Bits 0-6: Decoded P-divider coefficient value */
+#define PLL0USB_NP_DIV_PDEC_MASK        (0x7f << PLL0USB_NP_DIV_PDEC_SHIFT)
+#  define PLL0USB_NP_DIV_PDEC(n)        ((n) << PLL0USB_NP_DIV_PDEC_SHIFT)
+                                                 /* Bits 7-11:  Reserved */
+#define PLL0USB_NP_DIV_NDEC_SHIFT       (12)     /* Bits 12-21: Decoded N-divider coefficient value */
+#define PLL0USB_NP_DIV_NDEC_MASK        (0x3ff << PLL0USB_NP_DIV_NDEC_SHIFT)
+#  define PLL0USB_NP_DIV_NDEC(n)        ((n) << PLL0USB_NP_DIV_NDEC_SHIFT)
+                                                 /* Bits 22-31:  Reserved */
+/* PLL0AUDIO status register */
+
+#define PLL0AUDIO_STAT_LOCK             (1 << 0)  /* Bit 0:  PLL0 lock indicator */
+#define PLL0AUDIO_STAT_FR               (1 << 1)  /* Bit 1:  PLL0 free running indicator */
+                                                  /* Bits 2-31: Reserved */
+/* PLL0AUDIO control register */
+
+#define PLL0AUDIO_CTRL_PD               (1 << 0)  /* Bit 0:  PLL0 power down */
+#define PLL0AUDIO_CTRL_BYPASS           (1 << 1)  /* Bit 1:  Input clock bypass control */
+#define PLL0AUDIO_CTRL_DIRECTI          (1 << 2)  /* Bit 2:  PLL0 direct input */
+#define PLL0AUDIO_CTRL_DIRECTO          (1 << 3)  /* Bit 3:  PLL0 direct output */
+#define PLL0AUDIO_CTRL_CLKEN            (1 << 4)  /* Bit 4:  PLL0 clock enable */
+                                                  /* Bit 5:  Reserved */
+#define PLL0AUDIO_CTRL_FRM              (1 << 6)  /* Bit 6:  Free running mode */
+                                                  /* Bits 7-10: Reserved */
+#define PLL0AUDIO_CTRL_AUTOBLOCK        (1 << 11) /* Bit 11: Block clock during frequency change */
+
+#define PLL0AUDIO_CTRL_PLLFRACTREQ      (1 << 12) /* Bit 12: Fractional PLL word write request */
+#define PLL0AUDIO_CTRL_SELEXT           (1 << 13) /* Bit 13: Select fractional divider */
+#define PLL0AUDIO_CTRL_MODPD            (1 << 14) /* Bit 14: Sigma-Delta modulator power-down */
+                                                  /* Bits 15-23: Reserved */
+#define PLL0AUDIO_CTRL_CLKSEL_SHIFT     (24)      /* Bits 24-28: Clock source selection */
+#define PLL0AUDIO_CTRL_CLKSEL_MASK      (31 << PLL0AUDIO_CTRL_CLKSEL_SHIFT)
+#  define PLL0AUDIO_CLKSEL_32KHZOSC     (0 << PLL0AUDIO_CTRL_CLKSEL_SHIFT)  /* 32 kHz oscillator */
+#  define PLL0AUDIO_CLKSEL_IRC          (1 << PLL0AUDIO_CTRL_CLKSEL_SHIFT)  /* IRC (default) */
+#  define PLL0AUDIO_CLKSEL_ENET_RXCLK   (2 << PLL0AUDIO_CTRL_CLKSEL_SHIFT)  /* ENET_RX_CLK */
+#  define PLL0AUDIO_CLKSEL_ENET_TXCLK   (3 << PLL0AUDIO_CTRL_CLKSEL_SHIFT)  /* ENET_TX_CLK */
+#  define PLL0AUDIO_CLKSEL_GPCLKIN      (4 << PLL0AUDIO_CTRL_CLKSEL_SHIFT)  /* GP_CLKIN */
+#  define PLL0AUDIO_CLKSEL_XTAL         (6 << PLL0AUDIO_CTRL_CLKSEL_SHIFT)  /* Crystal oscillator */
+#  define PLL0AUDIO_CLKSEL_PLL1         (9 << PLL0AUDIO_CTRL_CLKSEL_SHIFT)  /* PLL1 */
+#  define PLL0AUDIO_CLKSEL_IDIVA        (12 << PLL0AUDIO_CTRL_CLKSEL_SHIFT) /* IDIVA */
+#  define PLL0AUDIO_CLKSEL_IDIVB        (13 << PLL0AUDIO_CTRL_CLKSEL_SHIFT) /* IDIVB */
+#  define PLL0AUDIO_CLKSEL_IDIVC        (14 << PLL0AUDIO_CTRL_CLKSEL_SHIFT) /* IDIVC */
+#  define PLL0AUDIO_CLKSEL_IDIVD        (15 << PLL0AUDIO_CTRL_CLKSEL_SHIFT) /* IDIVD */
+#  define PLL0AUDIO_CLKSEL_IDIVE        (16 << PLL0AUDIO_CTRL_CLKSEL_SHIFT) /* IDIVE */
+                                                  /* Bits 29-31:  Reserved */
+/* PLL0AUDIO M-divider */
+
+#define PLL0AUDIO_MDIV_MDEC_SHIFT       (0)       /* Bits 0-16: Decoded M-divider coefficient value (1-131071) */
+#define PLL0AUDIO_MDIV_MDEC_MASK        (0x1ffff << PLL0AUDIO_MDIV_MDEC_SHIFT)
+#  define PLL0AUDIO_MDIV_MDEC(n)        ((n) << PLL0AUDIO_MDIV_MDEC_SHIFT)
+                                                  /* Bits 17-31:  Reserved */
+/* PLL0AUDIO N/P-divider */
+
+#define PLL0AUDIO_NP_DIV_PDEC_SHIFT     (0)      /* Bits 0-6: Decoded P-divider coefficient value */
+#define PLL0AUDIO_NP_DIV_PDEC_MASK      (0x7f << PLL0AUDIO_NP_DIV_PDEC_SHIFT)
+#  define PLL0AUDIO_NP_DIV_PDEC(n)      ((n) << PLL0AUDIO_NP_DIV_PDEC_SHIFT)
+                                                 /* Bits 7-11:  Reserved */
+#define PLL0AUDIO_NP_DIV_NDEC_SHIFT     (12)     /* Bits 12-21: Decoded N-divider coefficient value */
+#define PLL0AUDIO_NP_DIV_NDEC_MASK      (0x3ff << PLL0AUDIO_NP_DIV_NDEC_SHIFT)
+#  define PLL0AUDIO_NP_DIV_NDEC(n)      ((n) << PLL0AUDIO_NP_DIV_NDEC_SHIFT)
+                                                 /* Bits 22-31:  Reserved */
+/* PLL0AUDIO fractional */
+
+#define PLL0AUDIO_FRAC_CTRL_SHIFT       (0)      /* Bits 0-21: Decoded P-divider coefficient value */
+#define PLL0AUDIO_FRAC_CTRL_MASK        (0x3fffff << PLL0AUDIO_FRAC_CTRL_SHIFT)
+#  define PLL0AUDIO_FRA_CCTRL(n)        ((n) << PLL0AUDIO_FRAC_CTRL_SHIFT)
+                                                 /* Bits 22-31:  Reserved */
+/* PLL1 status register */
+
+#define PLL1_STAT_LOCK                  (1 << 0)  /* Bit 0:  PLL1 lock indicator */
+                                                  /* Bits 1-31: Reserved */
+/* PLL1 control register */
+
+#define PLL1_CTRL_PD                    (1 << 0)  /* Bit 0:  PLL1 power down */
+#define PLL1_CTRL_BYPASS                (1 << 1)  /* Bit 1:  Input clock bypass control */
+                                                  /* Bits 2-5: Reserved */
+#define PLL1_CTRL_FBSEL                 (1 << 6)  /* Bit 6:  PLL1 feedback select */
+#define PLL1_CTRL_DIRECT                (1 << 7)  /* Bit 7:  PLL1 direct CCO output */
+
+#define PLL1_CTRL_PSEL_SHIFT            (8)       /* Bits 8-9: Post-divider division ratio P */
+#define PLL1_CTRL_PSEL_MASK             (3 << PLL1_CTRL_PSEL_SHIFT)
+#  define PLL1_CTRL_PSEL_DIV1           (0 << PLL1_CTRL_PSEL_SHIFT)
+#  define PLL1_CTRL_PSEL_DIV2           (1 << PLL1_CTRL_PSEL_SHIFT)
+#  define PLL1_CTRL_PSEL_DIV4           (2 << PLL1_CTRL_PSEL_SHIFT)
+#  define PLL1_CTRL_PSEL_DIV8           (3 << PLL1_CTRL_PSEL_SHIFT)
+                                                  /* Bit 10: Reserved */
+#define PLL1_CTRL_AUTOBLOCK             (1 << 11) /* Bit 11: Block clock during frequency change */
+#define PLL1_CTRL_NSEL_SHIFT            (12)      /* Bits 12-13: Pre-divider division ratio N */
+#define PLL1_CTRL_NSEL_MASK             (3 << PLL1_CTRL_NSEL_SHIFT)
+#  define PLL1_CTRL_NSEL_DIV1           (0 << PLL1_CTRL_NSEL_SHIFT)
+#  define PLL1_CTRL_NSEL_DIV2           (1 << PLL1_CTRL_NSEL_SHIFT)
+#  define PLL1_CTRL_NSEL_DIV3           (2 << PLL1_CTRL_NSEL_SHIFT)
+#  define PLL1_CTRL_NSEL_DIV4           (3 << PLL1_CTRL_NSEL_SHIFT)
+                                                  /* Bits 14-15: Reserved */
+#define PLL1_CTRL_MSEL_SHIFT            (16)      /* Bits 16-23: Feedback-divider division ratio M */
+#define PLL1_CTRL_MSEL_MASK             (0xff << PLL1_CTRL_MSEL_SHIFT)
+#  define PLL1_CTRL_MSEL(n)             (((n)-1) << PLL1_CTRL_MSEL_SHIFT) /* n=1..256 */
+#define PLL1_CTRL_CLKSEL_SHIFT          (24)      /* Bits 24-28: Clock source selection */
+#define PLL1_CTRL_CLKSEL_MASK           (31 << PLL1_CTRL_CLKSEL_SHIFT)
+#  define PLL1_CLKSEL_32KHZOSC          (0 << PLL1_CTRL_CLKSEL_SHIFT)  /* 32 kHz oscillator */
+#  define PLL1_CLKSEL_IRC               (1 << PLL1_CTRL_CLKSEL_SHIFT)  /* IRC (default) */
+#  define PLL1_CLKSEL_ENET_RXCLK        (2 << PLL1_CTRL_CLKSEL_SHIFT)  /* ENET_RX_CLK */
+#  define PLL1_CLKSEL_ENET_TXCLK        (3 << PLL1_CTRL_CLKSEL_SHIFT)  /* ENET_TX_CLK */
+#  define PLL1_CLKSEL_GPCLKIN           (4 << PLL1_CTRL_CLKSEL_SHIFT)  /* GP_CLKIN */
+#  define PLL1_CLKSEL_XTAL              (6 << PLL1_CTRL_CLKSEL_SHIFT)  /* Crystal oscillator */
+#  define PLL1_CLKSEL_PLL0USB           (7 << PLL1_CTRL_CLKSEL_SHIFT)  /* PLL0USB */
+#  define PLL1_CLKSEL_PLL0AUDIO         (8 << PLL1_CTRL_CLKSEL_SHIFT)  /* PLL0AUDIO */
+#  define PLL1_CLKSEL_IDIVA             (12 << PLL1_CTRL_CLKSEL_SHIFT) /* IDIVA */
+#  define PLL1_CLKSEL_IDIVB             (13 << PLL1_CTRL_CLKSEL_SHIFT) /* IDIVB */
+#  define PLL1_CLKSEL_IDIVC             (14 << PLL1_CTRL_CLKSEL_SHIFT) /* IDIVC */
+#  define PLL1_CLKSEL_IDIVD             (15 << PLL1_CTRL_CLKSEL_SHIFT) /* IDIVD */
+#  define PLL1_CLKSEL_IDIVE             (16 << PLL1_CTRL_CLKSEL_SHIFT) /* IDIVE */
+                                                 /* Bits 29-31:  Reserved */
+/* Integer divider A control register */
+
+#define IDIVA_CTRL_PD                   (1 << 0)  /* Bit 0:  Integer divider A power down */
+                                                  /* Bit 1:  Reserved */
+#define IDIVA_CTRL_IDIV_SHIFT           (2)       /* Bits 2-3: Integer divider A divider values (1/(IDIV + 1)) */
+#define IDIVA_CTRL_IDIV_MASK            (3 << IDIVA_CTRL_IDIV_SHIFT)
+#  define IDIVA_CTRL_IDIV(n)            (((n)-1) << IDIVA_CTRL_IDIV_SHIFT) /* n=1..4 */
+                                                  /* Bits 4-10: Reserved */
+#define IDIVA_CTRL_AUTOBLOCK            (1 << 11) /* Bit 11: Block clock during frequency change */
+                                                  /* Bits 12-23: Reserved */
+#define IDIVA_CTRL_CLKSEL_SHIFT         (24)      /* Bits 24-28: Clock source selection */
+#define IDIVA_CTRL_CLKSEL_MASK          (31 << IDIVA_CTRL_CLKSEL_SHIFT)
+#  define IDIVA_CLKSEL_32KHZOSC         (0 << IDIVA_CTRL_CLKSEL_SHIFT)  /* 32 kHz oscillator */
+#  define IDIVA_CLKSEL_IRC              (1 << IDIVA_CTRL_CLKSEL_SHIFT)  /* IRC (default) */
+#  define IDIVA_CLKSEL_ENET_RXCLK       (2 << IDIVA_CTRL_CLKSEL_SHIFT)  /* ENET_RX_CLK */
+#  define IDIVA_CLKSEL_ENET_TXCLK       (3 << IDIVA_CTRL_CLKSEL_SHIFT)  /* ENET_TX_CLK */
+#  define IDIVA_CLKSEL_GPCLKIN          (4 << IDIVA_CTRL_CLKSEL_SHIFT)  /* GP_CLKIN */
+#  define IDIVA_CLKSEL_XTAL             (6 << IDIVA_CTRL_CLKSEL_SHIFT)  /* Crystal oscillator */
+#  define IDIVA_CLKSEL_PLL0USB          (7 << IDIVA_CTRL_CLKSEL_SHIFT)  /* PLL0USB */
+#  define IDIVA_CLKSEL_PLL0AUDIO        (8 << IDIVA_CTRL_CLKSEL_SHIFT)  /* PLL0AUDIO */
+#  define IDIVA_CLKSEL_PLL1             (9 << IDIVA_CTRL_CLKSEL_SHIFT)  /* PLL1 */
+                                                 /* Bits 29-31:  Reserved */
+/* Integer divider B/C/D control register */
+
+#define IDIVBCD_CTRL_PD                 (1 << 0)  /* Bit 0:  Integer divider power down */
+                                                  /* Bit 1: Reserved */
+#define IDIVBCD_CTRL_IDIV_SHIFT         (2)       /* Bits 2-5: Integer divider A divider values (1/(IDIV + 1)) */
+#define IDIVBCD_CTRL_IDIV_MASK          (15 << IDIVBCD_CTRL_IDIV_SHIFT)
+#  define IDIVBCD_CTRL_IDIV(n)          (((n)-1) << IDIVBCD_CTRL_IDIV_SHIFT) /* n=1..16 */
+                                                  /* Bits 6-10: Reserved */
+#define IDIVBCD_CTRL_AUTOBLOCK          (1 << 11) /* Bit 11: Block clock during frequency change */
+                                                  /* Bits 12-23: Reserved */
+#define IDIVBCD_CTRL_CLKSEL_SHIFT       (24)      /* Bits 24-28: Clock source selection */
+#define IDIVBCD_CTRL_CLKSEL_MASK        (31 << IDIVBCD_CTRL_CLKSEL_SHIFT)
+#  define IDIVBCD_CLKSEL_32KHZOSC       (0 << IDIVBCD_CTRL_CLKSEL_SHIFT)  /* 32 kHz oscillator */
+#  define IDIVBCD_CLKSEL_IRC            (1 << IDIVBCD_CTRL_CLKSEL_SHIFT)  /* IRC (default) */
+#  define IDIVBCD_CLKSEL_ENET_RXCLK     (2 << IDIVBCD_CTRL_CLKSEL_SHIFT)  /* ENET_RX_CLK */
+#  define IDIVBCD_CLKSEL_ENET_TXCLK     (3 << IDIVBCD_CTRL_CLKSEL_SHIFT)  /* ENET_TX_CLK */
+#  define IDIVBCD_CLKSEL_GPCLKIN        (4 << IDIVBCD_CTRL_CLKSEL_SHIFT)  /* GP_CLKIN */
+#  define IDIVBCD_CLKSEL_XTAL           (6 << IDIVBCD_CTRL_CLKSEL_SHIFT)  /* Crystal oscillator */
+#  define IDIVBCD_CLKSEL_PLL0AUDIO      (8 << IDIVBCD_CTRL_CLKSEL_SHIFT)  /* PLL0AUDIO */
+#  define IDIVBCD_CLKSEL_PLL1           (9 << IDIVBCD_CTRL_CLKSEL_SHIFT)  /* PLL1 */
+#  define IDIVBCD_CLKSEL_IDIVA          (12 << IDIVBCD_CTRL_CLKSEL_SHIFT) /* IDIVA */
+                                                 /* Bits 29-31:  Reserved */
+/* Integer divider E control register */
+
+#define IDIVE_CTRL_PD                   (1 << 0)  /* Bit 0:  Integer divider E power down */
+                                                  /* Bit 1: Reserved */
+#define IDIVE_CTRL_IDIV_SHIFT           (2)       /* Bits 2-9: Integer divider A divider values (1/(IDIV + 1)) */
+#define IDIVE_CTRL_IDIV_MASK            (0xff << IDIVE_CTRL_IDIV_SHIFT)
+#  define IDIVE_CTRL_IDIV(n)            (((n)-1) << IDIVE_CTRL_IDIV_SHIFT) /* n=1..256 */
+                                                  /* Bit 10: Reserved */
+#define IDIVE_CTRL_AUTOBLOCK            (1 << 11) /* Bit 11: Block clock during frequency change */
+                                                  /* Bits 12-23: Reserved */
+#define IDIVE_CTRL_CLKSEL_SHIFT         (24)      /* Bits 24-28: Clock source selection */
+#define IDIVE_CTRL_CLKSEL_MASK          (31 << IDIVE_CTRL_CLKSEL_SHIFT)
+#  define IDIVE_CLKSEL_32KHZOSC         (0 << IDIVE_CTRL_CLKSEL_SHIFT)  /* 32 kHz oscillator */
+#  define IDIVE_CLKSEL_IRC              (1 << IDIVE_CTRL_CLKSEL_SHIFT)  /* IRC (default) */
+#  define IDIVE_CLKSEL_ENET_RXCLK       (2 << IDIVE_CTRL_CLKSEL_SHIFT)  /* ENET_RX_CLK */
+#  define IDIVE_CLKSEL_ENET_TXCLK       (3 << IDIVE_CTRL_CLKSEL_SHIFT)  /* ENET_TX_CLK */
+#  define IDIVE_CLKSEL_GPCLKIN          (4 << IDIVE_CTRL_CLKSEL_SHIFT)  /* GP_CLKIN */
+#  define IDIVE_CLKSEL_XTAL             (6 << IDIVE_CTRL_CLKSEL_SHIFT)  /* Crystal oscillator */
+#  define IDIVE_CLKSEL_PLL0AUDIO        (8 << IDIVE_CTRL_CLKSEL_SHIFT)  /* PLL0AUDIO */
+#  define IDIVE_CLKSEL_PLL1             (9 << IDIVE_CTRL_CLKSEL_SHIFT)  /* PLL1 */
+#  define IDIVE_CLKSEL_IDIVA            (12 << IDIVE_CTRL_CLKSEL_SHIFT) /* IDIVA */
+                                                 /* Bits 29-31:  Reserved */
+/* Output stage 0 control register (BASE_SAFE_CLK) */
+
+#define BASE_SAFE_CLK_PD                (1 << 0)  /* Bit 0:  Output stage power down */
+                                                  /* Bits 1-10: Reserved */
+#define BASE_SAFE_CLK_AUTOBLOCK         (1 << 11) /* Bit 11: Block clock during frequency change */
+                                                  /* Bits 12-23: Reserved */
+#define BASE_SAFE_CLK_CLKSEL_SHIFT      (24)      /* Bits 24-28: Clock source selection */
+#define BASE_SAFE_CLK_CLKSEL_MASK       (31 << BASE_SAFE_CLK_CLKSEL_SHIFT)
+#  define BASE_SAFE_CLKSEL_IRC          (1 << BASE_SAFE_CLK_CLKSEL_SHIFT)  /* IRC (default) */
+                                                 /* Bits 29-31:  Reserved */
+/* Output stage 1 control register (BASE_USB0_CLK) */
+
+#define BASE_USB0_CLK_PD                (1 << 0)  /* Bit 0:  Output stage power down */
+                                                  /* Bits 1-10: Reserved */
+#define BASE_USB0_CLK_AUTOBLOCK         (1 << 11) /* Bit 11: Block clock during frequency change */
+                                                  /* Bits 12-23: Reserved */
+#define BASE_USB0_CLK_CLKSEL_SHIFT      (24)      /* Bits 24-28: Clock source selection */
+#define BASE_USB0_CLK_CLKSEL_MASK       (31 << BASE_USB0_CLK_CLKSEL_SHIFT)
+#  define BASE_USB0_CLKSEL_PLL0USB      (7 << BASE_USB0_CLK_CLKSEL_SHIFT)  /* PLL0USB (default) */
+                                                  /* Bits 29-31:  Reserved */
+/* Output stage 2 control register (BASE_PERIPH_CLK) */
+
+#define BASE_PERIPH_CLK_PD              (1 << 0)  /* Bit 0:  Output stage power down */
+                                                  /* Bits 1-10: Reserved */
+#define BASE_PERIPH_CLK_AUTOBLOCK       (1 << 11) /* Bit 11: Block clock during frequency change */
+                                                  /* Bits 12-23: Reserved */
+#define BASE_PERIPH_CLK_CLKSEL_SHIFT    (24)      /* Bits 24-28: Clock source selection */
+#define BASE_PERIPH_CLK_CLKSEL_MASK     (31 << BASE_PERIPH_CLK_CLKSEL_SHIFT)
+#  define BASE_PERIPH_CLKSEL_32KHZOSC   (0 << BASE_PERIPH_CLK_CLKSEL_SHIFT)  /* 32 kHz oscillator */
+#  define BASE_PERIPH_CLKSEL_IRC        (1 << BASE_PERIPH_CLK_CLKSEL_SHIFT)  /* IRC (default) */
+#  define BASE_PERIPH_CLKSEL_ENET_RXCLK (2 << BASE_PERIPH_CLK_CLKSEL_SHIFT)  /* ENET_RX_CLK */
+#  define BASE_PERIPH_CLKSEL_ENET_TXCLK (3 << BASE_PERIPH_CLK_CLKSEL_SHIFT)  /* ENET_TX_CLK */
+#  define BASE_PERIPH_CLKSEL_GPCLKIN    (4 << BASE_PERIPH_CLK_CLKSEL_SHIFT)  /* GP_CLKIN */
+#  define BASE_PERIPH_CLKSEL_XTAL       (6 << BASE_PERIPH_CLK_CLKSEL_SHIFT)  /* Crystal oscillator */
+#  define BASE_PERIPH_CLKSEL_PLL0AUDIO  (8 << BASE_PERIPH_CLK_CLKSEL_SHIFT)  /* PLL0AUDIO */
+#  define BASE_PERIPH_CLKSEL_PLL1       (9 << BASE_PERIPH_CLK_CLKSEL_SHIFT)  /* PLL1 */
+#  define BASE_PERIPH_CLKSEL_IDIVA      (12 << BASE_PERIPH_CLK_CLKSEL_SHIFT) /* IDIVA */
+#  define BASE_PERIPH_CLKSEL_IDIVB      (13 << BASE_PERIPH_CLK_CLKSEL_SHIFT) /* IDIVB */
+#  define BASE_PERIPH_CLKSEL_IDIVC      (14 << BASE_PERIPH_CLK_CLKSEL_SHIFT) /* IDIVC */
+#  define BASE_PERIPH_CLKSEL_IDIVD      (15 << BASE_PERIPH_CLK_CLKSEL_SHIFT) /* IDIVD */
+#  define BASE_PERIPH_CLKSEL_IDIVE      (16 << BASE_PERIPH_CLK_CLKSEL_SHIFT) /* IDIVE */
+                                                  /* Bits 29-31:  Reserved */
+/* Output stage 3 control register (BASE_USB1_CLK) */
+
+#define BASE_USB1_CLK_PD                (1 << 0)  /* Bit 0:  Output stage power down */
+                                                  /* Bits 1-10: Reserved */
+#define BASE_USB1_CLK_AUTOBLOCK         (1 << 11) /* Bit 11: Block clock during frequency change */
+                                                  /* Bits 12-23: Reserved */
+#define BASE_USB1_CLK_CLKSEL_SHIFT      (24)      /* Bits 24-28: Clock source selection */
+#define BASE_USB1_CLK_CLKSEL_MASK       (31 << BASE_USB1_CLK_CLKSEL_SHIFT)
+#  define BASE_USB1_CLKSEL_32KHZOSC     (0 << BASE_USB1_CLK_CLKSEL_SHIFT)  /* 32 kHz oscillator */
+#  define BASE_USB1_CLKSEL_IRC          (1 << BASE_USB1_CLK_CLKSEL_SHIFT)  /* IRC (default) */
+#  define BASE_USB1_CLKSEL_ENET_RXCLK   (2 << BASE_USB1_CLK_CLKSEL_SHIFT)  /* ENET_RX_CLK */
+#  define BASE_USB1_CLKSEL_ENET_TXCLK   (3 << BASE_USB1_CLK_CLKSEL_SHIFT)  /* ENET_TX_CLK */
+#  define BASE_USB1_CLKSEL_GPCLKIN      (4 << BASE_USB1_CLK_CLKSEL_SHIFT)  /* GP_CLKIN */
+#  define BASE_USB1_CLKSEL_XTAL         (6 << BASE_USB1_CLK_CLKSEL_SHIFT)  /* Crystal oscillator */
+#  define BASE_USB1_CLKSEL_PLL0USB      (7 << BASE_USB1_CLK_CLKSEL_SHIFT)  /* PLL0USB */
+#  define BASE_USB1_CLKSEL_PLL0AUDIO    (8 << BASE_USB1_CLK_CLKSEL_SHIFT)  /* PLL0AUDIO */
+#  define BASE_USB1_CLKSEL_PLL1         (9 << BASE_USB1_CLK_CLKSEL_SHIFT)  /* PLL1 */
+#  define BASE_USB1_CLKSEL_IDIVA        (12 << BASE_USB1_CLK_CLKSEL_SHIFT) /* IDIVA */
+#  define BASE_USB1_CLKSEL_IDIVB        (13 << BASE_USB1_CLK_CLKSEL_SHIFT) /* IDIVB */
+#  define BASE_USB1_CLKSEL_IDIVC        (14 << BASE_USB1_CLK_CLKSEL_SHIFT) /* IDIVC */
+#  define BASE_USB1_CLKSEL_IDIVD        (15 << BASE_USB1_CLK_CLKSEL_SHIFT) /* IDIVD */
+#  define BASE_USB1_CLKSEL_IDIVE        (16 << BASE_USB1_CLK_CLKSEL_SHIFT) /* IDIVE */
+                                                 /* Bits 29-31:  Reserved */
+/* Output stage 4 control register (BASE_M4_CLK) */
+/* NOTE: Clocks 4-19 are identical */
+
+#define BASE_M4_CLK_PD                  (1 << 0)  /* Bit 0:  Output stage power down */
+                                                  /* Bits 1-10: Reserved */
+#define BASE_M4_CLK_AUTOBLOCK           (1 << 11) /* Bit 11: Block clock during frequency change */
+                                                  /* Bits 12-23: Reserved */
+#define BASE_M4_CLK_CLKSEL_SHIFT        (24)      /* Bits 24-28: Clock source selection */
+#define BASE_M4_CLK_CLKSEL_MASK         (31 << BASE_M4_CLK_CLKSEL_SHIFT)
+#  define BASE_M4_CLKSEL_32KHZOSC       (0 << BASE_M4_CLK_CLKSEL_SHIFT)  /* 32 kHz oscillator */
+#  define BASE_M4_CLKSEL_IRC            (1 << BASE_M4_CLK_CLKSEL_SHIFT)  /* IRC (default) */
+#  define BASE_M4_CLKSEL_ENET_RXCLK     (2 << BASE_M4_CLK_CLKSEL_SHIFT)  /* ENET_RX_CLK */
+#  define BASE_M4_CLKSEL_ENET_TXCLK     (3 << BASE_M4_CLK_CLKSEL_SHIFT)  /* ENET_TX_CLK */
+#  define BASE_M4_CLKSEL_GPCLKIN        (4 << BASE_M4_CLK_CLKSEL_SHIFT)  /* GP_CLKIN */
+#  define BASE_M4_CLKSEL_XTAL           (6 << BASE_M4_CLK_CLKSEL_SHIFT)  /* Crystal oscillator */
+#  define BASE_M4_CLKSEL_PLL0AUDIO      (8 << BASE_M4_CLK_CLKSEL_SHIFT)  /* PLL0AUDIO */
+#  define BASE_M4_CLKSEL_PLL1           (9 << BASE_M4_CLK_CLKSEL_SHIFT)  /* PLL1 */
+#  define BASE_M4_CLKSEL_IDIVA          (12 << BASE_M4_CLK_CLKSEL_SHIFT) /* IDIVA */
+#  define BASE_M4_CLKSEL_IDIVB          (13 << BASE_M4_CLK_CLKSEL_SHIFT) /* IDIVB */
+#  define BASE_M4_CLKSEL_IDIVC          (14 << BASE_M4_CLK_CLKSEL_SHIFT) /* IDIVC */
+#  define BASE_M4_CLKSEL_IDIVD          (15 << BASE_M4_CLK_CLKSEL_SHIFT) /* IDIVD */
+#  define BASE_M4_CLKSEL_IDIVE          (16 << BASE_M4_CLK_CLKSEL_SHIFT) /* IDIVE */
+                                                 /* Bits 29-31:  Reserved */
+/* Output stage 5 control register (BASE_SPIFI_CLK) */
+/* NOTE: Clocks 4-19 are identical */
+
+#define BASE_SPIFI_CLK_PD               (1 << 0)  /* Bit 0:  Output stage power down */
+                                                  /* Bits 1-10: Reserved */
+#define BASE_SPIFI_CLK_AUTOBLOCK        (1 << 11) /* Bit 11: Block clock during frequency change */
+                                                  /* Bits 12-23: Reserved */
+#define BASE_SPIFI_CLK_CLKSEL_SHIFT     (24)      /* Bits 24-28: Clock source selection */
+#define BASE_SPIFI_CLK_CLKSEL_MASK      (31 << BASE_SPIFI_CLK_CLKSEL_SHIFT)
+#  define BASE_SPIFI_CLKSEL_32KHZOSC    (0 << BASE_SPIFI_CLK_CLKSEL_SHIFT)  /* 32 kHz oscillator */
+#  define BASE_SPIFI_CLKSEL_IRC         (1 << BASE_SPIFI_CLK_CLKSEL_SHIFT)  /* IRC (default) */
+#  define BASE_SPIFI_CLKSEL_ENET_RXCLK  (2 << BASE_SPIFI_CLK_CLKSEL_SHIFT)  /* ENET_RX_CLK */
+#  define BASE_SPIFI_CLKSEL_ENET_TXCLK  (3 << BASE_SPIFI_CLK_CLKSEL_SHIFT)  /* ENET_TX_CLK */
+#  define BASE_SPIFI_CLKSEL_GPCLKIN     (4 << BASE_SPIFI_CLK_CLKSEL_SHIFT)  /* GP_CLKIN */
+#  define BASE_SPIFI_CLKSEL_XTAL        (6 << BASE_SPIFI_CLK_CLKSEL_SHIFT)  /* Crystal oscillator */
+#  define BASE_SPIFI_CLKSEL_PLL0AUDIO   (8 << BASE_SPIFI_CLK_CLKSEL_SHIFT)  /* PLL0AUDIO */
+#  define BASE_SPIFI_CLKSEL_PLL1        (9 << BASE_SPIFI_CLK_CLKSEL_SHIFT)  /* PLL1 */
+#  define BASE_SPIFI_CLKSEL_IDIVA       (12 << BASE_SPIFI_CLK_CLKSEL_SHIFT) /* IDIVA */
+#  define BASE_SPIFI_CLKSEL_IDIVB       (13 << BASE_SPIFI_CLK_CLKSEL_SHIFT) /* IDIVB */
+#  define BASE_SPIFI_CLKSEL_IDIVC       (14 << BASE_SPIFI_CLK_CLKSEL_SHIFT) /* IDIVC */
+#  define BASE_SPIFI_CLKSEL_IDIVD       (15 << BASE_SPIFI_CLK_CLKSEL_SHIFT) /* IDIVD */
+#  define BASE_SPIFI_CLKSEL_IDIVE       (16 << BASE_SPIFI_CLK_CLKSEL_SHIFT) /* IDIVE */
+                                                 /* Bits 29-31:  Reserved */
+/* Output stage 6 control register (BASE_SPI_CLK) */
+/* NOTE: Clocks 4-19 are identical */
+
+#define BASE_SPI_CLK_PD                 (1 << 0)  /* Bit 0:  Output stage power down */
+                                                  /* Bits 1-10: Reserved */
+#define BASE_SPI_CLK_AUTOBLOCK          (1 << 11) /* Bit 11: Block clock during frequency change */
+                                                  /* Bits 12-23: Reserved */
+#define BASE_SPI_CLK_CLKSEL_SHIFT       (24)      /* Bits 24-28: Clock source selection */
+#define BASE_SPI_CLK_CLKSEL_MASK        (31 << BASE_SPI_CLK_CLKSEL_SHIFT)
+#  define BASE_SPI_CLKSEL_32KHZOSC      (0 << BASE_SPI_CLK_CLKSEL_SHIFT)  /* 32 kHz oscillator */
+#  define BASE_SPI_CLKSEL_IRC           (1 << BASE_SPI_CLK_CLKSEL_SHIFT)  /* IRC (default) */
+#  define BASE_SPI_CLKSEL_ENET_RXCLK    (2 << BASE_SPI_CLK_CLKSEL_SHIFT)  /* ENET_RX_CLK */
+#  define BASE_SPI_CLKSEL_ENET_TXCLK    (3 << BASE_SPI_CLK_CLKSEL_SHIFT)  /* ENET_TX_CLK */
+#  define BASE_SPI_CLKSEL_GPCLKIN       (4 << BASE_SPI_CLK_CLKSEL_SHIFT)  /* GP_CLKIN */
+#  define BASE_SPI_CLKSEL_XTAL          (6 << BASE_SPI_CLK_CLKSEL_SHIFT)  /* Crystal oscillator */
+#  define BASE_SPI_CLKSEL_PLL0AUDIO     (8 << BASE_SPI_CLK_CLKSEL_SHIFT)  /* PLL0AUDIO */
+#  define BASE_SPI_CLKSEL_PLL1          (9 << BASE_SPI_CLK_CLKSEL_SHIFT)  /* PLL1 */
+#  define BASE_SPI_CLKSEL_IDIVA         (12 << BASE_SPI_CLK_CLKSEL_SHIFT) /* IDIVA */
+#  define BASE_SPI_CLKSEL_IDIVB         (13 << BASE_SPI_CLK_CLKSEL_SHIFT) /* IDIVB */
+#  define BASE_SPI_CLKSEL_IDIVC         (14 << BASE_SPI_CLK_CLKSEL_SHIFT) /* IDIVC */
+#  define BASE_SPI_CLKSEL_IDIVD         (15 << BASE_SPI_CLK_CLKSEL_SHIFT) /* IDIVD */
+#  define BASE_SPI_CLKSEL_IDIVE         (16 << BASE_SPI_CLK_CLKSEL_SHIFT) /* IDIVE */
+                                                 /* Bits 29-31:  Reserved */
+/* Output stage 7 control register (BASE_PHY_RX_CLK) */
+/* NOTE: Clocks 4-19 are identical */
+
+#define BASE_PHYRX_CLK_PD               (1 << 0)  /* Bit 0:  Output stage power down */
+                                                  /* Bits 1-10: Reserved */
+#define BASE_PHYRX_CLK_AUTOBLOCK        (1 << 11) /* Bit 11: Block clock during frequency change */
+                                                  /* Bits 12-23: Reserved */
+#define BASE_PHYRX_CLK_CLKSEL_SHIFT     (24)      /* Bits 24-28: Clock source selection */
+#define BASE_PHYRX_CLK_CLKSEL_MASK      (31 << BASE_PHYRX_CLK_CLKSEL_SHIFT)
+#  define BASE_PHYRX_CLKSEL_32KHZOSC    (0 << BASE_PHYRX_CLK_CLKSEL_SHIFT)  /* 32 kHz oscillator */
+#  define BASE_PHYRX_CLKSEL_IRC         (1 << BASE_PHYRX_CLK_CLKSEL_SHIFT)  /* IRC (default) */
+#  define BASE_PHYRX_CLKSEL_ENET_RXCLK  (2 << BASE_PHYRX_CLK_CLKSEL_SHIFT)  /* ENET_RX_CLK */
+#  define BASE_PHYRX_CLKSEL_ENET_TXCLK  (3 << BASE_PHYRX_CLK_CLKSEL_SHIFT)  /* ENET_TX_CLK */
+#  define BASE_PHYRX_CLKSEL_GPCLKIN     (4 << BASE_PHYRX_CLK_CLKSEL_SHIFT)  /* GP_CLKIN */
+#  define BASE_PHYRX_CLKSEL_XTAL        (6 << BASE_PHYRX_CLK_CLKSEL_SHIFT)  /* Crystal oscillator */
+#  define BASE_PHYRX_CLKSEL_PLL0AUDIO   (8 << BASE_PHYRX_CLK_CLKSEL_SHIFT)  /* PLL0AUDIO */
+#  define BASE_PHYRX_CLKSEL_PLL1        (9 << BASE_PHYRX_CLK_CLKSEL_SHIFT)  /* PLL1 */
+#  define BASE_PHYRX_CLKSEL_IDIVA       (12 << BASE_PHYRX_CLK_CLKSEL_SHIFT) /* IDIVA */
+#  define BASE_PHYRX_CLKSEL_IDIVB       (13 << BASE_PHYRX_CLK_CLKSEL_SHIFT) /* IDIVB */
+#  define BASE_PHYRX_CLKSEL_IDIVC       (14 << BASE_PHYRX_CLK_CLKSEL_SHIFT) /* IDIVC */
+#  define BASE_PHYRX_CLKSEL_IDIVD       (15 << BASE_PHYRX_CLK_CLKSEL_SHIFT) /* IDIVD */
+#  define BASE_PHYRX_CLKSEL_IDIVE       (16 << BASE_PHYRX_CLK_CLKSEL_SHIFT) /* IDIVE */
+                                                 /* Bits 29-31:  Reserved */
+/* Output stage 8 control register (BASE_PHY_TX_CLK) */
+/* NOTE: Clocks 4-19 are identical */
+
+#define BASE_PHYTX_CLK_PD               (1 << 0)  /* Bit 0:  Output stage power down */
+                                                  /* Bits 1-10: Reserved */
+#define BASE_PHYTX_CLK_AUTOBLOCK        (1 << 11) /* Bit 11: Block clock during frequency change */
+                                                  /* Bits 12-23: Reserved */
+#define BASE_PHYTX_CLK_CLKSEL_SHIFT     (24)      /* Bits 24-28: Clock source selection */
+#define BASE_PHYTX_CLK_CLKSEL_MASK      (31 << BASE_PHYTX_CLK_CLKSEL_SHIFT)
+#  define BASE_PHYTX_CLKSEL_32KHZOSC    (0 << BASE_PHYTX_CLK_CLKSEL_SHIFT)  /* 32 kHz oscillator */
+#  define BASE_PHYTX_CLKSEL_IRC         (1 << BASE_PHYTX_CLK_CLKSEL_SHIFT)  /* IRC (default) */
+#  define BASE_PHYTX_CLKSEL_ENET_RXCLK  (2 << BASE_PHYTX_CLK_CLKSEL_SHIFT)  /* ENET_RX_CLK */
+#  define BASE_PHYTX_CLKSEL_ENET_TXCLK  (3 << BASE_PHYTX_CLK_CLKSEL_SHIFT)  /* ENET_TX_CLK */
+#  define BASE_PHYTX_CLKSEL_GPCLKIN     (4 << BASE_PHYTX_CLK_CLKSEL_SHIFT)  /* GP_CLKIN */
+#  define BASE_PHYTX_CLKSEL_XTAL        (6 << BASE_PHYTX_CLK_CLKSEL_SHIFT)  /* Crystal oscillator */
+#  define BASE_PHYTX_CLKSEL_PLL0AUDIO   (8 << BASE_PHYTX_CLK_CLKSEL_SHIFT)  /* PLL0AUDIO */
+#  define BASE_PHYTX_CLKSEL_PLL1        (9 << BASE_PHYTX_CLK_CLKSEL_SHIFT)  /* PLL1 */
+#  define BASE_PHYTX_CLKSEL_IDIVA       (12 << BASE_PHYTX_CLK_CLKSEL_SHIFT) /* IDIVA */
+#  define BASE_PHYTX_CLKSEL_IDIVB       (13 << BASE_PHYTX_CLK_CLKSEL_SHIFT) /* IDIVB */
+#  define BASE_PHYTX_CLKSEL_IDIVC       (14 << BASE_PHYTX_CLK_CLKSEL_SHIFT) /* IDIVC */
+#  define BASE_PHYTX_CLKSEL_IDIVD       (15 << BASE_PHYTX_CLK_CLKSEL_SHIFT) /* IDIVD */
+#  define BASE_PHYTX_CLKSEL_IDIVE       (16 << BASE_PHYTX_CLK_CLKSEL_SHIFT) /* IDIVE */
+                                                 /* Bits 29-31:  Reserved */
+/* Output stage 9 control register (BASE_APB1_CLK) */
+/* NOTE: Clocks 4-19 are identical */
+
+#define BASE_APB1_CLK_PD                (1 << 0)  /* Bit 0:  Output stage power down */
+                                                  /* Bits 1-10: Reserved */
+#define BASE_APB1_CLK_AUTOBLOCK         (1 << 11) /* Bit 11: Block clock during frequency change */
+                                                  /* Bits 12-23: Reserved */
+#define BASE_APB1_CLK_CLKSEL_SHIFT      (24)      /* Bits 24-28: Clock source selection */
+#define BASE_APB1_CLK_CLKSEL_MASK       (31 << BASE_APB1_CLK_CLKSEL_SHIFT)
+#  define BASE_APB1_CLKSEL_32KHZOSC     (0 << BASE_APB1_CLK_CLKSEL_SHIFT)  /* 32 kHz oscillator */
+#  define BASE_APB1_CLKSEL_IRC          (1 << BASE_APB1_CLK_CLKSEL_SHIFT)  /* IRC (default) */
+#  define BASE_APB1_CLKSEL_ENET_RXCLK   (2 << BASE_APB1_CLK_CLKSEL_SHIFT)  /* ENET_RX_CLK */
+#  define BASE_APB1_CLKSEL_ENET_TXCLK   (3 << BASE_APB1_CLK_CLKSEL_SHIFT)  /* ENET_TX_CLK */
+#  define BASE_APB1_CLKSEL_GPCLKIN      (4 << BASE_APB1_CLK_CLKSEL_SHIFT)  /* GP_CLKIN */
+#  define BASE_APB1_CLKSEL_XTAL         (6 << BASE_APB1_CLK_CLKSEL_SHIFT)  /* Crystal oscillator */
+#  define BASE_APB1_CLKSEL_PLL0AUDIO    (8 << BASE_APB1_CLK_CLKSEL_SHIFT)  /* PLL0AUDIO */
+#  define BASE_APB1_CLKSEL_PLL1         (9 << BASE_APB1_CLK_CLKSEL_SHIFT)  /* PLL1 */
+#  define BASE_APB1_CLKSEL_IDIVA        (12 << BASE_APB1_CLK_CLKSEL_SHIFT) /* IDIVA */
+#  define BASE_APB1_CLKSEL_IDIVB        (13 << BASE_APB1_CLK_CLKSEL_SHIFT) /* IDIVB */
+#  define BASE_APB1_CLKSEL_IDIVC        (14 << BASE_APB1_CLK_CLKSEL_SHIFT) /* IDIVC */
+#  define BASE_APB1_CLKSEL_IDIVD        (15 << BASE_APB1_CLK_CLKSEL_SHIFT) /* IDIVD */
+#  define BASE_APB1_CLKSEL_IDIVE        (16 << BASE_APB1_CLK_CLKSEL_SHIFT) /* IDIVE */
+                                                 /* Bits 29-31:  Reserved */
+/* Output stage 11 control register (BASE_LCD_CLK) */
+/* NOTE: Clocks 4-19 are identical */
+
+#define BASE_LCD_CLK_PD                 (1 << 0)  /* Bit 0:  Output stage power down */
+                                                  /* Bits 1-10: Reserved */
+#define BASE_LCD_CLK_AUTOBLOCK          (1 << 11) /* Bit 11: Block clock during frequency change */
+                                                  /* Bits 12-23: Reserved */
+#define BASE_LCD_CLK_CLKSEL_SHIFT       (24)      /* Bits 24-28: Clock source selection */
+#define BASE_LCD_CLK_CLKSEL_MASK        (31 << BASE_LCD_CLK_CLKSEL_SHIFT)
+#  define BASE_LCD_CLKSEL_32KHZOSC      (0 << BASE_LCD_CLK_CLKSEL_SHIFT)  /* 32 kHz oscillator */
+#  define BASE_LCD_CLKSEL_IRC           (1 << BASE_LCD_CLK_CLKSEL_SHIFT)  /* IRC (default) */
+#  define BASE_LCD_CLKSEL_ENET_RXCLK    (2 << BASE_LCD_CLK_CLKSEL_SHIFT)  /* ENET_RX_CLK */
+#  define BASE_LCD_CLKSEL_ENET_TXCLK    (3 << BASE_LCD_CLK_CLKSEL_SHIFT)  /* ENET_TX_CLK */
+#  define BASE_LCD_CLKSEL_GPCLKIN       (4 << BASE_LCD_CLK_CLKSEL_SHIFT)  /* GP_CLKIN */
+#  define BASE_LCD_CLKSEL_XTAL          (6 << BASE_LCD_CLK_CLKSEL_SHIFT)  /* Crystal oscillator */
+#  define BASE_LCD_CLKSEL_PLL0AUDIO     (8 << BASE_LCD_CLK_CLKSEL_SHIFT)  /* PLL0AUDIO */
+#  define BASE_LCD_CLKSEL_PLL1          (9 << BASE_LCD_CLK_CLKSEL_SHIFT)  /* PLL1 */
+#  define BASE_LCD_CLKSEL_IDIVA         (12 << BASE_LCD_CLK_CLKSEL_SHIFT) /* IDIVA */
+#  define BASE_LCD_CLKSEL_IDIVB         (13 << BASE_LCD_CLK_CLKSEL_SHIFT) /* IDIVB */
+#  define BASE_LCD_CLKSEL_IDIVC         (14 << BASE_LCD_CLK_CLKSEL_SHIFT) /* IDIVC */
+#  define BASE_LCD_CLKSEL_IDIVD         (15 << BASE_LCD_CLK_CLKSEL_SHIFT) /* IDIVD */
+#  define BASE_LCD_CLKSEL_IDIVE         (16 << BASE_LCD_CLK_CLKSEL_SHIFT) /* IDIVE */
+                                                /* Bits 29-31:  Reserved */
+/* Output stage 12 control register (BASE_VADC_CLK) */
+/* NOTE: Clocks 4-19 are identical */
+
+#define BASE_VADC_CLK_PD                (1 << 0)  /* Bit 0:  Output stage power down */
+                                                  /* Bits 1-10: Reserved */
+#define BASE_VADC_CLK_AUTOBLOCK         (1 << 11) /* Bit 11: Block clock during frequency change */
+                                                  /* Bits 12-23: Reserved */
+#define BASE_VADC_CLK_CLKSEL_SHIFT      (24)      /* Bits 24-28: Clock source selection */
+#define BASE_VADC_CLK_CLKSEL_MASK       (31 << BASE_VADC_CLK_CLKSEL_SHIFT)
+#  define BASE_VADC_CLKSEL_32KHZOSC     (0 << BASE_VADC_CLK_CLKSEL_SHIFT)  /* 32 kHz oscillator */
+#  define BASE_VADC_CLKSEL_IRC          (1 << BASE_VADC_CLK_CLKSEL_SHIFT)  /* IRC (default) */
+#  define BASE_VADC_CLKSEL_ENET_RXCLK   (2 << BASE_VADC_CLK_CLKSEL_SHIFT)  /* ENET_RX_CLK */
+#  define BASE_VADC_CLKSEL_ENET_TXCLK   (3 << BASE_VADC_CLK_CLKSEL_SHIFT)  /* ENET_TX_CLK */
+#  define BASE_VADC_CLKSEL_GPCLKIN      (4 << BASE_VADC_CLK_CLKSEL_SHIFT)  /* GP_CLKIN */
+#  define BASE_VADC_CLKSEL_XTAL         (6 << BASE_VADC_CLK_CLKSEL_SHIFT)  /* Crystal oscillator */
+#  define BASE_VADC_CLKSEL_PLL0AUDIO    (8 << BASE_VADC_CLK_CLKSEL_SHIFT)  /* PLL0AUDIO */
+#  define BASE_VADC_CLKSEL_PLL1         (9 << BASE_VADC_CLK_CLKSEL_SHIFT)  /* PLL1 */
+#  define BASE_VADC_CLKSEL_IDIVA        (12 << BASE_VADC_CLK_CLKSEL_SHIFT) /* IDIVA */
+#  define BASE_VADC_CLKSEL_IDIVB        (13 << BASE_VADC_CLK_CLKSEL_SHIFT) /* IDIVB */
+#  define BASE_VADC_CLKSEL_IDIVC        (14 << BASE_VADC_CLK_CLKSEL_SHIFT) /* IDIVC */
+#  define BASE_VADC_CLKSEL_IDIVD        (15 << BASE_VADC_CLK_CLKSEL_SHIFT) /* IDIVD */
+#  define BASE_VADC_CLKSEL_IDIVE        (16 << BASE_VADC_CLK_CLKSEL_SHIFT) /* IDIVE */
+                                                 /* Bits 29-31:  Reserved */
+/* Output stage 14 control register (BASE_SSP0_CLK) */
+/* NOTE: Clocks 4-19 are identical */
+
+#define BASE_SSP0_CLK_PD                (1 << 0)  /* Bit 0:  Output stage power down */
+                                                  /* Bits 1-10: Reserved */
+#define BASE_SSP0_CLK_AUTOBLOCK         (1 << 11) /* Bit 11: Block clock during frequency change */
+                                                  /* Bits 12-23: Reserved */
+#define BASE_SSP0_CLK_CLKSEL_SHIFT      (24)      /* Bits 24-28: Clock source selection */
+#define BASE_SSP0_CLK_CLKSEL_MASK       (31 << BASE_SSP0_CLK_CLKSEL_SHIFT)
+#  define BASE_SSP0_CLKSEL_32KHZOSC     (0 << BASE_SSP0_CLK_CLKSEL_SHIFT)  /* 32 kHz oscillator */
+#  define BASE_SSP0_CLKSEL_IRC          (1 << BASE_SSP0_CLK_CLKSEL_SHIFT)  /* IRC (default) */
+#  define BASE_SSP0_CLKSEL_ENET_RXCLK   (2 << BASE_SSP0_CLK_CLKSEL_SHIFT)  /* ENET_RX_CLK */
+#  define BASE_SSP0_CLKSEL_ENET_TXCLK   (3 << BASE_SSP0_CLK_CLKSEL_SHIFT)  /* ENET_TX_CLK */
+#  define BASE_SSP0_CLKSEL_GPCLKIN      (4 << BASE_SSP0_CLK_CLKSEL_SHIFT)  /* GP_CLKIN */
+#  define BASE_SSP0_CLKSEL_XTAL         (6 << BASE_SSP0_CLK_CLKSEL_SHIFT)  /* Crystal oscillator */
+#  define BASE_SSP0_CLKSEL_PLL0AUDIO    (8 << BASE_SSP0_CLK_CLKSEL_SHIFT)  /* PLL0AUDIO */
+#  define BASE_SSP0_CLKSEL_PLL1         (9 << BASE_SSP0_CLK_CLKSEL_SHIFT)  /* PLL1 */
+#  define BASE_SSP0_CLKSEL_IDIVA        (12 << BASE_SSP0_CLK_CLKSEL_SHIFT) /* IDIVA */
+#  define BASE_SSP0_CLKSEL_IDIVB        (13 << BASE_SSP0_CLK_CLKSEL_SHIFT) /* IDIVB */
+#  define BASE_SSP0_CLKSEL_IDIVC        (14 << BASE_SSP0_CLK_CLKSEL_SHIFT) /* IDIVC */
+#  define BASE_SSP0_CLKSEL_IDIVD        (15 << BASE_SSP0_CLK_CLKSEL_SHIFT) /* IDIVD */
+#  define BASE_SSP0_CLKSEL_IDIVE        (16 << BASE_SSP0_CLK_CLKSEL_SHIFT) /* IDIVE */
+                                                 /* Bits 29-31:  Reserved */
+/* Output stage 15 control register (BASE_SSP1_CLK) */
+/* NOTE: Clocks 4-19 are identical */
+
+#define BASE_SSP1_CLK_PD                (1 << 0)  /* Bit 0:  Output stage power down */
+                                                  /* Bits 1-10: Reserved */
+#define BASE_SSP1_CLK_AUTOBLOCK         (1 << 11) /* Bit 11: Block clock during frequency change */
+                                                  /* Bits 12-23: Reserved */
+#define BASE_SSP1_CLK_CLKSEL_SHIFT      (24)      /* Bits 24-28: Clock source selection */
+#define BASE_SSP1_CLK_CLKSEL_MASK       (31 << BASE_SSP1_CLK_CLKSEL_SHIFT)
+#  define BASE_SSP1_CLKSEL_32KHZOSC     (0 << BASE_SSP1_CLK_CLKSEL_SHIFT)  /* 32 kHz oscillator */
+#  define BASE_SSP1_CLKSEL_IRC          (1 << BASE_SSP1_CLK_CLKSEL_SHIFT)  /* IRC (default) */
+#  define BASE_SSP1_CLKSEL_ENET_RXCLK   (2 << BASE_SSP1_CLK_CLKSEL_SHIFT)  /* ENET_RX_CLK */
+#  define BASE_SSP1_CLKSEL_ENET_TXCLK   (3 << BASE_SSP1_CLK_CLKSEL_SHIFT)  /* ENET_TX_CLK */
+#  define BASE_SSP1_CLKSEL_GPCLKIN      (4 << BASE_SSP1_CLK_CLKSEL_SHIFT)  /* GP_CLKIN */
+#  define BASE_SSP1_CLKSEL_XTAL         (6 << BASE_SSP1_CLK_CLKSEL_SHIFT)  /* Crystal oscillator */
+#  define BASE_SSP1_CLKSEL_PLL0AUDIO    (8 << BASE_SSP1_CLK_CLKSEL_SHIFT)  /* PLL0AUDIO */
+#  define BASE_SSP1_CLKSEL_PLL1         (9 << BASE_SSP1_CLK_CLKSEL_SHIFT)  /* PLL1 */
+#  define BASE_SSP1_CLKSEL_IDIVA        (12 << BASE_SSP1_CLK_CLKSEL_SHIFT) /* IDIVA */
+#  define BASE_SSP1_CLKSEL_IDIVB        (13 << BASE_SSP1_CLK_CLKSEL_SHIFT) /* IDIVB */
+#  define BASE_SSP1_CLKSEL_IDIVC        (14 << BASE_SSP1_CLK_CLKSEL_SHIFT) /* IDIVC */
+#  define BASE_SSP1_CLKSEL_IDIVD        (15 << BASE_SSP1_CLK_CLKSEL_SHIFT) /* IDIVD */
+#  define BASE_SSP1_CLKSEL_IDIVE        (16 << BASE_SSP1_CLK_CLKSEL_SHIFT) /* IDIVE */
+                                                /* Bits 29-31:  Reserved */
+/* Output stage 16 control register (BASE_USART0_CLK) */
+/* NOTE: Clocks 4-19 are identical */
+
+#define BASE_USART0_CLK_PD              (1 << 0)  /* Bit 0:  Output stage power down */
+                                                  /* Bits 1-10: Reserved */
+#define BASE_USART0_CLK_AUTOBLOCK       (1 << 11) /* Bit 11: Block clock during frequency change */
+                                                 /* Bits 12-23: Reserved */
+#define BASE_USART0_CLK_CLKSEL_SHIFT    (24)      /* Bits 24-28: Clock source selection */
+#define BASE_USART0_CLK_CLKSEL_MASK     (31 << BASE_USART0_CLK_CLKSEL_SHIFT)
+#  define BASE_USART0_CLKSEL_32KHZOSC   (0 << BASE_USART0_CLK_CLKSEL_SHIFT)  /* 32 kHz oscillator */
+#  define BASE_USART0_CLKSEL_IRC        (1 << BASE_USART0_CLK_CLKSEL_SHIFT)  /* IRC (default) */
+#  define BASE_USART0_CLKSEL_ENET_RXCLK (2 << BASE_USART0_CLK_CLKSEL_SHIFT)  /* ENET_RX_CLK */
+#  define BASE_USART0_CLKSEL_ENET_TXCLK (3 << BASE_USART0_CLK_CLKSEL_SHIFT)  /* ENET_TX_CLK */
+#  define BASE_USART0_CLKSEL_GPCLKIN    (4 << BASE_USART0_CLK_CLKSEL_SHIFT)  /* GP_CLKIN */
+#  define BASE_USART0_CLKSEL_XTAL       (6 << BASE_USART0_CLK_CLKSEL_SHIFT)  /* Crystal oscillator */
+#  define BASE_USART0_CLKSEL_PLL0AUDIO  (8 << BASE_USART0_CLK_CLKSEL_SHIFT)  /* PLL0AUDIO */
+#  define BASE_USART0_CLKSEL_PLL1       (9 << BASE_USART0_CLK_CLKSEL_SHIFT)  /* PLL1 */
+#  define BASE_USART0_CLKSEL_IDIVA      (12 << BASE_USART0_CLK_CLKSEL_SHIFT) /* IDIVA */
+#  define BASE_USART0_CLKSEL_IDIVB      (13 << BASE_USART0_CLK_CLKSEL_SHIFT) /* IDIVB */
+#  define BASE_USART0_CLKSEL_IDIVC      (14 << BASE_USART0_CLK_CLKSEL_SHIFT) /* IDIVC */
+#  define BASE_USART0_CLKSEL_IDIVD      (15 << BASE_USART0_CLK_CLKSEL_SHIFT) /* IDIVD */
+#  define BASE_USART0_CLKSEL_IDIVE      (16 << BASE_USART0_CLK_CLKSEL_SHIFT) /* IDIVE */
+                                                /* Bits 29-31:  Reserved */
+/* Output stage 17 control register (BASE_UART1_CLK) */
+/* NOTE: Clocks 4-19 are identical */
+
+#define BASE_UART1_CLK_PD               (1 << 0)  /* Bit 0:  Output stage power down */
+                                                  /* Bits 1-10: Reserved */
+#define BASE_UART1_CLK_AUTOBLOCK        (1 << 11) /* Bit 11: Block clock during frequency change */
+                                                 /* Bits 12-23: Reserved */
+#define BASE_UART1_CLK_CLKSEL_SHIFT     (24)      /* Bits 24-28: Clock source selection */
+#define BASE_UART1_CLK_CLKSEL_MASK      (31 << BASE_UART1_CLK_CLKSEL_SHIFT)
+#  define BASE_UART1_CLKSEL_32KHZOSC    (0 << BASE_UART1_CLK_CLKSEL_SHIFT)  /* 32 kHz oscillator */
+#  define BASE_UART1_CLKSEL_IRC         (1 << BASE_UART1_CLK_CLKSEL_SHIFT)  /* IRC (default) */
+#  define BASE_UART1_CLKSEL_ENET_RXCLK  (2 << BASE_UART1_CLK_CLKSEL_SHIFT)  /* ENET_RX_CLK */
+#  define BASE_UART1_CLKSEL_ENET_TXCLK  (3 << BASE_UART1_CLK_CLKSEL_SHIFT)  /* ENET_TX_CLK */
+#  define BASE_UART1_CLKSEL_GPCLKIN     (4 << BASE_UART1_CLK_CLKSEL_SHIFT)  /* GP_CLKIN */
+#  define BASE_UART1_CLKSEL_XTAL        (6 << BASE_UART1_CLK_CLKSEL_SHIFT)  /* Crystal oscillator */
+#  define BASE_UART1_CLKSEL_PLL0AUDIO   (8 << BASE_UART1_CLK_CLKSEL_SHIFT)  /* PLL0AUDIO */
+#  define BASE_UART1_CLKSEL_PLL1        (9 << BASE_UART1_CLK_CLKSEL_SHIFT)  /* PLL1 */
+#  define BASE_UART1_CLKSEL_IDIVA       (12 << BASE_UART1_CLK_CLKSEL_SHIFT) /* IDIVA */
+#  define BASE_UART1_CLKSEL_IDIVB       (13 << BASE_UART1_CLK_CLKSEL_SHIFT) /* IDIVB */
+#  define BASE_UART1_CLKSEL_IDIVC       (14 << BASE_UART1_CLK_CLKSEL_SHIFT) /* IDIVC */
+#  define BASE_UART1_CLKSEL_IDIVD       (15 << BASE_UART1_CLK_CLKSEL_SHIFT) /* IDIVD */
+#  define BASE_UART1_CLKSEL_IDIVE       (16 << BASE_UART1_CLK_CLKSEL_SHIFT) /* IDIVE */
+                                                /* Bits 29-31:  Reserved */
+/* Output stage 18 control register (BASE_USART2_CLK) */
+/* NOTE: Clocks 4-19 are identical */
+
+#define BASE_USART2_CLK_PD              (1 << 0)  /* Bit 0:  Output stage power down */
+                                                 /* Bits 1-10: Reserved */
+#define BASE_USART2_CLK_AUTOBLOCK       (1 << 11) /* Bit 11: Block clock during frequency change */
+                                                 /* Bits 12-23: Reserved */
+#define BASE_USART2_CLK_CLKSEL_SHIFT    (24)      /* Bits 24-28: Clock source selection */
+#define BASE_USART2_CLK_CLKSEL_MASK     (31 << BASE_USART2_CLK_CLKSEL_SHIFT)
+#  define BASE_USART2_CLKSEL_32KHZOSC   (0 << BASE_USART2_CLK_CLKSEL_SHIFT)  /* 32 kHz oscillator */
+#  define BASE_USART2_CLKSEL_IRC        (1 << BASE_USART2_CLK_CLKSEL_SHIFT)  /* IRC (default) */
+#  define BASE_USART2_CLKSEL_ENET_RXCLK (2 << BASE_USART2_CLK_CLKSEL_SHIFT)  /* ENET_RX_CLK */
+#  define BASE_USART2_CLKSEL_ENET_TXCLK (3 << BASE_USART2_CLK_CLKSEL_SHIFT)  /* ENET_TX_CLK */
+#  define BASE_USART2_CLKSEL_GPCLKIN    (4 << BASE_USART2_CLK_CLKSEL_SHIFT)  /* GP_CLKIN */
+#  define BASE_USART2_CLKSEL_XTAL       (6 << BASE_USART2_CLK_CLKSEL_SHIFT)  /* Crystal oscillator */
+#  define BASE_USART2_CLKSEL_PLL0AUDIO  (8 << BASE_USART2_CLK_CLKSEL_SHIFT)  /* PLL0AUDIO */
+#  define BASE_USART2_CLKSEL_PLL1       (9 << BASE_USART2_CLK_CLKSEL_SHIFT)  /* PLL1 */
+#  define BASE_USART2_CLKSEL_IDIVA      (12 << BASE_USART2_CLK_CLKSEL_SHIFT) /* IDIVA */
+#  define BASE_USART2_CLKSEL_IDIVB      (13 << BASE_USART2_CLK_CLKSEL_SHIFT) /* IDIVB */
+#  define BASE_USART2_CLKSEL_IDIVC      (14 << BASE_USART2_CLK_CLKSEL_SHIFT) /* IDIVC */
+#  define BASE_USART2_CLKSEL_IDIVD      (15 << BASE_USART2_CLK_CLKSEL_SHIFT) /* IDIVD */
+#  define BASE_USART2_CLKSEL_IDIVE      (16 << BASE_USART2_CLK_CLKSEL_SHIFT) /* IDIVE */
+                                                /* Bits 29-31:  Reserved */
+/* Output stage 19 control register (BASE_USART3_CLK) */
+/* NOTE: Clocks 4-19 are identical */
+
+#define BASE_USART3_CLK_PD              (1 << 0)  /* Bit 0:  Output stage power down */
+                                                 /* Bits 1-10: Reserved */
+#define BASE_USART3_CLK_AUTOBLOCK       (1 << 11) /* Bit 11: Block clock during frequency change */
+                                                 /* Bits 12-23: Reserved */
+#define BASE_USART3_CLK_CLKSEL_SHIFT    (24)      /* Bits 24-28: Clock source selection */
+#define BASE_USART3_CLK_CLKSEL_MASK     (31 << BASE_USART3_CLK_CLKSEL_SHIFT)
+#  define BASE_USART3_CLKSEL_32KHZOSC   (0 << BASE_USART3_CLK_CLKSEL_SHIFT)  /* 32 kHz oscillator */
+#  define BASE_USART3_CLKSEL_IRC        (1 << BASE_USART3_CLK_CLKSEL_SHIFT)  /* IRC (default) */
+#  define BASE_USART3_CLKSEL_ENET_RXCLK (2 << BASE_USART3_CLK_CLKSEL_SHIFT)  /* ENET_RX_CLK */
+#  define BASE_USART3_CLKSEL_ENET_TXCLK (3 << BASE_USART3_CLK_CLKSEL_SHIFT)  /* ENET_TX_CLK */
+#  define BASE_USART3_CLKSEL_GPCLKIN    (4 << BASE_USART3_CLK_CLKSEL_SHIFT)  /* GP_CLKIN */
+#  define BASE_USART3_CLKSEL_XTAL       (6 << BASE_USART3_CLK_CLKSEL_SHIFT)  /* Crystal oscillator */
+#  define BASE_USART3_CLKSEL_PLL0AUDIO  (8 << BASE_USART3_CLK_CLKSEL_SHIFT)  /* PLL0AUDIO */
+#  define BASE_USART3_CLKSEL_PLL1       (9 << BASE_USART3_CLK_CLKSEL_SHIFT)  /* PLL1 */
+#  define BASE_USART3_CLKSEL_IDIVA      (12 << BASE_USART3_CLK_CLKSEL_SHIFT) /* IDIVA */
+#  define BASE_USART3_CLKSEL_IDIVB      (13 << BASE_USART3_CLK_CLKSEL_SHIFT) /* IDIVB */
+#  define BASE_USART3_CLKSEL_IDIVC      (14 << BASE_USART3_CLK_CLKSEL_SHIFT) /* IDIVC */
+#  define BASE_USART3_CLKSEL_IDIVD      (15 << BASE_USART3_CLK_CLKSEL_SHIFT) /* IDIVD */
+#  define BASE_USART3_CLKSEL_IDIVE      (16 << BASE_USART3_CLK_CLKSEL_SHIFT) /* IDIVE */
+                                                /* Bits 29-31:  Reserved */
+/* Output stage 20 control register (BASE_OUT_CLK) */
+
+#define BASE_OUT_CLK_PD                 (1 << 0)  /* Bit 0:  Output stage power down */
+                                                  /* Bits 1-10: Reserved */
+#define BASE_OUT_CLK_AUTOBLOCK          (1 << 11) /* Bit 11: Block clock during frequency change */
+                                                  /* Bits 12-23: Reserved */
+#define BASE_OUT_CLK_CLKSEL_SHIFT       (24)      /* Bits 24-28: Clock source selection */
+#define BASE_OUT_CLK_CLKSEL_MASK        (31 << BASE_OUT_CLK_CLKSEL_SHIFT)
+#  define BASE_OUT_CLKSEL_32KHZOSC      (0 << BASE_OUT_CLK_CLKSEL_SHIFT)  /* 32 kHz oscillator */
+#  define BASE_OUT_CLKSEL_IRC           (1 << BASE_OUT_CLK_CLKSEL_SHIFT)  /* IRC (default) */
+#  define BASE_OUT_CLKSEL_ENET_RXCLK    (2 << BASE_OUT_CLK_CLKSEL_SHIFT)  /* ENET_RX_CLK */
+#  define BASE_OUT_CLKSEL_ENET_TXCLK    (3 << BASE_OUT_CLK_CLKSEL_SHIFT)  /* ENET_TX_CLK */
+#  define BASE_OUT_CLKSEL_GPCLKIN       (4 << BASE_OUT_CLK_CLKSEL_SHIFT)  /* GP_CLKIN */
+#  define BASE_OUT_CLKSEL_XTAL          (6 << BASE_OUT_CLK_CLKSEL_SHIFT)  /* Crystal oscillator */
+#  define BASE_OUT_CLKSEL_PLL0USB       (7 << BASE_OUT_CLK_CLKSEL_SHIFT)  /* PLL0USB */
+#  define BASE_OUT_CLKSEL_PLL0AUDIO     (8 << BASE_OUT_CLK_CLKSEL_SHIFT)  /* PLL0AUDIO */
+#  define BASE_OUT_CLKSEL_PLL1          (9 << BASE_OUT_CLK_CLKSEL_SHIFT)  /* PLL1 */
+#  define BASE_OUT_CLKSEL_IDIVA         (12 << BASE_OUT_CLK_CLKSEL_SHIFT) /* IDIVA */
+#  define BASE_OUT_CLKSEL_IDIVB         (13 << BASE_OUT_CLK_CLKSEL_SHIFT) /* IDIVB */
+#  define BASE_OUT_CLKSEL_IDIVC         (14 << BASE_OUT_CLK_CLKSEL_SHIFT) /* IDIVC */
+#  define BASE_OUT_CLKSEL_IDIVD         (15 << BASE_OUT_CLK_CLKSEL_SHIFT) /* IDIVD */
+#  define BASE_OUT_CLKSEL_IDIVE         (16 << BASE_OUT_CLK_CLKSEL_SHIFT) /* IDIVE */
+                                                 /* Bits 29-31:  Reserved */
+/* Output stage 25 control register (BASE_APLL_CLK) */
+
+#define BASE_APLL_CLK_PD                (1 << 0)  /* Bit 0:  Output stage power down */
+                                                  /* Bits 1-10: Reserved */
+#define BASE_APLL_CLK_AUTOBLOCK         (1 << 11) /* Bit 11: Block clock during frequency change */
+                                                  /* Bits 12-23: Reserved */
+#define BASE_APLL_CLK_CLKSEL_SHIFT      (24)      /* Bits 24-28: Clock source selection */
+#define BASE_APLL_CLK_CLKSEL_MASK       (31 << BASE_APLL_CLK_CLKSEL_SHIFT)
+#  define BASE_APLL_CLKSEL_32KHZOSC     (0 << BASE_APLL_CLK_CLKSEL_SHIFT)  /* 32 kHz oscillator */
+#  define BASE_APLL_CLKSEL_IRC          (1 << BASE_APLL_CLK_CLKSEL_SHIFT)  /* IRC (default) */
+#  define BASE_APLL_CLKSEL_ENET_RXCLK   (2 << BASE_APLL_CLK_CLKSEL_SHIFT)  /* ENET_RX_CLK */
+#  define BASE_APLL_CLKSEL_ENET_TXCLK   (3 << BASE_APLL_CLK_CLKSEL_SHIFT)  /* ENET_TX_CLK */
+#  define BASE_APLL_CLKSEL_GPCLKIN      (4 << BASE_APLL_CLK_CLKSEL_SHIFT)  /* GP_CLKIN */
+#  define BASE_APLL_CLKSEL_XTAL         (6 << BASE_APLL_CLK_CLKSEL_SHIFT)  /* Crystal oscillator */
+#  define BASE_APLL_CLKSEL_PLL0AUDIO    (8 << BASE_APLL_CLK_CLKSEL_SHIFT)  /* PLL0AUDIO */
+#  define BASE_APLL_CLKSEL_PLL1         (9 << BASE_APLL_CLK_CLKSEL_SHIFT)  /* PLL1 */
+#  define BASE_APLL_CLKSEL_IDIVA        (12 << BASE_APLL_CLK_CLKSEL_SHIFT) /* IDIVA */
+#  define BASE_APLL_CLKSEL_IDIVB        (13 << BASE_APLL_CLK_CLKSEL_SHIFT) /* IDIVB */
+#  define BASE_APLL_CLKSEL_IDIVC        (14 << BASE_APLL_CLK_CLKSEL_SHIFT) /* IDIVC */
+#  define BASE_APLL_CLKSEL_IDIVD        (15 << BASE_APLL_CLK_CLKSEL_SHIFT) /* IDIVD */
+#  define BASE_APLL_CLKSEL_IDIVE        (16 << BASE_APLL_CLK_CLKSEL_SHIFT) /* IDIVE */
+                                                 /* Bits 29-31:  Reserved */
+/* Output stage 26/27 control register (BASE_CGU_OUT0/1_CLK) */
+/* NOTE: Clocks 26-27 are identical */
+
+#define BASE_CGU_CLK_PD                 (1 << 0)  /* Bit 0:  Output stage power down */
+                                                  /* Bits 1-10: Reserved */
+#define BASE_CGU_CLK_AUTOBLOCK          (1 << 11) /* Bit 11: Block clock during frequency change */
+                                                  /* Bits 12-23: Reserved */
+#define BASE_CGU_CLK_CLKSEL_SHIFT       (24)      /* Bits 24-28: Clock source selection */
+#define BASE_CGU_CLK_CLKSEL_MASK        (31 << BASE_CGU_CLK_CLKSEL_SHIFT)
+#  define BASE_CGU_CLKSEL_32KHZOSC      (0 << BASE_CGU_CLK_CLKSEL_SHIFT)  /* 32 kHz oscillator */
+#  define BASE_CGU_CLKSEL_IRC           (1 << BASE_CGU_CLK_CLKSEL_SHIFT)  /* IRC (default) */
+#  define BASE_CGU_CLKSEL_ENET_RXCLK    (2 << BASE_CGU_CLK_CLKSEL_SHIFT)  /* ENET_RX_CLK */
+#  define BASE_CGU_CLKSEL_ENET_TXCLK    (3 << BASE_CGU_CLK_CLKSEL_SHIFT)  /* ENET_TX_CLK */
+#  define BASE_CGU_CLKSEL_GPCLKIN       (4 << BASE_CGU_CLK_CLKSEL_SHIFT)  /* GP_CLKIN */
+#  define BASE_CGU_CLKSEL_XTAL          (6 << BASE_CGU_CLK_CLKSEL_SHIFT)  /* Crystal oscillator */
+#  define BASE_CGU_CLKSEL_PLL0USB       (7 << BASE_CGU_CLK_CLKSEL_SHIFT)  /* PLL0USB */
+#  define BASE_CGU_CLKSEL_PLL0AUDIO     (8 << BASE_CGU_CLK_CLKSEL_SHIFT)  /* PLL0AUDIO */
+#  define BASE_CGU_CLKSEL_PLL1          (9 << BASE_CGU_CLK_CLKSEL_SHIFT)  /* PLL1 */
+#  define BASE_CGU_CLKSEL_IDIVA         (12 << BASE_CGU_CLK_CLKSEL_SHIFT) /* IDIVA */
+#  define BASE_CGU_CLKSEL_IDIVB         (13 << BASE_CGU_CLK_CLKSEL_SHIFT) /* IDIVB */
+#  define BASE_CGU_CLKSEL_IDIVC         (14 << BASE_CGU_CLK_CLKSEL_SHIFT) /* IDIVC */
+#  define BASE_CGU_CLKSEL_IDIVD         (15 << BASE_CGU_CLK_CLKSEL_SHIFT) /* IDIVD */
+#  define BASE_CGU_CLKSEL_IDIVE         (16 << BASE_CGU_CLK_CLKSEL_SHIFT) /* IDIVE */
+                                                 /* Bits 29-31:  Reserved */
+
+/****************************************************************************************************
+ * Public Types
+ ****************************************************************************************************/
+
+/****************************************************************************************************
+ * Public Data
+ ****************************************************************************************************/
+
+/****************************************************************************************************
+ * Public Functions
+ ****************************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_CGU_H */
diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_creg.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_creg.h
new file mode 100644
index 000000000..61a62e694
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_creg.h
@@ -0,0 +1,291 @@
+/************************************************************************************
+ * arch/arm/src/lpc43xx/chip/lpc43_creg.h
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_CREG_H
+#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_CREG_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+/* Register Offsets *****************************************************************/
+
+#define LPC43_CREG0_OFFSET            0x0004 /* Chip configuration register 0 */
+#define LPC43_CREG_M4MEMMAP_OFFSET    0x0100 /* ARM Cortex-M4 memory mapping */
+#define LPC43_CREG1_OFFSET            0x0108 /* Chip configuration register 1 */
+#define LPC43_CREG2_OFFSET            0x010c /* Chip configuration register 2 */
+#define LPC43_CREG3_OFFSET            0x0110 /* Chip configuration register 3 */
+#define LPC43_CREG4_OFFSET            0x0114 /* Chip configuration register 4 */
+#define LPC43_CREG5_OFFSET            0x0118 /* Chip configuration register 5 */
+#define LPC43_CREG_DMAMUX_OFFSET      0x011c /* DMA mux control */
+#define LPC43_CREG_FLASHCFGA_OFFSET   0x0120 /* Flash accelerator bank A configuration */
+#define LPC43_CREG_FLASHCFGB_OFFSET   0x0124 /* Flash accelerator bankd B configuration */
+#define LPC43_CREG_ETBCFG_OFFSET      0x0128 /* ETB RAM configuration */
+#define LPC43_CREG6_OFFSET            0x012c /* Chip configuration register 6 */
+#define LPC43_CREG_M4TXEVENT_OFFSET   0x0130 /* Cortex-M4 TXEV event clear 0 */
+#define LPC43_CREG_CHIPID_OFFSET      0x0200 /* Part ID */
+#define LPC43_CREG_M0TXEVENT_OFFSET   0x0400 /* Cortex-M0 TXEV event clear */
+#define LPC43_CREG_M0APPMEMMAP_OFFSET 0x0404 /* ARM Cortex-M0 memory mapping */
+#define LPC43_CREG_USB0FLADJ_OFFSET   0x0500 /* USB0 frame length adjust */
+#define LPC43_CREG_USB1FLADJ_OFFSET   0x0600 /* USB1 frame length adjust */
+
+/* Register Addresses ***************************************************************/
+
+#define LPC43_CREG0                   (LPC43_CREG_BASE+LPC43_CREG0_OFFSET)
+#define LPC43_CREG_M4MEMMAP           (LPC43_CREG_BASE+LPC43_CREG_M4MEMMAP_OFFSET)
+#define LPC43_CREG1                   (LPC43_CREG_BASE+LPC43_CREG1_OFFSET)
+#define LPC43_CREG2                   (LPC43_CREG_BASE+LPC43_CREG2_OFFSET)
+#define LPC43_CREG3                   (LPC43_CREG_BASE+LPC43_CREG3_OFFSET)
+#define LPC43_CREG4                   (LPC43_CREG_BASE+LPC43_CREG4_OFFSET)
+#define LPC43_CREG5                   (LPC43_CREG_BASE+LPC43_CREG5_OFFSET)
+#define LPC43_CREG_DMAMUX             (LPC43_CREG_BASE+LPC43_CREG_DMAMUX_OFFSET)
+#define LPC43_CREG_FLASHCFGA          (LPC43_CREG_BASE+LPC43_CREG_FLASHCFGA_OFFSET)
+#define LPC43_CREG_FLASHCFGB          (LPC43_CREG_BASE+LPC43_CREG_FLASHCFGB_OFFSET)
+#define LPC43_CREG_ETBCFG             (LPC43_CREG_BASE+LPC43_CREG_ETBCFG_OFFSET)
+#define LPC43_CREG6                   (LPC43_CREG_BASE+LPC43_CREG6_OFFSET)
+#define LPC43_CREG_M4TXEVENT          (LPC43_CREG_BASE+LPC43_CREG_M4TXEVENT_OFFSET)
+#define LPC43_CREG_CHIPID             (LPC43_CREG_BASE+LPC43_CREG_CHIPID_OFFSET)
+#define LPC43_CREG_M0TXEVENT          (LPC43_CREG_BASE+LPC43_CREG_M0TXEVENT_OFFSET)
+#define LPC43_CREG_M0APPMEMMAP        (LPC43_CREG_BASE+LPC43_CREG_M0APPMEMMAP_OFFSET)
+#define LPC43_CREG_USB0FLADJ          (LPC43_CREG_BASE+LPC43_CREG_USB0FLADJ_OFFSET)
+#define LPC43_CREG_USB1FLADJ          (LPC43_CREG_BASE+LPC43_CREG_USB1FLADJ_OFFSET)
+
+/* Register Bit Definitions *********************************************************/
+
+/* Chip configuration register 0 */
+
+#define CREG0_EN1KHZ                  (1 << 0)  /* Bit 0:  Enable 1 kHz output */
+#define CREG0_EN32KHZ                 (1 << 1)  /* Bit 1:  Enable 32 kHz output */
+#define CREG0_RESET32KHZ              (1 << 2)  /* Bit 2:  32 kHz oscillator reset */
+#define CREG0_PD32KHZ                 (1 << 3)  /* Bit 3:  32 kHz power control */
+                                                /* Bit 4:  Reserved */
+#define CREG0_USB0PHY                 (1 << 5)  /* Bit 5:  USB0 PHY power control */
+#define CREG0_ALARMCTRL_SHIFT         (6)       /* Bits 6-7: RTC_ALARM pin output control 0 R/W */
+#define CREG0_ALARMCTRL_MASK          (3 << CREG0_ALARMCTRL_SHIFT)
+#  define CREG0_ALARMCTRL_RTC         (0 << CREG0_ALARMCTRL_SHIFT) /* RTC alarm */
+#  define CREG0_ALARMCTRL_EVENT       (1 << CREG0_ALARMCTRL_SHIFT) /* Event router event */
+#  define CREG0_ALARMCTRL_INACTIVE    (3 << CREG0_ALARMCTRL_SHIFT) /* Inactive */
+#define CREG0_BODLVL1_SHIFT           (8)       /* Bits 8-9: BOD trip level to generate an interrupt */
+#define CREG0_BODLVL1_MASK            (3 << CREG0_BODLVL1_SHIFT)
+#  define CREG0_BODLVL1_LEVEL0        (0 << CREG0_BODLVL1_SHIFT) /* Level 0 interrupt */
+#  define CREG0_BODLVL1_LEVEL1        (1 << CREG0_BODLVL1_SHIFT) /* Level 1 interrupt */
+#  define CREG0_BODLVL1_LEVEL2        (2 << CREG0_BODLVL1_SHIFT) /* Level 2 interrupt */
+#  define CREG0_BODLVL1_LEVEL3        (3 << CREG0_BODLVL1_SHIFT) /* Level 3 interrupt */
+#define CREG0_BODLVL2_SHIFT           (10)      /* Bits 10-11: BOD trip level to generate a reset */
+#define CREG0_BODLVL2_MASK            (3 << CREG0_BODLVL2_SHIFT)
+#  define CREG0_BODLVL2_LEVEL0        (0 << CREG0_BODLVL2_SHIFT) /* Level 0 reset */
+#  define CREG0_BODLVL2_LEVEL1        (1 << CREG0_BODLVL2_SHIFT) /* Level 1 reset */
+#  define CREG0_BODLVL2_LEVEL2        (2 << CREG0_BODLVL2_SHIFT) /* Level 2 reset */
+#  define CREG0_BODLVL2_LEVEL3        (3 << CREG0_BODLVL2_SHIFT) /* Level 3 reset */
+#define CREG0_SAMPLECTRL_SHIFT        (12)      /* Bits 12-13:  SAMPLE pin input/output control */
+#define CREG0_SAMPLECTRL_MASK         (3 << CREG0_SAMPLECTRL_SHIFT)
+#  define CREG0_SAMPLECTRL_MONITOR    (1 << CREG0_SAMPLECTRL_SHIFT) /* Output from event monitor/recorder */
+#  define CREG0_SAMPLECTRL_EVNTRTR    (2 << CREG0_SAMPLECTRL_SHIFT) /* Output from the event router */
+#define CREG0_WAKEUP0CTRL_SHIFT       (14)      /* Bits 14-15: WAKEUP0 pin input/output control */
+#define CREG0_WAKEUP0CTRL_MASK        (3 << CREG0_WAKEUP0CTRL_SHIFT)
+#  define CREG0_WAKEUP0CTRL_EVNTIN    (0 << CREG0_WAKEUP0CTRL_SHIFT) /* Input to the event router */
+#  define CREG0_WAKEUP0CTRL_EVNTOUT   (1 << CREG0_WAKEUP0CTRL_SHIFT) /* Output from the event router */
+#  define CREG0_WAKEUP0CTRL_EVNTIN2   (3 << CREG0_WAKEUP0CTRL_SHIFT) /* Input to the event router */
+#define CREG0_WAKEUP1CTRL_SHIFT       (16)      /* Bits 16-17: WAKEUP1 pin input/output control */
+#define CREG0_WAKEUP1CTRL_MASK        (3 << CREG0_WAKEUP1CTRL_SHIFT)
+#  define CREG0_WAKEUP1CTRL_EVNTIN    (0 << CREG0_WAKEUP1CTRL_SHIFT) /* Input to the event router */
+#  define CREG0_WAKEUP1CTRL_EVNTOUT   (1 << CREG0_WAKEUP1CTRL_SHIFT) /* Output from the event router */
+#  define CREG0_WAKEUP1CTRL_EVNTIN2   (3 << CREG0_WAKEUP1CTRL_SHIFT) /* Input to the event router */
+                                                /* Bits 18-31:  Reserved */
+/* ARM Cortex-M4 memory mapping */
+                                                /* Bits 0-11:  Reserved */
+#define CREG_M4MEMMAP_SHIFT           (12)      /* Bits 12-31: M4MAP Shadow address */
+#define CREG_M4MEMMAP_MASK            (0x000fffff << CREG_M4MEMMAP_SHIFT)
+
+/* Chip configuration register 1-4.  Bit definitions not provided in the user manual */
+
+/* Chip configuration register 5 */
+                                                /* Bits 0-5:  Reserved */
+#define CREG5_M4TAPSEL                (1 << 6)  /* Bit 6:  JTAG debug select for M4 core */
+                                                /* Bits 7-8:  Reserved */
+#define CREG5_M0APPTAPSEL             (1 << 9)  /* Bit 9:  JTAG debug select for M0 co-processor */
+                                                /* Bits 10-31:  Reserved */
+/* DMA mux control */
+
+#define CREG_DMAMUX_PER0_SHIFT        (0)       /* Bits 0-1: Selection for DMA peripheral 0 */
+#define CREG_DMAMUX_PER0_MASK         (3 << CREG_DMAMUX_PER0_SHIFT)
+#  define CREG_DMAMUX_PER0 SPIFI      (0 << CREG_DMAMUX_PER0_SHIFT) /* SPIFI */
+#  define CREG_DMAMUX_PER0_SCTM2      (1 << CREG_DMAMUX_PER0_SHIFT) /* SCT match 2 */
+#  define CREG_DMAMUX_PER0_T3M1       (3 << CREG_DMAMUX_PER0_SHIFT) /* T3 match 1 */
+#define CREG_DMAMUX_PER1_SHIFT        (2)       /* Bits 2-3: Selection for DMA peripheral 1 */
+#define CREG_DMAMUX_PER1_MASK         (3 << CREG_DMAMUX_PER1_SHIFT)
+#  define CREG_DMAMUX_PER1_T0M0       (0 << CREG_DMAMUX_PER1_SHIFT) /* Timer 0 match 0 */
+#  define CREG_DMAMUX_PER1_U0TX       (1 << CREG_DMAMUX_PER1_SHIFT) /* USART0 transmit */
+#define CREG_DMAMUX_PER2_SHIFT        (4)       /* Bits 4-5: Selection for DMA peripheral 2 */
+#define CREG_DMAMUX_PER2_MASK         (3 << CREG_DMAMUX_PER2_SHIFT)
+#  define CREG_DMAMUX_PER2_T0M1       (0 << CREG_DMAMUX_PER2_SHIFT) /* Timer 0 match 1 */
+#  define CREG_DMAMUX_PER2_U0RX       (1 << CREG_DMAMUX_PER2_SHIFT) /* USART0 receive */
+#define CREG_DMAMUX_PER3_SHIFT        (6)       /* Bits 6-7: Selection for DMA peripheral 3 */
+#define CREG_DMAMUX_PER3_MASK         (3 << CREG_DMAMUX_PER3_SHIFT)
+#  define CREG_DMAMUX_PER3_T1M0       (0 << CREG_DMAMUX_PER3_SHIFT) /* Timer 1 match 0 */
+#  define CREG_DMAMUX_PER3_U1TX       (1 << CREG_DMAMUX_PER3_SHIFT) /* UART1 transmit */
+#  define CREG_DMAMUX_PER3_I2S1D1     (2 << CREG_DMAMUX_PER3_SHIFT) /* I2S1 DMA request 1 */
+#  define CREG_DMAMUX_PER3_SSP1TX     (3 << CREG_DMAMUX_PER3_SHIFT) /* SSP1 transmit */
+#define CREG_DMAMUX_PER4_SHIFT        (8)       /* Bits 8-9: Selection for DMA peripheral 4 */
+#define CREG_DMAMUX_PER4_MASK         (3 << CREG_DMAMUX_PER4_SHIFT)
+#  define CREG_DMAMUX_PER4_T1M1       (0 << CREG_DMAMUX_PER4_SHIFT) /* Timer 1 match 1 */
+#  define CREG_DMAMUX_PER4_U1RX       (1 << CREG_DMAMUX_PER4_SHIFT) /* UART1 receive */
+#  define CREG_DMAMUX_PER4_I2S1D2     (2 << CREG_DMAMUX_PER4_SHIFT) /* I2S1 DMA request 2 */
+#  define CREG_DMAMUX_PER4_SSP1RX     (3 << CREG_DMAMUX_PER4_SHIFT) /* SSP1 receive */
+#define CREG_DMAMUX_PER5_SHIFT        (10)      /* Bits 10-11: Selection for DMA peripheral 5 */
+#define CREG_DMAMUX_PER5_MASK         (3 << CREG_DMAMUX_PER5_SHIFT)
+#  define CREG_DMAMUX_PER5_T2M0       (0 << CREG_DMAMUX_PER5_SHIFT) /* Timer 2 match 0 */
+#  define CREG_DMAMUX_PER5_U2TX       (1 << CREG_DMAMUX_PER5_SHIFT) /* USART2 transmit */
+#  define CREG_DMAMUX_PER5_SSP1TX     (2 << CREG_DMAMUX_PER5_SHIFT) /* SSP1 transmit */
+#define CREG_DMAMUX_PER6_SHIFT        (12)      /* Bits 12-13: Selection for DMA peripheral 6 */
+#define CREG_DMAMUX_PER6_MASK         (3 << CREG_DMAMUX_PER6_SHIFT)
+#  define CREG_DMAMUX_PER6_T2M1       (0 << CREG_DMAMUX_PER6_SHIFT) /* Timer 2 match 1 */
+#  define CREG_DMAMUX_PER6_U2RX       (1 << CREG_DMAMUX_PER6_SHIFT) /* USART2 receive */
+#  define CREG_DMAMUX_PER6_SSP1RX     (2 << CREG_DMAMUX_PER6_SHIFT) /* SSP1 receive */
+#define CREG_DMAMUX_PER7_SHIFT        (14)      /* Bits 14-15: Selection for DMA peripheral 7 */
+#define CREG_DMAMUX_PER7_MASK         (3 << CREG_DMAMUX_PER7_SHIFT)
+#  define CREG_DMAMUX_PER7_T3M1       (0 << CREG_DMAMUX_PER7_SHIFT) /* Timer 3 match l */
+#  define CREG_DMAMUX_PER7_U3TX       (1 << CREG_DMAMUX_PER7_SHIFT) /* USART3 transmit */
+#  define CREG_DMAMUX_PER7_SCTM0      (2 << CREG_DMAMUX_PER7_SHIFT) /* SCT match output 0 */
+#define CREG_DMAMUX_PER8_SHIFT        (16)      /* Bits 16-17: Selection for DMA peripheral 8 */
+#define CREG_DMAMUX_PER8_MASK         (3 << CREG_DMAMUX_PER8_SHIFT)
+#  define CREG_DMAMUX_PER8_T3M1       (0 << CREG_DMAMUX_PER8_SHIFT) /* Timer 3 match 1 */
+#  define CREG_DMAMUX_PER8_U3RX       (1 << CREG_DMAMUX_PER8_SHIFT) /* USART3 receive */
+#  define CREG_DMAMUX_PER8_SCTM1      (2 << CREG_DMAMUX_PER8_SHIFT) /* SCT match output 1 */
+#define CREG_DMAMUX_PER9_SHIFT        (18)      /* Bits 18-19: Selection for DMA peripheral 9 */
+#define CREG_DMAMUX_PER9_MASK         (3 << CREG_DMAMUX_PER9_SHIFT)
+#  define CREG_DMAMUX_PER9_SSP0RX     (0 << CREG_DMAMUX_PER9_SHIFT) /* SSP0 receive */
+#  define CREG_DMAMUX_PER9_I2S0D1     (1 << CREG_DMAMUX_PER9_SHIFT) /* I2S0 DMA request 1 */
+#  define CREG_DMAMUX_PER9_SCTM1      (2 << CREG_DMAMUX_PER9_SHIFT) /* SCT match output 1 */
+#define CREG_DMAMUX_PER10_SHIFT       (20)      /* Bits 20-21: Selection for DMA peripheral 10 */
+#define CREG_DMAMUX_PER10_MASK        (3 << CREG_DMAMUX_PER10_SHIFT)
+#  define CREG_DMAMUX_PER10_SSP0TX    (0 << CREG_DMAMUX_PER10_SHIFT) /* SSP0 transmit */
+#  define CREG_DMAMUX_PER10_I2S0D2    (1 << CREG_DMAMUX_PER10_SHIFT) /* I2S0 DMA request 2 */
+#  define CREG_DMAMUX_PER10_SCTM0     (2 << CREG_DMAMUX_PER10_SHIFT) /* SCT match output 0 */
+#define CREG_DMAMUX_PER11_SHIFT       (22)      /* Bits 22-23: Selection for DMA peripheral 11 */
+#define CREG_DMAMUX_PER11_MASK        (3 << CREG_DMAMUX_PER11_SHIFT)
+#  define CREG_DMAMUX_PER11_SSP1RX    (0 << CREG_DMAMUX_PER11_SHIFT) /* SSP1 receive */
+#  define CREG_DMAMUX_PER11_U0TX      (2 << CREG_DMAMUX_PER11_SHIFT) /* USART0 transmit */
+#define CREG_DMAMUX_PER12_SHIFT       (24)      /* Bits 24-25: Selection for DMA peripheral 12 */
+#define CREG_DMAMUX_PER12_MASK        (3 << CREG_DMAMUX_PER12_SHIFT)
+#  define CREG_DMAMUX_PER12_SSP1TX    (0 << CREG_DMAMUX_PER12_SHIFT) /* SSP1 transmit */
+#  define CREG_DMAMUX_PER12_U0RX      (2 << CREG_DMAMUX_PER12_SHIFT) /* USART0 receive */
+#define CREG_DMAMUX_PER13_SHIFT       (26)      /* Bits 26-27: Selection for DMA peripheral 13 */
+#define CREG_DMAMUX_PER13_MASK        (3 << CREG_DMAMUX_PER13_SHIFT)
+#  define CREG_DMAMUX_PER13_ADC0      (0 << CREG_DMAMUX_PER13_SHIFT) /* ADC0 */
+#  define CREG_DMAMUX_PER13_SSP1RX    (2 << CREG_DMAMUX_PER13_SHIFT) /* SSP1 receive */
+#  define CREG_DMAMUX_PER13_U3RX      (3 << CREG_DMAMUX_PER13_SHIFT) /* USART3 receive */
+#define CREG_DMAMUX_PER14_SHIFT       (28)      /* Bits 28-29: Selection for DMA peripheral 14 */
+#define CREG_DMAMUX_PER14_MASK        (3 << CREG_DMAMUX_PER12_SHIFT)
+#  define CREG_DMAMUX_PER14_ADC1      (0 << CREG_DMAMUX_PER14_SHIFT) /* ADC1 */
+#  define CREG_DMAMUX_PER14_SSP1TX    (2 << CREG_DMAMUX_PER14_SHIFT) /* SSP1 transmit */
+#  define CREG_DMAMUX_PER14_U3TX      (3 << CREG_DMAMUX_PER14_SHIFT) /* USART3 transmit */
+#define CREG_DMAMUX_PER15_SHIFT       (30)      /* Bits 30-31: Selection for DMA peripheral 15 */
+#define CREG_DMAMUX_PER15_MASK        (3 << CREG_DMAMUX_PER15_SHIFT)
+#  define CREG_DMAMUX_PER15_DAC       (0 << CREG_DMAMUX_PER15_SHIFT) /* DAC */
+#  define CREG_DMAMUX_PER15_SCTM3     (1 << CREG_DMAMUX_PER15_SHIFT) /* SCT match output 3 */
+#  define CREG_DMAMUX_PER15_T3M0      (3 << CREG_DMAMUX_PER15_SHIFT) /* Timer 3 match 0 */
+
+/* Flash accelerator bank A/B configuration */
+                                                /* Bits 0-11:  Reserved */
+#define CREG_FLASHCFG_FLASHTIM_SHIFT  (12)      /* Bits 12-15: Flash access time */
+#define CREG_FLASHCFG_FLASHTIM_MASK   (15 << CREG_FLASHCFG_FLASHTIM_SHIFT)
+#  define CREG_FLASHCFG_FLASHTIM(n)   (((n)-1) << CREG_FLASHCFG_FLASHTIM_SHIFT) /* n BASE_M4_CLK clocks, n=1..10 */
+                                                /* Bits 16-31:  Reserved */
+#define CREG_FLASHCFG_POW             (1 << 31) /* Bit 31:  Flash bank A power control */
+
+/* ETB RAM configuration */
+
+#define CREG_ETBCFG                   (1 << 0)  /* Bit 0: Select SRAM interface */
+                                                /* Bits 1-31:  Reserved */
+/* Chip configuration register 6 */
+
+#define CREG6_ETHMODE_SHIFT           (0)       /* Bits 0-2: Selects the Ethernet mode */
+#define CREG6_ETHMODE_MASK            (7 << CREG6_ETHMODE_SHIFT)
+#  define CREG6_ETHMODE_MII           (0 << CREG6_ETHMODE_SHIFT)
+#  define CREG6_ETHMODE_RMII          (4 << CREG6_ETHMODE_SHIFT)
+                                                /* Bit 3:  Reserved */
+#define CREG6_CTOUTCTRL               (1 << 4)  /* Bit 4:  Selects the functionality of the SCT outputs */
+                                                /* Bits 5-11:  Reserved */
+#define CREG6_I2S0_TXSCK              (1 << 12) /* Bit 12:  I2S0_TX_SCK input select */
+#define CREG6_I2S0_RXSCK              (1 << 13) /* Bit 13:  I2S0_RX_SCK input select */
+#define CREG6_I2S1_TXSCK              (1 << 14) /* Bit 14:  I2S1_TX_SCK input select */
+#define CREG6_I2S1_RXSCK              (1 << 15) /* Bit 15:  I2S1_RX_SCK input select */
+#define CREG6_EMC_CLK                 (1 << 16) /* Bit 16:  EMC_CLK divided clock select */
+                                                /* Bits 17-31:  Reserved */
+/* Cortex-M4 TXEV event clear 0 */
+
+#define CREG_M4TXEVENT                (1 << 0)  /* Bit 0: Cortex-M4 TXEV event */
+                                                /* Bits 1-31:  Reserved */
+/* Part ID (32-bit ID) */
+
+#define CREG_CHIPID_FLASHLESS1        0x5906002b /* LPC4350/30/20/10 */
+#define CREG_CHIPID_FLASHLESS2        0x6906002b /* LPC4350/30/20/10 */
+#define CREG_CHIPID_FLASHPARTS        0x4906002b /* LPC4357/53 */
+
+/* Cortex-M0 TXEV event clear */
+
+#define CREG_M0TXEVENT                (1 << 0)  /* Bit 0: Cortex-M0 TXEV event */
+                                                /* Bits 1-31:  Reserved */
+/* ARM Cortex-M0 memory mapping */
+                                                /* Bits 0-11:  Reserved */
+#define CREG_M0APPMEMMAP_SHIFT        (12)      /* Bits 12-31: M4MAP Shadow address */
+#define CREG_M0APPMEMMAP_MASK         (0x000fffff << CREG_M0APPMEMMAP_SHIFT)
+
+/* USB0/1 frame length adjust */
+
+#define CREG_USBFLADJ_SHIFT           (0)       /* Bits 0-5: FLTV Frame length timing value */
+#define CREG_USBFLADJ_MASK            (0x3f << CREG_USBFLADJ_SHIFT)
+#  define CREG_USBFLADJ(n)            ((((n)-59488) >> 4) << CREG_USBFLADJ_SHIFT)
+                                                /* Bits 6-31:  Reserved */
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_CREG_H */
diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_dac.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_dac.h
new file mode 100644
index 000000000..e06ecf442
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_dac.h
@@ -0,0 +1,94 @@
+/************************************************************************************
+ * arch/arm/src/lpc43xx/lpc43_dac.h
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_DAC_H
+#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_DAC_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Register offsets *****************************************************************/
+
+#define LPC43_DAC_CR_OFFSET     0x0000 /* D/A Converter Register */
+#define LPC43_DAC_CTRL_OFFSET   0x0004 /* DAC Control register */
+#define LPC43_DAC_CNTVAL_OFFSET 0x0008 /* DAC Counter Value register */
+
+/* Register addresses ***************************************************************/
+
+#define LPC43_DAC_CR            (LPC43_DAC_BASE+LPC43_DAC_CR_OFFSET)
+#define LPC43_DAC_CTRL          (LPC43_DAC_BASE+LPC43_DAC_CTRL_OFFSET)
+#define LPC43_DAC_CNTVAL        (LPC43_DAC_BASE+LPC43_DAC_CNTVAL_OFFSET)
+
+/* Register bit definitions *********************************************************/
+
+/* D/A Converter Register */
+                                          /* Bits 0-5: Reserved */
+#define DAC_CR_VALUE_SHIFT      (6)       /* Bits 6-15: Controls voltage on the AOUT pin */
+#define DAC_CR_VALUE_MASK       (0x3ff << DAC_CR_VALUE_SHIFT)
+#define DAC_CR_BIAS             (1 << 16) /* Bit 16: Controls DAC settling time */
+                                          /* Bits 17-31: Reserved */
+/* DAC Control register */
+
+#define DAC_CTRL_INTDMAREQ      (1 << 0) /* Bit 0: Timer timed out */
+#define DAC_CTRL_DBLBUFEN       (1 << 1) /* Bit 1: Enable DACR double-buffering */
+#define DAC_CTRL_CNTEN          (1 << 2) /* Bit 2: Enable timeout counter */
+#define DAC_CTRL_DMAEN          (1 << 3) /* Bit 3: Enable DMA access */
+                                         /* Bits 4-31: Reserved */
+/* DAC Counter Value register */
+
+#define DAC_CNTVAL_SHIFT        (0)      /* Bits 0-15: Reload value for DAC interrupt/DMA timer */
+#define DAC_CNTVAL_MASK         (0xffff << DAC_CNTVAL_SHIFT)
+                                         /* Bits 8-31: Reserved */
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_DAC_H */
diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_eeprom.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_eeprom.h
new file mode 100644
index 000000000..19391d479
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_eeprom.h
@@ -0,0 +1,158 @@
+/************************************************************************************
+ * arch/arm/src/lpc43xx/chip/lpc43_eeprom.h
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_EEPROM_H
+#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_EEPROM_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+/* Register Offsets *****************************************************************/
+
+/* EEPROM registers */
+
+#define LPC43_EEPROM_CMD_OFFSET        0x000 /* EEPROM command register */
+#define LPC43_EEPROM_RWSTATE_OFFSET    0x008 /* EEPROM read wait state register */
+#define LPC43_EEPROM_AUTOPROG_OFFSET   0x00c /* EEPROM auto programming register */
+#define LPC43_EEPROM_WSTATE_OFFSET     0x010 /* EEPROM wait state register */
+#define LPC43_EEPROM_CLKDIV_OFFSET     0x014 /* EEPROM clock divider register */
+#define LPC43_EEPROM_PWRDWN_OFFSET     0x018 /* EEPROM power-down register */
+
+/* EEPROM interrupt registers */
+
+#define LPC43_EEPROM_INTENCLR_OFFSET   0xfd8 /* EEPROM interrupt enable clear */
+#define LPC43_EEPROM_INTENSET_OFFSET   0xfdc /* EEPROM interrupt enable set */
+#define LPC43_EEPROM_INTSTAT_OFFSET    0xfe0 /* EEPROM interrupt status */
+#define LPC43_EEPROM_INTEN_OFFSET      0xfe4 /* EEPROM interrupt enable */
+#define LPC43_EEPROM_INTSTATCLR_OFFSET 0xfe8 /* EEPROM interrupt status clear */
+#define LPC43_EEPROM_INTSTATSET_OFFSET 0xfec /* EEPROM interrupt status set */
+
+/* Register Addresses ***************************************************************/
+
+/* EEPROM registers */
+
+#define LPC43_EEPROM_CMD               (LPC43_EEPROMC_BASE+LPC43_EEPROM_CMD_OFFSET)
+#define LPC43_EEPROM_RWSTATE           (LPC43_EEPROMC_BASE+LPC43_EEPROM_RWSTATE_OFFSET)
+#define LPC43_EEPROM_AUTOPROG          (LPC43_EEPROMC_BASE+LPC43_EEPROM_AUTOPROG_OFFSET)
+#define LPC43_EEPROM_WSTATE            (LPC43_EEPROMC_BASE+LPC43_EEPROM_WSTATE_OFFSET)
+# LPC43_EEPROM_CLKDIV                  (LPC43_EEPROMC_BASE+LPC43_EEPROM_CLKDIV_OFFSET)
+#define LPC43_EEPROM_PWRDWN            (LPC43_EEPROMC_BASE+LPC43_EEPROM_PWRDWN_OFFSET)
+
+/* EEPROM interrupt registers */
+
+#define LPC43_EEPROM_INTENCLR          (LPC43_EEPROMC_BASE+LPC43_EEPROM_INTENCLR_OFFSET)
+#define LPC43_EEPROM_INTENSET          (LPC43_EEPROMC_BASE+LPC43_EEPROM_INTENSET_OFFSET)
+#define LPC43_EEPROM_INTSTAT           (LPC43_EEPROMC_BASE+LPC43_EEPROM_INTSTAT_OFFSET)
+#define LPC43_EEPROM_INTEN             (LPC43_EEPROMC_BASE+LPC43_EEPROM_INTEN_OFFSET)
+#define LPC43_EEPROM_INTSTATCLR        (LPC43_EEPROMC_BASE+LPC43_EEPROM_INTSTATCLR_OFFSET)
+#define LPC43_EEPROM_INTSTATSET        (LPC43_EEPROMC_BASE+LPC43_EEPROM_INTSTATSET_OFFSET)
+
+/* Register Bit Definitions *********************************************************/
+
+/* EEPROM registers */
+
+/* EEPROM command register */
+
+#define EEPROM_CMD_SHIFT               (0)       /* Bits 0-2: Command */
+#define EEPROM_CMD_MASK                (7 << EEPROM_CMD_SHIFT)
+#  define EEPROM_CMD_PROGRAM           6        /* 110=erase/program page */
+                                                /* Bits 3-31: Reserved */
+/* EEPROM read wait state register */
+
+#define EEPROM_RWSTATE_RPHASE2_SHIFT   (0)       /* Bits 0-7: Wait states 2 (minus 1) */
+#define EEPROM_RWSTATE_RPHASE2_MASK    (0xff << EEPROM_RWSTATE_RPHASE2_SHIFT)
+#  define EEPROM_RWSTATE_RPHASE2(n)    (((n)-1) << EEPROM_RWSTATE_RPHASE2_SHIFT)
+#define EEPROM_RWSTATE_RPHASE1_SHIFT   (8)       /* Bits 8-15: Wait states 1 (minus 1) */
+#define EEPROM_RWSTATE_RPHASE1_MASK    (0xff << EEPROM_RWSTATE_RPHASE1_SHIFT)
+#  define EEPROM_RWSTATE_RPHASE1(n)    (((n)-1) << EEPROM_RWSTATE_RPHASE1_SHIFT)
+                                                /* Bits 16-31: Reserved */
+/* EEPROM auto programming register */
+
+#define EEPROM_AUTOPROG_SHIFT          (0)       /* Bits 0-1: Auto programming mode */
+#define EEPROM_AUTOPROG_MASK           (3 << EEPROM_AUTOPROG_SHIFT)
+#  define EEPROM_AUTOPROG_OFF          (0 << EEPROM_AUTOPROG_SHIFT) /* auto programming off */
+#  define EEPROM_AUTOPROG_FIRST        (1 << EEPROM_AUTOPROG_SHIFT) /* erase/program cycle triggered by first word */
+#  define EEPROM_AUTOPROG_LAST         (2 << EEPROM_AUTOPROG_SHIFT) /* erase/program cycle triggered by last word */
+                                                /* Bits 2-31: Reserved */
+/* EEPROM wait state register */
+
+#define EEPROM_WSTATE_PHASE3_SHIFT     (0)       /* Bits 0-7: Wait states for phase 3 (minus 1) */
+#define EEPROM_WSTATE_PHASE3_MASK      (0xff << EEPROM_WSTATE_PHASE3_SHIFT)
+#define EEPROM_WSTATE_PHASE2_SHIFT     (8)       /* Bits 8-15: Wait states for phase 2 (minus 1) */
+#define EEPROM_WSTATE_PHASE2_MASK      (0xff << EEPROM_WSTATE_PHASE2_SHIFT)
+#define EEPROM_WSTATE_PHASE1_SHIFT     (16)      /* Bits 16-23: Wait states for phase 1 (minus 1) */
+#define EEPROM_WSTATE_PHASE1_MASK      (0xff << EEPROM_WSTATE_PHASE1_SHIFT)
+                                                 /* Bits 24-30: Reserved */
+#define EEPROM_WSTATE_LCK_PARWEP       (1 << 31) /* Bit 31: Lock for write, erase and program */
+
+/* EEPROM clock divider register */
+
+#define EEPROM_CLKDIV_MASK             (0xffff)  /* Bits 0-15: Division factor (minus 1) */
+#define EEPROM_CLKDIV(n)               ((n)-1)   /* Bits 0-15: Division factor (minus 1) */
+                                                 /* Bits 16-31: Reserved */
+/* EEPROM power-down register */
+
+#define EEPROM_PWRDWN                  (1 << 0)  /* Bit 0:  Power down mode bit */
+                                                 /* Bits 1-31: Reserved */
+/* EEPROM interrupt registers */
+/* EEPROM interrupt enable clear */
+/* EEPROM interrupt enable set */
+/* EEPROM interrupt status */
+/* EEPROM interrupt enable */
+/* EEPROM interrupt status clear */
+/* EEPROM interrupt status set */
+                                                /* Bits 0-1: Reserved */
+#define EEPROM_INT_ENDOFPROG           (1 << 2) /* Bit 2:  Program operation finished interrupt */
+                                                /* Bits 3-31: Reserved */
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_EEPROM_H */
diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_emc.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_emc.h
new file mode 100644
index 000000000..4fb3ae38b
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_emc.h
@@ -0,0 +1,425 @@
+/****************************************************************************************************
+ * arch/arm/src/lpc43xx/chip/lpc43_emc.h
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_EMC_H
+#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_EMC_H
+
+/****************************************************************************************************
+ * Included Files
+ ****************************************************************************************************/
+
+#include <nuttx/config.h>
+
+/****************************************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************************************/
+/* Register Offsets *********************************************************************************/
+
+#define LPC43_EMC_CONTROL_OFFSET          0x0000 /* EMC Control register */
+#define LPC43_EMC_STATUS_OFFSET           0x0004 /* EMC Status register */
+#define LPC43_EMC_CONFIG_OFFSET           0x0008 /* EMC Configuration register */
+#define LPC43_EMC_DYNCONTROL_OFFSET       0x0020 /* Dynamic Memory Control register */
+#define LPC43_EMC_DYNREFRESH_OFFSET       0x0024 /* Dynamic Memory Refresh Timer register */
+#define LPC43_EMC_DYNREADCONFIG_OFFSET    0x0028 /* Dynamic Memory Read Configuration register */
+#define LPC43_EMC_DYNRP_OFFSET            0x0030 /* Dynamic Memory Precharge Command Period register */
+#define LPC43_EMC_DYNRAS_OFFSET           0x0034 /* Dynamic Memory Active to Precharge Command Period register */
+#define LPC43_EMC_DYNSREX_OFFSET          0x0038 /* Dynamic Memory Self Refresh Exit Time register */
+#define LPC43_EMC_DYNAPR_OFFSET           0x003c /* Dynamic Memory Last Data Out to Active Time register */
+#define LPC43_EMC_DYNDAL_OFFSET           0x0040 /* Dynamic Memory Data In to Active Command Time register */
+#define LPC43_EMC_DYNWR_OFFSET            0x0044 /* Dynamic Memory Write Recovery Time register */
+#define LPC43_EMC_DYNRC_OFFSET            0x0048 /* Dynamic Memory Active to Active Command Period register */
+#define LPC43_EMC_DYNRFC_OFFSET           0x004c /* Dynamic Memory Auto-refresh Period register */
+#define LPC43_EMC_DYNXSR_OFFSET           0x0050 /* Dynamic Memory Exit Self Refresh register */
+#define LPC43_EMC_DYNRRD_OFFSET           0x0054 /* Dynamic Memory Active Bank A to Active Bank B Time register */
+#define LPC43_EMC_DYNMRD_OFFSET           0x0058 /* Dynamic Memory Load Mode register to Active Command Time */
+#define LPC43_EMC_STATEXTWAIT_OFFSET      0x0080 /* Static Memory Extended Wait register */
+
+#define LPC43_EMC_DYNCONFIG_CSOFFSET      0x0000
+#define LPC43_EMC_DYNRASCAS_CSOFFSET      0x0004
+#define LPC43_EMC_DYNCS_OFFSET(n)         (0x100 + ((n) << 5))
+#define LPC43_EMC_DYNCONFIG_OFFSET(n)     (DYNCS_OFFSET(n)+DYNCONFIG_CSOFFSET)
+#define LPC43_EMC_DYNRASCAS_OFFSET(n)     (DYNCS_OFFSET(n)+DYNRASCAS_CSOFFSET)
+
+#define LPC43_EMC_DYNCONFIG0_OFFSET       0x0100 /* Dynamic Memory Configuration register CS0 */
+#define LPC43_EMC_DYNRASCAS0_OFFSET       0x0104 /* Dynamic Memory RAS & CAS Delay register CS0 */
+#define LPC43_EMC_DYNCONFIG1_OFFSET       0x0120 /* Dynamic Memory Configuration register CS1 */
+#define LPC43_EMC_DYNRASCAS1_OFFSET       0x0124 /* Dynamic Memory RAS & CAS Delay register CS1 */
+#define LPC43_EMC_DYNCONFIG2_OFFSET       0x0140 /* Dynamic Memory Configuration register CS2 */
+#define LPC43_EMC_DYNRASCAS2_OFFSET       0x0144 /* Dynamic Memory RAS & CAS Delay register CS2 */
+#define LPC43_EMC_DYNCONFIG3_OFFSET       0x0160 /* Dynamic Memory Configuration register CS3 */
+#define LPC43_EMC_DYNRASCAS3_OFFSET       0x0164 /* ynamic Memory RAS & CAS Delay register CS3 */
+
+#define LPC43_EMC_STATCONFIG_CSOFFSET     0x0000 /* Static Memory Configuration register */
+#define LPC43_EMC_STATWAITWEN_CSOFFSET    0x0004 /* Static Memory Write Enable Delay register */
+#define LPC43_EMC_STATWAITOEN_CSOFFSET    0x0008 /* Static Memory Output Enable Delay register */
+#define LPC43_EMC_STATWAITRD_CSOFFSET     0x000c /* Static Memory Read Delay register */
+#define LPC43_EMC_STATWAITPAGE_CSOFFSET   0x0010 /* Static Memory Write Delay registers */
+#define LPC43_EMC_STATWAITWR_CSOFFSET     0x0014 /* Static Memory Page Mode Read Delay register  */
+#define LPC43_EMC_STATWAITTURN_CSOFFSET   0x0018 /* Static Memory Turn Round Delay register */
+#define LPC43_EMC_STATCS_OFFSET(n)        (0x0200 + ((n) << 5))
+#define LPC43_EMC_STATCONFIG_OFFSET(n)    (LPC43_EMC_STATCS_OFFSET(n)+LPC43_EMC_STATCONFIG_CSOFFSET)
+#define LPC43_EMC_STATWAITWEN_OFFSET(n)   (LPC43_EMC_STATCS_OFFSET(n)+LPC43_EMC_STATWAITWEN_CSOFFSET)
+#define LPC43_EMC_STATWAITOEN_OFFSET(n)   (LPC43_EMC_STATCS_OFFSET(n)+LPC43_EMC_STATWAITOEN_CSOFFSET)
+#define LPC43_EMC_STATWAITRD_OFFSET(n)    (LPC43_EMC_STATCS_OFFSET(n)+LPC43_EMC_STATWAITRD_CSOFFSET)
+#define LPC43_EMC_STATWAITPAGE_OFFSET(n)  (LPC43_EMC_STATCS_OFFSET(n)+LPC43_EMC_STATWAITPAGE_CSOFFSET)
+#define LPC43_EMC_STATWAITWR_OFFSET(n)    (LPC43_EMC_STATCS_OFFSET(n)+LPC43_EMC_STATWAITWR_CSOFFSET)
+#define LPC43_EMC_STATWAITTURN_OFFSET(n)  (LPC43_EMC_STATCS_OFFSET(n)+LPC43_EMC_STATWAITTURN_CSOFFSET)
+
+#define LPC43_EMC_STATCONFIG0_OFFSET      0x0200 /* Static Memory Configuration register CS0 */
+#define LPC43_EMC_STATWAITWEN0_OFFSET     0x0204 /* Static Memory Write Enable Delay register CS0 */
+#define LPC43_EMC_STATWAITOEN0_OFFSET     0x0208 /* Static Memory Output Enable Delay register CS0 */
+#define LPC43_EMC_STATWAITRD0_OFFSET      0x020c /* Static Memory Read Delay register CS0 */
+#define LPC43_EMC_STATWAITPAGE0_OFFSET    0x0210 /* Static Memory Page Mode Read Delay register CS0 */
+#define LPC43_EMC_STATWAITWR0_OFFSET      0x0214 /* Static Memory Write Delay register CS0 */
+#define LPC43_EMC_STATWAITTURN0_OFFSET    0x0218 /* Static Memory Turn Round Delay register CS0 */
+
+#define LPC43_EMC_STATCONFIG1_OFFSET      0x0220 /* Static Memory Configuration register CS1 */
+#define LPC43_EMC_STATWAITWEN1_OFFSET     0x0224 /* Static Memory Write Enable Delay register CS1 */
+#define LPC43_EMC_STATWAITOEN1_OFFSET     0x0228 /* Static Memory Output Enable Delay register CS1 */
+#define LPC43_EMC_STATWAITRD1_OFFSET      0x022c /* Static Memory Read Delay register CS1 */
+#define LPC43_EMC_STATWAITPAGE1_OFFSET    0x0230 /* Static Memory Page Mode Read Delay register CS1 */
+#define LPC43_EMC_STATWAITWR1_OFFSET      0x0234 /* Static Memory Write Delay registers CS1 */
+#define LPC43_EMC_STATWAITTURN1_OFFSET    0x0238 /* Static Memory Turn Round Delay register CS1 */
+
+#define LPC43_EMC_STATCONFIG2_OFFSET      0x0240 /* Static Memory Configuration register CS2 */
+#define LPC43_EMC_STATWAITWEN2_OFFSET     0x0244 /* Static Memory Write Enable Delay register CS2 */
+#define LPC43_EMC_STATWAITOEN2_OFFSET     0x0248 /* Static Memory Output Enable Delay register CS2 */
+#define LPC43_EMC_STATWAITRD2_OFFSET      0x024c /* Static Memory Read Delay register CS2 */
+#define LPC43_EMC_STATWAITPAGE2_OFFSET    0x0250 /* Static Memory Page Mode Read Delay register CS2 */
+#define LPC43_EMC_STATWAITWR2_OFFSET      0x0254 /* Static Memory Write Delay registers CS2 */
+#define LPC43_EMC_STATWAITTURN2_OFFSET    0x0258 /* Static Memory Turn Round Delay register CS2 */
+
+#define LPC43_EMC_STATCONFIG3_OFFSET      0x0260 /* Static Memory Configuration register CS3 */
+#define LPC43_EMC_STATWAITWEN3_OFFSET     0x0264 /* Static Memory Write Enable Delay register CS3 */
+#define LPC43_EMC_STATWAITOEN3_OFFSET     0x0268 /* Static Memory Output Enable Delay register CS3 */
+#define LPC43_EMC_STATWAITRD3_OFFSET      0x026c /* Static Memory Read Delay register CS3 */
+#define LPC43_EMC_STATWAITPAGE3_OFFSET    0x0270 /* Static Memory Page Mode Read Delay register CS3 */
+#define LPC43_EMC_STATWAITWR3_OFFSET      0x0274 /* Static Memory Write Delay registers CS3 */
+#define LPC43_EMC_STATWAITTURN3_OFFSET    0x0278 /* Static Memory Turn Round Delay register CS3 */
+
+/* Register Addresses *******************************************************************************/
+
+#define LPC43_EMC_CONTROL                 (LPC43_EMC_BASE+LPC43_EMC_CONTROL_OFFSET)
+#define LPC43_EMC_STATUS                  (LPC43_EMC_BASE+LPC43_EMC_STATUS_OFFSET)
+#define LPC43_EMC_CONFIG                  (LPC43_EMC_BASE+LPC43_EMC_CONFIG_OFFSET)
+#define LPC43_EMC_DYNCONTROL              (LPC43_EMC_BASE+LPC43_EMC_DYNCONTROL_OFFSET)
+#define LPC43_EMC_DYNREFRESH              (LPC43_EMC_BASE+LPC43_EMC_DYNREFRESH_OFFSET)
+#define LPC43_EMC_DYNREADCONFIG           (LPC43_EMC_BASE+LPC43_EMC_DYNREADCONFIG_OFFSET)
+#define LPC43_EMC_DYNRP                   (LPC43_EMC_BASE+LPC43_EMC_DYNRP_OFFSET)
+#define LPC43_EMC_DYNRAS                  (LPC43_EMC_BASE+LPC43_EMC_DYNRAS_OFFSET)
+#define LPC43_EMC_DYNSREX                 (LPC43_EMC_BASE+LPC43_EMC_DYNSREX_OFFSET)
+#define LPC43_EMC_DYNAPR                  (LPC43_EMC_BASE+LPC43_EMC_DYNAPR_OFFSET)
+#define LPC43_EMC_DYNDAL                  (LPC43_EMC_BASE+LPC43_EMC_DYNDAL_OFFSET)
+#define LPC43_EMC_DYNWR                   (LPC43_EMC_BASE+LPC43_EMC_DYNWR_OFFSET)
+#define LPC43_EMC_DYNRC                   (LPC43_EMC_BASE+LPC43_EMC_DYNRC_OFFSET)
+#define LPC43_EMC_DYNRFC                  (LPC43_EMC_BASE+LPC43_EMC_DYNRFC_OFFSET)
+#define LPC43_EMC_DYNXSR                  (LPC43_EMC_BASE+LPC43_EMC_DYNXSR_OFFSET)
+#define LPC43_EMC_DYNRRD                  (LPC43_EMC_BASE+LPC43_EMC_DYNRRD_OFFSET)
+#define LPC43_EMC_DYNMRD                  (LPC43_EMC_BASE+LPC43_EMC_DYNMRD_OFFSET)
+#define LPC43_EMC_STATEXTWAIT             (LPC43_EMC_BASE+LPC43_EMC_STATEXTWAIT_OFFSET)
+
+#define LPC43_EMC_DYNCS(n)                (LPC43_EMC_BASE+LPC43_EMC_DYNCS_OFFSET(n))
+#define LPC43_EMC_DYNCONFIG(n)            (LPC43_EMC_BASE+LPC43_EMC_DYNCONFIG_OFFSET(n))
+#define LPC43_EMC_DYNRASCAS(n)            (LPC43_EMC_BASE+LPC43_EMC_DYNRASCAS_OFFSET(n))
+
+#define LPC43_EMC_DYNCONFIG0              (LPC43_EMC_BASE+LPC43_EMC_DYNCONFIG0_OFFSET)
+#define LPC43_EMC_DYNRASCAS0              (LPC43_EMC_BASE+LPC43_EMC_DYNRASCAS0_OFFSET)
+#define LPC43_EMC_DYNCONFIG1              (LPC43_EMC_BASE+LPC43_EMC_DYNCONFIG1_OFFSET)
+#define LPC43_EMC_DYNRASCAS1              (LPC43_EMC_BASE+LPC43_EMC_DYNRASCAS1_OFFSET)
+#define LPC43_EMC_DYNCONFIG2              (LPC43_EMC_BASE+LPC43_EMC_DYNCONFIG2_OFFSET)
+#define LPC43_EMC_DYNRASCAS2              (LPC43_EMC_BASE+LPC43_EMC_DYNRASCAS2_OFFSET)
+#define LPC43_EMC_DYNCONFIG3              (LPC43_EMC_BASE+LPC43_EMC_DYNCONFIG3_OFFSET)
+#define LPC43_EMC_DYNRASCAS3              (LPC43_EMC_BASE+LPC43_EMC_DYNRASCAS3_OFFSET)
+
+#define LPC43_EMC_STATCS(n)               (LPC43_EMC_BASE+LPC43_EMC_STATCS_OFFSET(n))
+#define LPC43_EMC_STATCONFIG(n)           (LPC43_EMC_BASE+LPC43_EMC_STATCONFIG_OFFSET(n))
+#define LPC43_EMC_STATWAITWEN(n)          (LPC43_EMC_BASE+LPC43_EMC_STATWAITWEN_OFFSET(n))
+#define LPC43_EMC_STATWAITOEN(n)          (LPC43_EMC_BASE+LPC43_EMC_STATWAITOEN_OFFSET(n))
+#define LPC43_EMC_STATWAITRD(n)           (LPC43_EMC_BASE+LPC43_EMC_STATWAITRD_OFFSET(n))
+#define LPC43_EMC_STATWAITPAGE(n)         (LPC43_EMC_BASE+LPC43_EMC_STATWAITPAGE_OFFSET(n))
+#define LPC43_EMC_STATWAITWR(n)           (LPC43_EMC_BASE+LPC43_EMC_STATWAITWR_OFFSET(n))
+#define LPC43_EMC_STATWAITTURN(n)         (LPC43_EMC_BASE+LPC43_EMC_STATWAITTURN_OFFSET(n))
+
+#define LPC43_EMC_STATCONFIG0             (LPC43_EMC_BASE+LPC43_EMC_STATCONFIG0_OFFSET)
+#define LPC43_EMC_STATWAITWEN0            (LPC43_EMC_BASE+LPC43_EMC_STATWAITWEN0_OFFSET)
+#define LPC43_EMC_STATWAITOEN0            (LPC43_EMC_BASE+LPC43_EMC_STATWAITOEN0_OFFSET)
+#define LPC43_EMC_STATWAITRD0             (LPC43_EMC_BASE+LPC43_EMC_STATWAITRD0_OFFSET)
+#define LPC43_EMC_STATWAITPAGE0           (LPC43_EMC_BASE+LPC43_EMC_STATWAITPAGE0_OFFSET)
+#define LPC43_EMC_STATWAITWR0             (LPC43_EMC_BASE+LPC43_EMC_STATWAITWR0_OFFSET)
+#define LPC43_EMC_STATWAITTURN0           (LPC43_EMC_BASE+LPC43_EMC_STATWAITTURN0_OFFSET)
+
+#define LPC43_EMC_STATCONFIG1             (LPC43_EMC_BASE+LPC43_EMC_STATCONFIG1_OFFSET)
+#define LPC43_EMC_STATWAITWEN1            (LPC43_EMC_BASE+LPC43_EMC_STATWAITWEN1_OFFSET)
+#define LPC43_EMC_STATWAITOEN1            (LPC43_EMC_BASE+LPC43_EMC_STATWAITOEN1_OFFSET)
+#define LPC43_EMC_STATWAITRD1             (LPC43_EMC_BASE+LPC43_EMC_STATWAITRD1_OFFSET)
+#define LPC43_EMC_STATWAITPAGE1           (LPC43_EMC_BASE+LPC43_EMC_STATWAITPAGE1_OFFSET)
+#define LPC43_EMC_STATWAITWR1             (LPC43_EMC_BASE+LPC43_EMC_STATWAITWR1_OFFSET)
+#define LPC43_EMC_STATWAITTURN1           (LPC43_EMC_BASE+LPC43_EMC_STATWAITTURN1_OFFSET)
+
+#define LPC43_EMC_STATCONFIG2             (LPC43_EMC_BASE+LPC43_EMC_STATCONFIG2_OFFSET)
+#define LPC43_EMC_STATWAITWEN2            (LPC43_EMC_BASE+LPC43_EMC_STATWAITWEN2_OFFSET)
+#define LPC43_EMC_STATWAITOEN2            (LPC43_EMC_BASE+LPC43_EMC_STATWAITOEN2_OFFSET)
+#define LPC43_EMC_STATWAITRD2             (LPC43_EMC_BASE+LPC43_EMC_STATWAITRD2_OFFSET)
+#define LPC43_EMC_STATWAITPAGE2           (LPC43_EMC_BASE+LPC43_EMC_STATWAITPAGE2_OFFSET)
+#define LPC43_EMC_STATWAITWR2             (LPC43_EMC_BASE+LPC43_EMC_STATWAITWR2_OFFSET)
+#define LPC43_EMC_STATWAITTURN2           (LPC43_EMC_BASE+LPC43_EMC_STATWAITTURN2_OFFSET)
+
+#define LPC43_EMC_STATCONFIG3             (LPC43_EMC_BASE+LPC43_EMC_STATCONFIG3_OFFSET)
+#define LPC43_EMC_STATWAITWEN3            (LPC43_EMC_BASE+LPC43_EMC_STATWAITWEN3_OFFSET)
+#define LPC43_EMC_STATWAITOEN3            (LPC43_EMC_BASE+LPC43_EMC_STATWAITOEN3_OFFSET)
+#define LPC43_EMC_STATWAITRD3             (LPC43_EMC_BASE+LPC43_EMC_STATWAITRD3_OFFSET)
+#define LPC43_EMC_STATWAITPAGE3           (LPC43_EMC_BASE+LPC43_EMC_STATWAITPAGE3_OFFSET)
+#define LPC43_EMC_STATWAITWR3             (LPC43_EMC_BASE+LPC43_EMC_STATWAITWR3_OFFSET)
+#define LPC43_EMC_STATWAITTURN3           (LPC43_EMC_BASE+LPC43_EMC_STATWAITTURN3_OFFSET)
+
+/* Register Bit Definitions *************************************************************************/
+
+/* EMC Control register */
+
+#define EMC_CONTROL_ENA                   (1 << 0)  /* Bit 0:  EMC Enable */
+#define EMC_CONTROL_ADDRMIRROR            (1 << 1)  /* Bit 1:  Address mirror */
+#define EMC_CONTROL_LOWPOWER              (1 << 2)  /* Bit 2:  Low-power mode */
+                                                    /* Bits 3-31: Reserved */
+/* EMC Status register */
+#define EMC__
+#define EMC_STATUS_BUSY                   (1 << 0)  /* Bit 0:  Busy */
+#define EMC_STATUS_WB                     (1 << 1)  /* Bit 1:  Write buffer status */
+#define EMC_CONFIG_SA                     (1 << 2)  /* Bit 2:  Self-refresh acknowledge */
+                                                    /* Bits 3-31: Reserved */
+/* EMC Configuration register */
+
+#define EMC_CONFIG_EM                     (1 << 0)  /* Bit 0:  Endian mode */
+                                                    /* Bits 1-7: Reserved */
+#define EMC_CONFIG_CR                     (1 << 8)  /* Bit 8:  Clock Ratio */
+                                                    /* Bits 9-31: Reserved */
+/* Dynamic Memory Control register */
+
+#define EMC_DYNCONTROL_
+#define EMC_DYNCONTROL_CE                 (1 << 0)  /* Bit 0:  Dynamic memory clock enable */
+#define EMC_DYNCONTROL_CS                 (1 << 1)  /* Bit 1:  Dynamic memory clock control */
+#define EMC_DYNCONTROL_SR                 (1 << 2)  /* Bit 2:  Self-refresh request, EMCSREFREQ */
+                                                    /* Bits 3-4: Reserved */
+#define EMC_DYNCONTROL_MMC                (1 << 5)  /* Bit 5:  Memory clock control */
+                                                    /* Bit 6: Reserved */
+#define EMC_DYNCONTROL_SI_SHIFT           (7)       /* Bits 7-8: SDRAM initialization */
+#define EMC_DYNCONTROL_SI_MASK            (3 << EMC_DYNCONTROL_SI_SHIFT)
+#  define EMC_DYNCONTROL_SI_NORMAL        (0 << EMC_DYNCONTROL_SI_SHIFT) /* SDRAM NORMAL command */
+#  define EMC_DYNCONTROL_SI_MODE          (1 << EMC_DYNCONTROL_SI_SHIFT) /* SDRAM MODE command */
+#  define EMC_DYNCONTROL_SI_PALL          (2 << EMC_DYNCONTROL_SI_SHIFT) /* SDRAM PALL (precharge all) command */
+#  define EMC_DYNCONTROL_SI_ MASK         (3 << EMC_DYNCONTROL_SI_SHIFT) /* SDRAM NOP (no operation) command) */
+                                                    /* Bits 9-31: Reserved */
+/* Dynamic Memory Refresh Timer register */
+
+#define EMC_DYNREFRESH_SHIFT              (0)       /* Bits 0-10: Refresh timer */
+#define EMC_DYNREFRESH_MASK               (0x7ff << EMC_DYNREFRESH_SHIFT)
+                                                    /* Bits 11-31: Reserved */
+/* Dynamic Memory Read Configuration register */
+
+#define EMC_DYNREADCONFIG_SHIFT           (0)       /* Bits 0-1: Read data strategy */
+#define EMC_DYNREADCONFIG_MASK            (3 << EMC_DYNREADCONFIG_SHIFT)
+#  define EMC_DYNREADCONFIG_0p5CCLK       (1 << EMC_DYNREADCONFIG_SHIFT) /* Command delayed by 0.5 CCLK */
+#  define EMC_DYNREADCONFIG_1p5CCLK       (2 << EMC_DYNREADCONFIG_SHIFT) /* Command delayed by 1.5 CCLK */
+#  define EMC_DYNREADCONFIG_2p5CCLK       (3 << EMC_DYNREADCONFIG_SHIFT) /* Command delayed by 2.5 CCLK */
+                                                    /* Bits 2-31: Reserved */
+/* Dynamic Memory Precharge Command Period register */
+
+#define EMC_DYNRP_SHIFT                   (0)       /* Bits 0-3: Precharge command period */
+#define EMC_DYNRP_MASK                    (15 << EMC_DYNRP_SHIFT)
+#  define EMC_DYNRP(n)                    (((n)-1) << EMC_DYNRP_SHIFT) /* Delay n CCLK cycles */
+                                                    /* Bits 2-31: Reserved */
+/* Dynamic Memory Active to Precharge Command Period register */
+
+#define EMC_DYNRAS_SHIFT                   (0)       /* Bits 0-3: Active to precharge command period */
+#define EMC_DYNRAS_MASK                    (15 << EMC_DYNRAS_SHIFT)
+#  define EMC_DYNRAS(n)                    (((n)-1) << EMC_DYNRAS_SHIFT) /* Delay n CCLK cycles */
+                                                     /* Bits 4-31: Reserved */
+/* Dynamic Memory Self Refresh Exit Time register */
+
+#define EMC_DYNSREX_SHIFT                  (0)       /* Bits 0-3: Self-refresh exit time */
+#define EMC_DYNSREX_MASK                   (15 << EMC_DYNSREX_SHIFT)
+#  define EMC_DYNSREX(n)                   (((n)-1) << EMC_DYNSREX_SHIFT) /* Delay n CCLK cycles */
+                                                     /* Bits 4-31: Reserved */
+/* Dynamic Memory Last Data Out to Active Time register */
+
+#define EMC_DYNAPR_SHIFT                   (0)       /* Bits 0-3: Last-data-out to active command time */
+#define EMC_DYNAPR_MASK                    (15 << EMC_DYNAPR_SHIFT)
+#  define EMC_DYNAPR(n)                    (((n)-1) << EMC_DYNAPR_SHIFT) /* Delay n CCLK cycles */
+                                                     /* Bits 4-31: Reserved */
+/* Dynamic Memory Data In to Active Command Time register */
+
+#define EMC_DYNDAL_SHIFT                   (0)       /* Bits 0-3: Data-in to active command */
+#define EMC_DYNDAL_MASK                    (15 << EMC_DYNDAL_SHIFT)
+#  define EMC_DYNDAL(n)                    (((n)-1) << EMC_DYNDAL_SHIFT) /* Delay n CCLK cycles */
+                                                     /* Bits 4-31: Reserved */
+/* Dynamic Memory Write Recovery Time register */
+
+#define EMC_DYNWR_SHIFT                    (0)       /* Bits 0-3: Write recovery time */
+#define EMC_DYNWR_MASK                     (15 << EMC_DYNWR_SHIFT)
+#  define EMC_DYNWR(n)                     (((n)-1) << EMC_DYNWR_SHIFT) /* Delay n CCLK cycles */
+                                                     /* Bits 4-31: Reserved */
+/* Dynamic Memory Active to Active Command Period register */
+
+#define EMC_DYNRC_SHIFT                    (0)       /* Bits 0-4: Active to active command period */
+#define EMC_DYNRC_MASK                     (31 << EMC_DYNRC_SHIFT)
+#  define EMC_DYNRC(n)                     (((n)-1) << EMC_DYNRC_SHIFT) /* Delay n CCLK cycles */
+                                                     /* Bits 5-31: Reserved */
+/* Dynamic Memory Auto-refresh Period register */
+
+#define EMC_DYNRFC_SHIFT                   (0)       /* Bits 0-4: Auto-refresh period and
+                                                      * auto-refresh to active command period */
+#define EMC_DYNRFC_MASK                    (31 << EMC_DYNRFC_SHIFT)
+#  define EMC_DYNRFC(n)                    (((n)-1) << EMC_DYNRFC_SHIFT) /* Delay n CCLK cycles */
+                                                     /* Bits 5-31: Reserved */
+/* Dynamic Memory Exit Self Refresh register */
+
+#define EMC_DYNXSR_SHIFT                   (0)       /* Bits 0-4: Exit self-refresh to active command time */
+#define EMC_DYNXSR_MASK                    (31 << EMC_DYNXSR_SHIFT)
+#  define EMC_DYNXSR(n)                    (((n)-1) << EMC_DYNXSR_SHIFT) /* Delay n CCLK cycles */
+                                                     /* Bits 5-31: Reserved */
+/* Dynamic Memory Active Bank A to Active Bank B Time register */
+
+#define EMC_DYNRRD_SHIFT                   (0)       /* Bits 0-3: Active bank A to active bank B latency */
+#define EMC_DYNRRD_MASK                    (15 << EMC_DYNRRD_SHIFT)
+#  define EMC_DYNRRD(n)                    (((n)-1) << EMC_DYNRRD_SHIFT) /* Delay n CCLK cycles */
+                                                     /* Bits 4-31: Reserved */
+/* Dynamic Memory Load Mode register to Active Command Time */
+
+#define EMC_DYNMRD_SHIFT                   (0)       /* Bits 0-3: Load mode register to active command time */
+#define EMC_DYNMRD_MASK                    (15 << EMC_DYNMRD_SHIFT)
+#  define EMC_DYNMRD(n)                    (((n)-1) << EMC_DYNMRD_SHIFT) /* Delay n CCLK cycles */
+                                                     /* Bits 4-31: Reserved */
+/* Static Memory Extended Wait register */
+
+#define EMC_STATEXTWAIT_SHIFT              (0)       /* Bits 0-9: Extended wait time out */
+#define EMC_STATEXTWAIT_MASK               (0x3ff << EMC_STATEXTWAIT_SHIFT)
+#  define EMC_STATEXTWAIT(n)               (((n)-1) << EMC_STATEXTWAIT_SHIFT) /* Delay n CCLK cycles */
+                                                     /* Bits 10-31: Reserved */
+/* Dynamic Memory Configuration registers */
+                                                     /* Bits 0-2: Reserved */
+#define EMC_DYNCONFIG_MD_SHIFT             (3)       /* Bits 3-4: Memory device */
+#define EMC_DYNCONFIG_MD_MASK              (3 << EMC_DYNCONFIG_MD_SHIFT)
+#  define EMC_DYNCONFIG_MD_SDRAM           (0 << EMC_DYNCONFIG_MD_SHIFT) /* SDRAM (POR reset value) */
+                                                     /* Bits 5-6: Reserved */
+#define EMC_DYNCONFIG_AM0_SHIFT            (7)       /* Bits 7-12: AM0 Address mapping (see user manual) */
+#define EMC_DYNCONFIG_AM0_MASK             (0x3f << EMC_DYNCONFIG_AM0_SHIFT)
+                                                     /* Bit 13: Reserved */
+#define EMC_DYNCONFIG_AM1                  (1 << 14) /* Bit 14: AM1 Address mapping (see user manual) */
+                                                     /* Bits 15-18: Reserved */
+#define EMC_DYNCONFIG_BENA                 (1 << 10) /* Bit 19: Buffer enable */
+#define EMC_DYNCONFIG_WP                   (1 << 20) /* Bit 20: Write protect. */
+                                                     /* Bits 21-31: Reserved */
+/* Dynamic Memory RAS & CAS Delay registers */
+
+#define EMC_DYNRASCAS_RAS_SHIFT            (0)       /* Bits 0-1: RAS latency (active to read/write delay) */
+#define EMC_DYNRASCAS_RAS_MASK             (3 << EMC_DYNRASCAS_RAS_SHIFT)
+#  define EMC_DYNRASCAS_RAS_1CCLK          (1 << EMC_DYNRASCAS_RAS_SHIFT) /* One CCLK cycle */
+#  define EMC_DYNRASCAS_RAS_2CCLK          (2 << EMC_DYNRASCAS_RAS_SHIFT) /* Two CCLK cycles */
+#  define EMC_DYNRASCAS_RAS_3CCLK          (3 << EMC_DYNRASCAS_RAS_SHIFT) /* Three CCLK cycles (POR reset value) */
+                                                     /* Bits 2-7: Reserved */
+#define EMC_DYNRASCAS_CAS_SHIFT            (8)       /* Bits 8-9: CAS latency */
+#define EMC_DYNRASCAS_CAS_MASK             (3 << EMC_DYNRASCAS_CAS_SHIFT)
+#  define EMC_DYNRASCAS_CAS_1CCLK          (1 << EMC_DYNRASCAS_CAS_SHIFT) /* One CCLK cycle */
+#  define EMC_DYNRASCAS_CAS_2CCLK          (2 << EMC_DYNRASCAS_CAS_SHIFT) /* Two CCLK cycles */
+#  define EMC_DYNRASCAS_CAS_3CCLK          (3 << EMC_DYNRASCAS_CAS_SHIFT) /* Three CCLK cycles (POR reset value) */
+                                                     /* Bits 10-31: Reserved */
+/* Static Memory Configuration registers */
+
+#define EMC_STATCONFIG_MW_SHIFT            (0)       /* Bits 0-1: Memory width */
+#define EMC_STATCONFIG_MW_MASK             (3 << EMC_STATCONFIG_MW_SHIFT)
+#  define EMC_STATCONFIG_MW_8BITS          (0 << EMC_STATCONFIG_MW_SHIFT)
+#  define EMC_STATCONFIG_MW_16BITS         (1 << EMC_STATCONFIG_MW_SHIFT)
+#  define EMC_STATCONFIG_MW_32BITS         (2 << EMC_STATCONFIG_MW_SHIFT)
+                                                     /* Bit 2:  Reserved */
+#define EMC_STATCONFIG_PM                  (1 << 3)  /* Bit 3:  Page mode */
+                                                     /* Bits 4-5: Reserved */
+#define EMC_STATCONFIG_PC                  (1 << 6)  /* Bit 6:  Chip select polarity */
+#define EMC_STATCONFIG_PB                  (1 << 7)  /* Bit 7:  Byte lane state */
+#define EMC_STATCONFIG_EW                  (1 << 8)  /* Bit 8:  Extended wait */
+                                                     /* Bits 9-18: Reserved */
+#define EMC_STATCONFIG_BENA                (1 << 19) /* Bit 19: Buffer enable */
+#define EMC_STATCONFIG_WP                  (1 << 20) /* Bit 20: Write protect */
+                                                     /* Bits 21-31: Reserved */
+/* Static Memory Write Enable Delay registers */
+
+#define EMC_STATWAITWEN_SHIFT              (0)       /* Bits 0-3: Wait write enable */
+#define EMC_STATWAITWEN_MASK               (15 << EMC_STATWAITWEN_SHIFT)
+#  define EMC_STATWAITWEN(n)               (((n)-1) << EMC_STATWAITWEN_SHIFT) /* Delay n CCLK cycles */
+                                                     /* Bits 4-31: Reserved */
+/* Static Memory Output Enable Delay registers */
+
+#define EMC_STATWAITOEN_SHIFT              (0)       /* Bits 0-3: Wait output enable */
+#define EMC_STATWAITOEN_MASK               (15 << EMC_STATWAITOEN_SHIFT)
+#  define EMC_STATWAITOEN(n)               (((n)-1) << EMC_STATWAITOEN_SHIFT) /* Delay n CCLK cycles */
+                                                     /* Bits 4-31: Reserved */
+/* Static Memory Read Delay registers */
+
+#define EMC_STATWAITRD_SHIFT               (0)       /* Bits 0-4: Non-page mode read wait states or
+                                                      * asynchronous page mode read first access wait state */
+#define EMC_STATWAITRD_MASK                (31 << EMC_STATWAITRD_SHIFT)
+#  define EMC_STATWAITRD(n)                (((n)-1) << EMC_STATWAITRD_SHIFT) /* Delay n CCLK cycles */
+                                                     /* Bits 5-31: Reserved */
+/* Static Memory Page Mode Read Delay registers */
+
+#define EMC_STATWAITPAGE_SHIFT             (0)       /* Bits 0-4: Asynchronous page mode read after the
+                                                      * first read wait states */
+#define EMC_STATWAITPAGE_MASK              (31 << EMC_STATWAITPAGE_SHIFT)
+#  define EMC_STATWAITPAGE(n)              (((n)-1) << EMC_STATWAITPAGE_SHIFT) /* Delay n CCLK cycles */
+                                                     /* Bits 5-31: Reserved */
+/* Static Memory Write Delay registers */
+
+#define EMC_STATWAITWR_SHIFT               (0)       /* Bits 0-4: Write wait states */
+#define EMC_STATWAITWR_MASK                (31 << EMC_STATWAITWR_SHIFT)
+#  define EMC_STATWAITWR(n)                (((n)-1) << EMC_STATWAITWR_SHIFT) /* Delay n CCLK cycles */
+                                                     /* Bits 5-31: Reserved */
+/* Static Memory Turn Round Delay registers */
+
+#define EMC_STATWAITTURN_SHIFT             (0)       /* Bits 0-3: Bus turnaround cycles */
+#define EMC_STATWAITTURN_MASK              (15 << EMC_STATWAITTURN_SHIFT)
+#  define EMC_STATWAITTURN(n)              (((n)-1) << EMC_STATWAITTURN_SHIFT) /* Delay n CCLK cycles */
+                                                     /* Bits 5-31: Reserved */
+
+/****************************************************************************************************
+ * Public Types
+ ****************************************************************************************************/
+
+/****************************************************************************************************
+ * Public Data
+ ****************************************************************************************************/
+
+/****************************************************************************************************
+ * Public Functions
+ ****************************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_EMC_H */
diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_ethernet.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_ethernet.h
new file mode 100644
index 000000000..e7d16fe26
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_ethernet.h
@@ -0,0 +1,666 @@
+/****************************************************************************************************
+ * arch/arm/src/lpc43xx/chip/lpc43_ethernet.h
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_ETHERNET_H
+#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_ETHERNET_H
+
+/****************************************************************************************************
+ * Included Files
+ ****************************************************************************************************/
+
+#include <nuttx/config.h>
+
+/****************************************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************************************/
+/* Register Offsets *********************************************************************************/
+/* MAC Registers */
+
+#define LPC43_ETH_MACCFG_OFFSET      0x0000 /* MAC configuration register */
+#define LPC43_ETH_MACFFLT_OFFSET     0x0004 /* MAC frame filter register */
+#define LPC43_ETH_MACHTHI_OFFSET     0x0008 /* MAC hash table high register */
+#define LPC43_ETH_MACHTLO_OFFSET     0x000c /* MAC hash table low register */
+#define LPC43_ETH_MACMIIA_OFFSET     0x0010 /* MAC MII address register */
+#define LPC43_ETH_MACMIID_OFFSET     0x0014 /* MAC MII data register */
+#define LPC43_ETH_MACFC_OFFSET       0x0018 /* MAC flow control register */
+#define LPC43_ETH_MACVLANT_OFFSET    0x001c /* MAC VLAN tag register */
+#define LPC43_ETH_MACDBG_OFFSET      0x0024 /* MAC debug register */
+#define LPC43_ETH_MACRWFFLT_OFFSET   0x0028 /* MAC remote wakeup frame filter reg */
+#define LPC43_ETH_MACPMTCS_OFFSET    0x002c /* MAC PMT control and status register */
+#define LPC43_ETH_MACINTR_OFFSET     0x0038 /* MAC interrupt status register */
+#define LPC43_ETH_MACIM_OFFSET       0x003c /* MAC interrupt mask register */
+#define LPC43_ETH_MACA0HI_OFFSET     0x0040 /* MAC address 0 high register */
+#define LPC43_ETH_MACA0LO_OFFSET     0x0044 /* MAC address 0 low register */
+
+/* IEEE 1588 time stamp registers */
+
+#define LPC43_ETH_TSCTRL_OFFSET      0x0700 /* Time stamp control register */
+#define LPC43_ETH_SSINCR_OFFSET      0x0704 /* Sub-second increment register */
+#define LPC43_ETH_SECONDS_OFFSET     0x0708 /* System time seconds register */
+#define LPC43_ETH_NANOSEC_OFFSET     0x070c /* System time nanoseconds register */
+#define LPC43_ETH_SECUPD_OFFSET      0x0710 /* System time seconds update register */
+#define LPC43_ETH_NSECUPD_OFFSET     0x0714 /* System time nanoseconds update register */
+#define LPC43_ETH_ADDEND_OFFSET      0x0718 /* Time stamp addend register */
+#define LPC43_ETH_TGTSEC_OFFSET      0x071c /* Target time seconds register */
+#define LPC43_ETH_TGTNSEC_OFFSET     0x0720 /* Target time nanoseconds register */
+#define LPC43_ETH_HIGHWORD_OFFSET    0x0724 /* System time higher word seconds register */
+#define LPC43_ETH_TSSTAT_OFFSET      0x0728 /* Time stamp status register */
+
+/* DMA Registers */
+
+#define LPC43_ETH_DMABMODE_OFFSET    0x1000 /* DMA bus mode register */
+#define LPC43_ETH_DMATXPD_OFFSET     0x1004 /* DMA transmit poll demand register */
+#define LPC43_ETH_DMARXPD_OFFSET     0x1008 /* DMA receive poll demand register */
+#define LPC43_ETH_DMARXDLA_OFFSET    0x100c /* DMA receive descriptor list address register */
+#define LPC43_ETH_DMATXDLA_OFFSET    0x1010 /* DMA transmit descriptor list address register */
+#define LPC43_ETH_DMASTAT_OFFSET     0x1014 /* DMA status register */
+#define LPC43_ETH_DMAOPMODE_OFFSET   0x1018 /* DMA operation mode register */
+#define LPC43_ETH_DMAINTEN_OFFSET    0x101c /* DMA interrupt enable register */
+#define LPC43_ETH_DMAMFBO_OFFSET     0x1020 /* DMA missed frame and buffer overflow counter register */
+#define LPC43_ETH_DMARXWDT_OFFSET    0x1024 /* DMA receive status watchdog timer register */
+#define LPC43_ETH_DMACHTXD_OFFSET    0x1048 /* DMA current host transmit descriptor register */
+#define LPC43_ETH_DMACHRXD_OFFSET    0x104c /* DMA current host receive descriptor register */
+#define LPC43_ETH_DMACHTXBUF_OFFSET  0x1050 /* DMA current host transmit buffer address register */
+#define LPC43_ETH_DMACHRXBUF_OFFSET  0x1054 /* DMA current host receive buffer address register */
+
+/* Register Base Addresses **************************************************************************/
+/* MAC Registers */
+
+#define LPC43_ETH_MACCR              (LPC43_ETHERNET_BASE+LPC43_ETH_MACCFG_OFFSET)
+#define LPC43_ETH_MACFFLT            (LPC43_ETHERNET_BASE+LPC43_ETH_MACFFLT_OFFSET)
+#define LPC43_ETH_MACHTHI            (LPC43_ETHERNET_BASE+LPC43_ETH_MACHTHI_OFFSET)
+#define LPC43_ETH_MACHTLO            (LPC43_ETHERNET_BASE+LPC43_ETH_MACHTLO_OFFSET)
+#define LPC43_ETH_MACMIIA            (LPC43_ETHERNET_BASE+LPC43_ETH_MACMIIA_OFFSET)
+#define LPC43_ETH_MACMIID            (LPC43_ETHERNET_BASE+LPC43_ETH_MACMIID_OFFSET)
+#define LPC43_ETH_MACFC              (LPC43_ETHERNET_BASE+LPC43_ETH_MACFC_OFFSET)
+#define LPC43_ETH_MACVLANT           (LPC43_ETHERNET_BASE+LPC43_ETH_MACVLANT_OFFSET)
+#define LPC43_ETH_MACDBG             (LPC43_ETHERNET_BASE+LPC43_ETH_MACDBG_OFFSET)
+#define LPC43_ETH_MACRWFFLT          (LPC43_ETHERNET_BASE+LPC43_ETH_MACRWFFLT_OFFSET)
+#define LPC43_ETH_MACPMTCS           (LPC43_ETHERNET_BASE+LPC43_ETH_MACPMTCS_OFFSET)
+#define LPC43_ETH_MACSR              (LPC43_ETHERNET_BASE+LPC43_ETH_MACINTR_OFFSET)
+#define LPC43_ETH_MACIM              (LPC43_ETHERNET_BASE+LPC43_ETH_MACIM_OFFSET)
+#define LPC43_ETH_MACA0HI            (LPC43_ETHERNET_BASE+LPC43_ETH_MACA0HI_OFFSET)
+#define LPC43_ETH_MACA0LO            (LPC43_ETHERNET_BASE+LPC43_ETH_MACA0LO_OFFSET)
+
+/* IEEE 1588 time stamp registers */
+
+#define LPC43_ETH_TSCTRL             (LPC43_ETHERNET_BASE+LPC43_ETH_TSCTRL_OFFSET)
+#define LPC43_ETH_SSINCR             (LPC43_ETHERNET_BASE+LPC43_ETH_SSINCR_OFFSET)
+#define LPC43_ETH_SECONDS            (LPC43_ETHERNET_BASE+LPC43_ETH_SECONDS_OFFSET)
+#define LPC43_ETH_NANOSEC            (LPC43_ETHERNET_BASE+LPC43_ETH_NANOSEC_OFFSET)
+#define LPC43_ETH_SECUPD             (LPC43_ETHERNET_BASE+LPC43_ETH_SECUPD_OFFSET)
+#define LPC43_ETH_NSECUPD            (LPC43_ETHERNET_BASE+LPC43_ETH_NSECUPD_OFFSET)
+#define LPC43_ETH_ADDEND             (LPC43_ETHERNET_BASE+LPC43_ETH_ADDEND_OFFSET)
+#define LPC43_ETH_TGTSEC             (LPC43_ETHERNET_BASE+LPC43_ETH_TGTSEC_OFFSET)
+#define LPC43_ETH_TGTNSEC            (LPC43_ETHERNET_BASE+LPC43_ETH_TGTNSEC_OFFSET)
+#define LPC43_ETH_HIGHWORD           (LPC43_ETHERNET_BASE+LPC43_ETH_HIGHWORD_OFFSET)
+#define LPC43_ETH_TSSTAT             (LPC43_ETHERNET_BASE+LPC43_ETH_TSSTAT_OFFSET)
+
+/* DMA Registers */
+
+#define LPC43_ETH_DMABMODE           (LPC43_ETHERNET_BASE+LPC43_ETH_DMABMODE_OFFSET)
+#define LPC43_ETH_DMATXPD            (LPC43_ETHERNET_BASE+LPC43_ETH_DMATXPD_OFFSET)
+#define LPC43_ETH_DMARXPD            (LPC43_ETHERNET_BASE+LPC43_ETH_DMARXPD_OFFSET)
+#define LPC43_ETH_DMARXDLA           (LPC43_ETHERNET_BASE+LPC43_ETH_DMARXDLA_OFFSET)
+#define LPC43_ETH_DMATXDLA           (LPC43_ETHERNET_BASE+LPC43_ETH_DMATXDLA_OFFSET)
+#define LPC43_ETH_DMASTAT            (LPC43_ETHERNET_BASE+LPC43_ETH_DMASTAT_OFFSET)
+#define LPC43_ETH_DMAOPMODE          (LPC43_ETHERNET_BASE+LPC43_ETH_DMAOPMODE_OFFSET)
+#define LPC43_ETH_DMAINTEN           (LPC43_ETHERNET_BASE+LPC43_ETH_DMAINTEN_OFFSET)
+#define LPC43_ETH_DMAMFBO            (LPC43_ETHERNET_BASE+LPC43_ETH_DMAMFBO_OFFSET)
+#define LPC43_ETH_DMARXWDT           (LPC43_ETHERNET_BASE+LPC43_ETH_DMARXWDT_OFFSET)
+#define LPC43_ETH_DMACHTXD           (LPC43_ETHERNET_BASE+LPC43_ETH_DMACHTXD_OFFSET)
+#define LPC43_ETH_DMACHRXD           (LPC43_ETHERNET_BASE+LPC43_ETH_DMACHRXD_OFFSET)
+#define LPC43_ETH_DMACHTXBUF         (LPC43_ETHERNET_BASE+LPC43_ETH_DMACHTXBUF_OFFSET)
+#define LPC43_ETH_DMACHRXBUF         (LPC43_ETHERNET_BASE+LPC43_ETH_DMACHRXBUF_OFFSET)
+
+/* Register Bit-Field Definitions *******************************************************************/
+/* MAC Registers */
+
+/* MAC configuration register */
+                                               /* Bits 0-1:  Reserved */
+#define ETH_MACCFG_RE                (1 << 2)  /* Bit 2:  Receiver enable */
+#define ETH_MACCFG_TE                (1 << 3)  /* Bit 3:  Transmitter enable */
+#define ETH_MACCFG_DF                (1 << 4)  /* Bit 4:  Deferral check */
+#define ETH_MACCFG_BL_SHIFT          (5)       /* Bits 5-6: Back-off limit */
+#define ETH_MACCFG_BL_MASK           (3 << ETH_MACCFG_BL_SHIFT)
+#  define ETH_MACCFG_BL_10           (0 << ETH_MACCFG_BL_SHIFT) /* 00: k = min (n, 10) */
+#  define ETH_MACCFG_BL_8            (1 << ETH_MACCFG_BL_SHIFT) /* 01: k = min (n, 8) */
+#  define ETH_MACCFG_BL_4            (2 << ETH_MACCFG_BL_SHIFT) /* 10: k = min (n, 4) */
+#  define ETH_MACCFG_BL_1            (3 << ETH_MACCFG_BL_SHIFT) /* 11: k = min (n, 1) */
+#define ETH_MACCFG_ACS               (1 << 7)  /* Bit 7:  Automatic pad/CRC stripping */
+#define ETH_MACCFG_LUD               (1 << 8)  /* Bit 8:  Link up/down */
+#define ETH_MACCFG_RD                (1 << 9)  /* Bit 9:  Disable Retry */
+                                               /* Bit 10: Reserved */
+#define ETH_MACCFG_DM                (1 << 11) /* Bit 11: Duplex mode */
+#define ETH_MACCFG_LM                (1 << 12) /* Bit 12: Loopback mode */
+#define ETH_MACCFG_DO                (1 << 13) /* Bit 13: Disable receive own */
+#define ETH_MACCFG_FES               (1 << 14) /* Bit 14: Fast Ethernet speed */
+#define ETH_MACCFG_PS                (1 << 15) /* Bit 15: Port select */
+#define ETH_MACCFG_DCRS              (1 << 16) /* Bit 16: Disable carrier sense during transmission */
+#define ETH_MACCFG_IFG_SHIFT         (17)      /* Bits 17-19: Interframe gap */
+#define ETH_MACCFG_IFG_MASK          (7 << ETH_MACCFG_IFG_SHIFT)
+#  define ETH_MACCFG_IFG(n)          ((12-((n) >> 3)) << ETH_MACCFG_IFG_SHIFT) /* n bit times, n=40,48,..96 */
+#define ETH_MACCFG_JE                (1 << 20) /* Bit 20: Jumbo frame enable */
+                                               /* Bit 21: Reserved */
+#define ETH_MACCFG_JD                (1 << 22) /* Bit 22: Jabber disable */
+#define ETH_MACCFG_WD                (1 << 23) /* Bit 23: Watchdog disable */
+#define ETH_MACCFG_CSTF              (1 << 25) /* Bits 25: CRC stripping for Type frames */
+                                               /* Bots 24-31: Reserved */
+/* MAC frame filter register */
+
+#define ETH_MACFFLT_PR               (1 << 0)  /* Bit 0: Promiscuous mode */
+                                               /* Bits 1-2: Reserved */
+#define ETH_MACFFLT_DAIF             (1 << 3)  /* Bit 3: Destination address inverse filtering */
+#define ETH_MACFFLT_PM               (1 << 4)  /* Bit 4: Pass all multicast */
+#define ETH_MACFFLT_DBF              (1 << 5)  /* Bit 5: Disable Broadcast Frames */
+#define ETH_MACFFLT_PCF_SHIFT        (6)       /* Bits 6-7: Pass control frames */
+#define ETH_MACFFLT_PCF_MASK         (3 << ETH_MACFFLT_PCF_SHIFT)
+#  define ETH_MACFFLT_PCF_NONE       (0 << ETH_MACFFLT_PCF_SHIFT) /* Prevents all control frames */
+#  define ETH_MACFFLT_PCF_PAUSE      (1 << ETH_MACFFLT_PCF_SHIFT) /* Prevents all except Pause control frames */
+#  define ETH_MACFFLT_PCF_ALL        (2 << ETH_MACFFLT_PCF_SHIFT) /* Forwards all control frames */
+#  define ETH_MACFFLT_PCF_FILTER     (3 << ETH_MACFFLT_PCF_SHIFT) /* Forwards all that pass address filter */
+#define ETH_MACFFLT_SAIF             (1 << 8)  /* Bit 8: Source address inverse filtering */
+#define ETH_MACFFLT_SAF              (1 << 9)  /* Bit 9: Source address filter */
+                                               /* Bits 10-30: Reserved */
+#define ETH_MACFFLT_RA               (1 << 31) /* Bit 31: Receive all */
+
+/* MAC hash table high/low register (32-bit values) */
+
+/* MAC MII address register */
+
+#define ETH_MACMIIA_GB               (1 << 0)  /* Bit 0: MII busy */
+#define ETH_MACMIIA_WR               (1 << 1)  /* Bit 1: MII write */
+#define ETH_MACMIIA_CR_SHIFT         (2)       /* Bits 2-5: Clock range */
+#define ETH_MACMIIA_CR_MASK          (15 << ETH_MACMIIA_CR_SHIFT)
+#  define ETH_MACMIIA_CR_60_100      (0 << ETH_MACMIIA_CR_SHIFT)  /* 60-100  MHz CLK_M4_ETHERNET/42 */
+#  define ETH_MACMIIA_CR_100_150     (1 << ETH_MACMIIA_CR_SHIFT)  /* 100-150 MHz CLK_M4_ETHERNET/62 */
+#  define ETH_MACMIIA_CR_20_35       (2 << ETH_MACMIIA_CR_SHIFT)  /* 20-35   MHz CLK_M4_ETHERNET/16 */
+#  define ETH_MACMIIA_CR_35_60       (3 << ETH_MACMIIA_CR_SHIFT)  /* 35-60   MHz CLK_M4_ETHERNET/26 */
+#  define ETH_MACMIIA_CR_150_168     (4 << ETH_MACMIIA_CR_SHIFT)  /* 150-168 MHz CLK_M4_ETHERNET/102 */
+#  define ETH_MACMIIA_CR_150_168     (5 << ETH_MACMIIA_CR_SHIFT)  /* 250 - 300 MHz CLK_M4_ETHERNET/124 */
+#  define ETH_MACMIIA_CR_DIV42       (8 << ETH_MACMIIA_CR_SHIFT)  /* 60-100  MHz CLK_M4_ETHERNET/42 */
+#  define ETH_MACMIIA_CR_DIV62       (9 << ETH_MACMIIA_CR_SHIFT)  /* 100-150 MHz CLK_M4_ETHERNET/62 */
+#  define ETH_MACMIIA_CR_DIV16       (10 << ETH_MACMIIA_CR_SHIFT) /* 20-35   MHz CLK_M4_ETHERNET/16 */
+#  define ETH_MACMIIA_CR_DIV26       (11 << ETH_MACMIIA_CR_SHIFT) /* 35-60   MHz CLK_M4_ETHERNET/26 */
+#  define ETH_MACMIIA_CR_DIV102      (12 << ETH_MACMIIA_CR_SHIFT) /* 150-168 MHz CLK_M4_ETHERNET/102 */
+#  define ETH_MACMIIA_CR_DIV124      (13 << ETH_MACMIIA_CR_SHIFT) /* 250 - 300 MHz CLK_M4_ETHERNET/124 */
+#  define ETH_MACMIIA_CR_DIV42_2     (14 << ETH_MACMIIA_CR_SHIFT) /* 60-100  MHz CLK_M4_ETHERNET/42 */
+#  define ETH_MACMIIA_CR_DIV62_2     (15 << ETH_MACMIIA_CR_SHIFT) /* 100-150 MHz CLK_M4_ETHERNET/62 */
+#define ETH_MACMIIA_MR_SHIFT         (6)       /* Bits 6-10: MII register */
+#define ETH_MACMIIA_MR_MASK          (31 << ETH_MACMIIA_MR_SHIFT)
+#define ETH_MACMIIA_PA_SHIFT         (11)      /* Bits 11-15: PHY address */
+#define ETH_MACMIIA_PA_MASK          (31 << ETH_MACMIIA_PA_SHIFT)
+                                               /* Bits 16-31: Reserved */
+/* MAC MII data register */
+
+#define ETH_MACMIID_MASK             (0xffff)
+
+/* MAC flow control register */
+
+#define ETH_MACFC_FCB                (1 << 0)  /* Bit 0: Flow control busy/back pressure activate */
+#define ETH_MACFC_TFE                (1 << 1)  /* Bit 1: Transmit flow control enable */
+#define ETH_MACFC_RFE                (1 << 2)  /* Bit 2: Receive flow control enable */
+#define ETH_MACFC_UP                 (1 << 3)  /* Bit 3: Unicast pause frame detect */
+#define ETH_MACFC_PLT_SHIFT          (4)       /* Bits 4-5: Pause low threshold */
+#define ETH_MACFC_PLT_MASK           (3 << ETH_MACFC_PLT_SHIFT)
+#  define ETH_MACFC_PLT(n)           ((n) << ETH_MACFC_PLT_SHIFT)
+                                               /* Bit 6:  Reserved */
+#define ETH_MACFC_DZPQ               (1 << 7)  /* Bit 7:  Disable Zero-Quanta Pause */
+                                               /* Bits 8-15: Reserved */
+#define ETH_MACFC_PT_SHIFT           (16)      /* Bits 16-31: Pause time */
+#define ETH_MACFC_PT_MASK            (0xffff << ETH_MACFC_PT_SHIFT)
+
+/* MAC VLAN tag register */
+
+#define ETH_MACVLANT_VL_SHIFT        (0)       /* Bits 0-15: VLAN tag identifier (for receive frames) */
+#define ETH_MACVLANT_VL_MAS K        (0xffff << ETH_MACVLANT_VLANTI_SHIFT)
+#define ETH_MACVLANT_ETV             (1 << 16) /* Bit 16: 12-bit VLAN tag comparison */
+
+/* MAC debug register */
+
+#define ETH_MACDBG_RXACTIVE          (1 << 0)  /* Bit 0: MAC MII receive protocol engine active */
+#define ETH_MACDBG_FS0_SHIFT         (1)       /* Bits 1-2: MAC small FIFO read / write controllers status */
+#define ETH_MACDBG_FS0_MASK          (3 << ETH_MACDBG_FS0_SHIFT)
+#define ETH_MACDBG_RFS1              (1 << 4)  /* Bit 4: Rx FIFO write controller active */
+#define ETH_MACDBG_RFS_SHIFT         (5)       /* Bits 5-6: Rx FIFO read controller status */
+#define ETH_MACDBG_RFS_MASK          (3 << ETH_MACDBG_RFS_SHIFT)
+#  define ETH_MACDBG_RFS_IDLE        (0 << ETH_MACDBG_RFS_SHIFT) /* 00: IDLE state */
+#  define ETH_MACDBG_RFS_RFRAME      (1 << ETH_MACDBG_RFS_SHIFT) /* 01: Reading frame data */
+#  define ETH_MACDBG_RFS_RSTATUS     (2 << ETH_MACDBG_RFS_SHIFT) /* 10: Reading frame status (or time-stamp) */
+#  define ETH_MACDBG_RFS_FLUSHING    (3 << ETH_MACDBG_RFS_SHIFT) /* 11: Flushing the frame data and status */
+                                               /* Bit 7:  Reserved */
+#define ETH_MACDBG_RFFL_SHIFT        (8)       /* Bits 8-9: Rx FIFO fill level */
+#define ETH_MACDBG_RFFL_MASK         (3 << ETH_MACDBG_RFFL_SHIFT)
+#  define ETH_MACDBG_RFFL_EMPTY      (0 << ETH_MACDBG_RFFL_SHIFT) /* 00: RxFIFO empty */
+#  define ETH_MACDBG_RFFL_DEACT      (1 << ETH_MACDBG_RFFL_SHIFT) /* 01: RxFIFO fill-level below flow-control de-activate threshold */
+#  define ETH_MACDBG_RFFL_ACTIV      (2 << ETH_MACDBG_RFFL_SHIFT) /* 10: RxFIFO fill-level above flow-control activate threshold */
+#  define ETH_MACDBG_RFFL_FULL       (3 << ETH_MACDBG_RFFL_SHIFT) /* 11: RxFIFO full */
+                                              /* Bits 10-15: Reserved */
+#define ETH_MACDBG_TXACTIVE          (1 << 16) /* Bit 16: MAC MII transmit engine active */
+#define ETH_MACDBG_TXSTAT_SHIFT      (17)      /* Bits 17-18: State of the MAC transmit frame controller module */
+#define ETH_MACDBG_TXSTAT_MASK       (3 << ETH_MACDBG_TXSTAT_SHIFT)
+#  define ETH_MACDBG_TXSTAT_IDLE     (0 << ETH_MACDBG_TXSTAT_SHIFT) /* 00: Idle */
+#  define ETH_MACDBG_TXSTAT_WAITING  (1 << ETH_MACDBG_TXSTAT_SHIFT) /* 01: Waiting for Status of previous frame or IFG/backoff period to be over */
+#  define ETH_MACDBG_TXSTAT_PAUSE    (2 << ETH_MACDBG_TXSTAT_SHIFT) /* 10: Generating and transmitting a Pause control frame */
+#  define ETH_MACDBG_TXSTAT_FRAME    (3 << ETH_MACDBG_TXSTAT_SHIFT) /* 11: Transferring input frame for transmission */
+#define ETH_MACDBG_PAUSE             (1 << 19) /* Bit 19: MAC transmitter in pause */
+#define ETH_MACDBG_TFRS_SHIFT        (20)      /* Bits 20-21: State of the TxFIFO read Controller */
+#define ETH_MACDBG_TFRS_MASK         (3 << ETH_MACDBG_TFRS_SHIFT)
+#  define ETH_MACDBG_TFRS_IDLE       (0 << ETH_MACDBG_TFRS_SHIFT) /* 00: Idle state */
+#  define ETH_MACDBG_TFRS_READ       (1 << ETH_MACDBG_TFRS_SHIFT) /* 01: Read state */
+#  define ETH_MACDBG_TFRS_WAITING    (2 << ETH_MACDBG_TFRS_SHIFT) /* 10: Waiting for TxStatus from MAC transmitter */
+#  define ETH_MACDBG_TFRS_WRITING    (3 << ETH_MACDBG_TFRS_SHIFT) /* 11: Writing the received TxStatus or flushing the TxFIFO */
+#define ETH_MACDBG_TFS1              (1 << 22) /* Bit 22: Tx FIFO write active */
+                                               /* Bit 23: Reserved */
+#define ETH_MACDBG_TFNE              (1 << 24) /* Bit 24: Tx FIFO not empty */
+#define ETH_MACDBG_TFF               (1 << 25) /* Bit 25: Tx FIFO full */
+                                               /* Bits 26-31: Reserved */
+
+/* MAC remote wakeup frame filter reg.  Provides 32-bit access to remote remote wake-up filters. */
+
+/* MAC PMT control and status register */
+
+#define ETH_MACPMTCS_PD              (1 << 0)  /* Bit 0: Power down */
+#define ETH_MACPMTCS_MPE             (1 << 1)  /* Bit 1: Magic Packet enable */
+#define ETH_MACPMTCS_WFE             (1 << 2)  /* Bit 2: Wakeup frame enable */
+                                               /* Bits 3-4: Reserved */
+#define ETH_MACPMTCS_MPR             (1 << 5)  /* Bit 5: Magic packet received */
+#define ETH_MACPMTCS_WFR             (1 << 6)  /* Bit 6: Wakeup frame received */
+#define ETH_MACPMTCS_GU              (1 << 9)  /* Bit 9: Global unicast */
+                                               /* Bits 10-30: Reserved */
+#define ETH_MACPMTCS_WFFRPR          (1 << 31) /* Bit 31: Wake-up Frame Filter Register Pointer Reset */
+
+/* MAC interrupt status register */
+                                               /* Bits 0-2: Reserved */
+#define ETH_MACINTR_PMT              (1 << 3)  /* Bit 3: PMT status */
+                                               /* Bits 4-8: Reserved */
+#define ETH_MACINTR_TS               (1 << 9)  /* Bit 9: Time stamp trigger status */
+                                               /* Bits 10-31: Reserved */
+/* MAC interrupt mask register */
+                                               /* Bits 0-2: Reserved */
+#define ETH_MACIM_PMTIM              (1 << 3)  /* Bit 3: PMT interrupt mask */
+                                               /* Bits 4-8: Reserved */
+#define ETH_MACIM_TSIM               (1 << 9)  /* Bit 9: Time stamp interrupt mask */
+                                               /* Bits 10-31: Reserved */
+#define ETH_MACIM_ALLINTS            (ETH_MACIM_PMTIM|ETH_MACIM_TSTIM)
+
+/* MAC address 0 high register */
+
+#define ETH_MACA0HI_MACA0H_SHIFT     (0)       /* Bits 0-15: MAC address0 high [47:32] */
+#define ETH_MACA0HI_MACA0H_MASK      (0xffff << ETH_MACA0HI_MACA0H_SHIFT)
+                                               /* Bits 16-30: Reserved */
+#define ETH_MACA0HI_MO               (1 << 31) /* Bit 31: Always 1 */
+
+/* MAC address 0 low register (MAC address0 low [31:0]) */
+
+/* Time stamp control register */
+
+#define ETH_TSCTRL_TSENA             (1 << 0)  /* Bit 0:  Time stamp enable */
+#define ETH_TSCTRL_TSCFUPDT          (1 << 1)  /* Bit 1:  Time stamp fine or coarse update */
+#define ETH_TSCTRL_TSINIT            (1 << 2)  /* Bit 2:  Time stamp initialize */
+#define ETH_TSCTRL_TSUPDT            (1 << 3)  /* Bit 3:  Time stamp up */
+#define ETH_TSCTRL_TSTRIG            (1 << 4)  /* Bit 4:  Time stamp interrupt trigger enable */
+#define ETH_TSCTRL_TSADDREG          (1 << 5)  /* Bit 5:  Addend reg update */
+                                               /* Bits 6-7: Reserved */
+#define ETH_TSCTRL_TSENALL           (1 << 8)  /* Bit 8:  Enable time stamp for all frames */
+#define ETH_TSCTRL_TSCTRLSSR         (1 << 9)  /* Bit 9:  Time stamp digital or binary rollover control */
+#define ETH_TSCTRL_TSVER2ENA         (1 << 10) /* Bit 10: Enable PTP packet snooping for version 2 format */
+#define ETH_TSCTRL_TSIPENA           (1 << 11) /* Bit 11: Enable time stamp snapshot for ptp over ethernet frames */
+#define ETH_TSCTRL_TSIPV6ENA         (1 << 12) /* Bit 12: Enable time stamp snapshot for IPv6 frames */
+#define ETH_TSCTRL_TSIPV4ENA         (1 << 13) /* Bit 13: Enable time stamp snapshot for IPv4 frames */
+#define ETH_TSCTRL_TSEVNTENA         (1 << 14) /* Bit 14: Enable time stamp snapshot for event messages */
+#define ETH_TSCTRL_TSMSTRENA         (1 << 15) /* Bit 15: Enable snapshot for messages relevant to master */
+#define ETH_TSCTRL_TSCNT_SHIFT       (16)      /* Bits 16-17: Time stamp clock node type */
+#define ETH_TSCTRL_TSCNT_MASK        (3 << ETH_TSCTRL_TSCNT_SHIFT)
+#  define ETH_TSCTRL_TSCNT_ORDINARY  (0 << ETH_TSCTRL_TSCNT_SHIFT) /* 00: Ordinary clock */
+#  define ETH_TSCTRL_TSCNT_BOUNDARY  (1 << ETH_TSCTRL_TSCNT_SHIFT) /* 01: Boundary clock */
+#  define ETH_TSCTRL_TSCNT_E2E       (2 << ETH_TSCTRL_TSCNT_SHIFT) /* 10: End-to-end transparent clock */
+#  define ETH_TSCTRL_TSCNT_P2P       (3 << ETH_TSCTRL_TSCNT_SHIFT) /* 11: Peer-to-peer transparent clock */
+#define ETH_TSCTRL_TSENMACADDR       (1 << 18) /* Bit 18: Enable MAC address for PTP frame filtering */
+                                               /* Bits 19-31: Reserved */
+/* Sub-second increment register */
+
+#define ETH_SSINCR_MASK              (0xff)    /* Bits 0-7: Sub-second increment value */
+                                               /* Bits 8-31: Reserved */
+/* System time seconds register (32-bit) */
+
+/* System time nanoseconds register */
+
+#define ETH_NANOSEC_MASK             (0x7fffffff) /* Bits 0-30: Time stamp sub seconds */
+#define ETH_NANOSEC_PSNT             (1 << 31)    /* Bit 31: Positive or negative time */
+
+/* System time seconds update register (32-bit) */
+
+/* System time nanoseconds update register */
+
+#define ETH_NSECUPD_MASK             (0x7fffffff) /* Bits 0-30: Time stamp sub seconds */
+#define ETH_NSECUPD_ADDSUB           (1 << 31)    /* Bit 31: Add or subtract time */
+
+/* Time stamp addend register  (32-bit) */
+/* Target time seconds register (32-bit) */
+/* Target time nanoseconds register (32-bit) */
+
+#define ETH_TGTNSEC_MASK             (0x7fffffff) /* Bits 0-30: Target time stamp low */
+                                                  /* Bit 31: Reserved */
+/* System time higher words seconds register */
+
+#define ETH_HIGHWORD_MASK            (0x0000ffff) /* Bits 0-15:Time stamp higher word */
+#define ETH_HIGHWORD_ADDSUB          (1 << 31)    /* Bit 31: Add or subtract time */
+
+/* Time stamp status register */
+
+#define ETH_TSSTAT_TSSOVF            (1 << 0)  /* Bit 0: Time stamp second overflow */
+#define ETH_TSSTAT_TSTARGT           (1 << 1)  /* Bit 1: Time stamp target time reached */
+                                               /* Bits 2-31: Reserved */
+/* DMA Registers */
+
+/* DMA bus mode register */
+
+#define ETH_DMABMODE_SWR              (1 << 0)  /* Bit 0: Software reset */
+#define ETH_DMABMODE_DA               (1 << 1)  /* Bit 1: DMA arbitration scheme */
+#define ETH_DMABMODE_DSL_SHIFT        (2)       /* Bits 2-6: Descriptor skip length */
+#define ETH_DMABMODE_DSL_MASK         (31 << ETH_DMABMODE_DSL_SHIFT)
+#  define ETH_DMABMODE_DSL(n)         ((n) << ETH_DMABMODE_DSL_SHIFT)
+#define ETH_DMABMODE_ATDS             (1 << 7)  /* Bit 7: Alternate descriptor size */
+#define ETH_DMABMODE_PBL_SHIFT        (8)       /* Bits 8-13: Programmable burst length */
+#define ETH_DMABMODE_PBL_MASK         (0x3f << ETH_DMABMODE_PBL_SHIFT)
+#  define ETH_DMABMODE_PBL(n)         ((n) << ETH_DMABMODE_PBL_SHIFT) /* n=1, 2, 4, 8, 16, 32 */
+#define ETH_DMABMODE_PR_SHIFT         (14)      /* Bits 14-15: Rx-to-Tx priority ratio */
+#define ETH_DMABMODE_PR_MASK          (3 << ETH_DMABMODE_PR_SHIFT)
+#  define ETH_DMABMODE_PR_1TO1        (0 << ETH_DMABMODE_PR_SHIFT) /* 00: 1-to-1 */
+#  define ETH_DMABMODE_PR_2TO1        (1 << ETH_DMABMODE_PR_SHIFT) /* 01: 2-to-1 */
+#  define ETH_DMABMODE_PR_3TO1        (2 << ETH_DMABMODE_PR_SHIFT) /* 10: 3-to-1 */
+#  define ETH_DMABMODE_PR_4TO1        (3 << ETH_DMABMODE_PR_SHIFT) /* 11: 4-to-1 */
+#define ETH_DMABMODE_FB               (1 << 16) /* Bit 16: Fixed burst */
+#define ETH_DMABMODE_RPBL_SHIFT       (17)      /* Bits 17-22: RxDMA PBL */
+#define ETH_DMABMODE_RPBL_MASK        (0x3f << ETH_DMABMODE_RPBL_SHIFT)
+#  define ETH_DMABMODE_RPBL(n)        ((n) << ETH_DMABMODE_RPBL_SHIFT) /* n=1, 2, 4, 8, 16, 32 */
+#define ETH_DMABMODE_USP              (1 << 23) /* Bit 23: Use separate PBL */
+#define ETH_DMABMODE_PBL8X            (1 << 24) /* Bit 24: 8 x PBL mode */
+#define ETH_DMABMODE_AAL              (1 << 25) /* Bit 25: Address-aligned beats */
+#define ETH_DMABMODE_MB               (1 << 26) /* Bit 26: Mixed burst */
+#define ETH_DMABMODE_TXPR             (1 << 27) /* Bit 27: Tx DMA has higher priority than Rx DMA */
+                                                /* Bits 28-31: Reserved */
+/* DMA transmit poll demand register (32-bit) */
+/* DMA receive poll demand register (32-bit) */
+/* DMA receive descriptor list address register (32-bit address) */
+/* DMA transmit descriptor list address register (32-bit address) */
+
+/* Interrupt bit definitions common between the DMA status register (DMASTAT) and
+ * the DMA interrupt enable register (DMAINTEN).
+ */
+
+#define ETH_DMAINT_TI                (1 << 0)  /* Bit 0:  Transmit interrupt */
+#define ETH_DMAINT_TPS               (1 << 1)  /* Bit 1:  Transmit process stopped */
+#define ETH_DMAINT_TU                (1 << 2)  /* Bit 2:  Transmit buffer unavailable */
+#define ETH_DMAINT_TJT               (1 << 3)  /* Bit 3:  Transmit jabber timeout */
+#define ETH_DMAINT_OVF               (1 << 4)  /* Bit 4:  Receive overflow */
+#define ETH_DMAINT_UNF               (1 << 5)  /* Bit 5:  Transmit underflow */
+#define ETH_DMAINT_RI                (1 << 6)  /* Bit 6:  Receive interrupt */
+#define ETH_DMAINT_RU                (1 << 7)  /* Bit 7:  Receive buffer unavailable */
+#define ETH_DMAINT_RPS               (1 << 8)  /* Bit 8:  Receive process stopped */
+#define ETH_DMAINT_RWT               (1 << 9)  /* Bit 9:  Receive watchdog timeout */
+#define ETH_DMAINT_ETI               (1 << 10) /* Bit 10: Early transmit interrupt */
+                                               /* Bits 11-12: Reserved */
+#define ETH_DMAINT_FBI               (1 << 13) /* Bit 13: Fatal bus error interrupt */
+#define ETH_DMAINT_ERI               (1 << 14) /* Bit 14: Early receive interrupt */
+#define ETH_DMAINT_AIS               (1 << 15) /* Bit 15: Abnormal interrupt summary */
+#define ETH_DMAINT_NIS               (1 << 16) /* Bit 16: Normal interrupt summary */
+                                               /* Bits 17-31: Reserved */
+
+/* DMA operation mode register */
+                                               /* Bit 0:  Reserved */
+#define ETH_DMAOPMODE_SR             (1 << 1)  /* Bit 1:  Start/stop receive */
+#define ETH_DMAOPMODE_OSF            (1 << 2)  /* Bit 2:  Operate on second frame */
+#define ETH_DMAOPMODE_RTC_SHIFT      (3)       /* Bits 3-4: Receive threshold control */
+#define ETH_DMAOPMODE_RTC_MASK       (3 << ETH_DMAOPMODE_RTC_SHIFT)
+#  define ETH_DMAOPMODE_RTC_64       (0 << ETH_DMAOPMODE_RTC_SHIFT)
+#  define ETH_DMAOPMODE_RTC_32       (1 << ETH_DMAOPMODE_RTC_SHIFT)
+#  define ETH_DMAOPMODE_RTC_96       (2 << ETH_DMAOPMODE_RTC_SHIFT)
+#  define ETH_DMAOPMODE_RTC_128      (3 << ETH_DMAOPMODE_RTC_SHIFT)
+                                               /* Bit 5:  Reserved */
+#define ETH_DMAOPMODE_FUF            (1 << 6)  /* Bit 6:  Forward undersized good frames */
+#define ETH_DMAOPMODE_FEF            (1 << 7)  /* Bit 7:  Forward error frames */
+                                               /* Bits 8-12: Reserved */
+#define ETH_DMAOPMODE_ST             (1 << 13) /* Bit 13: Start/stop transmission */
+#define ETH_DMAOPMODE_TTC_SHIFT      (14)      /* Bits 14-16: Transmit threshold control */
+#define ETH_DMAOPMODE_TTC_MASK       (7 << ETH_DMAOPMODE_TTC_SHIFT)
+#  define ETH_DMAOPMODE_TTC_64       (0 << ETH_DMAOPMODE_TTC_SHIFT)
+#  define ETH_DMAOPMODE_TTC_128      (1 << ETH_DMAOPMODE_TTC_SHIFT)
+#  define ETH_DMAOPMODE_TTC_192      (2 << ETH_DMAOPMODE_TTC_SHIFT)
+#  define ETH_DMAOPMODE_TTC_256      (3 << ETH_DMAOPMODE_TTC_SHIFT)
+#  define ETH_DMAOPMODE_TTC_40       (4 << ETH_DMAOPMODE_TTC_SHIFT)
+#  define ETH_DMAOPMODE_TTC_32       (5 << ETH_DMAOPMODE_TTC_SHIFT)
+#  define ETH_DMAOPMODE_TTC_24       (6 << ETH_DMAOPMODE_TTC_SHIFT)
+#  define ETH_DMAOPMODE_TTC_16       (7 << ETH_DMAOPMODE_TTC_SHIFT)
+                                               /* Bits 17-19: Reserved */
+#define ETH_DMAOPMODE_FTF            (1 << 20) /* Bit 20: Flush transmit FIFO */
+                                               /* Bits 21-23: Reserved */
+#define ETH_DMAOPMODE_DFF            (1 << 24) /* Bit 24: Disable flushing of received frames */
+                                               /* Bits 25-31: Reserved */
+
+/* DMA missed frame and buffer overflow counter register */
+
+#define ETH_DMAMFBO_FMC_SHIFT       (0)       /* Bits 0-15: Number of frames missed */
+#define ETH_DMAMFBO_FMC_MASK        (0xffff << ETH_DMAMFBO_FMC_SHIFT)
+#define ETH_DMAMFBO_OC              (1 << 16) /* Bit 16: Overflow bit for missed frame counter */
+#define ETH_DMAMFBO_FMA_SHIFT       (17)      /* Bits 17-27: Number of frames missed by the application */
+#define ETH_DMAMFBO_FMA_MASK        (0x7ff << ETH_DMAMFBO_FMA_SHIFT)
+#define ETH_DMAMFBO_OF              (1 << 28) /* Bit 28: Overflow bit for FIFO overflow counter */
+                                              /* Bits 29-31: Reserved */
+/* DMA receive status watchdog timer register */
+
+#define ETH_DMARXWDT_MASK            (0xff)   /* Bits 9-6: RI watchdog timeout */
+                                              /* Bits 8-31: Reserved */
+/* DMA current host transmit descriptor register (32-bit address) */
+/* DMA current host receive descriptor register (32-bit address) */
+/* DMA current host transmit buffer address register (32-bit address) */
+/* DMA current host receive buffer address register (32-bit address) */
+
+/* DMA Descriptors **********************************************************************************/
+/* TDES0: Transmit descriptor Word0 */
+
+#define ETH_TDES0_DB                 (1 << 0)  /* Bit 0:  Deferred bit */
+#define ETH_TDES0_UF                 (1 << 1)  /* Bit 1:  Underflow error */
+#define ETH_TDES0_ED                 (1 << 2)  /* Bit 2:  Excessive deferral */
+#define ETH_TDES0_CC_SHIFT           (3)       /* Bits 3-6: Collision count */
+#define ETH_TDES0_CC_MASK            (15 << ETH_TDES0_CC_SHIFT)
+#define ETH_TDES0_VF                 (1 << 7)  /* Bit 7:  VLAN frame */
+#define ETH_TDES0_EC                 (1 << 8)  /* Bit 8:  Excessive collision */
+#define ETH_TDES0_LC                 (1 << 9)  /* Bit 9:  Late collision */
+#define ETH_TDES0_NC                 (1 << 10) /* Bit 10: No carrier */
+#define ETH_TDES0_LC                 (1 << 11) /* Bit 11: Loss of carrier */
+#define ETH_TDES0_IPE                (1 << 12) /* Bit 12: IP payload error */
+#define ETH_TDES0_FF                 (1 << 13) /* Bit 13: Frame flushed */
+#define ETH_TDES0_JT                 (1 << 14) /* Bit 14: Jabber timeout */
+#define ETH_TDES0_ES                 (1 << 15) /* Bit 15: Error summary */
+#define ETH_TDES0_IHE                (1 << 16) /* Bit 16: IP header error */
+#define ETH_TDES0_TTSS               (1 << 17) /* Bit 17: Transmit time stamp status */
+                                               /* Bits 18-19: Reserved */
+#define ETH_TDES0_TCH                (1 << 20) /* Bit 20: Second address chained */
+#define ETH_TDES0_TER                (1 << 21) /* Bit 21: Transmit end of ring */
+                                               /* Bits 22-24: Reserved */
+#define ETH_TDES0_TTSE               (1 << 25) /* Bit 25: Transmit time stamp enable */
+#define ETH_TDES0_DP                 (1 << 26) /* Bit 26: Disable pad */
+#define ETH_TDES0_DC                 (1 << 27) /* Bit 27: Disable CRC */
+#define ETH_TDES0_FS                 (1 << 28) /* Bit 28: First segment */
+#define ETH_TDES0_LS                 (1 << 29) /* Bit 29: Last segment */
+#define ETH_TDES0_IC                 (1 << 30) /* Bit 30: Interrupt on completion */
+#define ETH_TDES0_OWN                (1 << 31) /* Bit 31: Own bit */
+
+/* TDES1: Transmit descriptor Word1 */
+
+#define ETH_TDES1_TBS1_SHIFT         (0)  /* Bits 0-12: Transmit buffer 1 size */
+#define ETH_TDES1_TBS1_MASK          (0x1fff << ETH_TDES1_TBS1_SHIFT)
+#define ETH_TDES1_TBS2_SHIFT         (16)  /* Bits 16-28: Transmit buffer 2 size */
+#define ETH_TDES1_TBS2_MASK          (0x1fff << ETH_TDES1_TBS2_SHIFT)
+
+/* TDES2: Transmit descriptor Word2 (32-bit address) */
+/* TDES3: Transmit descriptor Word3 (32-bit address) */
+/* TDES6: Transmit descriptor Word6 (32-bit time stamp) */
+/* TDES7: Transmit descriptor Word7 (32-bit time stamp) */
+
+/* RDES0: Receive descriptor Word0 */
+
+#define ETH_RDES0_ESA                (1 << 0)  /* Bit 0:  Extended status available */
+#define ETH_RDES0_CE                 (1 << 1)  /* Bit 1:  CRC error */
+#define ETH_RDES0_DE                 (1 << 2)  /* Bit 2:  Dribble bit error */
+#define ETH_RDES0_RE                 (1 << 3)  /* Bit 3:  Receive error */
+#define ETH_RDES0_RWT                (1 << 4)  /* Bit 4:  Receive watchdog timeout */
+#define ETH_RDES0_FT                 (1 << 5)  /* Bit 5:  Frame type */
+#define ETH_RDES0_LC                 (1 << 6)  /* Bit 6:  Late collision */
+#define ETH_RDES0_TSA                (1 << 7)  /* Bit 7:  Time stamp available */
+#define ETH_RDES0_LS                 (1 << 8)  /* Bit 8:  Last descriptor */
+#define ETH_RDES0_FS                 (1 << 9)  /* Bit 9:  First descriptor */
+#define ETH_RDES0_VLAN               (1 << 10) /* Bit 10: VLAN tag */
+#define ETH_RDES0_OE                 (1 << 11) /* Bit 11: Overflow error */
+#define ETH_RDES0_LE                 (1 << 12) /* Bit 12: Length error */
+#define ETH_RDES0_SAF                (1 << 13) /* Bit 13: Source address filter fail */
+#define ETH_RDES0_DE                 (1 << 14) /* Bit 14: Descriptor error */
+#define ETH_RDES0_ES                 (1 << 15) /* Bit 15: Error summary */
+#define ETH_RDES0_FL_SHIFT           (16)      /* Bits 16-29: Frame length */
+#define ETH_RDES0_FL_MASK            (0x3fff << ETH_RDES0_FL_SHIFT)
+#define ETH_RDES0_AFM                (1 << 30) /* Bit 30: Destination address filter fail */
+#define ETH_RDES0_OWN                (1 << 31) /* Bit 31: Own bit */
+
+/* RDES1: Receive descriptor Word1 */
+
+#define ETH_RDES1_RBS1_SHIFT         (0)       /* Bits 0-12: Receive buffer 1 size */
+#define ETH_RDES1_RBS1_MASK          (0x1fff << ETH_RDES1_RBS1_SHIFT)
+                                               /* Bit 13: Reserved */
+#define ETH_RDES1_RCH                (1 << 14) /* Bit 14: Second address chained */
+#define ETH_RDES1_RER                (1 << 15) /* Bit 15: Receive end of ring */
+#define ETH_RDES1_RBS2_SHIFT         (16)      /* Bits 16-28: Receive buffer 2 size */
+#define ETH_RDES1_RBS2_MASK          (0x1fff << ETH_RDES1_RBS2_SHIFT)
+                                               /* Bit 29-31: Reserved */
+/* RDES2: Receive descriptor Word2 (32-bit address) */
+/* RDES3: Receive descriptor Word3 (32-bit address) */
+
+/* RDES4: Receive descriptor Word4 */
+
+                                               /* Bits 0-5: Reserved */
+#define ETH_RDES4_IPV4               (1 << 6)  /* Bit 6:  IPv4 packet received */
+#define ETH_RDES4_IPV6               (1 << 7)  /* Bit 7:  IPv6 packet received */
+#define ETH_RDES4_MT_SHIFT           (8)       /* Bits 8-11: Message type */
+#define ETH_RDES4_MT_MASK            (15 << ETH_RDES4_MT_SHIFT)
+#  define ETH_RDES4_MT_NONE          (0 << ETH_RDES4_MT_SHIFT)  /* No PTP message received */
+#  define ETH_RDES4_MT_SYNC          (1 << ETH_RDES4_MT_SHIFT)  /* SYNC (all clock types) */
+#  define ETH_RDES4_MT_FOLLOWUP      (2 << ETH_RDES4_MT_SHIFT)  /* Follow_Up (all clock types) */
+#  define ETH_RDES4_MT_DELAYREQ      (3 << ETH_RDES4_MT_SHIFT)  /* Delay_Req (all clock types) */
+#  define ETH_RDES4_MT_DELAYRESP     (4 << ETH_RDES4_MT_SHIFT)  /* Delay_Resp (all clock types) */
+#  define ETH_RDES4_MT_PDELREQAM     (5 << ETH_RDES4_MT_SHIFT)  /* Pdelay_Req (in peer-to-peer
+                                                                 * transparent clock) */
+#  define ETH_RDES4_MT_PDELREQMM     (6 << ETH_RDES4_MT_SHIFT)  /* Pdelay_Resp (in peer-to-peer
+                                                                 * transparent clock) */
+#  define ETH_RDES4_MT_PDELREQFUS    (7 << ETH_RDES4_MT_SHIFT)  /* Pdelay_Resp_Follow_Up (in
+                                                                 * peer-to-peer transparent clock) */
+#  define ETH_RDES4_MT_PDELREQFUS    (8 << ETH_RDES4_MT_SHIFT)  /* Announce */
+#  define ETH_RDES4_MT_PDELREQFUS    (9 << ETH_RDES4_MT_SHIFT)  /* Management */
+#  define ETH_RDES4_MT_PDELREQFUS    (10 << ETH_RDES4_MT_SHIFT) /* Signaling */
+#  define ETH_RDES4_MT_PDELREQFUS    (15 << ETH_RDES4_MT_SHIFT) /* PTP packet with Reserved message type */
+#define ETH_RDES4_PTPTYPE            (1 << 12) /* Bit 12: PTP frame type */
+#define ETH_RDES4_PTPVERSION         (1 << 13) /* Bit 13: PTP version */
+                                               /* Bits 14-31:  Reserved */
+
+/* RDES5: Receive descriptor Word5 - Reserved */
+/* RDES6: Receive descriptor Word6 (32-bit time stamp) */
+/* RDES7: Receive descriptor Word7 (32-bit time stamp) */
+
+/****************************************************************************************************
+ * Public Types
+ ****************************************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/* Ethernet TX DMA Descriptor.  Descriptor size can be 4 DWORDS (16 bytes) or 8 DWORDS (32 bytes)
+ * depending on the setting of the ATDS bit in the DMA Bus Mode register.
+ */ 
+
+struct eth_txdesc_s
+{
+  /* Normal DMA descriptor words */
+
+  volatile uint32_t tdes0;   /* Status */
+  volatile uint32_t tdes1;   /* Control and buffer1/2 lengths */
+  volatile uint32_t tdes2;   /* Buffer1 address pointer */
+  volatile uint32_t tdes3;   /* Buffer2 or next descriptor address pointer */
+
+  /* Alternate DMA descriptor with time stamp */
+
+#ifdef CONFIG_LPC43_ETH_ALTDESC
+  volatile uint32_t tdes4;   /* Reserved */
+  volatile uint32_t tdes5;   /* Reserved */
+  volatile uint32_t tdes6;   /* Time Stamp Low value for transmit and receive */
+  volatile uint32_t tdes7;   /* Time Stamp High value for transmit and receive */
+#endif
+};
+
+/* Ethernet RX DMA Descriptor.  Descriptor size can be 4 DWORDS (16 bytes) or 8 DWORDS (32 bytes)
+ * depending on the setting of the ATDS bit in the DMA Bus Mode register.
+ */ 
+
+struct eth_rxdesc_s
+{
+  volatile uint32_t rdes0;   /* Status */
+  volatile uint32_t rdes1;   /* Control and buffer1/2 lengths */
+  volatile uint32_t rdes2;   /* Buffer1 address pointer */
+  volatile uint32_t rdes3;   /* Buffer2 or next descriptor address pointer */
+
+  /* Alternate DMA descriptor with time stamp and PTP support */
+
+#ifdef CONFIG_LPC43_ETH_ALTDESC
+  volatile uint32_t rdes4;   /* Extended status for PTP receive descriptor */
+  volatile uint32_t rdes5;   /* Reserved */
+  volatile uint32_t rdes6;   /* Time Stamp Low value for transmit and receive */
+  volatile uint32_t rdes7;   /* Time Stamp High value for transmit and receive */
+#endif
+};
+
+/****************************************************************************************************
+ * Public Functions
+ ****************************************************************************************************/
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C" {
+#else
+#define EXTERN extern
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* LPC43_NETHERNET > 0 */
+#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_ETHERNET_H */
+
diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_evntmntr.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_evntmntr.h
new file mode 100644
index 000000000..a12112ece
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_evntmntr.h
@@ -0,0 +1,150 @@
+/****************************************************************************************************
+ * arch/arm/src/lpc43xx/chip/lpc43_eventmntr.h
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_EVNTMNTR_H
+#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_EVNTMNTR_H
+
+/****************************************************************************************************
+ * Included Files
+ ****************************************************************************************************/
+
+#include <nuttx/config.h>
+
+/****************************************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************************************/
+/* Register Offsets *********************************************************************************/
+
+#define LPC43_EMR_CONTROL_OFFSET       0x0004 /* Event Monitor/Recorder Control register */
+#define LPC43_EMR_STATUS_OFFSET        0x0000 /* Event Monitor/Recorder Status register */
+#define LPC43_EMR_COUNTERS_OFFSET      0x0008 /* Event Monitor/Recorder Counters register */
+
+#define LPC43_EMR_FIRSTSTAMP_OFFSET(n) (0x0010 + ((n) << 2))
+#define LPC43_EMR_FIRSTSTAMP0_OFFSET   0x0010 /* Event Monitor/Recorder First Stamp register Ch0 */
+#define LPC43_EMR_FIRSTSTAMP1_OFFSET   0x0014 /* Event Monitor/Recorder First Stamp register Ch1 */
+#define LPC43_EMR_FIRSTSTAMP2_OFFSET   0x0018 /* Event Monitor/Recorder First Stamp register Ch2 */
+
+#define LPC43_EMR_LASTSTAMP_OFFSET(n)  (0x0020 + ((n) << 2))
+#define LPC43_EMR_LASTSTAMP0_OFFSET    0x0020 /* Event Monitor/Recorder Last Stamp register Ch0 */
+#define LPC43_EMR_LASTSTAMP1_OFFSET    0x0024 /* Event Monitor/Recorder Last Stamp register Ch1 */
+#define LPC43_EMR_LASTSTAMP2_OFFSET    0x0028 /* Event Monitor/Recorder Last Stamp register Ch2 */
+
+/* Register Addresses *******************************************************************************/
+
+#define LPC43_EMR_CONTROL              (LPC43_EVNTMNTR_BASE+LPC43_EMR_CONTROL_OFFSET)
+#define LPC43_EMR_STATUS               (LPC43_EVNTMNTR_BASE+LPC43_EMR_STATUS_OFFSET)
+#define LPC43_EMR_COUNTERS             (LPC43_EVNTMNTR_BASE+LPC43_EMR_COUNTERS_OFFSET)
+
+#define LPC43_EMR_FIRSTSTAMP(n)        (LPC43_EVNTMNTR_BASE+LPC43_EMR_FIRSTSTAMP_OFFSET(n))
+#define LPC43_EMR_FIRSTSTAMP0          (LPC43_EVNTMNTR_BASE+LPC43_EMR_FIRSTSTAMP0_OFFSET)
+#define LPC43_EMR_FIRSTSTAMP1          (LPC43_EVNTMNTR_BASE+LPC43_EMR_FIRSTSTAMP1_OFFSET)
+#define LPC43_EMR_FIRSTSTAMP2          (LPC43_EVNTMNTR_BASE+LPC43_EMR_FIRSTSTAMP2_OFFSET)
+
+#define LPC43_EMR_LASTSTAMP(n)         (LPC43_EVNTMNTR_BASE+LPC43_EMR_LASTSTAMP_OFFSET(n))
+#define LPC43_EMR_LASTSTAMP0           (LPC43_EVNTMNTR_BASE+LPC43_EMR_LASTSTAMP0_OFFSET)
+#define LPC43_EMR_LASTSTAMP1           (LPC43_EVNTMNTR_BASE+LPC43_EMR_LASTSTAMP1_OFFSET)
+#define LPC43_EMR_LASTSTAMP2           (LPC43_EVNTMNTR_BASE+LPC43_EMR_LASTSTAMP2_OFFSET)
+
+/* Register Bit Definitions *************************************************************************/
+
+/* Event Monitor/Recorder Control register */
+
+#define EMR_CONTROL_INTWAKE_EN0        (1 << 0)  /* Bit 0:  Interrupt and wakeup enable Ch0 */
+#define EMR_CONTROL_GPCLEAR_EN0        (1 << 1)  /* Bit 1:  Enables auto clearing of RTC GP regs Ch0 */
+#define EMR_CONTROL_POL0               (1 << 2)  /* Bit 2:  Selects polarity of input pin WAKEUP0 */
+#define EMR_CONTROL_EV0_INPUT_EN       (1 << 3)  /* Bit 3:  Event enable control Ch0 */
+                                                 /* Bits 4-9: Reserved */
+#define EMR_CONTROL_INTWAKE_EN1        (1 << 10) /* Bit 10: Interrupt and wakeup enable Ch1 */
+#define EMR_CONTROL_GPCLEAR_EN1        (1 << 11) /* Bit 11: Enables auto clearing the RTC GP regs Ch1 */
+#define EMR_CONTROL_POL1               (1 << 12) /* Bit 12: Selects polarity of input pin WAKEUP1 */
+#define EMR_CONTROL_EV1_INPUT_EN       (1 << 13) /* Bit 13: Event enable control Ch1 */
+                                                 /* Bits 14-19: Reserved */
+#define EMR_CONTROL_INTWAKE_EN2        (1 << 20) /* Bit 20: Interrupt and wakeup enable Ch2 */
+#define EMR_CONTROL_GPCLEAR_EN2        (1 << 21) /* Bit 21: Enables auto clearing of RTC GP regs Ch2 */
+#define EMR_CONTROL_POL2               (1 << 22) /* Bit 22: Selects polarity of input pin WAKEUP2 */
+#define EMR_CONTROL_EV2_INPUT_EN       (1 << 23) /* Bit 23: Event enable control Ch2 */
+                                                 /* Bits 24-29: Reserved */
+#define EMR_CONTROL_ERMODE_SHIFT       (30)      /* Bits 30-31: Enable Event Monitor/Recorder */
+#define EMR_CONTROL_ERMODE_MASK        (3 << EMR_CONTROL_ERMODE_SHIFT)
+#  define EMR_CONTROL_ERMODE_DISABLE   (0 << EMR_CONTROL_ERMODE_SHIFT) /* Disable Event Monitor/Recorder clocks */
+#  define EMR_CONTROL_ERMODE_16Hz      (1 << EMR_CONTROL_ERMODE_SHIFT) /* 16 Hz sample clock */
+#  define EMR_CONTROL_ERMODE_64Hz      (2 << EMR_CONTROL_ERMODE_SHIFT) /* 64 Hz sample clock */
+#  define EMR_CONTROL_ERMODE_1KHz      (3 << EMR_CONTROL_ERMODE_SHIFT) /* 1 kHz sample clock */
+
+/* Event Monitor/Recorder Status register */
+
+#define EMR_STATUS_EV0                 (1 << 0)  /* Bit 0:  Channel0 event flag (WAKEUP0 pin) */
+#define EMR_STATUS_EV1                 (1 << 1)  /* Bit 1:  Channel1 Event flag (WAKEUP1 pin) */
+#define EMR_STATUS_EV2                 (1 << 2)  /* Bit 2:  Channel2 Event flag (WAKEUP2 pin) */
+#define EMR_STATUS_GPCLR               (1 << 3)  /* Bit 3:  General purpose register asynchronous clear flag */
+                                                 /* Bits 4-30: Reserved */
+#define EMR_STATUS_WAKEUP              (1 << 31) /* Bit 31:  WAKEUP Interrupt/wakeup request flag */
+
+/* Event Monitor/Recorder Counters register */
+
+#define EMR_COUNTERS_COUNTER0_SHIFT    (0)       /* Bits 0-2: Value of the counter for Event 0 */
+#define EMR_COUNTERS_COUNTER0_MASK     (7 << EMR_COUNTERS_COUNTER0_SHIFT)
+                                                 /* Bits 3-7: Reserved */
+#define EMR_COUNTERS_COUNTER1_SHIFT    (8)       /* Bits 8-10: Value of the counter for event 1 */
+#define EMR_COUNTERS_COUNTER1_MASK     (8 << EMR_COUNTERS_COUNTER1_SHIFT)
+                                                 /* Bits 11-15: Reserved */
+#define EMR_COUNTERS_COUNTER2_SHIFT    (16)      /* Bits 16-18: Value of the counter for event 2 */
+#define EMR_COUNTERS_COUNTER2_MASK     (7 << EMR_COUNTERS_COUNTER2_SHIFT)
+                                                 /* Bits 19-31: Reserved */
+/* Event Monitor/Recorder First/Last Stamp registers */
+
+#define EMR_STAMP_SEC_SHIFT            (0)       /* Bits 0-5: Seconds value 0-59 */
+#define EMR_STAMP_SEC_MASK             (63 << EMR_STAMP_SEC_SHIFT)
+#define EMR_STAMP_MIN_SHIFT            (6)       /* Bits 6-11: Minutes value 0-59 */
+#define EMR_STAMP_MIN_MASK             (63 << EMR_STAMP_MIN_SHIFT)
+#define EMR_STAMP_HOUR_SHIFT           (12)      /* Bits 12-16: Hours value 0-23 */
+#define EMR_STAMP_HOUR_MASK            (31 << EMR_STAMP_HOUR_SHIFT)
+#define EMR_STAMP_DOY_SHIFT            (17)      /* Bits 17-25: Day of Year value1-366 */
+#define EMR_STAMP_DOY_MASK             (511 << EMR_STAMP_DOY_SHIFT)
+                                                 /* Bits 26-31: Reserved */
+
+/****************************************************************************************************
+ * Public Types
+ ****************************************************************************************************/
+
+/****************************************************************************************************
+ * Public Data
+ ****************************************************************************************************/
+
+/****************************************************************************************************
+ * Public Functions
+ ****************************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_EVNTMNTR_H */
diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_evntrtr.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_evntrtr.h
new file mode 100644
index 000000000..644e6758e
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_evntrtr.h
@@ -0,0 +1,159 @@
+/************************************************************************************
+ * arch/arm/src/lpc43xx/chip/lpc43_evntrtr.h
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_EVNTRTR_H
+#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_EVNTRTR_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+/* Register Offsets *****************************************************************/
+
+#define LPC43_EVNTRTR_HILO_OFFSET    0x0000 /* Level configuration register */
+#define LPC43_EVNTRTR_EDGE_OFFSET    0x0004 /* Edge configuration */
+
+#define LPC43_EVNTRTR_CLREN_OFFSET   0x0fd8 /* Clear event enable register */
+#define LPC43_EVNTRTR_SETEN_OFFSET   0x0fdc /* Set event enable register */
+#define LPC43_EVNTRTR_STATUS_OFFSET  0x0fe0 /* Event Status register */
+#define LPC43_EVNTRTR_ENABLE_OFFSET  0x0fe4 /* Event Enable register */
+#define LPC43_EVNTRTR_CLRSTAT_OFFSET 0x0fe8 /* Clear event status register */
+#define LPC43_EVNTRTR_SETSTAT_OFFSET 0x0fec /* Set event status register */
+
+/* Register Addresses ***************************************************************/
+
+#define LPC43_EVNTRTR_HILO           (LPC43_EVNTRTR_BASE+LPC43_EVNTRTR_HILO_OFFSET)
+#define LPC43_EVNTRTR_EDGE           (LPC43_EVNTRTR_BASE+LPC43_EVNTRTR_EDGE_OFFSET)
+
+#define LPC43_EVNTRTR_CLREN          (LPC43_EVNTRTR_BASE+LPC43_EVNTRTR_CLREN_OFFSET)
+#define LPC43_EVNTRTR_SETEN          (LPC43_EVNTRTR_BASE+LPC43_EVNTRTR_SETEN_OFFSET)
+#define LPC43_EVNTRTR_STATUS         (LPC43_EVNTRTR_BASE+LPC43_EVNTRTR_STATUS_OFFSET)
+#define LPC43_EVNTRTR_ENABLE         (LPC43_EVNTRTR_BASE+LPC43_EVNTRTR_ENABLE_OFFSET)
+#define LPC43_EVNTRTR_CLRSTAT        (LPC43_EVNTRTR_BASE+LPC43_EVNTRTR_CLRSTAT_OFFSET)
+#define LPC43_EVNTRTR_SETSTAT        (LPC43_EVNTRTR_BASE+LPC43_EVNTRTR_SETSTAT_OFFSET)
+
+/* Register Bit Definitions *********************************************************/
+
+/* Event router inputs.  Bit settings common to all registers */
+
+#define EVNTRTR_SOURCE_WAKEUP0       0  /* WAKEUP0 pin */
+#define EVNTRTR_SOURCE_WAKEUP1       1  /* WAKEUP1 pin */
+#define EVNTRTR_SOURCE_WAKEUP2       2  /* WAKEUP2 pin */
+#define EVNTRTR_SOURCE_WAKEUP3       3  /* WAKEUP3 pin */
+#define EVNTRTR_SOURCE_ATIMER        4  /* Alarm timer interrupt */
+#define EVNTRTR_SOURCE_RTC           5  /* RTC interrupt and event recorder/monitor interrupt */
+#define EVNTRTR_SOURCE_BOD           6  /* BOD trip level 1interrupt */
+#define EVNTRTR_SOURCE_WWDT          7  /* WWDT interrupt */
+#define EVNTRTR_SOURCE_ETHERNET      8  /* Ethernet wake-up packet indicator */
+#define EVNTRTR_SOURCE_USB0          9  /* USB0 wake-up request signal */
+#define EVNTRTR_SOURCE_USB1          10 /* USB1 AHB_NEED_CLK signal */
+#define EVNTRTR_SOURCE_SDMMC         11 /* SD/MMC interrupt */
+#define EVNTRTR_SOURCE_CAN           12 /* C_CAN0 | C_CAN1 interrupt */
+#define EVNTRTR_SOURCE_TIM2          13 /* Combined timer output 2 (SCT output 2 | TIMER0 Ch2) */
+#define EVNTRTR_SOURCE_TIM6          14 /* Combined timer output 6 (SCT output 6 | TIMER1 Ch2) */
+#define EVNTRTR_SOURCE_QEI           15 /* QEI interrupt */
+#define EVNTRTR_SOURCE_TIM14         16 /* Combined timer output 14 (SCT output 14 | TIMER3 Ch2) */
+                                        /* 17-18: Reserved */              
+#define EVNTRTR_SOURCE_RESET         19 /* Reset event */
+
+#define EVNTRTR_WAKEUP0              (1 << EVNTRTR_SOURCE_WAKEUP0)
+#define EVNTRTR_WAKEUP1              (1 << EVNTRTR_SOURCE_WAKEUP1)
+#define EVNTRTR_WAKEUP2              (1 << EVNTRTR_SOURCE_WAKEUP2)
+#define EVNTRTR_WAKEUP3              (1 << EVNTRTR_SOURCE_WAKEUP3)
+#define EVNTRTR_ATIMER               (1 << EVNTRTR_SOURCE_ATIMER)
+#define EVNTRTR_RTC                  (1 << EVNTRTR_SOURCE_RTC)
+#define EVNTRTR_BOD                  (1 << EVNTRTR_SOURCE_BOD)
+#define EVNTRTR_WWDT                 (1 << EVNTRTR_SOURCE_WWDT)
+#define EVNTRTR_ETH                  (1 << EVNTRTR_SOURCE_ETHERNET)
+#define EVNTRTR_USB0                 (1 << EVNTRTR_SOURCE_USB0)
+#define EVNTRTR_USB1                 (1 << EVNTRTR_SOURCE_USB1)
+#define EVNTRTR_SDMMC                (1 << EVNTRTR_SOURCE_SDMMC)
+#define EVNTRTR_CAN                  (1 << EVNTRTR_SOURCE_CAN)
+#define EVNTRTR_TIM2                 (1 << EVNTRTR_SOURCE_TIM2)
+#define EVNTRTR_TIM6                 (1 << EVNTRTR_SOURCE_TIM6)
+#define EVNTRTR_QEI                  (1 << EVNTRTR_SOURCE_QEI)
+#define EVNTRTR_TIM14                (1 << EVNTRTR_SOURCE_TIM14)
+#define EVNTRTR_RESET                (1 << EVNTRTR_SOURCE_RESET)
+
+/* Level configuration register */
+
+#define EVNTRTR_HILO(n)              (1 << (n))
+
+/* Edge configuration */
+
+#define EVNTRTR_EDGE(n)              (1 << (n))
+
+/* Clear event enable register */
+
+#define EVNTRTR_CLREN(n)             (1 << (n))
+
+/* Set event enable register */
+
+#define EVNTRTR_SETEN(n)             (1 << (n))
+
+/* Event Status register */
+
+#define EVNTRTR_STATUS(n)            (1 << (n))
+
+/* Event Enable register */
+
+#define EVNTRTR_ENABLE(n)            (1 << (n))
+
+/* Clear event status register */
+
+#define EVNTRTR_CLRSTAT(n)           (1 << (n))
+
+/* Set event status register */
+
+#define EVNTRTR_SETSTAT(n)           (1 << (n))
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_EVNTRTR_H */
diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_flash.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_flash.h
new file mode 100644
index 000000000..4f99484da
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_flash.h
@@ -0,0 +1,187 @@
+/************************************************************************************
+ * arch/arm/src/lpc43xx/chip/lpc43_flash.h
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_FLASH_H
+#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_FLASH_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+/* The AES is controlled through a set of simple API calls located in the LPC43xx
+ * ROM.  This value holds the pointer to the AES driver table.
+ */
+
+#define LPC43_ROM_IAP_DRIVER_TABLE LPC43_ROM_DRIVER_TABLE0
+
+#define IAP_LOCATION *(volatile unsigned int *)LPC43_ROM_IAP_DRIVER_TABLE;
+
+/* General usage:
+ *
+ * Declare a function pointer in your code like:
+ *
+ *  iap_t iap = (iap_t)IAP_LOCATION;
+ *
+ * Then call the IAP using the function pointe like:
+ *
+ *  unsigned long command[6];
+ *  unsigned long result[5];
+ *  ...
+ *  iap(command, result);
+ */
+
+/* IAP Commands
+ *
+ *   See tables 1042-1053 in the "LPC43xx User Manual" (UM10503), Rev. 1.2, 8 June
+ *   2012, NXP for definitions descriptions of each IAP command.
+ */
+
+#define IAP_INIT            49   /* Initialization */
+#define IAP_WRITE_PREPARE   50   /* Prepare sectors for write operation */
+#define IAP_WRITE           51   /* Copy RAM to Flash */
+#define IAP_ERASE_SECTOR    52   /* Erase sectors */
+#define IAP_BLANK_CHECK     53   /* Blank check sectors */
+#define IAP_PART_ID         54   /* Read part ID */
+#define IAP_BOOT_VERSION    55   /* Read Boot Code version */
+#define IAP_SERIAL_NUMBER   58   /* Read device serial number */
+#define IAP_COMPARE         56   /* Compare */
+#define IAP_REINVOKE        57   /* Reinvoke ISP */
+#define IAP_ERASE_PAGE      59   /* Erase page */
+#define IAP_SET_BANK        60   /* Set active boot flash bank */
+
+/* ISP/IAP return codes */
+
+/* Command is executed successfully. Sent by ISP handler only when command given by
+ * the host has been completely and successfully executed.
+ */
+
+#define CMD_SUCCESS 0
+
+/* Invalid command */
+
+#define INVALID_COMMAND
+
+/* Source address is not on word boundary. */
+
+#define SRC_ADDR_ERROR 2
+
+/* Destination address not on word or 256 byte boundary. */
+
+#define DST_ADDR_ERROR 3
+
+/* Source address is not mapped in the memory map. Count value is taken into
+ * consideration where applicable.
+ */
+
+#define SRC_ADDR_NOT_MAPPED 4
+
+/* Destination address is not mapped in the memory map. Count value is taken into
+ * consideration where applicable.
+ */
+
+#define DST_ADDR_NOT_MAPPED 5
+
+/* Byte count is not multiple of 4 or is not a permitted value. */
+
+#define COUNT_ERROR 6
+
+/* Sector number is invalid or end sector number is greater than start sector number. */
+
+#define INVALID_SECTOR 7
+
+/* Sector is not blank. */
+
+#define SECTOR_NOT_BLANK 8
+
+/* Command to prepare sector for write operation was not executed. */
+
+#define SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION 9
+
+/* Source and destination data not equal. */
+
+#define COMPARE_ERROR 10
+
+/* Flash programming hardware interface is busy. */
+
+#define BUSY 11
+
+/* Insufficient number of parameters or invalid parameter. */
+
+#define PARAM_ERROR 12
+
+/* Address is not on word boundary. */
+
+#define ADDR_ERROR 13
+
+/* Address is not mapped in the memory map. Count value is taken in to consideration
+ * where applicable.
+ */
+
+#define ADDR_NOT_MAPPED 14
+
+/* Command is locked. */
+
+#define CMD_LOCKED 15
+
+/* Unlock code is invalid. */
+
+#define INVALID_CODE 16
+
+/* Invalid baud rate setting. */
+
+#define INVALID_BAUD_RATE 17
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/* IAP function pointer */
+
+typedef void (*iap_t)(unsigned int *cmd, unsigned int *result);
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_FLASH_H */
diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_gima.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_gima.h
new file mode 100644
index 000000000..993242ebe
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_gima.h
@@ -0,0 +1,336 @@
+/****************************************************************************************************
+ * arch/arm/src/lpc43xx/chip/lpc43_gima.h
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_GIMA_H
+#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_GIMA_H
+
+/****************************************************************************************************
+ * Included Files
+ ****************************************************************************************************/
+
+#include <nuttx/config.h>
+
+/****************************************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************************************/
+/* Register Offsets *********************************************************************************/
+
+/* Timer capture input multiplexor registers */
+
+#define LPC43_GIMA_CAP_OFFSET(t,i)    (((t) << 4) | ((i) << 2))
+#define LPC43_GIMA_CAP00_OFFSET       0x0000  /* Timer 0 CAP0_0 capture input multiplexer (GIMA output 0) */
+#define LPC43_GIMA_CAP01_OFFSET       0x0004  /* Timer 0 CAP0_1 capture input multiplexer (GIMA output 1) */
+#define LPC43_GIMA_CAP02_OFFSET       0x0008  /* Timer 0 CAP0_2 capture input multiplexer (GIMA output 2) */
+#define LPC43_GIMA_CAP03_OFFSET       0x000c  /* Timer 0 CAP0_3 capture input multiplexer (GIMA output 3) */
+#define LPC43_GIMA_CAP10_OFFSET       0x0010  /* Timer 1 CAP1_0 capture input multiplexer (GIMA output 4) */
+#define LPC43_GIMA_CAP11_OFFSET       0x0014  /* Timer 1 CAP1_1 capture input multiplexer (GIMA output 5) */
+#define LPC43_GIMA_CAP12_OFFSET       0x0018  /* Timer 1 CAP1_2 capture input multiplexer (GIMA output 6) */
+#define LPC43_GIMA_CAP13_OFFSET       0x001c  /* Timer 1 CAP1_3 capture input multiplexer (GIMA output 7) */
+#define LPC43_GIMA_CAP20_OFFSET       0x0020  /* Timer 2 CAP2_0 capture input multiplexer (GIMA output 8) */
+#define LPC43_GIMA_CAP21_OFFSET       0x0024  /* Timer 2 CAP2_1 capture input multiplexer (GIMA output 9) */
+#define LPC43_GIMA_CAP22_OFFSET       0x0028  /* Timer 2 CAP2_2 capture input multiplexer (GIMA output 10) */
+#define LPC43_GIMA_CAP23_OFFSET       0x002c  /* Timer 2 CAP2_3 capture input multiplexer (GIMA output 11) */
+#define LPC43_GIMA_CAP30_OFFSET       0x0030  /* Timer 3 CAP3_0 capture input multiplexer (GIMA output 12) */
+#define LPC43_GIMA_CAP31_OFFSET       0x0034  /* Timer 3 CAP3_1 capture input multiplexer (GIMA output 13) */
+#define LPC43_GIMA_CAP32_OFFSET       0x0038  /* Timer 3 CAP3_2 capture input multiplexer (GIMA output 14) */
+#define LPC43_GIMA_CAP33_OFFSET       0x003c  /* Timer 3 CAP3_3 capture input multiplexer (GIMA output 15) */
+
+#define LPC43_GIMA_CTIN_OFFSET(i)     (0x0040 + ((i) << 2))
+#define LPC43_GIMA_CTIN0_OFFSET       0x0040  /* SCT CTIN_0 capture input multiplexer (GIMA output 16) */
+#define LPC43_GIMA_CTIN1_OFFSET       0x0044  /* SCT CTIN_1 capture input multiplexer (GIMA output 17) */
+#define LPC43_GIMA_CTIN2_OFFSET       0x0048  /* SCT CTIN_2 capture input multiplexer (GIMA output 18) */
+#define LPC43_GIMA_CTIN3_OFFSET       0x004c  /* SCT CTIN_3 capture input multiplexer (GIMA output 19) */
+#define LPC43_GIMA_CTIN4_OFFSET       0x0050  /* SCT CTIN_4 capture input multiplexer (GIMA output 20) */
+#define LPC43_GIMA_CTIN5_OFFSET       0x0054  /* SCT CTIN_5 capture input multiplexer (GIMA output 21) */
+#define LPC43_GIMA_CTIN6_OFFSET       0x0058  /* SCT CTIN_6 capture input multiplexer (GIMA output 22) */
+#define LPC43_GIMA_CTIN7_OFFSET       0x005c  /* SCT CTIN_7 capture input multiplexer (GIMA output 23) */
+
+#define LPC43_GIMA_VADCTRIG_OFFSET    0x0060  /* VADC trigger input multiplexer (GIMA output 24) */
+#define LPC43_GIMA_EVNTRTR13_OFFSET   0x0064  /* Event router input 13 multiplexer (GIMA output 25) */
+#define LPC43_GIMA_EVNTRTR14_OFFSET   0x0068  /* Event router input 14 multiplexer (GIMA output 26) */
+#define LPC43_GIMA_EVNTRTR16_OFFSET   0x006c  /* Event router input 16 multiplexer (GIMA output 27) */
+#define LPC43_GIMA_ADCSTART0_OFFSET   0x0070  /* ADC start0 input multiplexer (GIMA output 28) */
+#define LPC43_GIMA_ADCSTART1_OFFSET   0x0074  /* ADC start1 input multiplexer (GIMA output 29) */
+
+/* Register Addresses *******************************************************************************/
+
+#define LPC43_GIMA_CAP(t,i)           (LPC43_GIMA_BASE+LPC43_GIMA_CAP_OFFSET(t,i))
+#define LPC43_GIMA_CAP00              (LPC43_GIMA_BASE+LPC43_GIMA_CAP00_OFFSET)
+#define LPC43_GIMA_CAP01              (LPC43_GIMA_BASE+LPC43_GIMA_CAP01_OFFSET)
+#define LPC43_GIMA_CAP02              (LPC43_GIMA_BASE+LPC43_GIMA_CAP02_OFFSET)
+#define LPC43_GIMA_CAP03              (LPC43_GIMA_BASE+LPC43_GIMA_CAP03_OFFSET)
+#define LPC43_GIMA_CAP10              (LPC43_GIMA_BASE+LPC43_GIMA_CAP10_OFFSET)
+#define LPC43_GIMA_CAP11              (LPC43_GIMA_BASE+LPC43_GIMA_CAP11_OFFSET)
+#define LPC43_GIMA_CAP12              (LPC43_GIMA_BASE+LPC43_GIMA_CAP12_OFFSET)
+#define LPC43_GIMA_CAP13              (LPC43_GIMA_BASE+LPC43_GIMA_CAP13_OFFSET)
+#define LPC43_GIMA_CAP20              (LPC43_GIMA_BASE+LPC43_GIMA_CAP20_OFFSET)
+#define LPC43_GIMA_CAP21              (LPC43_GIMA_BASE+LPC43_GIMA_CAP21_OFFSET)
+#define LPC43_GIMA_CAP22              (LPC43_GIMA_BASE+LPC43_GIMA_CAP22_OFFSET)
+#define LPC43_GIMA_CAP23              (LPC43_GIMA_BASE+LPC43_GIMA_CAP23_OFFSET)
+#define LPC43_GIMA_CAP30              (LPC43_GIMA_BASE+LPC43_GIMA_CAP30_OFFSET)
+#define LPC43_GIMA_CAP31              (LPC43_GIMA_BASE+LPC43_GIMA_CAP31_OFFSET)
+#define LPC43_GIMA_CAP32              (LPC43_GIMA_BASE+LPC43_GIMA_CAP32_OFFSET)
+#define LPC43_GIMA_CAP33              (LPC43_GIMA_BASE+LPC43_GIMA_CAP33_OFFSET)
+
+#define LPC43_GIMA_CTIN(i)            (LPC43_GIMA_BASE+LPC43_GIMA_CTIN_OFFSET(i))
+#define LPC43_GIMA_CTIN0              (LPC43_GIMA_BASE+LPC43_GIMA_CTIN0_OFFSET)
+#define LPC43_GIMA_CTIN1              (LPC43_GIMA_BASE+LPC43_GIMA_CTIN1_OFFSET)
+#define LPC43_GIMA_CTIN2              (LPC43_GIMA_BASE+LPC43_GIMA_CTIN2_OFFSET)
+#define LPC43_GIMA_CTIN3              (LPC43_GIMA_BASE+LPC43_GIMA_CTIN3_OFFSET)
+#define LPC43_GIMA_CTIN4              (LPC43_GIMA_BASE+LPC43_GIMA_CTIN4_OFFSET)
+#define LPC43_GIMA_CTIN5              (LPC43_GIMA_BASE+LPC43_GIMA_CTIN5_OFFSET)
+#define LPC43_GIMA_CTIN6              (LPC43_GIMA_BASE+LPC43_GIMA_CTIN6_OFFSET)
+#define LPC43_GIMA_CTIN7              (LPC43_GIMA_BASE+LPC43_GIMA_CTIN7_OFFSET)
+#define LPC43_GIMA_VADCTRIG           (LPC43_GIMA_BASE+LPC43_GIMA_VADCTRIG_OFFSET)
+#define LPC43_GIMA_EVNTRTR13          (LPC43_GIMA_BASE+LPC43_GIMA_EVNTRTR13_OFFSET)
+#define LPC43_GIMA_EVNTRTR14          (LPC43_GIMA_BASE+LPC43_GIMA_EVNTRTR14_OFFSET)
+#define LPC43_GIMA_EVNTRTR16          (LPC43_GIMA_BASE+LPC43_GIMA_EVNTRTR16_OFFSET)
+#define LPC43_GIMA_ADCSTART0          (LPC43_GIMA_BASE+LPC43_GIMA_ADCSTART0_OFFSET)
+#define LPC43_GIMA_ADCSTART1          (LPC43_GIMA_BASE+LPC43_GIMA_ADCSTART1_OFFSET)
+
+/* Register Bit Definitions *************************************************************************/
+
+/* Common register field definitions */
+
+#define GIMA_INV                      (1 << 0)  /* Bit 0:  Invert input  */
+#define GIMA_EDGE                     (1 << 1)  /* Bit 1:  Enable rising edge detection */
+#define GIMA_SYNCH                    (1 << 2)  /* Bit 2:  Enable synchronization */
+#define GIMA_PULSE                    (1 << 3)  /* Bit 3:  Enable single pulse generation */
+#define GIMA_SELECT_SHIFT             (4)       /* Bits 4-7: Select input */
+#define GIMA_SELECT_MASK              (15 << GIMA_SELECT_SHIFT)
+                                                /* Bits 8-31:  Reserved */
+/* Timer 0 CAP0_0 capture input multiplexer (GIMA output 0) */
+                                                /* Bits 4-7:  Same as the common definitions */
+#  define GIMA_CAP00_SELECT_CTIN0     (0 << GIMA_SELECT_SHIFT) /* CTIN_0 */
+#  define GIMA_CAP00_SELECT_SGPIO3    (1 << GIMA_SELECT_SHIFT) /* SGPIO3 */
+#  define GIMA_CAP00_SELECT_TOCAP0    (2 << GIMA_SELECT_SHIFT) /* T0_CAP0 */
+                                                /* Bits 8-31: Reserved */
+/* Timer 0 CAP0_1 capture input multiplexer (GIMA output 1) */
+                                                /* Bits 4-7:  Same as the common definitions */
+#  define GIMA_CAP01_SELECT_CTIN1     (0 << GIMA_SELECT_SHIFT) /* CTIN_1 */
+#  define GIMA_CAP01_SELECT_U2TX      (1 << GIMA_SELECT_SHIFT) /* USART2 TX active */
+#  define GIMA_CAP01_SELECT_TOCAP1    (2 << GIMA_SELECT_SHIFT) /* T0_CAP1 */
+                                                /* Bits 8-31: Reserved */
+/* Timer 0 CAP0_2 capture input multiplexer (GIMA output 2) */
+                                                /* Bits 4-7:  Same as the common definitions */
+#  define GIMA_CAP02_SELECT_CTIN2     (0 << GIMA_SELECT_SHIFT) /* CTIN_2 */
+#  define GIMA_CAP02_SELECT_SGPIO3D   (1 << GIMA_SELECT_SHIFT) /* SGPIO3_DIV */
+#  define GIMA_CAP02_SELECT_T0CAP2    (2 << GIMA_SELECT_SHIFT) /* T0_CAP2 */
+                                                /* Bits 8-31: Reserved */
+/* Timer 0 CAP0_3 capture input multiplexer (GIMA output 3) */
+                                                /* Bits 4-7:  Same as the common definitions */
+#  define GIMA_CAP03_SELECT_CTOUT15   (0 << GIMA_SELECT_SHIFT) /* CTOUT_15 or T3_MAT3 */
+#  define GIMA_CAP03_SELECT_T0CAP3    (1 << GIMA_SELECT_SHIFT) /* T0_CAP3 */
+#  define GIMA_CAP03_SELECT_T3MAT3    (2 << GIMA_SELECT_SHIFT) /* T3_MAT3 */
+                                                /* Bits 8-31: Reserved */
+/* Timer 1 CAP1_0 capture input multiplexer (GIMA output 4) */
+                                                /* Bits 4-7:  Same as the common definitions */
+#  define GIMA_CAP10_SELECT_CTIN0     (0 << GIMA_SELECT_SHIFT) /* CTIN_0 */
+#  define GIMA_CAP10_SELECT_SGPIO12   (1 << GIMA_SELECT_SHIFT) /* SGPIO12 */
+#  define GIMA_CAP10_SELECT_T1CAP0    (2 << GIMA_SELECT_SHIFT) /* T1_CAP0 */
+                                                /* Bits 8-31: Reserved */
+/* Timer 1 CAP1_1 capture input multiplexer (GIMA output 5) */
+                                                 /* Bits 4-7:  Same as the common definitions */
+#  define GIMA_CAP11_SELECT_CTIN3     (0 << GIMA_SELECT_SHIFT) /* CTIN_3 */
+#  define GIMA_CAP11_SELECT_U0TX      (1 << GIMA_SELECT_SHIFT) /* USART0 TX active */
+#  define GIMA_CAP11_SELECT_T1CAP1    (2 << GIMA_SELECT_SHIFT) /* T1_CAP1 */
+                                                /* Bits 8-31: Reserved */
+/* Timer 1 CAP1_2 capture input multiplexer (GIMA output 6) */
+                                                /* Bits 4-7:  Same as the common definitions */
+#  define GIMA_CAP12_SELECT_CTIN4     (0 << GIMA_SELECT_SHIFT) /* CTIN_4 */
+#  define GIMA_CAP12_SELECT_U0RX      (1 << GIMA_SELECT_SHIFT) /* USART0 RX active */
+#  define GIMA_CAP12_SELECT_T1CAP2    (2 << GIMA_SELECT_SHIFT) /* T1_CAP2 */
+                                                /* Bits 8-31: Reserved */
+/* Timer 1 CAP1_3 capture input multiplexer (GIMA output 7) */
+                                                /* Bits 4-7:  Same as the common definitions */
+#  define GIMA_CAP13_SELECT_CTOUT3    (0 << GIMA_SELECT_SHIFT) /* CTOUT_3 or T0_MAT3 */
+#  define GIMA_CAP13_SELECT_T1CAP3    (1 << GIMA_SELECT_SHIFT) /* T1_CAP3 */
+#  define GIMA_CAP13_SELECT_T0MAT3    (2 << GIMA_SELECT_SHIFT) /* T0_MAT3 */
+                                                /* Bits 8-31: Reserved */
+/* Timer 2 CAP2_0 capture input multiplexer (GIMA output 8) */
+                                                /* Bits 4-7:  Same as the common definitions */
+#  define GIMA_CAP20_SELECT_CTIN0     (0 << GIMA_SELECT_SHIFT) /* CTIN_0 */
+#  define GIMA_CAP20_SELECT_SGPIO12D  (1 << GIMA_SELECT_SHIFT) /* SGPIO12_DIV */
+#  define GIMA_CAP20_SELECT_T2CAP0    (2 << GIMA_SELECT_SHIFT) /* T2_CAP0 */
+                                                /* Bits 8-31: Reserved */
+/* Timer 2 CAP2_1 capture input multiplexer (GIMA output 9) */
+                                                /* Bits 4-7:  Same as the common definitions */
+#  define GIMA_CAP21_SELECT_CTIN1     (0 << GIMA_SELECT_SHIFT) /* CTIN_1 */
+#  define GIMA_CAP21_SELECT_U2TX      (1 << GIMA_SELECT_SHIFT) /* USART2 TX active */
+#  define GIMA_CAP21_SELECT_T2CAP1    (2 << GIMA_SELECT_SHIFT) /* T2_CAP1 */
+                                                /* Bits 8-31: Reserved */
+/* Timer 2 CAP2_2 capture input multiplexer (GIMA output 10) */
+                                                /* Bits 4-7:  Same as the common definitions */
+#  define GIMA_CAP22_SELECT_CTIN5     (0 << GIMA_SELECT_SHIFT) /* CTIN_5 */
+#  define GIMA_CAP22_SELECT_U2RX      (1 << GIMA_SELECT_SHIFT) /* USART2 RX active */
+#  define GIMA_CAP22_SELECT_I2S1TX    (2 << GIMA_SELECT_SHIFT) /* I2S1_TX_MWS */
+#  define GIMA_CAP22_SELECT_T2CAP2    (3 << GIMA_SELECT_SHIFT) /* T2_CAP2 */
+                                                /* Bits 8-31: Reserved */
+/* Timer 2 CAP2_3 capture input multiplexer (GIMA output 11) */
+                                                /* Bits 4-7:  Same as the common definitions */
+#  define GIMA_CAP23_SELECT_CTOUT7    (0 << GIMA_SELECT_SHIFT) /* CTOUT_7 or T1_MAT3 */
+#  define GIMA_CAP23_SELECT_T2CAP3    (1 << GIMA_SELECT_SHIFT) /* T2_CAP3 */
+#  define GIMA_CAP23_SELECT_T1MAT3    (2 << GIMA_SELECT_SHIFT) /* T1_MAT3 */
+                                                /* Bits 8-31: Reserved */
+/* Timer 3 CAP3_0 capture input multiplexer (GIMA output 12) */
+                                                /* Bits 4-7:  Same as the common definitions */
+#  define GIMA_CAP30_SELECT_CTIN0     (0 << GIMA_SELECT_SHIFT) /* CTIN_0 */
+#  define GIMA_CAP30_SELECT_I2S0RX    (1 << GIMA_SELECT_SHIFT) /* I2S0_RX_MWS */
+#  define GIMA_CAP30_SELECT_T3CAP0    (2 << GIMA_SELECT_SHIFT) /* T3_CAP0 */
+                                                /* Bits 8-31: Reserved */
+/* Timer 3 CAP3_1 capture input multiplexer (GIMA output 13) */
+                                                /* Bits 4-7:  Same as the common definitions */
+#  define GIMA_CAP31_SELECT_CTIN6     (0 << GIMA_SELECT_SHIFT) /* CTIN_6 */
+#  define GIMA_CAP31_SELECT_U3TX      (1 << GIMA_SELECT_SHIFT) /* USART3 TX active */
+#  define GIMA_CAP31_SELECT_I2S0TX    (2 << GIMA_SELECT_SHIFT) /* I2S0_TX_MWS */
+#  define GIMA_CAP31_SELECT_T3CAP1    (3 << GIMA_SELECT_SHIFT) /* T3_CAP1 */
+                                                /* Bits 8-31: Reserved */
+/* Timer 3 CAP3_2 capture input multiplexer (GIMA output 14) */
+                                                /* Bits 4-7:  Same as the common definitions */
+#  define GIMA_CAP32_SELECT_CTIN7     (0 << GIMA_SELECT_SHIFT) /* CTIN_7 */
+#  define GIMA_CAP32_SELECT_U3RX      (1 << GIMA_SELECT_SHIFT) /* USART3 RX active */
+#  define GIMA_CAP32_SELECT_SOF0      (2 << GIMA_SELECT_SHIFT) /* SOF0 (Start-Of-Frame USB0) */
+#  define GIMA_CAP32_SELECT_T3CAP2    (3 << GIMA_SELECT_SHIFT) /* T3_CAP2 */
+                                                /* Bits 8-31: Reserved */
+/* Timer 3 CAP3_3 capture input multiplexer (GIMA output 15) */
+                                                /* Bits 4-7:  Same as the common definitions */
+#  define GIMA_CAP33_SELECT_CTOUT11   (0 << GIMA_SELECT_SHIFT) /* CTOUT11 or T2_MAT3 */
+#  define GIMA_CAP33_SELECT_SOF1      (1 << GIMA_SELECT_SHIFT) /* SOF1 (Start-Of-Frame USB1) */
+#  define GIMA_CAP33_SELECT_T3CAP3    (2 << GIMA_SELECT_SHIFT) /* T3_CAP3 */
+#  define GIMA_CAP33_SELECT_T2MAT3    (3 << GIMA_SELECT_SHIFT) /* T2_MAT3 */
+                                                /* Bits 8-31: Reserved */
+/* SCT CTIN_0 capture input multiplexer (GIMA output 16) */
+                                                /* Bits 4-7:  Same as the common definitions */
+#  define GIMA_CTIN0_SELECT_CTIN0     (0 << GIMA_SELECT_SHIFT) /* CTIN_0 */
+#  define GIMA_CTIN0_SELECT_SGPIO3    (1 << GIMA_SELECT_SHIFT) /* SGPIO3 */
+#  define GIMA_CTIN0_SELECT_SGPIO3D   (2 << GIMA_SELECT_SHIFT) /* SGPIO3_DIV */
+                                                /* Bits 8-31: Reserved */
+/* SCT CTIN_1 capture input multiplexer (GIMA output 17) */
+                                                /* Bits 4-7:  Same as the common definitions */
+#  define GIMA_CTIN1_SELECT_CTIN1     (0 << GIMA_SELECT_SHIFT) /* CTIN_1 */
+#  define GIMA_CTIN1_SELECT_U2TX      (1 << GIMA_SELECT_SHIFT) /* USART2 TX active */
+#  define GIMA_CTIN1_SELECT_SGPIO12   (2 << GIMA_SELECT_SHIFT) /* SGPIO12 */
+                                                /* Bits 8-31: Reserved */
+/* SCT CTIN_2 capture input multiplexer (GIMA output 18) */
+                                                /* Bits 4-7:  Same as the common definitions */
+#  define GIMA_CTIN2_SELECT_CTIN2     (0 << GIMA_SELECT_SHIFT) /* CTIN_2 */
+#  define GIMA_CTIN2_SELECT_SGPIO12   (1 << GIMA_SELECT_SHIFT) /* SGPIO12 */
+#  define GIMA_CTIN2_SELECT_SGPIO12D  (2 << GIMA_SELECT_SHIFT) /* SGPIO12_DIV */
+                                                /* Bits 8-31: Reserved */
+/* SCT CTIN_3 capture input multiplexer (GIMA output 19) */
+                                                /* Bits 4-7:  Same as the common definitions */
+#  define GIMA_CTIN3_SELECT_CTIN3     (0 << GIMA_SELECT_SHIFT) /* CTIN_3 */
+#  define GIMA_CTIN3_SELECT_U0TX      (1 << GIMA_SELECT_SHIFT) /* USART0 TX active */
+                                                /* Bits 8-31: Reserved */
+/* SCT CTIN_4 capture input multiplexer (GIMA output 20) */
+                                                /* Bits 4-7:  Same as the common definitions */
+#  define GIMA_CTIN4_SELECT_CTIN4     (0 << GIMA_SELECT_SHIFT) /* CTIN_4*/
+#  define GIMA_CTIN4_SELECT_U0RX      (1 << GIMA_SELECT_SHIFT) /* USART0 RX active */
+#  define GIMA_CTIN4_SELECT_I2S1RX    (2 << GIMA_SELECT_SHIFT) /* I2S1_RX_MWS1 */
+#  define GIMA_CTIN4_SELECT_I2S1TX    (3 << GIMA_SELECT_SHIFT) /* I2S1_TX_MWS1 */
+                                                /* Bits 8-31: Reserved */
+/* SCT CTIN_5 capture input multiplexer (GIMA output 21) */
+                                                /* Bits 4-7:  Same as the common definitions */
+#  define GIMA_CTIN5_SELECT_CTIN5     (0 << GIMA_SELECT_SHIFT) /* CTIN_5 */
+#  define GIMA_CTIN5_SELECT_U2RX      (1 << GIMA_SELECT_SHIFT) /* USART2 RX active */
+#  define GIMA_CTIN5_SELECT_SGPIO12D  (2 << GIMA_SELECT_SHIFT) /* SGPIO12_DIV */
+                                                /* Bits 8-31: Reserved */
+/* SCT CTIN_6 capture input multiplexer (GIMA output 22) */
+                                                /* Bits 4-7:  Same as the common definitions */
+#  define GIMA_CTIN6_SELECT_CTIN6     (0 << GIMA_SELECT_SHIFT) /* CTIN_6 */
+#  define GIMA_CTIN6_SELECT_U3TX      (1 << GIMA_SELECT_SHIFT) /* USART3 TX active */
+#  define GIMA_CTIN6_SELECT_I2S0RX    (2 << GIMA_SELECT_SHIFT) /* I2S0_RX_MWS */
+#  define GIMA_CTIN6_SELECT_I2S0TX    (3 << GIMA_SELECT_SHIFT) /* I2S0_TX_MWS */
+                                                /* Bits 8-31: Reserved */
+/* SCT CTIN_7 capture input multiplexer (GIMA output 23) */
+                                                /* Bits 4-7:  Same as the common definitions */
+#  define GIMA_CTIN7_SELECT_CTIN7     (0 << GIMA_SELECT_SHIFT) /* CTIN_7 */
+#  define GIMA_CTIN7_SELECT_U3RX      (1 << GIMA_SELECT_SHIFT) /* USART3 RX active */
+#  define GIMA_CTIN7_SELECT_SOF0      (2 << GIMA_SELECT_SHIFT) /* SOF0 (Start-Of-Frame USB0) */
+#  define GIMA_CTIN7_SELECT_SOF1      (3 << GIMA_SELECT_SHIFT) /* SOF1 (Start-Of-Frame USB1) */
+                                                /* Bits 8-31: Reserved */
+/* VADC trigger input multiplexer (GIMA output 24) */
+                                                /* Bits 4-7:  Same as the common definitions */
+#  define GIMA_VADC_SELECT_GPIO6p28   (0 << GIMA_SELECT_SHIFT) /* GPIO6[28] */
+#  define GIMA_VADC_SELECT_GPIO5p3    (1 << GIMA_SELECT_SHIFT) /* GPIO5[3] */
+#  define GIMA_VADC_SELECT_SGPIO10    (2 << GIMA_SELECT_SHIFT) /* SGPIO10 */
+#  define GIMA_VADC_SELECT_SGPIO12    (3 << GIMA_SELECT_SHIFT) /* SGPIO12 */
+#  define GIMA_VADC_SELECT_MCOB2      (5 << GIMA_SELECT_SHIFT) /* MCOB2 */
+#  define GIMA_VADC_SELECT_CTOUT0     (6 << GIMA_SELECT_SHIFT) /* CTOUT_0 or T0_MAT0 */
+#  define GIMA_VADC_SELECT_CTOUT8     (7 << GIMA_SELECT_SHIFT) /* CTOUT_8 or T2_MAT0 */
+#  define GIMA_VADC_SELECT_T0MAT0     (8 << GIMA_SELECT_SHIFT) /* T0_MAT0 */
+#  define GIMA_VADC_SELECT_T2MAT0     (9 << GIMA_SELECT_SHIFT) /* T2_MAT0 */
+                                                /* Bits 8-31: Reserved */
+/* Event router input 13 multiplexer (GIMA output 25) */
+                                                /* Bits 4-7:  Same as the common definitions */
+#  define GIMA_EVNTRTR_SELECT_CTOUT2  (0 << GIMA_SELECT_SHIFT) /* CTOUT_2 or T0_MAT2 */
+#  define GIMA_EVNTRTR_SELECT_SGPIO3  (1 << GIMA_SELECT_SHIFT) /* SGPIO3 */
+#  define GIMA_EVNTRTR_SELECT_T0MAT2  (2 << GIMA_SELECT_SHIFT) /* T0_MAT2 */
+                                                /* Bits 8-31: Reserved */
+/* Event router input 14 multiplexer (GIMA output 26) */
+                                                /* Bits 4-7:  Same as the common definitions */
+#  define GIMA_EVNTRTR_SELECT_CTOUT6  (0 << GIMA_SELECT_SHIFT) /* CTOUT_6 or T1_MAT2 */
+#  define GIMA_EVNTRTR_SELECT_SGPIO12 (1 << GIMA_SELECT_SHIFT) /* SGPIO12 */
+#  define GIMA_EVNTRTR_SELECT_T1MAT2  (2 << GIMA_SELECT_SHIFT) /* T1_MAT2 */
+                                                /* Bits 8-31: Reserved */
+/* Event router input 16 multiplexer (GIMA output 27) */
+                                                /* Bits 4-7:  Same as the common definitions */
+#  define GIMA_EVNTRTR_SELECT_CTOUT14 (0 << GIMA_SELECT_SHIFT) /* CTOUT_14 or T3_MAT2 */
+#  define GIMA_EVNTRTR_SELECT_T3MAT2  (1 << GIMA_SELECT_SHIFT) /* T3_MAT2 */
+                                                /* Bits 8-31: Reserved */
+/* ADC start0 input multiplexer (GIMA output 28) */
+                                                /* Bits 4-7:  Same as the common definitions */
+#  define GIMA_ADC0_SELECT_CTOUT15    (0 << GIMA_SELECT_SHIFT) /* CTOUT_15 or T3_MAT3 */
+#  define GIMA_ADC0_SELECT_T3MAT2     (1 << GIMA_SELECT_SHIFT) /* T3_MAT2 */
+                                                /* Bits 8-31: Reserved */
+/* ADC start1 input multiplexer (GIMA output 29) */
+                                                /* Bits 4-7:  Same as the common definitions */
+#  define GIMA_ADC1_SELECT_CTOUT8     (0 << GIMA_SELECT_SHIFT) /* CTOUT_8 or T2_MAT0 */
+#  define GIMA_ADC1_SELECT_T2MAT0     (1 << GIMA_SELECT_SHIFT) /* T2_MAT0 */
+                                                /* Bits 8-31: Reserved */
+
+/****************************************************************************************************
+ * Public Types
+ ****************************************************************************************************/
+
+/****************************************************************************************************
+ * Public Data
+ ****************************************************************************************************/
+
+/****************************************************************************************************
+ * Public Functions
+ ****************************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_GIMA_H */
diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_gpdma.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_gpdma.h
new file mode 100644
index 000000000..f885c1387
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_gpdma.h
@@ -0,0 +1,466 @@
+/****************************************************************************************************
+ * arch/arm/src/lpc43xx/chip/lpc43_gpdma.h
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_GPDMA_H
+#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_GPDMA_H
+
+/****************************************************************************************************
+ * Included Files
+ ****************************************************************************************************/
+
+#include <nuttx/config.h>
+
+/****************************************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************************************/
+/* Register Offsets *********************************************************************************/
+
+#define LPC43_GPDMA_INTSTAT_OFFSET        0x0000 /* DMA Interrupt Status Register */
+#define LPC43_GPDMA_INTTCSTAT_OFFSET      0x0004 /* DMA Interrupt Terminal Count Request Status Register */
+#define LPC43_GPDMA_INTTCCLEAR_OFFSET     0x0008 /* DMA Interrupt Terminal Count Request Clear Register */
+#define LPC43_GPDMA_INTERRSTAT_OFFSET     0x000c /* DMA Interrupt Error Status Register */
+#define LPC43_GPDMA_INTERRCLR_OFFSET      0x0010 /* DMA Interrupt Error Clear Register */
+#define LPC43_GPDMA_RAWINTTCSTAT_OFFSET   0x0014 /* DMA Raw Interrupt Terminal Count Status Register */
+#define LPC43_GPDMA_RAWINTERRSTAT_OFFSET  0x0018 /* DMA Raw Error Interrupt Status Register */
+#define LPC43_GPDMA_ENBLDCHNS_OFFSET      0x001c /* DMA Enabled Channel Register */
+#define LPC43_GPDMA_SOFTBREQ_OFFSET       0x0020 /* DMA Software Burst Request Register */
+#define LPC43_GPDMA_SOFTSREQ_OFFSET       0x0024 /* DMA Software Single Request Register */
+#define LPC43_GPDMA_SOFTLBREQ_OFFSET      0x0028 /* DMA Software Last Burst Request Register */
+#define LPC43_GPDMA_SOFTLSREQ_OFFSET      0x002c /* DMA Software Last Single Request Register */
+#define LPC43_GPDMA_CONFIG_OFFSET         0x0030 /* DMA Configuration Register */
+#define LPC43_GPDMA_SYNC_OFFSET           0x0034 /* DMA Synchronization Register */
+
+/* Channel registers */
+
+#define LPC43_GPDMA_SRCADDR_CHOFFSET      0x0000 /* DMA Channel Source Address Register */
+#define LPC43_GPDMA_DESTADDR_CHOFFSET     0x0004 /* DMA Channel Destination Address Register */
+#define LPC43_GPDMA_LLI_CHOFFSET          0x0008 /* DMA Channel Linked List Item Register */
+#define LPC43_GPDMA_CONTROL_CHOFFSET      0x000c /* DMA Channel Control Register */
+#define LPC43_GPDMA_CONFIG_CHOFFSET       0x0010 /* DMA Channel Configuration Register */
+
+#define LPC43_GPDMA_CHOFFSET(n)           (0x0100 ((n) << 5))
+#define LPC43_GPDMA_SRCADDR_OFFSET(n)     (LPC43_GPDMA_CHOFFSET(n)+LPC43_GPDMA_SRCADDR_CHOFFSET)
+#define LPC43_GPDMA_DESTADDR_OFFSET(n)    (LPC43_GPDMA_CHOFFSET(n)+LPC43_GPDMA_DESTADDR_CHOFFSET)
+#define LPC43_GPDMA_LLI_OFFSET(n)         (LPC43_GPDMA_CHOFFSET(n)+LPC43_GPDMA_LLI_CHOFFSET)
+#define LPC43_GPDMA_CONTROL_OFFSET(n)     (LPC43_GPDMA_CHOFFSET(n)+LPC43_GPDMA_CONTROL_CHOFFSET)
+#define LPC43_GPDMA_CONFIG_OFFSET(n)      (LPC43_GPDMA_CHOFFSET(n)+LPC43_GPDMA_CONFIG_CHOFFSET)
+
+#define LPC43_GPDMA_SRCADDR0_OFFSET       0x0100 /* DMA Channel 0 Source Address Register */
+#define LPC43_GPDMA_DESTADDR0_OFFSET      0x0104 /* DMA Channel 0 Destination Address Register */
+#define LPC43_GPDMA_LLI0_OFFSET           0x0108 /* DMA Channel 0 Linked List Item Register */
+#define LPC43_GPDMA_CONTROL0_OFFSET       0x010c /* DMA Channel 0 Control Register */
+#define LPC43_GPDMA_CONFIG0_OFFSET        0x0110 /* DMA Channel 0 Configuration Register */
+
+#define LPC43_GPDMA_SRCADDR1_OFFSET       0x0120 /* DMA Channel 1 Source Address Register */
+#define LPC43_GPDMA_DESTADDR1_OFFSET      0x0124 /* DMA Channel 1 Destination Address Register */
+#define LPC43_GPDMA_LLI1_OFFSET           0x0128 /* DMA Channel 1 Linked List Item Register */
+#define LPC43_GPDMA_CONTROL1_OFFSET       0x012c /* DMA Channel 1 Control Register */
+#define LPC43_GPDMA_CONFIG1_OFFSET        0x0130 /* DMA Channel 1 Configuration Register */
+
+#define LPC43_GPDMA_SRCADDR2_OFFSET       0x0140 /* DMA Channel 2 Source Address Register */
+#define LPC43_GPDMA_DESTADDR2_OFFSET      0x0144 /* DMA Channel 2 Destination Address Register */
+#define LPC43_GPDMA_LLI2_OFFSET           0x0148 /* DMA Channel 2 Linked List Item Register */
+#define LPC43_GPDMA_CONTROL2_OFFSET       0x014c /* DMA Channel 2 Control Register */
+#define LPC43_GPDMA_CONFIG2_OFFSET        0x0150 /* DMA Channel 2 Configuration Register */
+
+#define LPC43_GPDMA_SRCADDR3_OFFSET       0x0160 /* DMA Channel 3 Source Address Register */
+#define LPC43_GPDMA_DESTADDR3_OFFSET      0x0164 /* DMA Channel 3 Destination Address */
+#define LPC43_GPDMA_LLI3_OFFSET           0x0168 /* DMA Channel 3 Linked List Item Register */
+#define LPC43_GPDMA_CONTROL3_OFFSET       0x016c /* DMA Channel 3 Control Register */
+#define LPC43_GPDMA_CONFIG3_OFFSET        0x0170 /* DMA Channel 3 Configuration Register */
+
+#define LPC43_GPDMA_SRCADDR4_OFFSET       0x0180 /* DMA Channel 4 Source Address Register */
+#define LPC43_GPDMA_DESTADDR4_OFFSET      0x0184 /* DMA Channel 4 Destination Address Register */
+#define LPC43_GPDMA_LLI4_OFFSET           0x0188 /* DMA Channel 4 Linked List Item Register */
+#define LPC43_GPDMA_CONTROL4_OFFSET       0x018c /* DMA Channel 4 Control Register */
+#define LPC43_GPDMA_CONFIG4_OFFSET        0x0190 /* DMA Channel 4 Configuration Register */
+
+#define LPC43_GPDMA_SRCADDR5_OFFSET       0x01a0 /* DMA Channel 5 Source Address Register */
+#define LPC43_GPDMA_DESTADDR5_OFFSET      0x01a4 /* DMA Channel 5 Destination Address Register */
+#define LPC43_GPDMA_LLI5_OFFSET           0x01a8 /* DMA Channel 5 Linked List Item Register */
+#define LPC43_GPDMA_CONTROL5_OFFSET       0x01ac /* DMA Channel 5 Control Register */
+#define LPC43_GPDMA_CONFIG5_OFFSET        0x01b0 /* DMA Channel 5 Configuration Register */
+
+#define LPC43_GPDMA_SRCADDR6_OFFSET       0x01c0 /* DMA Channel 6 Source Address Register */
+#define LPC43_GPDMA_DESTADDR6_OFFSET      0x01c4 /* DMA Channel 6 Destination Address Register */
+#define LPC43_GPDMA_LLI6_OFFSET           0x01c8 /* DMA Channel 6 Linked List Item Register */
+#define LPC43_GPDMA_CONTROL6_OFFSET       0x01cc /* DMA Channel 6 Control Register */
+#define LPC43_GPDMA_CONFIG6_OFFSET        0x01d0 /* DMA Channel 6 Configuration Register */
+
+#define LPC43_GPDMA_SRCADDR7_OFFSET       0x01e0 /* DMA Channel 7 Source Address Register */
+#define LPC43_GPDMA_DESTADDR7_OFFSET      0x01e4 /* DMA Channel 7 Destination Address Register */
+#define LPC43_GPDMA_LLI7_OFFSET           0x01e8 /* DMA Channel 7 Linked List Item Register */
+#define LPC43_GPDMA_CONTROL7_OFFSET       0x01ec /* DMA Channel 7 Control Register */
+#define LPC43_GPDMA_CONFIG7_OFFSET        0x01f0 /* DMA Channel 7 Configuration Register */
+
+/* Register Addresses *******************************************************************************/
+
+#define LPC43_GPDMA_INTSTAT               (LPC43_DMA_BASE+LPC43_GPDMA_INTSTAT_OFFSET)
+#define LPC43_GPDMA_INTTCSTAT             (LPC43_DMA_BASE+LPC43_GPDMA_INTTCSTAT_OFFSET)
+#define LPC43_GPDMA_INTTCCLEAR            (LPC43_DMA_BASE+LPC43_GPDMA_INTTCCLEAR_OFFSET)
+#define LPC43_GPDMA_INTERRSTAT            (LPC43_DMA_BASE+LPC43_GPDMA_INTERRSTAT_OFFSET)
+#define LPC43_GPDMA_INTERRCLR             (LPC43_DMA_BASE+LPC43_GPDMA_INTERRCLR_OFFSET)
+#define LPC43_GPDMA_RAWINTTCSTAT          (LPC43_DMA_BASE+LPC43_GPDMA_RAWINTTCSTAT_OFFSET)
+#define LPC43_GPDMA_RAWINTERRSTAT         (LPC43_DMA_BASE+LPC43_GPDMA_RAWINTERRSTAT_OFFSET)
+#define LPC43_GPDMA_ENBLDCHNS             (LPC43_DMA_BASE+LPC43_GPDMA_ENBLDCHNS_OFFSET)
+#define LPC43_GPDMA_SOFTBREQ              (LPC43_DMA_BASE+LPC43_GPDMA_SOFTBREQ_OFFSET)
+#define LPC43_GPDMA_SOFTSREQ              (LPC43_DMA_BASE+LPC43_GPDMA_SOFTSREQ_OFFSET)
+#define LPC43_GPDMA_SOFTLBREQ             (LPC43_DMA_BASE+LPC43_GPDMA_SOFTLBREQ_OFFSET)
+#define LPC43_GPDMA_SOFTLSREQ             (LPC43_DMA_BASE+LPC43_GPDMA_SOFTLSREQ_OFFSET)
+#define LPC43_GPDMA_CONFIG                (LPC43_DMA_BASE+LPC43_GPDMA_CONFIG_OFFSET)
+#define LPC43_GPDMA_SYNC                  (LPC43_DMA_BASE+LPC43_GPDMA_SYNC_OFFSET)
+
+/* Channel registers */
+
+#define LPC43_GPDMA_CHANNEL(n)            (LPC43_DMA_BASE+LPC43_GPDMA_CHOFFSET(n))
+#define LPC43_GPDMA_SRCADDR(n)            (LPC43_DMA_BASE+LPC43_GPDMA_SRCADDR_OFFSET(n))
+#define LPC43_GPDMA_DESTADDR(n)           (LPC43_DMA_BASE+LPC43_GPDMA_DESTADDR_OFFSET(n))
+#define LPC43_GPDMA_LLI(n)                (LPC43_DMA_BASE+LPC43_GPDMA_LLI_OFFSET(n))
+#define LPC43_GPDMA_CONTROL(n)            (LPC43_DMA_BASE+LPC43_GPDMA_CONTROL_OFFSET(n))
+#define LPC43_GPDMA_CONFIG(n)             (LPC43_DMA_BASE+LPC43_GPDMA_CONFIG_OFFSET(n))
+
+#define LPC43_GPDMA_SRCADDR0              (LPC43_DMA_BASE+LPC43_GPDMA_SRCADDR0_OFFSET)
+#define LPC43_GPDMA_DESTADDR0             (LPC43_DMA_BASE+LPC43_GPDMA_DESTADDR0_OFFSET)
+#define LPC43_GPDMA_LLI0                  (LPC43_DMA_BASE+LPC43_GPDMA_LLI0_OFFSET)
+#define LPC43_GPDMA_CONTROL0              (LPC43_DMA_BASE+LPC43_GPDMA_CONTROL0_OFFSET)
+#define LPC43_GPDMA_CONFIG0               (LPC43_DMA_BASE+LPC43_GPDMA_CONFIG0_OFFSET)
+
+#define LPC43_GPDMA_SRCADDR1              (LPC43_DMA_BASE+LPC43_GPDMA_SRCADDR1_OFFSET)
+#define LPC43_GPDMA_DESTADDR1             (LPC43_DMA_BASE+LPC43_GPDMA_DESTADDR1_OFFSET)
+#define LPC43_GPDMA_LLI1                  (LPC43_DMA_BASE+LPC43_GPDMA_LLI1_OFFSET)
+#define LPC43_GPDMA_CONTROL1              (LPC43_DMA_BASE+LPC43_GPDMA_CONTROL1_OFFSET)
+#define LPC43_GPDMA_CONFIG1               (LPC43_DMA_BASE+LPC43_GPDMA_CONFIG1_OFFSET)
+
+#define LPC43_GPDMA_SRCADDR2              (LPC43_DMA_BASE+LPC43_GPDMA_SRCADDR2_OFFSET)
+#define LPC43_GPDMA_DESTADDR2             (LPC43_DMA_BASE+LPC43_GPDMA_DESTADDR2_OFFSET)
+#define LPC43_GPDMA_LLI2                  (LPC43_DMA_BASE+LPC43_GPDMA_LLI2_OFFSET)
+#define LPC43_GPDMA_CONTROL2              (LPC43_DMA_BASE+LPC43_GPDMA_CONTROL2_OFFSET)
+#define LPC43_GPDMA_CONFIG2               (LPC43_DMA_BASE+LPC43_GPDMA_CONFIG2_OFFSET)
+
+#define LPC43_GPDMA_SRCADDR3              (LPC43_DMA_BASE+LPC43_GPDMA_SRCADDR3_OFFSET)
+#define LPC43_GPDMA_DESTADDR3             (LPC43_DMA_BASE+LPC43_GPDMA_DESTADDR3_OFFSET)
+#define LPC43_GPDMA_LLI3                  (LPC43_DMA_BASE+LPC43_GPDMA_LLI3_OFFSET)
+#define LPC43_GPDMA_CONTROL3              (LPC43_DMA_BASE+LPC43_GPDMA_CONTROL3_OFFSET)
+#define LPC43_GPDMA_CONFIG3               (LPC43_DMA_BASE+LPC43_GPDMA_CONFIG3_OFFSET)
+
+#define LPC43_GPDMA_SRCADDR4              (LPC43_DMA_BASE+LPC43_GPDMA_SRCADDR4_OFFSET)
+#define LPC43_GPDMA_DESTADDR4             (LPC43_DMA_BASE+LPC43_GPDMA_DESTADDR4_OFFSET)
+#define LPC43_GPDMA_LLI4                  (LPC43_DMA_BASE+LPC43_GPDMA_LLI4_OFFSET)
+#define LPC43_GPDMA_CONTROL4              (LPC43_DMA_BASE+LPC43_GPDMA_CONTROL4_OFFSET)
+#define LPC43_GPDMA_CONFIG4               (LPC43_DMA_BASE+LPC43_GPDMA_CONFIG4_OFFSET)
+
+#define LPC43_GPDMA_SRCADDR5              (LPC43_DMA_BASE+LPC43_GPDMA_SRCADDR5_OFFSET)
+#define LPC43_GPDMA_DESTADDR5             (LPC43_DMA_BASE+LPC43_GPDMA_DESTADDR5_OFFSET)
+#define LPC43_GPDMA_LLI5                  (LPC43_DMA_BASE+LPC43_GPDMA_LLI5_OFFSET)
+#define LPC43_GPDMA_CONTROL5              (LPC43_DMA_BASE+LPC43_GPDMA_CONTROL5_OFFSET)
+#define LPC43_GPDMA_CONFIG5               (LPC43_DMA_BASE+LPC43_GPDMA_CONFIG5_OFFSET)
+
+#define LPC43_GPDMA_SRCADDR6              (LPC43_DMA_BASE+LPC43_GPDMA_SRCADDR6_OFFSET)
+#define LPC43_GPDMA_DESTADDR6             (LPC43_DMA_BASE+LPC43_GPDMA_DESTADDR6_OFFSET)
+#define LPC43_GPDMA_LLI6                  (LPC43_DMA_BASE+LPC43_GPDMA_LLI6_OFFSET)
+#define LPC43_GPDMA_CONTROL6              (LPC43_DMA_BASE+LPC43_GPDMA_CONTROL6_OFFSET)
+#define LPC43_GPDMA_CONFIG6               (LPC43_DMA_BASE+LPC43_GPDMA_CONFIG6_OFFSET)
+
+#define LPC43_GPDMA_SRCADDR7              (LPC43_DMA_BASE+LPC43_GPDMA_SRCADDR7_OFFSET)
+#define LPC43_GPDMA_DESTADDR7             (LPC43_DMA_BASE+LPC43_GPDMA_DESTADDR7_OFFSET)
+#define LPC43_GPDMA_LLI7                  (LPC43_DMA_BASE+LPC43_GPDMA_LLI7_OFFSET)
+#define LPC43_GPDMA_CONTROL7              (LPC43_DMA_BASE+LPC43_GPDMA_CONTROL7_OFFSET)
+#define LPC43_GPDMA_CONFIG7               (LPC43_DMA_BASE+LPC43_GPDMA_CONFIG7_OFFSET)
+
+/* Register Bit Definitions *************************************************************************/
+
+/* Common macros for DMA channel and source bit settings */
+
+#define GPDMA_CHANNEL(n)                  (1 << (n)) /* Bits 0-7 correspond to DMA channel 0-7 */
+#define GPDMA_SOURCE(n)                   (1 << (n)) /* Bits 0-15 correspond to DMA source 0-15 */
+#define GPDMA_REQUEST(n)                  (1 << (n)) /* Bits 0-15 correspond to DMA request 0-15 */
+
+/* DMA Interrupt Status Register */
+
+#define GPDMA_INTSTAT(n)                  (1 << (n)) /* Bits 0-7: Status of DMA channel n interrupts after masking */
+                                                     /* Bits 8-31: Reserved */
+/* DMA Interrupt Terminal Count Request Status Register */
+
+#define GPDMA_INTTCSTAT(n)                (1 << (n)) /* Bits 0-7: Terminal count interrupt request status for DMA channel n */
+                                                     /* Bits 8-31: Reserved */
+/* DMA Interrupt Terminal Count Request Clear Register */
+
+#define GPDMA_INTTCCLEAR(n)               (1 << (n)) /* Bits 0-7: Clear terminal count interrupt request for DMA channel n */
+                                                     /* Bits 8-31: Reserved */
+/* DMA Interrupt Error Status Register */
+
+#define GPDMA_INTERRSTAT(n)               (1 << (n)) /* Bits 0-7: Interrupt error status for DMA channel n */
+                                                     /* Bits 8-31: Reserved */
+/* DMA Interrupt Error Clear Register */
+
+#define GPDMA_INTERRCLR(n)                (1 << (n)) /* Bits 0-7: Clear nterrupt error status for DMA channel n */
+                                                     /* Bits 8-31: Reserved */
+/* DMA Raw Interrupt Terminal Count Status Register */
+
+#define GPDMA_RAWINTTCSTAT(n)             (1 << (n)) /* Bits 0-7: Terminal count interrupt request status for DMA channel n */
+                                                     /* Bits 8-31: Reserved */
+/* DMA Raw Error Interrupt Status Register */
+
+#define GPDMA_RAWINTERRSTAT(n)            (1 << (n)) /* Bits 0-7: Interrupt error status for DMA channel n */
+                                                     /* Bits 8-31: Reserved */
+/* DMA Enabled Channel Register */
+
+#define GPDMA_ENBLDCHNS(n)                (1 << (n)) /* Bits 0-7: Enabled status for DMA channel n */
+                                                     /* Bits 8-31: Reserved */
+/* DMA Software Burst Request Register */
+
+#define GPDMA_SOFTBREQ(n)                 (1 << (n)) /* Bits 0-15: Software burst request flags for source n */
+                                                     /* Bits 16-31: Reserved */
+
+/* DMA Software Single Request Register */
+
+#define GPDMA_SOFTSREQ(n)                 (1 << (n)) /* Bits 0-15: Software single burst request flags for source n */
+                                                     /* Bits 16-31: Reserved */
+/* DMA Software Last Burst Request Register */
+
+#define GPDMA_SOFTLBREQ(n)                (1 << (n)) /* Bits 0-15: Software last burst request flags for source n */
+                                                     /* Bits 16-31: Reserved */
+                                                     
+/* DMA Software Last Single Request Register */
+
+#define GPDMA_SOFTLSREQ(n)                (1 << (n)) /* Bits 0-15: Software last single burst request flags for source n */
+                                                     /* Bits 16-31: Reserved */
+/* DMA Configuration Register */
+
+#define GPDMA_CONFIG_ENA                  (1 << 0)  /* Bit 0:  DMA Controller enable */
+#define GPDMA_CONFIG_M0                   (1 << 1)  /* Bit 1:  AHB Master 0 endianness configuration */
+#define GPDMA_CONFIG_M1                   (1 << 2)  /* Bit 2:  M1 AHB Master 1 endianness configuration */
+                                                    /* Bits 3-31: Reserved */
+/* DMA Synchronization Register */
+
+#define GPDMA_SYNC(n)                     (1 << (n)) /* Bits 0-15: Control synchrononization for DMA request n */
+                                                     /* Bits 16-31: Reserved */
+/* DMA Channel Source Address Register (32-bit address) */
+/* DMA Channel Destination Address Register (32-bit address) */
+
+/* DMA Channel Linked List Item Register */
+
+#define GPDMA_LLI_LM                      (1 << 0)   /* Bit 0: LM AHB master select for loading the next LLI */
+                                                     /* Bit 1: Reserved */
+#define GPDMA_LLI_MASK                    0xfffffffc /* 31:2 LLI Linked list item */
+
+/* DMA Channel Control Register */
+
+#define GPDMA_CONTROL_XFRSIZE_SHIFT      (0)       /* Bits 0-11: Transfer size in number of transfers */
+#define GPDMA_CONTROL_XFRSIZE_MASK       (0xfff << GPDMA_CONTROL_XFRSIZE_SHIFT)
+#define GPDMA_CONTROL_SBSIZE_SHIFT       (12)      /* Bits 12-14: Source burst size */
+#define GPDMA_CONTROL_SBSIZE_MASK        (7 << GPDMA_CONTROL_XFRSIZE_MASK)
+#  define GPDMA_CONTROL_SBSIZE_1         (0 << GPDMA_CONTROL_XFRSIZE_MASK) /* Source burst size = 1 */
+#  define GPDMA_CONTROL_SBSIZE_4         (1 << GPDMA_CONTROL_XFRSIZE_MASK) /* Source burst size = 4 */
+#  define GPDMA_CONTROL_SBSIZE_8         (2 << GPDMA_CONTROL_XFRSIZE_MASK) /* Source burst size = 8 */
+#  define GPDMA_CONTROL_SBSIZE_16        (3 << GPDMA_CONTROL_XFRSIZE_MASK) /* Source burst size = 16 */
+#  define GPDMA_CONTROL_SBSIZE_32        (4 << GPDMA_CONTROL_XFRSIZE_MASK) /* Source burst size = 32 */
+#  define GPDMA_CONTROL_SBSIZE_64        (5 << GPDMA_CONTROL_XFRSIZE_MASK) /* Source burst size = 64 */
+#  define GPDMA_CONTROL_SBSIZE_128       (6 << GPDMA_CONTROL_XFRSIZE_MASK) /* Source burst size = 128 */
+#  define GPDMA_CONTROL_SBSIZE_256       (7 << GPDMA_CONTROL_XFRSIZE_MASK) /* Source burst size = 256 */
+#define GPDMA_CONTROL_DBSIZE_SHIFT       (15)      /* Bits 15-17: Destination burst size */
+#define GPDMA_CONTROL_DBSIZE_MASK        (7 << GPDMA_CONTROL_DBSIZE_SHIFT)
+#  define GPDMA_CONTROL_DBSIZE_1         (0 << GPDMA_CONTROL_DBSIZE_SHIFT) /* Destination burst size = 1 */
+#  define GPDMA_CONTROL_DBSIZE_4         (1 << GPDMA_CONTROL_DBSIZE_SHIFT) /* Destination burst size = 4 */
+#  define GPDMA_CONTROL_DBSIZE_8         (2 << GPDMA_CONTROL_DBSIZE_SHIFT) /* Destination burst size = 8 */
+#  define GPDMA_CONTROL_DBSIZE_16        (3 << GPDMA_CONTROL_DBSIZE_SHIFT) /* Destination burst size = 16 */
+#  define GPDMA_CONTROL_DBSIZE_32        (4 << GPDMA_CONTROL_DBSIZE_SHIFT) /* Destination burst size = 32 */
+#  define GPDMA_CONTROL_DBSIZE_64        (5 << GPDMA_CONTROL_DBSIZE_SHIFT) /* Destination burst size = 64 */
+#  define GPDMA_CONTROL_DBSIZE_128       (6 << GPDMA_CONTROL_DBSIZE_SHIFT) /* Destination burst size = 128 */
+#  define GPDMA_CONTROL_DBSIZE_256       (7 << GPDMA_CONTROL_DBSIZE_SHIFT) /* Destination burst size = 256 */
+#define GPDMA_CONTROL_SWIDTH_SHIFT       (18)       /* Bits 18-20: Source transfer width */
+#define GPDMA_CONTROL_SWIDTH_MASK        (7 << GPDMA_CONTROL_SWIDTH_SHIFT)
+#  define GPDMA_CONTROL_SWIDTH_BYTE      (0 << GPDMA_CONTROL_SWIDTH_SHIFT) /* Byte (8-bit) */
+#  define GPDMA_CONTROL_SWIDTH_HWORD     (1 << GPDMA_CONTROL_SWIDTH_SHIFT) /* Halfword (16-bit) */
+#  define GPDMA_CONTROL_SWIDTH_WORD      (2 << GPDMA_CONTROL_SWIDTH_SHIFT) /* Word (32-bit) */
+#define GPDMA_CONTROL_DWIDTH_SHIFT       (21)       /* Bits 21-23: Destination transfer width */
+#define GPDMA_CONTROL_DWIDTH_MASK        (7 << GPDMA_CONTROL_DWIDTH_SHIFT)
+#  define GPDMA_CONTROL_DWIDTH_BYTE      (0 << GPDMA_CONTROL_DWIDTH_SHIFT) /* Byte (8-bit) */
+#  define GPDMA_CONTROL_DWIDTH_HWORD     (1 << GPDMA_CONTROL_DWIDTH_SHIFT) /* Halfword (16-bit) */
+#  define GPDMA_CONTROL_DWIDTH_WORD      (2 << GPDMA_CONTROL_DWIDTH_SHIFT) /* Word (32-bit) */
+#define GPDMA_CONTROL_SS                 (1 << 24) /* Bit 24: Source AHB master select */
+#define GPDMA_CONTROL_DS                 (1 << 25) /* Bit 25: Destination AHB master select */
+#define GPDMA_CONTROL_SI                 (1 << 26) /* Bit 26: Source increment */
+#define GPDMA_CONTROL_DI                 (1 << 27) /* Bit 27: Destination increment */
+#define GPDMA_CONTROL_PROT1              (1 << 28) /* Bit 28: Privileged mode */
+#define GPDMA_CONTROL_PROT2              (1 << 29) /* Bit 29: Bufferable */
+#define GPDMA_CONTROL_PROT3              (1 << 30) /* Bit 30: Cacheable */
+#define GPDMA_CONTROL_IE                 (1 << 31) /* Bit 31: Terminal count interrupt enable bit */
+
+/* DMA Channel Configuration Register */
+
+#define GPDMA_CONFIG_ENA                 (1 << 0)  /* Bit 0:  Channel enable */
+#define GPDMA_CONFIG_SRCPER_SHIFT        (1)       /* Bits 1-5: Source peripheral */
+#define GPDMA_CONFIG_SRCPER_MASK         (31 << GPDMA_CONFIG_SRCPER_SHIFT)
+#  define GPDMA_CONFIG_SRCPER_SPIFI      (0 << GPDMA_CONFIG_SRCPER_SHIFT)  /* SPIFI */
+#  define GPDMA_CONFIG_SRCPER_SCTM3_1    (0 << GPDMA_CONFIG_SRCPER_SHIFT)  /* SCT match3 */
+#  define GPDMA_CONFIG_SRCPER_SGPIO14_1  (0 << GPDMA_CONFIG_SRCPER_SHIFT)  /* SGPIO14 */
+#  define GPDMA_CONFIG_SRCPER_T3MAT1_1   (0 << GPDMA_CONFIG_SRCPER_SHIFT)  /* Timer3 match 1 */
+#  define GPDMA_CONFIG_SRCPER_T0MAT0     (1 << GPDMA_CONFIG_SRCPER_SHIFT)  /* Timer0 match 0 */
+#  define GPDMA_CONFIG_SRCPER_U0TX_1     (1 << GPDMA_CONFIG_SRCPER_SHIFT)  /* USART0 transmit */
+#  define GPDMA_CONFIG_SRCPER_T0MAT1     (2 << GPDMA_CONFIG_SRCPER_SHIFT)  /* Timer0 match 1 */
+#  define GPDMA_CONFIG_SRCPER_U0RX_1     (2 << GPDMA_CONFIG_SRCPER_SHIFT)  /* USART0 receive */
+#  define GPDMA_CONFIG_SRCPER_T1MAT0     (3 << GPDMA_CONFIG_SRCPER_SHIFT)  /* Timer1 match 0 */
+#  define GPDMA_CONFIG_SRCPER_U1TX       (3 << GPDMA_CONFIG_SRCPER_SHIFT)  /* UART1 transmit */
+#  define GPDMA_CONFIG_SRCPER_I2S1D1     (3 << GPDMA_CONFIG_SRCPER_SHIFT)  /* I2S1 DMA request 1 */
+#  define GPDMA_CONFIG_SRCPER_SSP1TX_1   (3 << GPDMA_CONFIG_SRCPER_SHIFT)  /* SSP1 transmit */
+#  define GPDMA_CONFIG_SRCPER_T1MAT1     (4 << GPDMA_CONFIG_SRCPER_SHIFT)  /* Timer1 match 1 */
+#  define GPDMA_CONFIG_SRCPER_U1RX       (4 << GPDMA_CONFIG_SRCPER_SHIFT)  /* UART1 receive */
+#  define GPDMA_CONFIG_SRCPER_I2S1D2     (4 << GPDMA_CONFIG_SRCPER_SHIFT)  /* I2S1 DMA request 2 */
+#  define GPDMA_CONFIG_SRCPER_SSP1RX_1   (4 << GPDMA_CONFIG_SRCPER_SHIFT)  /* SSP1 receive */
+#  define GPDMA_CONFIG_SRCPER_T2MAT0     (5 << GPDMA_CONFIG_SRCPER_SHIFT)  /* Timer2 match 0 */
+#  define GPDMA_CONFIG_SRCPER_U2TX       (5 << GPDMA_CONFIG_SRCPER_SHIFT)  /* USART2 transmit */
+#  define GPDMA_CONFIG_SRCPER_SSP1TX_2   (5 << GPDMA_CONFIG_SRCPER_SHIFT)  /* SSP1 transmit */
+#  define GPDMA_CONFIG_SRCPER_SGPIO15_1  (5 << GPDMA_CONFIG_SRCPER_SHIFT)  /* SGPIO15 */
+#  define GPDMA_CONFIG_SRCPER_T2MAT1     (6 << GPDMA_CONFIG_SRCPER_SHIFT)  /* Timer2 match 1 */
+#  define GPDMA_CONFIG_SRCPER_U2RX       (6 << GPDMA_CONFIG_SRCPER_SHIFT)  /* USART2 receive */
+#  define GPDMA_CONFIG_SRCPER_SSP1RX_2   (6 << GPDMA_CONFIG_SRCPER_SHIFT)  /* SSP1 receive */
+#  define GPDMA_CONFIG_SRCPER_SGPIO14_2  (6 << GPDMA_CONFIG_SRCPER_SHIFT)  /* SGPIO14 */
+#  define GPDMA_CONFIG_SRCPER_T3MAT0_1   (7 << GPDMA_CONFIG_SRCPER_SHIFT)  /* Timer3 match 0 */
+#  define GPDMA_CONFIG_SRCPER_U3TX_1     (7 << GPDMA_CONFIG_SRCPER_SHIFT)  /* USART3 transmit */
+#  define GPDMA_CONFIG_SRCPER_SCTD0_1    (7 << GPDMA_CONFIG_SRCPER_SHIFT)  /* SCT DMA request 0 */
+#  define GPDMA_CONFIG_SRCPER_VADCWR     (7 << GPDMA_CONFIG_SRCPER_SHIFT)  /* VADC write */
+#  define GPDMA_CONFIG_SRCPER_T3MAT1_2   (8 << GPDMA_CONFIG_SRCPER_SHIFT)  /* Timer3 match 1 */
+#  define GPDMA_CONFIG_SRCPER_U3RX_1     (8 << GPDMA_CONFIG_SRCPER_SHIFT)  /* USART3 receive */
+#  define GPDMA_CONFIG_SRCPER_SCTD1_1    (8 << GPDMA_CONFIG_SRCPER_SHIFT)  /* SCT DMA request 1 */
+#  define GPDMA_CONFIG_SRCPER_VADCRD     (8 << GPDMA_CONFIG_SRCPER_SHIFT)  /* VADC read */
+#  define GPDMA_CONFIG_SRCPER_SSP0RX     (9 << GPDMA_CONFIG_SRCPER_SHIFT)  /* SSP0 receive */
+#  define GPDMA_CONFIG_SRCPER_I2S0D1     (9 << GPDMA_CONFIG_SRCPER_SHIFT)  /* I2S0 DMA request 1 */
+#  define GPDMA_CONFIG_SRCPER_SCTD1_2    (9 << GPDMA_CONFIG_SRCPER_SHIFT)  /* SCT DMA request 1 */
+#  define GPDMA_CONFIG_SRCPER_SSP0TX     (10 << GPDMA_CONFIG_SRCPER_SHIFT) /* SSP0 transmit */
+#  define GPDMA_CONFIG_SRCPER_I2S0D2     (10 << GPDMA_CONFIG_SRCPER_SHIFT) /* I2S0 DMA request 2 */
+#  define GPDMA_CONFIG_SRCPER_SCTD0_2    (10 << GPDMA_CONFIG_SRCPER_SHIFT) /* SCT DMA request 0 */
+#  define GPDMA_CONFIG_SRCPER_SSP1RX_3   (11 << GPDMA_CONFIG_SRCPER_SHIFT) /* SSP1 receive */
+#  define GPDMA_CONFIG_SRCPER_SGPIO14_3  (11 << GPDMA_CONFIG_SRCPER_SHIFT) /* SGPIO14 */
+#  define GPDMA_CONFIG_SRCPER_U0TX_2     (11 << GPDMA_CONFIG_SRCPER_SHIFT) /* USART0 transmit */
+#  define GPDMA_CONFIG_SRCPER_SSP1TX_3   (12 << GPDMA_CONFIG_SRCPER_SHIFT) /* SSP1 transmit */
+#  define GPDMA_CONFIG_SRCPER_SGPIO15_2  (12 << GPDMA_CONFIG_SRCPER_SHIFT) /* SGPIO15 */
+#  define GPDMA_CONFIG_SRCPER_U0RX_2     (12 << GPDMA_CONFIG_SRCPER_SHIFT) /* USART0 receive */
+#  define GPDMA_CONFIG_SRCPER_ADC0       (13 << GPDMA_CONFIG_SRCPER_SHIFT) /* ADC0 */
+#  define GPDMA_CONFIG_SRCPER_SSP1RX_4   (13 << GPDMA_CONFIG_SRCPER_SHIFT) /* SSP1 receive */
+#  define GPDMA_CONFIG_SRCPER_U3RX_2     (13 << GPDMA_CONFIG_SRCPER_SHIFT) /* USART3 receive */
+#  define GPDMA_CONFIG_SRCPER_ADC1       (14 << GPDMA_CONFIG_SRCPER_SHIFT) /* ADC1 */
+#  define GPDMA_CONFIG_SRCPER_SSP1TX_4   (14 << GPDMA_CONFIG_SRCPER_SHIFT) /* SSP1 transmit */
+#  define GPDMA_CONFIG_SRCPER_U3TX_2     (14 << GPDMA_CONFIG_SRCPER_SHIFT) /* USART3 transmit */
+#  define GPDMA_CONFIG_SRCPER_DAC        (15 << GPDMA_CONFIG_SRCPER_SHIFT) /* DAC */
+#  define GPDMA_CONFIG_SRCPER_SCTM3_2    (15 << GPDMA_CONFIG_SRCPER_SHIFT) /* SCT match 3 */
+#  define GPDMA_CONFIG_SRCPER_SGPIO15_3  (15 << GPDMA_CONFIG_SRCPER_SHIFT) /* SGPIO15 */
+#  define GPDMA_CONFIG_SRCPER_T3MAT0_2   (15 << GPDMA_CONFIG_SRCPER_SHIFT) /* Timer3 match 0 */
+#define GPDMA_CONFIG_DESTPER_SHIFT       (6)       /* Bits 6-10: Destination peripheral */
+#define GPDMA_CONFIG_DESTPER_MASK        (31 << GPDMA_CONFIG_DESTPER_SHIFT)
+#  define GPDMA_CONFIG_DESTPER_SPIFI     (0 << GPDMA_CONFIG_DESTPER_SHIFT)  /* SPIFI */
+#  define GPDMA_CONFIG_DESTPER_SCTM3_1   (0 << GPDMA_CONFIG_DESTPER_SHIFT)  /* SCT match3 */
+#  define GPDMA_CONFIG_DESTPER_SGPIO14_1 (0 << GPDMA_CONFIG_DESTPER_SHIFT)  /* SGPIO14 */
+#  define GPDMA_CONFIG_DESTPER_T3MAT1_1  (0 << GPDMA_CONFIG_DESTPER_SHIFT)  /* Timer3 match 1 */
+#  define GPDMA_CONFIG_DESTPER_T0MAT0    (1 << GPDMA_CONFIG_DESTPER_SHIFT)  /* Timer0 match 0 */
+#  define GPDMA_CONFIG_DESTPER_U0TX_1    (1 << GPDMA_CONFIG_DESTPER_SHIFT)  /* USART0 transmit */
+#  define GPDMA_CONFIG_DESTPER_T0MAT1    (2 << GPDMA_CONFIG_DESTPER_SHIFT)  /* Timer0 match 1 */
+#  define GPDMA_CONFIG_DESTPER_U0RX_1    (2 << GPDMA_CONFIG_DESTPER_SHIFT)  /* USART0 receive */
+#  define GPDMA_CONFIG_DESTPER_T1MAT0    (3 << GPDMA_CONFIG_DESTPER_SHIFT)  /* Timer1 match 0 */
+#  define GPDMA_CONFIG_DESTPER_U1TX      (3 << GPDMA_CONFIG_DESTPER_SHIFT)  /* UART1 transmit */
+#  define GPDMA_CONFIG_DESTPER_I2S1D1    (3 << GPDMA_CONFIG_DESTPER_SHIFT)  /* I2S1 DMA request 1 */
+#  define GPDMA_CONFIG_DESTPER_SSP1TX_1  (3 << GPDMA_CONFIG_DESTPER_SHIFT)  /* SSP1 transmit */
+#  define GPDMA_CONFIG_DESTPER_T1MAT1    (4 << GPDMA_CONFIG_DESTPER_SHIFT)  /* Timer1 match 1 */
+#  define GPDMA_CONFIG_DESTPER_U1RX      (4 << GPDMA_CONFIG_DESTPER_SHIFT)  /* UART1 receive */
+#  define GPDMA_CONFIG_DESTPER_I2S1D2    (4 << GPDMA_CONFIG_DESTPER_SHIFT)  /* I2S1 DMA request 2 */
+#  define GPDMA_CONFIG_DESTPER_SSP1RX_1  (4 << GPDMA_CONFIG_DESTPER_SHIFT)  /* SSP1 receive */
+#  define GPDMA_CONFIG_DESTPER_T2MAT0    (5 << GPDMA_CONFIG_DESTPER_SHIFT)  /* Timer2 match 0 */
+#  define GPDMA_CONFIG_DESTPER_U2TX      (5 << GPDMA_CONFIG_DESTPER_SHIFT)  /* USART2 transmit */
+#  define GPDMA_CONFIG_DESTPER_SSP1TX_2  (5 << GPDMA_CONFIG_DESTPER_SHIFT)  /* SSP1 transmit */
+#  define GPDMA_CONFIG_DESTPER_SGPIO15_1 (5 << GPDMA_CONFIG_DESTPER_SHIFT)  /* SGPIO15 */
+#  define GPDMA_CONFIG_DESTPER_T2MAT1    (6 << GPDMA_CONFIG_DESTPER_SHIFT)  /* Timer2 match 1 */
+#  define GPDMA_CONFIG_DESTPER_U2RX      (6 << GPDMA_CONFIG_DESTPER_SHIFT)  /* USART2 receive */
+#  define GPDMA_CONFIG_DESTPER_SSP1RX_2  (6 << GPDMA_CONFIG_DESTPER_SHIFT)  /* SSP1 receive */
+#  define GPDMA_CONFIG_DESTPER_SGPIO14_2 (6 << GPDMA_CONFIG_DESTPER_SHIFT)  /* SGPIO14 */
+#  define GPDMA_CONFIG_DESTPER_T3MAT0_1  (7 << GPDMA_CONFIG_DESTPER_SHIFT)  /* Timer3 match 0 */
+#  define GPDMA_CONFIG_DESTPER_U3TX_1    (7 << GPDMA_CONFIG_DESTPER_SHIFT)  /* USART3 transmit */
+#  define GPDMA_CONFIG_DESTPER_SCTD0_1   (7 << GPDMA_CONFIG_DESTPER_SHIFT)  /* SCT DMA request 0 */
+#  define GPDMA_CONFIG_DESTPER_VADCWR    (7 << GPDMA_CONFIG_DESTPER_SHIFT)  /* VADC write */
+#  define GPDMA_CONFIG_DESTPER_T3MAT1_2  (8 << GPDMA_CONFIG_DESTPER_SHIFT)  /* Timer3 match 1 */
+#  define GPDMA_CONFIG_DESTPER_U3RX_1    (8 << GPDMA_CONFIG_DESTPER_SHIFT)  /* USART3 receive */
+#  define GPDMA_CONFIG_DESTPER_SCTD1_1   (8 << GPDMA_CONFIG_DESTPER_SHIFT)  /* SCT DMA request 1 */
+#  define GPDMA_CONFIG_DESTPER_VADCRD    (8 << GPDMA_CONFIG_DESTPER_SHIFT)  /* VADC read */
+#  define GPDMA_CONFIG_DESTPER_SSP0RX    (9 << GPDMA_CONFIG_DESTPER_SHIFT)  /* SSP0 receive */
+#  define GPDMA_CONFIG_DESTPER_I2S0D1    (9 << GPDMA_CONFIG_DESTPER_SHIFT)  /* I2S0 DMA request 1 */
+#  define GPDMA_CONFIG_DESTPER_SCTD1_2   (9 << GPDMA_CONFIG_DESTPER_SHIFT)  /* SCT DMA request 1 */
+#  define GPDMA_CONFIG_DESTPER_SSP0TX    (10 << GPDMA_CONFIG_DESTPER_SHIFT) /* SSP0 transmit */
+#  define GPDMA_CONFIG_DESTPER_I2S0D2    (10 << GPDMA_CONFIG_DESTPER_SHIFT) /* I2S0 DMA request 2 */
+#  define GPDMA_CONFIG_DESTPER_SCTD0_2   (10 << GPDMA_CONFIG_DESTPER_SHIFT) /* SCT DMA request 0 */
+#  define GPDMA_CONFIG_DESTPER_SSP1RX_3  (11 << GPDMA_CONFIG_DESTPER_SHIFT) /* SSP1 receive */
+#  define GPDMA_CONFIG_DESTPER_SGPIO14_3 (11 << GPDMA_CONFIG_DESTPER_SHIFT) /* SGPIO14 */
+#  define GPDMA_CONFIG_DESTPER_U0TX_2    (11 << GPDMA_CONFIG_DESTPER_SHIFT) /* USART0 transmit */
+#  define GPDMA_CONFIG_DESTPER_SSP1TX_3  (12 << GPDMA_CONFIG_DESTPER_SHIFT) /* SSP1 transmit */
+#  define GPDMA_CONFIG_DESTPER_SGPIO15_2 (12 << GPDMA_CONFIG_DESTPER_SHIFT) /* SGPIO15 */
+#  define GPDMA_CONFIG_DESTPER_U0RX_2    (12 << GPDMA_CONFIG_DESTPER_SHIFT) /* USART0 receive */
+#  define GPDMA_CONFIG_DESTPER_ADC0      (13 << GPDMA_CONFIG_DESTPER_SHIFT) /* ADC0 */
+#  define GPDMA_CONFIG_DESTPER_SSP1RX_4  (13 << GPDMA_CONFIG_DESTPER_SHIFT) /* SSP1 receive */
+#  define GPDMA_CONFIG_DESTPER_U3RX_2    (13 << GPDMA_CONFIG_DESTPER_SHIFT) /* USART3 receive */
+#  define GPDMA_CONFIG_DESTPER_ADC1      (14 << GPDMA_CONFIG_DESTPER_SHIFT) /* ADC1 */
+#  define GPDMA_CONFIG_DESTPER_SSP1TX_4  (14 << GPDMA_CONFIG_DESTPER_SHIFT) /* SSP1 transmit */
+#  define GPDMA_CONFIG_DESTPER_U3TX_2    (14 << GPDMA_CONFIG_DESTPER_SHIFT) /* USART3 transmit */
+#  define GPDMA_CONFIG_DESTPER_DAC       (15 << GPDMA_CONFIG_DESTPER_SHIFT) /* DAC */
+#  define GPDMA_CONFIG_DESTPER_SCTM3_2   (15 << GPDMA_CONFIG_DESTPER_SHIFT) /* SCT match 3 */
+#  define GPDMA_CONFIG_DESTPER_SGPIO15_3 (15 << GPDMA_CONFIG_DESTPER_SHIFT) /* SGPIO15 */
+#  define GPDMA_CONFIG_DESTPER_T3MAT0_2  (15 << GPDMA_CONFIG_DESTPER_SHIFT) /* Timer3 match 0 */
+#define GPDMA_CONFIG_FCNTRL_SHIFT        (11)       /* Bits 11-13: Flow control and transfer type */
+#define GPDMA_CONFIG_FCNTRL_MASK         (7 << GPDMA_CONFIG_FCNTRL_SHIFT)
+#  define GPDMA_CONFIG_FCNTRL_M2M_DMA    (0 << GPDMA_CONFIG_FCNTRL_SHIFT) /* Memory to memory (DMA control) */
+#  define GPDMA_CONFIG_FCNTRL_M2P_DMA    (1 << GPDMA_CONFIG_FCNTRL_SHIFT) /* Memory to peripheral (DMA control) */
+#  define GPDMA_CONFIG_FCNTRL_P2M_DMA    (2 << GPDMA_CONFIG_FCNTRL_SHIFT) /* Peripheral to memory (DMA control) */
+#  define GPDMA_CONFIG_FCNTRL_P2P_DMA    (3 << GPDMA_CONFIG_FCNTRL_SHIFT) /* SRC peripheral to DEST peripheral (DMA control) */
+#  define GPDMA_CONFIG_FCNTRL_P2P_DEST   (4 << GPDMA_CONFIG_FCNTRL_SHIFT) /* SRC peripheral to DEST peripheral (DEST control) */
+#  define GPDMA_CONFIG_FCNTRL_M2P_PER    (5 << GPDMA_CONFIG_FCNTRL_SHIFT) /* Memory to peripheral (peripheral control) */
+#  define GPDMA_CONFIG_FCNTRL_P2M_PER    (6 << GPDMA_CONFIG_FCNTRL_SHIFT) /* Peripheral to memory (peripheral control) */
+#  define GPDMA_CONFIG_FCNTRL_P2P_SRC    (7 << GPDMA_CONFIG_FCNTRL_SHIFT) /* SRC peripheral to DEST peripheral (SRC control) */
+#define GPDMA_CONFIG_IE                  (1 << 14) /* Bit 14: Interrupt error mask */
+#define GPDMA_CONFIG_ITC                 (1 << 15) /* Bit 15: Terminal count interrupt mask */
+#define GPDMA_CONFIG_LOCK                (1 << 16) /* Bit 16: Lock */
+#define GPDMA_CONFIG_ACTIVE              (1 << 17) /* Bit 17: Active */
+#define GPDMA_CONFIG_HALT                (1 << 18) /* Bit 18: Halt */
+                                                   /* Bits 19-31: Reserved */
+
+/****************************************************************************************************
+ * Public Types
+ ****************************************************************************************************/
+
+/****************************************************************************************************
+ * Public Data
+ ****************************************************************************************************/
+
+/****************************************************************************************************
+ * Public Functions
+ ****************************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_GPDMA_H */
diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_gpio.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_gpio.h
new file mode 100644
index 000000000..6d3bb5d80
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_gpio.h
@@ -0,0 +1,439 @@
+/****************************************************************************************************
+ * arch/arm/src/lpc43xx/chip/lpc43_gpio.h
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_GPIO_H
+#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_GPIO_H
+
+/****************************************************************************************************
+ * Included Files
+ ****************************************************************************************************/
+
+#include <nuttx/config.h>
+
+/****************************************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************************************/
+
+ /* Register Offsets *********************************************************************************/
+
+/* Pin interrupt registers (relative to LPC43_GPIOINT_BASE) */
+
+#define LPC43_GPIOINT_ISEL_OFFSET   0x0000 /* Pin Interrupt Mode register */
+#define LPC43_GPIOINT_IENR_OFFSET   0x0004 /* Pin interrupt level (rising edge) interrupt enable register */
+#define LPC43_GPIOINT_SIENR_OFFSET  0x0008 /* Pin interrupt level (rising edge) interrupt set register */
+#define LPC43_GPIOINT_CIENR_OFFSET  0x000c /* Pin interrupt level (rising edge interrupt) clear register */
+#define LPC43_GPIOINT_IENF_OFFSET   0x0010 /* Pin interrupt active level (falling edge) interrupt enable register */
+#define LPC43_GPIOINT_SIENF_OFFSET  0x0014 /* Pin interrupt active level (falling edge) interrupt set register */
+#define LPC43_GPIOINT_CIENF_OFFSET  0x0018 /* Pin interrupt active level (falling edge) interrupt clear register */
+#define LPC43_GPIOINT_RISE_OFFSET   0x001c /* Pin interrupt rising edge register */
+#define LPC43_GPIOINT_FALL_OFFSET   0x0020 /* Pin interrupt falling edge register */
+#define LPC43_GPIOINT_IST_OFFSET    0x0024 /* Pin interrupt status register */
+
+/* GPIO GROUP interrupt registers (relative to either LPC43_GRP0INT_BASE or LPC43_GRP1INT_BASE) */
+
+#define LPC43_GRPINT_CTRL_OFFSET    0x0000 /* GPIO grouped interrupt control register */
+
+#define LPC43_GRPINT_POL_OFFSET(p)  (0x0020 + ((p) << 2 ))
+#define LPC43_GRPINT_POL0_OFFSET    0x0020 /* GPIO grouped interrupt port 0 polarity register */
+#define LPC43_GRPINT_POL1_OFFSET    0x0024 /* GPIO grouped interrupt port 1 polarity register */
+#define LPC43_GRPINT_POL2_OFFSET    0x0028 /* GPIO grouped interrupt port 2 polarity register */
+#define LPC43_GRPINT_POL3_OFFSET    0x002c /* GPIO grouped interrupt port 3 polarity register */
+#define LPC43_GRPINT_POL4_OFFSET    0x0030 /* GPIO grouped interrupt port 4 polarity register */
+#define LPC43_GRPINT_POL5_OFFSET    0x0034 /* GPIO grouped interrupt port 5 polarity register */
+#define LPC43_GRPINT_POL6_OFFSET    0x0038 /* GPIO grouped interrupt port 6 polarity register */
+#define LPC43_GRPINT_POL7_OFFSET    0x003c /* GPIO grouped interrupt port 7 polarity register */
+
+#define LPC43_GRPINT_ENA_OFFSET(p)  (0x0040 + ((p) << 2 ))
+#define LPC43_GRPINT_ENA0_OFFSET    0x0040 /* GPIO grouped interrupt port 0 enable register */
+#define LPC43_GRPINT_ENA1_OFFSET    0x0044 /* GPIO grouped interrupt port 1 enable register */
+#define LPC43_GRPINT_ENA2_OFFSET    0x0048 /* GPIO grouped interrupt port 2 enable register */
+#define LPC43_GRPINT_ENA3_OFFSET    0x004c /* GPIO grouped interrupt port 3 enable register */
+#define LPC43_GRPINT_ENA4_OFFSET    0x0050 /* GPIO grouped interrupt port 4 enable register */
+#define LPC43_GRPINT_ENA5_OFFSET    0x0054 /* GPIO grouped interrupt port 5 enable register */
+#define LPC43_GRPINT_ENA6_OFFSET    0x0058 /* GPIO grouped interrupt port 5 enable register */
+#define LPC43_GRPINT_ENA7_OFFSET    0x005c /* GPIO grouped interrupt port 5 enable register */
+
+/* GPIO Port Registers (relative to LPC43_GPIO_BASE) */
+
+#define LPC43_GPIO_B_OFFSET(p,n)    (((p) << 5) + (n))
+#define LPC43_GPIO_B0_OFFSET(n)     (0x0000 + (n)) /* PIO0_0 to PIO0_31 byte pin registers */
+#define LPC43_GPIO_B1_OFFSET(n)     (0x0020 + (n)) /* PIO1_0 to PIO1_31 byte pin registers */
+#define LPC43_GPIO_B2_OFFSET(n)     (0x0040 + (n)) /* PIO2_0 to PIO2_31 byte pin registers */
+#define LPC43_GPIO_B3_OFFSET(n)     (0x0060 + (n)) /* PIO3_0 to PIO3_31 byte pin registers */
+#define LPC43_GPIO_B4_OFFSET(n)     (0x0080 + (n)) /* PIO4_0 to PIO4_31 byte pin registers */
+#define LPC43_GPIO_B5_OFFSET(n)     (0x00a0 + (n)) /* PIO5_0 to PIO5_31 byte pin registers */
+#define LPC43_GPIO_B6_OFFSET(n)     (0x00c0 + (n)) /* PIO6_0 to PIO6_31 byte pin registers */
+#define LPC43_GPIO_B7_OFFSET(n)     (0x00e0 + (n)) /* PIO7_0 to PIO7_31 byte pin registers */
+
+#define LPC43_GPIO_W_OFFSET(p,n)    (0x1000 + ((p) << 7) + ((n) << 2))
+#define LPC43_GPIO_W0_OFFSET(n)     (0x1000 + ((n) << 2)) /* PIO0_0 to PIO0_31 word pin registers */
+#define LPC43_GPIO_W1_OFFSET(n)     (0x1080 + ((n) << 2)) /* PIO1_0 to PIO1_31 word pin registers */
+#define LPC43_GPIO_W2_OFFSET(n)     (0x1100 + ((n) << 2)) /* PIO2_0 to PIO2_31 word pin registers */
+#define LPC43_GPIO_W3_OFFSET(n)     (0x1180 + ((n) << 2)) /* PIO3_0 to PIO3_31 word pin registers */
+#define LPC43_GPIO_W4_OFFSET(n)     (0x1200 + ((n) << 2)) /* PIO4_0 to PIO4_31 word pin registers */
+#define LPC43_GPIO_W5_OFFSET(n)     (0x1280 + ((n) << 2)) /* PIO5_0 to PIO5_31 word pin registers */
+#define LPC43_GPIO_W6_OFFSET(n)     (0x1300 + ((n) << 2)) /* PIO6_0 to PIO6_31 word pin registers */
+#define LPC43_GPIO_W7_OFFSET(n)     (0x1380 + ((n) << 2)) /* PIO7_0 to PIO7_31 word pin registers */
+
+#define LPC43_GPIO_DIR_OFFSET(p)    (0x2000 + ((p) << 2))
+#define LPC43_GPIO_DIR0_OFFSET      0x2000 /* Direction registers port 0 */
+#define LPC43_GPIO_DIR1_OFFSET      0x2004 /* Direction registers port 1 */
+#define LPC43_GPIO_DIR2_OFFSET      0x2008 /* Direction registers port 2 */
+#define LPC43_GPIO_DIR3_OFFSET      0x200c /* Direction registers port 3 */
+#define LPC43_GPIO_DIR4_OFFSET      0x2010 /* Direction registers port 4 */
+#define LPC43_GPIO_DIR5_OFFSET      0x2014 /* Direction registers port 5 */
+#define LPC43_GPIO_DIR6_OFFSET      0x2018 /* Direction registers port 6 */
+#define LPC43_GPIO_DIR7_OFFSET      0x201c /* Direction registers port 7 */
+
+#define LPC43_GPIO_MASK_OFFSET(p)   (0x2080 + ((p) << 2))
+#define LPC43_GPIO_MASK0_OFFSET     0x2080 /* Mask register port 0 */
+#define LPC43_GPIO_MASK1_OFFSET     0x2084 /* Mask register port 1 */
+#define LPC43_GPIO_MASK2_OFFSET     0x2088 /* Mask register port 2 */
+#define LPC43_GPIO_MASK3_OFFSET     0x208c /* Mask register port 3 */
+#define LPC43_GPIO_MASK4_OFFSET     0x2090 /* Mask register port 4 */
+#define LPC43_GPIO_MASK5_OFFSET     0x2094 /* Mask register port 5 */
+#define LPC43_GPIO_MASK6_OFFSET     0x2098 /* Mask register port 6 */
+#define LPC43_GPIO_MASK7_OFFSET     0x209c /* Mask register port 7 */
+
+#define LPC43_GPIO_PIN_OFFSET(p)    (0x2100 + ((p) << 2))
+#define LPC43_GPIO_PIN0_OFFSET      0x2100 /* Port pin register port 0 */
+#define LPC43_GPIO_PIN1_OFFSET      0x2104 /* Port pin register port 1 */
+#define LPC43_GPIO_PIN2_OFFSET      0x2108 /* Port pin register port 2 */
+#define LPC43_GPIO_PIN3_OFFSET      0x210c /* Port pin register port 3 */
+#define LPC43_GPIO_PIN4_OFFSET      0x2110 /* Port pin register port 4 */
+#define LPC43_GPIO_PIN5_OFFSET      0x2114 /* Port pin register port 5 */
+#define LPC43_GPIO_PIN6_OFFSET      0x2118 /* Port pin register port 6 */
+#define LPC43_GPIO_PIN7_OFFSET      0x211c /* Port pin register port 7 */
+
+#define LPC43_GPIO_MPIN_OFFSET(p)   (0x2100 + ((p) << 2))
+#define LPC43_GPIO_MPIN0_OFFSET     0x2180 /* Masked port register port 0 */
+#define LPC43_GPIO_MPIN1_OFFSET     0x2184 /* Masked port register port 1 */
+#define LPC43_GPIO_MPIN2_OFFSET     0x2188 /* Masked port register port 2 */
+#define LPC43_GPIO_MPIN3_OFFSET     0x218c /* Masked port register port 3 */
+#define LPC43_GPIO_MPIN4_OFFSET     0x2190 /* Masked port register port 4 */
+#define LPC43_GPIO_MPIN5_OFFSET     0x2194 /* Masked port register port 5 */
+#define LPC43_GPIO_MPIN6_OFFSET     0x2198 /* Masked port register port 6 */
+#define LPC43_GPIO_MPIN7_OFFSET     0x219c /* Masked port register port 7 */
+
+#define LPC43_GPIO_SET_OFFSET(p)    (0x2200 + ((p) << 2))
+#define LPC43_GPIO_SET0_OFFSET      0x2200 /* Write: Set register for port 0 */
+#define LPC43_GPIO_SET1_OFFSET      0x2204 /* Write: Set register for port 1 */
+#define LPC43_GPIO_SET2_OFFSET      0x2208 /* Write: Set register for port 2 */
+#define LPC43_GPIO_SET3_OFFSET      0x220c /* Write: Set register for port 3 */
+#define LPC43_GPIO_SET4_OFFSET      0x2210 /* Write: Set register for port 4 */
+#define LPC43_GPIO_SET5_OFFSET      0x2214 /* Write: Set register for port 5 */
+#define LPC43_GPIO_SET6_OFFSET      0x2218 /* Write: Set register for port 6 */
+#define LPC43_GPIO_SET7_OFFSET      0x221c /* Write: Set register for port 7 */
+
+#define LPC43_GPIO_CLR_OFFSET(p)    (0x2280 + ((p) << 2))
+#define LPC43_GPIO_CLR0_OFFSET      0x2280 /* Clear port 0 */
+#define LPC43_GPIO_CLR1_OFFSET      0x2284 /* Clear port 1 */
+#define LPC43_GPIO_CLR2_OFFSET      0x2288 /* Clear port 2 */
+#define LPC43_GPIO_CLR3_OFFSET      0x228c /* Clear port 3 */
+#define LPC43_GPIO_CLR4_OFFSET      0x2290 /* Clear port 4 */
+#define LPC43_GPIO_CLR5_OFFSET      0x2294 /* Clear port 5 */
+#define LPC43_GPIO_CLR6_OFFSET      0x2298 /* Clear port 6 */
+#define LPC43_GPIO_CLR7_OFFSET      0x229c /* Clear port 7 */
+
+#define LPC43_GPIO_NOT_OFFSET(p)    (0x2300 + ((p) << 2))
+#define LPC43_GPIO_NOT0_OFFSET      0x2300 /* Toggle port 0 */
+#define LPC43_GPIO_NOT1_OFFSET      0x2304 /* Toggle port 1 */
+#define LPC43_GPIO_NOT2_OFFSET      0x2308 /* Toggle port 2 */
+#define LPC43_GPIO_NOT3_OFFSET      0x230c /* Toggle port 3 */
+#define LPC43_GPIO_NOT4_OFFSET      0x2310 /* Toggle port 4 */
+#define LPC43_GPIO_NOT5_OFFSET      0x2314 /* Toggle port 5 */
+#define LPC43_GPIO_NOT6_OFFSET      0x2318 /* Toggle port 6 */
+#define LPC43_GPIO_NOT7_OFFSET      0x231c /* Toggle port 7 */
+
+/* Register Addresses *******************************************************************************/
+
+/* Pin interrupt registers (relative to LPC43_GPIOINT_BASE) */
+
+#define LPC43_GPIOINT_ISEL          (LPC43_GPIOINT_BASE+LPC43_GPIOINT_ISEL_OFFSET)
+#define LPC43_GPIOINT_IENR          (LPC43_GPIOINT_BASE+LPC43_GPIOINT_IENR_OFFSET)
+#define LPC43_GPIOINT_SIENR         (LPC43_GPIOINT_BASE+LPC43_GPIOINT_SIENR_OFFSET)
+#define LPC43_GPIOINT_CIENR         (LPC43_GPIOINT_BASE+LPC43_GPIOINT_CIENR_OFFSET)
+#define LPC43_GPIOINT_IENF          (LPC43_GPIOINT_BASE+LPC43_GPIOINT_IENF_OFFSET)
+#define LPC43_GPIOINT_SIENF         (LPC43_GPIOINT_BASE+LPC43_GPIOINT_SIENF_OFFSET)
+#define LPC43_GPIOINT_CIENF         (LPC43_GPIOINT_BASE+LPC43_GPIOINT_CIENF_OFFSET)
+#define LPC43_GPIOINT_RISE          (LPC43_GPIOINT_BASE+LPC43_GPIOINT_RISE_OFFSET)
+#define LPC43_GPIOINT_FALL          (LPC43_GPIOINT_BASE+LPC43_GPIOINT_FALL_OFFSET)
+#define LPC43_GPIOINT_IST           (LPC43_GPIOINT_BASE+LPC43_GPIOINT_IST_OFFSET)
+
+/* GPIO GROUP0 interrupt registers (relative to LPC43_GRP0INT_BASE) */
+
+#define LPC43_GRP0INT_CTRL          (LPC43_GRP0INT_BASE+LPC43_GRPINT_CTRL_OFFSET)
+
+#define LPC43_GRP0INT_POL(p)        (LPC43_GRP0INT_BASE+LPC43_GRPINT_POL_OFFSET(p))
+#define LPC43_GRP0INT_POL0          (LPC43_GRP0INT_BASE+LPC43_GRPINT_POL0_OFFSET)
+#define LPC43_GRP0INT_POL1          (LPC43_GRP0INT_BASE+LPC43_GRPINT_POL1_OFFSET)
+#define LPC43_GRP0INT_POL2          (LPC43_GRP0INT_BASE+LPC43_GRPINT_POL2_OFFSET)
+#define LPC43_GRP0INT_POL3          (LPC43_GRP0INT_BASE+LPC43_GRPINT_POL3_OFFSET)
+#define LPC43_GRP0INT_POL4          (LPC43_GRP0INT_BASE+LPC43_GRPINT_POL4_OFFSET)
+#define LPC43_GRP0INT_POL5          (LPC43_GRP0INT_BASE+LPC43_GRPINT_POL5_OFFSET)
+#define LPC43_GRP0INT_POL6          (LPC43_GRP0INT_BASE+LPC43_GRPINT_POL6_OFFSET)
+#define LPC43_GRP0INT_POL7          (LPC43_GRP0INT_BASE+LPC43_GRPINT_POL7_OFFSET)
+
+#define LPC43_GRP0INT_ENA(p)        (LPC43_GRP0INT_BASE+LPC43_GRPINT_ENA_OFFSET(p))
+#define LPC43_GRP0INT_ENA0          (LPC43_GRP0INT_BASE+LPC43_GRPINT_ENA0_OFFSET)
+#define LPC43_GRP0INT_ENA1          (LPC43_GRP0INT_BASE+LPC43_GRPINT_ENA1_OFFSET)
+#define LPC43_GRP0INT_ENA2          (LPC43_GRP0INT_BASE+LPC43_GRPINT_ENA2_OFFSET)
+#define LPC43_GRP0INT_ENA3          (LPC43_GRP0INT_BASE+LPC43_GRPINT_ENA3_OFFSET)
+#define LPC43_GRP0INT_ENA4          (LPC43_GRP0INT_BASE+LPC43_GRPINT_ENA4_OFFSET)
+#define LPC43_GRP0INT_ENA5          (LPC43_GRP0INT_BASE+LPC43_GRPINT_ENA5_OFFSET)
+#define LPC43_GRP0INT_ENA6          (LPC43_GRP0INT_BASE+LPC43_GRPINT_ENA6_OFFSET)
+#define LPC43_GRP0INT_ENA7          (LPC43_GRP0INT_BASE+LPC43_GRPINT_ENA7_OFFSET)
+
+/* GPIO GROUP1 interrupt registers (relative to LPC43_GRP1INT_BASE) */
+
+#define LPC43_GRP1INT_CTRL          (LPC43_GRP1INT_BASE+LPC43_GRPINT_CTRL_OFFSET)
+
+#define LPC43_GRP1INT_POL(p)        (LPC43_GRP1INT_BASE+LPC43_GRPINT_POL_OFFSET(p))
+#define LPC43_GRP1INT_POL0          (LPC43_GRP1INT_BASE+LPC43_GRPINT_POL0_OFFSET)
+#define LPC43_GRP1INT_POL1          (LPC43_GRP1INT_BASE+LPC43_GRPINT_POL1_OFFSET)
+#define LPC43_GRP1INT_POL2          (LPC43_GRP1INT_BASE+LPC43_GRPINT_POL2_OFFSET)
+#define LPC43_GRP1INT_POL3          (LPC43_GRP1INT_BASE+LPC43_GRPINT_POL3_OFFSET)
+#define LPC43_GRP1INT_POL4          (LPC43_GRP1INT_BASE+LPC43_GRPINT_POL4_OFFSET)
+#define LPC43_GRP1INT_POL5          (LPC43_GRP1INT_BASE+LPC43_GRPINT_POL5_OFFSET)
+#define LPC43_GRP1INT_POL6          (LPC43_GRP1INT_BASE+LPC43_GRPINT_POL6_OFFSET)
+#define LPC43_GRP1INT_POL7          (LPC43_GRP1INT_BASE+LPC43_GRPINT_POL7_OFFSET)
+
+#define LPC43_GRP1INT_ENA(p)        (LPC43_GRP1INT_BASE+LPC43_GRPINT_ENA_OFFSET(p))
+#define LPC43_GRP1INT_ENA0          (LPC43_GRP1INT_BASE+LPC43_GRPINT_ENA0_OFFSET)
+#define LPC43_GRP1INT_ENA1          (LPC43_GRP1INT_BASE+LPC43_GRPINT_ENA1_OFFSET)
+#define LPC43_GRP1INT_ENA2          (LPC43_GRP1INT_BASE+LPC43_GRPINT_ENA2_OFFSET)
+#define LPC43_GRP1INT_ENA3          (LPC43_GRP1INT_BASE+LPC43_GRPINT_ENA3_OFFSET)
+#define LPC43_GRP1INT_ENA4          (LPC43_GRP1INT_BASE+LPC43_GRPINT_ENA4_OFFSET)
+#define LPC43_GRP1INT_ENA5          (LPC43_GRP1INT_BASE+LPC43_GRPINT_ENA5_OFFSET)
+#define LPC43_GRP1INT_ENA6          (LPC43_GRP1INT_BASE+LPC43_GRPINT_ENA6_OFFSET)
+#define LPC43_GRP1INT_ENA7          (LPC43_GRP1INT_BASE+LPC43_GRPINT_ENA7_OFFSET)
+
+/* GPIO Port Registers (relative to LPC43_GPIO_BASE) */
+
+#define LPC43_GPIO_B(p,n)           (LPC43_GPIO_BASE+LPC43_GPIO_B_OFFSET(p,n))
+#define LPC43_GPIO_B0(n)            (LPC43_GPIO_BASE+LPC43_GPIO_B0_OFFSET(n))
+#define LPC43_GPIO_B1(n)            (LPC43_GPIO_BASE+LPC43_GPIO_B1_OFFSET(n))
+#define LPC43_GPIO_B2(n)            (LPC43_GPIO_BASE+LPC43_GPIO_B2_OFFSET(n))
+#define LPC43_GPIO_B3(n)            (LPC43_GPIO_BASE+LPC43_GPIO_B3_OFFSET(n))
+#define LPC43_GPIO_B4(n)            (LPC43_GPIO_BASE+LPC43_GPIO_B4_OFFSET(n))
+#define LPC43_GPIO_B5(n)            (LPC43_GPIO_BASE+LPC43_GPIO_B5_OFFSET(n))
+#define LPC43_GPIO_B6(n)            (LPC43_GPIO_BASE+LPC43_GPIO_B6_OFFSET(n))
+#define LPC43_GPIO_B7(n)            (LPC43_GPIO_BASE+LPC43_GPIO_B7_OFFSET(n))
+
+#define LPC43_GPIO_W(p,n)           (LPC43_GPIO_BASE+LPC43_GPIO_W_OFFSET(p,n))
+#define LPC43_GPIO_W0(n)            (LPC43_GPIO_BASE+LPC43_GPIO_W0_OFFSET(n))
+#define LPC43_GPIO_W1(n)            (LPC43_GPIO_BASE+LPC43_GPIO_W1_OFFSET(n))
+#define LPC43_GPIO_W2(n)            (LPC43_GPIO_BASE+LPC43_GPIO_W2_OFFSET(n))
+#define LPC43_GPIO_W3(n)            (LPC43_GPIO_BASE+LPC43_GPIO_W3_OFFSET(n))
+#define LPC43_GPIO_W4(n)            (LPC43_GPIO_BASE+LPC43_GPIO_W4_OFFSET(n))
+#define LPC43_GPIO_W5(n)            (LPC43_GPIO_BASE+LPC43_GPIO_W5_OFFSET(n))
+#define LPC43_GPIO_W6(n)            (LPC43_GPIO_BASE+LPC43_GPIO_W6_OFFSET(n))
+#define LPC43_GPIO_W7(n)            (LPC43_GPIO_BASE+LPC43_GPIO_W7_OFFSET(n))
+
+#define LPC43_GPIO_DIR(p)           (LPC43_GPIO_BASE+LPC43_GPIO_DIR_OFFSET(p))
+#define LPC43_GPIO_DIR0             (LPC43_GPIO_BASE+LPC43_GPIO_DIR0_OFFSET)
+#define LPC43_GPIO_DIR1             (LPC43_GPIO_BASE+LPC43_GPIO_DIR1_OFFSET)
+#define LPC43_GPIO_DIR2             (LPC43_GPIO_BASE+LPC43_GPIO_DIR2_OFFSET)
+#define LPC43_GPIO_DIR3             (LPC43_GPIO_BASE+LPC43_GPIO_DIR3_OFFSET)
+#define LPC43_GPIO_DIR4             (LPC43_GPIO_BASE+LPC43_GPIO_DIR4_OFFSET)
+#define LPC43_GPIO_DIR5             (LPC43_GPIO_BASE+LPC43_GPIO_DIR5_OFFSET)
+#define LPC43_GPIO_DIR6             (LPC43_GPIO_BASE+LPC43_GPIO_DIR6_OFFSET)
+#define LPC43_GPIO_DIR7             (LPC43_GPIO_BASE+LPC43_GPIO_DIR7_OFFSET)
+
+#define LPC43_GPIO_MASK(p)          (LPC43_GPIO_BASE+LPC43_GPIO_MASK_OFFSET(p))
+#define LPC43_GPIO_MASK0            (LPC43_GPIO_BASE+LPC43_GPIO_MASK0_OFFSET)
+#define LPC43_GPIO_MASK1            (LPC43_GPIO_BASE+LPC43_GPIO_MASK1_OFFSET)
+#define LPC43_GPIO_MASK2            (LPC43_GPIO_BASE+LPC43_GPIO_MASK2_OFFSET)
+#define LPC43_GPIO_MASK3            (LPC43_GPIO_BASE+LPC43_GPIO_MASK3_OFFSET)
+#define LPC43_GPIO_MASK4            (LPC43_GPIO_BASE+LPC43_GPIO_MASK4_OFFSET)
+#define LPC43_GPIO_MASK5            (LPC43_GPIO_BASE+LPC43_GPIO_MASK5_OFFSET)
+#define LPC43_GPIO_MASK6            (LPC43_GPIO_BASE+LPC43_GPIO_MASK6_OFFSET)
+#define LPC43_GPIO_MASK7            (LPC43_GPIO_BASE+LPC43_GPIO_MASK7_OFFSET)
+
+#define LPC43_GPIO_PIN(p)           (LPC43_GPIO_BASE+LPC43_GPIO_PIN_OFFSET(p))
+#define LPC43_GPIO_PIN0             (LPC43_GPIO_BASE+LPC43_GPIO_PIN0_OFFSET)
+#define LPC43_GPIO_PIN1             (LPC43_GPIO_BASE+LPC43_GPIO_PIN1_OFFSET)
+#define LPC43_GPIO_PIN2             (LPC43_GPIO_BASE+LPC43_GPIO_PIN2_OFFSET)
+#define LPC43_GPIO_PIN3             (LPC43_GPIO_BASE+LPC43_GPIO_PIN3_OFFSET)
+#define LPC43_GPIO_PIN4             (LPC43_GPIO_BASE+LPC43_GPIO_PIN4_OFFSET)
+#define LPC43_GPIO_PIN5             (LPC43_GPIO_BASE+LPC43_GPIO_PIN5_OFFSET)
+#define LPC43_GPIO_PIN6             (LPC43_GPIO_BASE+LPC43_GPIO_PIN6_OFFSET)
+#define LPC43_GPIO_PIN7             (LPC43_GPIO_BASE+LPC43_GPIO_PIN7_OFFSET)
+
+#define LPC43_GPIO_MPIN(p)          (LPC43_GPIO_BASE+LPC43_GPIO_MPIN_OFFSET(p))
+#define LPC43_GPIO_MPIN0            (LPC43_GPIO_BASE+LPC43_GPIO_MPIN0_OFFSET)
+#define LPC43_GPIO_MPIN1            (LPC43_GPIO_BASE+LPC43_GPIO_MPIN1_OFFSET)
+#define LPC43_GPIO_MPIN2            (LPC43_GPIO_BASE+LPC43_GPIO_MPIN2_OFFSET)
+#define LPC43_GPIO_MPIN3            (LPC43_GPIO_BASE+LPC43_GPIO_MPIN3_OFFSET)
+#define LPC43_GPIO_MPIN4            (LPC43_GPIO_BASE+LPC43_GPIO_MPIN4_OFFSET)
+#define LPC43_GPIO_MPIN5            (LPC43_GPIO_BASE+LPC43_GPIO_MPIN5_OFFSET)
+#define LPC43_GPIO_MPIN6            (LPC43_GPIO_BASE+LPC43_GPIO_MPIN6_OFFSET)
+#define LPC43_GPIO_MPIN7            (LPC43_GPIO_BASE+LPC43_GPIO_MPIN7_OFFSET)
+
+#define LPC43_GPIO_SET(p)           (LPC43_GPIO_BASE+LPC43_GPIO_SET_OFFSET(p))
+#define LPC43_GPIO_SET0             (LPC43_GPIO_BASE+LPC43_GPIO_SET0_OFFSET)
+#define LPC43_GPIO_SET1             (LPC43_GPIO_BASE+LPC43_GPIO_SET1_OFFSET)
+#define LPC43_GPIO_SET2             (LPC43_GPIO_BASE+LPC43_GPIO_SET2_OFFSET)
+#define LPC43_GPIO_SET3             (LPC43_GPIO_BASE+LPC43_GPIO_SET3_OFFSET)
+#define LPC43_GPIO_SET4             (LPC43_GPIO_BASE+LPC43_GPIO_SET4_OFFSET)
+#define LPC43_GPIO_SET5             (LPC43_GPIO_BASE+LPC43_GPIO_SET5_OFFSET)
+#define LPC43_GPIO_SET6             (LPC43_GPIO_BASE+LPC43_GPIO_SET6_OFFSET)
+#define LPC43_GPIO_SET7             (LPC43_GPIO_BASE+LPC43_GPIO_SET7_OFFSET)
+
+#define LPC43_GPIO_CLR(p)           (LPC43_GPIO_BASE+LPC43_GPIO_CLR_OFFSET(p))
+#define LPC43_GPIO_CLR0             (LPC43_GPIO_BASE+LPC43_GPIO_CLR0_OFFSET)
+#define LPC43_GPIO_CLR1             (LPC43_GPIO_BASE+LPC43_GPIO_CLR1_OFFSET)
+#define LPC43_GPIO_CLR2             (LPC43_GPIO_BASE+LPC43_GPIO_CLR2_OFFSET)
+#define LPC43_GPIO_CLR3             (LPC43_GPIO_BASE+LPC43_GPIO_CLR3_OFFSET)
+#define LPC43_GPIO_CLR4             (LPC43_GPIO_BASE+LPC43_GPIO_CLR4_OFFSET)
+#define LPC43_GPIO_CLR5             (LPC43_GPIO_BASE+LPC43_GPIO_CLR5_OFFSET)
+#define LPC43_GPIO_CLR6             (LPC43_GPIO_BASE+LPC43_GPIO_CLR6_OFFSET)
+#define LPC43_GPIO_CLR7             (LPC43_GPIO_BASE+LPC43_GPIO_CLR7_OFFSET)
+
+#define LPC43_GPIO_NOT(p)           (LPC43_GPIO_BASE+LPC43_GPIO_NOT_OFFSET(p))
+#define LPC43_GPIO_NOT0             (LPC43_GPIO_BASE+LPC43_GPIO_NOT0_OFFSET)
+#define LPC43_GPIO_NOT1             (LPC43_GPIO_BASE+LPC43_GPIO_NOT1_OFFSET)
+#define LPC43_GPIO_NOT2             (LPC43_GPIO_BASE+LPC43_GPIO_NOT2_OFFSET)
+#define LPC43_GPIO_NOT3             (LPC43_GPIO_BASE+LPC43_GPIO_NOT3_OFFSET)
+#define LPC43_GPIO_NOT4             (LPC43_GPIO_BASE+LPC43_GPIO_NOT4_OFFSET)
+#define LPC43_GPIO_NOT5             (LPC43_GPIO_BASE+LPC43_GPIO_NOT5_OFFSET)
+#define LPC43_GPIO_NOT6             (LPC43_GPIO_BASE+LPC43_GPIO_NOT6_OFFSET)
+#define LPC43_GPIO_NOT7             (LPC43_GPIO_BASE+LPC43_GPIO_NOT7_OFFSET)
+
+/* Register Bit Definitions *************************************************************************/
+
+/* Pin Interrupt Mode register */
+
+#define GPIOINT_ISEL(i)             (1 << (i)) /* Bits 0-7: Selects the interrupt mode */
+
+/* Pin interrupt level (rising edge) interrupt enable register */
+
+#define GPIOINT_IENR(i)             (1 << (i)) /* Bits 0-7: Enables the rising edge or level interrupt */
+
+/* Pin interrupt level (rising edge) interrupt set register */
+
+#define GPIOINT_SIENR(i)            (1 << (i)) /* Bits 0-7: Set bits in the IENR, enabling interrupts */
+
+/* Pin interrupt level (rising edge interrupt) clear register */
+
+#define GPIOINT_CIENR(i)            (1 << (i)) /* Bits 0-7: Clears bits in the IENR, disabling interrupts */
+
+/* Pin interrupt active level (falling edge) interrupt enable register */
+
+#define GPIOINT_IENF(i)             (1 << (i)) /* Bits 0-7: Enables the falling edge or configures the active level interrupt */
+
+/* Pin interrupt active level (falling edge) interrupt set register */
+
+#define GPIOINT_SIENF(i)            (1 << (i)) /* Bits 0-7: Set bits in the IENF, enabling interrupts */
+
+/* Pin interrupt active level (falling edge) interrupt clear register */
+
+#define GPIOINT_CIENF(i)            (1 << (i)) /* Bits 0-7: Clears bits in the IENF, disabling interrupts */
+
+/* Pin interrupt rising edge register */
+
+#define GPIOINT_RISE(i)             (1 << (i)) /* Bits 0-7: Rising edge detect */
+
+/* Pin interrupt falling edge register */
+
+#define GPIOINT_FALL(i)             (1 << (i)) /* Bits 0-7: Falling edge detect */
+
+/* Pin interrupt status register */
+
+#define GPIOINT_IST(i)              (1 << (i)) /* Bits 0-7: Pin interrupt status */
+
+/* GPIO grouped interrupt control registers */
+
+#define GRPINT_CTRL_INT             (1 << 0)  /* Bit 0:  Group interrupt status */
+#define GRPINT_CTRL_COMB            (1 << 1)  /* Bit 1:  Combine enabled inputs for group interrupt */
+#define GRPINT_CTRL_TRIG            (1 << 2)  /* Bit 2:  Group interrupt trigger */
+                                              /* Bits 3-31:  Reserved */
+/* GPIO grouped interrupt polarity registers */
+
+#define GRPINT_POL(p)               (1 << (p)) /* Bits 0-31: Configure polarity of port pins */
+
+/* GPIO grouped interrupt enable registers */
+
+#define GRPINT_ENA(p)               (1 << (p)) /* Bits 0-31: Enable pin for group interrupt */
+
+/* Byte pin registers */
+
+#define GPIO_B                      (1 << 0)  /* Bit 0:  State of GPIO pin */
+                                              /* Bits 1-7: Reserved */
+/* Byte word registers.  On Read:  0x00000000 or 0xffffffff.  On write 0x0000000 or any
+ * non-zero value
+ */
+
+/* Direction registers */
+
+#define GPIO_DIR(p)                 (1 << (p)) /* Bits 0-31: Selects pin direction for pin */
+
+/* Mask registers */
+
+#define GPIO_MASK(p)                (1 << (p)) /* Bits 0-31: Controls which bits are active */
+
+/* Port pin registers */
+
+#define GPIO_PIN(p)                 (1 << (p)) /* Bits 0-31: Read/write pin state */
+
+/* Masked port registers */
+
+#define GPIO_MPIN(p)                (1 << (p)) /* Bits 0-31: Read/write masked pin state */
+
+/* Write: Set registers */
+
+#define GPIO_SET(p)                 (1 << (p)) /* Bits 0-31: Read or set output bits */
+
+/* Write: Clear registers */
+
+#define GPIO_CLR(p)                 (1 << (p)) /* Bits 0-31: Clear output bits */
+
+/* Toggle registers */
+
+#define GPIO_NOT(p)                 (1 << (p)) /* Bits 0-31: Toggle output bits */
+
+/****************************************************************************************************
+ * Public Types
+ ****************************************************************************************************/
+
+/****************************************************************************************************
+ * Public Data
+ ****************************************************************************************************/
+
+/****************************************************************************************************
+ * Public Functions
+ ****************************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_GPIO_H */
diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_i2c.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_i2c.h
new file mode 100644
index 000000000..000fbed51
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_i2c.h
@@ -0,0 +1,205 @@
+/************************************************************************************
+ * arch/arm/src/lpc43xx/lpc43_i2c.h
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_I2C_H
+#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_I2C_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Register offsets *****************************************************************/
+
+#define LPC43_I2C_CONSET_OFFSET    0x0000 /* I2C Control Set Register */
+#define LPC43_I2C_STAT_OFFSET      0x0004 /* I2C Status Register */
+#define LPC43_I2C_DAT_OFFSET       0x0008 /* I2C Data Register */
+#define LPC43_I2C_ADR0_OFFSET      0x000c /* I2C Slave Address Register 0 */
+#define LPC43_I2C_SCLH_OFFSET      0x0010 /* SCH Duty Cycle Register High Half Word */
+#define LPC43_I2C_SCLL_OFFSET      0x0014 /* SCL Duty Cycle Register Low Half Word */
+#define LPC43_I2C_CONCLR_OFFSET    0x0018 /* I2C Control Clear Register */
+#define LPC43_I2C_MMCTRL_OFFSET    0x001c /* Monitor mode control register */
+#define LPC43_I2C_ADR1_OFFSET      0x0020 /* I2C Slave Address Register 1 */
+#define LPC43_I2C_ADR2_OFFSET      0x0024 /* I2C Slave Address Register 2 */
+#define LPC43_I2C_ADR3_OFFSET      0x0028 /* I2C Slave Address Register 3 */
+#define LPC43_I2C_BUFR_OFFSET      0x002c /* Data buffer register */
+#define LPC43_I2C_MASK0_OFFSET     0x0030 /* I2C Slave address mask register 0 */
+#define LPC43_I2C_MASK1_OFFSET     0x0034 /* I2C Slave address mask register 1 */
+#define LPC43_I2C_MASK2_OFFSET     0x0038 /* I2C Slave address mask register 2 */
+#define LPC43_I2C_MASK3_OFFSET     0x003c /* I2C Slave address mask register */
+
+/* Register addresses ***************************************************************/
+
+#define LPC43_I2C0_CONSET          (LPC43_I2C0_BASE+LPC43_I2C_CONSET_OFFSET)
+#define LPC43_I2C0_STAT            (LPC43_I2C0_BASE+LPC43_I2C_STAT_OFFSET)
+#define LPC43_I2C0_DAT             (LPC43_I2C0_BASE+LPC43_I2C_DAT_OFFSET)
+#define LPC43_I2C0_ADR0            (LPC43_I2C0_BASE+LPC43_I2C_ADR0_OFFSET)
+#define LPC43_I2C0_SCLH            (LPC43_I2C0_BASE+LPC43_I2C_SCLH_OFFSET)
+#define LPC43_I2C0_SCLL            (LPC43_I2C0_BASE+LPC43_I2C_SCLL_OFFSET)
+#define LPC43_I2C0_CONCLR          (LPC43_I2C0_BASE+LPC43_I2C_CONCLR_OFFSET)
+#define LPC43_I2C0_MMCTRL          (LPC43_I2C0_BASE+LPC43_I2C_MMCTRL_OFFSET)
+#define LPC43_I2C0_ADR1            (LPC43_I2C0_BASE+LPC43_I2C_ADR1_OFFSET)
+#define LPC43_I2C0_ADR2            (LPC43_I2C0_BASE+LPC43_I2C_ADR2_OFFSET)
+#define LPC43_I2C0_ADR3            (LPC43_I2C0_BASE+LPC43_I2C_ADR3_OFFSET)
+#define LPC43_I2C0_BUFR            (LPC43_I2C0_BASE+LPC43_I2C_BUFR_OFFSET)
+#define LPC43_I2C0_MASK0           (LPC43_I2C0_BASE+LPC43_I2C_MASK0_OFFSET)
+#define LPC43_I2C0_MASK1           (LPC43_I2C0_BASE+LPC43_I2C_MASK1_OFFSET)
+#define LPC43_I2C0_MASK2           (LPC43_I2C0_BASE+LPC43_I2C_MASK2_OFFSET)
+#define LPC43_I2C0_MASK3           (LPC43_I2C0_BASE+LPC43_I2C_MASK3_OFFSET)
+
+#define LPC43_I2C1_CONSET          (LPC43_I2C1_BASE+LPC43_I2C_CONSET_OFFSET)
+#define LPC43_I2C1_STAT            (LPC43_I2C1_BASE+LPC43_I2C_STAT_OFFSET)
+#define LPC43_I2C1_DAT             (LPC43_I2C1_BASE+LPC43_I2C_DAT_OFFSET)
+#define LPC43_I2C1_ADR0            (LPC43_I2C1_BASE+LPC43_I2C_ADR0_OFFSET)
+#define LPC43_I2C1_SCLH            (LPC43_I2C1_BASE+LPC43_I2C_SCLH_OFFSET)
+#define LPC43_I2C1_SCLL            (LPC43_I2C1_BASE+LPC43_I2C_SCLL_OFFSET)
+#define LPC43_I2C1_CONCLR          (LPC43_I2C1_BASE+LPC43_I2C_CONCLR_OFFSET)
+#define LPC43_I2C1_MMCTRL          (LPC43_I2C1_BASE+LPC43_I2C_MMCTRL_OFFSET)
+#define LPC43_I2C1_ADR1            (LPC43_I2C1_BASE+LPC43_I2C_ADR1_OFFSET)
+#define LPC43_I2C1_ADR2            (LPC43_I2C1_BASE+LPC43_I2C_ADR2_OFFSET)
+#define LPC43_I2C1_ADR3            (LPC43_I2C1_BASE+LPC43_I2C_ADR3_OFFSET)
+#define LPC43_I2C1_BUFR            (LPC43_I2C1_BASE+LPC43_I2C_BUFR_OFFSET)
+#define LPC43_I2C1_MASK0           (LPC43_I2C1_BASE+LPC43_I2C_MASK0_OFFSET)
+#define LPC43_I2C1_MASK1           (LPC43_I2C1_BASE+LPC43_I2C_MASK1_OFFSET)
+#define LPC43_I2C1_MASK2           (LPC43_I2C1_BASE+LPC43_I2C_MASK2_OFFSET)
+#define LPC43_I2C1_MASK3           (LPC43_I2C1_BASE+LPC43_I2C_MASK3_OFFSET)
+
+#define LPC43_I2C2_CONSET          (LPC43_I2C2_BASE+LPC43_I2C_CONSET_OFFSET)
+#define LPC43_I2C2_STAT            (LPC43_I2C2_BASE+LPC43_I2C_STAT_OFFSET)
+#define LPC43_I2C2_DAT             (LPC43_I2C2_BASE+LPC43_I2C_DAT_OFFSET)
+#define LPC43_I2C2_ADR0            (LPC43_I2C2_BASE+LPC43_I2C_ADR0_OFFSET)
+#define LPC43_I2C2_SCLH            (LPC43_I2C2_BASE+LPC43_I2C_SCLH_OFFSET)
+#define LPC43_I2C2_SCLL            (LPC43_I2C2_BASE+LPC43_I2C_SCLL_OFFSET)
+#define LPC43_I2C2_CONCLR          (LPC43_I2C2_BASE+LPC43_I2C_CONCLR_OFFSET)
+#define LPC43_I2C2_MMCTRL          (LPC43_I2C2_BASE+LPC43_I2C_MMCTRL_OFFSET)
+#define LPC43_I2C2_ADR1            (LPC43_I2C2_BASE+LPC43_I2C_ADR1_OFFSET)
+#define LPC43_I2C2_ADR2            (LPC43_I2C2_BASE+LPC43_I2C_ADR2_OFFSET)
+#define LPC43_I2C2_ADR3            (LPC43_I2C2_BASE+LPC43_I2C_ADR3_OFFSET)
+#define LPC43_I2C2_BUFR            (LPC43_I2C2_BASE+LPC43_I2C_BUFR_OFFSET)
+#define LPC43_I2C2_MASK0           (LPC43_I2C2_BASE+LPC43_I2C_MASK0_OFFSET)
+#define LPC43_I2C2_MASK1           (LPC43_I2C2_BASE+LPC43_I2C_MASK1_OFFSET)
+#define LPC43_I2C2_MASK2           (LPC43_I2C2_BASE+LPC43_I2C_MASK2_OFFSET)
+#define LPC43_I2C2_MASK3           (LPC43_I2C2_BASE+LPC43_I2C_MASK3_OFFSET)
+
+/* Register bit definitions *********************************************************/
+/* I2C Control Set Register */
+                                             /* Bits 0-1: Reserved */
+#define I2C_CONSET_AA              (1 << 2)  /* Bit 2:  Assert acknowledge flag */
+#define I2C_CONSET_SI              (1 << 3)  /* Bit 3:  I2C interrupt flag */
+#define I2C_CONSET_STO             (1 << 4)  /* Bit 4:  STOP flag */
+#define I2C_CONSET_STA             (1 << 5)  /* Bit 5:  START flag */
+#define I2C_CONSET_I2EN            (1 << 6)  /* Bit 6:  I2C interface enable */
+                                             /* Bits 7-31: Reserved */
+/* I2C Control Clear Register */
+                                             /* Bits 0-1: Reserved */
+#define I2C_CONCLR_AAC             (1 << 2)  /* Bit 2:  Assert acknowledge Clear bit */
+#define I2C_CONCLR_SIC             (1 << 3)  /* Bit 3:  I2C interrupt Clear bit */
+                                             /* Bit 4:  Reserved */
+#define I2C_CONCLR_STAC            (1 << 5)  /* Bit 5:  START flag Clear bit */
+#define I2C_CONCLRT_I2ENC          (1 << 6)  /* Bit 6:  I2C interface Disable bit */
+                                             /* Bits 7-31: Reserved */
+/* I2C Status Register
+ *
+ *   See tables 997-1002 in the "LPC43xx User Manual" (UM10503), Rev. 1.2, 8 June
+ *   2012, NXP for definitions of status codes.
+ */
+
+#define I2C_STAT_MASK              (0xff)    /* Bits 0-7: I2C interface status
+                                              *           Bits 0-2 always zero */
+                                             /* Bits 8-31: Reserved */
+/* I2C Data Register */
+
+#define I2C_DAT_MASK               (0xff)    /* Bits 0-7: I2C data */
+                                             /* Bits 8-31: Reserved */
+/* Monitor mode control register */
+
+#define I2C_MMCTRL_MMENA           (1 << 0)  /* Bit 0:  Monitor mode enable */
+#define I2C_MMCTRL_ENASCL          (1 << 1)  /* Bit 1:  SCL output enable */
+#define I2C_MMCTRL_MATCHALL        (1 << 2)  /* Bit 2:  Select interrupt register match */
+                                             /* Bits 3-31: Reserved */
+/* Data buffer register */
+
+#define I2C_BUFR_MASK              (0xff)    /* Bits 0-7: 8 MSBs of the I2DAT shift register */
+                                             /* Bits 8-31: Reserved */
+/* I2C Slave address registers:
+ *
+ *   I2C Slave Address Register 0
+ *   I2C Slave Address Register 1
+ *   I2C Slave Address Register 2
+ *   I2C Slave Address Register 3
+ */
+
+#define I2C_ADR_GC                  (1 << 0) /* Bit 0: GC General Call enable bit */
+#define I2C_ADR_ADDR_SHIFT          (1)      /* Bits 1-7: I2C slave address */
+#define I2C_ADR_ADDR_MASK           (0x7f << I2C_ADR_ADDR_SHIFT)
+                                             /* Bits 8-31: Reserved */
+/* I2C Slave address mask registers:
+ *
+ *   I2C Slave address mask register 0
+ *   I2C Slave address mask register 1
+ *   I2C Slave address mask register 2
+ *   I2C Slave address mask register 3
+ */
+                                             /* Bit 0: Reserved */
+#define I2C_MASK_SHIFT              (1)      /* Bits 1-7: I2C mask bits */
+#define I2C_MASK_MASK               (0x7f << I2C_ADR_ADDR_SHIFT)
+                                             /* Bits 8-31: Reserved */
+/* SCH Duty Cycle Register High Half Word */
+
+#define I2C_SCLH_MASK               (0xffff) /* Bit 0-15: Count for SCL HIGH time period selection */
+                                             /* Bits 16-31: Reserved */
+/* SCL Duty Cycle Register Low Half Word */
+
+#define I2C_SCLL_MASK               (0xffff) /* Bit 0-15: Count for SCL LOW time period selection */
+                                             /* Bits 16-31: Reserved */
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_I2C_H */
diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_i2s.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_i2s.h
new file mode 100644
index 000000000..71fc875e9
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_i2s.h
@@ -0,0 +1,202 @@
+/************************************************************************************
+ * arch/arm/src/lpc43xx/lpc43_i2s
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_I2S_H
+#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_I2S_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Register offsets *****************************************************************/
+
+#define LPC43_I2S_DAO_OFFSET        0x0000 /* Digital Audio Output Register */
+#define LPC43_I2S_DAI_OFFSET        0x0004 /* Digital Audio Input Register */
+#define LPC43_I2S_TXFIFO_OFFSET     0x0008 /* Transmit FIFO */
+#define LPC43_I2S_RXFIFO_OFFSET     0x000c /* Receive FIFO */
+#define LPC43_I2S_STATE_OFFSET      0x0010 /* Status Feedback Register */
+#define LPC43_I2S_DMA1_OFFSET       0x0014 /* DMA Configuration Register 1 */
+#define LPC43_I2S_DMA2_OFFSET       0x0018 /* DMA Configuration Register 2 */
+#define LPC43_I2S_IRQ_OFFSET        0x001c /* Interrupt Request Control Register */
+#define LPC43_I2S_TXRATE_OFFSET     0x0020 /* Transmit MCLK divider */
+#define LPC43_I2S_RXRATE_OFFSET     0x0024 /* Receive MCLK divider */
+#define LPC43_I2S_TXBITRATE_OFFSET  0x0028 /* Transmit bit rate divider */
+#define LPC43_I2S_RXBITRATE_OFFSET  0x002c /* Receive bit rate divider */
+#define LPC43_I2S_TXMODE_OFFSET     0x0030 /* Transmit mode control */
+#define LPC43_I2S_RXMODE_OFFSET     0x0034 /* Receive mode control */
+
+/* Register addresses ***************************************************************/
+
+#define LPC43_I2S0_DAO              (LPC43_I2S0_BASE+LPC43_I2S_DAO_OFFSET)
+#define LPC43_I2S0_DAI              (LPC43_I2S0_BASE+LPC43_I2S_DAI_OFFSET)
+#define LPC43_I2S0_TXFIFO           (LPC43_I2S0_BASE+LPC43_I2S_TXFIFO_OFFSET)
+#define LPC43_I2S0_RXFIFO           (LPC43_I2S0_BASE+LPC43_I2S_RXFIFO_OFFSET)
+#define LPC43_I2S0_STATE            (LPC43_I2S0_BASE+LPC43_I2S_STATE_OFFSET)
+#define LPC43_I2S0_DMA1             (LPC43_I2S0_BASE+LPC43_I2S_DMA1_OFFSET)
+#define LPC43_I2S0_DMA2             (LPC43_I2S0_BASE+LPC43_I2S_DMA2_OFFSET)
+#define LPC43_I2S0_IRQ              (LPC43_I2S0_BASE+LPC43_I2S_IRQ_OFFSET)
+#define LPC43_I2S0_TXRATE           (LPC43_I2S0_BASE+LPC43_I2S_TXRATE_OFFSET)
+#define LPC43_I2S0_RXRATE           (LPC43_I2S0_BASE+LPC43_I2S_RXRATE_OFFSET)
+#define LPC43_I2S0_TXBITRATE        (LPC43_I2S0_BASE+LPC43_I2S_TXBITRATE_OFFSET)
+#define LPC43_I2S0_RXBITRATE        (LPC43_I2S0_BASE+LPC43_I2S_RXBITRATE_OFFSET)
+#define LPC43_I2S0_TXMODE           (LPC43_I2S0_BASE+LPC43_I2S_TXMODE_OFFSET)
+#define LPC43_I2S0_RXMODE           (LPC43_I2S0_BASE+LPC43_I2S_RXMODE_OFFSET)
+
+#define LPC43_I2S1_DAO              (LPC43_I2S1_BASE+LPC43_I2S_DAO_OFFSET)
+#define LPC43_I2S1_DAI              (LPC43_I2S1_BASE+LPC43_I2S_DAI_OFFSET)
+#define LPC43_I2S1_TXFIFO           (LPC43_I2S1_BASE+LPC43_I2S_TXFIFO_OFFSET)
+#define LPC43_I2S1_RXFIFO           (LPC43_I2S1_BASE+LPC43_I2S_RXFIFO_OFFSET)
+#define LPC43_I2S1_STATE            (LPC43_I2S1_BASE+LPC43_I2S_STATE_OFFSET)
+#define LPC43_I2S1_DMA1             (LPC43_I2S1_BASE+LPC43_I2S_DMA1_OFFSET)
+#define LPC43_I2S1_DMA2             (LPC43_I2S1_BASE+LPC43_I2S_DMA2_OFFSET)
+#define LPC43_I2S1_IRQ              (LPC43_I2S1_BASE+LPC43_I2S_IRQ_OFFSET)
+#define LPC43_I2S1_TXRATE           (LPC43_I2S1_BASE+LPC43_I2S_TXRATE_OFFSET)
+#define LPC43_I2S1_RXRATE           (LPC43_I2S1_BASE+LPC43_I2S_RXRATE_OFFSET)
+#define LPC43_I2S1_TXBITRATE        (LPC43_I2S1_BASE+LPC43_I2S_TXBITRATE_OFFSET)
+#define LPC43_I2S1_RXBITRATE        (LPC43_I2S1_BASE+LPC43_I2S_RXBITRATE_OFFSET)
+#define LPC43_I2S1_TXMODE           (LPC43_I2S1_BASE+LPC43_I2S_TXMODE_OFFSET)
+#define LPC43_I2S1_RXMODE           (LPC43_I2S1_BASE+LPC43_I2S_RXMODE_OFFSET)
+
+/* Register bit definitions *********************************************************/
+
+/* Digital Audio Output Register */
+
+#define I2S_DAO_WDWID_SHIFT         (0)       /* Bits 0-1: Selects the number of bytes in data */
+#define I2S_DAO_WDWID_MASK          (3 << I2S_DAO_WDWID_SHIFT)
+#  define I2S_DAO_WDWID_8BITS       (0 << I2S_DAO_WDWID_SHIFT)
+#  define I2S_DAO_WDWID_16BITS      (1 << I2S_DAO_WDWID_SHIFT)
+#  define I2S_DAO_WDWID_32BITS      (3 << I2S_DAO_WDWID_SHIFT)
+#define I2S_DAO_MONO                (1 << 2)  /* Bit 2:  Mono format */
+#define I2S_DAO_STOP                (1 << 3)  /* Bit 3:  Disable FIFOs / mute mode */
+#define I2S_DAO_RESET               (1 << 4)  /* Bit 4:  Reset TX channel and FIFO */
+#define I2S_DAO_WSSEL               (1 << 5)  /* Bit 5:  Slave mode select */
+#define I2S_DAO_WSHALFPER_SHIFT     (6)       /* Bits 6-14: Word select half period minus 1 */
+#define I2S_DAO_WSHALFPER_MASK      (0x01ff << I2S_DAO_WSHALFPER_SHIFT)
+#define I2S_DAO_MUTE                (1 << 15) /* Bit 15: Send only zeros on channel */
+                                              /* Bits 16-31: Reserved */
+/* Digital Audio Input Register */
+
+#define I2S_DAI_WDWID_SHIFT         (0)       /* Bits 0-1: Selects the number of bytes in data */
+#define I2S_DAI_WDWID_MASK          (3 << I2S_DAI_WDWID_SHIFT)
+#  define I2S_DAI_WDWID_8BITS       (0 << I2S_DAI_WDWID_SHIFT)
+#  define I2S_DAI_WDWID_16BITS      (1 << I2S_DAI_WDWID_SHIFT)
+#  define I2S_DAI_WDWID_32BITS      (3 << I2S_DAI_WDWID_SHIFT)
+#define I2S_DAI_MONO                (1 << 2)  /* Bit 2:  Mono format */
+#define I2S_DAI_STOP                (1 << 3)  /* Bit 3:  Disable FIFOs / mute mode */
+#define I2S_DAI_RESET               (1 << 4)  /* Bit 4:  Reset TX channel and FIFO */
+#define I2S_DAI_WSSEL               (1 << 5)  /* Bit 5:  Slave mode select */
+#define I2S_DAI_WSHALFPER_SHIFT     (6)       /* Bits 6-14: Word select half period minus 1 */
+#define I2S_DAI_WSHALFPER_MASK      (0x01ff << I2S_DAI_WSHALFPER_SHIFT)
+                                              /* Bits 15-31: Reserved */
+/* Transmit FIFO: 8 × 32-bit transmit FIFO */
+/* Receive FIFO: 8 × 32-bit receive FIFO */
+
+/* Status Feedback Register */
+
+#define I2S_STATE_IRQ               (1 << 0)  /* Bit 0:  Receive Transmit Interrupt */
+#define I2S_STATE_DMAREQ1           (1 << 1)  /* Bit 1:  Receive or Transmit DMA Request 1 */
+#define I2S_STATE_DMAREQ2           (1 << 2)  /* Bit 2:  Receive or Transmit DMA Request 2 */
+                                              /* Bits 3-7: Reserved */
+#define I2S_STATE_RXLEVEL_SHIFT     (8)       /* Bits 8-11: Current level of the Receive FIFO */
+#define I2S_STATE_RXLEVEL_MASK      (15 << I2S_STATE_RXLEVEL_SHIFT)
+                                              /* Bits 12-15: Reserved */
+#define I2S_STATE_TXLEVEL_SHIFT     (16)      /* Bits 16-19: Current level of the Transmit FIFO */
+#define I2S_STATE_TXLEVEL_MASK      (15 << I2S_STATE_TXLEVEL_SHIFT)
+                                              /* Bits 20-31: Reserved */
+/* DMA Configuration Register 1 and 2 */
+
+#define I2S_DMA_RXDMAEN             (1 << 0)  /* Bit 0:  Enable DMA1 for I2S receive */
+#define I2S_DMA_TXDMAEN             (1 << 1)  /* Bit 1:  Enable DMA1 for I2S transmit */
+                                              /* Bits 2-7: Reserved */
+#define I2S_DMA_RXDEPTH_SHIFT       (8)       /* Bits 8-11: FIFO level that triggers RX request on DMA1 */
+#define I2S_DMA_RXDEPTH_MASK        (15 << I2S_DMA_RXDEPTH_SHIFT)
+                                              /* Bits 12-15: Reserved */
+#define I2S_DMA_TXDEPTH_SHIFT       (16)      /* Bits 16-19: FIFO level that triggers a TX request on DMA1 */
+#define I2S_DMA_TXDEPTH_MASK        (15 << I2S_DMA_TXDEPTH_SHIFT)
+                                              /* Bits 20-31: Reserved */
+/* Interrupt Request Control Register */
+
+#define I2S_IRQ_RXEN                (1 << 0)  /* Bit 0:  Enable I2S receive interrupt */
+#define I2S_IRQ_TXEN                (1 << 1)  /* Bit 1:  Enable I2S transmit interrupt */
+                                              /* Bits 2-7: Reserved */
+#define I2S_IRQ_RXDEPTH_SHIFT       (8)       /* Bits 8-11: Set FIFO level for irq request */
+#define I2S_IRQ_RXDEPTH_MASK        (15 << I2S_IRQ_RXDEPTH_SHIFT)
+                                              /* Bits 12-15: Reserved */
+#define I2S_IRQ_TXDEPTH_SHIFT       (16)      /* Bits 16-19: Set FIFO level for irq request */
+#define I2S_IRQ_TXDEPTH_MASK        (15 << I2S_IRQ_TXDEPTH_SHIFT)
+                                              /* Bits 20-31: Reserved */
+/* Transmit and Receive MCLK divider */
+
+#define I2S_RATE_YDIV_SHIFT         (0)       /* Bits 0-7: I2S transmit MCLK rate denominator */
+#define I2S_RATE_YDIV_MASK          (0xff << I2S_RATE_YDIV_SHIFT)
+#define I2S_RATE_XDIV_SHIFT         (8)       /* Bits 8-15: I2S transmit MCLK rate numerator */
+#define I2S_RATE_XDIV_MASK          (0xff << I2S_RATE_XDIV_SHIFT)
+                                              /* Bits 16-31: Reserved */
+
+/* Transmit and received bit rate divider */
+
+#define I2S_BITRATE_SHIFT           (0)       /* Bits 0-5: I2S transmit bit rate */
+#define I2S_BITRATE_MASK            (0x3f << I2S_BITRATE_SHIFT)
+                                              /* Bits 6-31: Reserved */
+/* Transmit and Receive mode control */
+
+#define I2S_MODE_CLKSEL_SHIFT       (0)       /* Bits 0-1: Clock source for bit clock divider */
+#define I2S_MODE_CLKSEL_MASK        (3 << I2S_MODE_CLKSEL_SHIFT)
+#  define I2S_MODE_CLKSEL_FRACDIV   (0 << I2S_MODE_CLKSEL_SHIFT) /* TX/RX fractional rate divider */
+#  define I2S_MODE_CLKSEL_RXMCLK    (2 << I2S_MODE_CLKSEL_SHIFT) /* RX_CLCK for TX_MCLK source */
+#  define I2S_MODE_CLKSEL_TXMCLK    (2 << I2S_MODE_CLKSEL_SHIFT) /* TX_CLCK for RX_MCLK source */
+#define I2S_MODE_4PIN               (1 << 2)  /* Bit 2:  Transmit/Receive 4-pin mode selection */
+#define I2S_MODE_MCENA              (1 << 3)  /* Bit 3:  Enable for the TX/RX_MCLK output */
+                                              /* Bits 4-31: Reserved */
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_I2S_H */
diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_lcd.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_lcd.h
new file mode 100644
index 000000000..5762bed5e
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_lcd.h
@@ -0,0 +1,304 @@
+/****************************************************************************************************
+ * arch/arm/src/lpc43xx/chip/lpc43_lcd.h
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_LCD_H
+#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_LCD_H
+
+/****************************************************************************************************
+ * Included Files
+ ****************************************************************************************************/
+
+#include <nuttx/config.h>
+
+/****************************************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************************************/
+/* Register Offsets *********************************************************************************/
+
+#define LPC43_LCD_TIMH_OFFSET         0x000 /* Horizontal Timing Control register */
+#define LPC43_LCD_TIMV_OFFSET         0x004 /* Vertical Timing Control register */
+#define LPC43_LCD_POL_OFFSET          0x008 /* Clock and Signal Polarity Control register */
+#define LPC43_LCD_LE_OFFSET           0x00c /* Line End Control register */
+#define LPC43_LCD_UPBASE_OFFSET       0x010 /* Upper Panel Frame Base Address register */
+#define LPC43_LCD_LPBASE_OFFSET       0x014 /* Lower Panel Frame Base Address register */
+#define LPC43_LCD_CTRL_OFFSET         0x018 /* LCD Control register */
+#define LPC43_LCD_INTMSK_OFFSET       0x01c /* Interrupt Mask register */
+#define LPC43_LCD_INTRAW_OFFSET       0x020 /* Raw Interrupt Status register */
+#define LPC43_LCD_INTSTAT_OFFSET      0x024 /* Masked Interrupt Status register */
+#define LPC43_LCD_INTCLR_OFFSET       0x028 /* Interrupt Clear register */
+#define LPC43_LCD_UPCURR_OFFSET       0x02c /* Upper Panel Current Address Value register */
+#define LPC43_LCD_LPCURR_OFFSET       0x030 /* Lower Panel Current Address Value register */
+
+/*  0x200 to 0x3fc 256x16-bit Color Palette registers */
+
+#define LPC43_LCD_PAL_OFFSET(n)       (0x200 + ((n) << 2)) /* n=0..128, two colors per word */
+
+/* 0x800 to 0xbfc Cursor Image registers */
+
+#define LPC43_LCD_CRSR_IMG_OFFSET(n)  (0x800 + ((n) << 2)) /* n = 0..256 */
+
+#define LPC43_LCD_CRSR_CTRL_OFFSET    0xc00 /* Cursor Control register */
+#define LPC43_LCD_CRSR_CFG_OFFSET     0xc04 /* Cursor Configuration register */
+#define LPC43_LCD_CRSR_PAL0_OFFSET    0xc08 /* Cursor Palette register 0 */
+#define LPC43_LCD_CRSR_PAL1_OFFSET    0xc0c /* Cursor Palette register 1 */
+#define LPC43_LCD_CRSR_XY_OFFSET      0xc10 /* Cursor XY Position register */
+#define LPC43_LCD_CRSR_CLIP_OFFSET    0xc14 /* Cursor Clip Position register */
+#define LPC43_LCD_CRSR_INTMSK_OFFSET  0xc20 /* Cursor Interrupt Mask register */
+#define LPC43_LCD_CRSR_INTCLR_OFFSET  0xc24 /* Cursor Interrupt Clear register */
+#define LPC43_LCD_CRSR_INTRAW_OFFSET  0xc28 /* Cursor Raw Interrupt Status register */
+#define LPC43_LCD_CRSR_INTSTAT_OFFSET 0xc2c /* Cursor Masked Interrupt Status register */
+
+/* Register Addresses *******************************************************************************/
+
+#define LPC43_LCD_TIMH                (LPC43_LCD_BASE+LPC43_LCD_TIMH_OFFSET)
+#define LPC43_LCD_TIMV                (LPC43_LCD_BASE+LPC43_LCD_TIMV_OFFSET)
+#define LPC43_LCD_POL                 (LPC43_LCD_BASE+LPC43_LCD_POL_OFFSET)
+#define LPC43_LCD_LE                  (LPC43_LCD_BASE+LPC43_LCD_LE_OFFSET)
+#define LPC43_LCD_UPBASE              (LPC43_LCD_BASE+LPC43_LCD_UPBASE_OFFSET)
+#define LPC43_LCD_LPBASE              (LPC43_LCD_BASE+LPC43_LCD_LPBASE_OFFSET)
+#define LPC43_LCD_CTRL                (LPC43_LCD_BASE+LPC43_LCD_CTRL_OFFSET)
+#define LPC43_LCD_INTMSK              (LPC43_LCD_BASE+LPC43_LCD_INTMSK_OFFSET)
+#define LPC43_LCD_INTRAW              (LPC43_LCD_BASE+LPC43_LCD_INTRAW_OFFSET)
+#define LPC43_LCD_INTSTAT             (LPC43_LCD_BASE+LPC43_LCD_INTSTAT_OFFSET)
+#define LPC43_LCD_INTCLR              (LPC43_LCD_BASE+LPC43_LCD_INTCLR_OFFSET)
+#define LPC43_LCD_UPCURR              (LPC43_LCD_BASE+LPC43_LCD_UPCURR_OFFSET)
+#define LPC43_LCD_LPCURR              (LPC43_LCD_BASE+LPC43_LCD_LPCURR_OFFSET)
+
+/*  0x200 to 0x3fc 256x16-bit Color Palette registers */
+
+#define LPC43_LCD_PAL(n)              (LPC43_LCD_BASE+LPC43_LCD_PAL_OFFSET(n))
+
+/* 0x800 to 0xbfc Cursor Image registers */
+
+#define LPC43_LCD_CRSR_IMG(n)         (LPC43_LCD_BASE+LPC43_LCD_CRSR_IMG_OFFSET(n))
+
+#define LPC43_LCD_CRSR_CTRL           (LPC43_LCD_BASE+LPC43_LCD_CRSR_CTRL_OFFSET)
+#define LPC43_LCD_CRSR_CFG            (LPC43_LCD_BASE+LPC43_LCD_CRSR_CFG_OFFSET)
+#define LPC43_LCD_CRSR_PAL0           (LPC43_LCD_BASE+LPC43_LCD_CRSR_PAL0_OFFSET)
+#define LPC43_LCD_CRSR_PAL1           (LPC43_LCD_BASE+LPC43_LCD_CRSR_PAL1_OFFSET)
+#define LPC43_LCD_CRSR_XY             (LPC43_LCD_BASE+LPC43_LCD_CRSR_XY_OFFSET)
+#define LPC43_LCD_CRSR_CLIP           (LPC43_LCD_BASE+LPC43_LCD_CRSR_CLIP_OFFSET)
+#define LPC43_LCD_CRSR_INTMSK         (LPC43_LCD_BASE+LPC43_LCD_CRSR_INTMSK_OFFSET)
+#define LPC43_LCD_CRSR_INTCLR         (LPC43_LCD_BASE+LPC43_LCD_CRSR_INTCLR_OFFSET)
+#define LPC43_LCD_CRSR_INTRAW         (LPC43_LCD_BASE+LPC43_LCD_CRSR_INTRAW_OFFSET)
+#define LPC43_LCD_CRSR_INTSTAT        (LPC43_LCD_BASE+LPC43_LCD_CRSR_INTSTAT_OFFSET)
+
+/* Register Bit Definitions *************************************************************************/
+
+/* Horizontal Timing Control register */
+
+                                                /* Bits 0-1: Reserved */
+#define LCD_TIMH_PPL_SHIFT            (2)       /* Bits 2-7: Pixels-per-line */
+#define LCD_TIMH_PPL_MASK             (0x3f << LCD_TIMH_PPL_SHIFT)
+#define LCD_TIMH_HSW_SHIFT            (8)       /* Bits 8-15: Horizontal synchronization pulse width */
+#define LCD_TIMH_HSW_MASK             (0xff << LCD_TIMH_HSW_SHIFT)
+#define LCD_TIMH_HFP_SHIFT            (16)      /* Bits 16-23:  Horizontal front porch */
+#define LCD_TIMH_HFP_MASK             (0xff << LCD_TIMH_HFP_SHIFT)
+#define LCD_TIMH_HBP_SHIFT            (24)      /* Bits 24-31:  Horizontal back porch */
+#define LCD_TIMH_HBP_MASK             (0xff << LCD_TIMH_HBP_SHIFT)
+                                                /* Bit nn: Reserved */
+/* Vertical Timing Control register */
+
+#define LCD_TIMV_LPP_SHIFT            (0)       /* Bits 0-9: Lines per panel */
+#define LCD_TIMV_LPP_MASK             (0x3ff << LCD_TIMV_LPP_SHIFT)
+#define LCD_TIMV_VSW_SHIFT            (10)      /* Bits 10-15: Vertical synchronization pulse width */
+#define LCD_TIMV_VSW_MASK             (0x3f << LCD_TIMV_VSW_SHIFT)
+#define LCD_TIMV_VFP_SHIFT            (16)      /* Bits 16-23: Vertical front porch */
+#define LCD_TIMV_VFP_MASK             (0xff << LCD_TIMV_VFP_SHIFT)
+#define LCD_TIMV_VBP_SHIFT            (24)      /* Bits 24-31: Vertical back porch */
+#define LCD_TIMV_VBP_MASK             (0xff << LCD_TIMV_VBP_SHIFT)
+
+/* Clock and Signal Polarity Control register */
+
+#define LCD_POL_PCDLO_SHIFT           (0)       /* Bits 0-4: Lower five bits of panel clock divisor */
+#define LCD_POL_PCDLO_MASK            (31 << LCD_POL_PCDLO_SHIFT)
+#define LCD_POL_CLKSEL                (1 << 5)  /* Bit 5:  Clock Select */
+#define LCD_POL_ACB_SHIFT             (6)       /* Bits 6-10: AC bias pin frequency */
+#define LCD_POL_ACB_MASK              (31 << LCD_POL_ACB_SHIFT)
+#define LCD_POL_IVS                   (1 << 11) /* Bit 11: Invert vertical synchronization */
+#define LCD_POL_IHS                   (1 << 12) /* Bit 12: Invert horizontal synchronization */
+#define LCD_POL_IPC                   (1 << 13) /* Bit 13: Invert panel clock */
+#define LCD_POL_IOE                   (1 << 14) /* Bit 14: Invert output enable */
+                                                /* Bit 15: Reserved */
+#define LCD_POL_CPL_SHIFT             (16)      /* Bits 16-25: Clocks per line */
+#define LCD_POL_CPL_MASK              (0x3ff << LCD_POL_CPL_SHIFT)
+#define LCD_POL_BCD                   (1 << 26) /* Bit 26: Bypass pixel clock divider */
+#define LCD_POL_PCDHI_SHIFT           (27)       /* Bits 27-31: Upper five bits of panel clock divisor */
+#define LCD_POL_PCDHI_MASK            (31 << LCD_POL_PCDHI_SHIFT)
+
+/* Line End Control register */
+
+#define LCD_LE_DELAY_SHIFT            (0)       /* Bits 0-6: Line-end delay */
+#define LCD_LE_DELAY_MASK             (0x7f << LCD_LE_DELAY_SHIFT)
+                                                /* Bits 7-15: Reserved */
+#define LCD_LE_ENA                    (1 << 16) /* Bit 16: LCD Line end enable */
+                                                /* Bits 17-31: Reserved */
+
+/* Upper Panel Frame Base Address register */
+                                                /* Bits 0-2: Reserved */
+#define LCD_UPBASE_SHIFT              (3)       /* Bits 3-31: Upper panel base address */
+#define LCD_UPBASE_MASK               (0xfffffff8)
+
+/* Lower Panel Frame Base Address register */
+                                                /* Bits 0-2: Reserved */
+#define LCD_LPBASE_SHIFT              (3)       /* Bits 3-31: Lower panel base address */
+#define LCD_LPBASE_MASK               (0xfffffff8)
+
+/* LCD Control register */
+
+#define LCD_CTRL_LCDEN                (1 << 0)  /* Bit 0:  LCD enable control bit */
+#define LCD_CTRL_LCDBPP_SHIFT         (1)       /* Bits 1-3: LCD bits per pixel */
+#define LCD_CTRL_LCDBPP_MASK          (7 << LCD_CTRL_LCDBPP_SHIFT)
+#  define LCD_CTRL_LCDBPP_1BPP        (0 << LCD_CTRL_LCDBPP_SHIFT) /* 1 bpp */
+#  define LCD_CTRL_LCDBPP_2BPP        (1 << LCD_CTRL_LCDBPP_SHIFT) /* 2 bpp */
+#  define LCD_CTRL_LCDBPP_4BPP        (2 << LCD_CTRL_LCDBPP_SHIFT) /* 4 bpp */
+#  define LCD_CTRL_LCDBPP_8BPP        (3 << LCD_CTRL_LCDBPP_SHIFT) /* 8 bpp */
+#  define LCD_CTRL_LCDBPP_16BPP       (4 << LCD_CTRL_LCDBPP_SHIFT) /* 16 bpp */
+#  define LCD_CTRL_LCDBPP_24BPP       (5 << LCD_CTRL_LCDBPP_SHIFT) /* 24 bpp (TFT panel only) */
+#  define LCD_CTRL_LCDBPP_RGB565      (6 << LCD_CTRL_LCDBPP_SHIFT) /* 16 bpp, 5:6:5 mode */
+#  define LCD_CTRL_LCDBPP_RGB444      (7 << LCD_CTRL_LCDBPP_SHIFT) /* 12 bpp, 4:4:4 mode */
+#define LCD_CTRL_LCDBW                (1 << 4)  /* Bit 4:  STN LCD monochrome/color selection */
+#define LCD_CTRL_LCDTFT               (1 << 5)  /* Bit 5:  LCD panel TFT type selection */
+#define LCD_CTRL_LCDMONO8             (1 << 6)  /* Bit 6:  Monochrome LCD interface width */
+#define LCD_CTRL_LCDDUAL              (1 << 7)  /* Bit 7:  Single or Dual LCD panel selection */
+#define LCD_CTRL_BGR                  (1 << 8)  /* Bit 8:  Color format selection */
+#define LCD_CTRL_BEBO                 (1 << 9)  /* Bit 9:  Big-endian Byte Order */
+#define LCD_CTRL_BEPO                 (1 << 10) /* Bit 10: Big-Endian Pixel Ordering */
+#define LCD_CTRL_LCDPWR               (1 << 11) /* Bit 11: LCD power enable */
+#define LCD_CTRL_LCDVCOMP_SHIFT       (12)      /* Bits 12-13: LCD vertical compare interrupt */
+#define LCD_CTRL_LCDVCOMP_MASK        (3 << LCD_CTRL_LCDVCOMP_SHIFT)
+#  define LCD_CTRL_LCDVCOMP_START     (0 << LCD_CTRL_LCDVCOMP_SHIFT) /* Start of vertical synchronization */
+#  define LCD_CTRL_LCDVCOMP_BACK      (1 << LCD_CTRL_LCDVCOMP_SHIFT) /* Start of back porch */
+#  define LCD_CTRL_LCDVCOMP_ACTIVE    (2 << LCD_CTRL_LCDVCOMP_SHIFT) /* Start of active video */
+#  define LCD_CTRL_LCDVCOMP_FRONT     (3 << LCD_CTRL_LCDVCOMP_SHIFT) /* Start of front porch */
+                                                /* Bits 14-15: Reserved */
+#define LCD_INTMSK_WATERMARK          (1 << 16) /* Bit 16: LCD DMA FIFO watermark level */
+                                                /* Bits 17-31: Reserved */
+/* Interrupt Mask register */
+/* Raw Interrupt Status register */
+/* Masked Interrupt Status register */
+/* Interrupt Clear register */
+
+
+                                                /* Bit 0: Reserved */
+#define LCD_INT_FUFI                  (1 << 1)  /* Bit 1:  FIFO underflow interrupt */
+#define LCD_INT_LNBUI                 (1 << 2)  /* Bit 2:  LCD next base address update interrupt enable */
+#define LCD_INT_VCOMPI                (1 << 3)  /* Bit 3:  Vertical compare interrupt enable */
+#define LCD_INT_BERI                  (1 << 4)  /* Bit 4:  AHB master error interrupt enable */
+                                                /* Bits 5-31: Reserved */
+/* Upper Panel Current Address Value register (32-bit address) */
+/* Lower Panel Current Address Value register (32-bit address) */
+
+/*  256x16-bit Color Palette registers */
+
+#define LCD_PAL_R0_SHIFT              (0)       /* Bits 0-4: Red palette data */
+#define LCD_PAL_R0_MASK               (31 << LCD_PAL_R0_SHIFT)
+#define LCD_PAL_G0_SHIFT              (5)       /* Bits 5-9: Green palette data */
+#define LCD_PAL_G0_MASK               (31 << LCD_PAL_G0_SHIFT)
+#define LCD_PAL_B0_SHIFT              (10)      /* Bits 10-14: Blue palette data */
+#define LCD_PAL_B0_MASK               (31 << LCD_PAL_B0_SHIFT)
+#define LCD_PAL_I0                    (1 << 16) /* Bit 15: Intensity / unused bit */
+#define LCD_PAL_R1_SHIFT              (16)      /* Bits 16-20: Red palette data */
+#define LCD_PAL_R1_MASK               (31 << LCD_PAL_R1_SHIFT)
+#define LCD_PAL_G1_SHIFT              (21)      /* Bits 21-25: Green palette data */
+#define LCD_PAL_G1_MASK               (31 << LCD_PAL_G1_SHIFT)
+#define LCD_PAL_B1_SHIFT              (26)      /* Bits 26-30: Blue palette data */
+#define LCD_PAL_B1_MASK               (31 << LCD_PAL_B1_SHIFT)
+#define LCD_PAL_I1                    (1 << 31) /* Bit 31: Intensity / unused bit */
+
+/* Cursor Image registers (32-bit image data) */
+
+/* Cursor Control register */
+
+#define LCD_CRSR_CTRL_ON              (1 << 0)  /* Bit 0:  Cursor enable */
+                                                /* Bits 1-3: Reserved */
+#define LCD_CRSR_CTRL_NUM_SHIFT       (4)       /* Bits 4-5: Cursor image number */
+#define LCD_CRSR_CTRL_NUM_MASK        (3 << LCD_CRSR_CTRL_NUM_SHIFT)
+#  define LCD_CRSR_CTRL_NUM_0         (0 << LCD_CRSR_CTRL_NUM_SHIFT)
+#  define LCD_CRSR_CTRL_NUM_1         (1 << LCD_CRSR_CTRL_NUM_SHIFT)
+#  define LCD_CRSR_CTRL_NUM_2         (2 << LCD_CRSR_CTRL_NUM_SHIFT)
+#  define LCD_CRSR_CTRL_NUM_3         (3 << LCD_CRSR_CTRL_NUM_SHIFT)
+                                                /* Bits 6-31: Reserved */
+/* Cursor Configuration register */
+
+#define LCD_CRSR_CFG_CRSRSIZE         (1 << 0)  /* Bit 0:  Cursor size selection */
+#define LCD_CRSR_CFG_FRAMESYNC        (1 << 1)  /* Bit 1:  Cursor frame synchronization type */
+                                                /* Bits 2-31: Reserved */
+/* Cursor Palette register 0/1 */
+
+#define LCD_CRSR_PAL_RED_SHIFT        (0)       /* Bits 0-7: Red color component */
+#define LCD_CRSR_PAL_RED_MASK         (0xff << LCD_CRSR_PAL_RED_SHIFT)
+#define LCD_CRSR_PAL_GREEN_SHIFT      (8)       /* Bits 8-15: Green color component */
+#define LCD_CRSR_PAL_GREEN_MASK       (0xff << LCD_CRSR_PAL_GREEN_SHIFT)
+#define LCD_CRSR_PAL_BLUE_SHIFT       (16)       /* Bits 16-23: Blue color component */
+#define LCD_CRSR_PAL_BLUE_MASK        (0xff << LCD_CRSR_PAL_BLUE_SHIFT)
+                                                /* Bits 24-31: Reserved */
+/* Cursor XY Position register */
+
+#define LCD_CRSRX_SHIFT               (0)       /* Bits 0-9: X ordinate of the cursor origin measured in pixels */
+#define LCD_CRSRX_MASK                (0x3ff << LCD_CRSRX_SHIFT)
+                                                /* Bits 10-15: Reserved */
+#define LCD_CRSRY_SHIFT               (16)      /* Bits 16-25: Y ordinate of the cursor origin measured in pixels */
+#define LCD_CRSRY_MASK                (0x3ff << LCD_CRSRY_SHIFT)
+                                                /* Bits 26-31: Reserved */
+/* Cursor Clip Position register */
+
+#define LCD_CRSR_CLIPX_SHIFT          (0)       /* Bits 0-5: Cursor clip position for X direction */
+#define LCD_CRSR_CLIPX_MASK           (0x3f << LCD_CRSR_CLIPX_SHIFT)
+                                                /* Bits 6-7: Reserved */
+#define LCD_CRSR_CLIPY_SHIFT          (8)       /* Bits 8-13: Cursor clip position for Y direction */
+#define LCD_CRSR_CLIPY_MASK           (0x3f << LCD_CRSR_CLIPY_SHIFT)
+                                                /* Bits 14-31: Reserved */
+/* Cursor Interrupt Mask register */
+/* Cursor Interrupt Clear register */
+/* Cursor Raw Interrupt Status register */
+/* Cursor Masked Interrupt Status register */
+
+#define LCD_CRSR_INT                  (1 << 0)  /* CRSRIM Cursor interrupt */
+                                                /* Bits 1-31: Reserved */
+
+/****************************************************************************************************
+ * Public Types
+ ****************************************************************************************************/
+
+/****************************************************************************************************
+ * Public Data
+ ****************************************************************************************************/
+
+/****************************************************************************************************
+ * Public Functions
+ ****************************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_LCD_H */
diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_mcpwm.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_mcpwm.h
new file mode 100644
index 000000000..6344c24c9
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_mcpwm.h
@@ -0,0 +1,274 @@
+/************************************************************************************
+ * arch/arm/src/lpc43xx/lpc43_mcpwm.h
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_MCPWM_H
+#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_MCPWM_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Register offsets *****************************************************************/
+
+#define LPC43_MCPWM_CON_OFFSET       0x0000 /* PWM Control read address */
+#define LPC43_MCPWM_CONSET_OFFSET    0x0004 /* PWM Control set address */
+#define LPC43_MCPWM_CONCLR_OFFSET    0x0008 /* PWM Control clear address */
+#define LPC43_MCPWM_CAPCON_OFFSET    0x000c /* Capture Control read address */
+#define LPC43_MCPWM_CAPCONSET_OFFSET 0x0010 /* Capture Control set address */
+#define LPC43_MCPWM_CAPCONCLR_OFFSET 0x0014 /* Event Control clear address */
+#define LPC43_MCPWM_TC0_OFFSET       0x0018 /* Timer Counter register, channel 0 */
+#define LPC43_MCPWM_TC1_OFFSET       0x001c /* Timer Counter register, channel 1 */
+#define LPC43_MCPWM_TC2_OFFSET       0x0020 /* Timer Counter register, channel 2 */
+#define LPC43_MCPWM_LIM0_OFFSET      0x0024 /* Limit register, channel 0 */
+#define LPC43_MCPWM_LIM1_OFFSET      0x0028 /* Limit register, channel 1 */
+#define LPC43_MCPWM_LIM2_OFFSET      0x002c /* Limit register, channel 2 */
+#define LPC43_MCPWM_MAT0_OFFSET      0x0030 /* Match register, channel 0 */
+#define LPC43_MCPWM_MAT1_OFFSET      0x0034 /* Match register, channel 1 */
+#define LPC43_MCPWM_MAT2_OFFSET      0x0038 /* Match register, channel 2 */
+#define LPC43_MCPWM_DT_OFFSET        0x003c /* Dead time register */
+#define LPC43_MCPWM_MCCP_OFFSET      0x0040 /* Communication Pattern register */
+#define LPC43_MCPWM_CAP0_OFFSET      0x0044 /* Capture register, channel 0 */
+#define LPC43_MCPWM_CAP1_OFFSET      0x0048 /* Capture register, channel 1 */
+#define LPC43_MCPWM_CAP2_OFFSET      0x004c /* Capture register, channel 2 */
+#define LPC43_MCPWM_INTEN_OFFSET     0x0050 /* Interrupt Enable read address */
+#define LPC43_MCPWM_INTENSET_OFFSET  0x0054 /* Interrupt Enable set address */
+#define LPC43_MCPWM_INTENCLR_OFFSET  0x0058 /* Interrupt Enable clear address */
+#define LPC43_MCPWM_CNTCON_OFFSET    0x005c /* Count Control read address */
+#define LPC43_MCPWM_CNTCONSET_OFFSET 0x0060 /* Count Control set address */
+#define LPC43_MCPWM_CNTCONCLR_OFFSET 0x0064 /* Count Control clear address */
+#define LPC43_MCPWM_INTF_OFFSET      0x0068 /* Interrupt flags read address */
+#define LPC43_MCPWM_INTFSET_OFFSET   0x006c /* Interrupt flags set address */
+#define LPC43_MCPWM_INTFCLR_OFFSET   0x0070 /* Interrupt flags clear address */
+#define LPC43_MCPWM_CAPCLR_OFFSET    0x0074 /* Capture clear address */
+
+/* Register addresses ***************************************************************/
+
+#define LPC43_MCPWM_CON              (LPC43_MCPWM_BASE+LPC43_MCPWM_CON_OFFSET)
+#define LPC43_MCPWM_CONSET           (LPC43_MCPWM_BASE+LPC43_MCPWM_CONSET_OFFSET)
+#define LPC43_MCPWM_CONCLR           (LPC43_MCPWM_BASE+LPC43_MCPWM_CONCLR_OFFSET)
+#define LPC43_MCPWM_CAPCON           (LPC43_MCPWM_BASE+LPC43_MCPWM_CAPCON_OFFSET)
+#define LPC43_MCPWM_CAPCONSET        (LPC43_MCPWM_BASE+LPC43_MCPWM_CAPCONSET_OFFSET)
+#define LPC43_MCPWM_CAPCONCLR        (LPC43_MCPWM_BASE+LPC43_MCPWM_CAPCONCLR_OFFSET)
+#define LPC43_MCPWM_TC0              (LPC43_MCPWM_BASE+LPC43_MCPWM_TC0_OFFSET)
+#define LPC43_MCPWM_TC1              (LPC43_MCPWM_BASE+LPC43_MCPWM_TC1_OFFSET)
+#define LPC43_MCPWM_TC2              (LPC43_MCPWM_BASE+LPC43_MCPWM_TC2_OFFSET)
+#define LPC43_MCPWM_LIM0             (LPC43_MCPWM_BASE+LPC43_MCPWM_LIM0_OFFSET)
+#define LPC43_MCPWM_LIM1             (LPC43_MCPWM_BASE+LPC43_MCPWM_LIM1_OFFSET)
+#define LPC43_MCPWM_LIM2             (LPC43_MCPWM_BASE+LPC43_MCPWM_LIM2_OFFSET)
+#define LPC43_MCPWM_MAT0             (LPC43_MCPWM_BASE+LPC43_MCPWM_MAT0_OFFSET)
+#define LPC43_MCPWM_MAT1             (LPC43_MCPWM_BASE+LPC43_MCPWM_MAT1_OFFSET)
+#define LPC43_MCPWM_MAT2             (LPC43_MCPWM_BASE+LPC43_MCPWM_MAT2_OFFSET)
+#define LPC43_MCPWM_DT               (LPC43_MCPWM_BASE+LPC43_MCPWM_DT_OFFSET)
+#define LPC43_MCPWM_MCCP             (LPC43_MCPWM_BASE+LPC43_MCPWM_MCCP_OFFSET)
+#define LPC43_MCPWM_CAP0             (LPC43_MCPWM_BASE+LPC43_MCPWM_CAP0_OFFSET)
+#define LPC43_MCPWM_CAP1             (LPC43_MCPWM_BASE+LPC43_MCPWM_CAP1_OFFSET)
+#define LPC43_MCPWM_CAP2             (LPC43_MCPWM_BASE+LPC43_MCPWM_CAP2_OFFSET)
+#define LPC43_MCPWM_INTEN            (LPC43_MCPWM_BASE+LPC43_MCPWM_INTEN_OFFSET)
+#define LPC43_MCPWM_INTENSET         (LPC43_MCPWM_BASE+LPC43_MCPWM_INTENSET_OFFSET)
+#define LPC43_MCPWM_INTENCLR         (LPC43_MCPWM_BASE+LPC43_MCPWM_INTENCLR_OFFSET)
+#define LPC43_MCPWM_CNTCON           (LPC43_MCPWM_BASE+LPC43_MCPWM_CNTCON_OFFSET)
+#define LPC43_MCPWM_CNTCONSET        (LPC43_MCPWM_BASE+LPC43_MCPWM_CNTCONSET_OFFSET)
+#define LPC43_MCPWM_CNTCONCLR        (LPC43_MCPWM_BASE+LPC43_MCPWM_CNTCONCLR_OFFSET)
+#define LPC43_MCPWM_INTF             (LPC43_MCPWM_BASE+LPC43_MCPWM_INTF_OFFSET)
+#define LPC43_MCPWM_INTFSET          (LPC43_MCPWM_BASE+LPC43_MCPWM_INTFSET_OFFSET)
+#define LPC43_MCPWM_INTFCLR          (LPC43_MCPWM_BASE+LPC43_MCPWM_INTFCLR_OFFSET)
+#define LPC43_MCPWM_CAPCLR           (LPC43_MCPWM_BASE+LPC43_MCPWM_CAPCLR_OFFSET)
+
+/* Register bit definitions *********************************************************/
+/* There are no bit field definitions for the following registers because they support
+ * 32-bit values:
+ *
+ * - Timer Counter register, channel 0 (TC0), Timer Counter register, channel 1 (TC1),
+ *   and Timer Counter register, channel 2 (TC2): 32-bit Timer/Counter values for
+ *   channels 0, 1, 2 (no bit field definitions)
+ *
+ * - Limit register, channel 0 (LIM0), Limit register, channel 1 (LIM1), and Limit
+ *   register, channel 2 (LIM2): 32-bit Limit values for TC0, 1, 2 (no bit field
+ *   definitions)
+ *
+ * - Match register, channel 0 MAT0), Match register, channel 1 (MAT1), and Match
+ *   register, channel 2 (MAT2): 32-bit Match values for TC0, 1, 2 (no bit field
+ *   definitions).
+ *
+ * - Capture register, channel 0 (CAP0), Capture register, channel 1 (CAP1), and
+ *   Capture register, channel 2 (CAP2): 32-bit TC value at a capture event for
+ *  channels 0, 1, 2 (no bit field definitions)
+ */
+
+/* PWM Control read address (CON), PWM Control set address (CONSET), and PWM Control
+ * clear address (CONCLR) common regiser bit definitions.
+ */
+
+#define MCPWM_CON_RUN0               (1 << 0)  /* Bit 0:  Stops/starts timer channel 0 */
+#define MCPWM_CON_CENTER0            (1 << 1)  /* Bit 1:  Chan 0 edge/center aligned operation */
+#define MCPWM_CON_POLA0              (1 << 2)  /* Bit 2:  Polarity of MCOA0 and MCOB0 */
+#define MCPWM_CON_DTE0               (1 << 3)  /* Bit 3:  Dead time feature control */
+#define MCPWM_CON_DISUP0             (1 << 4)  /* Bit 4:  Enable/disable register updates */
+                                               /* Bits 5-7: Reserved */
+#define MCPWM_CON_RUN1               (1 << 8)  /* Bit 8:  Stops/starts timer channel 1 */
+#define MCPWM_CON_CENTER1            (1 << 9)  /* Bit 9:  Chan 1 edge/center aligned operation */
+#define MCPWM_CON_POLA1              (1 << 10) /* Bit 10: Polarity of MCOA1 and MCOB1 */
+#define MCPWM_CON_DTE1               (1 << 11) /* Bit 11: Dead time feature control */
+#define MCPWM_CON_DISUP1             (1 << 12) /* Bit 12: Enable/disable register updates */
+                                               /* Bits 13-15: Reserved */
+#define MCPWM_CON_RUN2               (1 << 16) /* Bit 16:  Stops/starts timer channel 2 */
+#define MCPWM_CON_CENTER2            (1 << 17) /* Bit 17:  Chan 2 edge/center aligned operation */
+#define MCPWM_CON_POLA2              (1 << 18) /* Bit 18: Polarity of MCOA1 and MCOB1 */
+#define MCPWM_CON_DTE2               (1 << 19) /* Bit 19: Dead time feature control */
+#define MCPWM_CON_DISUP2             (1 << 20) /* Bit 20: Enable/disable register updates */
+                                               /* Bits 21-28: Reserved */
+#define MCPWM_CON_INVBDC             (1 << 29) /* Bit 29: Polarity of MCOB outputs (all channels)  */
+#define MCPWM_CON_ACMODE             (1 << 30) /* Bit 30: 3-phase AC mode select */
+#define MCPWM_CON_DCMODE             (1 << 31) /* Bit 31: 3-phase DC mode select */
+
+/* Capture Control read address (CAPCON), Capture Control set address (CAPCONSET),
+ * and Event Control clear address (CAPCONCLR) common register bit defintions
+ */
+
+#define MCPWM_CAPCON_CAP0MCI0RE      (1 << 0)  /* Bit 0:  Enable chan0 rising edge capture MCI0 */
+#define MCPWM_CAPCON_CAP0MCI0FE      (1 << 1)  /* Bit 1:  Enable chan 0 falling edge capture MCI0 */
+#define MCPWM_CAPCON_CAP0MCI1RE      (1 << 2)  /* Bit 2:  Enable chan 0 rising edge capture MCI1 */
+#define MCPWM_CAPCON_CAP0MCI1FE      (1 << 3)  /* Bit 3:  Enable chan 0 falling edge capture MCI1 */
+#define MCPWM_CAPCON_CAP0MCI2RE      (1 << 4)  /* Bit 4:  Enable chan 0 rising edge capture MCI2 */
+#define MCPWM_CAPCON_CAP0MCI2FE      (1 << 5)  /* Bit 5:  Enable chan 0 falling edge capture MCI2 */
+#define MCPWM_CAPCON_CAP1MCI0RE      (1 << 6)  /* Bit 6:  Enable chan 1 rising edge capture MCI0 */
+#define MCPWM_CAPCON_CAP1MCI0FE      (1 << 7)  /* Bit 7:  Enable chan 1 falling edge capture MCI0 */
+#define MCPWM_CAPCON_CAP1MCI1RE      (1 << 8)  /* Bit 8:  Enable chan 1 rising edge capture MCI1 */
+#define MCPWM_CAPCON_CAP1MCI1FE      (1 << 9)  /* Bit 9:  Enable chan 1 falling edge capture MCI1 */
+#define MCPWM_CAPCON_CAP1MCI2RE      (1 << 10) /* Bit 10: Enable chan 1 rising edge capture MCI2 */
+#define MCPWM_CAPCON_CAP1MCI2FE      (1 << 11) /* Bit 11: Enable chan 1 falling edge capture MCI2 */
+#define MCPWM_CAPCON_CAP2MCI0RE      (1 << 12) /* Bit 12: Enable chan 2 rising edge capture MCI0 */
+#define MCPWM_CAPCON_CAP2MCI0FE      (1 << 13) /* Bit 13: Enable chan 2 falling edge capture MCI0 */
+#define MCPWM_CAPCON_CAP2MCI1RE      (1 << 14) /* Bit 14: Enable chan 2 rising edge capture MCI1 */
+#define MCPWM_CAPCON_CAP2MCI1FE      (1 << 15) /* Bit 15: Enable chan 2 falling edge capture MCI1 */
+#define MCPWM_CAPCON_CAP2MCI2RE      (1 << 16) /* Bit 16: Enable chan 2 rising edge capture MCI2 */
+#define MCPWM_CAPCON_CAP2MCI2FE      (1 << 17) /* Bit 17: Enable chan 2 falling edge capture MCI2 */
+#define MCPWM_CAPCON_RT0             (1 << 18) /* Bit 18: TC0 reset by chan 0 capture event */
+#define MCPWM_CAPCON_RT1             (1 << 19) /* Bit 19: TC1 reset by chan 1 capture event */
+#define MCPWM_CAPCON_RT2             (1 << 20) /* Bit 20: TC2 reset by chan 2 capture event */
+                                               /* Bits 21-31: Reserved
+/* Dead time register */
+
+#define MCPWM_DT_DT0_SHIFT           (0)       /* Bits 0-9: Dead time for channel 0 */
+#define MCPWM_DT_DT0_MASK            (0x03ff << MCPWM_DT_DT0_SHIFT)
+#define MCPWM_DT_DT1_SHIFT           (10)      /* Bits 10-19: Dead time for channel 1 */
+#define MCPWM_DT_DT1_MASK            (0x03ff << MCPWM_DT_DT1_SHIFT)
+#define MCPWM_DT_DT2_SHIFT           (20)      /* Bits 20-29: Dead time for channel 2 */
+#define MCPWM_DT_DT2_MASK            (0x03ff << MCPWM_DT_DT2_SHIFT)
+                                               /* Bits 30-31: reserved */
+/* Communication Pattern register */
+
+#define MCPWM_MCCP_CCPA0             (1 << 0)  /* Bit 0:  Iinternal MCOA0 */
+#define MCPWM_MCCP_CCPB0             (1 << 1)  /* Bit 1:  MCOB0 tracks internal MCOA0 */
+#define MCPWM_MCCP_CCPA1             (1 << 2)  /* Bit 2:  MCOA1 tracks internal MCOA0 */
+#define MCPWM_MCCP_CCPB1             (1 << 3)  /* Bit 3:  MCOB1 tracks internal MCOA0 */
+#define MCPWM_MCCP_CCPA2             (1 << 4)  /* Bit 4:  MCOA2 tracks internal MCOA0 */
+#define MCPWM_MCCP_CCPB2             (1 << 5)  /* Bit 5:  MCOB2 tracks internal MCOA0 */
+                                               /* Bits 6-31: reserved */
+
+/* Interrupt Enable read address (INTEN), Interrupt Enable set address (INTENSET),
+ * Interrupt Enable clear address (INTENCLR), Interrupt flags read address (INTF),
+ * Interrupt flags set address (INTFSET), and Interrupt flags clear address (INTFCLR)
+ * common bit field definitions
+ */
+
+#define MCPWM_INT_ILIM0              (1 << 0)  /* Bit 0:  Limit interrupts for channel 0 */
+#define MCPWM_INT_IMAT0              (1 << 1)  /* Bit 1:  Match interrupts for channel 0 */
+#define MCPWM_INT_ICAP0              (1 << 2)  /* Bit 2:  Capture interrupts for channel 0 */
+                                               /* Bit 3:  Reserved */
+#define MCPWM_INT_ILIM1              (1 << 4)  /* Bit 4:  Limit interrupts for channel 1 */
+#define MCPWM_INT_IMAT1              (1 << 5)  /* Bit 5:  Match interrupts for channel 1 */
+#define MCPWM_INT_ICAP1              (1 << 6)  /* Bit 6:  Capture interrupts for channel 1 */
+                                               /* Bit 7:  Reserved */
+#define MCPWM_INT_ILIM2              (1 << 8)  /* Bit 8:  Limit interrupts for channel 2 */
+#define MCPWM_INT_IMAT2              (1 << 9)  /* Bit 9:  Match interrupts for channel 2 */
+#define MCPWM_INT_ICAP2              (1 << 10) /* Bit 10: Capture interrupts for channel 2 */
+                                               /* Bits 11-14:  Reserved */
+#define MCPWM_INT_ABORT              (1 << 15) /* Bit 15:  Fast abort interrupt */
+                                               /* Bits 16-31: Reserved */
+
+/* Count Control read address (CNTCON), Count Control set address (CNTCONSET), and
+ * Count Control clear address (CNTCONCLR) common register bit definitions.
+ */
+
+#define MCPWM_CNTCON_TC0MCI0RE       (1 << 0)  /* Bit 0:  Counter 0 incr on rising edge MCI0 */
+#define MCPWM_CNTCON_TC0MCI0FE       (1 << 1)  /* Bit 1:  Counter 0 incr onfalling edge MCI0 */
+#define MCPWM_CNTCON_TC0MCI1RE       (1 << 2)  /* Bit 2:  Counter 0 incr onrising edge MCI1 */
+#define MCPWM_CNTCON_TC0MCI1FE       (1 << 3)  /* Bit 3:  Counter 0 incr onfalling edge MCI1 */
+#define MCPWM_CNTCON_TC0MCI2RE       (1 << 4)  /* Bit 4:  Counter 0 incr onrising edge MCI2 */
+#define MCPWM_CNTCON_TC0MCI2FE       (1 << 5)  /* Bit 5:  Counter 0 incr onfalling edge MCI2 */
+#define MCPWM_CNTCON_TC1MCI0RE       (1 << 6)  /* Bit 6:  Counter 1 incr onrising edge MCI0 */
+#define MCPWM_CNTCON_TC1MCI0FE       (1 << 7)  /* Bit 7:  Counter 1 incr onfalling edge MCI0 */
+#define MCPWM_CNTCON_TC1MCI1RE       (1 << 8)  /* Bit 8:  Counter 1 incr onrising edge MCI1 */
+#define MCPWM_CNTCON_TC1MCI1FE       (1 << 9)  /* Bit 9:  Counter 1 incr onfalling edge MCI1 */
+#define MCPWM_CNTCON_TC1MCI2RE       (1 << 10) /* Bit 10: Counter 1 incr onrising edge MCI2 */
+#define MCPWM_CNTCON_TC1MCI2FE       (1 << 11) /* Bit 11: Counter 1 incr onfalling edge MCI2 */
+#define MCPWM_CNTCON_TC2MCI0RE       (1 << 12) /* Bit 12: Counter 2 incr onrising edge MCI0 */
+#define MCPWM_CNTCON_TC2MCI0FE       (1 << 13) /* Bit 13: Counter 2 incr onfalling edge MCI0 */
+#define MCPWM_CNTCON_TC2MCI1RE       (1 << 14) /* Bit 14: Counter 2 incr onrising edge MCI1 */
+#define MCPWM_CNTCON_TC2MCI1FE       (1 << 15) /* Bit 15: Counter 2 incr onfalling edge MCI1 */
+#define MCPWM_CNTCON_TC2MCI2RE       (1 << 16) /* Bit 16: Counter 2 incr onrising edge MCI2 */
+#define MCPWM_CNTCON_TC2MCI2FE       (1 << 17) /* Bit 17: Counter 2 incr onfalling edge MCI2 */
+                                               /* Bits 18-28: Reserved */
+#define MCPWM_CNTCON_CNTR0           (1 << 29) /* Bit 29: Channel 0 counter mode */
+#define MCPWM_CNTCON_CNTR1           (1 << 30) /* Bit 30: Channel 1 counter mode */
+#define MCPWM_CNTCON_CNTR2           (1 << 31) /* Bit 31: Channel 2 counter mode */
+
+/* Capture clear address */
+
+#define MCPWM_CAPCLR_CLR0            (1 << 0)  /* Bit 0:  Clear CAP0 register */
+#define MCPWM_CAPCLR_CLR1            (1 << 1)  /* Bit 1:  Clear CAP1 register */
+#define MCPWM_CAPCLR_CLR2            (1 << 2)  /* Bit 2:  Clear CAP2 register */
+                                               /* Bits 2-31: Reserved */ 
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_MCPWM_H */
diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_otp.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_otp.h
new file mode 100644
index 000000000..67b5af319
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_otp.h
@@ -0,0 +1,192 @@
+/************************************************************************************
+ * arch/arm/src/lpc43xx/chip/lpc43_otp.h
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_OTP_H
+#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_OTP_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+/* Register Offsets *****************************************************************/
+
+#define LPC43_OTP_MEM00_OFFSET   0x0010  /* General purpose OTP memory 0, word 0 */
+#define LPC43_OTP_MEM01_OFFSET   0x0014  /* General purpose OTP memory 0, word 1 */
+#define LPC43_OTP_MEM02_OFFSET   0x0018  /* General purpose OTP memory 0, word 2 */
+#define LPC43_OTP_MEM03_OFFSET   0x001c  /* General purpose OTP memory 0, word 3 */
+
+#define LPC43_OTP_MEM10_OFFSET   0x0020  /* General purpose OTP memory 1, word 0 */
+#define LPC43_OTP_MEM11_OFFSET   0x0024  /* General purpose OTP memory 1, word 1 */
+#define LPC43_OTP_MEM12_OFFSET   0x0028  /* General purpose OTP memory 1, word 2 */
+#define LPC43_OTP_MEM13_OFFSET   0x002c  /* General purpose OTP memory 1, word 3 */
+
+#define LPC43_OTP_MEM20_OFFSET   0x0034  /* General purpose OTP memory 2, word 0 */
+#define LPC43_OTP_MEM21_OFFSET   0x0038  /* General purpose OTP memory 2, word 1 */
+#define LPC43_OTP_MEM22_OFFSET   0x003c  /* General purpose OTP memory 2, word 2 */ 
+
+#define LPC43_OTP_AES00_OFFSET   0x0010  /* AES key 0, word 0 */
+#define LPC43_OTP_AES01_OFFSET   0x0014  /* AES key 0, word 1 */
+#define LPC43_OTP_AES02_OFFSET   0x0018  /* AES key 0, word 2 */
+#define LPC43_OTP_AES03_OFFSET   0x001c  /* AES key 0, word 3 */
+
+#define LPC43_OTP_AES10_OFFSET   0x0020  /* AES key 1, word 0 */
+#define LPC43_OTP_AES11_OFFSET   0x0024  /* AES key 1, word 1 */
+#define LPC43_OTP_AES12_OFFSET   0x0028  /* AES key 1, word 2 */
+#define LPC43_OTP_AES13_OFFSET   0x002c  /* AES key 1, word 3 */
+
+#define LPC43_OTP_CCD_OFFSET     0x0030  /* Customer control data */
+#define LPC43_OTP_USBID_OFFSET   0x0034  /* USB ID */
+
+/* Register Addresses ***************************************************************/
+
+#define LPC43_OTP_MEM00          (LPC43_OTPC_BASE+LPC43_OTP_MEM00_OFFSET)
+#define LPC43_OTP_MEM01          (LPC43_OTPC_BASE+LPC43_OTP_MEM01_OFFSET)
+#define LPC43_OTP_MEM02          (LPC43_OTPC_BASE+LPC43_OTP_MEM02_OFFSET)
+#define LPC43_OTP_MEM03          (LPC43_OTPC_BASE+LPC43_OTP_MEM03_OFFSET)
+
+#define LPC43_OTP_MEM10          (LPC43_OTPC_BASE+LPC43_OTP_MEM10_OFFSET)
+#define LPC43_OTP_MEM11          (LPC43_OTPC_BASE+LPC43_OTP_MEM11_OFFSET)
+#define LPC43_OTP_MEM12          (LPC43_OTPC_BASE+LPC43_OTP_MEM12_OFFSET)
+#define LPC43_OTP_MEM13          (LPC43_OTPC_BASE+LPC43_OTP_MEM13_OFFSET)
+
+#define LPC43_OTP_MEM20          (LPC43_OTPC_BASE+LPC43_OTP_MEM20_OFFSET)
+#define LPC43_OTP_MEM21          (LPC43_OTPC_BASE+LPC43_OTP_MEM21_OFFSET)
+#define LPC43_OTP_MEM22          (LPC43_OTPC_BASE+LPC43_OTP_MEM22_OFFSET)
+
+#define LPC43_OTP_AES00          (LPC43_OTPC_BASE+LPC43_OTP_AES00_OFFSET)
+#define LPC43_OTP_AES01          (LPC43_OTPC_BASE+LPC43_OTP_AES01_OFFSET)
+#define LPC43_OTP_AES02          (LPC43_OTPC_BASE+LPC43_OTP_AES02_OFFSET)
+#define LPC43_OTP_AES03          (LPC43_OTPC_BASE+LPC43_OTP_AES03_OFFSET)
+
+#define LPC43_OTP_AES10          (LPC43_OTPC_BASE+LPC43_OTP_AES10_OFFSET)
+#define LPC43_OTP_AES11          (LPC43_OTPC_BASE+LPC43_OTP_AES11_OFFSET)
+#define LPC43_OTP_AES12          (LPC43_OTPC_BASE+LPC43_OTP_AES12_OFFSET)
+#define LPC43_OTP_AES13          (LPC43_OTPC_BASE+LPC43_OTP_AES13_OFFSET)
+
+#define LPC43_OTP_CCD            (LPC43_OTPC_BASE+LPC43_OTP_CCD_OFFSET)
+#define LPC43_OTP_USBID          (LPC43_OTPC_BASE+LPC43_OTP_USBID_OFFSET)
+
+/* Register Bit Definitions *********************************************************/
+
+/* Customer control data */
+                                           /* Bits 0-22: Reserved */
+#define OTP_CCD_USBID            (1 << 23) /* Bit 23: USB ID enable */
+                                           /* Bit 24: Reserved */
+#define OPT_CCD_BOOTSRC_SHIFT    (25)      /* Bits 25-28: Boot source selection in OTP */
+#define OPT_CCD_BOOTSRC_MASK     (15 << OPT_CCD_BOOTSRC_SHIFT)
+#  define OPT_CCD_BOOTSRC_EXT    (0 << OPT_CCD_BOOTSRC_SHIFT) /* External pins */
+#  define OPT_CCD_BOOTSRC_USART0 (1 << OPT_CCD_BOOTSRC_SHIFT) /* USART0 */
+#  define OPT_CCD_BOOTSRC_EMC8   (3 << OPT_CCD_BOOTSRC_SHIFT) /* EMC 8-bit */
+#  define OPT_CCD_BOOTSRC_EMC16  (4 << OPT_CCD_BOOTSRC_SHIFT) /* EMC 16-bit */
+#  define OPT_CCD_BOOTSRC_EMC32  (5 << OPT_CCD_BOOTSRC_SHIFT) /* EMC 32-bit */
+#  define OPT_CCD_BOOTSRC_USB0   (6 << OPT_CCD_BOOTSRC_SHIFT) /* USB0 */
+#  define OPT_CCD_BOOTSRC_USB1   (7 << OPT_CCD_BOOTSRC_SHIFT) /* USB1 */
+#  define OPT_CCD_BOOTSRC_SPI    (8 << OPT_CCD_BOOTSRC_SHIFT) /* SPI (via SSP) */
+#  define OPT_CCD_BOOTSRC_USART3 (9 << OPT_CCD_BOOTSRC_SHIFT) /* USART3 */
+                                           /* Bits 29-30: Reserved */
+#define OTP_CCD_JTAGDIS          (1 << 31) /* Bit 31: JTAG disable */
+
+/* USB ID */
+
+#define OTP_USBID_VID_SHIFT      (0)       /* Bits 0-15: USB vendor ID */
+#define OTP_USBID_VID_MASK       (0xffff << OTP_USBID_VID_SHIFT)
+#define OTP_USBID_PID_SHIFT      (0)       /* Bits 16-31: USB product ID */
+#define OTP_USBID_PID_MASK       (0xffff << OTP_USBID_PID_SHIFT)
+
+/* OTP API *************************************************************************/
+/* The AES is controlled through a set of simple API calls located in the LPC43xx
+ * ROM.  This value holds the pointer to the OTP driver table.
+ */
+
+#define LPC43_ROM_OTP_DRIVER_TABLE LPC43_ROM_DRIVER_TABLE1
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+struct lpc43_otp_s
+{
+  /* Initializes the OTP controller */
+
+  unsigned int (*otp_Init)(void);
+
+  /* Programs boot source */
+
+  unsigned int (*otp_ProgBootSrc)(unsigned int src);
+
+  /* JTAG disable. This command disables JTAG only when the device is AES capable. */
+
+  unsigned int (*otp_ProgJTAGDis)(void);
+
+  /* Programs USB_ID */
+
+  unsigned int (*otp_ProgUSBID)(unsigned int pid, unsigned int vid);
+
+  /* Reserved */
+
+  void *reserved[3];
+
+  /* Program the general purpose OTP memories. Use only if the device is not AES
+   * capable.
+   */
+
+  unsigned int (*otp_ProgGP0)(unsigned int data, unsigned int mask);
+  unsigned int (*otp_ProgGP1)(unsigned int data, unsigned int mask);
+  unsigned int (*otp_ProgGP2)(unsigned int data, unsigned int mask);
+
+  /* Program AES keys.  16 byte keys are expected. */
+
+  unsigned int (*otp_ProgKey1)(unsigned char *key);
+  unsigned int (*otp_ProgKey2)(unsigned char *key);
+
+  /* Generate new random number using the hardware Random Number Generator (RNG). */
+
+  unsigned int (*otp_GenRand)(void);
+};
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_OTP_H */
diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_pmc.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_pmc.h
new file mode 100644
index 000000000..511c515a2
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_pmc.h
@@ -0,0 +1,82 @@
+/************************************************************************************
+ * arch/arm/src/lpc43xx/chip/lpc43_pmc.h
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_PMC_H
+#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_PMC_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+/* Register Offsets *****************************************************************/
+
+#define LPC43_PD0_SLEEP0_HWENA_OFFSET 0x0000 /* Hardware sleep event enable register */
+#define LPC43_PD0_SLEEP0_MODE_OFFSET  0x001c /* Power-down mode control register */
+
+/* Register Addresses ***************************************************************/
+
+#define LPC43_PD0_SLEEP0_HWENA        (LPC43_PMC_BASE+LPC43_PD0_SLEEP0_HWENA_OFFSET)
+#define LPC43_PD0_SLEEP0_MODE         (LPC43_PMC_BASE+LPC43_PD0_SLEEP0_MODE_OFFSET)
+
+/* Register Bit Definitions *********************************************************/
+
+/* Hardware sleep event enable register */
+
+#define PD0_SLEEP0_HWENA              (1 << 0)  /* Bit 0:  Enable power down mode */
+                                                /* Bits 1-31:  Reserved */
+/* Power-down mode control register */
+
+#define PD0_DEEP_SLEEP_MODE           0x003000aa
+#define PD0_PWRDOWN_MODE              0x0030fcba
+#define PD0_DEEP_PWRDOWN_MODE         0x0030ff7f
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_PMC_H */
diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_qei.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_qei.h
new file mode 100644
index 000000000..9994c4e9e
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_qei.h
@@ -0,0 +1,211 @@
+/************************************************************************************
+ * arch/arm/src/lpc43xx/lpc43_qei.h
+ *
+ *   Copyright (C) 2010 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LPC43XX_LPC43_QEI_H
+#define __ARCH_ARM_SRC_LPC43XX_LPC43_QEI_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Register offsets *****************************************************************/
+/* Control registers */
+
+#define LPC43_QEI_CON_OFFSET     0x0000 /* Control register */
+#define LPC43_QEI_STAT_OFFSET    0x0004 /* Encoder status register */
+#define LPC43_QEI_CONF_OFFSET    0x0008 /* Configuration register */
+
+/* Position, index, and timer registers */
+
+#define LPC43_QEI_POS_OFFSET     0x000c /* Position register */
+#define LPC43_QEI_MAXPOS_OFFSET  0x0010 /* Maximum position register */
+#define LPC43_QEI_CMPOS0_OFFSET  0x0014 /* Position compare register */
+#define LPC43_QEI_CMPOS1_OFFSET  0x0018 /* Position compare register */
+#define LPC43_QEI_CMPOS2_OFFSET  0x001c /* Position compare register */
+#define LPC43_QEI_INXCNT_OFFSET  0x0020 /* Index count register */
+#define LPC43_QEI_INXCMP0_OFFSET 0x0024 /* Index compare register 0 */
+#define LPC43_QEI_LOAD_OFFSET    0x0028 /* Velocity timer reload register */
+#define LPC43_QEI_TIME_OFFSET    0x002c /* Velocity timer register */
+#define LPC43_QEI_VEL_OFFSET     0x0030 /* Velocity counter register */
+#define LPC43_QEI_CAP_OFFSET     0x0034 /* Velocity capture register */
+#define LPC43_QEI_VELCOMP_OFFSET 0x0038 /* Velocity compare register */
+#define LPC43_QEI_FLTRPHA_OFFSET 0x003c /* Input digital filter register phase A */
+#define LPC43_QEI_FLTRPHB_OFFSET 0x0040 /* Input digital filter register phase B */
+#define LPC43_QEI_FLTRINX_OFFSET 0x0044 /* Input digital filter register index */
+#define LPC43_QEI_WINDOW_OFFSET  0x0048 /* Index acceptance window register */
+#define LPC43_QEI_INXCMP1_OFFSET 0x004c /* Index compare register 1 */
+#define LPC43_QEI_INXCMP2_OFFSET 0x0050 /* Index compare register 2 */
+
+/* Interrupt registers */
+
+#define LPC43_QEI_IEC_OFFSET     0x0fd8 /* Interrupt enable clear register */
+#define LPC43_QEI_IES_OFFSET     0x0fdc /* Interrupt enable set register */
+#define LPC43_QEI_INTSTAT_OFFSET 0x0fe0 /* Interrupt status register */
+#define LPC43_QEI_IE_OFFSET      0x0fe4 /* Interrupt enable register */
+#define LPC43_QEI_CLR_OFFSET     0x0fe8 /* Interrupt status clear register */
+#define LPC43_QEI_SET_OFFSET     0x0fec /* Interrupt status set register */
+
+/* Register addresses ***************************************************************/
+/* Control registers */
+
+#define LPC43_QEI_CON            (LPC43_QEI_BASE+LPC43_QEI_CON_OFFSET)
+#define LPC43_QEI_STAT           (LPC43_QEI_BASE+LPC43_QEI_STAT_OFFSET)
+#define LPC43_QEI_CONF           (LPC43_QEI_BASE+LPC43_QEI_CONF_OFFSET)
+
+/* Position, index, and timer registers */
+
+#define LPC43_QEI_POS            (LPC43_QEI_BASE+LPC43_QEI_POS_OFFSET)
+#define LPC43_QEI_MAXPOS         (LPC43_QEI_BASE+LPC43_QEI_MAXPOS_OFFSET)
+#define LPC43_QEI_CMPOS0         (LPC43_QEI_BASE+LPC43_QEI_CMPOS0_OFFSET)
+#define LPC43_QEI_CMPOS1         (LPC43_QEI_BASE+LPC43_QEI_CMPOS1_OFFSET)
+#define LPC43_QEI_CMPOS2         (LPC43_QEI_BASE+LPC43_QEI_CMPOS2_OFFSET)
+#define LPC43_QEI_INXCNT         (LPC43_QEI_BASE+LPC43_QEI_INXCNT_OFFSET)
+#define LPC43_QEI_INXCMP0        (LPC43_QEI_BASE+LPC43_QEI_INXCMP0_OFFSET)
+#define LPC43_QEI_LOAD           (LPC43_QEI_BASE+LPC43_QEI_LOAD_OFFSET)
+#define LPC43_QEI_TIME           (LPC43_QEI_BASE+LPC43_QEI_TIME_OFFSET)
+#define LPC43_QEI_VEL            (LPC43_QEI_BASE+LPC43_QEI_VEL_OFFSET)
+#define LPC43_QEI_CAP            (LPC43_QEI_BASE+LPC43_QEI_CAP_OFFSET)
+#define LPC43_QEI_VELCOMP        (LPC43_QEI_BASE+LPC43_QEI_VELCOMP_OFFSET)
+#define LPC43_QEI_FLTRPHA        (LPC43_QEI_BASE+LPC43_QEI_FLTRPHA_OFFSET)
+#define LPC43_QEI_FLTRPHB        (LPC43_QEI_BASE+LPC43_QEI_FLTRPHB_OFFSET)
+#define LPC43_QEI_FLTRINX        (LPC43_QEI_BASE+LPC43_QEI_FLTRINX_OFFSET)
+#define LPC43_QEI_WINDOW         (LPC43_QEI_BASE+LPC43_QEI_WINDOW_OFFSET)
+#define LPC43_QEI_INXCMP1        (LPC43_QEI_BASE+LPC43_QEI_INXCMP1_OFFSET)
+#define LPC43_QEI_INXCMP2        (LPC43_QEI_BASE+LPC43_QEI_INXCMP2_OFFSET)
+
+/* Interrupt registers */
+
+#define LPC43_QEI_IEC            (LPC43_QEI_BASE+LPC43_QEI_IEC_OFFSET)
+#define LPC43_QEI_IES            (LPC43_QEI_BASE+LPC43_QEI_IES_OFFSET)
+#define LPC43_QEI_INTSTAT        (LPC43_QEI_BASE+LPC43_QEI_INTSTAT_OFFSET)
+#define LPC43_QEI_IE             (LPC43_QEI_BASE+LPC43_QEI_IE_OFFSET)
+#define LPC43_QEI_CLR            (LPC43_QEI_BASE+LPC43_QEI_CLR_OFFSET)
+#define LPC43_QEI_SET            (LPC43_QEI_BASE+LPC43_QEI_SET_OFFSET)
+
+/* Register bit definitions *********************************************************/
+/* The following registers hold 32-bit integer values and have no bit fields defined
+ * in this section:
+ *
+ *   Position register (POS)
+ *   Maximum position register (MAXPOS)
+ *   Position compare register 0 (CMPOS0)
+ *   Position compare register 1 (CMPOS1)
+ *   Position compare register 2 (CMPOS2)
+ *   Index count register (INXCNT)
+ *   Index compare register 0 (INXCMP0)
+ *   Index compare register 1 (INXCMP1)
+ *   Index compare register 2 (INXCMP2)
+ *   Velocity timer reload register (LOAD)
+ *   Velocity timer register (TIME)
+ *   Velocity counter register (VEL)
+ *   Velocity capture register (CAP)
+ *   Velocity compare register (VELCOMP)
+ *   Digital filter registers (FLTRPHA, FLTRPHB)
+ *   Digital filter index register (FLTINX)
+ *   Index acceptance window register (WINDOW)
+ */
+
+/* Control registers */
+/* Control register */
+
+#define QEI_CON_RESP             (1 << 0)  /* Bit 0:  Reset position counter */
+#define QEI_CON_RESPI            (1 << 1)  /* Bit 1:  Reset position counter on index */
+#define QEI_CON_RESV             (1 << 2)  /* Bit 2:  Reset velocity */
+#define QEI_CON_RESI             (1 << 3)  /* Bit 3:  Reset index counter */
+                                           /* Bits 4-31: reserved */
+/* Encoder status register */
+
+#define QEI_STAT_DIR             (1 << 0)  /* Bit 0:  Direction bit */
+                                           /* Bits 1-31: reserved */
+/* Configuration register */
+
+#define QEI_CONF_DIRINV          (1 << 0)  /* Bit 0:  Direction invert */
+#define QEI_CONF_SIGMODE         (1 << 1)  /* Bit 1:  Signal Mode */
+#define QEI_CONF_CAPMODE         (1 << 2)  /* Bit 2:  Capture Mode */
+#define QEI_CONF_INVINX          (1 << 3)  /* Bit 3:  Invert Index */
+#define QEI_CONF_CRESPI          (1 << 4)  /* Bit 4:  Reset position counter on index */
+                                           /* Bits 1-15: reserved */
+#define QEI_CONF_INXGATE_SHIFT   (16)      /* Bits 16-19: Index gating configuration */
+#define QEI_CONF_INXGATE_MASK    (15 << QEI_CONF_INXGATE_SHIFT)
+#  define QEI_CONF_INXGATE_A1B0  (1 << QEI_CONF_INXGATE_SHIFT) /* Pass index on Pha=1 Phb=0 */
+#  define QEI_CONF_INXGATE_A1B1  (2 << QEI_CONF_INXGATE_SHIFT) /* Pass index on Pha=1 Phb=1 */
+#  define QEI_CONF_INXGATE_A0B1  (4 << QEI_CONF_INXGATE_SHIFT) /* Pass index on Pha=0 Phb=1 */
+#  define QEI_CONF_INXGATE_A0B0  (8 << QEI_CONF_INXGATE_SHIFT) /* Pass index on Pha=0 Phb=0 */
+                                           /* Bits 4-31: reserved */
+
+/* Interrupt registers */
+/* Interrupt enable clear register (IEC), Interrupt enable set register (IES),
+ * Interrupt status register (INTSTAT), Interrupt enable register (IE), Interrupt
+ * status clear register (CLR), and Interrupt status set register (SET) common
+ * bit definitions.
+ */
+
+#define QEI_INT_INX              (1 << 0)  /* Bit 0:  Index pulse detected */
+#define QEI_INT_TIM              (1 << 1)  /* Bit 1:  Velocity timer overflow occurred */
+#define QEI_INT_VELC             (1 << 2)  /* Bit 2:  Captured velocity less than compare velocity */
+#define QEI_INT_DIR              (1 << 3)  /* Bit 3:  Change of direction detected */
+#define QEI_INT_ERR              (1 << 4)  /* Bit 4:  Encoder phase error detected */
+#define QEI_INT_ENCLK            (1 << 5)  /* Bit 5:  Eencoder clock pulse detected */
+#define QEI_INT_POS0             (1 << 6)  /* Bit 6:  Position 0 compare equal to current position */
+#define QEI_INT_POS1             (1 << 7)  /* Bit 7:  Position 1 compare equal to current position */
+#define QEI_INT_POS2             (1 << 8)  /* Bit 8:  Position 2 compare equal to current position */
+#define QEI_INT_REV0             (1 << 9)  /* Bit 9:  Index 0 compare equal to current index count */
+#define QEI_INT_POS0REV          (1 << 10) /* Bit 10: Position 0 and revolution count interrupt */
+#define QEI_INT_POS1REV          (1 << 11) /* Bit 11: Position 1 and revolution count interrupt */
+#define QEI_INT_POS2REV          (1 << 12) /* Bit 12: Position 2 and revolution count interrupt */
+#define QEI_INT_REV1             (1 << 13) /* Bit 13: Index 1 compare equal to current index count */
+#define QEI_INT_REV2             (1 << 14) /* Bit 14: Index 2 compare equal to current index count */
+#define QEI_INT_MAXPOS           (1 << 15) /* Bit 15: Current position count goes through MAXPOS */
+                                           /* Bits 16-31: reserved */
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_LPC43XX_LPC43_QEI_H */
diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_rgu.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_rgu.h
new file mode 100644
index 000000000..acf2fdc5d
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_rgu.h
@@ -0,0 +1,669 @@
+/****************************************************************************************************
+ * arch/arm/src/lpc43xx/chip/lpc43_rgu.h
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_RGU_H
+#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_RGU_H
+
+/****************************************************************************************************
+ * Included Files
+ ****************************************************************************************************/
+
+#include <nuttx/config.h>
+
+/****************************************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************************************/
+/* Register Offsets *********************************************************************************/
+
+#define LPC43_RGU_CTRL0_OFFSET           0x100  /* Reset control register 0 */
+#define LPC43_RGU_CTRL1_OFFSET           0x104  /* Reset control register 1 */
+#define LPC43_RGU_STATUS0_OFFSET         0x110  /* Reset status register 0 */
+#define LPC43_RGU_STATUS1_OFFSET         0x114  /* Reset status register 1 */
+#define LPC43_RGU_STATUS2_OFFSET         0x118  /* Reset status register 2 */
+#define LPC43_RGU_STATUS3_OFFSET         0x11c  /* Reset status register 3 */
+#define LPC43_RGU_ACTIVE0_OFFSET         0x150  /* Reset active status register */
+#define LPC43_RGU_ACTIVE1_OFFSET         0x154  /* Reset active status register */
+
+/* External Status Register Indices */
+
+#define RGU_CORE_RST                     0
+#define RGU_PERIPH_RST                   1
+#define RGU_MASTER_RST                   2
+#define RGU_WWDT_RST                     4
+#define RGU_CREG_RST                     5
+#define RGU_BUS_RST                      8
+#define RGU_SCU_RST                      9
+#define RGU_M4_RST                       13
+#define RGU_LCD_RST                      16
+#define RGU_USB0_RST                     17
+#define RGU_USB1_RST                     18
+#define RGU_DMA_RST                      19
+#define RGU_SDIO_RST                     20
+#define RGU_EMC_RST                      21
+#define RGU_ETHERNET_RST                 22
+#define RGU_FLASHA_RST                   25
+#define RGU_EEPROM_RST                   27
+#define RGU_GPIO_RST                     28
+#define RGU_FLASHB_RST                   29
+#define RGU_TIMER0_RST                   32
+#define RGU_TIMER1_RST                   33
+#define RGU_TIMER2_RST                   34
+#define RGU_TIMER3_RST                   35
+#define RGU_RITIMER_RST                  36
+#define RGU_SCT_RST                      37
+#define RGU_MCPWM_RST                    38
+#define RGU_QEI_RST                      39
+#define RGU_ADC0_RST                     40
+#define RGU_ADC1_RST                     41
+#define RGU_DAC_RST                      42
+#define RGU_USART0_RST                   44
+#define RGU_UART1_RST                    45
+#define RGU_USART2_RST                   46
+#define RGU_USART3_RST                   47
+#define RGU_I2C0_RST                     48
+#define RGU_I2C1_RST                     49
+#define RGU_SSP0_RST                     50
+#define RGU_SSP1_RST                     51
+#define RGU_I2S_RST                      52
+#define RGU_SPIFI_RST                    53
+#define RGU_CAN1_RST                     54
+#define RGU_CAN0_RST                     55
+#define RGU_M0APP_RST                    56
+#define RGU_SGPIO_RST                    57
+#define RGU_SPI_RST                      58
+
+/* External Status Registers */
+
+#define LPC43_RGU_EXTSTAT_OFFSET(n)      (0x0400 + ((n) << 2))  /* Reset external status register n=0..63 */
+#define LPC43_RGU_EXTSTAT0_OFFSET        0x400  /* Reset external status register 0 for CORE_RST */
+#define LPC43_RGU_EXTSTAT1_OFFSET        0x404  /* Reset external status register 1 for PERIPH_RST */
+#define LPC43_RGU_EXTSTAT2_OFFSET        0x408  /* Reset external status register 2 for MASTER_RST */
+#define LPC43_RGU_EXTSTAT4_OFFSET        0x410  /* Reset external status register 4 for WWDT_RST */
+#define LPC43_RGU_EXTSTAT5_OFFSET        0x414  /* Reset external status register 5 for CREG_RST */
+#define LPC43_RGU_EXTSTAT8_OFFSET        0x420  /* Reset external status register 8 for BUS_RST */
+#define LPC43_RGU_EXTSTAT9_OFFSET        0x424  /* Reset external status register 9 for SCU_RST */
+#define LPC43_RGU_EXTSTAT13_OFFSET       0x434  /* Reset external status register 13 for M4_RST */
+#define LPC43_RGU_EXTSTAT16_OFFSET       0x440  /* Reset external status register 16 for LCD_RST */
+#define LPC43_RGU_EXTSTAT17_OFFSET       0x444  /* Reset external status register 17 for USB0_RST */
+#define LPC43_RGU_EXTSTAT18_OFFSET       0x448  /* Reset external status register 18 for USB1_RST */
+#define LPC43_RGU_EXTSTAT19_OFFSET       0x44c  /* Reset external status register 19 for DMA_RST */
+#define LPC43_RGU_EXTSTAT20_OFFSET       0x450  /* Reset external status register 20 for SDIO_RST */
+#define LPC43_RGU_EXTSTAT21_OFFSET       0x454  /* Reset external status register 21 for EMC_RST */
+#define LPC43_RGU_EXTSTAT22_OFFSET       0x458  /* Reset external status register 22 for ETHERNET_RST */
+#define LPC43_RGU_EXTSTAT25_OFFSET       0x464  /* Reset external status register 25 for FLASHA_RST */
+#define LPC43_RGU_EXTSTAT27_OFFSET       0x46c  /* Reset external status register 27 for EEPROM_RST */
+#define LPC43_RGU_EXTSTAT28_OFFSET       0x470  /* Reset external status register 28 for GPIO_RST */
+#define LPC43_RGU_EXTSTAT29_OFFSET       0x474  /* Reset external status register 29 for FLASHB_RST */
+#define LPC43_RGU_EXTSTAT32_OFFSET       0x480  /* Reset external status register 32 for TIMER0_RST */
+#define LPC43_RGU_EXTSTAT33_OFFSET       0x484  /* Reset external status register 33 for TIMER1_RST */
+#define LPC43_RGU_EXTSTAT34_OFFSET       0x488  /* Reset external status register 34 for TIMER2_RST */
+#define LPC43_RGU_EXTSTAT35_OFFSET       0x48c  /* Reset external status register 35 for TIMER3_RST */
+#define LPC43_RGU_EXTSTAT36_OFFSET       0x490  /* Reset external status register 36 for RITIMER_RST */
+#define LPC43_RGU_EXTSTAT37_OFFSET       0x494  /* Reset external status register 37 for SCT_RST */
+#define LPC43_RGU_EXTSTAT38_OFFSET       0x498  /* Reset external status register 38 for MCPWM_RST */
+#define LPC43_RGU_EXTSTAT39_OFFSET       0x49c  /* Reset external status register 39 for QEI_RST */
+#define LPC43_RGU_EXTSTAT40_OFFSET       0x4a0  /* Reset external status register 40 for ADC0_RST */
+#define LPC43_RGU_EXTSTAT41_OFFSET       0x4a4  /* Reset external status register 41 for ADC1_RST */
+#define LPC43_RGU_EXTSTAT42_OFFSET       0x4a8  /* Reset external status register 42 for DAC_RST */
+#define LPC43_RGU_EXTSTAT44_OFFSET       0x4b0  /* Reset external status register 44 for USART0_RST */
+#define LPC43_RGU_EXTSTAT45_OFFSET       0x4b4  /* Reset external status register 45 for UART1_RST */
+#define LPC43_RGU_EXTSTAT46_OFFSET       0x4b8  /* Reset external status register 46 for USART2_RST */
+#define LPC43_RGU_EXTSTAT47_OFFSET       0x4bc  /* Reset external status register 47 for USART3_RST */
+#define LPC43_RGU_EXTSTAT48_OFFSET       0x4c0  /* Reset external status register 48 for I2C0_RST */
+#define LPC43_RGU_EXTSTAT49_OFFSET       0x4c4  /* Reset external status register 49 for I2C1_RST */
+#define LPC43_RGU_EXTSTAT50_OFFSET       0x4c8  /* Reset external status register 50 for SSP0_RST */
+#define LPC43_RGU_EXTSTAT51_OFFSET       0x4cc  /* Reset external status register 51 for SSP1_RST */
+#define LPC43_RGU_EXTSTAT52_OFFSET       0x4d0  /* Reset external status register 52 for I2S_RST */
+#define LPC43_RGU_EXTSTAT53_OFFSET       0x4d4  /* Reset external status register 53 for SPIFI_RST */
+#define LPC43_RGU_EXTSTAT54_OFFSET       0x4d8  /* Reset external status register 54 for CAN1_RST */
+#define LPC43_RGU_EXTSTAT55_OFFSET       0x4dc  /* Reset external status register 55 for CAN0_RST */
+#define LPC43_RGU_EXTSTAT56_OFFSET       0x4e0  /* Reset external status register 56 for M0APP_RST */
+#define LPC43_RGU_EXTSTAT57_OFFSET       0x4e4  /* Reset external status register 57 for SGPIO_RST */
+#define LPC43_RGU_EXTSTAT58_OFFSET       0x4e8  /* Reset external status register 58 for SPI_RST */
+
+/* Register Addresses *******************************************************************************/
+
+#define LPC43_RGU_CTRL0                  (LPC43_RGU_BASE+LPC43_RGU_CTRL0_OFFSET)
+#define LPC43_RGU_CTRL1                  (LPC43_RGU_BASE+LPC43_RGU_CTRL1_OFFSET)
+#define LPC43_RGU_STATUS0                (LPC43_RGU_BASE+LPC43_RGU_STATUS0_OFFSET)
+#define LPC43_RGU_STATUS1                (LPC43_RGU_BASE+LPC43_RGU_STATUS1_OFFSET)
+#define LPC43_RGU_STATUS2                (LPC43_RGU_BASE+LPC43_RGU_STATUS2_OFFSET)
+#define LPC43_RGU_STATUS3                (LPC43_RGU_BASE+LPC43_RGU_STATUS3_OFFSET)
+#define LPC43_RGU_ACTIVE0                (LPC43_RGU_BASE+LPC43_RGU_ACTIVE0_OFFSET)
+#define LPC43_RGU_ACTIVE1                (LPC43_RGU_BASE+LPC43_RGU_ACTIVE1_OFFSET)
+
+/* External Status Registers */
+
+#define LPC43_RGU_EXTSTAT(n)             (LPC43_RGU_BASE+LPC43_RGU_EXTSTAT_OFFSET(n))
+#define LPC43_RGU_EXTSTAT0               (LPC43_RGU_BASE+LPC43_RGU_EXTSTAT0_OFFSET)
+#define LPC43_RGU_EXTSTAT1               (LPC43_RGU_BASE+LPC43_RGU_EXTSTAT1_OFFSET)
+#define LPC43_RGU_EXTSTAT2               (LPC43_RGU_BASE+LPC43_RGU_EXTSTAT2_OFFSET)
+#define LPC43_RGU_EXTSTAT4               (LPC43_RGU_BASE+LPC43_RGU_EXTSTAT4_OFFSET)
+#define LPC43_RGU_EXTSTAT5               (LPC43_RGU_BASE+LPC43_RGU_EXTSTAT5_OFFSET)
+#define LPC43_RGU_EXTSTAT8               (LPC43_RGU_BASE+LPC43_RGU_EXTSTAT8_OFFSET)
+#define LPC43_RGU_EXTSTAT9               (LPC43_RGU_BASE+LPC43_RGU_EXTSTAT9_OFFSET)
+#define LPC43_RGU_EXTSTAT13              (LPC43_RGU_BASE+LPC43_RGU_EXTSTAT13_OFFSET)
+#define LPC43_RGU_EXTSTAT16              (LPC43_RGU_BASE+LPC43_RGU_EXTSTAT16_OFFSET)
+#define LPC43_RGU_EXTSTAT17              (LPC43_RGU_BASE+LPC43_RGU_EXTSTAT17_OFFSET)
+#define LPC43_RGU_EXTSTAT18              (LPC43_RGU_BASE+LPC43_RGU_EXTSTAT18_OFFSET)
+#define LPC43_RGU_EXTSTAT19              (LPC43_RGU_BASE+LPC43_RGU_EXTSTAT19_OFFSET)
+#define LPC43_RGU_EXTSTAT20              (LPC43_RGU_BASE+LPC43_RGU_EXTSTAT20_OFFSET)
+#define LPC43_RGU_EXTSTAT21              (LPC43_RGU_BASE+LPC43_RGU_EXTSTAT21_OFFSET)
+#define LPC43_RGU_EXTSTAT22              (LPC43_RGU_BASE+LPC43_RGU_EXTSTAT22_OFFSET)
+#define LPC43_RGU_EXTSTAT25              (LPC43_RGU_BASE+LPC43_RGU_EXTSTAT25_OFFSET)
+#define LPC43_RGU_EXTSTAT27              (LPC43_RGU_BASE+LPC43_RGU_EXTSTAT27_OFFSET)
+#define LPC43_RGU_EXTSTAT28              (LPC43_RGU_BASE+LPC43_RGU_EXTSTAT28_OFFSET)
+#define LPC43_RGU_EXTSTAT29              (LPC43_RGU_BASE+LPC43_RGU_EXTSTAT29_OFFSET)
+#define LPC43_RGU_EXTSTAT32              (LPC43_RGU_BASE+LPC43_RGU_EXTSTAT32_OFFSET)
+#define LPC43_RGU_EXTSTAT33              (LPC43_RGU_BASE+LPC43_RGU_EXTSTAT33_OFFSET)
+#define LPC43_RGU_EXTSTAT34              (LPC43_RGU_BASE+LPC43_RGU_EXTSTAT34_OFFSET)
+#define LPC43_RGU_EXTSTAT35              (LPC43_RGU_BASE+LPC43_RGU_EXTSTAT35_OFFSET)
+#define LPC43_RGU_EXTSTAT36              (LPC43_RGU_BASE+LPC43_RGU_EXTSTAT36_OFFSET)
+#define LPC43_RGU_EXTSTAT37              (LPC43_RGU_BASE+LPC43_RGU_EXTSTAT37_OFFSET)
+#define LPC43_RGU_EXTSTAT38              (LPC43_RGU_BASE+LPC43_RGU_EXTSTAT38_OFFSET)
+#define LPC43_RGU_EXTSTAT39              (LPC43_RGU_BASE+LPC43_RGU_EXTSTAT39_OFFSET)
+#define LPC43_RGU_EXTSTAT40              (LPC43_RGU_BASE+LPC43_RGU_EXTSTAT40_OFFSET)
+#define LPC43_RGU_EXTSTAT41              (LPC43_RGU_BASE+LPC43_RGU_EXTSTAT41_OFFSET)
+#define LPC43_RGU_EXTSTAT42              (LPC43_RGU_BASE+LPC43_RGU_EXTSTAT42_OFFSET)
+#define LPC43_RGU_EXTSTAT44              (LPC43_RGU_BASE+LPC43_RGU_EXTSTAT44_OFFSET)
+#define LPC43_RGU_EXTSTAT45              (LPC43_RGU_BASE+LPC43_RGU_EXTSTAT45_OFFSET)
+#define LPC43_RGU_EXTSTAT46              (LPC43_RGU_BASE+LPC43_RGU_EXTSTAT46_OFFSET)
+#define LPC43_RGU_EXTSTAT47              (LPC43_RGU_BASE+LPC43_RGU_EXTSTAT47_OFFSET)
+#define LPC43_RGU_EXTSTAT48              (LPC43_RGU_BASE+LPC43_RGU_EXTSTAT48_OFFSET)
+#define LPC43_RGU_EXTSTAT49              (LPC43_RGU_BASE+LPC43_RGU_EXTSTAT49_OFFSET)
+#define LPC43_RGU_EXTSTAT50              (LPC43_RGU_BASE+LPC43_RGU_EXTSTAT50_OFFSET)
+#define LPC43_RGU_EXTSTAT51              (LPC43_RGU_BASE+LPC43_RGU_EXTSTAT51_OFFSET)
+#define LPC43_RGU_EXTSTAT52              (LPC43_RGU_BASE+LPC43_RGU_EXTSTAT52_OFFSET)
+#define LPC43_RGU_EXTSTAT53              (LPC43_RGU_BASE+LPC43_RGU_EXTSTAT53_OFFSET)
+#define LPC43_RGU_EXTSTAT54              (LPC43_RGU_BASE+LPC43_RGU_EXTSTAT54_OFFSET)
+#define LPC43_RGU_EXTSTAT55              (LPC43_RGU_BASE+LPC43_RGU_EXTSTAT55_OFFSET)
+#define LPC43_RGU_EXTSTAT56              (LPC43_RGU_BASE+LPC43_RGU_EXTSTAT56_OFFSET)
+#define LPC43_RGU_EXTSTAT57              (LPC43_RGU_BASE+LPC43_RGU_EXTSTAT57_OFFSET)
+#define LPC43_RGU_EXTSTAT58              (LPC43_RGU_BASE+LPC43_RGU_EXTSTAT58_OFFSET)
+
+/* Alternative naming */
+
+#define LPC43_RGU_EXTSTAT_CORE_RST       LPC43_RGU_EXTSTAT0
+#define LPC43_RGU_EXTSTAT_PERIPH_RST     LPC43_RGU_EXTSTAT1
+#define LPC43_RGU_EXTSTAT_MASTER_RST     LPC43_RGU_EXTSTAT2
+#define LPC43_RGU_EXTSTAT_WWDT_RST       LPC43_RGU_EXTSTAT4
+#define LPC43_RGU_EXTSTAT_CREG_RST       LPC43_RGU_EXTSTAT5
+#define LPC43_RGU_EXTSTAT_BUS_RST        LPC43_RGU_EXTSTAT8
+#define LPC43_RGU_EXTSTAT_SCU_RST        LPC43_RGU_EXTSTAT9
+#define LPC43_RGU_EXTSTAT_M4_RST         LPC43_RGU_EXTSTAT13
+#define LPC43_RGU_EXTSTAT_LCD_RST        LPC43_RGU_EXTSTAT16
+#define LPC43_RGU_EXTSTAT_USB0_RST       LPC43_RGU_EXTSTAT17
+#define LPC43_RGU_EXTSTAT_USB1_RST       LPC43_RGU_EXTSTAT18
+#define LPC43_RGU_EXTSTAT_DMA_RST        LPC43_RGU_EXTSTAT19
+#define LPC43_RGU_EXTSTAT_SDIO_RST       LPC43_RGU_EXTSTAT20
+#define LPC43_RGU_EXTSTAT_EMC_RST        LPC43_RGU_EXTSTAT21
+#define LPC43_RGU_EXTSTAT_ETHERNET_RST   LPC43_RGU_EXTSTAT22
+#define LPC43_RGU_EXTSTAT_FLASHA_RST     LPC43_RGU_EXTSTAT25
+#define LPC43_RGU_EXTSTAT_EEPROM_RST     LPC43_RGU_EXTSTAT27
+#define LPC43_RGU_EXTSTAT_GPIO_RST       LPC43_RGU_EXTSTAT28
+#define LPC43_RGU_EXTSTAT_FLASHB_RST     LPC43_RGU_EXTSTAT29
+#define LPC43_RGU_EXTSTAT_TIMER0_RST     LPC43_RGU_EXTSTAT32
+#define LPC43_RGU_EXTSTAT_TIMER1_RST     LPC43_RGU_EXTSTAT33
+#define LPC43_RGU_EXTSTAT_TIMER2_RST     LPC43_RGU_EXTSTAT34
+#define LPC43_RGU_EXTSTAT_TIMER3_RST     LPC43_RGU_EXTSTAT35
+#define LPC43_RGU_EXTSTAT_RITIMER_RST    LPC43_RGU_EXTSTAT36
+#define LPC43_RGU_EXTSTAT_SCT_RST        LPC43_RGU_EXTSTAT37
+#define LPC43_RGU_EXTSTAT_MCPWM_RST      LPC43_RGU_EXTSTAT38
+#define LPC43_RGU_EXTSTAT_QEI_RST        LPC43_RGU_EXTSTAT39
+#define LPC43_RGU_EXTSTAT_ADC0_RST       LPC43_RGU_EXTSTAT40
+#define LPC43_RGU_EXTSTAT_ADC1_RST       LPC43_RGU_EXTSTAT41
+#define LPC43_RGU_EXTSTAT_DAC_RST        LPC43_RGU_EXTSTAT42
+#define LPC43_RGU_EXTSTAT_USART0_RST     LPC43_RGU_EXTSTAT44
+#define LPC43_RGU_EXTSTAT_UART1_RST      LPC43_RGU_EXTSTAT45
+#define LPC43_RGU_EXTSTAT_USART2_RST     LPC43_RGU_EXTSTAT46
+#define LPC43_RGU_EXTSTAT_USART3_RST     LPC43_RGU_EXTSTAT47
+#define LPC43_RGU_EXTSTAT_I2C0_RST       LPC43_RGU_EXTSTAT48
+#define LPC43_RGU_EXTSTAT_I2C1_RST       LPC43_RGU_EXTSTAT49
+#define LPC43_RGU_EXTSTAT_SSP0_RST       LPC43_RGU_EXTSTAT50
+#define LPC43_RGU_EXTSTAT_SSP1_RST       LPC43_RGU_EXTSTAT51
+#define LPC43_RGU_EXTSTAT_I2S_RST        LPC43_RGU_EXTSTAT52
+#define LPC43_RGU_EXTSTAT_SPIFI_RST      LPC43_RGU_EXTSTAT53
+#define LPC43_RGU_EXTSTAT_CAN1_RST       LPC43_RGU_EXTSTAT54
+#define LPC43_RGU_EXTSTAT_CAN0_RST       LPC43_RGU_EXTSTAT55
+#define LPC43_RGU_EXTSTAT_M0APP_RST      LPC43_RGU_EXTSTAT56
+#define LPC43_RGU_EXTSTAT_SGPIO_RST      LPC43_RGU_EXTSTAT57
+#define LPC43_RGU_EXTSTAT_SPI_RST        LPC43_RGU_EXTSTAT58
+
+/* Register Bit Definitions *************************************************************************/
+
+/* Reset control register 0 */
+
+#define RGU_CTRL0_CORE_RST               (1 << 0)
+#define RGU_CTRL0_PERIPH_RST             (1 << 1)
+#define RGU_CTRL0_MASTER_RST             (1 << 2)
+                                                   /* Bit 3:  Reserved */
+#define RGU_CTRL0_WWDT_RST               (1 << 4)  /* Writing a one to this bit has no effect */
+#define RGU_CTRL0_CREG_RST               (1 << 5)  /* Writing a one to this bit has no effect */
+                                                   /* Bits 6-7:  Reserved */
+#define RGU_CTRL0_BUS_RST                (1 << 8)
+#define RGU_CTRL0_SCU_RST                (1 << 9)
+                                                   /* Bits 10-12:  Reserved */
+#define RGU_CTRL0_M4_RST                 (1 << 13)
+                                                   /* Bits 14-15:  Reserved */
+#define RGU_CTRL0_LCD_RST                (1 << 16)
+#define RGU_CTRL0_USB0_RST               (1 << 17)
+#define RGU_CTRL0_USB1_RST               (1 << 18)
+#define RGU_CTRL0_DMA_RST                (1 << 19)
+#define RGU_CTRL0_SDIO_RST               (1 << 20)
+#define RGU_CTRL0_EMC_RST                (1 << 21)
+#define RGU_CTRL0_ETHERNET_RST           (1 << 22)
+                                                   /* Bits 23-24:  Reserved */
+#define RGU_CTRL0_FLASHA_RST             (1 << 25)
+                                                   /* Bit 26:  Reserved */
+#define RGU_CTRL0_EEPROM_RST             (1 << 27)
+#define RGU_CTRL0_GPIO_RST               (1 << 28)
+#define RGU_CTRL0_FLASHB_RST             (1 << 29)
+                                                   /* Bits 30-31:  Reserved */
+/* Reset control register 1 */
+
+#define RGU_CTRL1_TIMER0_RST             (1 << 0)
+#define RGU_CTRL1_TIMER1_RST             (1 << 1)
+#define RGU_CTRL1_TIMER2_RST             (1 << 2)
+#define RGU_CTRL1_TIMER3_RST             (1 << 3)
+#define RGU_CTRL1_RITIMER_RST            (1 << 4)
+#define RGU_CTRL1_SCT_RST                (1 << 5)
+#define RGU_CTRL1_MCPWM_RST              (1 << 6)
+#define RGU_CTRL1_QEI_RST                (1 << 7)
+#define RGU_CTRL1_ADC0_RST               (1 << 8)
+#define RGU_CTRL1_ADC1_RST               (1 << 9)
+#define RGU_CTRL1_DAC_RST                (1 << 10)
+                                                    /* Bit 11:  Reserved */
+#define RGU_CTRL1_USART0_RST             (1 << 12)
+#define RGU_CTRL1_UART1_RST              (1 << 13)
+#define RGU_CTRL1_USART2_RST             (1 << 14)
+#define RGU_CTRL1_USART3_RST             (1 << 15)
+#define RGU_CTRL1_I2C0_RST               (1 << 16)
+#define RGU_CTRL1_I2C1_RST               (1 << 17)
+#define RGU_CTRL1_SSP0_RST               (1 << 18)
+#define RGU_CTRL1_SSP1_RST               (1 << 19)
+#define RGU_CTRL1_I2S_RST                (1 << 20)
+#define RGU_CTRL1_SPIFI_RST              (1 << 21)
+#define RGU_CTRL1_CAN1_RST               (1 << 22)
+#define RGU_CTRL1_CAN0_RST               (1 << 23)
+#define RGU_CTRL1_M0APP_RST              (1 << 24)
+#define RGU_CTRL1_SGPIO_RST              (1 << 25)
+#define RGU_CTRL1_SPI_RST                (1 << 26)
+                                                    /* Bits 27-31:  Reserved */
+/* Reset status register 0 */
+
+#define RGU_RST_NONE                     0          /* No reset activated */
+#define RGU_RST_HW                       1          /* Reset output activated by input to the reset generator */
+#define RGU_RST_SW                       3          /* Reset output activated by software write to RESET_CTRL register */
+
+#define RGU_STATUS0_CORE_RST_SHIFT       (0)        /* Bits 0-1: Status of the CORE_RST reset generator output */
+#define RGU_STATUS0_CORE_RST_MASK        (3 << RGU_STATUS0_CORE_RST_SHIFT)
+#  define RGU_STATUS0_CORE_RST_NONE      (0 << RGU_STATUS0_CORE_RST_SHIFT) /* No reset activated */
+#  define RGU_STATUS0_CORE_RST_HW        (1 << RGU_STATUS0_CORE_RST_SHIFT) /* Activated by reset generator */
+#  define RGU_STATUS0_CORE_RST_SW        (3 << RGU_STATUS0_CORE_RST_SHIFT) /* Activated by software */
+#define RGU_STATUS0_PERIPH_RST_SHIFT     (2)        /* Bits 2-3: Status of the PERIPH_RST reset generator output */
+#define RGU_STATUS0_PERIPH_RST_MASK      (3 << RGU_STATUS0_PERIPH_RST_SHIFT)
+#  define RGU_STATUS0_PERIPH_RST_NONE    (0 << RGU_STATUS0_PERIPH_RST_SHIFT) /* No reset activated */
+#  define RGU_STATUS0_PERIPH_RST_HW      (1 << RGU_STATUS0_PERIPH_RST_SHIFT) /* Activated by reset generator */
+#  define RGU_STATUS0_PERIPH_RST_SW      (3 << RGU_STATUS0_PERIPH_RST_SHIFT) /* Activated by software */
+#define RGU_STATUS0_MASTER_RST_SHIFT     (4)        /* Bits 4-5: Status of the MASTER_RST reset generator output */
+#define RGU_STATUS0_MASTER_RST_MASK      (3 << RGU_STATUS0_MASTER_RST_SHIFT)
+#  define RGU_STATUS0_MASTER_RST_NONE    (0 << RGU_STATUS0_MASTER_RST_SHIFT) /* No reset activated */
+#  define RGU_STATUS0_MASTER_RST_HW      (1 << RGU_STATUS0_MASTER_RST_SHIFT) /* Activated by reset generator */
+#  define RGU_STATUS0_MASTER_RST_SW      (3 << RGU_STATUS0_MASTER_RST_SHIFT) /* Activated by software */
+                                                    /* Bits 6-7:  Reserved */
+#define RGU_STATUS0_WWDT_RST_SHIFT       (8)        /* Bits 8-9: Status of the WWDT_RST reset generator output */
+#define RGU_STATUS0_WWDT_RST_MASK        (3 << RGU_STATUS0_WWDT_RST_SHIFT)
+#  define RGU_STATUS0_WWDT_RST_NONE      (0 << RGU_STATUS0_WWDT_RST_SHIFT) /* No reset activated */
+#  define RGU_STATUS0_WWDT_RST_HW        (1 << RGU_STATUS0_WWDT_RST_SHIFT) /* Activated by reset generator */
+#define RGU_STATUS0_CREG_RST_SHIFT       (10)       /* Bits 10-11: Status of the CREG_RST reset generator output */
+#define RGU_STATUS0_CREG_RST_MASK        (3 << RGU_STATUS0_CREG_RST_SHIFT)
+#  define RGU_STATUS0_CREG_RST_NONE      (0 << RGU_STATUS0_CREG_RST_SHIFT) /* No reset activated */
+#  define RGU_STATUS0_CREG_RST_HW        (1 << RGU_STATUS0_CREG_RST_SHIFT) /* Activated by reset generator */
+                                                    /* Bits 12-15:  Reserved */
+#define RGU_STATUS0_BUS_RST_SHIFT        (16)       /* Bits 16-17: Status of the BUS_RST reset generator output */
+#define RGU_STATUS0_BUS_RST_MASK         (3 << RGU_STATUS0_BUS_RST_SHIFT)
+#  define RGU_STATUS0_BUS_RST_NONE       (0 << RGU_STATUS0_BUS_RST_SHIFT) /* No reset activated */
+#  define RGU_STATUS0_BUS_RST_HW         (1 << RGU_STATUS0_BUS_RST_SHIFT) /* Activated by reset generator */
+#  define RGU_STATUS0_BUS_RST_SW         (3 << RGU_STATUS0_BUS_RST_SHIFT) /* Activated by software */
+#define RGU_STATUS0_SCU_RST_SHIFT        (18)       /* Bits 18-19: Status of the SCU_RST reset generator output */
+#define RGU_STATUS0_SCU_RST_MASK         (3 << RGU_STATUS0_SCU_RST_SHIFT)
+#  define RGU_STATUS0_SCU_RST_NONE       (0 << RGU_STATUS0_SCU_RST_SHIFT) /* No reset activated */
+#  define RGU_STATUS0_SCU_RST_HW         (1 << RGU_STATUS0_SCU_RST_SHIFT) /* Activated by reset generator */
+#  define RGU_STATUS0_SCU_RST_SW         (3 << RGU_STATUS0_SCU_RST_SHIFT) /* Activated by software */
+                                                    /* Bits 20-25:  Reserved */
+#define RGU_STATUS0_M4_RST_SHIFT         (26)       /* Bits 26-27: Status of the M4_RST reset generator output */
+#define RGU_STATUS0_M4_RST_MASK          (3 << RGU_STATUS0_M4_RST_SHIFT)
+#  define RGU_STATUS0_M4_RST_NONE        (0 << RGU_STATUS0_M4_RST_SHIFT) /* No reset activated */
+#  define RGU_STATUS0_M4_RST_HW          (1 << RGU_STATUS0_M4_RST_SHIFT) /* Activated by reset generator */
+#  define RGU_STATUS0_M4_RST_SW          (3 << RGU_STATUS0_M4_RST_SHIFT) /* Activated by software */
+                                                    /* Bits 29-31:  Reserved */
+/* Reset status register 1 */
+
+#define RGU_STATUS1_LCD_RST_SHIFT        (0)        /* Bits 0-1: Status of the LCD_RST reset generator output */
+#define RGU_STATUS1_LCD_RST_MASK         (3 << RGU_STATUS1_LCD_RST_SHIFT)
+#  define RGU_STATUS1_LCD_RST_NONE       (0 << RGU_STATUS1_LCD_RST_SHIFT) /* No reset activated */
+#  define RGU_STATUS1_LCD_RST_HW         (1 << RGU_STATUS1_LCD_RST_SHIFT) /* Activated by reset generator */
+#  define RGU_STATUS1_LCD_RST_SW         (3 << RGU_STATUS1_LCD_RST_SHIFT) /* Activated by software */
+#define RGU_STATUS1_USB0_RST_SHIFT       (2)        /* Bits 2-3: Status of the USB0_RST reset generator output */
+#define RGU_STATUS1_USB0_RST_MASK        (3 << RGU_STATUS1_USB0_RST_SHIFT)
+#  define RGU_STATUS1_USB0_RST_NONE      (0 << RGU_STATUS1_USB0_RST_SHIFT) /* No reset activated */
+#  define RGU_STATUS1_USB0_RST_HW        (1 << RGU_STATUS1_USB0_RST_SHIFT) /* Activated by reset generator */
+#  define RGU_STATUS1_USB0_RST_SW        (3 << RGU_STATUS1_USB0_RST_SHIFT) /* Activated by software */
+#define RGU_STATUS1_USB1_RST_SHIFT       (4)        /* Bits 4-5: Status of the USB1_RST reset generator output */
+#define RGU_STATUS1_USB1_RST_MASK        (3 << RGU_STATUS1_USB1_RST_SHIFT)
+#  define RGU_STATUS1_USB1_RST_NONE      (0 << RGU_STATUS1_USB1_RST_SHIFT) /* No reset activated */
+#  define RGU_STATUS1_USB1_RST_HW        (1 << RGU_STATUS1_USB1_RST_SHIFT) /* Activated by reset generator */
+#  define RGU_STATUS1_USB1_RST_SW        (3 << RGU_STATUS1_USB1_RST_SHIFT) /* Activated by software */
+#define RGU_STATUS1_DMA_RST_SHIFT        (6)        /* Bits 6-7: Status of the DMA_RST reset generator output */
+#define RGU_STATUS1_DMA_RST_MASK         (3 << RGU_STATUS1_DMA_RST_SHIFT)
+#  define RGU_STATUS1_DMA_RST_NONE       (0 << RGU_STATUS1_DMA_RST_SHIFT) /* No reset activated */
+#  define RGU_STATUS1_DMA_RST_HW         (1 << RGU_STATUS1_DMA_RST_SHIFT) /* Activated by reset generator */
+#  define RGU_STATUS1_DMA_RST_SW         (3 << RGU_STATUS1_DMA_RST_SHIFT) /* Activated by software */
+#define RGU_STATUS1_SDIO_RST_SHIFT       (8)        /* Bits 8-9: Status of the SDIO_RST reset generator output */
+#define RGU_STATUS1_SDIO_RST_MASK        (3 << RGU_STATUS1_SDIO_RST_SHIFT)
+#  define RGU_STATUS1_SDIO_RST_NONE      (0 << RGU_STATUS1_SDIO_RST_SHIFT) /* No reset activated */
+#  define RGU_STATUS1_SDIO_RST_HW        (1 << RGU_STATUS1_SDIO_RST_SHIFT) /* Activated by reset generator */
+#  define RGU_STATUS1_SDIO_RST_SW        (3 << RGU_STATUS1_SDIO_RST_SHIFT) /* Activated by software */
+#define RGU_STATUS1_EMC_RST_SHIFT        (10)       /* Bits 10-11: Status of the EMC_RST reset generator output */
+#define RGU_STATUS1_EMC_RST_MASK         (3 << RGU_STATUS1_EMC_RST_SHIFT)
+#  define RGU_STATUS1_EMC_RST_NONE       (0 << RGU_STATUS1_EMC_RST_SHIFT) /* No reset activated */
+#  define RGU_STATUS1_EMC_RST_HW         (1 << RGU_STATUS1_EMC_RST_SHIFT) /* Activated by reset generator */
+#  define RGU_STATUS1_EMC_RST_SW         (3 << RGU_STATUS1_EMC_RST_SHIFT) /* Activated by software */
+#define RGU_STATUS1_ETHERNET_RST_SHIFT   (12)       /* Bits 12-13: Status of the ETHERNET_RST reset generator output */
+#define RGU_STATUS1_ETHERNET_RST_MASK    (3 << RGU_STATUS1_ETHERNET_RST_SHIFT)
+#  define RGU_STATUS1_ETHERNET_RST_NONE  (0 << RGU_STATUS1_ETHERNET_RST_SHIFT) /* No reset activated */
+#  define RGU_STATUS1_ETHERNET_RST_HW    (1 << RGU_STATUS1_ETHERNET_RST_SHIFT) /* Activated by reset generator */
+#  define RGU_STATUS1_ETHERNET_RST_SW    (3 << RGU_STATUS1_ETHERNET_RST_SHIFT) /* Activated by software */
+#define RGU_STATUS1_FLASHA_RST_SHIFT     (18)       /* Bits 18-19: Status of the FLASHA_RST reset generator output */
+#define RGU_STATUS1_FLASHA_RST_MASK      (3 << RGU_STATUS1_FLASHA_RST_SHIFT)
+#  define RGU_STATUS1_FLASHA_RST_NONE    (0 << RGU_STATUS1_FLASHA_RST_SHIFT) /* No reset activated */
+#  define RGU_STATUS1_FLASHA_RST_HW      (1 << RGU_STATUS1_FLASHA_RST_SHIFT) /* Activated by reset generator */
+#  define RGU_STATUS1_FLASHA_RST_SW      (3 << RGU_STATUS1_FLASHA_RST_SHIFT) /* Activated by software */
+#define RGU_STATUS1_EEPROM_RST_SHIFT     (22)       /* Bits 22-23: Status of the EEPROM_RST reset generator output */
+#define RGU_STATUS1_EEPROM_RST_MASK      (3 << RGU_STATUS1_EEPROM_RST_SHIFT)
+#  define RGU_STATUS1_EEPROM_RST_NONE    (0 << RGU_STATUS1_EEPROM_RST_SHIFT) /* No reset activated */
+#  define RGU_STATUS1_EEPROM_RST_HW      (1 << RGU_STATUS1_EEPROM_RST_SHIFT) /* Activated by reset generator */
+#  define RGU_STATUS1_EEPROM_RST_SW      (3 << RGU_STATUS1_EEPROM_RST_SHIFT) /* Activated by software */
+#define RGU_STATUS1_GPIO_RST_SHIFT       (24)       /* Bits 24-25: Status of the GPIO_RST reset generator output */
+#define RGU_STATUS1_GPIO_RST_MASK        (3 << RGU_STATUS1_GPIO_RST_SHIFT)
+#  define RGU_STATUS1_GPIO_RST_NONE      (0 << RGU_STATUS1_GPIO_RST_SHIFT) /* No reset activated */
+#  define RGU_STATUS1_GPIO_RST_HW        (1 << RGU_STATUS1_GPIO_RST_SHIFT) /* Activated by reset generator */
+#  define RGU_STATUS1_GPIO_RST_SW        (3 << RGU_STATUS1_GPIO_RST_SHIFT) /* Activated by software */
+#define RGU_STATUS1_FLASHB_RST_SHIFT     (26)       /* Bits 26-27: Status of the FLASHB_RST reset generator output */
+#define RGU_STATUS1_FLASHB_RST_MASK      (3 << RGU_STATUS1_FLASHB_RST_SHIFT)
+#  define RGU_STATUS1_FLASHB_RST_NONE    (0 << RGU_STATUS1_FLASHB_RST_SHIFT) /* No reset activated */
+#  define RGU_STATUS1_FLASHB_RST_HW      (1 << RGU_STATUS1_FLASHB_RST_SHIFT) /* Activated by reset generator */
+#  define RGU_STATUS1_FLASHB_RST_SW      (3 << RGU_STATUS1_FLASHB_RST_SHIFT) /* Activated by software */
+                                                    /* Bits 28-31:  Reserved */
+/* Reset status register 2 */
+
+#define RGU_STATUS2_TIMER0_RST_SHIFT     (0)        /* Bits 0-1: 1:0  Status of the TIMER0_RST reset generator output */
+#define RGU_STATUS2_TIMER0_RST_MASK      (3 << RGU_STATUS2_TIMER0_RST_SHIFT)
+#  define RGU_STATUS2_TIMER0_RST_NONE    (0 << RGU_STATUS2_TIMER0_RST_SHIFT) /* No reset activated */
+#  define RGU_STATUS2_TIMER0_RST_HW      (1 << RGU_STATUS2_TIMER0_RST_SHIFT) /* Activated by reset generator */
+#  define RGU_STATUS2_TIMER0_RST_SW      (3 << RGU_STATUS2_TIMER0_RST_SHIFT) /* Activated by software */
+#define RGU_STATUS2_TIMER1_RST_SHIFT     (2)        /* Bits 2-3: 3:2  Status of the TIMER1_RST reset generator output */
+#define RGU_STATUS2_TIMER1_RST_MASK      (3 << RGU_STATUS2_TIMER1_RST_SHIFT)
+#  define RGU_STATUS2_TIMER1_RST_NONE    (0 << RGU_STATUS2_TIMER1_RST_SHIFT) /* No reset activated */
+#  define RGU_STATUS2_TIMER1_RST_HW      (1 << RGU_STATUS2_TIMER1_RST_SHIFT) /* Activated by reset generator */
+#  define RGU_STATUS2_TIMER1_RST_SW      (3 << RGU_STATUS2_TIMER1_RST_SHIFT) /* Activated by software */
+#define RGU_STATUS2_TIMER2_RST_SHIFT     (4)        /* Bits 4-5: 5:4  Status of the TIMER2_RST reset generator output */
+#define RGU_STATUS2_TIMER2_RST_MASK      (3 << RGU_STATUS2_TIMER2_RST_SHIFT)
+#  define RGU_STATUS2_TIMER2_RST_NONE    (0 << RGU_STATUS2_TIMER2_RST_SHIFT) /* No reset activated */
+#  define RGU_STATUS2_TIMER2_RST_HW      (1 << RGU_STATUS2_TIMER2_RST_SHIFT) /* Activated by reset generator */
+#  define RGU_STATUS2_TIMER2_RST_SW      (3 << RGU_STATUS2_TIMER2_RST_SHIFT) /* Activated by software */
+#define RGU_STATUS2_TIMER3_RST_SHIFT     (6)        /* Bits 6-7: 7:6  Status of the TIMER3_RST reset generator output */
+#define RGU_STATUS2_TIMER3_RST_MASK      (3 << RGU_STATUS2_TIMER3_RST_SHIFT)
+#  define RGU_STATUS2_TIMER3_RST_NONE    (0 << RGU_STATUS2_TIMER3_RST_SHIFT) /* No reset activated */
+#  define RGU_STATUS2_TIMER3_RST_HW      (1 << RGU_STATUS2_TIMER3_RST_SHIFT) /* Activated by reset generator */
+#  define RGU_STATUS2_TIMER3_RST_SW      (3 << RGU_STATUS2_TIMER3_RST_SHIFT) /* Activated by software */
+#define RGU_STATUS2_RITIMER_RST_SHIFT    (8)        /* Bits 8-9: 9:8  Status of the RITIMER_RST reset generator output */
+#define RGU_STATUS2_RITIMER_RST_MASK     (3 << RGU_STATUS2_RITIMER_RST_SHIFT)
+#  define RGU_STATUS2_RITIMER_RST_NONE   (0 << RGU_STATUS2_RITIMER_RST_SHIFT) /* No reset activated */
+#  define RGU_STATUS2_RITIMER_RST_HW     (1 << RGU_STATUS2_RITIMER_RST_SHIFT) /* Activated by reset generator */
+#  define RGU_STATUS2_RITIMER_RST_SW     (3 << RGU_STATUS2_RITIMER_RST_SHIFT) /* Activated by software */
+#define RGU_STATUS2_SCT_RST_SHIFT        (10)       /* Bits 10-11: 11:10  Status of the SCT_RST reset generator output */
+#define RGU_STATUS2_SCT_RST_MASK         (3 << RGU_STATUS2_SCT_RST_SHIFT)
+#  define RGU_STATUS2_SCT_RST_NONE       (0 << RGU_STATUS2_SCT_RST_SHIFT) /* No reset activated */
+#  define RGU_STATUS2_SCT_RST_HW         (1 << RGU_STATUS2_SCT_RST_SHIFT) /* Activated by reset generator */
+#  define RGU_STATUS2_SCT_RST_SW         (3 << RGU_STATUS2_SCT_RST_SHIFT) /* Activated by software */
+#define RGU_STATUS2_MCPWM_RST_SHIFT      (12)       /* Bits 12-13: 13:12  Status of the MOTOCONPWM_RST reset generator output */
+#define RGU_STATUS2_MCPWM_RST_MASK       (3 << RGU_STATUS2_MCPWM_RST_SHIFT)
+#  define RGU_STATUS2_MCPWM_RST_NONE     (0 << RGU_STATUS2_MCPWM_RST_SHIFT) /* No reset activated */
+#  define RGU_STATUS2_MCPWM_RST_HW       (1 << RGU_STATUS2_MCPWM_RST_SHIFT) /* Activated by reset generator */
+#  define RGU_STATUS2_MCPWM_RST_SW       (3 << RGU_STATUS2_MCPWM_RST_SHIFT) /* Activated by software */
+#define RGU_STATUS2_QEI_RST_SHIFT        (14)       /* Bits 14-15: 15:14  Status of the QEI_RST reset generator output */
+#define RGU_STATUS2_QEI_RST_MASK         (3 << RGU_STATUS2_QEI_RST_SHIFT)
+#  define RGU_STATUS2_QEI_RST_NONE       (0 << RGU_STATUS2_QEI_RST_SHIFT) /* No reset activated */
+#  define RGU_STATUS2_QEI_RST_HW         (1 << RGU_STATUS2_QEI_RST_SHIFT) /* Activated by reset generator */
+#  define RGU_STATUS2_QEI_RST_SW         (3 << RGU_STATUS2_QEI_RST_SHIFT) /* Activated by software */
+#define RGU_STATUS2_ADC0_RST_SHIFT       (16)       /* Bits 16-17: 17:16  Status of the ADC0_RST reset generator output */
+#define RGU_STATUS2_ADC0_RST_MASK        (3 << RGU_STATUS2_ADC0_RST_SHIFT)
+#  define RGU_STATUS2_ADC0_RST_NONE      (0 << RGU_STATUS2_ADC0_RST_SHIFT) /* No reset activated */
+#  define RGU_STATUS2_ADC0_RST_HW        (1 << RGU_STATUS2_ADC0_RST_SHIFT) /* Activated by reset generator */
+#  define RGU_STATUS2_ADC0_RST_SW        (3 << RGU_STATUS2_ADC0_RST_SHIFT) /* Activated by software */
+#define RGU_STATUS2_ADC1_RST_SHIFT       (18)       /* Bits 18-19: 19:18  Status of the ADC1_RST reset generator output */
+#define RGU_STATUS2_ADC1_RST_MASK        (3 << RGU_STATUS2_ADC1_RST_SHIFT)
+#  define RGU_STATUS2_ADC1_RST_NONE      (0 << RGU_STATUS2_ADC1_RST_SHIFT) /* No reset activated */
+#  define RGU_STATUS2_ADC1_RST_HW        (1 << RGU_STATUS2_ADC1_RST_SHIFT) /* Activated by reset generator */
+#  define RGU_STATUS2_ADC1_RST_SW        (3 << RGU_STATUS2_ADC1_RST_SHIFT) /* Activated by software */
+#define RGU_STATUS2_DAC_RST_SHIFT        (20)       /* Bits 20-21: 21:20  Status of the DAC_RST reset generator output */
+#define RGU_STATUS2_DAC_RST_MASK         (3 << RGU_STATUS2_DAC_RST_SHIFT)
+#  define RGU_STATUS2_DAC_RST_NONE       (0 << RGU_STATUS2_DAC_RST_SHIFT) /* No reset activated */
+#  define RGU_STATUS2_DAC_RST_HW         (1 << RGU_STATUS2_DAC_RST_SHIFT) /* Activated by reset generator */
+#  define RGU_STATUS2_DAC_RST_SW         (3 << RGU_STATUS2_DAC_RST_SHIFT) /* Activated by software */
+                                                   /* Bits 22-23:  Reserved */
+#define RGU_STATUS2_USART0_RST_SHIFT     (24)       /* Bits 24-24: 25:24  Status of the USART0_RST reset generator output */
+#define RGU_STATUS2_USART0_RST_MASK      (3 << RGU_STATUS2_USART0_RST_SHIFT)
+#  define RGU_STATUS2_USART0_RST_NONE    (0 << RGU_STATUS2_USART0_RST_SHIFT) /* No reset activated */
+#  define RGU_STATUS2_USART0_RST_HW      (1 << RGU_STATUS2_USART0_RST_SHIFT) /* Activated by reset generator */
+#  define RGU_STATUS2_USART0_RST_SW      (3 << RGU_STATUS2_USART0_RST_SHIFT) /* Activated by software */
+#define RGU_STATUS2_UART1_RST_SHIFT      (26)       /* Bits 26-27: 27:26  Status of the UART1_RST reset generator output */
+#define RGU_STATUS2_UART1_RST_MASK       (3 << RGU_STATUS2_UART1_RST_SHIFT)
+#  define RGU_STATUS2_UART1_RST_NONE     (0 << RGU_STATUS2_UART1_RST_SHIFT) /* No reset activated */
+#  define RGU_STATUS2_UART1_RST_HW       (1 << RGU_STATUS2_UART1_RST_SHIFT) /* Activated by reset generator */
+#  define RGU_STATUS2_UART1_RST_SW       (3 << RGU_STATUS2_UART1_RST_SHIFT) /* Activated by software */
+#define RGU_STATUS2_USART2_RST_SHIFT     (28)       /* Bits 28-29: 29:28  Status of the USART2_RST reset generator output */
+#define RGU_STATUS2_USART2_RST_MASK      (3 << RGU_STATUS2_USART2_RST_SHIFT)
+#  define RGU_STATUS2_USART2_RST_NONE    (0 << RGU_STATUS2_USART2_RST_SHIFT) /* No reset activated */
+#  define RGU_STATUS2_USART2_RST_HW      (1 << RGU_STATUS2_USART2_RST_SHIFT) /* Activated by reset generator */
+#  define RGU_STATUS2_USART2_RST_SW      (3 << RGU_STATUS2_USART2_RST_SHIFT) /* Activated by software */
+#define RGU_STATUS2_USART3_RST_SHIFT     (30)       /* Bits 30-31: 31:30  Status of the USART3_RST reset generator output */
+#define RGU_STATUS2_USART3_RST_MASK      (3 << RGU_STATUS2_USART3_RST_SHIFT)
+#  define RGU_STATUS2_USART3_RST_NONE    (0 << RGU_STATUS2_USART3_RST_SHIFT) /* No reset activated */
+#  define RGU_STATUS2_USART3_RST_HW      (1 << RGU_STATUS2_USART3_RST_SHIFT) /* Activated by reset generator */
+#  define RGU_STATUS2_USART3_RST_SW      (3 << RGU_STATUS2_USART3_RST_SHIFT) /* Activated by software */
+
+/* Reset status register 3 */
+
+#define RGU_STATUS3_I2C0_RST_SHIFT       (0)        /* Bits 0-1: 1:0  Status of the I2C0_RST reset generator output */
+#define RGU_STATUS3_I2C0_RST_MASK        (3 << RGU_STATUS3_I2C0_RST_SHIFT)
+#  define RGU_STATUS3_I2C0_RST_NONE      (0 << RGU_STATUS3_I2C0_RST_SHIFT) /* No reset activated */
+#  define RGU_STATUS3_I2C0_RST_HW        (1 << RGU_STATUS3_I2C0_RST_SHIFT) /* Activated by reset generator */
+#  define RGU_STATUS3_I2C0_RST_SW        (3 << RGU_STATUS3_I2C0_RST_SHIFT) /* Activated by software */
+#define RGU_STATUS3_I2C1_RST_SHIFT       (2)        /* Bits 2-3: 3:2  Status of the I2C1_RST reset generator output */
+#define RGU_STATUS3_I2C1_RST_MASK        (3 << RGU_STATUS3_I2C1_RST_SHIFT)
+#  define RGU_STATUS3_I2C1_RST_NONE      (0 << RGU_STATUS3_I2C1_RST_SHIFT) /* No reset activated */
+#  define RGU_STATUS3_I2C1_RST_HW        (1 << RGU_STATUS3_I2C1_RST_SHIFT) /* Activated by reset generator */
+#  define RGU_STATUS3_I2C1_RST_SW        (3 << RGU_STATUS3_I2C1_RST_SHIFT) /* Activated by software */
+#define RGU_STATUS3_SSP0_RST_SHIFT       (4)        /* Bits 4-5: 5:4  Status of the SSP0_RST reset generator output */
+#define RGU_STATUS3_SSP0_RST_MASK        (3 << RGU_STATUS3_SSP0_RST_SHIFT)
+#  define RGU_STATUS3_SSP0_RST_NONE      (0 << RGU_STATUS3_SSP0_RST_SHIFT) /* No reset activated */
+#  define RGU_STATUS3_SSP0_RST_HW        (1 << RGU_STATUS3_SSP0_RST_SHIFT) /* Activated by reset generator */
+#  define RGU_STATUS3_SSP0_RST_SW        (3 << RGU_STATUS3_SSP0_RST_SHIFT) /* Activated by software */
+#define RGU_STATUS3_SSP1_RST_SHIFT       (6)        /* Bits 6-7: 7:6  Status of the SSP1_RST reset generator output */
+#define RGU_STATUS3_SSP1_RST_MASK        (3 << RGU_STATUS3_SSP1_RST_SHIFT)
+#  define RGU_STATUS3_SSP1_RST_NONE      (0 << RGU_STATUS3_SSP1_RST_SHIFT) /* No reset activated */
+#  define RGU_STATUS3_SSP1_RST_HW        (1 << RGU_STATUS3_SSP1_RST_SHIFT) /* Activated by reset generator */
+#  define RGU_STATUS3_SSP1_RST_SW        (3 << RGU_STATUS3_SSP1_RST_SHIFT) /* Activated by software */
+#define RGU_STATUS3_I2S_RST_SHIFT        (8)        /* Bits 8-9: 9:8  Status of the I2S_RST reset generator output */
+#define RGU_STATUS3_I2S_RST_MASK         (3 << RGU_STATUS3_I2S_RST_SHIFT)
+#  define RGU_STATUS3_I2S_RST_NONE       (0 << RGU_STATUS3_I2S_RST_SHIFT) /* No reset activated */
+#  define RGU_STATUS3_I2S_RST_HW         (1 << RGU_STATUS3_I2S_RST_SHIFT) /* Activated by reset generator */
+#  define RGU_STATUS3_I2S_RST_SW         (3 << RGU_STATUS3_I2S_RST_SHIFT) /* Activated by software */
+#define RGU_STATUS3_SPIFI_RST_SHIFT      (10)       /* Bits 10-11: 11:10  Status of the SPIFI_RST reset generator output */
+#define RGU_STATUS3_SPIFI_RST_MASK       (3 << RGU_STATUS3_SPIFI_RST_SHIFT)
+#  define RGU_STATUS3_SPIFI_RST_NONE     (0 << RGU_STATUS3_SPIFI_RST_SHIFT) /* No reset activated */
+#  define RGU_STATUS3_SPIFI_RST_HW       (1 << RGU_STATUS3_SPIFI_RST_SHIFT) /* Activated by reset generator */
+#  define RGU_STATUS3_SPIFI_RST_SW       (3 << RGU_STATUS3_SPIFI_RST_SHIFT) /* Activated by software */
+#define RGU_STATUS3_CAN1_RST_SHIFT       (12)       /* Bits 12-13: 13:12  Status of the CAN1_RST reset generator output */
+#define RGU_STATUS3_CAN1_RST_MASK        (3 << RGU_STATUS3_CAN1_RST_SHIFT)
+#  define RGU_STATUS3_CAN1_RST_NONE      (0 << RGU_STATUS3_CAN1_RST_SHIFT) /* No reset activated */
+#  define RGU_STATUS3_CAN1_RST_HW        (1 << RGU_STATUS3_CAN1_RST_SHIFT) /* Activated by reset generator */
+#  define RGU_STATUS3_CAN1_RST_SW        (3 << RGU_STATUS3_CAN1_RST_SHIFT) /* Activated by software */
+#define RGU_STATUS3_CAN0_RST_SHIFT       (14)       /* Bits 14-15: 15:14  Status of the CAN0_RST reset generator output */
+#define RGU_STATUS3_CAN0_RST_MASK        (3 << RGU_STATUS3_CAN0_RST_SHIFT)
+#  define RGU_STATUS3_CAN0_RST_NONE      (0 << RGU_STATUS3_CAN0_RST_SHIFT) /* No reset activated */
+#  define RGU_STATUS3_CAN0_RST_HW        (1 << RGU_STATUS3_CAN0_RST_SHIFT) /* Activated by reset generator */
+#  define RGU_STATUS3_CAN0_RST_SW        (3 << RGU_STATUS3_CAN0_RST_SHIFT) /* Activated by software */
+#define RGU_STATUS3_M0APP_RST_SHIFT      (16)       /* Bits 16-17: 17:16  Status of the M0APP_RST reset generator output */
+#define RGU_STATUS3_M0APP_RST_MASK       (3 << RGU_STATUS3_M0APP_RST_SHIFT)
+#  define RGU_STATUS3_M0APP_RST_NONE     (0 << RGU_STATUS3_M0APP_RST_SHIFT) /* No reset activated */
+#  define RGU_STATUS3_M0APP_RST_HW       (1 << RGU_STATUS3_M0APP_RST_SHIFT) /* Activated by reset generator */
+#  define RGU_STATUS3_M0APP_RST_SW       (3 << RGU_STATUS3_M0APP_RST_SHIFT) /* Activated by software */
+#define RGU_STATUS3_SGPIO_RST_SHIFT      (18)       /* Bits 18-19: 19:18  Status of the SGPIO_RST reset generator output */
+#define RGU_STATUS3_SGPIO_RST_MASK       (3 << RGU_STATUS3_SGPIO_RST_SHIFT)
+#  define RGU_STATUS3_SGPIO_RST_NONE     (0 << RGU_STATUS3_SGPIO_RST_SHIFT) /* No reset activated */
+#  define RGU_STATUS3_SGPIO_RST_HW       (1 << RGU_STATUS3_SGPIO_RST_SHIFT) /* Activated by reset generator */
+#  define RGU_STATUS3_SGPIO_RST_SW       (3 << RGU_STATUS3_SGPIO_RST_SHIFT) /* Activated by software */
+#define RGU_STATUS3_SPI_RST_SHIFT        (20)       /* Bits 20-21: 21:20  Status of the SPI_RST reset generator output */
+#define RGU_STATUS3_SPI_RST_MASK         (3 << RGU_STATUS3_SPI_RST_SHIFT)
+#  define RGU_STATUS3_SPI_RST_NONE       (0 << RGU_STATUS3_SPI_RST_SHIFT) /* No reset activated */
+#  define RGU_STATUS3_SPI_RST_HW         (1 << RGU_STATUS3_SPI_RST_SHIFT) /* Activated by reset generator */
+#  define RGU_STATUS3_SPI_RST_SW         (3 << RGU_STATUS3_SPI_RST_SHIFT) /* Activated by software */
+                                                    /* Bits 22-31:  Reserved */
+/* Reset active status register */
+
+#define RGU_ACTIVE0_CORE_RST             (1 << 0)
+#define RGU_ACTIVE0_PERIPH_RST           (1 << 1)
+#define RGU_ACTIVE0_MASTER_RST           (1 << 2)
+                                                   /* Bit 3:  Reserved */
+#define RGU_ACTIVE0_WWDT_RST             (1 << 4)
+#define RGU_ACTIVE0_CREG_RST             (1 << 5)
+                                                   /* Bits 6-7:  Reserved */
+#define RGU_ACTIVE0_BUS_RST              (1 << 8)
+#define RGU_ACTIVE0_SCU_RST              (1 << 9)
+                                                   /* Bits 10-12:  Reserved */
+#define RGU_ACTIVE0_M4_RST               (1 << 13)
+                                                   /* Bits 14-15:  Reserved */
+#define RGU_ACTIVE0_LCD_RST              (1 << 16)
+#define RGU_ACTIVE0_USB0_RST             (1 << 17)
+#define RGU_ACTIVE0_USB1_RST             (1 << 18)
+#define RGU_ACTIVE0_DMA_RST              (1 << 19)
+#define RGU_ACTIVE0_SDIO_RST             (1 << 20)
+#define RGU_ACTIVE0_EMC_RST              (1 << 21)
+#define RGU_ACTIVE0_ETHERNET_RST         (1 << 22)
+                                                   /* Bits 23-24:  Reserved */
+#define RGU_ACTIVE0_FLASHA_RST           (1 << 25)
+                                                   /* Bit 26:  Reserved */
+#define RGU_ACTIVE0_EEPROM_RST           (1 << 27)
+#define RGU_ACTIVE0_GPIO_RST             (1 << 28)
+#define RGU_ACTIVE0_FLASHB_RST           (1 << 29)
+                                                   /* Bits 30-31:  Reserved */
+/* Reset active status register */
+
+#define RGU_ACTIVE1_TIMER0_RST           (1 << 0)
+#define RGU_ACTIVE1_TIMER1_RST           (1 << 1)
+#define RGU_ACTIVE1_TIMER2_RST           (1 << 2)
+#define RGU_ACTIVE1_TIMER3_RST           (1 << 3)
+#define RGU_ACTIVE1_RITIMER_RST          (1 << 4)
+#define RGU_ACTIVE1_SCT_RST              (1 << 5)
+#define RGU_ACTIVE1_MCPWM_RST            (1 << 6)
+#define RGU_ACTIVE1_QEI_RST              (1 << 7)
+#define RGU_ACTIVE1_ADC0_RST             (1 << 8)
+#define RGU_ACTIVE1_ADC1_RST             (1 << 9)
+#define RGU_ACTIVE1_DAC_RST              (1 << 10)
+                                                    /* Bit 11:  Reserved */
+#define RGU_ACTIVE1_USART0_RST           (1 << 12)
+#define RGU_ACTIVE1_UART1_RST            (1 << 13)
+#define RGU_ACTIVE1_USART2_RST           (1 << 14)
+#define RGU_ACTIVE1_USART3_RST           (1 << 15)
+#define RGU_ACTIVE1_I2C0_RST             (1 << 16)
+#define RGU_ACTIVE1_I2C1_RST             (1 << 17)
+#define RGU_ACTIVE1_SSP0_RST             (1 << 18)
+#define RGU_ACTIVE1_SSP1_RST             (1 << 19)
+#define RGU_ACTIVE1_I2S_RST              (1 << 20)
+#define RGU_ACTIVE1_SPIFI_RST            (1 << 21)
+#define RGU_ACTIVE1_CAN1_RST             (1 << 22)
+#define RGU_ACTIVE1_CAN0_RST             (1 << 23)
+#define RGU_ACTIVE1_M0APP_RST            (1 << 24)
+#define RGU_ACTIVE1_SGPIO_RST            (1 << 25)
+#define RGU_ACTIVE1_SPI_RST              (1 << 26)
+                                                    /* Bits 27-31:  Reserved */
+/* Reset external status register 0 for CORE_RST */
+
+#define RGU_EXTSTAT_CORE_EXTRESET        (1 << 0)   /* Bit 0: Reset activated by external reset from reset pin */
+                                                    /* Bits 1-3: Reserved */
+#define RGU_EXTSTAT_CORE_BODRESET        (1 << 4)   /* Bit 4: Reset activated by BOD reset */
+#define RGU_EXTSTAT_CORE_WWDTRESET       (1 << 5)   /* Bit 5: Reset activated by WWDT time-out */
+                                                    /* Bits 6-31: Reserved */
+/* Reset external status register 1 for PERIPH_RST */
+                                                    /* Bit 0: Reserved */
+#define RGU_EXTSTAT_PERIPH_CORERESET     (1 << 1)   /* Bit 1: Reset activated by CORE_RST output */
+                                                    /* Bits 2-31: Reserved */
+/* Reset external status register 2 for MASTER_RST */
+                                                    /* Bits 0-1: Reserved */
+#define RGU_EXTSTAT_MASTER_PERIPHRESET   (1 << 2)   /* Bit 2: Reset activated by PERIPHERAL_RST output */
+                                                    /* Bits 2-31: Reserved */
+/* Reset external status register 4 for WWDT_RST */
+                                                    /* Bit 0: Reserved */
+#define RGU_EXTSTAT_WWDT_CORERESET       (1 << 1)   /* Bit 1: Reset activated by CORE_RST output */
+                                                    /* Bits 2-31: Reserved */
+/* Reset external status register 5 for CREG_RST */
+                                                    /* Bit 0: Reserved */
+#define RGU_EXTSTAT_CREG_CORERESET       (1 << 1)   /* Bit 1: Reset activated by CORE_RST output */
+                                                    /* Bits 2-31: Reserved */
+/* Reset external status registers for PERIPHERAL_RESET */
+                                                    /* Bits 0-1: Reserved */
+#define RGU_EXTSTAT_PERIPH_RESET         (1 << 2)   /* Bit 2: Reset activated by PERIPHERAL_RST output */
+                                                    /* Bits 2-31: Reserved */
+/* Reset external status registers for MASTER_RESET */
+                                                    /* Bits 0-2: Reserved */
+#define RGU_EXTSTAT_MASTER_RESET         (1 << 3)   /* Bit 3: Reset activated by MASTER_RST output */
+                                                    /* Bits 2-31: Reserved */
+
+/****************************************************************************************************
+ * Public Types
+ ****************************************************************************************************/
+
+/****************************************************************************************************
+ * Public Data
+ ****************************************************************************************************/
+
+/****************************************************************************************************
+ * Public Functions
+ ****************************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_RGU_H */
diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_rit.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_rit.h
new file mode 100644
index 000000000..915836e80
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_rit.h
@@ -0,0 +1,89 @@
+/************************************************************************************
+ * arch/arm/src/lpc43xx/lpc43_rit.h
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_RIT_H
+#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_RIT_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Register offsets *****************************************************************/
+
+#define LPC43_RIT_COMPVAL_OFFSET 0x0000  /* Compare register */
+#define LPC43_RIT_MASK_OFFSET    0x0004  /* Mask register */
+#define LPC43_RIT_CTRL_OFFSET    0x0008  /* Control register */
+#define LPC43_RIT_COUNTER_OFFSET 0x000c  /* 32-bit counter */
+
+/* Register addresses ***************************************************************/
+
+#define LPC43_RIT_COMPVAL        (LPC43_RIT_BASE+LPC43_RIT_COMPVAL_OFFSET)
+#define LPC43_RIT_MASK           (LPC43_RIT_BASE+LPC43_RIT_MASK_OFFSET)
+#define LPC43_RIT_CTRL           (LPC43_RIT_BASE+LPC43_RIT_CTRL_OFFSET)
+#define LPC43_RIT_COUNTER        (LPC43_RIT_BASE+LPC43_RIT_COUNTER_OFFSET)
+
+/* Register bit definitions *********************************************************/
+/* Compare register (Bits 0-31: value compared to the counter) */
+
+/* Mask register (Bits 0-31: 32-bit mask value) */
+
+/* Control register */
+
+#define RIT_CTRL_INT             (1 << 0)  /* Bit 0: Interrupt flag */
+#define RIT_CTRL_ENCLR           (1 << 1)  /* Bit 1: Timer enable clear */
+#define RIT_CTRL_ENBR            (1 << 2)  /* Bit 2: Timer enable for debug */
+#define RIT_CTRL_EN              (1 << 3)  /* Bit 3: Timer enable */
+                                           /* Bits 4-31: Reserved */
+/* 32-bit counter (Bits 0-31: 32-bit up counter) */
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_RIT_H */
diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_rtc.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_rtc.h
new file mode 100644
index 000000000..971349354
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_rtc.h
@@ -0,0 +1,371 @@
+/************************************************************************************
+ * arch/arm/src/lpc43xx/lpc43_rtc.h
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LPC43XX_LPC43_RTC_H
+#define __ARCH_ARM_SRC_LPC43XX_LPC43_RTC_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Register offsets *****************************************************************/
+/* Miscellaneous registers */
+
+#define LPC43_RTC_ILR_OFFSET    0x0000 /* Interrupt Location Register */
+#define LPC43_RTC_CCR_OFFSET    0x0008 /* Clock Control Register */
+#define LPC43_RTC_CIIR_OFFSET   0x000c /* Counter Increment Interrupt Register */
+#define LPC43_RTC_AMR_OFFSET    0x0010 /* Alarm Mask Register */
+
+/* Consolidated time registers */
+
+#define LPC43_RTC_CTIME0_OFFSET 0x0014 /* Consolidated Time Register 0 */
+#define LPC43_RTC_CTIME1_OFFSET 0x0018 /* Consolidated Time Register 1 */
+#define LPC43_RTC_CTIME2_OFFSET 0x001c /* Consolidated Time Register 2 */
+
+/* Time counter registers */
+
+#define LPC43_RTC_SEC_OFFSET    0x0020 /* Seconds Counter */
+#define LPC43_RTC_MIN_OFFSET    0x0024 /* Minutes Register */
+#define LPC43_RTC_HOUR_OFFSET   0x0028 /* Hours Register */
+#define LPC43_RTC_DOM_OFFSET    0x002c /* Day of Month Register */
+#define LPC43_RTC_DOW_OFFSET    0x0030 /* Day of Week Register */
+#define LPC43_RTC_DOY_OFFSET    0x0034 /* Day of Year Register */
+#define LPC43_RTC_MONTH_OFFSET  0x0038 /* Months Register */
+#define LPC43_RTC_YEAR_OFFSET   0x003c /* Years Register */
+#define LPC43_RTC_CALIB_OFFSET  0x0040 /* Calibration Value Register */
+
+/* Alarm register group */
+
+#define LPC43_RTC_ASEC_OFFSET   0x0060 /* Alarm value for Seconds */
+#define LPC43_RTC_AMIN_OFFSET   0x0064 /* Alarm value for Minutes */
+#define LPC43_RTC_AHOUR_OFFSET  0x0068 /* Alarm value for Hours */
+#define LPC43_RTC_ADOM_OFFSET   0x006c /* Alarm value for Day of Month */
+#define LPC43_RTC_ADOW_OFFSET   0x0070 /* Alarm value for Day of Week */
+#define LPC43_RTC_ADOY_OFFSET   0x0074 /* Alarm value for Day of Year */
+#define LPC43_RTC_AMON_OFFSET   0x0078 /* Alarm value for Months  */
+#define LPC43_RTC_AYEAR_OFFSET  0x007c /* Alarm value for Year */
+
+/* General Purpose Registers.
+ *
+ * In addition to the RTC registers, 64 general purpose registers are available
+ * to store data when the main power supply is switched off. The general purpose
+ * registers reside in the RTC power domain and can be battery powered.
+ */
+
+#define LPC43_REGFILE_OFFSET(n) (0x0000 + ((n) << 2))
+#define LPC43_REGFILE0_OFFSET   0x0000
+#define LPC43_REGFILE1_OFFSET   0x0004
+#define LPC43_REGFILE2_OFFSET   0x0008
+#define LPC43_REGFILE3_OFFSET   0x000c
+#define LPC43_REGFILE4_OFFSET   0x0010
+#define LPC43_REGFILE5_OFFSET   0x0014
+#define LPC43_REGFILE6_OFFSET   0x0018
+#define LPC43_REGFILE7_OFFSET   0x001c
+#define LPC43_REGFILE8_OFFSET   0x0020
+#define LPC43_REGFILE9_OFFSET   0x0024
+#define LPC43_REGFILE10_OFFSET  0x0028
+#define LPC43_REGFILE11_OFFSET  0x002c
+#define LPC43_REGFILE12_OFFSET  0x0030
+#define LPC43_REGFILE13_OFFSET  0x0034
+#define LPC43_REGFILE14_OFFSET  0x0038
+#define LPC43_REGFILE15_OFFSET  0x003c
+#define LPC43_REGFILE16_OFFSET  0x0040
+#define LPC43_REGFILE17_OFFSET  0x0044
+#define LPC43_REGFILE18_OFFSET  0x0048
+#define LPC43_REGFILE19_OFFSET  0x004c
+#define LPC43_REGFILE20_OFFSET  0x0050
+#define LPC43_REGFILE21_OFFSET  0x0054
+#define LPC43_REGFILE22_OFFSET  0x0058
+#define LPC43_REGFILE23_OFFSET  0x005c
+#define LPC43_REGFILE24_OFFSET  0x0060
+#define LPC43_REGFILE25_OFFSET  0x0064
+#define LPC43_REGFILE26_OFFSET  0x0068
+#define LPC43_REGFILE27_OFFSET  0x006c
+#define LPC43_REGFILE28_OFFSET  0x0070
+#define LPC43_REGFILE29_OFFSET  0x0074
+#define LPC43_REGFILE30_OFFSET  0x0078
+#define LPC43_REGFILE31_OFFSET  0x007c
+#define LPC43_REGFILE32_OFFSET  0x0080
+#define LPC43_REGFILE33_OFFSET  0x0084
+#define LPC43_REGFILE34_OFFSET  0x0088
+#define LPC43_REGFILE35_OFFSET  0x008c
+#define LPC43_REGFILE36_OFFSET  0x0090
+#define LPC43_REGFILE37_OFFSET  0x0094
+#define LPC43_REGFILE38_OFFSET  0x0098
+#define LPC43_REGFILE39_OFFSET  0x009c
+#define LPC43_REGFILE40_OFFSET  0x00a0
+#define LPC43_REGFILE41_OFFSET  0x00a4
+#define LPC43_REGFILE42_OFFSET  0x00a8
+#define LPC43_REGFILE43_OFFSET  0x00ac
+#define LPC43_REGFILE44_OFFSET  0x00b0
+#define LPC43_REGFILE45_OFFSET  0x00b4
+#define LPC43_REGFILE46_OFFSET  0x00b8
+#define LPC43_REGFILE47_OFFSET  0x00bc
+#define LPC43_REGFILE48_OFFSET  0x00c0
+#define LPC43_REGFILE49_OFFSET  0x00c4
+#define LPC43_REGFILE50_OFFSET  0x00c8
+#define LPC43_REGFILE51_OFFSET  0x00cc
+#define LPC43_REGFILE52_OFFSET  0x00d0
+#define LPC43_REGFILE53_OFFSET  0x00d4
+#define LPC43_REGFILE54_OFFSET  0x00d8
+#define LPC43_REGFILE55_OFFSET  0x00dc
+#define LPC43_REGFILE56_OFFSET  0x00e0
+#define LPC43_REGFILE57_OFFSET  0x00e4
+#define LPC43_REGFILE58_OFFSET  0x00e8
+#define LPC43_REGFILE59_OFFSET  0x00ec
+#define LPC43_REGFILE60_OFFSET  0x00f0
+#define LPC43_REGFILE61_OFFSET  0x00f4
+#define LPC43_REGFILE62_OFFSET  0x00f8
+#define LPC43_REGFILE63_OFFSET  0x00fc
+
+/* Register addresses ***************************************************************/
+/* Miscellaneous registers */
+
+#define LPC43_RTC_ILR           (LPC43_RTC_BASE+LPC43_RTC_ILR_OFFSET)
+#define LPC43_RTC_CCR           (LPC43_RTC_BASE+LPC43_RTC_CCR_OFFSET)
+#define LPC43_RTC_CIIR          (LPC43_RTC_BASE+LPC43_RTC_CIIR_OFFSET)
+#define LPC43_RTC_AMR           (LPC43_RTC_BASE+LPC43_RTC_AMR_OFFSET)
+
+/* Consolidated time registers */
+
+#define LPC43_RTC_CTIME0        (LPC43_RTC_BASE+LPC43_RTC_CTIME0_OFFSET)
+#define LPC43_RTC_CTIME1        (LPC43_RTC_BASE+LPC43_RTC_CTIME1_OFFSET)
+#define LPC43_RTC_CTIME2        (LPC43_RTC_BASE+LPC43_RTC_CTIME2_OFFSET)
+
+/* Time counter registers */
+
+#define LPC43_RTC_SEC           (LPC43_RTC_BASE+LPC43_RTC_SEC_OFFSET)
+#define LPC43_RTC_MIN           (LPC43_RTC_BASE+LPC43_RTC_MIN_OFFSET)
+#define LPC43_RTC_HOUR          (LPC43_RTC_BASE+LPC43_RTC_HOUR_OFFSET)
+#define LPC43_RTC_DOM           (LPC43_RTC_BASE+LPC43_RTC_DOM_OFFSET)
+#define LPC43_RTC_DOW           (LPC43_RTC_BASE+LPC43_RTC_DOW_OFFSET)
+#define LPC43_RTC_DOY           (LPC43_RTC_BASE+LPC43_RTC_DOY_OFFSET)
+#define LPC43_RTC_MONTH         (LPC43_RTC_BASE+LPC43_RTC_MONTH_OFFSET)
+#define LPC43_RTC_YEAR          (LPC43_RTC_BASE+LPC43_RTC_YEAR_OFFSET)
+#define LPC43_RTC_CALIB         (LPC43_RTC_BASE+LPC43_RTC_CALIB_OFFSET)
+
+/* Alarm register group */
+
+#define LPC43_RTC_ASEC          (LPC43_RTC_BASE+LPC43_RTC_ASEC_OFFSET)
+#define LPC43_RTC_AMIN          (LPC43_RTC_BASE+LPC43_RTC_AMIN_OFFSET)
+#define LPC43_RTC_AHOUR         (LPC43_RTC_BASE+LPC43_RTC_AHOUR_OFFSET)
+#define LPC43_RTC_ADOM          (LPC43_RTC_BASE+LPC43_RTC_ADOM_OFFSET)
+#define LPC43_RTC_ADOW          (LPC43_RTC_BASE+LPC43_RTC_ADOW_OFFSET)
+#define LPC43_RTC_ADOY          (LPC43_RTC_BASE+LPC43_RTC_ADOY_OFFSET)
+#define LPC43_RTC_AMON          (LPC43_RTC_BASE+LPC43_RTC_AMON_OFFSET)
+#define LPC43_RTC_AYEAR         (LPC43_RTC_BASE+LPC43_RTC_AYEAR_OFFSET)
+
+/* General Purpose Registers */
+
+#define LPC43_REGFILE(n)        (LPC43_BACKUP_BASE+LPC43_REGFILE_OFFSET(n))
+#define LPC43_REGFILE0          (LPC43_BACKUP_BASE+LPC43_REGFILE0_OFFSET)
+#define LPC43_REGFILE1          (LPC43_BACKUP_BASE+LPC43_REGFILE1_OFFSET)
+#define LPC43_REGFILE2          (LPC43_BACKUP_BASE+LPC43_REGFILE2_OFFSET)
+#define LPC43_REGFILE3          (LPC43_BACKUP_BASE+LPC43_REGFILE3_OFFSET)
+#define LPC43_REGFILE4          (LPC43_BACKUP_BASE+LPC43_REGFILE4_OFFSET)
+#define LPC43_REGFILE5          (LPC43_BACKUP_BASE+LPC43_REGFILE5_OFFSET)
+#define LPC43_REGFILE6          (LPC43_BACKUP_BASE+LPC43_REGFILE6_OFFSET)
+#define LPC43_REGFILE7          (LPC43_BACKUP_BASE+LPC43_REGFILE7_OFFSET)
+#define LPC43_REGFILE8          (LPC43_BACKUP_BASE+LPC43_REGFILE8_OFFSET)
+#define LPC43_REGFILE9          (LPC43_BACKUP_BASE+LPC43_REGFILE9_OFFSET)
+#define LPC43_REGFILE10         (LPC43_BACKUP_BASE+LPC43_REGFILE10_OFFSET)
+#define LPC43_REGFILE11         (LPC43_BACKUP_BASE+LPC43_REGFILE11_OFFSET)
+#define LPC43_REGFILE12         (LPC43_BACKUP_BASE+LPC43_REGFILE12_OFFSET)
+#define LPC43_REGFILE13         (LPC43_BACKUP_BASE+LPC43_REGFILE13_OFFSET)
+#define LPC43_REGFILE14         (LPC43_BACKUP_BASE+LPC43_REGFILE14_OFFSET)
+#define LPC43_REGFILE15         (LPC43_BACKUP_BASE+LPC43_REGFILE15_OFFSET)
+#define LPC43_REGFILE16         (LPC43_BACKUP_BASE+LPC43_REGFILE16_OFFSET)
+#define LPC43_REGFILE17         (LPC43_BACKUP_BASE+LPC43_REGFILE17_OFFSET)
+#define LPC43_REGFILE18         (LPC43_BACKUP_BASE+LPC43_REGFILE18_OFFSET)
+#define LPC43_REGFILE19         (LPC43_BACKUP_BASE+LPC43_REGFILE19_OFFSET)
+#define LPC43_REGFILE20         (LPC43_BACKUP_BASE+LPC43_REGFILE20_OFFSET)
+#define LPC43_REGFILE21         (LPC43_BACKUP_BASE+LPC43_REGFILE21_OFFSET)
+#define LPC43_REGFILE22         (LPC43_BACKUP_BASE+LPC43_REGFILE22_OFFSET)
+#define LPC43_REGFILE23         (LPC43_BACKUP_BASE+LPC43_REGFILE23_OFFSET)
+#define LPC43_REGFILE24         (LPC43_BACKUP_BASE+LPC43_REGFILE24_OFFSET)
+#define LPC43_REGFILE25         (LPC43_BACKUP_BASE+LPC43_REGFILE25_OFFSET)
+#define LPC43_REGFILE26         (LPC43_BACKUP_BASE+LPC43_REGFILE26_OFFSET)
+#define LPC43_REGFILE27         (LPC43_BACKUP_BASE+LPC43_REGFILE27_OFFSET)
+#define LPC43_REGFILE28         (LPC43_BACKUP_BASE+LPC43_REGFILE28_OFFSET)
+#define LPC43_REGFILE29         (LPC43_BACKUP_BASE+LPC43_REGFILE29_OFFSET)
+#define LPC43_REGFILE30         (LPC43_BACKUP_BASE+LPC43_REGFILE30_OFFSET)
+#define LPC43_REGFILE31         (LPC43_BACKUP_BASE+LPC43_REGFILE31_OFFSET)
+#define LPC43_REGFILE32         (LPC43_BACKUP_BASE+LPC43_REGFILE32_OFFSET)
+#define LPC43_REGFILE33         (LPC43_BACKUP_BASE+LPC43_REGFILE33_OFFSET)
+#define LPC43_REGFILE34         (LPC43_BACKUP_BASE+LPC43_REGFILE34_OFFSET)
+#define LPC43_REGFILE35         (LPC43_BACKUP_BASE+LPC43_REGFILE35_OFFSET)
+#define LPC43_REGFILE36         (LPC43_BACKUP_BASE+LPC43_REGFILE36_OFFSET)
+#define LPC43_REGFILE37         (LPC43_BACKUP_BASE+LPC43_REGFILE37_OFFSET)
+#define LPC43_REGFILE38         (LPC43_BACKUP_BASE+LPC43_REGFILE38_OFFSET)
+#define LPC43_REGFILE39         (LPC43_BACKUP_BASE+LPC43_REGFILE39_OFFSET)
+#define LPC43_REGFILE40         (LPC43_BACKUP_BASE+LPC43_REGFILE40_OFFSET)
+#define LPC43_REGFILE41         (LPC43_BACKUP_BASE+LPC43_REGFILE41_OFFSET)
+#define LPC43_REGFILE42         (LPC43_BACKUP_BASE+LPC43_REGFILE42_OFFSET)
+#define LPC43_REGFILE43         (LPC43_BACKUP_BASE+LPC43_REGFILE43_OFFSET)
+#define LPC43_REGFILE44         (LPC43_BACKUP_BASE+LPC43_REGFILE44_OFFSET)
+#define LPC43_REGFILE45         (LPC43_BACKUP_BASE+LPC43_REGFILE45_OFFSET)
+#define LPC43_REGFILE46         (LPC43_BACKUP_BASE+LPC43_REGFILE46_OFFSET)
+#define LPC43_REGFILE47         (LPC43_BACKUP_BASE+LPC43_REGFILE47_OFFSET)
+#define LPC43_REGFILE48         (LPC43_BACKUP_BASE+LPC43_REGFILE48_OFFSET)
+#define LPC43_REGFILE49         (LPC43_BACKUP_BASE+LPC43_REGFILE49_OFFSET)
+#define LPC43_REGFILE50         (LPC43_BACKUP_BASE+LPC43_REGFILE50_OFFSET)
+#define LPC43_REGFILE51         (LPC43_BACKUP_BASE+LPC43_REGFILE51_OFFSET)
+#define LPC43_REGFILE52         (LPC43_BACKUP_BASE+LPC43_REGFILE52_OFFSET)
+#define LPC43_REGFILE53         (LPC43_BACKUP_BASE+LPC43_REGFILE53_OFFSET)
+#define LPC43_REGFILE54         (LPC43_BACKUP_BASE+LPC43_REGFILE54_OFFSET)
+#define LPC43_REGFILE55         (LPC43_BACKUP_BASE+LPC43_REGFILE55_OFFSET)
+#define LPC43_REGFILE56         (LPC43_BACKUP_BASE+LPC43_REGFILE56_OFFSET)
+#define LPC43_REGFILE57         (LPC43_BACKUP_BASE+LPC43_REGFILE57_OFFSET)
+#define LPC43_REGFILE58         (LPC43_BACKUP_BASE+LPC43_REGFILE58_OFFSET)
+#define LPC43_REGFILE59         (LPC43_BACKUP_BASE+LPC43_REGFILE59_OFFSET)
+#define LPC43_REGFILE60         (LPC43_BACKUP_BASE+LPC43_REGFILE60_OFFSET)
+#define LPC43_REGFILE61         (LPC43_BACKUP_BASE+LPC43_REGFILE61_OFFSET)
+#define LPC43_REGFILE62         (LPC43_BACKUP_BASE+LPC43_REGFILE62_OFFSET)
+#define LPC43_REGFILE63         (LPC43_BACKUP_BASE+LPC43_REGFILE63_OFFSET)
+
+/* Register bit definitions *********************************************************/
+/* Miscellaneous registers */
+/* Interrupt Location Register */
+
+#define RTC_ILR_RTCCIF          (1 << 0)  /* Bit 0:  Counter Increment Interrupt */
+#define RTC_ILR_RTCALF          (1 << 1)  /* Bit 1:  Alarm interrupt */
+                                          /* Bits 2-31: Reserved */
+/* Clock Control Register */
+
+#define RTC_CCR_CLKEN           (1 << 0)  /* Bit 0:  Clock Enable */
+#define RTC_CCR_CTCRST          (1 << 1)  /* Bit 1:  CTC Reset */
+                                          /* Bits 2-3: Internal test mode controls */
+#define RTC_CCR_CCALEN          (1 << 4)  /* Bit 4:  Calibration counter enable */
+                                          /* Bits 5-31: Reserved */
+/* Counter Increment Interrupt Register */
+
+#define RTC_CIIR_IMSEC          (1 << 0)  /* Bit 0:  Second interrupt */
+#define RTC_CIIR_IMMIN          (1 << 1)  /* Bit 1:  Minute interrupt */
+#define RTC_CIIR_IMHOUR         (1 << 2)  /* Bit 2:  Hour interrupt */
+#define RTC_CIIR_IMDOM          (1 << 3)  /* Bit 3:  Day of Month value interrupt */
+#define RTC_CIIR_IMDOW          (1 << 4)  /* Bit 4:  Day of Week value interrupt */
+#define RTC_CIIR_IMDOY          (1 << 5)  /* Bit 5:  Day of Year interrupt */
+#define RTC_CIIR_IMMON          (1 << 6)  /* Bit 6:  Month interrupt */
+#define RTC_CIIR_IMYEAR         (1 << 7)  /* Bit 7:  Yearinterrupt */
+                                          /* Bits 8-31: Reserved */
+/* Alarm Mask Register */
+
+#define RTC_AMR_SEC             (1 << 0)  /* Bit 0:  Second not compared for alarm */
+#define RTC_AMR_MIN             (1 << 1)  /* Bit 1:  Minutes not compared for alarm */
+#define RTC_AMR_HOUR            (1 << 2)  /* Bit 2:  Hour not compared for alarm */
+#define RTC_AMR_DOM             (1 << 3)  /* Bit 3:  Day of Monthnot compared for alarm */
+#define RTC_AMR_DOW             (1 << 4)  /* Bit 4:  Day of Week not compared for alarm */
+#define RTC_AMR_DOY             (1 << 5)  /* Bit 5:  Day of Year not compared for alarm */
+#define RTC_AMR_MON             (1 << 6)  /* Bit 6:  Month not compared for alarm */
+#define RTC_AMR_YEAR            (1 << 7)  /* Bit 7:  Year not compared for alarm */
+                                          /* Bits 8-31: Reserved */
+/* Consolidated time registers */
+/* Consolidated Time Register 0 */
+
+#define RTC_CTIME0_SEC_SHIFT    (0)       /* Bits 0-5: Seconds */
+#define RTC_CTIME0_SEC_MASK     (63 << RTC_CTIME0_SEC_SHIFT)
+                                          /* Bits 6-7: Reserved */
+#define RTC_CTIME0_MIN_SHIFT    (8)       /* Bits 8-13: Minutes */
+#define RTC_CTIME0_MIN_MASK     (63 << RTC_CTIME0_MIN_SHIFT)
+                                          /* Bits 14-15: Reserved */
+#define RTC_CTIME0_HOURS_SHIFT  (16)      /* Bits 16-20: Hours */
+#define RTC_CTIME0_HOURS_MASK   (31 << RTC_CTIME0_HOURS_SHIFT)
+                                          /* Bits 21-23: Reserved */
+#define RTC_CTIME0_DOW_SHIFT    (24)      /* Bits 24-26: Day of Week */
+#define RTC_CTIME0_DOW_MASK     (7 << RTC_CTIME0_DOW_SHIFT)
+                                          /* Bits 27-31: Reserved */
+/* Consolidated Time Register 1 */
+
+#define RTC_CTIME1_DOM_SHIFT    (0)       /* Bits 0-4: Day of Month */
+#define RTC_CTIME1_DOM_MASK     (31 << RTC_CTIME1_DOM_SHIFT)
+                                          /* Bits 5-7: Reserved */
+#define RTC_CTIME1_MON_SHIFT    (8)       /* Bits 8-11: Month */
+#define RTC_CTIME1_MON_MASK     (15 << RTC_CTIME1_MON_SHIFT)
+                                          /* Bits 12-15: Reserved */
+#define RTC_CTIME1_YEAR_SHIFT   (16)      /* Bits 16-27: Year */
+#define RTC_CTIME1_YEAR_MASK    (0x0fff << RTC_CTIME1_YEAR_SHIFT)
+                                          /* Bits 28-31: Reserved */
+/* Consolidated Time Register 2 */
+
+#define RTC_CTIME2_DOY_SHIFT    (0)       /* Bits 0-11: Day of Year */
+#define RTC_CTIME2_DOY_MASK     (0x0fff << RTC_CTIME2_DOY_SHIFT)
+                                          /* Bits 12-31: Reserved */
+/* Time counter registers */
+
+#define RTC_SEC_MASK            (0x003f)
+#define RTC_MIN_MASK            (0x003f)
+#define RTC_HOUR_MASK           (0x001f)
+#define RTC_DOM_MASK            (0x001f)
+#define RTC_DOW_MASK            (0x0007)
+#define RTC_DOY_MASK            (0x01ff)
+#define RTC_MONTH_MASK          (0x000f)
+#define RTC_YEAR_MASK           (0x0fff)
+
+/* Calibration Value Register */
+
+#define RTC_CALIB_CALVAL_SHIFT  (0)       /* Bits 0-16: calibration counter counts to this value */
+#define RTC_CALIB_CALVAL_MASK   (0xffff << RTC_CALIB_CALVAL_SHIFT)
+#define RTC_CALIB_CALDIR        (1 << 17) /* Bit 17: Calibration direction */
+                                          /* Bits 18-31: Reserved */
+/* Alarm register group */
+
+#define RTC_ASEC_MASK           (0x003f)
+#define RTC_AMIN_MASK           (0x003f)
+#define RTC_AHOUR_MASK          (0x001f)
+#define RTC_ADOM_MASK           (0x001f)
+#define RTC_ADOW_MASK           (0x0007)
+#define RTC_ADOY_MASK           (0x01ff)
+#define RTC_AMON_MASK           (0x000f)
+#define RTC_AYEAR_MASK          (0x0fff)
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_LPC43XX_LPC43_RTC_H */
diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_sct.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_sct.h
new file mode 100644
index 000000000..d93db2834
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_sct.h
@@ -0,0 +1,1593 @@
+/****************************************************************************************************
+ * arch/arm/src/lpc43xx/chip/lpc43_sct.h
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_SCT_H
+#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_SCT_H
+
+/****************************************************************************************************
+ * Included Files
+ ****************************************************************************************************/
+
+#include <nuttx/config.h>
+
+/****************************************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************************************/
+/* Register Offsets *********************************************************************************/
+
+#define LPC43_SCT_CONFIG_OFFSET     0x0000 /* SCT configuration register */
+#define LPC43_SCT_CTRL_OFFSET       0x0004 /* SCT control register */
+#define LPC43_SCT_CTRLL_OFFSET      0x0004 /* SCT control register low 16-bit */
+#define LPC43_SCT_CTRLH_OFFSET      0x0006 /* SCT control register high 16-bit */
+#define LPC43_SCT_LIMIT_OFFSET      0x0008 /* SCT limit register */
+#define LPC43_SCT_LIMITL_OFFSET     0x0008 /* SCT limit register low 16-bit */
+#define LPC43_SCT_LIMITH_OFFSET     0x000a /* SCT limit register high 16-bit */
+#define LPC43_SCT_HALT_OFFSET       0x000c /* SCT halt condition register */
+#define LPC43_SCT_HALTL_OFFSET      0x000c /* SCT halt condition register low 16-bit */
+#define LPC43_SCT_HALTH_OFFSET      0x000e /* SCT halt condition register high 16-bit */
+#define LPC43_SCT_STOP_OFFSET       0x0010 /* SCT stop condition register */
+#define LPC43_SCT_STOPL_OFFSET      0x0010 /* SCT stop condition register low 16-bit */
+#define LPC43_SCT_STOPH_OFFSET      0x0012 /* SCT stop condition register high 16-bit */
+#define LPC43_SCT_START_OFFSET      0x0014 /* SCT start condition register */
+#define LPC43_SCT_STARTL_OFFSET     0x0014 /* SCT start condition register low 16-bit */
+#define LPC43_SCT_STARTH_OFFSET     0x0016 /* SCT start condition register high 16-bit */
+
+#define LPC43_SCT_COUNT_OFFSET      0x0040 /* SCT counter register */
+#define LPC43_SCT_COUNTL_OFFSET     0x0040 /* SCT counter register low 16-bit */
+#define LPC43_SCT_COUNTH_OFFSET     0x0042 /* SCT counter register high 16-bit */
+#define LPC43_SCT_STATE_OFFSET      0x0044 /* SCT state register */
+#define LPC43_SCT_STATEL_OFFSET     0x0044 /* SCT state register low 16-bit */
+#define LPC43_SCT_STATEH_OFFSET     0x0046 /* SCT state register high 16-bit */
+#define LPC43_SCT_INPUT_OFFSET      0x0048 /* SCT input register */
+#define LPC43_SCT_REGM_OFFSET       0x004c /* SCT match/capture registers mode register */
+#define LPC43_SCT_REGML_OFFSET      0x004c /* SCT match/capture registers mode register low 16-bit */
+#define LPC43_SCT_REGMH_OFFSET      0x004e /* SCT match/capture registers mode register high 16-bit */
+#define LPC43_SCT_OUT_OFFSET        0x0050 /* SCT output register */
+#define LPC43_SCT_OUTDIRC_OFFSET    0x0054 /* SCT output counter direction control register */
+#define LPC43_SCT_RES_OFFSET        0x0058 /* SCT conflict resolution register */
+#define LPC43_SCT_DMAREQ0_OFFSET    0x005c /* SCT DMA request 0 register */
+#define LPC43_SCT_DMAREQ1_OFFSET    0x0060 /* SCT DMA request 1 register */
+
+#define LPC43_SCT_EVEN_OFFSET       0x00f0 /* SCT event enable register */
+#define LPC43_SCT_EVFLAG_OFFSET     0x00f4 /* SCT event flag register */
+#define LPC43_SCT_CONEN_OFFSET      0x00f8 /* SCT conflict enable register */
+#define LPC43_SCT_CONFLAG_OFFSET    0x00fC /* SCT conflict flag register */
+
+#define LPC43_SCT_MATCH_OFFSET(n)   (0x0100 + ((n) << 4)) /* n = 0..15 */
+#define LPC43_SCT_MATCH0_OFFSET     0x0100 /* SCT match value register of match channel 0 */
+#define LPC43_SCT_MATCH1_OFFSET     0x0104 /* SCT match value register of match channel 1 */
+#define LPC43_SCT_MATCH2_OFFSET     0x0108 /* SCT match value register of match channel 2 */
+#define LPC43_SCT_MATCH3_OFFSET     0x010c /* SCT match value register of match channel 3 */
+#define LPC43_SCT_MATCH4_OFFSET     0x0110 /* SCT match value register of match channel 4 */
+#define LPC43_SCT_MATCH5_OFFSET     0x0114 /* SCT match value register of match channel 5 */
+#define LPC43_SCT_MATCH6_OFFSET     0x0118 /* SCT match value register of match channel 6 */
+#define LPC43_SCT_MATCH7_OFFSET     0x011c /* SCT match value register of match channel 7 */
+#define LPC43_SCT_MATCH8_OFFSET     0x0120 /* SCT match value register of match channel 8 */
+#define LPC43_SCT_MATCH9_OFFSET     0x0124 /* SCT match value register of match channel 9 */
+#define LPC43_SCT_MATCH10_OFFSET    0x0128 /* SCT match value register of match channel 10 */
+#define LPC43_SCT_MATCH11_OFFSET    0x012c /* SCT match value register of match channel 11 */
+#define LPC43_SCT_MATCH12_OFFSET    0x0130 /* SCT match value register of match channel 12 */
+#define LPC43_SCT_MATCH13_OFFSET    0x0134 /* SCT match value register of match channel 13 */
+#define LPC43_SCT_MATCH14_OFFSET    0x0138 /* SCT match value register of match channel 14 */
+#define LPC43_SCT_MATCH15_OFFSET    0x013c /* SCT match value register of match channel 15 */
+
+#define LPC43_SCT_MATCHL_OFFSET(n) (0x0100 + ((n) << 4)) /* n = 0..15 */
+#define LPC43_SCT_MATCH0L_OFFSET    0x0100 /* SCT match value register of match channel 0; low 16-bit */
+#define LPC43_SCT_MATCH1L_OFFSET    0x0104 /* SCT match value register of match channel 1; low 16-bit */
+#define LPC43_SCT_MATCH2L_OFFSET    0x0108 /* SCT match value register of match channel 2; low 16-bit */
+#define LPC43_SCT_MATCH3L_OFFSET    0x010c /* SCT match value register of match channel 3; low 16-bit */
+#define LPC43_SCT_MATCH4L_OFFSET    0x0110 /* SCT match value register of match channel 4; low 16-bit */
+#define LPC43_SCT_MATCH5L_OFFSET    0x0114 /* SCT match value register of match channel 5; low 16-bit */
+#define LPC43_SCT_MATCH6L_OFFSET    0x0118 /* SCT match value register of match channel 6; low 16-bit */
+#define LPC43_SCT_MATCH7L_OFFSET    0x011c /* SCT match value register of match channel 7; low 16-bit */
+#define LPC43_SCT_MATCH8L_OFFSET    0x0120 /* SCT match value register of match channel 8; low 16-bit */
+#define LPC43_SCT_MATCH9L_OFFSET    0x0124 /* SCT match value register of match channel 9; low 16-bit */
+#define LPC43_SCT_MATCH10L_OFFSET   0x0128 /* SCT match value register of match channel 10; low 16-bit */
+#define LPC43_SCT_MATCH11L_OFFSET   0x012c /* SCT match value register of match channel 11; low 16-bit */
+#define LPC43_SCT_MATCH12L_OFFSET   0x0130 /* SCT match value register of match channel 12; low 16-bit */
+#define LPC43_SCT_MATCH13L_OFFSET   0x0134 /* SCT match value register of match channel 13; low 16-bit */
+#define LPC43_SCT_MATCH14L_OFFSET   0x0138 /* SCT match value register of match channel 14; low 16-bit */
+#define LPC43_SCT_MATCH15L_OFFSET   0x013c /* SCT match value register of match channel 15; low 16-bit */
+
+#define LPC43_SCT_MATCHH_OFFSET(n)  (0x0102 + ((n) << 4)) /* n = 0..15 */
+#define LPC43_SCT_MATCH0H_OFFSET    0x0102 /* SCT match value register of match channel 0; high 16-bit */
+#define LPC43_SCT_MATCH1H_OFFSET    0x0106 /* SCT match value register of match channel 1; high 16-bit */
+#define LPC43_SCT_MATCH2H_OFFSET    0x010a /* SCT match value register of match channel 2; high 16-bit */
+#define LPC43_SCT_MATCH3H_OFFSET    0x010e /* SCT match value register of match channel 3; high 16-bit */
+#define LPC43_SCT_MATCH4H_OFFSET    0x0112 /* SCT match value register of match channel 4; high 16-bit */
+#define LPC43_SCT_MATCH5H_OFFSET    0x0116 /* SCT match value register of match channel 5; high 16-bit */
+#define LPC43_SCT_MATCH6H_OFFSET    0x011a /* SCT match value register of match channel 6; high 16-bit */
+#define LPC43_SCT_MATCH7H_OFFSET    0x011e /* SCT match value register of match channel 7; high 16-bit */
+#define LPC43_SCT_MATCH8H_OFFSET    0x0122 /* SCT match value register of match channel 8; high 16-bit */
+#define LPC43_SCT_MATCH9H_OFFSET    0x0126 /* SCT match value register of match channel 9; high 16-bit */
+#define LPC43_SCT_MATCH10H_OFFSET   0x012a /* SCT match value register of match channel 10; high 16-bit */
+#define LPC43_SCT_MATCH11H_OFFSET   0x012e /* SCT match value register of match channel 11; high 16-bit */
+#define LPC43_SCT_MATCH12H_OFFSET   0x0132 /* SCT match value register of match channel 12; high 16-bit */
+#define LPC43_SCT_MATCH13H_OFFSET   0x0136 /* SCT match value register of match channel 13; high 16-bit */
+#define LPC43_SCT_MATCH14H_OFFSET   0x013a /* SCT match value register of match channel 14; high 16-bit */
+#define LPC43_SCT_MATCH15H_OFFSET   0x013e /* SCT match value register of match channel 15; high 16-bit */
+
+#define LPC43_SCT_CAP_OFFSET(n)     (0x0100 + ((n) << 4)) /* n = 0..15 */
+#define LPC43_SCT_CAP0_OFFSET       0x0100 /* SCT capture value register Ch0 */
+#define LPC43_SCT_CAP1_OFFSET       0x0104 /* SCT capture value register Ch1 */
+#define LPC43_SCT_CAP2_OFFSET       0x0108 /* SCT capture value register Ch2 */
+#define LPC43_SCT_CAP3_OFFSET       0x010c /* SCT capture value register Ch3 */
+#define LPC43_SCT_CAP4_OFFSET       0x0110 /* SCT capture value register Ch4 */
+#define LPC43_SCT_CAP5_OFFSET       0x0114 /* SCT capture value register Ch5 */
+#define LPC43_SCT_CAP6_OFFSET       0x0118 /* SCT capture value register Ch6 */
+#define LPC43_SCT_CAP7_OFFSET       0x011c /* SCT capture value register Ch7 */
+#define LPC43_SCT_CAP8_OFFSET       0x0120 /* SCT capture value register Ch8 */
+#define LPC43_SCT_CAP9_OFFSET       0x0124 /* SCT capture value register Ch9 */
+#define LPC43_SCT_CAP10_OFFSET      0x0128 /* SCT capture value register Ch10 */
+#define LPC43_SCT_CAP11_OFFSET      0x012c /* SCT capture value register Ch11 */
+#define LPC43_SCT_CAP12_OFFSET      0x0130 /* SCT capture value register Ch12 */
+#define LPC43_SCT_CAP13_OFFSET      0x0134 /* SCT capture value register Ch13 */
+#define LPC43_SCT_CAP14_OFFSET      0x0138 /* SCT capture value register Ch14 */
+#define LPC43_SCT_CAP15_OFFSET      0x013c /* SCT capture value register Ch15 */
+
+#define LPC43_SCT_CAPL_OFFSET(n)    (0x0100 + ((n) << 4)) /* n = 0..15 */
+#define LPC43_SCT_CAP0L_OFFSET      0x0100 /* SCT capture value register Ch0; low 16-bit */
+#define LPC43_SCT_CAP1L_OFFSET      0x0104 /* SCT capture value register Ch1; low 16-bit */
+#define LPC43_SCT_CAP2L_OFFSET      0x0108 /* SCT capture value register Ch2; low 16-bit */
+#define LPC43_SCT_CAP3L_OFFSET      0x010c /* SCT capture value register Ch3; low 16-bit */
+#define LPC43_SCT_CAP4L_OFFSET      0x0110 /* SCT capture value register Ch4; low 16-bit */
+#define LPC43_SCT_CAP5L_OFFSET      0x0114 /* SCT capture value register Ch5; low 16-bit */
+#define LPC43_SCT_CAP6L_OFFSET      0x0118 /* SCT capture value register Ch6; low 16-bit */
+#define LPC43_SCT_CAP7L_OFFSET      0x011c /* SCT capture value register Ch7; low 16-bit */
+#define LPC43_SCT_CAP8L_OFFSET      0x0120 /* SCT capture value register Ch8; low 16-bit */
+#define LPC43_SCT_CAP9L_OFFSET      0x0124 /* SCT capture value register Ch9; low 16-bit */
+#define LPC43_SCT_CAP10L_OFFSET     0x0128 /* SCT capture value register Ch10; low 16-bit */
+#define LPC43_SCT_CAP11L_OFFSET     0x012c /* SCT capture value register Ch11; low 16-bit */
+#define LPC43_SCT_CAP12L_OFFSET     0x0130 /* SCT capture value register Ch12; low 16-bit */
+#define LPC43_SCT_CAP13L_OFFSET     0x0134 /* SCT capture value register Ch13; low 16-bit */
+#define LPC43_SCT_CAP14L_OFFSET     0x0138 /* SCT capture value register Ch14; low 16-bit */
+#define LPC43_SCT_CAP15L_OFFSET     0x013c /* SCT capture value register Ch15; low 16-bit */
+
+#define LPC43_SCT_CAPH_OFFSET(n)    (0x0102 + ((n) << 4)) /* n = 0..15 */
+#define LPC43_SCT_CAP0H_OFFSET      0x0102 /* SCT capture value register Ch0; high 16-bit */
+#define LPC43_SCT_CAP1H_OFFSET      0x0106 /* SCT capture value register Ch1; high 16-bit */
+#define LPC43_SCT_CAP2H_OFFSET      0x010a /* SCT capture value register Ch2; high 16-bit */
+#define LPC43_SCT_CAP3H_OFFSET      0x010e /* SCT capture value register Ch3; high 16-bit */
+#define LPC43_SCT_CAP4H_OFFSET      0x0112 /* SCT capture value register Ch4; high 16-bit */
+#define LPC43_SCT_CAP5H_OFFSET      0x0116 /* SCT capture value register Ch5; high 16-bit */
+#define LPC43_SCT_CAP6H_OFFSET      0x011a /* SCT capture value register Ch6; high 16-bit */
+#define LPC43_SCT_CAP7H_OFFSET      0x011e /* SCT capture value register Ch7; high 16-bit */
+#define LPC43_SCT_CAP8H_OFFSET      0x0122 /* SCT capture value register Ch8; high 16-bit */
+#define LPC43_SCT_CAP9H_OFFSET      0x0126 /* SCT capture value register Ch9; high 16-bit */
+#define LPC43_SCT_CAP10H_OFFSET     0x012a /* SCT capture value register Ch10; high 16-bit */
+#define LPC43_SCT_CAP11H_OFFSET     0x012e /* SCT capture value register Ch11; high 16-bit */
+#define LPC43_SCT_CAP12H_OFFSET     0x0132 /* SCT capture value register Ch12; high 16-bit */
+#define LPC43_SCT_CAP13H_OFFSET     0x0136 /* SCT capture value register Ch13; high 16-bit */
+#define LPC43_SCT_CAP14H_OFFSET     0x013a /* SCT capture value register Ch14; high 16-bit */
+#define LPC43_SCT_CAP15H_OFFSET     0x013e /* SCT capture value register Ch15; high 16-bit */
+
+#define LPC43_SCT_MATCHA_OFFSET(n)  (0x0180 + ((n) << 4)) /* n = 0..15 */
+#define LPC43_SCT_MATCH0A_OFFSET    0x0180 /* SCT match alias register of match channel 0 */
+#define LPC43_SCT_MATCH1A_OFFSET    0x0184 /* SCT match alias register of match channel 1 */
+#define LPC43_SCT_MATCH2A_OFFSET    0x0188 /* SCT match alias register of match channel 2 */
+#define LPC43_SCT_MATCH3A_OFFSET    0x018c /* SCT match alias register of match channel 3 */
+#define LPC43_SCT_MATCH4A_OFFSET    0x0190 /* SCT match alias register of match channel 4 */
+#define LPC43_SCT_MATCH5A_OFFSET    0x0194 /* SCT match alias register of match channel 5 */
+#define LPC43_SCT_MATCH6A_OFFSET    0x0198 /* SCT match alias register of match channel 6 */
+#define LPC43_SCT_MATCH7A_OFFSET    0x019c /* SCT match alias register of match channel 7 */
+#define LPC43_SCT_MATCH8A_OFFSET    0x01a0 /* SCT match alias register of match channel 8 */
+#define LPC43_SCT_MATCH9A_OFFSET    0x01a4 /* SCT match alias register of match channel 9 */
+#define LPC43_SCT_MATCH10A_OFFSET   0x01a8 /* SCT match alias register of match channel 10 */
+#define LPC43_SCT_MATCH11A_OFFSET   0x01ac /* SCT match alias register of match channel 11 */
+#define LPC43_SCT_MATCH12A_OFFSET   0x01b0 /* SCT match alias register of match channel 12 */
+#define LPC43_SCT_MATCH13A_OFFSET   0x01b4 /* SCT match alias register of match channel 13 */
+#define LPC43_SCT_MATCH14A_OFFSET   0x01b8 /* SCT match alias register of match channel 14 */
+#define LPC43_SCT_MATCH15A_OFFSET   0x01bc /* SCT match alias register of match channel 15 */
+
+#define LPC43_SCT_MATCHLA_OFFSET(n) (0x0180 + ((n) << 4)) /* n = 0..15 */
+#define LPC43_SCT_MATCH0LA_OFFSET   0x0180 /* SCT match alias register of match channel 0; low 16-bit */
+#define LPC43_SCT_MATCH1LA_OFFSET   0x0184 /* SCT match alias register of match channel 1; low 16-bit */
+#define LPC43_SCT_MATCH2LA_OFFSET   0x0188 /* SCT match alias register of match channel 2; low 16-bit */
+#define LPC43_SCT_MATCH3LA_OFFSET   0x018c /* SCT match alias register of match channel 3; low 16-bit */
+#define LPC43_SCT_MATCH4LA_OFFSET   0x0190 /* SCT match alias register of match channel 4; low 16-bit */
+#define LPC43_SCT_MATCH5LA_OFFSET   0x0194 /* SCT match alias register of match channel 5; low 16-bit */
+#define LPC43_SCT_MATCH6LA_OFFSET   0x0198 /* SCT match alias register of match channel 6; low 16-bit */
+#define LPC43_SCT_MATCH7LA_OFFSET   0x019c /* SCT match alias register of match channel 7; low 16-bit */
+#define LPC43_SCT_MATCH8LA_OFFSET   0x01a0 /* SCT match alias register of match channel 8; low 16-bit */
+#define LPC43_SCT_MATCH9LA_OFFSET   0x01a4 /* SCT match alias register of match channel 9; low 16-bit */
+#define LPC43_SCT_MATCH10LA_OFFSET  0x01a8 /* SCT match alias register of match channel 10; low 16-bit */
+#define LPC43_SCT_MATCH11LA_OFFSET  0x01ac /* SCT match alias register of match channel 11; low 16-bit */
+#define LPC43_SCT_MATCH12LA_OFFSET  0x01b0 /* SCT match alias register of match channel 12; low 16-bit */
+#define LPC43_SCT_MATCH13LA_OFFSET  0x01b4 /* SCT match alias register of match channel 13; low 16-bit */
+#define LPC43_SCT_MATCH14LA_OFFSET  0x01b8 /* SCT match alias register of match channel 14; low 16-bit */
+#define LPC43_SCT_MATCH15LA_OFFSET  0x01bc /* SCT match alias register of match channel 15; low 16-bit */
+
+#define LPC43_SCT_MATCHHA_OFFSET(n) (0x0182 + ((n) << 4)) /* n = 0..15 */
+#define LPC43_SCT_MATCH0HA_OFFSET   0x0182 /* SCT match alias register of match channel 0; high 16-bit */
+#define LPC43_SCT_MATCH1HA_OFFSET   0x0186 /* SCT match alias register of match channel 1; high 16-bit */
+#define LPC43_SCT_MATCH2HA_OFFSET   0x018a /* SCT match alias register of match channel 2; high 16-bit */
+#define LPC43_SCT_MATCH3HA_OFFSET   0x018e /* SCT match alias register of match channel 3; high 16-bit */
+#define LPC43_SCT_MATCH4HA_OFFSET   0x0192 /* SCT match alias register of match channel 4; high 16-bit */
+#define LPC43_SCT_MATCH5HA_OFFSET   0x0196 /* SCT match alias register of match channel 5; high 16-bit */
+#define LPC43_SCT_MATCH6HA_OFFSET   0x019a /* SCT match alias register of match channel 6; high 16-bit */
+#define LPC43_SCT_MATCH7HA_OFFSET   0x019e /* SCT match alias register of match channel 7; high 16-bit */
+#define LPC43_SCT_MATCH8HA_OFFSET   0x01a2 /* SCT match alias register of match channel 8; high 16-bit */
+#define LPC43_SCT_MATCH9HA_OFFSET   0x01a6 /* SCT match alias register of match channel 9; high 16-bit */
+#define LPC43_SCT_MATCH10HA_OFFSET  0x01aa /* SCT match alias register of match channel 10; high 16-bit */
+#define LPC43_SCT_MATCH11HA_OFFSET  0x01ae /* SCT match alias register of match channel 11; high 16-bit */
+#define LPC43_SCT_MATCH12HA_OFFSET  0x01b2 /* SCT match alias register of match channel 12; high 16-bit */
+#define LPC43_SCT_MATCH13HA_OFFSET  0x01b6 /* SCT match alias register of match channel 13; high 16-bit */
+#define LPC43_SCT_MATCH14HA_OFFSET  0x01ba /* SCT match alias register of match channel 14; high 16-bit */
+#define LPC43_SCT_MATCH15HA_OFFSET  0x01be /* SCT match alias register of match channel 15; high 16-bit */
+
+#define LPC43_SCT_CAPA_OFFSET(n)    (0x0180 + ((n) << 4)) /* n = 0..15 */
+#define LPC43_SCT_CAP0A_OFFSET      0x0180 /* SCT capture alias register Ch0 */
+#define LPC43_SCT_CAP1A_OFFSET      0x0184 /* SCT capture alias register Ch1 */
+#define LPC43_SCT_CAP2A_OFFSET      0x0188 /* SCT capture alias register Ch2 */
+#define LPC43_SCT_CAP3A_OFFSET      0x018c /* SCT capture alias register Ch3 */
+#define LPC43_SCT_CAP4A_OFFSET      0x0190 /* SCT capture alias register Ch4 */
+#define LPC43_SCT_CAP5A_OFFSET      0x0194 /* SCT capture alias register Ch5 */
+#define LPC43_SCT_CAP6A_OFFSET      0x0198 /* SCT capture alias register Ch6 */
+#define LPC43_SCT_CAP7A_OFFSET      0x019c /* SCT capture alias register Ch7 */
+#define LPC43_SCT_CAP8A_OFFSET      0x01a0 /* SCT capture alias register Ch8 */
+#define LPC43_SCT_CAP9A_OFFSET      0x01a4 /* SCT capture alias register Ch9 */
+#define LPC43_SCT_CAP10A_OFFSET     0x01a8 /* SCT capture alias register Ch10 */
+#define LPC43_SCT_CAP11A_OFFSET     0x01ac /* SCT capture alias register Ch11 */
+#define LPC43_SCT_CAP12A_OFFSET     0x01b0 /* SCT capture alias register Ch12 */
+#define LPC43_SCT_CAP13A_OFFSET     0x01b4 /* SCT capture alias register Ch13 */
+#define LPC43_SCT_CAP14A_OFFSET     0x01b8 /* SCT capture alias register Ch14 */
+#define LPC43_SCT_CAP15A_OFFSET     0x01bc /* SCT capture alias register Ch15 */
+
+#define LPC43_SCT_CAPLA_OFFSET(n)   (0x0180 + ((n) << 4)) /* n = 0..15 */
+#define LPC43_SCT_CAP0LA_OFFSET     0x0180 /* SCT capture alias register Ch0; low 16-bit */
+#define LPC43_SCT_CAP1LA_OFFSET     0x0184 /* SCT capture alias register Ch1; low 16-bit */
+#define LPC43_SCT_CAP2LA_OFFSET     0x0188 /* SCT capture alias register Ch2; low 16-bit */
+#define LPC43_SCT_CAP3LA_OFFSET     0x018c /* SCT capture alias register Ch3; low 16-bit */
+#define LPC43_SCT_CAP4LA_OFFSET     0x0190 /* SCT capture alias register Ch4; low 16-bit */
+#define LPC43_SCT_CAP5LA_OFFSET     0x0194 /* SCT capture alias register Ch5; low 16-bit */
+#define LPC43_SCT_CAP6LA_OFFSET     0x0198 /* SCT capture alias register Ch6; low 16-bit */
+#define LPC43_SCT_CAP7LA_OFFSET     0x019c /* SCT capture alias register Ch7; low 16-bit */
+#define LPC43_SCT_CAP8LA_OFFSET     0x01a0 /* SCT capture alias register Ch8; low 16-bit */
+#define LPC43_SCT_CAP9LA_OFFSET     0x01a4 /* SCT capture alias register Ch9; low 16-bit */
+#define LPC43_SCT_CAP10LA_OFFSET    0x01a8 /* SCT capture alias register Ch10; low 16-bit */
+#define LPC43_SCT_CAP11LA_OFFSET    0x01ac /* SCT capture alias register Ch11; low 16-bit */
+#define LPC43_SCT_CAP12LA_OFFSET    0x01b0 /* SCT capture alias register Ch12; low 16-bit */
+#define LPC43_SCT_CAP13LA_OFFSET    0x01b4 /* SCT capture alias register Ch13; low 16-bit */
+#define LPC43_SCT_CAP14LA_OFFSET    0x01b8 /* SCT capture alias register Ch14; low 16-bit */
+#define LPC43_SCT_CAP15LA_OFFSET    0x01bc /* SCT capture alias register Ch15; low 16-bit */
+
+#define LPC43_SCT_CAPHA_OFFSET(n)   (0x0182 + ((n) << 4)) /* n = 0..15 */
+#define LPC43_SCT_CAP0HA_OFFSET     0x0182 /* SCT capture alias register Ch0; high 16-bit */
+#define LPC43_SCT_CAP1HA_OFFSET     0x0186 /* SCT capture alias register Ch1; high 16-bit */
+#define LPC43_SCT_CAP2HA_OFFSET     0x018a /* SCT capture alias register Ch2; high 16-bit */
+#define LPC43_SCT_CAP3HA_OFFSET     0x018e /* SCT capture alias register Ch3; high 16-bit */
+#define LPC43_SCT_CAP4HA_OFFSET     0x0192 /* SCT capture alias register Ch4; high 16-bit */
+#define LPC43_SCT_CAP5HA_OFFSET     0x0196 /* SCT capture alias register Ch5; high 16-bit */
+#define LPC43_SCT_CAP6HA_OFFSET     0x019a /* SCT capture alias register Ch6; high 16-bit */
+#define LPC43_SCT_CAP7HA_OFFSET     0x019e /* SCT capture alias register Ch7; high 16-bit */
+#define LPC43_SCT_CAP8HA_OFFSET     0x01a2 /* SCT capture alias register Ch8; high 16-bit */
+#define LPC43_SCT_CAP9HA_OFFSET     0x01a6 /* SCT capture alias register Ch9; high 16-bit */
+#define LPC43_SCT_CAP10HA_OFFSET    0x01aa /* SCT capture alias register Ch10; high 16-bit */
+#define LPC43_SCT_CAP11HA_OFFSET    0x01ae /* SCT capture alias register Ch11; high 16-bit */
+#define LPC43_SCT_CAP12HA_OFFSET    0x01b2 /* SCT capture alias register Ch12; high 16-bit */
+#define LPC43_SCT_CAP13HA_OFFSET    0x01b6 /* SCT capture alias register Ch13; high 16-bit */
+#define LPC43_SCT_CAP14HA_OFFSET    0x01ba /* SCT capture alias register Ch14; high 16-bit */
+#define LPC43_SCT_CAP15HA_OFFSET    0x01be /* SCT capture alias register Ch15; high 16-bit */
+
+#define LPC43_SCT_MATCHR_OFFSET(n)  (0x0200 + ((n) << 4)) /* n = 0..15 */
+#define LPC43_SCT_MATCHR0_OFFSET    0x0200 /* SCT match reload register of match channel 0 */
+#define LPC43_SCT_MATCHR1_OFFSET    0x0204 /* SCT match reload register of match channel 1 */
+#define LPC43_SCT_MATCHR2_OFFSET    0x0208 /* SCT match reload register of match channel 2 */
+#define LPC43_SCT_MATCHR3_OFFSET    0x020c /* SCT match reload register of match channel 3 */
+#define LPC43_SCT_MATCHR4_OFFSET    0x0210 /* SCT match reload register of match channel 4 */
+#define LPC43_SCT_MATCHR5_OFFSET    0x0214 /* SCT match reload register of match channel 5 */
+#define LPC43_SCT_MATCHR6_OFFSET    0x0218 /* SCT match reload register of match channel 6 */
+#define LPC43_SCT_MATCHR7_OFFSET    0x021c /* SCT match reload register of match channel 7 */
+#define LPC43_SCT_MATCHR8_OFFSET    0x0220 /* SCT match reload register of match channel 8 */
+#define LPC43_SCT_MATCHR9_OFFSET    0x0224 /* SCT match reload register of match channel 9 */
+#define LPC43_SCT_MATCHR10_OFFSET   0x0228 /* SCT match reload register of match channel 10 */
+#define LPC43_SCT_MATCHR11_OFFSET   0x022c /* SCT match reload register of match channel 11 */
+#define LPC43_SCT_MATCHR12_OFFSET   0x0230 /* SCT match reload register of match channel 12 */
+#define LPC43_SCT_MATCHR13_OFFSET   0x0234 /* SCT match reload register of match channel 13 */
+#define LPC43_SCT_MATCHR14_OFFSET   0x0238 /* SCT match reload register of match channel 14 */
+#define LPC43_SCT_MATCHR15_OFFSET   0x023c /* SCT match reload register of match channel 15 */
+
+#define LPC43_SCT_MATCHRL_OFFSET(n) (0x0200 + ((n) << 4)) /* n = 0..15 */
+#define LPC43_SCT_MATCHR0L_OFFSET   0x0200 /* SCT match reload register of match channel 0; low 16-bit */
+#define LPC43_SCT_MATCHR1L_OFFSET   0x0204 /* SCT match reload register of match channel 1; low 16-bit */
+#define LPC43_SCT_MATCHR2L_OFFSET   0x0208 /* SCT match reload register of match channel 2; low 16-bit */
+#define LPC43_SCT_MATCHR3L_OFFSET   0x020c /* SCT match reload register of match channel 3; low 16-bit */
+#define LPC43_SCT_MATCHR4L_OFFSET   0x0210 /* SCT match reload register of match channel 4; low 16-bit */
+#define LPC43_SCT_MATCHR5L_OFFSET   0x0214 /* SCT match reload register of match channel 5; low 16-bit */
+#define LPC43_SCT_MATCHR6L_OFFSET   0x0218 /* SCT match reload register of match channel 6; low 16-bit */
+#define LPC43_SCT_MATCHR7L_OFFSET   0x021c /* SCT match reload register of match channel 7; low 16-bit */
+#define LPC43_SCT_MATCHR8L_OFFSET   0x0220 /* SCT match reload register of match channel 8; low 16-bit */
+#define LPC43_SCT_MATCHR9L_OFFSET   0x0224 /* SCT match reload register of match channel 9; low 16-bit */
+#define LPC43_SCT_MATCHR10L_OFFSET  0x0228 /* SCT match reload register of match channel 10; low 16-bit */
+#define LPC43_SCT_MATCHR11L_OFFSET  0x022c /* SCT match reload register of match channel 11; low 16-bit */
+#define LPC43_SCT_MATCHR12L_OFFSET  0x0230 /* SCT match reload register of match channel 12; low 16-bit */
+#define LPC43_SCT_MATCHR13L_OFFSET  0x0234 /* SCT match reload register of match channel 13; low 16-bit */
+#define LPC43_SCT_MATCHR14L_OFFSET  0x0238 /* SCT match reload register of match channel 14; low 16-bit */
+#define LPC43_SCT_MATCHR15L_OFFSET  0x023c /* SCT match reload register of match channel 15; low 16-bit */
+
+#define LPC43_SCT_MATCHRH_OFFSET(n) (0x0202 + ((n) << 4)) /* n = 0..15 */
+#define LPC43_SCT_MATCHR0H_OFFSET   0x0202 /* SCT match reload register of match channel 0; high 16-bit */
+#define LPC43_SCT_MATCHR1H_OFFSET   0x0206 /* SCT match reload register of match channel 1; high 16-bit */
+#define LPC43_SCT_MATCHR2H_OFFSET   0x020a /* SCT match reload register of match channel 2; high 16-bit */
+#define LPC43_SCT_MATCHR3H_OFFSET   0x020e /* SCT match reload register of match channel 3; high 16-bit */
+#define LPC43_SCT_MATCHR4H_OFFSET   0x0212 /* SCT match reload register of match channel 4; high 16-bit */
+#define LPC43_SCT_MATCHR5H_OFFSET   0x0216 /* SCT match reload register of match channel 5; high 16-bit */
+#define LPC43_SCT_MATCHR6H_OFFSET   0x021a /* SCT match reload register of match channel 6; high 16-bit */
+#define LPC43_SCT_MATCHR7H_OFFSET   0x021e /* SCT match reload register of match channel 7; high 16-bit */
+#define LPC43_SCT_MATCHR8H_OFFSET   0x0222 /* SCT match reload register of match channel 8; high 16-bit */
+#define LPC43_SCT_MATCHR9H_OFFSET   0x0226 /* SCT match reload register of match channel 9; high 16-bit */
+#define LPC43_SCT_MATCHR10H_OFFSET  0x022a /* SCT match reload register of match channel 10; high 16-bit */
+#define LPC43_SCT_MATCHR11H_OFFSET  0x022e /* SCT match reload register of match channel 11; high 16-bit */
+#define LPC43_SCT_MATCHR12H_OFFSET  0x0232 /* SCT match reload register of match channel 12; high 16-bit */
+#define LPC43_SCT_MATCHR13H_OFFSET  0x0236 /* SCT match reload register of match channel 13; high 16-bit */
+#define LPC43_SCT_MATCHR14H_OFFSET  0x023a /* SCT match reload register of match channel 14; high 16-bit */
+#define LPC43_SCT_MATCHR15H_OFFSET  0x023e /* SCT match reload register of match channel 15; high 16-bit */
+
+#define LPC43_SCT_CAPC_OFFSET(n)    (0x0200 + ((n) << 4)) /* n = 0..15 */
+#define LPC43_SCT_CAPC0_OFFSET      0x0200 /* SCT capture control register Ch0 */
+#define LPC43_SCT_CAPC1_OFFSET      0x0204 /* SCT capture control register Ch1 */
+#define LPC43_SCT_CAPC2_OFFSET      0x0208 /* SCT capture control register Ch2 */
+#define LPC43_SCT_CAPC3_OFFSET      0x020c /* SCT capture control register Ch3 */
+#define LPC43_SCT_CAPC4_OFFSET      0x0210 /* SCT capture control register Ch4 */
+#define LPC43_SCT_CAPC5_OFFSET      0x0214 /* SCT capture control register Ch5 */
+#define LPC43_SCT_CAPC6_OFFSET      0x0218 /* SCT capture control register Ch6 */
+#define LPC43_SCT_CAPC7_OFFSET      0x021c /* SCT capture control register Ch7 */
+#define LPC43_SCT_CAPC8_OFFSET      0x0220 /* SCT capture control register Ch8 */
+#define LPC43_SCT_CAPC9_OFFSET      0x0224 /* SCT capture control register Ch9 */
+#define LPC43_SCT_CAPC10_OFFSET     0x0228 /* SCT capture control register Ch10 */
+#define LPC43_SCT_CAPC11_OFFSET     0x022c /* SCT capture control register Ch11 */
+#define LPC43_SCT_CAPC12_OFFSET     0x0230 /* SCT capture control register Ch12 */
+#define LPC43_SCT_CAPC13_OFFSET     0x0234 /* SCT capture control register Ch13 */
+#define LPC43_SCT_CAPC14_OFFSET     0x0238 /* SCT capture control register Ch14 */
+#define LPC43_SCT_CAPC15_OFFSET     0x023c /* SCT capture control register Ch15 */
+
+#define LPC43_SCT_CAPCL_OFFSET(n)   (0x0200 + ((n) << 4)) /* n = 0..15 */
+#define LPC43_SCT_CAPC0L_OFFSET     0x0200 /* SCT capture control register Ch0; low 16-bit */
+#define LPC43_SCT_CAPC1L_OFFSET     0x0204 /* SCT capture control register Ch1; low 16-bit */
+#define LPC43_SCT_CAPC2L_OFFSET     0x0208 /* SCT capture control register Ch2; low 16-bit */
+#define LPC43_SCT_CAPC3L_OFFSET     0x020c /* SCT capture control register Ch3; low 16-bit */
+#define LPC43_SCT_CAPC4L_OFFSET     0x0210 /* SCT capture control register Ch4; low 16-bit */
+#define LPC43_SCT_CAPC5L_OFFSET     0x0214 /* SCT capture control register Ch5; low 16-bit */
+#define LPC43_SCT_CAPC6L_OFFSET     0x0218 /* SCT capture control register Ch6; low 16-bit */
+#define LPC43_SCT_CAPC7L_OFFSET     0x021c /* SCT capture control register Ch7; low 16-bit */
+#define LPC43_SCT_CAPC8L_OFFSET     0x0220 /* SCT capture control register Ch8; low 16-bit */
+#define LPC43_SCT_CAPC9L_OFFSET     0x0224 /* SCT capture control register Ch9; low 16-bit */
+#define LPC43_SCT_CAPC10L_OFFSET    0x0228 /* SCT capture control register Ch10; low 16-bit */
+#define LPC43_SCT_CAPC11L_OFFSET    0x022c /* SCT capture control register Ch11; low 16-bit */
+#define LPC43_SCT_CAPC12L_OFFSET    0x0230 /* SCT capture control register Ch12; low 16-bit */
+#define LPC43_SCT_CAPC13L_OFFSET    0x0234 /* SCT capture control register Ch13; low 16-bit */
+#define LPC43_SCT_CAPC14L_OFFSET    0x0238 /* SCT capture control register Ch14; low 16-bit */
+#define LPC43_SCT_CAPC15L_OFFSET    0x023c /* SCT capture control register Ch15; low 16-bit */
+
+#define LPC43_SCT_CAPCH_OFFSET(n)   (0x0202 + ((n) << 4)) /* n = 0..15 */
+#define LPC43_SCT_CAPC0H_OFFSET     0x0202 /* SCT capture control register Ch0; high 16-bit */
+#define LPC43_SCT_CAPC1H_OFFSET     0x0206 /* SCT capture control register Ch1; high 16-bit */
+#define LPC43_SCT_CAPC2H_OFFSET     0x020a /* SCT capture control register Ch2; high 16-bit */
+#define LPC43_SCT_CAPC3H_OFFSET     0x020e /* SCT capture control register Ch3; high 16-bit */
+#define LPC43_SCT_CAPC4H_OFFSET     0x0212 /* SCT capture control register Ch4; high 16-bit */
+#define LPC43_SCT_CAPC5H_OFFSET     0x0216 /* SCT capture control register Ch5; high 16-bit */
+#define LPC43_SCT_CAPC6H_OFFSET     0x021a /* SCT capture control register Ch6; high 16-bit */
+#define LPC43_SCT_CAPC7H_OFFSET     0x021e /* SCT capture control register Ch7; high 16-bit */
+#define LPC43_SCT_CAPC8H_OFFSET     0x0222 /* SCT capture control register Ch8; high 16-bit */
+#define LPC43_SCT_CAPC9H_OFFSET     0x0226 /* SCT capture control register Ch9; high 16-bit */
+#define LPC43_SCT_CAPC10H_OFFSET    0x022a /* SCT capture control register Ch10; high 16-bit */
+#define LPC43_SCT_CAPC11H_OFFSET    0x022e /* SCT capture control register Ch11; high 16-bit */
+#define LPC43_SCT_CAPC12H_OFFSET    0x0232 /* SCT capture control register Ch12; high 16-bit */
+#define LPC43_SCT_CAPC13H_OFFSET    0x0236 /* SCT capture control register Ch13; high 16-bit */
+#define LPC43_SCT_CAPC14H_OFFSET    0x023a /* SCT capture control register Ch14; high 16-bit */
+#define LPC43_SCT_CAPC15H_OFFSET    0x023e /* SCT capture control register Ch15; high 16-bit */
+
+#define LPC43_SCT_MATCHRA_OFFSET(n) (0x0280 + ((n) << 4)) /* n = 0..15 */
+#define LPC43_SCT_MATCHR0A_OFFSET   0x0280 /* SCT match reload alias register of match channel 0 */
+#define LPC43_SCT_MATCHR1A_OFFSET   0x0284 /* SCT match reload alias register of match channel 1 */
+#define LPC43_SCT_MATCHR2A_OFFSET   0x0288 /* SCT match reload alias register of match channel 2 */
+#define LPC43_SCT_MATCHR3A_OFFSET   0x028c /* SCT match reload alias register of match channel 3 */
+#define LPC43_SCT_MATCHR4A_OFFSET   0x0290 /* SCT match reload alias register of match channel 4 */
+#define LPC43_SCT_MATCHR5A_OFFSET   0x0294 /* SCT match reload alias register of match channel 5 */
+#define LPC43_SCT_MATCHR6A_OFFSET   0x0298 /* SCT match reload alias register of match channel 6 */
+#define LPC43_SCT_MATCHR7A_OFFSET   0x029c /* SCT match reload alias register of match channel 7 */
+#define LPC43_SCT_MATCHR8A_OFFSET   0x02a0 /* SCT match reload alias register of match channel 8 */
+#define LPC43_SCT_MATCHR9A_OFFSET   0x02a4 /* SCT match reload alias register of match channel 9 */
+#define LPC43_SCT_MATCHR10A_OFFSET  0x02a8 /* SCT match reload alias register of match channel 10 */
+#define LPC43_SCT_MATCHR11A_OFFSET  0x02ac /* SCT match reload alias register of match channel 11 */
+#define LPC43_SCT_MATCHR12A_OFFSET  0x02b0 /* SCT match reload alias register of match channel 12 */
+#define LPC43_SCT_MATCHR13A_OFFSET  0x02b4 /* SCT match reload alias register of match channel 13 */
+#define LPC43_SCT_MATCHR14A_OFFSET  0x02b8 /* SCT match reload alias register of match channel 14 */
+#define LPC43_SCT_MATCHR15A_OFFSET  0x02bc /* SCT match reload alias register of match channel 15 */
+
+#define LPC43_SCT_MATCHRLA_OFFSET(n) (0x0280 + ((n) << 4)) /* n = 0..15 */
+#define LPC43_SCT_MATCHR0LA_OFFSET  0x0280 /* SCT match reload alias register of match channel 0; low 16-bit */
+#define LPC43_SCT_MATCHR1LA_OFFSET  0x0284 /* SCT match reload alias register of match channel 1; low 16-bit */
+#define LPC43_SCT_MATCHR2LA_OFFSET  0x0288 /* SCT match reload alias register of match channel 2; low 16-bit */
+#define LPC43_SCT_MATCHR3LA_OFFSET  0x028c /* SCT match reload alias register of match channel 3; low 16-bit */
+#define LPC43_SCT_MATCHR4LA_OFFSET  0x0290 /* SCT match reload alias register of match channel 4; low 16-bit */
+#define LPC43_SCT_MATCHR5LA_OFFSET  0x0294 /* SCT match reload alias register of match channel 5; low 16-bit */
+#define LPC43_SCT_MATCHR6LA_OFFSET  0x0298 /* SCT match reload alias register of match channel 6; low 16-bit */
+#define LPC43_SCT_MATCHR7LA_OFFSET  0x029c /* SCT match reload alias register of match channel 7; low 16-bit */
+#define LPC43_SCT_MATCHR8LA_OFFSET  0x02a0 /* SCT match reload alias register of match channel 8; low 16-bit */
+#define LPC43_SCT_MATCHR9LA_OFFSET  0x02a4 /* SCT match reload alias register of match channel 9; low 16-bit */
+#define LPC43_SCT_MATCHR10LA_OFFSET 0x02a8 /* SCT match reload alias register of match channel 10; low 16-bit */
+#define LPC43_SCT_MATCHR11LA_OFFSET 0x02ac /* SCT match reload alias register of match channel 11; low 16-bit */
+#define LPC43_SCT_MATCHR12LA_OFFSET 0x02b0 /* SCT match reload alias register of match channel 12; low 16-bit */
+#define LPC43_SCT_MATCHR13LA_OFFSET 0x02b4 /* SCT match reload alias register of match channel 13; low 16-bit */
+#define LPC43_SCT_MATCHR14LA_OFFSET 0x02b8 /* SCT match reload alias register of match channel 14; low 16-bit */
+#define LPC43_SCT_MATCHR15LA_OFFSET 0x02bc /* SCT match reload alias register of match channel 15; low 16-bit */
+
+#define LPC43_SCT_MATCHRHA_OFFSET(n) (0x0282 + ((n) << 4)) /* n = 0..15 */
+#define LPC43_SCT_MATCHR0HA_OFFSET  0x0282 /* SCT match reload alias register of match channel 0; high 16-bit */
+#define LPC43_SCT_MATCHR1HA_OFFSET  0x0286 /* SCT match reload alias register of match channel 1; high 16-bit */
+#define LPC43_SCT_MATCHR2HA_OFFSET  0x028a /* SCT match reload alias register of match channel 2; high 16-bit */
+#define LPC43_SCT_MATCHR3HA_OFFSET  0x028e /* SCT match reload alias register of match channel 3; high 16-bit */
+#define LPC43_SCT_MATCHR4HA_OFFSET  0x0292 /* SCT match reload alias register of match channel 4; high 16-bit */
+#define LPC43_SCT_MATCHR5HA_OFFSET  0x0296 /* SCT match reload alias register of match channel 5; high 16-bit */
+#define LPC43_SCT_MATCHR6HA_OFFSET  0x029a /* SCT match reload alias register of match channel 6; high 16-bit */
+#define LPC43_SCT_MATCHR7HA_OFFSET  0x029e /* SCT match reload alias register of match channel 7; high 16-bit */
+#define LPC43_SCT_MATCHR8HA_OFFSET  0x02a2 /* SCT match reload alias register of match channel 8; high 16-bit */
+#define LPC43_SCT_MATCHR9HA_OFFSET  0x02a6 /* SCT match reload alias register of match channel 9; high 16-bit */
+#define LPC43_SCT_MATCHR10HA_OFFSET 0x02aa /* SCT match reload alias register of match channel 10; high 16-bit */
+#define LPC43_SCT_MATCHR11HA_OFFSET 0x02ae /* SCT match reload alias register of match channel 11; high 16-bit */
+#define LPC43_SCT_MATCHR12HA_OFFSET 0x02b2 /* SCT match reload alias register of match channel 12; high 16-bit */
+#define LPC43_SCT_MATCHR13HA_OFFSET 0x02b6 /* SCT match reload alias register of match channel 13; high 16-bit */
+#define LPC43_SCT_MATCHR14HA_OFFSET 0x02ba /* SCT match reload alias register of match channel 14; high 16-bit */
+#define LPC43_SCT_MATCHR15HA_OFFSET 0x02be /* SCT match reload alias register of match channel 15; high 16-bit */
+
+#define LPC43_SCT_CAPCA_OFFSET(n)   (0x0280 + ((n) << 4)) /* n = 0..15 */
+#define LPC43_SCT_CAPC0A_OFFSET     0x0280 /* SCT capture control alias register Ch0 */
+#define LPC43_SCT_CAPC1A_OFFSET     0x0284 /* SCT capture control alias register Ch1 */
+#define LPC43_SCT_CAPC2A_OFFSET     0x0288 /* SCT capture control alias register Ch2 */
+#define LPC43_SCT_CAPC3A_OFFSET     0x028c /* SCT capture control alias register Ch3 */
+#define LPC43_SCT_CAPC4A_OFFSET     0x0290 /* SCT capture control alias register Ch4 */
+#define LPC43_SCT_CAPC5A_OFFSET     0x0294 /* SCT capture control alias register Ch5 */
+#define LPC43_SCT_CAPC6A_OFFSET     0x0298 /* SCT capture control alias register Ch6 */
+#define LPC43_SCT_CAPC7A_OFFSET     0x029c /* SCT capture control alias register Ch7 */
+#define LPC43_SCT_CAPC8A_OFFSET     0x02a0 /* SCT capture control alias register Ch8 */
+#define LPC43_SCT_CAPC9A_OFFSET     0x02a4 /* SCT capture control alias register Ch9 */
+#define LPC43_SCT_CAPC10A_OFFSET    0x02a8 /* SCT capture control alias register Ch10 */
+#define LPC43_SCT_CAPC11A_OFFSET    0x02ac /* SCT capture control alias register Ch11 */
+#define LPC43_SCT_CAPC12A_OFFSET    0x02b0 /* SCT capture control alias register Ch12 */
+#define LPC43_SCT_CAPC13A_OFFSET    0x02b4 /* SCT capture control alias register Ch13 */
+#define LPC43_SCT_CAPC14A_OFFSET    0x02b8 /* SCT capture control alias register Ch14 */
+#define LPC43_SCT_CAPC15A_OFFSET    0x02bc /* SCT capture control alias register Ch15 */
+
+#define LPC43_SCT_CAPCLA_OFFSET(n)  (0x0280 + ((n) << 4)) /* n = 0..15 */
+#define LPC43_SCT_CAPC0LA_OFFSET    0x0280 /* SCT capture control alias register Ch0; low 16-bit */
+#define LPC43_SCT_CAPC1LA_OFFSET    0x0284 /* SCT capture control alias register Ch1; low 16-bit */
+#define LPC43_SCT_CAPC2LA_OFFSET    0x0288 /* SCT capture control alias register Ch2; low 16-bit */
+#define LPC43_SCT_CAPC3LA_OFFSET    0x028c /* SCT capture control alias register Ch3; low 16-bit */
+#define LPC43_SCT_CAPC4LA_OFFSET    0x0290 /* SCT capture control alias register Ch4; low 16-bit */
+#define LPC43_SCT_CAPC5LA_OFFSET    0x0294 /* SCT capture control alias register Ch5; low 16-bit */
+#define LPC43_SCT_CAPC6LA_OFFSET    0x0298 /* SCT capture control alias register Ch6; low 16-bit */
+#define LPC43_SCT_CAPC7LA_OFFSET    0x029c /* SCT capture control alias register Ch7; low 16-bit */
+#define LPC43_SCT_CAPC8LA_OFFSET    0x02a0 /* SCT capture control alias register Ch8; low 16-bit */
+#define LPC43_SCT_CAPC9LA_OFFSET    0x02a4 /* SCT capture control alias register Ch9; low 16-bit */
+#define LPC43_SCT_CAPC10LA_OFFSET   0x02a8 /* SCT capture control alias register Ch10; low 16-bit */
+#define LPC43_SCT_CAPC11LA_OFFSET   0x02ac /* SCT capture control alias register Ch11; low 16-bit */
+#define LPC43_SCT_CAPC12LA_OFFSET   0x02b0 /* SCT capture control alias register Ch12; low 16-bit */
+#define LPC43_SCT_CAPC13LA_OFFSET   0x02b4 /* SCT capture control alias register Ch13; low 16-bit */
+#define LPC43_SCT_CAPC14LA_OFFSET   0x02b8 /* SCT capture control alias register Ch14; low 16-bit */
+#define LPC43_SCT_CAPC15LA_OFFSET   0x02bc /* SCT capture control alias register Ch15; low 16-bit */
+
+#define LPC43_SCT_CAPCHA_OFFSET(n)  (0x0282 + ((n) << 4)) /* n = 0..15 */
+#define LPC43_SCT_CAPC0HA_OFFSET    0x0282 /* SCT capture control alias register Ch0; high 16-bit */
+#define LPC43_SCT_CAPC1HA_OFFSET    0x0286 /* SCT capture control alias register Ch1; high 16-bit */
+#define LPC43_SCT_CAPC2HA_OFFSET    0x028a /* SCT capture control alias register Ch2; high 16-bit */
+#define LPC43_SCT_CAPC3HA_OFFSET    0x028e /* SCT capture control alias register Ch3; high 16-bit */
+#define LPC43_SCT_CAPC4HA_OFFSET    0x0292 /* SCT capture control alias register Ch4; high 16-bit */
+#define LPC43_SCT_CAPC5HA_OFFSET    0x0296 /* SCT capture control alias register Ch5; high 16-bit */
+#define LPC43_SCT_CAPC6HA_OFFSET    0x029a /* SCT capture control alias register Ch6; high 16-bit */
+#define LPC43_SCT_CAPC7HA_OFFSET    0x029e /* SCT capture control alias register Ch7; high 16-bit */
+#define LPC43_SCT_CAPC8HA_OFFSET    0x02a2 /* SCT capture control alias register Ch8; high 16-bit */
+#define LPC43_SCT_CAPC9HA_OFFSET    0x02a6 /* SCT capture control alias register Ch9; high 16-bit */
+#define LPC43_SCT_CAPC10HA_OFFSET   0x02aa /* SCT capture control alias register Ch10; high 16-bit */
+#define LPC43_SCT_CAPC11HA_OFFSET   0x02ae /* SCT capture control alias register Ch11; high 16-bit */
+#define LPC43_SCT_CAPC12HA_OFFSET   0x02b2 /* SCT capture control alias register Ch12; high 16-bit */
+#define LPC43_SCT_CAPC13HA_OFFSET   0x02b6 /* SCT capture control alias register Ch13; high 16-bit */
+#define LPC43_SCT_CAPC14HA_OFFSET   0x02ba /* SCT capture control alias register Ch14; high 16-bit */
+#define LPC43_SCT_CAPC15HA_OFFSET   0x02be /* SCT capture control alias register Ch15; high 16-bit */
+
+#define LPC43_SCT_EVSM_OFFSET(n)    (0x0300 + ((n) << 3))
+#define LPC43_SCT_EVC_OFFSET(n)     (0x0304 + ((n) << 3))
+
+#define LPC43_SCT_EVSM0_OFFSET      0x0300 /* SCT event state register 0 */
+#define LPC43_SCT_EVC0_OFFSET       0x0304 /* SCT event control register 0 */
+#define LPC43_SCT_EVSM1_OFFSET      0x0308 /* SCT event state register 1 */
+#define LPC43_SCT_EVC1_OFFSET       0x030c /* SCT event control register 1 */
+#define LPC43_SCT_EVSM2_OFFSET      0x0310 /* SCT event state register 2 */
+#define LPC43_SCT_EVC2_OFFSET       0x0314 /* SCT event control register 2 */
+#define LPC43_SCT_EVSM3_OFFSET      0x0318 /* SCT event state register 3 */
+#define LPC43_SCT_EVC3_OFFSET       0x031c /* SCT event control register 3 */
+#define LPC43_SCT_EVSM4_OFFSET      0x0320 /* SCT event state register 4 */
+#define LPC43_SCT_EVC4_OFFSET       0x0324 /* SCT event control register 4 */
+#define LPC43_SCT_EVSM5_OFFSET      0x0328 /* SCT event state register 5 */
+#define LPC43_SCT_EVC5_OFFSET       0x032c /* SCT event control register 5 */
+#define LPC43_SCT_EVSM6_OFFSET      0x0330 /* SCT event state register 6 */
+#define LPC43_SCT_EVC6_OFFSET       0x0334 /* SCT event control register 6 */
+#define LPC43_SCT_EVSM7_OFFSET      0x0338 /* SCT event state register 7 */
+#define LPC43_SCT_EVC7_OFFSET       0x033c /* SCT event control register 7 */
+#define LPC43_SCT_EVSM8_OFFSET      0x0340 /* SCT event state register 8 */
+#define LPC43_SCT_EVC8_OFFSET       0x0344 /* SCT event control register 8 */
+#define LPC43_SCT_EVSM9_OFFSET      0x0348 /* SCT event state register 9 */
+#define LPC43_SCT_EVC9_OFFSET       0x034c /* SCT event control register 9 */
+#define LPC43_SCT_EVSM10_OFFSET     0x0350 /* SCT event state register 10 */
+#define LPC43_SCT_EVC10_OFFSET      0x0354 /* SCT event control register 10 */
+#define LPC43_SCT_EVSM11_OFFSET     0x0358 /* SCT event state register 11 */
+#define LPC43_SCT_EVC11_OFFSET      0x035c /* SCT event control register 11 */
+#define LPC43_SCT_EVSM12_OFFSET     0x0360 /* SCT event state register 12 */
+#define LPC43_SCT_EVC12_OFFSET      0x0364 /* SCT event control register 12 */
+#define LPC43_SCT_EVSM13_OFFSET     0x0368 /* SCT event state register 13 */
+#define LPC43_SCT_EVC13_OFFSET      0x036c /* SCT event control register 13 */
+#define LPC43_SCT_EVSM14_OFFSET     0x0370 /* SCT event state register 14 */
+#define LPC43_SCT_EVC14_OFFSET      0x0374 /* SCT event control register 14 */
+#define LPC43_SCT_EVSM15_OFFSET     0x0378 /* SCT event state register 15 */
+#define LPC43_SCT_EVC15_OFFSET      0x037c /* SCT event control register 15 */
+
+#define LPC43_SCT_OUTSET_OFFSET(n)  (0x0500 + ((n) << 3))
+#define LPC43_SCT_OUTCLR_OFFSET(n)  (0x0504 + ((n) << 3))
+
+#define LPC43_SCT_OUTSET0_OFFSET    0x0500 /* SCT output 0 set register */
+#define LPC43_SCT_OUTCLR0_OFFSET    0x0504 /* SCT output 0 clear register */
+#define LPC43_SCT_OUTSET1_OFFSET    0x0508 /* SCT output 1 set register */
+#define LPC43_SCT_OUTCLR1_OFFSET    0x050c /* SCT output 1 clear register */
+#define LPC43_SCT_OUTSET2_OFFSET    0x0510 /* SCT output 2 set register */
+#define LPC43_SCT_OUTCLR2_OFFSET    0x0514 /* SCT output 2 clear register */
+#define LPC43_SCT_OUTSET3_OFFSET    0x0518 /* SCT output 3 set register */
+#define LPC43_SCT_OUTCLR3_OFFSET    0x051c /* SCT output 3 clear register */
+#define LPC43_SCT_OUTSET4_OFFSET    0x0520 /* SCT output 4 set register */
+#define LPC43_SCT_OUTCLR4_OFFSET    0x0524 /* SCT output 4 clear register */
+#define LPC43_SCT_OUTSET5_OFFSET    0x0528 /* SCT output 5 set register */
+#define LPC43_SCT_OUTCLR5_OFFSET    0x052c /* SCT output 5 clear register */
+#define LPC43_SCT_OUTSET6_OFFSET    0x0530 /* SCT output 6 set register */
+#define LPC43_SCT_OUTCLR6_OFFSET    0x0534 /* SCT output 6 clear register */
+#define LPC43_SCT_OUTSET7_OFFSET    0x0538 /* SCT output 7 set register */
+#define LPC43_SCT_OUTCLR7_OFFSET    0x053c /* SCT output 7 clear register */
+#define LPC43_SCT_OUTSET8_OFFSET    0x0540 /* SCT output 8 set register */
+#define LPC43_SCT_OUTCLR8_OFFSET    0x0544 /* SCT output 8 clear register */
+#define LPC43_SCT_OUTSET9_OFFSET    0x0548 /* SCT output 9 set register */
+#define LPC43_SCT_OUTCLR9_OFFSET    0x054c /* SCT output 9 clear register */
+#define LPC43_SCT_OUTSET10_OFFSET   0x0550 /* SCT output 10 set register */
+#define LPC43_SCT_OUTCLR10_OFFSET   0x0554 /* SCT output 10 clear register */
+#define LPC43_SCT_OUTSET11_OFFSET   0x0558 /* SCT output 11 set register */
+#define LPC43_SCT_OUTCLR11_OFFSET   0x055c /* SCT output 11 clear register */
+#define LPC43_SCT_OUTSET12_OFFSET   0x0560 /* SCT output 12 set register */
+#define LPC43_SCT_OUTCLR12_OFFSET   0x0564 /* SCT output 12 clear register */
+#define LPC43_SCT_OUTSET13_OFFSET   0x0568 /* SCT output 13 set register */
+#define LPC43_SCT_OUTCLR13_OFFSET   0x056c /* SCT output 13 clear register */
+#define LPC43_SCT_OUTSET14_OFFSET   0x0570 /* SCT output 14 set register */
+#define LPC43_SCT_OUTCLR14_OFFSET   0x0574 /* SCT output 14 clear register */
+#define LPC43_SCT_OUTSET15_OFFSET   0x0578 /* SCT output 15 set register */
+#define LPC43_SCT_OUTCLR15_OFFSET   0x057c /* SCT output 15 clear register */
+
+/* Register Addresses *******************************************************************************/
+
+#define LPC43_SCT_CONFIG            (LPC43_SCT_BASE+LPC43_SCT_CONFIG_OFFSET)
+#define LPC43_SCT_CTRL              (LPC43_SCT_BASE+LPC43_SCT_CTRL_OFFSET)
+#define LPC43_SCT_CTRLL             (LPC43_SCT_BASE+LPC43_SCT_CTRLL_OFFSET)
+#define LPC43_SCT_CTRLH             (LPC43_SCT_BASE+LPC43_SCT_CTRLH_OFFSET)
+#define LPC43_SCT_LIMIT             (LPC43_SCT_BASE+LPC43_SCT_LIMIT_OFFSET)
+#define LPC43_SCT_LIMITL            (LPC43_SCT_BASE+LPC43_SCT_LIMITL_OFFSET)
+#define LPC43_SCT_LIMITH            (LPC43_SCT_BASE+LPC43_SCT_LIMITH_OFFSET)
+#define LPC43_SCT_HALT              (LPC43_SCT_BASE+LPC43_SCT_HALT_OFFSET)
+#define LPC43_SCT_HALTL             (LPC43_SCT_BASE+LPC43_SCT_HALTL_OFFSET)
+#define LPC43_SCT_HALTH             (LPC43_SCT_BASE+LPC43_SCT_HALTH_OFFSET)
+#define LPC43_SCT_STOP              (LPC43_SCT_BASE+LPC43_SCT_STOP_OFFSET)
+#define LPC43_SCT_STOPL             (LPC43_SCT_BASE+LPC43_SCT_STOPL_OFFSET)
+#define LPC43_SCT_STOPH             (LPC43_SCT_BASE+LPC43_SCT_STOPH_OFFSET)
+#define LPC43_SCT_START             (LPC43_SCT_BASE+LPC43_SCT_START_OFFSET)
+#define LPC43_SCT_STARTL            (LPC43_SCT_BASE+LPC43_SCT_STARTL_OFFSET)
+#define LPC43_SCT_STARTH            (LPC43_SCT_BASE+LPC43_SCT_STARTH_OFFSET)
+
+#define LPC43_SCT_COUNT             (LPC43_SCT_BASE+LPC43_SCT_COUNT_OFFSET)
+#define LPC43_SCT_COUNTL            (LPC43_SCT_BASE+LPC43_SCT_COUNTL_OFFSET)
+#define LPC43_SCT_COUNTH            (LPC43_SCT_BASE+LPC43_SCT_COUNTH_OFFSET)
+#define LPC43_SCT_STATE             (LPC43_SCT_BASE+LPC43_SCT_STATE_OFFSET)
+#define LPC43_SCT_STATEL            (LPC43_SCT_BASE+LPC43_SCT_STATEL_OFFSET)
+#define LPC43_SCT_STATEH            (LPC43_SCT_BASE+LPC43_SCT_STATEH_OFFSET)
+#define LPC43_SCT_INPUT             (LPC43_SCT_BASE+LPC43_SCT_INPUT_OFFSET)
+#define LPC43_SCT_REGM              (LPC43_SCT_BASE+LPC43_SCT_REGM_OFFSET)
+#define LPC43_SCT_REGML             (LPC43_SCT_BASE+LPC43_SCT_REGML_OFFSET)
+#define LPC43_SCT_REGMH             (LPC43_SCT_BASE+LPC43_SCT_REGMH_OFFSET)
+#define LPC43_SCT_OUT               (LPC43_SCT_BASE+LPC43_SCT_OUT_OFFSET)
+#define LPC43_SCT_OUTDIRC           (LPC43_SCT_BASE+LPC43_SCT_OUTDIRC_OFFSET)
+#define LPC43_SCT_RES               (LPC43_SCT_BASE+LPC43_SCT_RES_OFFSET)
+#define LPC43_SCT_DMAREQ0           (LPC43_SCT_BASE+LPC43_SCT_DMAREQ0_OFFSET)
+#define LPC43_SCT_DMAREQ1           (LPC43_SCT_BASE+LPC43_SCT_DMAREQ1_OFFSET)
+
+#define LPC43_SCT_EVEN              (LPC43_SCT_BASE+LPC43_SCT_EVEN_OFFSET)
+#define LPC43_SCT_EVFLAG            (LPC43_SCT_BASE+LPC43_SCT_EVFLAG_OFFSET)
+#define LPC43_SCT_CONEN             (LPC43_SCT_BASE+LPC43_SCT_CONEN_OFFSET)
+#define LPC43_SCT_CONFLAG           (LPC43_SCT_BASE+LPC43_SCT_CONFLAG_OFFSET)
+
+#define LPC43_SCT_MATCH(n)          (LPC43_SCT_BASE+LPC43_SCT_MATCH_OFFSET(n))
+#define LPC43_SCT_MATCH0            (LPC43_SCT_BASE+LPC43_SCT_MATCH0_OFFSET)
+#define LPC43_SCT_MATCH1            (LPC43_SCT_BASE+LPC43_SCT_MATCH1_OFFSET)
+#define LPC43_SCT_MATCH2            (LPC43_SCT_BASE+LPC43_SCT_MATCH2_OFFSET)
+#define LPC43_SCT_MATCH3            (LPC43_SCT_BASE+LPC43_SCT_MATCH3_OFFSET)
+#define LPC43_SCT_MATCH4            (LPC43_SCT_BASE+LPC43_SCT_MATCH4_OFFSET)
+#define LPC43_SCT_MATCH5            (LPC43_SCT_BASE+LPC43_SCT_MATCH5_OFFSET)
+#define LPC43_SCT_MATCH6            (LPC43_SCT_BASE+LPC43_SCT_MATCH6_OFFSET)
+#define LPC43_SCT_MATCH7            (LPC43_SCT_BASE+LPC43_SCT_MATCH7_OFFSET)
+#define LPC43_SCT_MATCH8            (LPC43_SCT_BASE+LPC43_SCT_MATCH8_OFFSET)
+#define LPC43_SCT_MATCH9            (LPC43_SCT_BASE+LPC43_SCT_MATCH9_OFFSET)
+#define LPC43_SCT_MATCH10           (LPC43_SCT_BASE+LPC43_SCT_MATCH10_OFFSET)
+#define LPC43_SCT_MATCH11           (LPC43_SCT_BASE+LPC43_SCT_MATCH11_OFFSET)
+#define LPC43_SCT_MATCH12           (LPC43_SCT_BASE+LPC43_SCT_MATCH12_OFFSET)
+#define LPC43_SCT_MATCH13           (LPC43_SCT_BASE+LPC43_SCT_MATCH13_OFFSET)
+#define LPC43_SCT_MATCH14           (LPC43_SCT_BASE+LPC43_SCT_MATCH14_OFFSET)
+#define LPC43_SCT_MATCH15           (LPC43_SCT_BASE+LPC43_SCT_MATCH15_OFFSET)
+
+#define LPC43_SCT_MATCHL(n)         (LPC43_SCT_BASE+LPC43_SCT_MATCHL_OFFSET(n))
+#define LPC43_SCT_MATCHL0           (LPC43_SCT_BASE+LPC43_SCT_MATCHL0_OFFSET)
+#define LPC43_SCT_MATCHL1           (LPC43_SCT_BASE+LPC43_SCT_MATCHL1_OFFSET)
+#define LPC43_SCT_MATCHL2           (LPC43_SCT_BASE+LPC43_SCT_MATCHL2_OFFSET)
+#define LPC43_SCT_MATCHL3           (LPC43_SCT_BASE+LPC43_SCT_MATCHL3_OFFSET)
+#define LPC43_SCT_MATCHL4           (LPC43_SCT_BASE+LPC43_SCT_MATCHL4_OFFSET)
+#define LPC43_SCT_MATCHL5           (LPC43_SCT_BASE+LPC43_SCT_MATCHL5_OFFSET)
+#define LPC43_SCT_MATCHL6           (LPC43_SCT_BASE+LPC43_SCT_MATCHL6_OFFSET)
+#define LPC43_SCT_MATCHL7           (LPC43_SCT_BASE+LPC43_SCT_MATCHL7_OFFSET)
+#define LPC43_SCT_MATCHL8           (LPC43_SCT_BASE+LPC43_SCT_MATCHL8_OFFSET)
+#define LPC43_SCT_MATCHL9           (LPC43_SCT_BASE+LPC43_SCT_MATCHL9_OFFSET)
+#define LPC43_SCT_MATCHL10          (LPC43_SCT_BASE+LPC43_SCT_MATCHL10_OFFSET)
+#define LPC43_SCT_MATCHL11          (LPC43_SCT_BASE+LPC43_SCT_MATCHL11_OFFSET)
+#define LPC43_SCT_MATCHL12          (LPC43_SCT_BASE+LPC43_SCT_MATCHL12_OFFSET)
+#define LPC43_SCT_MATCHL13          (LPC43_SCT_BASE+LPC43_SCT_MATCHL13_OFFSET)
+#define LPC43_SCT_MATCHL14          (LPC43_SCT_BASE+LPC43_SCT_MATCHL14_OFFSET)
+#define LPC43_SCT_MATCHL15          (LPC43_SCT_BASE+LPC43_SCT_MATCHL15_OFFSET)
+
+#define LPC43_SCT_MATCHH(n)         (LPC43_SCT_BASE+LPC43_SCT_MATCHH_OFFSET(n))
+#define LPC43_SCT_MATCHH0           (LPC43_SCT_BASE+LPC43_SCT_MATCHH0_OFFSET)
+#define LPC43_SCT_MATCHH1           (LPC43_SCT_BASE+LPC43_SCT_MATCHH1_OFFSET)
+#define LPC43_SCT_MATCHH2           (LPC43_SCT_BASE+LPC43_SCT_MATCHH2_OFFSET)
+#define LPC43_SCT_MATCHH3           (LPC43_SCT_BASE+LPC43_SCT_MATCHH3_OFFSET)
+#define LPC43_SCT_MATCHH4           (LPC43_SCT_BASE+LPC43_SCT_MATCHH4_OFFSET)
+#define LPC43_SCT_MATCHH5           (LPC43_SCT_BASE+LPC43_SCT_MATCHH5_OFFSET)
+#define LPC43_SCT_MATCHH6           (LPC43_SCT_BASE+LPC43_SCT_MATCHH6_OFFSET)
+#define LPC43_SCT_MATCHH7           (LPC43_SCT_BASE+LPC43_SCT_MATCHH7_OFFSET)
+#define LPC43_SCT_MATCHH8           (LPC43_SCT_BASE+LPC43_SCT_MATCHH8_OFFSET)
+#define LPC43_SCT_MATCHH9           (LPC43_SCT_BASE+LPC43_SCT_MATCHH9_OFFSET)
+#define LPC43_SCT_MATCHH10          (LPC43_SCT_BASE+LPC43_SCT_MATCHH10_OFFSET)
+#define LPC43_SCT_MATCHH11          (LPC43_SCT_BASE+LPC43_SCT_MATCHH11_OFFSET)
+#define LPC43_SCT_MATCHH12          (LPC43_SCT_BASE+LPC43_SCT_MATCHH12_OFFSET)
+#define LPC43_SCT_MATCHH13          (LPC43_SCT_BASE+LPC43_SCT_MATCHH13_OFFSET)
+#define LPC43_SCT_MATCHH14          (LPC43_SCT_BASE+LPC43_SCT_MATCHH14_OFFSET)
+#define LPC43_SCT_MATCHH15          (LPC43_SCT_BASE+LPC43_SCT_MATCHH15_OFFSET)
+
+#define LPC43_SCT_CAP(n)            (LPC43_SCT_BASE+LPC43_SCT_CAP_OFFSET(n))
+#define LPC43_SCT_CAP0              (LPC43_SCT_BASE+LPC43_SCT_CAP0_OFFSET)
+#define LPC43_SCT_CAP1              (LPC43_SCT_BASE+LPC43_SCT_CAP1_OFFSET)
+#define LPC43_SCT_CAP2              (LPC43_SCT_BASE+LPC43_SCT_CAP2_OFFSET)
+#define LPC43_SCT_CAP3              (LPC43_SCT_BASE+LPC43_SCT_CAP3_OFFSET)
+#define LPC43_SCT_CAP4              (LPC43_SCT_BASE+LPC43_SCT_CAP4_OFFSET)
+#define LPC43_SCT_CAP5              (LPC43_SCT_BASE+LPC43_SCT_CAP5_OFFSET)
+#define LPC43_SCT_CAP6              (LPC43_SCT_BASE+LPC43_SCT_CAP6_OFFSET)
+#define LPC43_SCT_CAP7              (LPC43_SCT_BASE+LPC43_SCT_CAP7_OFFSET)
+#define LPC43_SCT_CAP8              (LPC43_SCT_BASE+LPC43_SCT_CAP8_OFFSET)
+#define LPC43_SCT_CAP9              (LPC43_SCT_BASE+LPC43_SCT_CAP9_OFFSET)
+#define LPC43_SCT_CAP10             (LPC43_SCT_BASE+LPC43_SCT_CAP10_OFFSET)
+#define LPC43_SCT_CAP11             (LPC43_SCT_BASE+LPC43_SCT_CAP11_OFFSET)
+#define LPC43_SCT_CAP12             (LPC43_SCT_BASE+LPC43_SCT_CAP12_OFFSET)
+#define LPC43_SCT_CAP13             (LPC43_SCT_BASE+LPC43_SCT_CAP13_OFFSET)
+#define LPC43_SCT_CAP14             (LPC43_SCT_BASE+LPC43_SCT_CAP14_OFFSET)
+#define LPC43_SCT_CAP15             (LPC43_SCT_BASE+LPC43_SCT_CAP15_OFFSET)
+
+#define LPC43_SCT_CAPL(n)           (LPC43_SCT_BASE+LPC43_SCT_CAPL_OFFSET(n))
+#define LPC43_SCT_CAPL0             (LPC43_SCT_BASE+LPC43_SCT_CAPL0_OFFSET)
+#define LPC43_SCT_CAPL1             (LPC43_SCT_BASE+LPC43_SCT_CAPL1_OFFSET)
+#define LPC43_SCT_CAPL2             (LPC43_SCT_BASE+LPC43_SCT_CAPL2_OFFSET)
+#define LPC43_SCT_CAPL3             (LPC43_SCT_BASE+LPC43_SCT_CAPL3_OFFSET)
+#define LPC43_SCT_CAPL4             (LPC43_SCT_BASE+LPC43_SCT_CAPL4_OFFSET)
+#define LPC43_SCT_CAPL5             (LPC43_SCT_BASE+LPC43_SCT_CAPL5_OFFSET)
+#define LPC43_SCT_CAPL6             (LPC43_SCT_BASE+LPC43_SCT_CAPL6_OFFSET)
+#define LPC43_SCT_CAPL7             (LPC43_SCT_BASE+LPC43_SCT_CAPL7_OFFSET)
+#define LPC43_SCT_CAPL8             (LPC43_SCT_BASE+LPC43_SCT_CAPL8_OFFSET)
+#define LPC43_SCT_CAPL9             (LPC43_SCT_BASE+LPC43_SCT_CAPL9_OFFSET)
+#define LPC43_SCT_CAPL10            (LPC43_SCT_BASE+LPC43_SCT_CAPL10_OFFSET)
+#define LPC43_SCT_CAPL11            (LPC43_SCT_BASE+LPC43_SCT_CAPL11_OFFSET)
+#define LPC43_SCT_CAPL12            (LPC43_SCT_BASE+LPC43_SCT_CAPL12_OFFSET)
+#define LPC43_SCT_CAPL13            (LPC43_SCT_BASE+LPC43_SCT_CAPL13_OFFSET)
+#define LPC43_SCT_CAPL14            (LPC43_SCT_BASE+LPC43_SCT_CAPL14_OFFSET)
+#define LPC43_SCT_CAPL15            (LPC43_SCT_BASE+LPC43_SCT_CAPL15_OFFSET)
+
+#define LPC43_SCT_CAPH(n)           (LPC43_SCT_BASE+LPC43_SCT_CAPH_OFFSET(n))
+#define LPC43_SCT_CAPH0             (LPC43_SCT_BASE+LPC43_SCT_CAPH0_OFFSET)
+#define LPC43_SCT_CAPH1             (LPC43_SCT_BASE+LPC43_SCT_CAPH1_OFFSET)
+#define LPC43_SCT_CAPH2             (LPC43_SCT_BASE+LPC43_SCT_CAPH2_OFFSET)
+#define LPC43_SCT_CAPH3             (LPC43_SCT_BASE+LPC43_SCT_CAPH3_OFFSET)
+#define LPC43_SCT_CAPH4             (LPC43_SCT_BASE+LPC43_SCT_CAPH4_OFFSET)
+#define LPC43_SCT_CAPH5             (LPC43_SCT_BASE+LPC43_SCT_CAPH5_OFFSET)
+#define LPC43_SCT_CAPH6             (LPC43_SCT_BASE+LPC43_SCT_CAPH6_OFFSET)
+#define LPC43_SCT_CAPH7             (LPC43_SCT_BASE+LPC43_SCT_CAPH7_OFFSET)
+#define LPC43_SCT_CAPH8             (LPC43_SCT_BASE+LPC43_SCT_CAPH8_OFFSET)
+#define LPC43_SCT_CAPH9             (LPC43_SCT_BASE+LPC43_SCT_CAPH9_OFFSET)
+#define LPC43_SCT_CAPH10            (LPC43_SCT_BASE+LPC43_SCT_CAPH10_OFFSET)
+#define LPC43_SCT_CAPH11            (LPC43_SCT_BASE+LPC43_SCT_CAPH11_OFFSET)
+#define LPC43_SCT_CAPH12            (LPC43_SCT_BASE+LPC43_SCT_CAPH12_OFFSET)
+#define LPC43_SCT_CAPH13            (LPC43_SCT_BASE+LPC43_SCT_CAPH13_OFFSET)
+#define LPC43_SCT_CAPH14            (LPC43_SCT_BASE+LPC43_SCT_CAPH14_OFFSET)
+#define LPC43_SCT_CAPH15            (LPC43_SCT_BASE+LPC43_SCT_CAPH15_OFFSET)
+
+#define LPC43_SCT_MATCHA(n)         (LPC43_SCT_BASE+LPC43_SCT_MATCHA_OFFSET(n))
+#define LPC43_SCT_MATCHA0           (LPC43_SCT_BASE+LPC43_SCT_MATCHA0_OFFSET)
+#define LPC43_SCT_MATCHA1           (LPC43_SCT_BASE+LPC43_SCT_MATCHA1_OFFSET)
+#define LPC43_SCT_MATCHA2           (LPC43_SCT_BASE+LPC43_SCT_MATCHA2_OFFSET)
+#define LPC43_SCT_MATCHA3           (LPC43_SCT_BASE+LPC43_SCT_MATCHA3_OFFSET)
+#define LPC43_SCT_MATCHA4           (LPC43_SCT_BASE+LPC43_SCT_MATCHA4_OFFSET)
+#define LPC43_SCT_MATCHA5           (LPC43_SCT_BASE+LPC43_SCT_MATCHA5_OFFSET)
+#define LPC43_SCT_MATCHA6           (LPC43_SCT_BASE+LPC43_SCT_MATCHA6_OFFSET)
+#define LPC43_SCT_MATCHA7           (LPC43_SCT_BASE+LPC43_SCT_MATCHA7_OFFSET)
+#define LPC43_SCT_MATCHA8           (LPC43_SCT_BASE+LPC43_SCT_MATCHA8_OFFSET)
+#define LPC43_SCT_MATCHA9           (LPC43_SCT_BASE+LPC43_SCT_MATCHA9_OFFSET)
+#define LPC43_SCT_MATCHA10          (LPC43_SCT_BASE+LPC43_SCT_MATCHA10_OFFSET)
+#define LPC43_SCT_MATCHA11          (LPC43_SCT_BASE+LPC43_SCT_MATCHA11_OFFSET)
+#define LPC43_SCT_MATCHA12          (LPC43_SCT_BASE+LPC43_SCT_MATCHA12_OFFSET)
+#define LPC43_SCT_MATCHA13          (LPC43_SCT_BASE+LPC43_SCT_MATCHA13_OFFSET)
+#define LPC43_SCT_MATCHA14          (LPC43_SCT_BASE+LPC43_SCT_MATCHA14_OFFSET)
+#define LPC43_SCT_MATCHA15          (LPC43_SCT_BASE+LPC43_SCT_MATCHA15_OFFSET)
+
+#define LPC43_SCT_MATCHLA(n)        (LPC43_SCT_BASE+LPC43_SCT_MATCHLA_OFFSET(n))
+#define LPC43_SCT_MATCHLA0          (LPC43_SCT_BASE+LPC43_SCT_MATCHLA0_OFFSET)
+#define LPC43_SCT_MATCHLA1          (LPC43_SCT_BASE+LPC43_SCT_MATCHLA1_OFFSET)
+#define LPC43_SCT_MATCHLA2          (LPC43_SCT_BASE+LPC43_SCT_MATCHLA2_OFFSET)
+#define LPC43_SCT_MATCHLA3          (LPC43_SCT_BASE+LPC43_SCT_MATCHLA3_OFFSET)
+#define LPC43_SCT_MATCHLA4          (LPC43_SCT_BASE+LPC43_SCT_MATCHLA4_OFFSET)
+#define LPC43_SCT_MATCHLA5          (LPC43_SCT_BASE+LPC43_SCT_MATCHLA5_OFFSET)
+#define LPC43_SCT_MATCHLA6          (LPC43_SCT_BASE+LPC43_SCT_MATCHLA6_OFFSET)
+#define LPC43_SCT_MATCHLA7          (LPC43_SCT_BASE+LPC43_SCT_MATCHLA7_OFFSET)
+#define LPC43_SCT_MATCHLA8          (LPC43_SCT_BASE+LPC43_SCT_MATCHLA8_OFFSET)
+#define LPC43_SCT_MATCHLA9          (LPC43_SCT_BASE+LPC43_SCT_MATCHLA9_OFFSET)
+#define LPC43_SCT_MATCHLA10         (LPC43_SCT_BASE+LPC43_SCT_MATCHLA10_OFFSET)
+#define LPC43_SCT_MATCHLA11         (LPC43_SCT_BASE+LPC43_SCT_MATCHLA11_OFFSET)
+#define LPC43_SCT_MATCHLA12         (LPC43_SCT_BASE+LPC43_SCT_MATCHLA12_OFFSET)
+#define LPC43_SCT_MATCHLA13         (LPC43_SCT_BASE+LPC43_SCT_MATCHLA13_OFFSET)
+#define LPC43_SCT_MATCHLA14         (LPC43_SCT_BASE+LPC43_SCT_MATCHLA14_OFFSET)
+#define LPC43_SCT_MATCHLA15         (LPC43_SCT_BASE+LPC43_SCT_MATCHLA15_OFFSET)
+
+#define LPC43_SCT_MATCHHA(n)        (LPC43_SCT_BASE+LPC43_SCT_MATCHHA_OFFSET(n))
+#define LPC43_SCT_MATCHHA0          (LPC43_SCT_BASE+LPC43_SCT_MATCHHA0_OFFSET)
+#define LPC43_SCT_MATCHHA1          (LPC43_SCT_BASE+LPC43_SCT_MATCHHA1_OFFSET)
+#define LPC43_SCT_MATCHHA2          (LPC43_SCT_BASE+LPC43_SCT_MATCHHA2_OFFSET)
+#define LPC43_SCT_MATCHHA3          (LPC43_SCT_BASE+LPC43_SCT_MATCHHA3_OFFSET)
+#define LPC43_SCT_MATCHHA4          (LPC43_SCT_BASE+LPC43_SCT_MATCHHA4_OFFSET)
+#define LPC43_SCT_MATCHHA5          (LPC43_SCT_BASE+LPC43_SCT_MATCHHA5_OFFSET)
+#define LPC43_SCT_MATCHHA6          (LPC43_SCT_BASE+LPC43_SCT_MATCHHA6_OFFSET)
+#define LPC43_SCT_MATCHHA7          (LPC43_SCT_BASE+LPC43_SCT_MATCHHA7_OFFSET)
+#define LPC43_SCT_MATCHHA8          (LPC43_SCT_BASE+LPC43_SCT_MATCHHA8_OFFSET)
+#define LPC43_SCT_MATCHHA9          (LPC43_SCT_BASE+LPC43_SCT_MATCHHA9_OFFSET)
+#define LPC43_SCT_MATCHHA10         (LPC43_SCT_BASE+LPC43_SCT_MATCHHA10_OFFSET)
+#define LPC43_SCT_MATCHHA11         (LPC43_SCT_BASE+LPC43_SCT_MATCHHA11_OFFSET)
+#define LPC43_SCT_MATCHHA12         (LPC43_SCT_BASE+LPC43_SCT_MATCHHA12_OFFSET)
+#define LPC43_SCT_MATCHHA13         (LPC43_SCT_BASE+LPC43_SCT_MATCHHA13_OFFSET)
+#define LPC43_SCT_MATCHHA14         (LPC43_SCT_BASE+LPC43_SCT_MATCHHA14_OFFSET)
+#define LPC43_SCT_MATCHHA15         (LPC43_SCT_BASE+LPC43_SCT_MATCHHA15_OFFSET)
+
+#define LPC43_SCT_CAPA(n)           (LPC43_SCT_BASE+LPC43_SCT_CAPA_OFFSET(n))
+#define LPC43_SCT_CAPA0             (LPC43_SCT_BASE+LPC43_SCT_CAPA0_OFFSET)
+#define LPC43_SCT_CAPA1             (LPC43_SCT_BASE+LPC43_SCT_CAPA1_OFFSET)
+#define LPC43_SCT_CAPA2             (LPC43_SCT_BASE+LPC43_SCT_CAPA2_OFFSET)
+#define LPC43_SCT_CAPA3             (LPC43_SCT_BASE+LPC43_SCT_CAPA3_OFFSET)
+#define LPC43_SCT_CAPA4             (LPC43_SCT_BASE+LPC43_SCT_CAPA4_OFFSET)
+#define LPC43_SCT_CAPA5             (LPC43_SCT_BASE+LPC43_SCT_CAPA5_OFFSET)
+#define LPC43_SCT_CAPA6             (LPC43_SCT_BASE+LPC43_SCT_CAPA6_OFFSET)
+#define LPC43_SCT_CAPA7             (LPC43_SCT_BASE+LPC43_SCT_CAPA7_OFFSET)
+#define LPC43_SCT_CAPA8             (LPC43_SCT_BASE+LPC43_SCT_CAPA8_OFFSET)
+#define LPC43_SCT_CAPA9             (LPC43_SCT_BASE+LPC43_SCT_CAPA9_OFFSET)
+#define LPC43_SCT_CAPA10            (LPC43_SCT_BASE+LPC43_SCT_CAPA10_OFFSET)
+#define LPC43_SCT_CAPA11            (LPC43_SCT_BASE+LPC43_SCT_CAPA11_OFFSET)
+#define LPC43_SCT_CAPA12            (LPC43_SCT_BASE+LPC43_SCT_CAPA12_OFFSET)
+#define LPC43_SCT_CAPA13            (LPC43_SCT_BASE+LPC43_SCT_CAPA13_OFFSET)
+#define LPC43_SCT_CAPA14            (LPC43_SCT_BASE+LPC43_SCT_CAPA14_OFFSET)
+#define LPC43_SCT_CAPA15            (LPC43_SCT_BASE+LPC43_SCT_CAPA15_OFFSET)
+
+#define LPC43_SCT_CAPLA(n)          (LPC43_SCT_BASE+LPC43_SCT_CAPLA_OFFSET(n))
+#define LPC43_SCT_CAPLA0            (LPC43_SCT_BASE+LPC43_SCT_CAPLA0_OFFSET)
+#define LPC43_SCT_CAPLA1            (LPC43_SCT_BASE+LPC43_SCT_CAPLA1_OFFSET)
+#define LPC43_SCT_CAPLA2            (LPC43_SCT_BASE+LPC43_SCT_CAPLA2_OFFSET)
+#define LPC43_SCT_CAPLA3            (LPC43_SCT_BASE+LPC43_SCT_CAPLA3_OFFSET)
+#define LPC43_SCT_CAPLA4            (LPC43_SCT_BASE+LPC43_SCT_CAPLA4_OFFSET)
+#define LPC43_SCT_CAPLA5            (LPC43_SCT_BASE+LPC43_SCT_CAPLA5_OFFSET)
+#define LPC43_SCT_CAPLA6            (LPC43_SCT_BASE+LPC43_SCT_CAPLA6_OFFSET)
+#define LPC43_SCT_CAPLA7            (LPC43_SCT_BASE+LPC43_SCT_CAPLA7_OFFSET)
+#define LPC43_SCT_CAPLA8            (LPC43_SCT_BASE+LPC43_SCT_CAPLA8_OFFSET)
+#define LPC43_SCT_CAPLA9            (LPC43_SCT_BASE+LPC43_SCT_CAPLA9_OFFSET)
+#define LPC43_SCT_CAPLA10           (LPC43_SCT_BASE+LPC43_SCT_CAPLA10_OFFSET)
+#define LPC43_SCT_CAPLA11           (LPC43_SCT_BASE+LPC43_SCT_CAPLA11_OFFSET)
+#define LPC43_SCT_CAPLA12           (LPC43_SCT_BASE+LPC43_SCT_CAPLA12_OFFSET)
+#define LPC43_SCT_CAPLA13           (LPC43_SCT_BASE+LPC43_SCT_CAPLA13_OFFSET)
+#define LPC43_SCT_CAPLA14           (LPC43_SCT_BASE+LPC43_SCT_CAPLA14_OFFSET)
+#define LPC43_SCT_CAPLA15           (LPC43_SCT_BASE+LPC43_SCT_CAPLA15_OFFSET)
+
+#define LPC43_SCT_CAPHA(n)          (LPC43_SCT_BASE+LPC43_SCT_CAPHA_OFFSET(n))
+#define LPC43_SCT_CAPHA0            (LPC43_SCT_BASE+LPC43_SCT_CAPHA0_OFFSET)
+#define LPC43_SCT_CAPHA1            (LPC43_SCT_BASE+LPC43_SCT_CAPHA1_OFFSET)
+#define LPC43_SCT_CAPHA2            (LPC43_SCT_BASE+LPC43_SCT_CAPHA2_OFFSET)
+#define LPC43_SCT_CAPHA3            (LPC43_SCT_BASE+LPC43_SCT_CAPHA3_OFFSET)
+#define LPC43_SCT_CAPHA4            (LPC43_SCT_BASE+LPC43_SCT_CAPHA4_OFFSET)
+#define LPC43_SCT_CAPHA5            (LPC43_SCT_BASE+LPC43_SCT_CAPHA5_OFFSET)
+#define LPC43_SCT_CAPHA6            (LPC43_SCT_BASE+LPC43_SCT_CAPHA6_OFFSET)
+#define LPC43_SCT_CAPHA7            (LPC43_SCT_BASE+LPC43_SCT_CAPHA7_OFFSET)
+#define LPC43_SCT_CAPHA8            (LPC43_SCT_BASE+LPC43_SCT_CAPHA8_OFFSET)
+#define LPC43_SCT_CAPHA9            (LPC43_SCT_BASE+LPC43_SCT_CAPHA9_OFFSET)
+#define LPC43_SCT_CAPHA10           (LPC43_SCT_BASE+LPC43_SCT_CAPHA10_OFFSET)
+#define LPC43_SCT_CAPHA11           (LPC43_SCT_BASE+LPC43_SCT_CAPHA11_OFFSET)
+#define LPC43_SCT_CAPHA12           (LPC43_SCT_BASE+LPC43_SCT_CAPHA12_OFFSET)
+#define LPC43_SCT_CAPHA13           (LPC43_SCT_BASE+LPC43_SCT_CAPHA13_OFFSET)
+#define LPC43_SCT_CAPHA14           (LPC43_SCT_BASE+LPC43_SCT_CAPHA14_OFFSET)
+#define LPC43_SCT_CAPHA15           (LPC43_SCT_BASE+LPC43_SCT_CAPHA15_OFFSET)
+
+#define LPC43_SCT_MATCHR(n)         (LPC43_SCT_BASE+LPC43_SCT_MATCHR_OFFSET(n))
+#define LPC43_SCT_MATCHR0           (LPC43_SCT_BASE+LPC43_SCT_MATCHR0_OFFSET)
+#define LPC43_SCT_MATCHR1           (LPC43_SCT_BASE+LPC43_SCT_MATCHR1_OFFSET)
+#define LPC43_SCT_MATCHR2           (LPC43_SCT_BASE+LPC43_SCT_MATCHR2_OFFSET)
+#define LPC43_SCT_MATCHR3           (LPC43_SCT_BASE+LPC43_SCT_MATCHR3_OFFSET)
+#define LPC43_SCT_MATCHR4           (LPC43_SCT_BASE+LPC43_SCT_MATCHR4_OFFSET)
+#define LPC43_SCT_MATCHR5           (LPC43_SCT_BASE+LPC43_SCT_MATCHR5_OFFSET)
+#define LPC43_SCT_MATCHR6           (LPC43_SCT_BASE+LPC43_SCT_MATCHR6_OFFSET)
+#define LPC43_SCT_MATCHR7           (LPC43_SCT_BASE+LPC43_SCT_MATCHR7_OFFSET)
+#define LPC43_SCT_MATCHR8           (LPC43_SCT_BASE+LPC43_SCT_MATCHR8_OFFSET)
+#define LPC43_SCT_MATCHR9           (LPC43_SCT_BASE+LPC43_SCT_MATCHR9_OFFSET)
+#define LPC43_SCT_MATCHR10          (LPC43_SCT_BASE+LPC43_SCT_MATCHR10_OFFSET)
+#define LPC43_SCT_MATCHR11          (LPC43_SCT_BASE+LPC43_SCT_MATCHR11_OFFSET)
+#define LPC43_SCT_MATCHR12          (LPC43_SCT_BASE+LPC43_SCT_MATCHR12_OFFSET)
+#define LPC43_SCT_MATCHR13          (LPC43_SCT_BASE+LPC43_SCT_MATCHR13_OFFSET)
+#define LPC43_SCT_MATCHR14          (LPC43_SCT_BASE+LPC43_SCT_MATCHR14_OFFSET)
+#define LPC43_SCT_MATCHR15          (LPC43_SCT_BASE+LPC43_SCT_MATCHR15_OFFSET)
+
+#define LPC43_SCT_MATCHRL(n)        (LPC43_SCT_BASE+LPC43_SCT_MATCHRL_OFFSET(n))
+#define LPC43_SCT_MATCHRL0          (LPC43_SCT_BASE+LPC43_SCT_MATCHRL0_OFFSET)
+#define LPC43_SCT_MATCHRL1          (LPC43_SCT_BASE+LPC43_SCT_MATCHRL1_OFFSET)
+#define LPC43_SCT_MATCHRL2          (LPC43_SCT_BASE+LPC43_SCT_MATCHRL2_OFFSET)
+#define LPC43_SCT_MATCHRL3          (LPC43_SCT_BASE+LPC43_SCT_MATCHRL3_OFFSET)
+#define LPC43_SCT_MATCHRL4          (LPC43_SCT_BASE+LPC43_SCT_MATCHRL4_OFFSET)
+#define LPC43_SCT_MATCHRL5          (LPC43_SCT_BASE+LPC43_SCT_MATCHRL5_OFFSET)
+#define LPC43_SCT_MATCHRL6          (LPC43_SCT_BASE+LPC43_SCT_MATCHRL6_OFFSET)
+#define LPC43_SCT_MATCHRL7          (LPC43_SCT_BASE+LPC43_SCT_MATCHRL7_OFFSET)
+#define LPC43_SCT_MATCHRL8          (LPC43_SCT_BASE+LPC43_SCT_MATCHRL8_OFFSET)
+#define LPC43_SCT_MATCHRL9          (LPC43_SCT_BASE+LPC43_SCT_MATCHRL9_OFFSET)
+#define LPC43_SCT_MATCHRL10         (LPC43_SCT_BASE+LPC43_SCT_MATCHRL10_OFFSET)
+#define LPC43_SCT_MATCHRL11         (LPC43_SCT_BASE+LPC43_SCT_MATCHRL11_OFFSET)
+#define LPC43_SCT_MATCHRL12         (LPC43_SCT_BASE+LPC43_SCT_MATCHRL12_OFFSET)
+#define LPC43_SCT_MATCHRL13         (LPC43_SCT_BASE+LPC43_SCT_MATCHRL13_OFFSET)
+#define LPC43_SCT_MATCHRL14         (LPC43_SCT_BASE+LPC43_SCT_MATCHRL14_OFFSET)
+#define LPC43_SCT_MATCHRL15         (LPC43_SCT_BASE+LPC43_SCT_MATCHRL15_OFFSET)
+
+#define LPC43_SCT_MATCHRH(n)        (LPC43_SCT_BASE+LPC43_SCT_MATCHRH_OFFSET(n))
+#define LPC43_SCT_MATCHRH0          (LPC43_SCT_BASE+LPC43_SCT_MATCHRH0_OFFSET)
+#define LPC43_SCT_MATCHRH1          (LPC43_SCT_BASE+LPC43_SCT_MATCHRH1_OFFSET)
+#define LPC43_SCT_MATCHRH2          (LPC43_SCT_BASE+LPC43_SCT_MATCHRH2_OFFSET)
+#define LPC43_SCT_MATCHRH3          (LPC43_SCT_BASE+LPC43_SCT_MATCHRH3_OFFSET)
+#define LPC43_SCT_MATCHRH4          (LPC43_SCT_BASE+LPC43_SCT_MATCHRH4_OFFSET)
+#define LPC43_SCT_MATCHRH5          (LPC43_SCT_BASE+LPC43_SCT_MATCHRH5_OFFSET)
+#define LPC43_SCT_MATCHRH6          (LPC43_SCT_BASE+LPC43_SCT_MATCHRH6_OFFSET)
+#define LPC43_SCT_MATCHRH7          (LPC43_SCT_BASE+LPC43_SCT_MATCHRH7_OFFSET)
+#define LPC43_SCT_MATCHRH8          (LPC43_SCT_BASE+LPC43_SCT_MATCHRH8_OFFSET)
+#define LPC43_SCT_MATCHRH9          (LPC43_SCT_BASE+LPC43_SCT_MATCHRH9_OFFSET)
+#define LPC43_SCT_MATCHRH10         (LPC43_SCT_BASE+LPC43_SCT_MATCHRH10_OFFSET)
+#define LPC43_SCT_MATCHRH11         (LPC43_SCT_BASE+LPC43_SCT_MATCHRH11_OFFSET)
+#define LPC43_SCT_MATCHRH12         (LPC43_SCT_BASE+LPC43_SCT_MATCHRH12_OFFSET)
+#define LPC43_SCT_MATCHRH13         (LPC43_SCT_BASE+LPC43_SCT_MATCHRH13_OFFSET)
+#define LPC43_SCT_MATCHRH14         (LPC43_SCT_BASE+LPC43_SCT_MATCHRH14_OFFSET)
+#define LPC43_SCT_MATCHRH15         (LPC43_SCT_BASE+LPC43_SCT_MATCHRH15_OFFSET)
+
+#define LPC43_SCT_CAPC(n)           (LPC43_SCT_BASE+LPC43_SCT_CAPC_OFFSET(n))
+#define LPC43_SCT_CAPC0             (LPC43_SCT_BASE+LPC43_SCT_CAPC0_OFFSET)
+#define LPC43_SCT_CAPC1             (LPC43_SCT_BASE+LPC43_SCT_CAPC1_OFFSET)
+#define LPC43_SCT_CAPC2             (LPC43_SCT_BASE+LPC43_SCT_CAPC2_OFFSET)
+#define LPC43_SCT_CAPC3             (LPC43_SCT_BASE+LPC43_SCT_CAPC3_OFFSET)
+#define LPC43_SCT_CAPC4             (LPC43_SCT_BASE+LPC43_SCT_CAPC4_OFFSET)
+#define LPC43_SCT_CAPC5             (LPC43_SCT_BASE+LPC43_SCT_CAPC5_OFFSET)
+#define LPC43_SCT_CAPC6             (LPC43_SCT_BASE+LPC43_SCT_CAPC6_OFFSET)
+#define LPC43_SCT_CAPC7             (LPC43_SCT_BASE+LPC43_SCT_CAPC7_OFFSET)
+#define LPC43_SCT_CAPC8             (LPC43_SCT_BASE+LPC43_SCT_CAPC8_OFFSET)
+#define LPC43_SCT_CAPC9             (LPC43_SCT_BASE+LPC43_SCT_CAPC9_OFFSET)
+#define LPC43_SCT_CAPC10            (LPC43_SCT_BASE+LPC43_SCT_CAPC10_OFFSET)
+#define LPC43_SCT_CAPC11            (LPC43_SCT_BASE+LPC43_SCT_CAPC11_OFFSET)
+#define LPC43_SCT_CAPC12            (LPC43_SCT_BASE+LPC43_SCT_CAPC12_OFFSET)
+#define LPC43_SCT_CAPC13            (LPC43_SCT_BASE+LPC43_SCT_CAPC13_OFFSET)
+#define LPC43_SCT_CAPC14            (LPC43_SCT_BASE+LPC43_SCT_CAPC14_OFFSET)
+#define LPC43_SCT_CAPC15            (LPC43_SCT_BASE+LPC43_SCT_CAPC15_OFFSET)
+
+#define LPC43_SCT_CAPCL(n)          (LPC43_SCT_BASE+LPC43_SCT_CAPCL_OFFSET(n))
+#define LPC43_SCT_CAPCL0            (LPC43_SCT_BASE+LPC43_SCT_CAPCL0_OFFSET)
+#define LPC43_SCT_CAPCL1            (LPC43_SCT_BASE+LPC43_SCT_CAPCL1_OFFSET)
+#define LPC43_SCT_CAPCL2            (LPC43_SCT_BASE+LPC43_SCT_CAPCL2_OFFSET)
+#define LPC43_SCT_CAPCL3            (LPC43_SCT_BASE+LPC43_SCT_CAPCL3_OFFSET)
+#define LPC43_SCT_CAPCL4            (LPC43_SCT_BASE+LPC43_SCT_CAPCL4_OFFSET)
+#define LPC43_SCT_CAPCL5            (LPC43_SCT_BASE+LPC43_SCT_CAPCL5_OFFSET)
+#define LPC43_SCT_CAPCL6            (LPC43_SCT_BASE+LPC43_SCT_CAPCL6_OFFSET)
+#define LPC43_SCT_CAPCL7            (LPC43_SCT_BASE+LPC43_SCT_CAPCL7_OFFSET)
+#define LPC43_SCT_CAPCL8            (LPC43_SCT_BASE+LPC43_SCT_CAPCL8_OFFSET)
+#define LPC43_SCT_CAPCL9            (LPC43_SCT_BASE+LPC43_SCT_CAPCL9_OFFSET)
+#define LPC43_SCT_CAPCL10           (LPC43_SCT_BASE+LPC43_SCT_CAPCL10_OFFSET)
+#define LPC43_SCT_CAPCL11           (LPC43_SCT_BASE+LPC43_SCT_CAPCL11_OFFSET)
+#define LPC43_SCT_CAPCL12           (LPC43_SCT_BASE+LPC43_SCT_CAPCL12_OFFSET)
+#define LPC43_SCT_CAPCL13           (LPC43_SCT_BASE+LPC43_SCT_CAPCL13_OFFSET)
+#define LPC43_SCT_CAPCL14           (LPC43_SCT_BASE+LPC43_SCT_CAPCL14_OFFSET)
+#define LPC43_SCT_CAPCL15           (LPC43_SCT_BASE+LPC43_SCT_CAPCL15_OFFSET)
+
+#define LPC43_SCT_CAPCH(n)          (LPC43_SCT_BASE+LPC43_SCT_CAPCH_OFFSET(n))
+#define LPC43_SCT_CAPCH0            (LPC43_SCT_BASE+LPC43_SCT_CAPCH0_OFFSET)
+#define LPC43_SCT_CAPCH1            (LPC43_SCT_BASE+LPC43_SCT_CAPCH1_OFFSET)
+#define LPC43_SCT_CAPCH2            (LPC43_SCT_BASE+LPC43_SCT_CAPCH2_OFFSET)
+#define LPC43_SCT_CAPCH3            (LPC43_SCT_BASE+LPC43_SCT_CAPCH3_OFFSET)
+#define LPC43_SCT_CAPCH4            (LPC43_SCT_BASE+LPC43_SCT_CAPCH4_OFFSET)
+#define LPC43_SCT_CAPCH5            (LPC43_SCT_BASE+LPC43_SCT_CAPCH5_OFFSET)
+#define LPC43_SCT_CAPCH6            (LPC43_SCT_BASE+LPC43_SCT_CAPCH6_OFFSET)
+#define LPC43_SCT_CAPCH7            (LPC43_SCT_BASE+LPC43_SCT_CAPCH7_OFFSET)
+#define LPC43_SCT_CAPCH8            (LPC43_SCT_BASE+LPC43_SCT_CAPCH8_OFFSET)
+#define LPC43_SCT_CAPCH9            (LPC43_SCT_BASE+LPC43_SCT_CAPCH9_OFFSET)
+#define LPC43_SCT_CAPCH10           (LPC43_SCT_BASE+LPC43_SCT_CAPCH10_OFFSET)
+#define LPC43_SCT_CAPCH11           (LPC43_SCT_BASE+LPC43_SCT_CAPCH11_OFFSET)
+#define LPC43_SCT_CAPCH12           (LPC43_SCT_BASE+LPC43_SCT_CAPCH12_OFFSET)
+#define LPC43_SCT_CAPCH13           (LPC43_SCT_BASE+LPC43_SCT_CAPCH13_OFFSET)
+#define LPC43_SCT_CAPCH14           (LPC43_SCT_BASE+LPC43_SCT_CAPCH14_OFFSET)
+#define LPC43_SCT_CAPCH15           (LPC43_SCT_BASE+LPC43_SCT_CAPCH15_OFFSET)
+
+#define LPC43_SCT_MATCHRA(n)        (LPC43_SCT_BASE+LPC43_SCT_MATCHRA_OFFSET(n))
+#define LPC43_SCT_MATCHRA0          (LPC43_SCT_BASE+LPC43_SCT_MATCHRA0_OFFSET)
+#define LPC43_SCT_MATCHRA1          (LPC43_SCT_BASE+LPC43_SCT_MATCHRA1_OFFSET)
+#define LPC43_SCT_MATCHRA2          (LPC43_SCT_BASE+LPC43_SCT_MATCHRA2_OFFSET)
+#define LPC43_SCT_MATCHRA3          (LPC43_SCT_BASE+LPC43_SCT_MATCHRA3_OFFSET)
+#define LPC43_SCT_MATCHRA4          (LPC43_SCT_BASE+LPC43_SCT_MATCHRA4_OFFSET)
+#define LPC43_SCT_MATCHRA5          (LPC43_SCT_BASE+LPC43_SCT_MATCHRA5_OFFSET)
+#define LPC43_SCT_MATCHRA6          (LPC43_SCT_BASE+LPC43_SCT_MATCHRA6_OFFSET)
+#define LPC43_SCT_MATCHRA7          (LPC43_SCT_BASE+LPC43_SCT_MATCHRA7_OFFSET)
+#define LPC43_SCT_MATCHRA8          (LPC43_SCT_BASE+LPC43_SCT_MATCHRA8_OFFSET)
+#define LPC43_SCT_MATCHRA9          (LPC43_SCT_BASE+LPC43_SCT_MATCHRA9_OFFSET)
+#define LPC43_SCT_MATCHRA10         (LPC43_SCT_BASE+LPC43_SCT_MATCHRA10_OFFSET)
+#define LPC43_SCT_MATCHRA11         (LPC43_SCT_BASE+LPC43_SCT_MATCHRA11_OFFSET)
+#define LPC43_SCT_MATCHRA12         (LPC43_SCT_BASE+LPC43_SCT_MATCHRA12_OFFSET)
+#define LPC43_SCT_MATCHRA13         (LPC43_SCT_BASE+LPC43_SCT_MATCHRA13_OFFSET)
+#define LPC43_SCT_MATCHRA14         (LPC43_SCT_BASE+LPC43_SCT_MATCHRA14_OFFSET)
+#define LPC43_SCT_MATCHRA15         (LPC43_SCT_BASE+LPC43_SCT_MATCHRA15_OFFSET)
+
+#define LPC43_SCT_MATCHRLA(n)       (LPC43_SCT_BASE+LPC43_SCT_MATCHRLA_OFFSET(n))
+#define LPC43_SCT_MATCHRLA0         (LPC43_SCT_BASE+LPC43_SCT_MATCHRLA0_OFFSET)
+#define LPC43_SCT_MATCHRLA1         (LPC43_SCT_BASE+LPC43_SCT_MATCHRLA1_OFFSET)
+#define LPC43_SCT_MATCHRLA2         (LPC43_SCT_BASE+LPC43_SCT_MATCHRLA2_OFFSET)
+#define LPC43_SCT_MATCHRLA3         (LPC43_SCT_BASE+LPC43_SCT_MATCHRLA3_OFFSET)
+#define LPC43_SCT_MATCHRLA4         (LPC43_SCT_BASE+LPC43_SCT_MATCHRLA4_OFFSET)
+#define LPC43_SCT_MATCHRLA5         (LPC43_SCT_BASE+LPC43_SCT_MATCHRLA5_OFFSET)
+#define LPC43_SCT_MATCHRLA6         (LPC43_SCT_BASE+LPC43_SCT_MATCHRLA6_OFFSET)
+#define LPC43_SCT_MATCHRLA7         (LPC43_SCT_BASE+LPC43_SCT_MATCHRLA7_OFFSET)
+#define LPC43_SCT_MATCHRLA8         (LPC43_SCT_BASE+LPC43_SCT_MATCHRLA8_OFFSET)
+#define LPC43_SCT_MATCHRLA9         (LPC43_SCT_BASE+LPC43_SCT_MATCHRLA9_OFFSET)
+#define LPC43_SCT_MATCHRLA10        (LPC43_SCT_BASE+LPC43_SCT_MATCHRLA10_OFFSET)
+#define LPC43_SCT_MATCHRLA11        (LPC43_SCT_BASE+LPC43_SCT_MATCHRLA11_OFFSET)
+#define LPC43_SCT_MATCHRLA12        (LPC43_SCT_BASE+LPC43_SCT_MATCHRLA12_OFFSET)
+#define LPC43_SCT_MATCHRLA13        (LPC43_SCT_BASE+LPC43_SCT_MATCHRLA13_OFFSET)
+#define LPC43_SCT_MATCHRLA14        (LPC43_SCT_BASE+LPC43_SCT_MATCHRLA14_OFFSET)
+#define LPC43_SCT_MATCHRLA15        (LPC43_SCT_BASE+LPC43_SCT_MATCHRLA15_OFFSET)
+
+#define LPC43_SCT_MATCHRHA(n)       (LPC43_SCT_BASE+LPC43_SCT_MATCHRHA_OFFSET(n))
+#define LPC43_SCT_MATCHRHA0         (LPC43_SCT_BASE+LPC43_SCT_MATCHRHA0_OFFSET)
+#define LPC43_SCT_MATCHRHA1         (LPC43_SCT_BASE+LPC43_SCT_MATCHRHA1_OFFSET)
+#define LPC43_SCT_MATCHRHA2         (LPC43_SCT_BASE+LPC43_SCT_MATCHRHA2_OFFSET)
+#define LPC43_SCT_MATCHRHA3         (LPC43_SCT_BASE+LPC43_SCT_MATCHRHA3_OFFSET)
+#define LPC43_SCT_MATCHRHA4         (LPC43_SCT_BASE+LPC43_SCT_MATCHRHA4_OFFSET)
+#define LPC43_SCT_MATCHRHA5         (LPC43_SCT_BASE+LPC43_SCT_MATCHRHA5_OFFSET)
+#define LPC43_SCT_MATCHRHA6         (LPC43_SCT_BASE+LPC43_SCT_MATCHRHA6_OFFSET)
+#define LPC43_SCT_MATCHRHA7         (LPC43_SCT_BASE+LPC43_SCT_MATCHRHA7_OFFSET)
+#define LPC43_SCT_MATCHRHA8         (LPC43_SCT_BASE+LPC43_SCT_MATCHRHA8_OFFSET)
+#define LPC43_SCT_MATCHRHA9         (LPC43_SCT_BASE+LPC43_SCT_MATCHRHA9_OFFSET)
+#define LPC43_SCT_MATCHRHA10        (LPC43_SCT_BASE+LPC43_SCT_MATCHRHA10_OFFSET)
+#define LPC43_SCT_MATCHRHA11        (LPC43_SCT_BASE+LPC43_SCT_MATCHRHA11_OFFSET)
+#define LPC43_SCT_MATCHRHA12        (LPC43_SCT_BASE+LPC43_SCT_MATCHRHA12_OFFSET)
+#define LPC43_SCT_MATCHRHA13        (LPC43_SCT_BASE+LPC43_SCT_MATCHRHA13_OFFSET)
+#define LPC43_SCT_MATCHRHA14        (LPC43_SCT_BASE+LPC43_SCT_MATCHRHA14_OFFSET)
+#define LPC43_SCT_MATCHRHA15        (LPC43_SCT_BASE+LPC43_SCT_MATCHRHA15_OFFSET)
+
+#define LPC43_SCT_CAPCA(n)          (LPC43_SCT_BASE+LPC43_SCT_CAPCA_OFFSET(n))
+#define LPC43_SCT_CAPCA0            (LPC43_SCT_BASE+LPC43_SCT_CAPCA0_OFFSET)
+#define LPC43_SCT_CAPCA1            (LPC43_SCT_BASE+LPC43_SCT_CAPCA1_OFFSET)
+#define LPC43_SCT_CAPCA2            (LPC43_SCT_BASE+LPC43_SCT_CAPCA2_OFFSET)
+#define LPC43_SCT_CAPCA3            (LPC43_SCT_BASE+LPC43_SCT_CAPCA3_OFFSET)
+#define LPC43_SCT_CAPCA4            (LPC43_SCT_BASE+LPC43_SCT_CAPCA4_OFFSET)
+#define LPC43_SCT_CAPCA5            (LPC43_SCT_BASE+LPC43_SCT_CAPCA5_OFFSET)
+#define LPC43_SCT_CAPCA6            (LPC43_SCT_BASE+LPC43_SCT_CAPCA6_OFFSET)
+#define LPC43_SCT_CAPCA7            (LPC43_SCT_BASE+LPC43_SCT_CAPCA7_OFFSET)
+#define LPC43_SCT_CAPCA8            (LPC43_SCT_BASE+LPC43_SCT_CAPCA8_OFFSET)
+#define LPC43_SCT_CAPCA9            (LPC43_SCT_BASE+LPC43_SCT_CAPCA9_OFFSET)
+#define LPC43_SCT_CAPCA10           (LPC43_SCT_BASE+LPC43_SCT_CAPCA10_OFFSET)
+#define LPC43_SCT_CAPCA11           (LPC43_SCT_BASE+LPC43_SCT_CAPCA11_OFFSET)
+#define LPC43_SCT_CAPCA12           (LPC43_SCT_BASE+LPC43_SCT_CAPCA12_OFFSET)
+#define LPC43_SCT_CAPCA13           (LPC43_SCT_BASE+LPC43_SCT_CAPCA13_OFFSET)
+#define LPC43_SCT_CAPCA14           (LPC43_SCT_BASE+LPC43_SCT_CAPCA14_OFFSET)
+#define LPC43_SCT_CAPCA15           (LPC43_SCT_BASE+LPC43_SCT_CAPCA15_OFFSET)
+
+#define LPC43_SCT_CAPCLA(n)         (LPC43_SCT_BASE+LPC43_SCT_CAPCLA_OFFSET(n))
+#define LPC43_SCT_CAPCLA0           (LPC43_SCT_BASE+LPC43_SCT_CAPCLA0_OFFSET)
+#define LPC43_SCT_CAPCLA1           (LPC43_SCT_BASE+LPC43_SCT_CAPCLA1_OFFSET)
+#define LPC43_SCT_CAPCLA2           (LPC43_SCT_BASE+LPC43_SCT_CAPCLA2_OFFSET)
+#define LPC43_SCT_CAPCLA3           (LPC43_SCT_BASE+LPC43_SCT_CAPCLA3_OFFSET)
+#define LPC43_SCT_CAPCLA4           (LPC43_SCT_BASE+LPC43_SCT_CAPCLA4_OFFSET)
+#define LPC43_SCT_CAPCLA5           (LPC43_SCT_BASE+LPC43_SCT_CAPCLA5_OFFSET)
+#define LPC43_SCT_CAPCLA6           (LPC43_SCT_BASE+LPC43_SCT_CAPCLA6_OFFSET)
+#define LPC43_SCT_CAPCLA7           (LPC43_SCT_BASE+LPC43_SCT_CAPCLA7_OFFSET)
+#define LPC43_SCT_CAPCLA8           (LPC43_SCT_BASE+LPC43_SCT_CAPCLA8_OFFSET)
+#define LPC43_SCT_CAPCLA9           (LPC43_SCT_BASE+LPC43_SCT_CAPCLA9_OFFSET)
+#define LPC43_SCT_CAPCLA10          (LPC43_SCT_BASE+LPC43_SCT_CAPCLA10_OFFSET)
+#define LPC43_SCT_CAPCLA11          (LPC43_SCT_BASE+LPC43_SCT_CAPCLA11_OFFSET)
+#define LPC43_SCT_CAPCLA12          (LPC43_SCT_BASE+LPC43_SCT_CAPCLA12_OFFSET)
+#define LPC43_SCT_CAPCLA13          (LPC43_SCT_BASE+LPC43_SCT_CAPCLA13_OFFSET)
+#define LPC43_SCT_CAPCLA14          (LPC43_SCT_BASE+LPC43_SCT_CAPCLA14_OFFSET)
+#define LPC43_SCT_CAPCLA15          (LPC43_SCT_BASE+LPC43_SCT_CAPCLA15_OFFSET)
+
+#define LPC43_SCT_CAPCHA(n)         (LPC43_SCT_BASE+LPC43_SCT_CAPCHA_OFFSET(n))
+#define LPC43_SCT_CAPCHA0           (LPC43_SCT_BASE+LPC43_SCT_CAPCHA0_OFFSET)
+#define LPC43_SCT_CAPCHA1           (LPC43_SCT_BASE+LPC43_SCT_CAPCHA1_OFFSET)
+#define LPC43_SCT_CAPCHA2           (LPC43_SCT_BASE+LPC43_SCT_CAPCHA2_OFFSET)
+#define LPC43_SCT_CAPCHA3           (LPC43_SCT_BASE+LPC43_SCT_CAPCHA3_OFFSET)
+#define LPC43_SCT_CAPCHA4           (LPC43_SCT_BASE+LPC43_SCT_CAPCHA4_OFFSET)
+#define LPC43_SCT_CAPCHA5           (LPC43_SCT_BASE+LPC43_SCT_CAPCHA5_OFFSET)
+#define LPC43_SCT_CAPCHA6           (LPC43_SCT_BASE+LPC43_SCT_CAPCHA6_OFFSET)
+#define LPC43_SCT_CAPCHA7           (LPC43_SCT_BASE+LPC43_SCT_CAPCHA7_OFFSET)
+#define LPC43_SCT_CAPCHA8           (LPC43_SCT_BASE+LPC43_SCT_CAPCHA8_OFFSET)
+#define LPC43_SCT_CAPCHA9           (LPC43_SCT_BASE+LPC43_SCT_CAPCHA9_OFFSET)
+#define LPC43_SCT_CAPCHA10          (LPC43_SCT_BASE+LPC43_SCT_CAPCHA10_OFFSET)
+#define LPC43_SCT_CAPCHA11          (LPC43_SCT_BASE+LPC43_SCT_CAPCHA11_OFFSET)
+#define LPC43_SCT_CAPCHA12          (LPC43_SCT_BASE+LPC43_SCT_CAPCHA12_OFFSET)
+#define LPC43_SCT_CAPCHA13          (LPC43_SCT_BASE+LPC43_SCT_CAPCHA13_OFFSET)
+#define LPC43_SCT_CAPCHA14          (LPC43_SCT_BASE+LPC43_SCT_CAPCHA14_OFFSET)
+#define LPC43_SCT_CAPCHA15          (LPC43_SCT_BASE+LPC43_SCT_CAPCHA15_OFFSET)
+
+#define LPC43_SCT_EVSM(n)           (LPC43_SCT_BASE+LPC43_SCT_EVSM_OFFSET(n))
+#define LPC43_SCT_EVC(n)            (LPC43_SCT_BASE+LPC43_SCT_EVC_OFFSET(n))
+
+#define LPC43_SCT_EVSM0             (LPC43_SCT_BASE+LPC43_SCT_EVSM0_OFFSET)
+#define LPC43_SCT_EVC0              (LPC43_SCT_BASE+LPC43_SCT_EVC0_OFFSET)
+#define LPC43_SCT_EVSM1             (LPC43_SCT_BASE+LPC43_SCT_EVSM1_OFFSET)
+#define LPC43_SCT_EVC1              (LPC43_SCT_BASE+LPC43_SCT_EVC1_OFFSET)
+#define LPC43_SCT_EVSM2             (LPC43_SCT_BASE+LPC43_SCT_EVSM2_OFFSET)
+#define LPC43_SCT_EVC2              (LPC43_SCT_BASE+LPC43_SCT_EVC2_OFFSET)
+#define LPC43_SCT_EVSM3             (LPC43_SCT_BASE+LPC43_SCT_EVSM3_OFFSET)
+#define LPC43_SCT_EVC3              (LPC43_SCT_BASE+LPC43_SCT_EVC3_OFFSET)
+#define LPC43_SCT_EVSM4             (LPC43_SCT_BASE+LPC43_SCT_EVSM4_OFFSET)
+#define LPC43_SCT_EVC4              (LPC43_SCT_BASE+LPC43_SCT_EVC4_OFFSET)
+#define LPC43_SCT_EVSM5             (LPC43_SCT_BASE+LPC43_SCT_EVSM5_OFFSET)
+#define LPC43_SCT_EVC5              (LPC43_SCT_BASE+LPC43_SCT_EVC5_OFFSET)
+#define LPC43_SCT_EVSM6             (LPC43_SCT_BASE+LPC43_SCT_EVSM6_OFFSET)
+#define LPC43_SCT_EVC6              (LPC43_SCT_BASE+LPC43_SCT_EVC6_OFFSET)
+#define LPC43_SCT_EVSM7             (LPC43_SCT_BASE+LPC43_SCT_EVSM7_OFFSET)
+#define LPC43_SCT_EVC7              (LPC43_SCT_BASE+LPC43_SCT_EVC7_OFFSET)
+#define LPC43_SCT_EVSM8             (LPC43_SCT_BASE+LPC43_SCT_EVSM8_OFFSET)
+#define LPC43_SCT_EVC8              (LPC43_SCT_BASE+LPC43_SCT_EVC8_OFFSET)
+#define LPC43_SCT_EVSM9             (LPC43_SCT_BASE+LPC43_SCT_EVSM9_OFFSET)
+#define LPC43_SCT_EVC9              (LPC43_SCT_BASE+LPC43_SCT_EVC9_OFFSET)
+#define LPC43_SCT_EVSM10            (LPC43_SCT_BASE+LPC43_SCT_EVSM10_OFFSET)
+#define LPC43_SCT_EVC10             (LPC43_SCT_BASE+LPC43_SCT_EVC10_OFFSET)
+#define LPC43_SCT_EVSM11            (LPC43_SCT_BASE+LPC43_SCT_EVSM11_OFFSET)
+#define LPC43_SCT_EVC11             (LPC43_SCT_BASE+LPC43_SCT_EVC11_OFFSET)
+#define LPC43_SCT_EVSM12            (LPC43_SCT_BASE+LPC43_SCT_EVSM12_OFFSET)
+#define LPC43_SCT_EVC12             (LPC43_SCT_BASE+LPC43_SCT_EVC12_OFFSET)
+#define LPC43_SCT_EVSM13            (LPC43_SCT_BASE+LPC43_SCT_EVSM13_OFFSET)
+#define LPC43_SCT_EVC13             (LPC43_SCT_BASE+LPC43_SCT_EVC13_OFFSET)
+#define LPC43_SCT_EVSM14            (LPC43_SCT_BASE+LPC43_SCT_EVSM14_OFFSET)
+#define LPC43_SCT_EVC14             (LPC43_SCT_BASE+LPC43_SCT_EVC14_OFFSET)
+#define LPC43_SCT_EVSM15            (LPC43_SCT_BASE+LPC43_SCT_EVSM15_OFFSET)
+#define LPC43_SCT_EVC15             (LPC43_SCT_BASE+LPC43_SCT_EVC15_OFFSET)
+
+#define LPC43_SCT_OUTSET(n)         (LPC43_SCT_BASE+LPC43_SCT_OUTSET_OFFSET(n))
+#define LPC43_SCT_OUTCLR(n)         (LPC43_SCT_BASE+LPC43_SCT_OUTCLR_OFFSET(n))
+
+#define LPC43_SCT_OUTSET0           (LPC43_SCT_BASE+LPC43_SCT_OUTSET0_OFFSET)
+#define LPC43_SCT_OUTCLR0           (LPC43_SCT_BASE+LPC43_SCT_OUTCLR0_OFFSET)
+#define LPC43_SCT_OUTSET1           (LPC43_SCT_BASE+LPC43_SCT_OUTSET1_OFFSET)
+#define LPC43_SCT_OUTCLR1           (LPC43_SCT_BASE+LPC43_SCT_OUTCLR1_OFFSET)
+#define LPC43_SCT_OUTSET2           (LPC43_SCT_BASE+LPC43_SCT_OUTSET2_OFFSET)
+#define LPC43_SCT_OUTCLR2           (LPC43_SCT_BASE+LPC43_SCT_OUTCLR2_OFFSET)
+#define LPC43_SCT_OUTSET3           (LPC43_SCT_BASE+LPC43_SCT_OUTSET3_OFFSET)
+#define LPC43_SCT_OUTCLR3           (LPC43_SCT_BASE+LPC43_SCT_OUTCLR3_OFFSET)
+#define LPC43_SCT_OUTSET4           (LPC43_SCT_BASE+LPC43_SCT_OUTSET4_OFFSET)
+#define LPC43_SCT_OUTCLR4           (LPC43_SCT_BASE+LPC43_SCT_OUTCLR4_OFFSET)
+#define LPC43_SCT_OUTSET5           (LPC43_SCT_BASE+LPC43_SCT_OUTSET5_OFFSET)
+#define LPC43_SCT_OUTCLR5           (LPC43_SCT_BASE+LPC43_SCT_OUTCLR5_OFFSET)
+#define LPC43_SCT_OUTSET6           (LPC43_SCT_BASE+LPC43_SCT_OUTSET6_OFFSET)
+#define LPC43_SCT_OUTCLR6           (LPC43_SCT_BASE+LPC43_SCT_OUTCLR6_OFFSET)
+#define LPC43_SCT_OUTSET7           (LPC43_SCT_BASE+LPC43_SCT_OUTSET7_OFFSET)
+#define LPC43_SCT_OUTCLR7           (LPC43_SCT_BASE+LPC43_SCT_OUTCLR7_OFFSET)
+#define LPC43_SCT_OUTSET8           (LPC43_SCT_BASE+LPC43_SCT_OUTSET8_OFFSET)
+#define LPC43_SCT_OUTCLR8           (LPC43_SCT_BASE+LPC43_SCT_OUTCLR8_OFFSET)
+#define LPC43_SCT_OUTSET9           (LPC43_SCT_BASE+LPC43_SCT_OUTSET9_OFFSET)
+#define LPC43_SCT_OUTCLR9           (LPC43_SCT_BASE+LPC43_SCT_OUTCLR9_OFFSET)
+#define LPC43_SCT_OUTSET10          (LPC43_SCT_BASE+LPC43_SCT_OUTSET10_OFFSET)
+#define LPC43_SCT_OUTCLR10          (LPC43_SCT_BASE+LPC43_SCT_OUTCLR10_OFFSET)
+#define LPC43_SCT_OUTSET11          (LPC43_SCT_BASE+LPC43_SCT_OUTSET11_OFFSET)
+#define LPC43_SCT_OUTCLR11          (LPC43_SCT_BASE+LPC43_SCT_OUTCLR11_OFFSET)
+#define LPC43_SCT_OUTSET12          (LPC43_SCT_BASE+LPC43_SCT_OUTSET12_OFFSET)
+#define LPC43_SCT_OUTCLR12          (LPC43_SCT_BASE+LPC43_SCT_OUTCLR12_OFFSET)
+#define LPC43_SCT_OUTSET13          (LPC43_SCT_BASE+LPC43_SCT_OUTSET13_OFFSET)
+#define LPC43_SCT_OUTCLR13          (LPC43_SCT_BASE+LPC43_SCT_OUTCLR13_OFFSET)
+#define LPC43_SCT_OUTSET14          (LPC43_SCT_BASE+LPC43_SCT_OUTSET14_OFFSET)
+#define LPC43_SCT_OUTCLR14          (LPC43_SCT_BASE+LPC43_SCT_OUTCLR14_OFFSET)
+#define LPC43_SCT_OUTSET15          (LPC43_SCT_BASE+LPC43_SCT_OUTSET15_OFFSET)
+#define LPC43_SCT_OUTCLR15          (LPC43_SCT_BASE+LPC43_SCT_OUTCLR15_OFFSET)
+
+/* Register Bit Definitions *************************************************************************/
+
+/* SCT configuration register */
+
+#define SCT_CONFIG_UNIFY            (1 << 0)  /* Bit 0:  0  SCT operation */
+#define SCT_CONFIG_CLKMODE_SHIFT    (1)       /* Bits 1-2: SCT clock mode */
+#define SCT_CONFIG_CLKMODE_MASK     (3 << SCT_CONFIG_CLKMODE_SHIFT)
+#  define SCT_CONFIG_CLKMODE_BUS    (0 << SCT_CONFIG_CLKMODE_SHIFT) /* Bus clock clocks SCT and prescalers */
+#  define SCT_CONFIG_CLKMODE_SCT    (1 << SCT_CONFIG_CLKMODE_SHIFT) /* SCT clock is the bus clock */
+#  define SCT_CONFIG_CLKMODE_CLKSEL (2 << SCT_CONFIG_CLKMODE_SHIFT) /* CLKSEL clocks SCT and prescalers */
+#  define SCT_CONFIG_CLKMODE_EDGE   (3 << SCT_CONFIG_CLKMODE_SHIFT) /* CLKSEL input edge clocks SCT and prescalers */
+#define SCT_CONFIG_CLKSEL_SHIFT     (3)       /* Bits 3-6: SCT clock select */
+#define SCT_CONFIG_CLKSEL_MASK      (15 << SCT_CONFIG_CLKSEL_SHIFT)
+# define SCT_CONFIG_CLKSEL_REDGE0   (0 << SCT_CONFIG_CLKSEL_SHIFT)  /* Rising edges on input 0 */
+# define SCT_CONFIG_CLKSEL_FEDGE0   (1 << SCT_CONFIG_CLKSEL_SHIFT)  /* Falling edges on input 0 */
+# define SCT_CONFIG_CLKSEL_REDGE1   (2 << SCT_CONFIG_CLKSEL_SHIFT)  /* Rising edges on input 1 */
+# define SCT_CONFIG_CLKSEL_FEDGE1   (3 << SCT_CONFIG_CLKSEL_SHIFT)  /* Falling edges on input 1 */
+# define SCT_CONFIG_CLKSEL_REDGE2   (4 << SCT_CONFIG_CLKSEL_SHIFT)  /* Rising edges on input 2 */
+# define SCT_CONFIG_CLKSEL_FEDGE2   (5 << SCT_CONFIG_CLKSEL_SHIFT)  /* Falling edges on input 2 */
+# define SCT_CONFIG_CLKSEL_REDGE3   (6 << SCT_CONFIG_CLKSEL_SHIFT)  /* Rising edges on input 3 */
+# define SCT_CONFIG_CLKSEL_FEDGE3   (7 << SCT_CONFIG_CLKSEL_SHIFT)  /* Falling edges on input 3 */
+# define SCT_CONFIG_CLKSEL_REDGE4   (8 << SCT_CONFIG_CLKSEL_SHIFT)  /* Rising edges on input 4 */
+# define SCT_CONFIG_CLKSEL_FEDGE4   (9 << SCT_CONFIG_CLKSEL_SHIFT)  /* Falling edges on input 4 */
+# define SCT_CONFIG_CLKSEL_REDGE5   (10 << SCT_CONFIG_CLKSEL_SHIFT) /* Rising edges on input 5 */
+# define SCT_CONFIG_CLKSEL_FEDGE5   (11 << SCT_CONFIG_CLKSEL_SHIFT) /* Falling edges on input 5 */
+# define SCT_CONFIG_CLKSEL_REDGE6   (12 << SCT_CONFIG_CLKSEL_SHIFT) /* Rising edges on input 6 */
+# define SCT_CONFIG_CLKSEL_FEDGE6   (13 << SCT_CONFIG_CLKSEL_SHIFT) /* Falling edges on input 6 */
+# define SCT_CONFIG_CLKSEL_REDGE7   (14 << SCT_CONFIG_CLKSEL_SHIFT) /* Rising edges on input 7 */
+# define SCT_CONFIG_CLKSEL_FEDGE7   (15 << SCT_CONFIG_CLKSEL_SHIFT) /* Falling edges on input 7 */
+#define SCT_CONFIG_NORELOADU        (1 << 7)  /* Bit 7:  Disable unified match register reload */
+#define SCT_CONFIG_NORELOADL        (1 << 7)  /* Bit 7:  Disable lower match registers reload */
+#define SCT_CONFIG_NORELOADH        (1 << 8)  /* Bit 8:  Disable higher match register reload */
+#define SCT_CONFIG_INSYNC_SHIFT     (9)       /* Bits 9-16: Synchronization for input n=1..7 */
+#define SCT_CONFIG_INSYNC_MASK      (0xff << SCT_CONFIG_INSYNC_SHIFT)
+#  define SCT_CONFIG_INSYNC(n)      (1 << (SCT_CONFIG_INSYNC_SHIFT+(n)))
+                                              /* Bits 17-31: Reserved */
+/* SCT control register */
+
+#define SCT_CTRL_DOWNU              (1 << 0)  /* Bit 0:  Unified counter counts down */
+#define SCT_CTRL_STOPU              (1 << 1)  /* Bit 1:  Unified counter stopped (I/O events can occur) */
+#define SCT_CTRL_HALTU              (1 << 2)  /* Bit 2:  Unified counter halted (no events can occur) */
+#define SCT_CTRL_CLRCTRU            (1 << 3)  /* Bit 3:  Clear unified counter */
+#define SCT_CTRL_BIDIRU             (1 << 4)  /* Bit 4:  Unified counter direction select */
+#define SCT_CTRL_PREU_SHIFT         (5)       /* Bits 5-12: Unified counter SCT clock prescale factor */
+#define SCT_CTRL_PREU_MASK          (0xff << SCT_CTRL_PREU_SHIFT)
+
+#define SCT_CTRL_DOWNL              (1 << 0)  /* Bit 0:  L counter counts down */
+#define SCT_CTRL_STOPL              (1 << 1)  /* Bit 1:  L counter stopped (I/O events can occur) */
+#define SCT_CTRL_HALTL              (1 << 2)  /* Bit 2:  L counter halted (no events can occur) */
+#define SCT_CTRL_CLRCTRL            (1 << 3)  /* Bit 3:  Clear L counter */
+#define SCT_CTRL_BIDIRL             (1 << 4)  /* Bit 4:  L counter direction select */
+#define SCT_CTRL_PREL_SHIFT         (5)       /* Bits 5-12: L counter SCT clock prescale factor */
+#define SCT_CTRL_PREL_MASK          (0xff << SCT_CTRL_PREL_SHIFT)
+                                              /* Bits 13-15: Reserved */
+#define SCT_CTRL_DOWNH              (1 << 16) /* Bit 16: H counter counts down */
+#define SCT_CTRL_STOPH              (1 << 17) /* Bit 17: H counter stopped (I/O events can occur) */
+#define SCT_CTRL_HALTH              (1 << 18) /* Bit 18: H counter halted (no events can occur) */
+#define SCT_CTRL_CLRCTRH            (1 << 19) /* Bit 19: Clear H counter */
+#define SCT_CTRL_BIDIRH             (1 << 20) /* Bit 20: H counter direction select */
+#define SCT_CTRL_PREH_SHIFT         (21)      /* Bits 21-28: H counter SCT clock prescale factor */
+#define SCT_CTRL_PREH_MASK          (0xff << yy)
+                                                /* Bits 29-31: Reserved */
+/* SCT control register low/high 16-bit */
+
+#define SCT_CTRL_DOWN               (1 << 0)  /* Bit 0:  Unified counter counts down */
+#define SCT_CTRL_STOP               (1 << 1)  /* Bit 1:  Unified counter stopped (I/O events can occur) */
+#define SCT_CTRL_HALT               (1 << 2)  /* Bit 2:  Unified counter halted (no events can occur) */
+#define SCT_CTRL_CLRCTR             (1 << 3)  /* Bit 3:  Clear unified counter */
+#define SCT_CTRL_BIDIR              (1 << 4)  /* Bit 4:  Unified counter direction select */
+#define SCT_CTRL_PRE_SHIFT          (5)       /* Bits 5-12: Unified counter SCT clock prescale factor */
+#define SCT_CTRL_PRE_MASK           (0xff << SCT_CTRL_PRE_SHIFT)
+                                              /* Bits 13-16: Reserved */
+/* SCT limit register (all 32-bits for unified counter) */
+
+#define SCT_LIMITL_SHIFT            (0)       /* Bits 0-15: Limit for L counter */
+#define SCT_LIMITL_MASK             (0xffff << SCT_LIMITL_SHIFT)
+#define SCT_LIMITH_SHIFT            (16)      /* Bits 16-31: Limit for H counter */
+#define SCT_LIMITH_MASK             (0xffff << SCT_LIMITH_SHIFT)
+
+/* SCT limit register low/high 16-bit (all 16-bits for limit value) */
+
+/* SCT halt condition register (all 32-bits for unified counter) */
+
+#define SCT_HALTU(n)                (1 << (n))
+#define SCT_HALTL_SHIFT             (0)       /* Bits 0-15: Set HALTL in CTRL register */
+#define SCT_HALTL_MASK              (0xffff << SCT_HALTL_SHIFT)
+#  define SCT_HALTL(n)              (1 << (n))
+#define SCT_HALTH_SHIFT             (16)      /* Bits 16-31:Set HALTL in CTRL register */
+#define SCT_HALTH_MASK              (0xffff << SCT_HALTH_SHIFT)
+#  define SCT_HALTH(n)              (1 << (SCT_HALTH_SHIFT+(n)))
+
+/* SCT halt condition register low/high 16-bit (all 16-bits for halt condition) */
+
+#define SCT_HALT(n)                 (1 << (n))
+
+/* SCT stop condition register (all 32-bits for unified counter) */
+
+#define SCT_STOPU(n)                (1 << (n))
+#define SCT_STOPL_SHIFT             (0)       /* Bits 0-15: Set STOPL in CTRL register */
+#define SCT_STOPL_MASK              (0xffff << SCT_STOPL_SHIFT)
+#  define SCT_STOPL(n)              (1 << (n))
+#define SCT_STOPH_SHIFT             (16)      /* Bits 16-31:Set STOPL in CTRL register */
+#define SCT_STOPH_MASK              (0xffff << SCT_STOPH_SHIFT)
+#  define SCT_STOPH(n)              (1 << (SCT_STOPH_SHIFT+(n)))
+
+/* SCT stop condition register low 16-bit (all 16-bits for stop condition) */
+
+#define SCT_STOP(n)                 (1 << (n))
+
+/* SCT start condition register (all 32-bits for unified counter) */
+
+#define SCT_STARTU(n)               (1 << (n))
+#define SCT_STARTL_SHIFT            (0)       /* Bits 0-15: Clear STOPL in CTRL register */
+#define SCT_STARTL_MASK             (0xffff << SCT_STARTL_SHIFT)
+#  define SCT_STARTL(n)             (1 << (n))
+#define SCT_STARTH_SHIFT            (16)      /* Bits 16-31: Clear STOPL in CTRL register */
+#define SCT_STARTH_MASK             (0xffff << SCT_STARTH_SHIFT)
+#  define SCT_STARTH(n)             (1 << (SCT_STARTH_SHIFT+(n)))
+
+/* SCT start condition register low 16-bit (all 16-bits for start condition) */
+
+#define SCT_START(n)                (1 << (n))
+
+/* SCT counter register (all 32-bits for unified counter) */
+
+#define SCT_COUNTL_SHIFT            (0)       /* Bits 0-15: L counter value */
+#define SCT_COUNTL_MASK             (0xffff << SCT_COUNTL_SHIFT)
+#define SCT_COUNTH_SHIFT            (16)      /* Bits 16-31: H counter value */
+#define SCT_COUNTH_MASK             (0xffff << SCT_COUNTH_SHIFT)
+
+/* SCT counter register low/high 16-bit (all 16-bits for counter value)*/
+
+/* SCT state register */
+
+#define SCT_STATEU_SHIFT            (0)       /* Bits 0-5: Unified counter state */
+#define SCT_STATEU_MASK             (31 << SCT_STATEL_SHIFT)
+#define SCT_STATEL_SHIFT            (0)       /* Bits 0-5: L counter state */
+#define SCT_STATEL_MASK             (31 << SCT_STATEL_SHIFT)
+                                              /* Bits 6-15: Reserved */
+#define SCT_STATEH_SHIFT            (16)      /* Bits 16-20: H counter state */
+#define SCT_STATEH_MASK             (31 << SCT_STATEH_SHIFT)
+                                              /* Bits 21-31: Reserved */
+/* SCT state register low/high 16-bit */
+
+#define SCT_STATE_SHIFT             (0)       /* Bits 0-5: Counter state */
+#define SCT_STATE_MASK              (31 << SCT_STATE_SHIFT)
+                                              /* Bits 6-15: Reserved */
+/* SCT input register */
+
+#define SCT_INPUT_AIN(n)            (1 << (n))
+#define SCT_INPUT_AIN0              (1 << 0)  /* Bit 0:  Real-time status of input 0 */
+#define SCT_INPUT_AIN1              (1 << 1)  /* Bit 1:  Real-time status of input 1 */
+#define SCT_INPUT_AIN2              (1 << 2)  /* Bit 2:  Real-time status of input 2 */
+#define SCT_INPUT_AIN3              (1 << 3)  /* Bit 3:  Real-time status of input 3 */
+#define SCT_INPUT_AIN4              (1 << 4)  /* Bit 4:  Real-time status of input 4 */
+#define SCT_INPUT_AIN5              (1 << 5)  /* Bit 5:  Real-time status of input 5 */
+#define SCT_INPUT_AIN6              (1 << 6)  /* Bit 6:  Real-time status of input 6 */
+#define SCT_INPUT_AIN7              (1 << 7)  /* Bit 7:  Real-time status of input 7 */
+                                              /* Bits 8-15: Reserved */
+#define SCT_INPUT_SIN(n)            (1 << ((n)+16))
+#define SCT_INPUT_SIN0              (1 << 16) /* Bit 16: Synchronized input 0 state */
+#define SCT_INPUT_SIN1              (1 << 17) /* Bit 17: Synchronized input 1 state */
+#define SCT_INPUT_SIN2              (1 << 18) /* Bit 18: Synchronized input 2 state */
+#define SCT_INPUT_SIN3              (1 << 19) /* Bit 19: Synchronized input 3 state */
+#define SCT_INPUT_SIN4              (1 << 20) /* Bit 20: Synchronized input 4 state */
+#define SCT_INPUT_SIN5              (1 << 21) /* Bit 21: Synchronized input 5 state */
+#define SCT_INPUT_SIN6              (1 << 22) /* Bit 22: Synchronized input 6 state */
+#define SCT_INPUT_SIN7              (1 << 23) /* Bit 23: Synchronized input 7 state */
+                                              /* Bits 24-31: Reserved */
+/* SCT match/capture registers mode register (all 32-bits for unified counter)*/
+
+#define SCT_REGMU(n)                (1 << (n))
+#define SCT_REGML_SHIFT             (0)       /* Bits 0-15: Match/capture registers n */
+#define SCT_REGML_MASK              (0xffff << SCT_REGML_SHIFT)
+#  define SCT_REGML(n)              (1 << (n))
+#define SCT_REGMH_SHIFT             (16)      /* Bits 16-31: Match/capture registers n */
+#define SCT_REGMH_MASK              (0xffff << SCT_REGMH_SHIFT)
+#  define SCT_REGMH(n)              (1 << (SCT_REGMH_SHIFT+(n)))
+
+/* SCT match/capture registers mode register low 16-bit (all 16-bits)*/
+
+#define SCT_REGM(n)                 (1 << (n))
+
+/* SCT output register */
+
+#define SCT_OUTU(n)                 (1 << (n)) /* Bits 0-15: Set output n */
+
+/* SCT output counter direction control register */
+
+#define SCT_OUTDIRC_UNCOND          (0)        /* Set and clear do not depend on any counter */
+#define SCT_OUTDIRC_REVU            (1)        /* Reversed when unified counter is counting down */
+#define SCT_OUTDIRC_REVL            (1)        /* Reversed when L counter is counting down */
+#define SCT_OUTDIRC_REVH            (2)        /* Reversed when H counter is counting down */
+
+#define SCT_OUTDIRC_SETCLR_SHIFT(c) ((c) << 1)
+#define SCT_OUTDIRC_SETCLR_SHIFT(c) (3 << SCT_OUTDIRC_SETCLR_SHIFT(c))
+#  define SCT_OUTDIRC_SETCLR(c,n)   ((n) << SCT_OUTDIRC_SETCLR_SHIFT(c))
+
+#define SCT_OUTDIRC_SETCLR0_SHIFT   (0)       /* Bits 0-1: Set/clear operation on output 0 */
+#define SCT_OUTDIRC_SETCLR0_MASK    (3 << SCT_OUTDIRC_SETCLR0_SHIFT)
+#  define SCT_OUTDIRC_SETCLR0(n)    ((n) << SCT_OUTDIRC_SETCLR0_SHIFT)
+#define SCT_OUTDIRC_SETCLR1_SHIFT   (2)       /* Bits 2-3: Set/clear operation on output 1 */
+#define SCT_OUTDIRC_SETCLR1_MASK    (3 << SCT_OUTDIRC_SETCLR1_SHIFT)
+#  define SCT_OUTDIRC_SETCLR1(n)    ((n) << SCT_OUTDIRC_SETCLR1_SHIFT)
+#define SCT_OUTDIRC_SETCLR2_SHIFT   (4)       /* Bits 4-5: Set/clear operation on output 2 */
+#define SCT_OUTDIRC_SETCLR2_MASK    (3 << SCT_OUTDIRC_SETCLR2_SHIFT)
+#  define SCT_OUTDIRC_SETCLR2(n)    ((n) << SCT_OUTDIRC_SETCLR2_SHIFT)
+#define SCT_OUTDIRC_SETCLR3_SHIFT   (6)       /* Bits 6-7: Set/clear operation on output 3 */
+#define SCT_OUTDIRC_SETCLR3_MASK    (3 << SCT_OUTDIRC_SETCLR3_SHIFT)
+#  define SCT_OUTDIRC_SETCLR3(n)    ((n) << SCT_OUTDIRC_SETCLR3_SHIFT)
+#define SCT_OUTDIRC_SETCLR4_SHIFT   (8)       /* Bits 8-9: Set/clear operation on output 4 */
+#define SCT_OUTDIRC_SETCLR4_MASK    (3 << SCT_OUTDIRC_SETCLR4_SHIFT)
+#  define SCT_OUTDIRC_SETCLR4(n)    ((n) << SCT_OUTDIRC_SETCLR4_SHIFT)
+#define SCT_OUTDIRC_SETCLR5_SHIFT   (10)       /* Bits 10-11: Set/clear operation on output 5 */
+#define SCT_OUTDIRC_SETCLR5_MASK    (3 << SCT_OUTDIRC_SETCLR5_SHIFT)
+#  define SCT_OUTDIRC_SETCLR5(n)    ((n) << SCT_OUTDIRC_SETCLR5_SHIFT)
+#define SCT_OUTDIRC_SETCLR6_SHIFT   (12)       /* Bits 12-13: Set/clear operation on output 6 */
+#define SCT_OUTDIRC_SETCLR6_MASK    (3 << SCT_OUTDIRC_SETCLR6_SHIFT)
+#  define SCT_OUTDIRC_SETCLR6(n)    ((n) << SCT_OUTDIRC_SETCLR6_SHIFT)
+#define SCT_OUTDIRC_SETCLR7_SHIFT   (14)       /* Bits 14-15: Set/clear operation on output 7 */
+#define SCT_OUTDIRC_SETCLR7_MASK    (3 << SCT_OUTDIRC_SETCLR7_SHIFT)
+#  define SCT_OUTDIRC_SETCLR7(n)    ((n) << SCT_OUTDIRC_SETCLR7_SHIFT)
+#define SCT_OUTDIRC_SETCLR8_SHIFT   (16)       /* Bits 16-17: Set/clear operation on output 8 */
+#define SCT_OUTDIRC_SETCLR8_MASK    (3 << SCT_OUTDIRC_SETCLR8_SHIFT)
+#  define SCT_OUTDIRC_SETCLR8(n)    ((n) << SCT_OUTDIRC_SETCLR8_SHIFT)
+#define SCT_OUTDIRC_SETCLR9_SHIFT   (18)       /* Bits 18-19: Set/clear operation on output 9 */
+#define SCT_OUTDIRC_SETCLR9_MASK    (3 << SCT_OUTDIRC_SETCLR9_SHIFT)
+#  define SCT_OUTDIRC_SETCLR9(n)    ((n) << SCT_OUTDIRC_SETCLR9_SHIFT)
+#define SCT_OUTDIRC_SETCLR10_SHIFT  (20)       /* Bits 20-21: Set/clear operation on output 10 */
+#define SCT_OUTDIRC_SETCLR10_MASK   (3 << SCT_OUTDIRC_SETCLR10_SHIFT)
+#  define SCT_OUTDIRC_SETCLR10(n)   ((n) << SCT_OUTDIRC_SETCLR10_SHIFT)
+#define SCT_OUTDIRC_SETCLR11_SHIFT  (22)       /* Bits 22-23: Set/clear operation on output 11 */
+#define SCT_OUTDIRC_SETCLR11_MASK   (3 << SCT_OUTDIRC_SETCLR11_SHIFT)
+#  define SCT_OUTDIRC_SETCLR11(n)   ((n) << SCT_OUTDIRC_SETCLR11_SHIFT)
+#define SCT_OUTDIRC_SETCLR12_SHIFT  (24)       /* Bits 24-25: Set/clear operation on output 12 */
+#define SCT_OUTDIRC_SETCLR12_MASK   (3 << SCT_OUTDIRC_SETCLR12_SHIFT)
+#  define SCT_OUTDIRC_SETCLR12(n)   ((n) << SCT_OUTDIRC_SETCLR12_SHIFT)
+#define SCT_OUTDIRC_SETCLR13_SHIFT  (26)       /* Bits 26-27: Set/clear operation on output 13 */
+#define SCT_OUTDIRC_SETCLR13_MASK   (3 << SCT_OUTDIRC_SETCLR13_SHIFT)
+#  define SCT_OUTDIRC_SETCLR13(n)   ((n) << SCT_OUTDIRC_SETCLR13_SHIFT)
+#define SCT_OUTDIRC_SETCLR14_SHIFT  (28)       /* Bits 28-29: Set/clear operation on output 14 */
+#define SCT_OUTDIRC_SETCLR14_MASK   (3 << SCT_OUTDIRC_SETCLR14_SHIFT)
+#  define SCT_OUTDIRC_SETCLR14(n)   ((n) << SCT_OUTDIRC_SETCLR14_SHIFT)
+#define SCT_OUTDIRC_SETCLR15_SHIFT  (30)       /* Bits 30-31: Set/clear operation on output 15 */
+#define SCT_OUTDIRC_SETCLR15_MASK   (3 << SCT_OUTDIRC_SETCLR15_SHIFT)
+#  define SCT_OUTDIRC_SETCLR15(n)   ((n) << SCT_OUTDIRC_SETCLR15_SHIFT)
+
+/* SCT conflict resolution register */
+
+#define SCT_RES_NOCHANGE            (0)        /* No change */
+#define SCT_RES_SET                 (1)        /* Set output */
+#define SCT_RES_CLEAR               (1)        /* Clear output */
+#define SCT_RES_TOGGLE              (2)        /* Toggle output */
+
+#define SCT_RES_OUT_SHIFT(c)        ((c) << 1)
+#define SCT_RES_OUT_SHIFT(c)        (3 << SCT_RES_OUT_SHIFT(c))
+#  define SCT_RES_OUT(c,n)          ((n) << SCT_RES_OUT_SHIFT(c))
+
+#define SCT_RES_OUT0_SHIFT          (0)       /* Bits 0-1: Effect of simultaneous set and clear on output 0 */
+#define SCT_RES_OUT0_MASK           (3 << SCT_RES_OUT0_SHIFT)
+#  define SCT_RES_OUT0(n)           ((n) << SCT_RES_OUT0_SHIFT)
+#define SCT_RES_OUT1_SHIFT          (2)       /* Bits 2-3: Effect of simultaneous set and clear on output 1 */
+#define SCT_RES_OUT1_MASK           (3 << SCT_RES_OUT1_SHIFT)
+#  define SCT_RES_OUT1(n)           ((n) << SCT_RES_OUT1_SHIFT)
+#define SCT_RES_OUT2_SHIFT          (4)       /* Bits 4-5: Effect of simultaneous set and clear on output 2 */
+#define SCT_RES_OUT2_MASK           (3 << SCT_RES_OUT2_SHIFT)
+#  define SCT_RES_OUT2(n)           ((n) << SCT_RES_OUT2_SHIFT)
+#define SCT_RES_OUT3_SHIFT          (6)       /* Bits 6-7: Effect of simultaneous set and clear on output 3 */
+#define SCT_RES_OUT3_MASK           (3 << SCT_RES_OUT3_SHIFT)
+#  define SCT_RES_OUT3(n)           ((n) << SCT_RES_OUT3_SHIFT)
+#define SCT_RES_OUT4_SHIFT          (8)       /* Bits 8-9: Effect of simultaneous set and clear on output 4 */
+#define SCT_RES_OUT4_MASK           (3 << SCT_RES_OUT4_SHIFT)
+#  define SCT_RES_OUT4(n)           ((n) << SCT_RES_OUT4_SHIFT)
+#define SCT_RES_OUT5_SHIFT          (10)       /* Bits 10-11: Effect of simultaneous set and clear on output 5 */
+#define SCT_RES_OUT5_MASK           (3 << SCT_RES_OUT5_SHIFT)
+#  define SCT_RES_OUT5(n)           ((n) << SCT_RES_OUT5_SHIFT)
+#define SCT_RES_OUT6_SHIFT          (12)       /* Bits 12-13: Effect of simultaneous set and clear on output 6 */
+#define SCT_RES_OUT6_MASK           (3 << SCT_RES_OUT6_SHIFT)
+#  define SCT_RES_OUT6(n)           ((n) << SCT_RES_OUT6_SHIFT)
+#define SCT_RES_OUT7_SHIFT          (14)       /* Bits 14-15: Effect of simultaneous set and clear on output 7 */
+#define SCT_RES_OUT7_MASK           (3 << SCT_RES_OUT7_SHIFT)
+#  define SCT_RES_OUT7(n)           ((n) << SCT_RES_OUT7_SHIFT)
+#define SCT_RES_OUT8_SHIFT          (16)       /* Bits 16-17: Effect of simultaneous set and clear on output 8 */
+#define SCT_RES_OUT8_MASK           (3 << SCT_RES_OUT8_SHIFT)
+#  define SCT_RES_OUT8(n)           ((n) << SCT_RES_OUT8_SHIFT)
+#define SCT_RES_OUT9_SHIFT          (18)       /* Bits 18-19: Effect of simultaneous set and clear on output 9 */
+#define SCT_RES_OUT9_MASK           (3 << SCT_RES_OUT9_SHIFT)
+#  define SCT_RES_OUT9(n)           ((n) << SCT_RES_OUT9_SHIFT)
+#define SCT_RES_OUT10_SHIFT         (20)       /* Bits 20-21: Effect of simultaneous set and clear on output 10 */
+#define SCT_RES_OUT10_MASK          (3 << SCT_RES_OUT10_SHIFT)
+#  define SCT_RES_OUT10(n)          ((n) << SCT_RES_OUT10_SHIFT)
+#define SCT_RES_OUT11_SHIFT         (22)       /* Bits 22-23: Effect of simultaneous set and clear on output 11 */
+#define SCT_RES_OUT11_MASK          (3 << SCT_RES_OUT11_SHIFT)
+#  define SCT_RES_OUT11(n)          ((n) << SCT_RES_OUT11_SHIFT)
+#define SCT_RES_OUT12_SHIFT         (24)       /* Bits 24-25: Effect of simultaneous set and clear on output 12 */
+#define SCT_RES_OUT12_MASK          (3 << SCT_RES_OUT12_SHIFT)
+#  define SCT_RES_OUT12(n)          ((n) << SCT_RES_OUT12_SHIFT)
+#define SCT_RES_OUT13_SHIFT         (26)       /* Bits 26-27: Effect of simultaneous set and clear on output 13 */
+#define SCT_RES_OUT13_MASK          (3 << SCT_RES_OUT13_SHIFT)
+#  define SCT_RES_OUT13(n)          ((n) << SCT_RES_OUT13_SHIFT)
+#define SCT_RES_OUT14_SHIFT         (28)       /* Bits 28-29: Effect of simultaneous set and clear on output 14 */
+#define SCT_RES_OUT14_MASK          (3 << SCT_RES_OUT14_SHIFT)
+#  define SCT_RES_OUT14(n)          ((n) << SCT_RES_OUT14_SHIFT)
+#define SCT_RES_OUT15_SHIFT         (30)       /* Bits 30-31: Effect of simultaneous set and clear on output 15 */
+#define SCT_RES_OUT15_MASK          (3 << SCT_RES_OUT15_SHIFT)
+#  define SCT_RES_OUT15(n)          ((n) << SCT_RES_OUT15_SHIFT)
+
+/* SCT DMA request 0/1 registers */
+
+#define SCT_DMAREQ_DEV_SHIFT        (0)       /* Bits 0-15:  Event n sets DMA request */
+#define SCT_DMAREQ_DEV_MASK         (0xffff << SCT_DMAREQ_DEV_SHIFT)
+#  define SCT_DMAREQ_DEV(n)         (1 << ((n) + SCT_DMAREQ_DEV_SHIFT))
+                                              /* Bits 16-29: Reserved */
+#define SCT_DMAREQ_DRL              (1 << 30) /* Bit 30: DMA request when counter reloaded */
+#define SCT_DMAREQ_DRQ              (1 << 31) /* Bit 31: State of DMA Request */
+
+/* SCT event enable register */
+
+#define SCT_EVEN_SHIFT              (0)       /* Bits 0-15:  Enable event n interrupts */
+#define SCT_EVEN_MASK               (0xffff << SCT_EVEN_SHIFT)
+#  define SCT_EVEN(n)               (1 << ((n) + SCT_EVEN_SHIFT))
+                                              /* Bits 1-31: Reserved */
+/* SCT event flag register */
+
+#define SCT_EVFLAG_SHIFT            (0)       /* Bits 0-15:  Event n status */
+#define SCT_EVFLAG_MASK             (0xffff << SCT_EVFLAG_SHIFT)
+#  define SCT_EVFLAG(n)             (1 << ((n) + SCT_EVFLAG_SHIFT))
+                                              /* Bits 1-31: Reserved */
+/* SCT conflict enable register */
+
+#define SCT_CONEN_SHIFT             (0)       /* Bits 0-15:  Event n conflict interrupts */
+#define SCT_CONEN_MASK              (0xffff << SCT_CONEN_SHIFT)
+#  define SCT_CONEN(n)              (1 << ((n) + SCT_CONEN_SHIFT))
+                                              /* Bits 1-31: Reserved */
+/* SCT conflict flag register */
+
+#define SCT_CONFLAG_DEV_SHIFT       (0)       /* Bits 0-15:  No-change conflict on output n */
+#define SCT_CONFLAG_DEV_MASK        (0xffff << SCT_CONFLAG_DEV_SHIFT)
+#  define SCT_CONFLAG_DEV(n)        (1 << ((n) + SCT_CONFLAG_DEV_SHIFT))
+                                              /* Bits 16-29: Reserved */
+#define SCT_CONFLAG_BUSERRU         (1 << 30) /* Bit 30: Unified counter bus error */
+#define SCT_CONFLAG_BUSERRL         (1 << 30) /* Bit 30: L counter bus error bus error */
+#define SCT_CONFLAG_BUSERRH         (1 << 31) /* Bit 31: H counter bus error bus error */
+
+/* SCT match value register of match channels 0-15 (all 32-bits for unified counter) */
+/* SCT match alias register of match channels 0-15 (all 32-bits for unified counter) */
+
+#define SCT_MATCHL_SHIFT            (0)       /* Bits 0-15: L match value */
+#define SCT_MATCHL_MASK             (0xffff << SCT_MATCHL_SHIFT)
+#define SCT_MATCHH_SHIFT            (16)      /* Bits 16-31: H match value */
+#define SCT_MATCHH_MASK             (0xffff << SCT_MATCHH_SHIFT)
+
+/* SCT high/low match value register of match channels 0-15 */
+/* SCT high/low match alias register of match channels 0-15 */
+
+#define SCT_MATCH_SHIFT             (0)       /* Bits 0-15: match value */
+#define SCT_MATCH_MASK              (0xffff << SCT_MATCH_SHIFT))
+
+/* SCT match reload register of match channels 0-15 (all 32-bits for unified counter) */
+/* SCT match reload alias register of match channels 0-15 (all 32-bits for unified counter) */
+
+#define SCT_RELOADL_SHIFT           (0)       /* Bits 0-15: L reload value */
+#define SCT_RELOADL_MASK            (0xffff << SCT_RELOADL_SHIFT)
+#define SCT_RELOADH_SHIFT           (16)      /* Bits 16-31: H reload value */
+#define SCT_RELOADH_MASK            (0xffff << SCT_RELOADH_SHIFT)
+
+/* SCT high/low match reload register of match channels 0-15 */
+/* SCT high/low match reload alias register of match channels 0-15 */
+
+#define SCT_RELOAD_SHIFT            (0)       /* Bits 0-15: Reload value */
+#define SCT_RELOAD_MASK             (0xffff << SCT_RELOAD_SHIFT)
+
+/* SCT capture value register of capture channels 0-15 (all 32-bits for unified counter) */
+/* SCT capture alias register of capture channels 0-15 (all 32-bits for unified counter) */
+
+#define SCT_CAPL_SHIFT              (0)       /* Bits 0-15: L capture value */
+#define SCT_CAPL_MASK               (0xffff << SCT_CAPL_SHIFT)
+#define SCT_CAPH_SHIFT              (16)      /* Bits 16-31: H capture value */
+#define SCT_CAPH_MASK               (0xffff << SCT_CAPH_SHIFT)
+
+/* SCT high/low capture value register of capture channels 0-15 */
+/* SCT high/low capture alias register of capture channels 0-15 */
+
+#define SCT_CAP_SHIFT               (0)       /* Bits 0-15: Capture value */
+#define SCT_CAP_MASK                (0xffff << SCT_CAP_SHIFT)
+
+/* SCT capture control register of capture channels 0-15 (all 32-bits for unified counter) */
+/* SCT capture control alias register of capture channels 0-15 (all 32-bits for unified counter) */
+
+#define SCT_CAPCONU(n)              (1 << (n))
+#define SCT_CAPCONL_SHIFT           (0)       /* Bits 0-15: L capture controls */
+#define SCT_CAPCONL_MASK            (0xffff << SCT_CAPCONL_SHIFT)
+#  define SCT_CAPCONL(n)            (1 << ((n)+SCT_CAPCONL_SHIFT))
+#define SCT_CAPCONH_SHIFT           (16)      /* Bits 16-31: H capture controls */
+#define SCT_CAPCONH_MASK            (0xffff << SCT_CAPCONH_SHIFT)
+#  define SCT_CAPCONH(n)            (1 << ((n)+SCT_CAPCONH_SHIFT))
+
+/* SCT high/low capture control register of capture channels 0-15 */
+/* SCT high/low capture control alias register of capture channels 0-15 */
+
+#define SCT_CAPCON_SHIFT            (0)       /* Bits 0-15: Capture controls */
+#define SCT_CAPCON_MASK             (0xffff << SCT_CAPCON_SHIFT)
+#  define SCT_CAPCON(n)             (1 << ((n)+SCT_CAPCON_SHIFT))
+
+/* SCT event state mask registers 0 to 15 */
+
+#define SCT_EVSM(n)                 (1 << (n))
+
+/* SCT event control registers 0 to 15 */
+
+#define SCT_EVC_MATCHSEL_SHIFT      (0)       /* Bits 0-3: Selects Match register associated event */
+#define SCT_EVC_MATCHSEL_MASK       (15 << SCT_EVC_MATCHSEL_SHIFT)
+#define SCT_EVC_HEVENT              (1 << 4)  /* Bit 4:  Select L/H counter */
+#define SCT_EVC_OUTSEL              (1 << 5)  /* Bit 5:  Input/output select*/
+#define SCT_EVC_IOSEL_SHIFT         (6)       /* Bits 6-9: Selects input or output signal associated event */
+#define SCT_EVC_IOSEL_MASK          (15 << SCT_EVC_IOSEL_SHIFT)
+#define SCT_EVC_IOCOND_SHIFT        (10)      /* Bits 10-11: Selects I/O condition for event n */
+#define SCT_EVC_IOCOND_MASK         (3 << SCT_EVC_IOCOND_SHIFT)
+#  define SCT_EVC_IOCOND_LOW        (0 << SCT_EVC_IOCOND_SHIFT)
+#  define SCT_EVC_IOCOND_RISE       (1 << SCT_EVC_IOCOND_SHIFT)
+#  define SCT_EVC_IOCOND_FALL       (2 << SCT_EVC_IOCOND_SHIFT)
+#  define SCT_EVC_IOCOND_HIGH       (3 << SCT_EVC_IOCOND_SHIFT)
+#define SCT_EVC_COMBMODE_SHIFT      (12)      /* Bits 12-13: Match and I/O condition usage */
+#define SCT_EVC_COMBMODE_MASK       (3 << SCT_EVC_COMBMODE_SHIFT)
+#  define SCT_EVC_COMBMODE_OR       (0 << SCT_EVC_COMBMODE_SHIFT)
+#  define SCT_EVC_COMBMODE_MATCH    (1 << SCT_EVC_COMBMODE_SHIFT)
+#  define SCT_EVC_COMBMODE_IO       (2 << SCT_EVC_COMBMODE_SHIFT)
+#  define SCT_EVC_COMBMODE_AND      (3 << SCT_EVC_COMBMODE_SHIFT)
+#define SCT_EVC_STATELD             (1 << 14)  /* Bit 14:  STATEV control */
+#define SCT_EVC_STATEV_SHIFT        (15)       /* Bits 15-19: State value */
+#define SCT_EVC_STATEV_MASK         (31 << SCT_EVC_STATEV_SHIFT)
+                                               /* Bits 20-31: Reserved */
+/* SCT output set registers 0 to 15 */
+
+#define SCT_OUTSET_SHIFT            (0)        /* Bits 0-15: Bit m selects event m to set output n */
+#define SCT_OUTSET_MASK             (0xffff << SCT_OUTSET_SHIFT)
+#  define SCT_OUTSET_MASK(m)        (1 << ((n)SCT_OUTSET_SHIFT))
+                                               /* Bits 16-31: Reserved */
+/* SCT output clear registers 0 to 15 */
+
+#define SCT_OUTCLR_SHIFT            (0)        /* Bits 0-15: Bit m selects event m to clear output n */
+#define SCT_OUTCLR_MASK             (0xffff << SCT_OUTCLR_SHIFT)
+#  define SCT_OUTCLR_MASK(m)        (1 << ((n)SCT_OUTCLR_SHIFT))
+                                               /* Bits 16-31: Reserved */
+
+/****************************************************************************************************
+ * Public Types
+ ****************************************************************************************************/
+
+/****************************************************************************************************
+ * Public Data
+ ****************************************************************************************************/
+
+/****************************************************************************************************
+ * Public Functions
+ ****************************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_SCT_H */
diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_scu.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_scu.h
new file mode 100644
index 000000000..d9dfe1ce9
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_scu.h
@@ -0,0 +1,435 @@
+/****************************************************************************************************
+ * arch/arm/src/lpc43xx/chip/lpc43_scu.h
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_SCU_SCU_H
+#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_SCU_SCU_H
+
+/****************************************************************************************************
+ * Included Files
+ ****************************************************************************************************/
+
+#include <nuttx/config.h>
+
+/****************************************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************************************/
+/* Register Offsets *********************************************************************************/
+
+/* Pin Groups */
+
+#define SPSP0                          0
+#define SPSP1                          1
+#define SPSP2                          2
+#define SPSP3                          3
+#define SPSP4                          4
+#define SPSP5                          5
+#define SPSP6                          6
+#define SPSP7                          7
+#define SPSP8                          8
+#define SPSP9                          9
+#define SPSP10                        10
+#define SPSP11                        11
+#define SPSP12                        12
+#define SPSP13                        13
+#define SPSP14                        14
+#define SPSP15                        15
+
+#define LPC43_SCU_SFSP_OFFSET(p,n)    (((p) << 7) | ((n) << 2))
+#define LPC43_SCU_SFSP0_OFFSET(n)     (0x0000 | ((n) << 2))
+#define LPC43_SCU_SFSP1_OFFSET(n)     (0x0080 | ((n) << 2))
+#define LPC43_SCU_SFSP2_OFFSET(n)     (0x0100 | ((n) << 2))
+#define LPC43_SCU_SFSP3_OFFSET(n)     (0x0180 | ((n) << 2))
+#define LPC43_SCU_SFSP4_OFFSET(n)     (0x0200 | ((n) << 2))
+#define LPC43_SCU_SFSP5_OFFSET(n)     (0x0280 | ((n) << 2))
+#define LPC43_SCU_SFSP6_OFFSET(n)     (0x0300 | ((n) << 2))
+#define LPC43_SCU_SFSP7_OFFSET(n)     (0x0380 | ((n) << 2))
+#define LPC43_SCU_SFSP8_OFFSET(n)     (0x0400 | ((n) << 2))
+#define LPC43_SCU_SFSP9_OFFSET(n)     (0x0480 | ((n) << 2))
+#define LPC43_SCU_SFSPA_OFFSET(n)     (0x0500 | ((n) << 2))
+#define LPC43_SCU_SFSPB_OFFSET(n)     (0x0580 | ((n) << 2))
+#define LPC43_SCU_SFSPC_OFFSET(n)     (0x0600 | ((n) << 2))
+#define LPC43_SCU_SFSPD_OFFSET(n)     (0x0680 | ((n) << 2))
+#define LPC43_SCU_SFSPE_OFFSET(n)     (0x0700 | ((n) << 2))
+#define LPC43_SCU_SFSPF_OFFSET(n)     (0x0780 | ((n) << 2))
+
+/* CLKn pins */
+
+#define SFSCLK0                       0
+#define SFSCLK1                       1
+#define SFSCLK2                       2
+#define SFSCLK3                       3
+
+#define LPC43_SCU_SFSCLK_OFFSET(n)    (0x0c00 | ((n) << 2))
+#define LPC43_SCU_SFSCLK0_OFFSET      0x0c00
+#define LPC43_SCU_SFSCLK1_OFFSET      0x0c04
+#define LPC43_SCU_SFSCLK2_OFFSET      0x0c08
+#define LPC43_SCU_SFSCLK3_OFFSET      0x0c0c
+
+/* USB1 USB1_DP/USB1_DM pins and I2C-bus open-drain pins */
+
+#define LPC43_SCU_SFSUSB_OFFSET       0x0c80
+#define LPC43_SCU_SFSI2C0_OFFSET      0x0c84
+
+/* ADC pin select registers */
+
+#define ENAIO0                        0
+#define ENAIO1                        1
+#define ENAIO2                        2
+
+#define LPC43_SCU_ENAIO_OFFSET(n)     (0x0c88 | ((n) << 2))
+#define LPC43_SCU_ENAIO0_OFFSET       0x0c88
+#define LPC43_SCU_ENAIO1_OFFSET       0x0c8c
+#define LPC43_SCU_ENAIO2_OFFSET       0x0c90
+
+/* EMC delay register */
+
+#define LPC43_SCU_EMCDELAYCLK_OFFSET  0x0d00
+
+/* Pin interrupt select registers */
+
+#define PINTSEL0                      0
+#define PINTSEL1                      1
+
+#define LPC43_SCU_PINTSEL_OFFSET(n)   (0x0e00 | ((n) << 2))
+#define LPC43_SCU_PINTSEL0_OFFSET     0x0e00
+#define LPC43_SCU_PINTSEL1_OFFSET     0x0e04
+
+/* Register Addresses *******************************************************************************/
+
+/* Pin Groups */
+
+#define LPC43_SCU_SFSP(p,n)           (LPC43_SCU_BASE+LPC43_SCU_SFSP_OFFSET(p,n))
+#define LPC43_SCU_SFSP0(n)            (LPC43_SCU_BASE+LPC43_SCU_SFSP0_OFFSET(n))
+#define LPC43_SCU_SFSP1(n)            (LPC43_SCU_BASE+LPC43_SCU_SFSP1_OFFSET(n))
+#define LPC43_SCU_SFSP2(n)            (LPC43_SCU_BASE+LPC43_SCU_SFSP2_OFFSET(n))
+#define LPC43_SCU_SFSP3(n)            (LPC43_SCU_BASE+LPC43_SCU_SFSP3_OFFSET(n))
+#define LPC43_SCU_SFSP4(n)            (LPC43_SCU_BASE+LPC43_SCU_SFSP4_OFFSET(n))
+#define LPC43_SCU_SFSP5(n)            (LPC43_SCU_BASE+LPC43_SCU_SFSP5_OFFSET(n))
+#define LPC43_SCU_SFSP6(n)            (LPC43_SCU_BASE+LPC43_SCU_SFSP6_OFFSET(n))
+#define LPC43_SCU_SFSP7(n)            (LPC43_SCU_BASE+LPC43_SCU_SFSP7_OFFSET(n))
+#define LPC43_SCU_SFSP8(n)            (LPC43_SCU_BASE+LPC43_SCU_SFSP8_OFFSET(n))
+#define LPC43_SCU_SFSP9(n)            (LPC43_SCU_BASE+LPC43_SCU_SFSP9_OFFSET(n))
+#define LPC43_SCU_SFSPA(n)            (LPC43_SCU_BASE+LPC43_SCU_SFSPA_OFFSET(n))
+#define LPC43_SCU_SFSPB(n)            (LPC43_SCU_BASE+LPC43_SCU_SFSPB_OFFSET(n))
+#define LPC43_SCU_SFSPC(n)            (LPC43_SCU_BASE+LPC43_SCU_SFSPC_OFFSET(n))
+#define LPC43_SCU_SFSPD(n)            (LPC43_SCU_BASE+LPC43_SCU_SFSPD_OFFSET(n))
+#define LPC43_SCU_SFSPE(n)            (LPC43_SCU_BASE+LPC43_SCU_SFSPE_OFFSET(n))
+#define LPC43_SCU_SFSPF(n)            (LPC43_SCU_BASE+LPC43_SCU_SFSPF_OFFSET(n))
+
+/* CLKn pins */
+
+#define LPC43_SCU_SFSCLK(n)           (LPC43_SCU_BASE+LPC43_SCU_SFSCLK_OFFSET(n))
+#define LPC43_SCU_SFSCLK0             (LPC43_SCU_BASE+LPC43_SCU_SFSCLK0_OFFSET)
+#define LPC43_SCU_SFSCLK1             (LPC43_SCU_BASE+LPC43_SCU_SFSCLK1_OFFSET)
+#define LPC43_SCU_SFSCLK2             (LPC43_SCU_BASE+LPC43_SCU_SFSCLK2_OFFSET)
+#define LPC43_SCU_SFSCLK3             (LPC43_SCU_BASE+LPC43_SCU_SFSCLK3_OFFSET)
+
+/* USB1 USB1_DP/USB1_DM pins and I2C-bus open-drain pins */
+
+#define LPC43_SCU_SFSUSB              (LPC43_SCU_BASE+LPC43_SCU_SFSUSB_OFFSET)
+#define LPC43_SCU_SFSI2C0             (LPC43_SCU_BASE+LPC43_SCU_SFSI2C0_OFFSET)
+
+/* ADC pin select registers */
+
+#define LPC43_SCU_ENAIO(n)            (LPC43_SCU_BASE+LPC43_SCU_ENAIO_OFFSET(n))
+#define LPC43_SCU_ENAIO0              (LPC43_SCU_BASE+LPC43_SCU_ENAIO0_OFFSET)
+#define LPC43_SCU_ENAIO1              (LPC43_SCU_BASE+LPC43_SCU_ENAIO1_OFFSET)
+#define LPC43_SCU_ENAIO2              (LPC43_SCU_BASE+LPC43_SCU_ENAIO2_OFFSET)
+
+/* EMC delay register */
+
+#define LPC43_SCU_EMCDELAYCLK         (LPC43_SCU_BASE+LPC43_SCU_EMCDELAYCLK_OFFSET)
+
+/* Pin interrupt select registers */
+
+#define LPC43_SCU_PINTSEL(n)          (LPC43_SCU_BASE+LPC43_SCU_PINTSEL_OFFSET(n))
+#define LPC43_SCU_PINTSEL0            (LPC43_SCU_BASE+LPC43_SCU_PINTSEL0_OFFSET)
+#define LPC43_SCU_PINTSEL1            (LPC43_SCU_BASE+LPC43_SCU_PINTSEL1_OFFSET)
+
+/* Register Bit Definitions *************************************************************************/
+/* Common Pin configuration register bit settings */
+
+#define SCU_PIN_MODE_SHIFT            (0)       /* Bits 0-2: Select pin function */
+#define SCU_PIN_MODE_MASK             (7 << SCU_PIN_MODE_SHIFT)
+#  define SCU_PIN_MODE_FUNC(n)        ((n) << SCU_PIN_MODE_SHIFT)
+#  define SCU_PIN_MODE_FUNC0          (0 << SCU_PIN_MODE_SHIFT) /* Function 0 (default) */
+#  define SCU_PIN_MODE_FUNC1          (1 << SCU_PIN_MODE_SHIFT) /* Function 1 */
+#  define SCU_PIN_MODE_FUNC2          (2 << SCU_PIN_MODE_SHIFT) /* Function 2 */
+#  define SCU_PIN_MODE_FUNC3          (3 << SCU_PIN_MODE_SHIFT) /* Function 3 */
+#  define SCU_PIN_MODE_FUNC4          (4 << SCU_PIN_MODE_SHIFT) /* Function 4 */
+#  define SCU_PIN_MODE_FUNC5          (5 << SCU_PIN_MODE_SHIFT) /* Function 5 */
+#  define SCU_PIN_MODE_FUNC6          (6 << SCU_PIN_MODE_SHIFT) /* Function 6 */
+#  define SCU_PIN_MODE_FUNC7          (7 << SCU_PIN_MODE_SHIFT) /* Function 7 */
+#define SCU_PIN_EPD                   (1 << 3)  /* Bit 3:  Enable pull-down resistor at pad */
+#define SCU_PIN_EPUN                  (1 << 4)  /* Bit 4:  Disable pull-up resistor at pad */
+                                                /* Bit 5:  Usage varies with pin type */
+#define SCU_PIN_EZI                   (1 << 6)  /* Bit 6:  Input buffer enable */
+#define SCU_PIN_ZIF                   (1 << 7)  /* Bit 7:  Input glitch filter */
+                                                /* Bits 8-9: Usage varies with pin type */
+                                                /* Bits 10-31: Reserved */
+/* Pin configuration registers for normal-drive pins (only):
+ *
+ *   P0_0 and P0_1
+ *   P1_0 to P1_16 and P1_18 to P1_20
+ *   P2_0 to P2_2 and P2_6 to P2_13
+ *   P3_0 to P3_2 and P3_4 to P3_8
+ *   P4_0 to P4_10
+ *   P5_0 to P5_7
+ *   P6_0 to P6_12
+ *   P7_0 to P7_7
+ *   P8_3 to P8_8
+ *   P9_0 to P9_6
+ *   PA_0 and PA_4
+ *   PB_0 to PB_6
+ *   PC_0 to PC_14
+ *   PE_0 to PE_15
+ *   PF_0 to PF_11
+ */
+                                                /* Bits 0-4: Same as common bit definitions */
+#define SCU_NDPIN_EHS                 (1 << 5)  /* Bit 5:  EHS Select Slew rate */
+                                                /* Bits 6-31: Same as common bit definitions */
+/* Pin configuration registers for high-drive pins
+ *
+ *   P1_17
+ *   P2_3 to P2_5
+ *   P8_0 to P8_2
+ *   PA_1 to PA_3
+ */
+                                                /* Bits 0-7:  Same as common bit definitions */
+#define SCU_HDPIN_EHD_SHIFT           (8)       /* Bits 8-9: Select drive strength */
+#define SCU_HDPIN_EHD_MASK            (3 << SCU_HDPIN_EHD_SHIFT)
+#  define SCU_HDPIN_EHD_NORMAL        (0 << SCU_HDPIN_EHD_SHIFT) /* Normal-drive: 4 mA drive strength */
+#  define SCU_HDPIN_EHD_MEDIUM        (1 << SCU_HDPIN_EHD_SHIFT) /* Medium-drive: 8 mA drive strength */
+#  define SCU_HDPIN_EHD_HIGH          (2 << SCU_HDPIN_EHD_SHIFT) /* High-drive: 14 mA drive strength */
+#  define SCU_HDPIN_EHD_ULTRA         (3 << SCU_HDPIN_EHD_SHIFT) /* Ultra high-drive: 20 mA drive strength */
+                                                /* Bits 10-31:  Reserved */
+/* Pin configuration registers for high-speed pins
+ *
+ * P3_3 and pins CLK0 to CLK3
+ */
+                                                /* Bits 0-4: Same as common bit definitions */
+#define SCU_HSPIN_EHS                 (1 << 5)  /* Bit 5:  EHS Select Slew rate */
+                                                /* Bits 6-31: Same as common bit definitions */
+/* Pin configuration register for USB1 pins USB1_DP/USB1_DM */
+
+#define SCU_SFSUSB_AIM                (1 << 0)  /* Bit 0:  Differential data input AIP/AIM */
+#define SCU_SFSUSB_ESEA               (1 << 1)  /* Bit 1:  Control signal for differential input or single input */
+#define SCU_SFSUSB_EPD                (1 << 2)  /* Bit 2:  Enable pull-down connect */
+                                                /* Bit 3:  Reserved */
+#define SCU_SFSUSB_EPWR               (1 << 4)  /* Bit 4:  Power mode */
+#define SCU_SFSUSB_VBUS               (1 << 5)  /* Bit 5:  Enable the vbus_valid signal */
+                                                /* Bits 6-31:  Reserved */
+/* Pin configuration register for open-drain I2C-bus pins */
+
+#define SCU_SFSI2C0_SCL_EFP           (1 << 0)  /* Bit 0:  Select input glitch filter time constant for the SCL pin */
+                                                /* Bit 1:  Reserved */
+#define SCU_SFSI2C0_SCL_EHD           (1 << 2)  /* Bit 2:  Select I2C mode for the SCL pin */
+#define SCU_SFSI2C0_SCL_EZI           (1 << 3)  /* Bit 3:  Enable the input receiver for the SCL pin */
+                                                /* Bits 4-6: Reserved */
+#define SCU_SFSI2C0_SCL_ZIF           (1 << 7)  /* Bit 7:  Enable or disable input glitch filter for the SCL pin */
+#define SCU_SFSI2C0_SDA_EFP           (1 << 8)  /* Bit 8:  Select input glitch filter time constant for the SDA pin */
+                                                /* Bit 9:  Reserved */
+#define SCU_SFSI2C0_SDA_EHD           (1 << 10) /* Bit 10: Select I2C mode for the SDA pin */
+#define SCU_SFSI2C0_SDA_EZI           (1 << 11) /* Bit 11: Enable the input receiver for the SDA pin */
+                                                /* Bits 12-14: Reserved */
+#define SCU_SFSI2C0_SDA_ZIF           (1 << 15) /* Bit 15: Enable or disable input glitch filter for the SDA pin */
+                                                /* Bits 16-31: Reserved */
+/* ADC0 function select register.  The following pins are controlled by the ENAIO0 register:
+ *
+ *   Pin   ADC function  ENAIO0 register bit
+ *   P4_3  ADC0_0        0
+ *   P4_1  ADC0_1        1
+ *   PF_8  ADC0_2        2
+ *   P7_5  ADC0_3        3
+ *   P7_4  ADC0_4        4
+ *   PF_10 ADC0_5        5
+ *   PB_6  ADC0_6        6
+ */
+
+#define SCU_ENAI00_ADC0(n)            (1 << (n))
+#define SCU_ENAI00_ADC0_0             (1 << 0)  /* Select ADC0_0 */
+#define SCU_ENAI00_ADC0_1             (1 << 1)  /* Select ADC0_1 */
+#define SCU_ENAI00_ADC0_2             (1 << 2)  /* Select ADC0_2 */
+#define SCU_ENAI00_ADC0_3             (1 << 3)  /* Select ADC0_3 */
+#define SCU_ENAI00_ADC0_4             (1 << 4)  /* Select ADC0_4 */
+#define SCU_ENAI00_ADC0_5             (1 << 5)  /* Select ADC0_5 */
+#define SCU_ENAI00_ADC0_6             (1 << 6)  /* Select ADC0_6 */
+
+/* ADC1 function select register.  The following pins are controlled by the ENAIO1 register:
+ *
+ *   Pin   ADC function  ENAIO0 register bit
+ *   PC_3  ADC1_0        0
+ *   PC_0  ADC1_1        1
+ *   PF_9  ADC1_2        2
+ *   PF_6  ADC1_3        3
+ *   PF_5  ADC1_4        4
+ *   PF_11 ADC1_5        5
+ *   P7_7  ADC1_6        6
+ *   PF_7  ADC1_7        7
+ */
+
+#define SCU_ENAI01_ADC1(n)            (1 << (n))
+#define SCU_ENAI01_ADC1_0             (1 << 0)  /* Select ADC1_0 */
+#define SCU_ENAI01_ADC1_1             (1 << 1)  /* Select ADC1_1 */
+#define SCU_ENAI01_ADC1_2             (1 << 2)  /* Select ADC1_2 */
+#define SCU_ENAI01_ADC1_3             (1 << 3)  /* Select ADC1_3 */
+#define SCU_ENAI01_ADC1_4             (1 << 4)  /* Select ADC1_4 */
+#define SCU_ENAI01_ADC1_5             (1 << 5)  /* Select ADC1_5 */
+#define SCU_ENAI01_ADC1_6             (1 << 6)  /* Select ADC1_6 */
+#define SCU_ENAI01_ADC1_7             (1 << 7)  /* Select ADC1_7 */
+
+/* Analog function select register.  The following pins are controlled by the ENAIO2 register:
+ *
+ *   Pin   ADC function         ENAIO0 register bit
+ *   P4_4  DAC                  0
+ *   PF_7  BG (band gap output) 4
+ */
+
+#define SCU_ENAI02_DAC                (1 << 0)  /* Select DAC */
+#define SCU_ENAI02_BG                 (1 << 4)  /* Select band gap output */
+
+/* EMC clock delay register.  The value 0x1111 corresponds to about 0.5 ns of delay */
+
+#define SCU_EMCDELAYCLK_SHIFT         (0)       /* Bits 0-15: EMC_CLKn SDRAM clock output delay */
+#define SCU_EMCDELAYCLK_MASK          (0xffff << SCU_EMCDELAYCLK_SHIFT)
+#  define SCU_EMCDELAYCLK(n)          ((n) << SCU_EMCDELAYCLK_SHIFT) /* 0=no delay, N*0x1111 = N*0.5 ns delay */
+                                                /* Bits 16-31:  Reserved */
+/* Pin interrupt select register 0 */
+
+#define SCU_GPIO_PORT0                0
+#define SCU_GPIO_PORT1                1
+#define SCU_GPIO_PORT2                2
+#define SCU_GPIO_PORT3                3
+#define SCU_GPIO_PORT4                4
+#define SCU_GPIO_PORT5                5
+#define SCU_GPIO_PORT6                6
+#define SCU_GPIO_PORT7                7
+
+#define SCU_GPIO_PIN0                 0
+#define SCU_GPIO_PIN1                 1
+#define SCU_GPIO_PIN2                 2
+#define SCU_GPIO_PIN3                 3
+#define SCU_GPIO_PIN4                 4
+#define SCU_GPIO_PIN5                 5
+#define SCU_GPIO_PIN6                 6
+#define SCU_GPIO_PIN7                 7
+#define SCU_GPIO_PIN8                 8
+#define SCU_GPIO_PIN9                 9
+#define SCU_GPIO_PIN10                10
+#define SCU_GPIO_PIN11                11
+#define SCU_GPIO_PIN12                12
+#define SCU_GPIO_PIN13                13
+#define SCU_GPIO_PIN14                14
+#define SCU_GPIO_PIN15                15
+#define SCU_GPIO_PIN16                16
+#define SCU_GPIO_PIN17                17
+#define SCU_GPIO_PIN18                18
+#define SCU_GPIO_PIN19                19
+#define SCU_GPIO_PIN20                20
+#define SCU_GPIO_PIN21                21
+#define SCU_GPIO_PIN22                22
+#define SCU_GPIO_PIN23                23
+#define SCU_GPIO_PIN24                24
+#define SCU_GPIO_PIN25                25
+#define SCU_GPIO_PIN26                26
+#define SCU_GPIO_PIN27                27
+#define SCU_GPIO_PIN28                28
+#define SCU_GPIO_PIN29                29
+#define SCU_GPIO_PIN30                30
+#define SCU_GPIO_PIN31                31
+
+#define SCU_PINTSEL0_SHIFT(n)         ((n) << 3)
+#define SCU_PINTSEL0_MASK(n)          (0xff << SCU_PINTSEL0_SHIFT(n)))
+#define SCU_PINTSEL0_INTPIN_SHIFT(n)  ((n) << 3)
+#define SCU_PINTSEL0_INTPIN_MASK(n)   (31 << SCU_PINTSEL0_INTPIN_SHIFT(n))
+#define SCU_PINTSEL0_PORTSEL_SHIFT(n) (((n) << 3) + 5)
+#define SCU_PINTSEL0_PORTSEL_MASK(n)  (7 << SCU_PINTSEL0_PORTSEL_SHIFT(n))
+
+#define SCU_PINTSEL0_INTPIN0_SHIFT    (0)       /* Bits 0-4: Pint interrupt 0 */
+#define SCU_PINTSEL0_INTPIN0_MASK     (31 << SCU_PINTSEL0_INTPIN0_SHIFT)
+#define SCU_PINTSEL0_PORTSEL0_SHIFT   (5)       /* Bits 5-7: Pin interrupt 0 */
+#define SCU_PINTSEL0_PORTSEL0_MASK    (7 << SCU_PINTSEL0_PORTSEL0_SHIFT)
+#define SCU_PINTSEL0_INTPIN1_SHIFT    (8)       /* Bits 8-12: Pint interrupt 1 */
+#define SCU_PINTSEL0_INTPIN1_MASK     (31 << SCU_PINTSEL0_INTPIN1_SHIFT)
+#define SCU_PINTSEL0_PORTSEL1_SHIFT   (13)      /* Bits 13-15: Pin interrupt 1 */
+#define SCU_PINTSEL0_PORTSEL1_MASK    (7 << SCU_PINTSEL0_PORTSEL1_SHIFT)
+#define SCU_PINTSEL0_INTPIN2_SHIFT    (16)      /* Bits 16-20: Pint interrupt 2 */
+#define SCU_PINTSEL0_INTPIN2_MASK     (31 << SCU_PINTSEL0_INTPIN2_SHIFT)
+#define SCU_PINTSEL0_PORTSEL2_SHIFT   (21)      /* Bits 21-23: Pin interrupt 2 */
+#define SCU_PINTSEL0_PORTSEL2_MASK    (7 << SCU_PINTSEL0_PORTSEL2_SHIFT)
+#define SCU_PINTSEL0_INTPIN3_SHIFT    (24)      /* Bits 24-28: Pint interrupt 3 */
+#define SCU_PINTSEL0_INTPIN3_MASK     (31 << SCU_PINTSEL0_INTPIN3_SHIFT)
+#define SCU_PINTSEL0_PORTSEL3_SHIFT   (29)      /* Bits 29-31: Pin interrupt 3 */
+#define SCU_PINTSEL0_PORTSEL3_MASK    (7 << SCU_PINTSEL0_PORTSEL3_SHIFT)
+
+/* Pin interrupt select register 1 */
+
+#define SCU_PINTSEL1_SHIFT(n)         (((n) - 4) << 3)
+#define SCU_PINTSEL1_MASK(n)          (0xff << SCU_PINTSEL1_SHIFT(n))
+#define SCU_PINTSEL1_INTPIN_SHIFT(n)  (((n) - 4) << 3)
+#define SCU_PINTSEL1_INTPIN_MASK(n)   (31 << SCU_PINTSEL0_INTPIN_SHIFT(n))
+#define SCU_PINTSEL1_PORTSEL_SHIFT(n) ((((n) - 4) << 3) + 5)
+#define SCU_PINTSEL1_PORTSEL_MASK(n)  (7 << SCU_PINTSEL0_PORTSEL_SHIFT(n))
+
+#define SCU_PINTSEL1_INTPIN4_SHIFT    (0)       /* Bits 0-4: Pint interrupt 4 */
+#define SCU_PINTSEL1_INTPIN4_MASK     (31 << SCU_PINTSEL1_INTPIN4_SHIFT)
+#define SCU_PINTSEL1_PORTSEL4_SHIFT   (5)       /* Bits 5-7: Pin interrupt 4 */
+#define SCU_PINTSEL1_PORTSEL4_MASK    (7 << SCU_PINTSEL1_PORTSEL4_SHIFT)
+#define SCU_PINTSEL1_INTPIN5_SHIFT    (8)       /* Bits 8-12: Pint interrupt 5 */
+#define SCU_PINTSEL1_INTPIN5_MASK     (31 << SCU_PINTSEL1_INTPIN5_SHIFT)
+#define SCU_PINTSEL1_PORTSEL5_SHIFT   (13)       /* Bits 13-15: Pin interrupt 5 */
+#define SCU_PINTSEL1_PORTSEL5_MASK    (7 << SCU_PINTSEL1_PORTSEL5_SHIFT)
+#define SCU_PINTSEL1_INTPIN6_SHIFT    (16)       /* Bits 16-20: Pint interrupt 6 */
+#define SCU_PINTSEL1_INTPIN6_MASK     (31 << SCU_PINTSEL1_INTPIN6_SHIFT)
+#define SCU_PINTSEL1_PORTSEL6_SHIFT   (21)       /* Bits 21-23: Pin interrupt 6 */
+#define SCU_PINTSEL1_PORTSEL6_MASK    (7 << SCU_PINTSEL1_PORTSEL6_SHIFT)
+#define SCU_PINTSEL1_INTPIN7_SHIFT    (24)       /* Bits 24-28: Pint interrupt 7 */
+#define SCU_PINTSEL1_INTPIN7_MASK     (31 << SCU_PINTSEL1_INTPIN7_SHIFT)
+#define SCU_PINTSEL1_PORTSEL7_SHIFT   (29)       /* Bits 29-31: Pin interrupt 7 */
+#define SCU_PINTSEL1_PORTSEL7_MASK    (7 << SCU_PINTSEL1_PORTSEL7_SHIFT)
+
+/****************************************************************************************************
+ * Public Types
+ ****************************************************************************************************/
+
+/****************************************************************************************************
+ * Public Data
+ ****************************************************************************************************/
+
+/****************************************************************************************************
+ * Public Functions
+ ****************************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_SCU_SCU_H */
diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_sdmmc.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_sdmmc.h
new file mode 100644
index 000000000..1236d82f3
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_sdmmc.h
@@ -0,0 +1,391 @@
+/************************************************************************************************
+ * arch/arm/src/lpc43xx/lpc43_sdmmc.h
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_SDMMC_H
+#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_SDMMC_H
+
+/************************************************************************************************
+ * Included Files
+ ************************************************************************************************/
+
+#include <nuttx/config.h>
+
+/************************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************************/
+
+/* MCI register offsets (with respect to the MCI base) ******************************************/
+
+#define LPC43_SDMMC_CTRL_OFFSET          0x0000 /* Control register */
+#define LPC43_SDMMC_PWREN_OFFSET         0x0004 /* Power Enable Register */
+#define LPC43_SDMMC_CLKDIV_OFFSET        0x0008 /* Clock-divider register */
+#define LPC43_SDMMC_CLKSRC_OFFSET        0x000c /* Clock-source register */
+#define LPC43_SDMMC_CLKENA_OFFSET        0x0010 /* Clock-enable register */
+#define LPC43_SDMMC_TMOUT_OFFSET         0x0014 /* Time-out register */
+#define LPC43_SDMMC_CTYPE_OFFSET         0x0018 /* Card-type register */
+#define LPC43_SDMMC_BLKSIZ_OFFSET        0x001c /* Block-size register */
+#define LPC43_SDMMC_BYTCNT_OFFSET        0x0020 /* Byte-count register */
+#define LPC43_SDMMC_INTMASK_OFFSET       0x0024 /* Interrupt-mask register */
+#define LPC43_SDMMC_CMDARG_OFFSET        0x0028 /* Command-argument register */
+#define LPC43_SDMMC_CMD_OFFSET           0x002c /* Command register */
+#define LPC43_SDMMC_RESP0_OFFSET         0x0030 /* Response-0 register */
+#define LPC43_SDMMC_RESP1_OFFSET         0x0034 /* Response-1 register */
+#define LPC43_SDMMC_RESP2_OFFSET         0x0038 /* Response-2 register */
+#define LPC43_SDMMC_RESP3_OFFSET         0x003c /* Response-3 register */
+#define LPC43_SDMMC_MINTSTS_OFFSET       0x0040 /* Masked interrupt-status register */
+#define LPC43_SDMMC_RINTSTS_OFFSET       0x0044 /* Raw interrupt-status register */
+#define LPC43_SDMMC_STATUS_OFFSET        0x0048 /* Status register */
+#define LPC43_SDMMC_FIFOTH_OFFSET        0x004c /* FIFO threshold register */
+#define LPC43_SDMMC_CDETECT_OFFSET       0x0050 /* Card-detect register value */
+#define LPC43_SDMMC_WRTPRT_OFFSET        0x0054 /* Write-protect register */
+                                                /* 0x58: Reserved */
+#define LPC43_SDMMC_TCBCNT_OFFSET        0x005c /* Transferred CIU card byte count */
+#define LPC43_SDMMC_TBBCNT_OFFSET        0x0060 /* Transferred cpu/DMA to/from BIU-FIFO byte count */
+#define LPC43_SDMMC_DEBNCE_OFFSET        0x0064 /* Debounce count register */
+                                                /* 0x0068-0x0074: Reserved */
+#define LPC43_SDMMC_RSTN_OFFSET          0x0078 /* Hardware Reset */
+#define LPC43_SDMMC_BMOD_OFFSET          0x0080 /* Bus Mode Register */
+#define LPC43_SDMMC_PLDMND_OFFSET        0x0084 /* Poll Demand Register */
+#define LPC43_SDMMC_DBADDR_OFFSET        0x0088 /* Descriptor List Base Address Register */
+#define LPC43_SDMMC_IDSTS_OFFSET         0x008c /* Internal DMAC Status Register */
+#define LPC43_SDMMC_IDINTEN_OFFSET       0x0090 /* Internal DMAC Interrupt Enable Register */
+#define LPC43_SDMMC_DSCADDR_OFFSET       0x0094 /* Current Host Descriptor Address Register */
+#define LPC43_SDMMC_BUFADDR_OFFSET       0x0098 /* Current Buffer Descriptor Address Register */
+                                                /* 0x009c-0x00ff: Reserved */
+#define LPC43_SDMMC_DATA_OFFSET          0x0100 /* Data FIFO read/write (>=) */
+
+/* MCI register (virtual) addresses *************************************************************/
+
+#define LPC43_SDMMC_CTRL                 (LPC43_SDMMC_BASE+LPC43_SDMMC_CTRL_OFFSET)
+#define LPC43_SDMMC_PWREN                (LPC43_SDMMC_BASE+LPC43_SDMMC_PWREN_OFFSET)
+#define LPC43_SDMMC_CLKDIV               (LPC43_SDMMC_BASE+LPC43_SDMMC_CLKDIV_OFFSET)
+#define LPC43_SDMMC_CLKSRC               (LPC43_SDMMC_BASE+LPC43_SDMMC_CLKSRC_OFFSET)
+#define LPC43_SDMMC_CLKENA               (LPC43_SDMMC_BASE+LPC43_SDMMC_CLKENA_OFFSET)
+#define LPC43_SDMMC_TMOUT                (LPC43_SDMMC_BASE+LPC43_SDMMC_TMOUT_OFFSET)
+#define LPC43_SDMMC_CTYPE                (LPC43_SDMMC_BASE+LPC43_SDMMC_CTYPE_OFFSET)
+#define LPC43_SDMMC_BLKSIZ               (LPC43_SDMMC_BASE+LPC43_SDMMC_BLKSIZ_OFFSET)
+#define LPC43_SDMMC_BYTCNT               (LPC43_SDMMC_BASE+LPC43_SDMMC_BYTCNT_OFFSET)
+#define LPC43_SDMMC_INTMASK              (LPC43_SDMMC_BASE+LPC43_SDMMC_INTMASK_OFFSET)
+#define LPC43_SDMMC_CMDARG               (LPC43_SDMMC_BASE+LPC43_SDMMC_CMDARG_OFFSET)
+#define LPC43_SDMMC_CMD                  (LPC43_SDMMC_BASE+LPC43_SDMMC_CMD_OFFSET)
+#define LPC43_SDMMC_RESP0                (LPC43_SDMMC_BASE+LPC43_SDMMC_RESP0_OFFSET)
+#define LPC43_SDMMC_RESP1                (LPC43_SDMMC_BASE+LPC43_SDMMC_RESP1_OFFSET)
+#define LPC43_SDMMC_RESP2                (LPC43_SDMMC_BASE+LPC43_SDMMC_RESP2_OFFSET)
+#define LPC43_SDMMC_RESP3                (LPC43_SDMMC_BASE+LPC43_SDMMC_RESP3_OFFSET)
+#define LPC43_SDMMC_MINTSTS              (LPC43_SDMMC_BASE+LPC43_SDMMC_MINTSTS_OFFSET)
+#define LPC43_SDMMC_RINTSTS              (LPC43_SDMMC_BASE+LPC43_SDMMC_RINTSTS_OFFSET)
+#define LPC43_SDMMC_STATUS               (LPC43_SDMMC_BASE+LPC43_SDMMC_STATUS_OFFSET)
+#define LPC43_SDMMC_FIFOTH               (LPC43_SDMMC_BASE+LPC43_SDMMC_FIFOTH_OFFSET)
+#define LPC43_SDMMC_CDETECT              (LPC43_SDMMC_BASE+LPC43_SDMMC_CDETECT_OFFSET)
+#define LPC43_SDMMC_WRTPRT               (LPC43_SDMMC_BASE+LPC43_SDMMC_WRTPRT_OFFSET)
+#define LPC43_SDMMC_TCBCNT               (LPC43_SDMMC_BASE+LPC43_SDMMC_TCBCNT_OFFSET)
+#define LPC43_SDMMC_TBBCNT               (LPC43_SDMMC_BASE+LPC43_SDMMC_TBBCNT_OFFSET)
+#define LPC43_SDMMC_TBBCNT               (LPC43_SDMMC_BASE+LPC43_SDMMC_TBBCNT_OFFSET)
+#define LPC43_SDMMC_DEBNCE               (LPC43_SDMMC_BASE+LPC43_SDMMC_DEBNCE_OFFSET)
+#define LPC43_SDMMC_DEBNCE               (LPC43_SDMMC_BASE+LPC43_SDMMC_DEBNCE_OFFSET)
+#define LPC43_SDMMC_RSTN                 (LPC43_SDMMC_BASE+LPC43_SDMMC_RSTN_OFFSET)
+#define LPC43_SDMMC_BMOD                 (LPC43_SDMMC_BASE+LPC43_SDMMC_BMOD_OFFSET)
+#define LPC43_SDMMC_PLDMND               (LPC43_SDMMC_BASE+LPC43_SDMMC_PLDMND_OFFSET)
+#define LPC43_SDMMC_DBADDR               (LPC43_SDMMC_BASE+LPC43_SDMMC_DBADDR_OFFSET)
+#define LPC43_SDMMC_IDSTS                (LPC43_SDMMC_BASE+LPC43_SDMMC_IDSTS_OFFSET)
+#define LPC43_SDMMC_IDINTEN              (LPC43_SDMMC_BASE+LPC43_SDMMC_IDINTEN_OFFSET)
+#define LPC43_SDMMC_DSCADDR              (LPC43_SDMMC_BASE+LPC43_SDMMC_DSCADDR_OFFSET)
+#define LPC43_SDMMC_BUFADDR              (LPC43_SDMMC_BASE+LPC43_SDMMC_BUFADDR_OFFSET)
+#define LPC43_SDMMC_DATA                 (LPC43_SDMMC_BASE+LPC43_SDMMC_DATA_OFFSET)
+
+/* MCI register bit definitions *****************************************************************/
+
+/* Control register CTRL */
+
+#define SDMMC_CTRL_CNTLRRESET            (1 << 0)  /* Bit 0:  Reset Module controller */
+#define SDMMC_CTRL_FIFORESET             (1 << 1)  /* Bit 1:  Reset to data FIFO To reset FIFO pointers */
+#define SDMMC_CTRL_DMARESET              (1 << 2)  /* Bit 2:  Reset internal DMA interface control logic */
+                                                   /* Bit 3:  Reserved */
+#define SDMMC_CTRL_INTENABLE             (1 << 4)  /* Bit 4:  Enable interrupts */
+                                                   /* Bit 5:  Reserved */
+#define SDMMC_CTRL_READWAIT              (1 << 6)  /* Bit 6:  Assert read wait */
+#define SDMMC_CTRL_SENDIRQRESP           (1 << 7)  /* Bit 7:  Send auto IRQ response */
+#define SDMMC_CTRL_ABORTREAD             (1 << 8)  /* Bit 8:  Reset data state-machine (suspend sequence) */
+#define SDMMC_CTRL_SENDCCSD              (1 << 9)  /* Bit 9:  Send CCSD to CE-ATA device */
+#define SDMMC_CTRL_AUTOSTOP              (1 << 10) /* Bit 10: Send STOP after CCSD to CE-ATA device */
+#define SDMMC_CTRL_CEATAINT              (1 << 11) /* Bit 11: CE-ATA device interrupts enabled */
+                                                   /* Bits 12-15:  Reserved */
+#define SDMMC_CTRL_CDVA0                 (1 << 16) /* Bit 16: Controls SD_VOLT0 pin */
+#define SDMMC_CTRL_CDVA0                 (1 << 17) /* Bit 17: Controls SD_VOLT1 pin */
+#define SDMMC_CTRL_CDVA0                 (1 << 18) /* Bit 18: Controls SD_VOLT2 pin */
+                                                   /* Bits 19-23:  Reserved */
+#define SDMMC_CTRL_INTDMA                (1 << 25) /* Bit 24: SD/MMC DMA use */
+                                                   /* Bits 26-31:  Reserved */
+/* Power Enable Register (PWREN) */
+
+#define SDMMC_PWREN                      (1 << 0)  /* Bit 0: Power on/off switch */
+                                                     /* Bits 1-31:  Reserved */
+/* Clock divider register CLKDIV */
+
+#define SDMMC_CLKDIV0_SHIFT               (0)       /* Bits 0-7: Clock divider 0 value */
+#define SDMMC_CLKDIV0_MASK                (255 << SDMMC_CLKDIV0_SHIFT)
+#define SDMMC_CLKDIV1_SHIFT               (8)       /* Bits 8-15: Clock divider 1 value */
+#define SDMMC_CLKDIV1_MASK                (255 << SDMMC_CLKDIV1_SHIFT)
+#define SDMMC_CLKDIV2_SHIFT               (16)      /* Bits 16-23: Clock divider 2 value */
+#define SDMMC_CLKDIV2_MASK                (255 << SDMMC_CLKDIV2_SHIFT)
+#define SDMMC_CLKDIV3_SHIFT               (24)      /* Bits 24-31: Clock divider 3 value */
+#define SDMMC_CLKDIV3_MASK                (255 << SDMMC_CLKDIV3_SHIFT)
+
+/* Clock source register CLKSRC */
+
+#define SDMMC_CLKSRC_SHIFT                (0)       /* Bits 0-1: Clock divider source for SD card */
+#define SDMMC_CLKSRC_MASK                 (3 << SDMMC_CLKSRC_SHIFT)
+#  define SDMMC_CLKSRC_CLKDIV0            (0 << SDMMC_CLKSRC_SHIFT) /* Clock divider 0 */
+#  define SDMMC_CLKSRC_CLKDIV1            (1 << SDMMC_CLKSRC_SHIFT) /* Clock divider 1 */
+#  define SDMMC_CLKSRC_CLKDIV2            (2 << SDMMC_CLKSRC_SHIFT) /* Clock divider 2 */
+#  define SDMMC_CLKSRC_CLKDIV3            (3 << SDMMC_CLKSRC_SHIFT) /* Clock divider 3 */
+                                                    /* Bits 2-31:  Reserved */
+/* Clock enable register CLKENA */
+
+#define SDMMC_CLKENA_EMABLE               (1 << 0)  /* Bit 0:  Clock enable */
+                                                    /* Bits 1-15:  Reserved */
+#define SDMMC_CLKENA_LOWPOWER             (1 << 16) /* Bit 16: Low-power mode */
+                                                    /* Bits 17-31:  Reserved */
+/*Timeout register TMOUT */
+
+#define SDMMC_TMOUT_RESPONSE_SHIFT        (0)       /* Bits 0-7: Response timeout value */
+#define SDMMC_TMOUT_RESPONSE_MASK         (255 << SDMMC_TMOUT_RESPONSE_SHIFT)
+#define SDMMC_TMOUT_DATA_SHIFT            (8)       /* Bits 8-31: Data Read Timeout value */
+#define SDMMC_TMOUT_DATA_MASK             (0x00ffffff << SDMMC_TMOUT_DATA_SHIFT)
+
+/* Card type register CTYPE */
+
+#define SDMMC_CTYPE_WIDTH4                (1 << 0)  /* Bit 0:  4-bit mode */
+                                                    /* Bits 1-15:  Reserved */
+#define SDMMC_CTYPE_WIDTH8                (1 << 16) /* Bit 16: 8-bit mode */
+                                                    /* Bits 17-31:  Reserved */
+/* Blocksize register BLKSIZ */
+
+#define SDMMC_BLKSIZ_SHIFT                (0)       /* Bits 0-15: Block size */
+#define SDMMC_BLKSIZ_MASK                 (0xffff << SDMMC_BLKSIZ_SHIFT)
+                                                    /* Bits 16-31:  Reserved */
+/* Interrupt mask register INTMASK
+ * Masked interrupt status register MINTSTS
+ * Raw interrupt status register RINTSTS
+ */
+
+#define SDMMC_INT_CDET                    (1 << 0)  /* Bit 0:  Card detect */
+#define SDMMC_INT_RE                      (1 << 1)  /* Bit 1:  Response error */
+#define SDMMC_INT_CDONE                   (1 << 2)  /* Bit 2:  Command done */
+#define SDMMC_INT_DTO                     (1 << 3)  /* Bit 3:  Data transfer over */
+#define SDMMC_INT_TXDR                    (1 << 4)  /* Bit 4:  Transmit FIFO data request */
+#define SDMMC_INT_RXDR                    (1 << 5)  /* Bit 5:  Receive FIFO data request */
+#define SDMMC_INT_RCRC                    (1 << 6)  /* Bit 6:  Response CRC error */
+#define SDMMC_INT_DCRC                    (1 << 7)  /* Bit 7:  Data CRC error */
+#define SDMMC_INT_RTO                     (1 << 8)  /* Bit 8:  Response timeout */
+#define SDMMC_INT_DRTO                    (1 << 9)  /* Bit 9:  Data read timeout */
+#define SDMMC_INT_HTO                     (1 << 10) /* Bit 10: Data starvation-by-cpu timeout */
+#define SDMMC_INT_FRUN                    (1 << 11) /* Bit 11: FIFO underrun/overrun error */
+#define SDMMC_INT_HLE                     (1 << 12) /* Bit 12: Hardware locked write error */
+#define SDMMC_INT_SBE                     (1 << 13) /* Bit 13: Start-bit error */
+#define SDMMC_INT_ACD                     (1 << 14) /* Bit 14: Auto command done */
+#define SDMMC_INT_EBE                     (1 << 15) /* Bit 15: End-bit error (read)/Write no CRC */
+#define SDMMC_INT_SDIO                    (1 << 16) /* Bit 16: Mask SDIO interrupt */
+                                                    /* Bits 17-31: Reserved */
+#define SDMMC_INT_ALL                     (0x1ffff)
+
+/* Command register CMD */
+
+#define SDMMC_CMD_CMDINDEX_SHIFT          (0)       /* Bits 0-5: 5:0 Command index */
+#define SDMMC_CMD_CMDINDEX_MASK           (63 << SDMMC_CMD_CMDINDEX_SHIFT)
+#define SDMMC_CMD_RESPONSE                (1 << 6)  /* Bit 6:  Response expected from card */
+#define SDMMC_CMD_LONGRESP                (1 << 7)  /* Bit 7:  Long response expected from card */
+#define SDMMC_CMD_RESPCRC                 (1 << 8)  /* Bit 8:  Check response CRC */
+#define SDMMC_CMD_DATAXFREXPTD            (1 << 9)  /* Bit 9:  Data transfer expected (read/write) */
+#define SDMMC_CMD_WRITE                   (1 << 10) /* Bit 10: Write to card */
+#define SDMMC_CMD_XFRMODE                 (1 << 11) /* Bit 11: Stream data transfer command */
+#define SDMMC_CMD_AUTOSTOP                (1 << 12) /* Bit 12: Send stop command at end of data transfer */
+#define SDMMC_CMD_WAITPREV                (1 << 13) /* Bit 13: Wait previous transfer complete before sending */
+#define SDMMC_CMD_STOPABORT               (1 << 14) /* Bit 14: Stop current data transfer */
+#define SDMMC_CMD_SENDINIT                (1 << 15) /* Bit 15: Send initialization sequence before command */
+                                                    /* Bits 16-20:  Reserved */
+#define SDMMC_CMD_UPDCLOCK                (1 << 21) /* Bit 21: Update clock register value (no command) */
+#define SDMMC_CMD_READCEATA               (1 << 22) /* Bit 22: Performing read access on CE-ATA device */
+#define SDMMC_CMD_CCSEXPTD                (1 << 23) /* Bit 23: Expect command completion from CE-ATA device */
+#define SDMMC_CMD_ENABOOT                 (1 << 24) /* Bit 24: Enable Boot */
+#define SDMMC_CMD_BACKEXPTED              (1 << 25) /* Bit 25: Expect Boot Acknowledge */
+#define SDMMC_CMD_DISBOOT                 (1 << 26) /* Bit 26: Disable Boot */
+#define SDMMC_CMD_BOOTMODE                (1 << 27) /* Bit 27: Boot Mode */
+#define SDMMC_CMD_VSWITCH                 (1 << 28) /* Bit 28: Voltage switch bit */
+                                                    /* Bits 29-30:  Reserved */
+#define SDMMC_CMD_STARTCMD                (1 << 31) /* Bit 31: Start command */
+
+/* Status register STATUS */
+
+#define SDMMC_STATUS_RXWMARK              (1 << 0)  /* Bit 0:  FIFO reached Receive watermark level */
+#define SDMMC_STATUS_TXWMARK              (1 << 1)  /* Bit 1:  FIFO reached Transmit watermark level */
+#define SDMMC_STATUS_FIFOEMPTY            (1 << 2)  /* Bit 2:  FIFO is empty */
+#define SDMMC_STATUS_FIFOFULL             (1 << 3)  /* Bit 3:  FIFO is full */
+#define SDMMC_STATUS_FSMSTATE_SHIFT       (4)       /* Bits 4-7: 7:4 Command FSM states */
+#define SDMMC_STATUS_FSMSTATE_MASK        (15 << SDMMC_STATUS_FSMSTATE_SHIFT)
+#  define SDMMC_STATUS_FSMSTATE_IDLE      (0  << SDMMC_STATUS_FSMSTATE_SHIFT) /* Idle */
+#  define SDMMC_STATUS_FSMSTATE_INIT      (1  << SDMMC_STATUS_FSMSTATE_SHIFT) /* Send init sequence */
+#  define SDMMC_STATUS_FSMSTATE_TXSTART   (2  << SDMMC_STATUS_FSMSTATE_SHIFT) /* Tx cmd start bit */
+#  define SDMMC_STATUS_FSMSTATE_TXTXBIT   (3  << SDMMC_STATUS_FSMSTATE_SHIFT) /* Tx cmd tx bit */
+#  define SDMMC_STATUS_FSMSTATE_TXCMDARG  (4  << SDMMC_STATUS_FSMSTATE_SHIFT) /* Tx cmd index + arg */
+#  define SDMMC_STATUS_FSMSTATE_TXCMDCRC  (5  << SDMMC_STATUS_FSMSTATE_SHIFT) /* Tx cmd crc7 */
+#  define SDMMC_STATUS_FSMSTATE_TXEND     (6  << SDMMC_STATUS_FSMSTATE_SHIFT) /* Tx cmd end bit */
+#  define SDMMC_STATUS_FSMSTATE_RXSTART   (7  << SDMMC_STATUS_FSMSTATE_SHIFT) /* Rx resp start bit */
+#  define SDMMC_STATUS_FSMSTATE_RXIRQ     (8  << SDMMC_STATUS_FSMSTATE_SHIFT) /* Rx resp IRQ response */
+#  define SDMMC_STATUS_FSMSTATE_RXTXBIT   (9  << SDMMC_STATUS_FSMSTATE_SHIFT) /* Rx resp tx bit */
+#  define SDMMC_STATUS_FSMSTATE_RXCMD     (10 << SDMMC_STATUS_FSMSTATE_SHIFT) /* Rx resp cmd idx */
+#  define SDMMC_STATUS_FSMSTATE_RXRESP    (11 << SDMMC_STATUS_FSMSTATE_SHIFT) /* Rx resp data */
+#  define SDMMC_STATUS_FSMSTATE_RXRESPCRC (12 << SDMMC_STATUS_FSMSTATE_SHIFT) /* Rx resp crc7 */
+#  define SDMMC_STATUS_FSMSTATE_RXEND     (13 << SDMMC_STATUS_FSMSTATE_SHIFT) /* Rx resp end bit */
+#  define SDMMC_STATUS_FSMSTATE_WAITNCC   (14 << SDMMC_STATUS_FSMSTATE_SHIFT) /* Cmd path wait NCC */
+#  define SDMMC_STATUS_FSMSTATE_WAITTURN  (15 << SDMMC_STATUS_FSMSTATE_SHIFT) /* Wait; CMD-to-resp turnaround */
+#define SDMMC_STATUS_DAT3                 (1 << 8)  /* Bit 8:  DAT3=1: Card present */
+#define SDMMC_STATUS_DATABUSY             (1 << 9)  /* Bit 9:  Card data busy */
+#define SDMMC_STATUS_MCBUSY               (1 << 10) /* Bit 10: Data transmit/receive state machine busy */
+#define SDMMC_STATUS_RESPINDEX_SHIFT      (11)      /* Bits 11-16: Index of previous response */
+#define SDMMC_STATUS_RESPINDEX_MASK       (63 << SDMMC_STATUS_RESPINDEX_SHIFT)
+#define SDMMC_STATUS_FIFOCOUNT_SHIFT      (17)      /* Bits 17-29: FIFO count */
+#define SDMMC_STATUS_FIFOCOUNT_MASK       (0x1fff << SDMMC_STATUS_FIFOCOUNT_SHIFT)
+#define SDMMC_STATUS_DMAACK               (1 << 30) /* Bit 30: DMA acknowledge signal state */
+#define SDMMC_STATUS_DMAREQ               (1 << 31) /* Bit 31: DMA request signal state */
+
+/* FIFO threshold register FIFOTH */
+
+#define SDMMC_FIFOTH_TXWMARK_SHIFT        (0)       /* Bits 0-11: FIFO threshold level when transmitting */
+#define SDMMC_FIFOTH_TXWMARK_MASK         (0xfff << SDMMC_FIFOTH_TXWMARK_SHIFT)
+                                                    /* Bits 12-15: Reserved */
+#define SDMMC_FIFOTH_RXWMARK_SHIFT        (16)      /* Bits 16-27: FIFO threshold level when receiving */
+#define SDMMC_FIFOTH_RXWMARK_MASK         (0xfff << SDMMC_FIFOTH_RXWMARK_SHIFT)
+#define SDMMC_FIFOTH_DMABURST_SHIFT       (28)      /* Bits 28-30: Burst size for multiple transaction */
+#define SDMMC_FIFOTH_DMABURST_MASK        (7 << SDMMC_FIFOTH_DMABURST_SHIFT)
+#  define SDMMC_FIFOTH_DMABURST_1XFR      (0 << SDMMC_FIFOTH_DMABURST_SHIFT) /* 1 transfer */
+#  define SDMMC_FIFOTH_DMABURST_4XFRS     (1 << SDMMC_FIFOTH_DMABURST_SHIFT) /* 4 transfers */
+#  define SDMMC_FIFOTH_DMABURST_8XFRS     (2 << SDMMC_FIFOTH_DMABURST_SHIFT) /* 8 transfers */
+#  define SDMMC_FIFOTH_DMABURST_16XFRS    (3 << SDMMC_FIFOTH_DMABURST_SHIFT) /* 16 transfers */
+#  define SDMMC_FIFOTH_DMABURST_32XFRS    (4 << SDMMC_FIFOTH_DMABURST_SHIFT) /* 32 transfers */
+#  define SDMMC_FIFOTH_DMABURST_64XFRS    (5 << SDMMC_FIFOTH_DMABURST_SHIFT) /* 64 transfers */
+#  define SDMMC_FIFOTH_DMABURST_128XFRS   (6 << SDMMC_FIFOTH_DMABURST_SHIFT) /* 128 transfers */
+#  define SDMMC_FIFOTH_DMABURST_256XFRS   (7 << SDMMC_FIFOTH_DMABURST_SHIFT) /* 256 transfers */
+                                                    /* Bit 31: Reserved */
+/* Card detect register CDETECT */
+
+#define SDMMC_CDETECT_NOTPRESENT          (1 << 0)  /* Bit 0: Card detect */
+                                                    /* Bit 1-31: Reserved */
+/* Write protect register WRTPRT */
+
+#define SDMMC_WRTPRT_PROTECTED            (1 << 0)  /* Bit 0: Write protect */
+                                                    /* Bit 1-31: Reserved */
+/* Debounce count register */
+
+#define SDMMC_DEBNCE_MASK                 0x00ffffff /* Bits 0-23: Debounce count */
+                                                     /* Bit 24-31: Reserved */
+
+/* Hardware Reset */
+
+#define SDMMC_RSTN                        (1 << 0)  /* Bit 0: Hardware reset */
+                                                    /* Bit 1-31: Reserved */
+
+/* Bus Mode Register */
+
+#define SDMMC_BMOD_SWR                    (1 << 0)  /* Bit 0:  Software Reset */
+#define SDMMC_BMOD_FB                     (1 << 1)  /* Bit 1:  Fixed Burst */
+#define SDMMC_BMOD_DSL_SHIFT              (2)       /* Bits 2-6: Descriptor Skip Length */
+#define SDMMC_BMOD_DSL_MASK               (31 << SDMMC_BMOD_DSL_SHIFT)
+#define SDMMC_BMOD_DE                     (1 << 7)  /* Bit 7:  SD/MMC DMA Enable */
+#define SDMMC_BMOD_PBL_SHIFT              (8)       /* Bits 8-10: Programmable Burst Length */
+#define SDMMC_BMOD_PBL_MASK               (7 << SDMMC_BMOD_PBL_SHIFT)
+#  define SDMMC_BMOD_PBL_1XFRS            (0 << SDMMC_BMOD_PBL_SHIFT) /* 1 transfer */
+#  define SDMMC_BMOD_PBL_4XFRS            (1 << SDMMC_BMOD_PBL_SHIFT) /* 4 transfers */
+#  define SDMMC_BMOD_PBL_8XFRS            (2 << SDMMC_BMOD_PBL_SHIFT) /* 8 transfers */
+#  define SDMMC_BMOD_PBL_16XFRS           (3 << SDMMC_BMOD_PBL_SHIFT) /* 16 transfers */
+#  define SDMMC_BMOD_PBL_32XFRS           (4 << SDMMC_BMOD_PBL_SHIFT) /* 32 transfers */
+#  define SDMMC_BMOD_PBL_64XFRS           (5 << SDMMC_BMOD_PBL_SHIFT) /* 64 transfers */
+#  define SDMMC_BMOD_PBL_128XFRS          (6 << SDMMC_BMOD_PBL_SHIFT) /* 128 transfers */
+#  define SDMMC_BMOD_PBL_256XFRS          (7 << SDMMC_BMOD_PBL_SHIFT) /* 256 transfers */
+                                                    /* Bits 11-31: Reserved */
+/* Internal DMAC Status Register */
+
+#define SDMMC_IDSTS_TI                    (1 << 0)  /* Bit 0:  Transmit Interrupt */
+#define SDMMC_IDSTS_RI                    (1 << 1)  /* Bit 1:  Receive Interrupt */
+#define SDMMC_IDSTS_FBE                   (1 << 2)  /* Bit 2:  Fatal Bus Error Interrupt */
+                                                    /* Bit 3:  Reserved */
+#define SDMMC_IDSTS_DU                    (1 << 4)  /* Bit 4:  Descriptor Unavailable Interrupt */
+#define SDMMC_IDSTS_CES                   (1 << 5)  /* Bit 5:  Card Error Summary */
+                                                    /* Bits 6-7: Reserved */
+#define SDMMC_IDSTS_NIS                   (1 << 8)  /* Bit 8:  Normal Interrupt Summary */
+#define SDMMC_IDSTS_AIS                   (1 << 9)  /* Bit 9:  Abnormal Interrupt Summary */
+#define SDMMC_IDSTS_EB_SHIFT              (10)      /* Bits 10-12: Error Bits */
+#define SDMMC_IDSTS_EB_MASK               (7 << SDMMC_IDSTS_EB_SHIFT)
+#  define SDMMC_IDSTS_EB_TXHABORT         (1 << SDMMC_IDSTS_EB_SHIFT) /* Host Abort received during transmission */
+#  define SDMMC_IDSTS_EB_RXHABORT         (2 << SDMMC_IDSTS_EB_SHIFT) /* Host Abort received during reception */
+#define SDMMC_IDSTS_FSM_SHIFT             (13)      /* Bits 13-16: DMAC state machine present state */
+#define SDMMC_IDSTS_FSM_MASK              (15 << SDMMC_IDSTS_FSM_SHIFT)
+#  define SDMMC_IDSTS_FSM_DMAIDLE         (0 << SDMMC_IDSTS_FSM_SHIFT) /* DMA_IDLE*/
+#  define SDMMC_IDSTS_FSM_DMASUSP         (1 << SDMMC_IDSTS_FSM_SHIFT) /* DMA_SUSPEND */
+#  define SDMMC_IDSTS_FSM_DESCRD          (2 << SDMMC_IDSTS_FSM_SHIFT) /* DESC_RD */
+#  define SDMMC_IDSTS_FSM_DESCCHK         (3 << SDMMC_IDSTS_FSM_SHIFT) /* DESC_CHK */
+#  define SDMMC_IDSTS_FSM_DMARDREQW       (4 << SDMMC_IDSTS_FSM_SHIFT) /* DMA_RD_REQ_WAIT */
+#  define SDMMC_IDSTS_FSM_DMAWRREQW       (5 << SDMMC_IDSTS_FSM_SHIFT) /* DMA_WR_REQ_WAIT */
+#  define SDMMC_IDSTS_FSM_DMARD           (6 << SDMMC_IDSTS_FSM_SHIFT) /* DMA_RD */
+#  define SDMMC_IDSTS_FSM_DMAWR           (7 << SDMMC_IDSTS_FSM_SHIFT) /* DMA_WR */
+#  define SDMMC_IDSTS_FSM_DMACLOSE        (8 << SDMMC_IDSTS_FSM_SHIFT) /* DESC_CLOSE */
+                                                    /* Bits 17-31: Reserved */
+/* Internal DMAC Interrupt Enable Register */
+
+#define SDMMC_IDINTEN_
+#define SDMMC_IDINTEN_TI                  (1 << 0)  /* Bit 0:  Transmit Interrupt */
+#define SDMMC_IDINTEN_RI                  (1 << 1)  /* Bit 1:  Receive Interrupt */
+#define SDMMC_IDINTEN_FBE                 (1 << 2)  /* Bit 2:  Fatal Bus Error Interrupt */
+                                                    /* Bit 3:  Reserved */
+#define SDMMC_IDINTEN_DU                  (1 << 4)  /* Bit 4:  Descriptor Unavailable Interrupt */
+#define SDMMC_IDINTEN_CES                 (1 << 5)  /* Bit 5:  Card Error Summary */
+                                                    /* Bits 6-7: Reserved */
+#define SDMMC_IDINTEN_NIS                 (1 << 8)  /* Bit 8:  Normal Interrupt Summary */
+#define SDMMC_IDINTEN_AIS                 (1 << 9)  /* Bit 9:  Abnormal Interrupt Summary */
+                                                    /* Bits 10-31: Reserved */
+
+/************************************************************************************************
+ * Public Types
+ ************************************************************************************************/
+
+/************************************************************************************************
+ * Public Data
+ ************************************************************************************************/
+
+/************************************************************************************************
+ * Public Functions
+ ************************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_SDMMC_H */
diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_sgpio.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_sgpio.h
new file mode 100644
index 000000000..bd3d2df39
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_sgpio.h
@@ -0,0 +1,682 @@
+/****************************************************************************************************
+ * arch/arm/src/lpc43xx/chip/lpc43_sgpio.h
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_SGPIO_H
+#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_SGPIO_H
+
+/****************************************************************************************************
+ * Included Files
+ ****************************************************************************************************/
+
+#include <nuttx/config.h>
+
+/****************************************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************************************/
+/* Register Offsets *********************************************************************************/
+
+#define LPC43_SGPIO_OUT_MUXCFG_OFFSET(n)   (0x0000 + ((n) << 2)
+#define LPC43_SGPIO_OUT_MUXCFG0_OFFSET     0x0000 /* Pin multiplexer configuration register 0 */
+#define LPC43_SGPIO_OUT_MUXCFG1_OFFSET     0x0004 /* Pin multiplexer configuration register 1 */
+#define LPC43_SGPIO_OUT_MUXCFG2_OFFSET     0x0008 /* Pin multiplexer configuration register 2 */
+#define LPC43_SGPIO_OUT_MUXCFG3_OFFSET     0x000c /* Pin multiplexer configuration register 3 */
+#define LPC43_SGPIO_OUT_MUXCFG4_OFFSET     0x0010 /* Pin multiplexer configuration register 4 */
+#define LPC43_SGPIO_OUT_MUXCFG5_OFFSET     0x0014 /* Pin multiplexer configuration register 5 */
+#define LPC43_SGPIO_OUT_MUXCFG6_OFFSET     0x0018 /* Pin multiplexer configuration register 6 */
+#define LPC43_SGPIO_OUT_MUXCFG7_OFFSET     0x001c /* Pin multiplexer configuration register 7 */
+#define LPC43_SGPIO_OUT_MUXCFG8_OFFSET     0x0020 /* Pin multiplexer configuration register 8 */
+#define LPC43_SGPIO_OUT_MUXCFG9_OFFSET     0x0024 /* Pin multiplexer configuration register 9 */
+#define LPC43_SGPIO_OUT_MUXCFG10_OFFSET    0x0028 /* Pin multiplexer configuration register 10 */
+#define LPC43_SGPIO_OUT_MUXCFG11_OFFSET    0x002c /* Pin multiplexer configuration register 11 */
+#define LPC43_SGPIO_OUT_MUXCFG12_OFFSET    0x0030 /* Pin multiplexer configuration register 12 */
+#define LPC43_SGPIO_OUT_MUXCFG13_OFFSET    0x0034 /* Pin multiplexer configuration register 13 */
+#define LPC43_SGPIO_OUT_MUXCFG14_OFFSET    0x0038 /* Pin multiplexer configuration register 14 */
+#define LPC43_SGPIO_OUT_MUXCFG15_OFFSET    0x003c /* Pin multiplexer configuration register 15 */
+
+#define LPC43_SGPIO_MUXCFG_OFFSET(n)       (0x0040 + ((n) << 2)
+#define LPC43_SGPIO_MUXCFG0_OFFSET         0x0040 /* SGPIO multiplexer configuration register 0 */
+#define LPC43_SGPIO_MUXCFG1_OFFSET         0x0044 /* SGPIO multiplexer configuration register 1 */
+#define LPC43_SGPIO_MUXCFG2_OFFSET         0x0048 /* SGPIO multiplexer configuration register 2 */
+#define LPC43_SGPIO_MUXCFG3_OFFSET         0x004c /* SGPIO multiplexer configuration register 3 */
+#define LPC43_SGPIO_MUXCFG4_OFFSET         0x0050 /* SGPIO multiplexer configuration register 4 */
+#define LPC43_SGPIO_MUXCFG5_OFFSET         0x0054 /* SGPIO multiplexer configuration register 5 */
+#define LPC43_SGPIO_MUXCFG6_OFFSET         0x0058 /* SGPIO multiplexer configuration register 6 */
+#define LPC43_SGPIO_MUXCFG7_OFFSET         0x005c /* SGPIO multiplexer configuration register 7 */
+#define LPC43_SGPIO_MUXCFG8_OFFSET         0x0060 /* SGPIO multiplexer configuration register 8 */
+#define LPC43_SGPIO_MUXCFG9_OFFSET         0x0064 /* SGPIO multiplexer configuration register 9 */
+#define LPC43_SGPIO_MUXCFG10_OFFSET        0x0068 /* SGPIO multiplexer configuration register 10 */
+#define LPC43_SGPIO_MUXCFG11_OFFSET        0x006c /* SGPIO multiplexer configuration register 11 */
+#define LPC43_SGPIO_MUXCFG12_OFFSET        0x0070 /* SGPIO multiplexer configuration register 12 */
+#define LPC43_SGPIO_MUXCFG13_OFFSET        0x0074 /* SGPIO multiplexer configuration register 13 */
+#define LPC43_SGPIO_MUXCFG14_OFFSET        0x0078 /* SGPIO multiplexer configuration register 14 */
+#define LPC43_SGPIO_MUXCFG15_OFFSET        0x007c /* SGPIO multiplexer configuration register 15 */
+
+#define LPC43_SGPIO_SLICE_MUXCFG_OFFSET(n) (0x0080 + ((n) << 2)
+#define LPC43_SGPIO_SLICE_MUXCFG0_OFFSET   0x0080 /* Slice multiplexer configuration register 0 */
+#define LPC43_SGPIO_SLICE_MUXCFG1_OFFSET   0x0084 /* Slice multiplexer configuration register 1 */
+#define LPC43_SGPIO_SLICE_MUXCFG2_OFFSET   0x0088 /* Slice multiplexer configuration register 2 */
+#define LPC43_SGPIO_SLICE_MUXCFG3_OFFSET   0x008c /* Slice multiplexer configuration register 3 */
+#define LPC43_SGPIO_SLICE_MUXCFG4_OFFSET   0x0090 /* Slice multiplexer configuration register 4 */
+#define LPC43_SGPIO_SLICE_MUXCFG5_OFFSET   0x0094 /* Slice multiplexer configuration register 5 */
+#define LPC43_SGPIO_SLICE_MUXCFG6_OFFSET   0x0098 /* Slice multiplexer configuration register 6 */
+#define LPC43_SGPIO_SLICE_MUXCFG7_OFFSET   0x009c /* Slice multiplexer configuration register 7 */
+#define LPC43_SGPIO_SLICE_MUXCFG8_OFFSET   0x00a0 /* Slice multiplexer configuration register 8 */
+#define LPC43_SGPIO_SLICE_MUXCFG9_OFFSET   0x00a4 /* Slice multiplexer configuration register 9 */
+#define LPC43_SGPIO_SLICE_MUXCFG10_OFFSET  0x00a8 /* Slice multiplexer configuration register 10 */
+#define LPC43_SGPIO_SLICE_MUXCFG11_OFFSET  0x00ac /* Slice multiplexer configuration register 11 */
+#define LPC43_SGPIO_SLICE_MUXCFG12_OFFSET  0x00b0 /* Slice multiplexer configuration register 12 */
+#define LPC43_SGPIO_SLICE_MUXCFG13_OFFSET  0x00b4 /* Slice multiplexer configuration register 13 */
+#define LPC43_SGPIO_SLICE_MUXCFG14_OFFSET  0x00b8 /* Slice multiplexer configuration register 14 */
+#define LPC43_SGPIO_SLICE_MUXCFG15_OFFSET  0x00bc /* Slice multiplexer configuration register 15 */
+
+#define LPC43_SGPIO_REG_OFFSET(n)          (0x00c0 + ((n) << 2)
+#define LPC43_SGPIO_REG0_OFFSET            0x00c0 /* Slice data register 0 */
+#define LPC43_SGPIO_REG1_OFFSET            0x00c4 /* Slice data register 1 */
+#define LPC43_SGPIO_REG2_OFFSET            0x00c8 /* Slice data register 2 */
+#define LPC43_SGPIO_REG3_OFFSET            0x00cc /* Slice data register 3 */
+#define LPC43_SGPIO_REG4_OFFSET            0x00d0 /* Slice data register 4 */
+#define LPC43_SGPIO_REG5_OFFSET            0x00d4 /* Slice data register 5 */
+#define LPC43_SGPIO_REG6_OFFSET            0x00d8 /* Slice data register 6 */
+#define LPC43_SGPIO_REG7_OFFSET            0x00dc /* Slice data register 7 */
+#define LPC43_SGPIO_REG8_OFFSET            0x00e0 /* Slice data register 8 */
+#define LPC43_SGPIO_REG9_OFFSET            0x00e4 /* Slice data register 9 */
+#define LPC43_SGPIO_REG10_OFFSET           0x00e8 /* Slice data register 10 */
+#define LPC43_SGPIO_REG11_OFFSET           0x00ec /* Slice data register 11 */
+#define LPC43_SGPIO_REG12_OFFSET           0x00f0 /* Slice data register 12 */
+#define LPC43_SGPIO_REG13_OFFSET           0x00f4 /* Slice data register 13 */
+#define LPC43_SGPIO_REG14_OFFSET           0x00f8 /* Slice data register 14 */
+#define LPC43_SGPIO_REG15_OFFSET           0x00fc /* Slice data register 15 */
+
+#define LPC43_SGPIO_REG_SS_OFFSET(n)       (0x0100 + ((n) << 2)
+#define LPC43_SGPIO_REG_SS0_OFFSET         0x0100 /* Slice data shadow register 0 */
+#define LPC43_SGPIO_REG_SS1_OFFSET         0x0104 /* Slice data shadow register 1 */
+#define LPC43_SGPIO_REG_SS2_OFFSET         0x0108 /* Slice data shadow register 2 */
+#define LPC43_SGPIO_REG_SS3_OFFSET         0x010c /* Slice data shadow register 3 */
+#define LPC43_SGPIO_REG_SS4_OFFSET         0x0110 /* Slice data shadow register 4 */
+#define LPC43_SGPIO_REG_SS5_OFFSET         0x0114 /* Slice data shadow register 5 */
+#define LPC43_SGPIO_REG_SS6_OFFSET         0x0118 /* Slice data shadow register 6 */
+#define LPC43_SGPIO_REG_SS7_OFFSET         0x011c /* Slice data shadow register 7 */
+#define LPC43_SGPIO_REG_SS8_OFFSET         0x0120 /* Slice data shadow register 8 */
+#define LPC43_SGPIO_REG_SS9_OFFSET         0x0124 /* Slice data shadow register 9 */
+#define LPC43_SGPIO_REG_SS10_OFFSET        0x0128 /* Slice data shadow register 10 */
+#define LPC43_SGPIO_REG_SS11_OFFSET        0x012c /* Slice data shadow register 11 */
+#define LPC43_SGPIO_REG_SS12_OFFSET        0x0130 /* Slice data shadow register 12 */
+#define LPC43_SGPIO_REG_SS13_OFFSET        0x0134 /* Slice data shadow register 13 */
+#define LPC43_SGPIO_REG_SS14_OFFSET        0x0138 /* Slice data shadow register 14 */
+#define LPC43_SGPIO_REG_SS15_OFFSET        0x013c /* Slice data shadow register 15 */
+
+#define LPC43_SGPIO_PRESET_OFFSET(n)       (0x0140 + ((n) << 2)
+#define LPC43_SGPIO_PRESET0_OFFSET         0x0140 /* COUNT0 reload value */
+#define LPC43_SGPIO_PRESET1_OFFSET         0x0144 /* COUNT1 reload value */
+#define LPC43_SGPIO_PRESET2_OFFSET         0x0148 /* COUNT2 reload value */
+#define LPC43_SGPIO_PRESET3_OFFSET         0x014c /* COUNT3 reload value */
+#define LPC43_SGPIO_PRESET4_OFFSET         0x0150 /* COUNT4 reload value */
+#define LPC43_SGPIO_PRESET5_OFFSET         0x0154 /* COUNT5 reload value */
+#define LPC43_SGPIO_PRESET6_OFFSET         0x0158 /* COUNT6 reload value */
+#define LPC43_SGPIO_PRESET7_OFFSET         0x015c /* COUNT7 reload value */
+#define LPC43_SGPIO_PRESET8_OFFSET         0x0160 /* COUNT8 reload value */
+#define LPC43_SGPIO_PRESET9_OFFSET         0x0164 /* COUNT9 reload value */
+#define LPC43_SGPIO_PRESET10_OFFSET        0x0168 /* COUNT10 reload value */
+#define LPC43_SGPIO_PRESET11_OFFSET        0x016c /* COUNT11 reload value */
+#define LPC43_SGPIO_PRESET12_OFFSET        0x0170 /* COUNT12 reload value */
+#define LPC43_SGPIO_PRESET13_OFFSET        0x0174 /* COUNT13 reload value */
+#define LPC43_SGPIO_PRESET14_OFFSET        0x0178 /* COUNT14 reload value */
+#define LPC43_SGPIO_PRESET15_OFFSET        0x017c /* COUNT15 reload value */
+
+#define LPC43_SGPIO_COUNT_OFFSET(n)        (0x0180 + ((n) << 2)
+#define LPC43_SGPIO_COUNT0_OFFSET          0x0180 /* Down counter 0 */
+#define LPC43_SGPIO_COUNT1_OFFSET          0x0184 /* Down counter 1 */
+#define LPC43_SGPIO_COUNT2_OFFSET          0x0188 /* Down counter 2 */
+#define LPC43_SGPIO_COUNT3_OFFSET          0x018c /* Down counter 3 */
+#define LPC43_SGPIO_COUNT4_OFFSET          0x0190 /* Down counter 4 */
+#define LPC43_SGPIO_COUNT5_OFFSET          0x0194 /* Down counter 5 */
+#define LPC43_SGPIO_COUNT6_OFFSET          0x0198 /* Down counter 6 */
+#define LPC43_SGPIO_COUNT7_OFFSET          0x019c /* Down counter 7 */
+#define LPC43_SGPIO_COUNT8_OFFSET          0x01a0 /* Down counter 8 */
+#define LPC43_SGPIO_COUNT9_OFFSET          0x01a4 /* Down counter 9 */
+#define LPC43_SGPIO_COUNT10_OFFSET         0x01a8 /* Down counter 10 */
+#define LPC43_SGPIO_COUNT11_OFFSET         0x01ac /* Down counter 11 */
+#define LPC43_SGPIO_COUNT12_OFFSET         0x01b0 /* Down counter 12 */
+#define LPC43_SGPIO_COUNT13_OFFSET         0x01b4 /* Down counter 13 */
+#define LPC43_SGPIO_COUNT14_OFFSET         0x01b8 /* Down counter 14 */
+#define LPC43_SGPIO_COUNT15_OFFSET         0x01bc /* Down counter 15 */
+
+#define LPC43_SGPIO_POS_OFFSET(n)          (0x01c0 + ((n) << 2)
+#define LPC43_SGPIO_POS0_OFFSET            0x01c0 /* Position register 0 */
+#define LPC43_SGPIO_POS1_OFFSET            0x01c4 /* Position register 1 */
+#define LPC43_SGPIO_POS2_OFFSET            0x01c8 /* Position register 2 */
+#define LPC43_SGPIO_POS3_OFFSET            0x01cc /* Position register 3 */
+#define LPC43_SGPIO_POS4_OFFSET            0x01d0 /* Position register 4 */
+#define LPC43_SGPIO_POS5_OFFSET            0x01d4 /* Position register 5 */
+#define LPC43_SGPIO_POS6_OFFSET            0x01d8 /* Position register 6 */
+#define LPC43_SGPIO_POS7_OFFSET            0x01dc /* Position register 7 */
+#define LPC43_SGPIO_POS8_OFFSET            0x01e0 /* Position register 8 */
+#define LPC43_SGPIO_POS9_OFFSET            0x01e4 /* Position register 9 */
+#define LPC43_SGPIO_POS10_OFFSET           0x01e8 /* Position register 0 */
+#define LPC43_SGPIO_POS11_OFFSET           0x01ec /* Position register 1 */
+#define LPC43_SGPIO_POS12_OFFSET           0x01f0 /* Position register 2 */
+#define LPC43_SGPIO_POS13_OFFSET           0x01f4 /* Position register 3 */
+#define LPC43_SGPIO_POS14_OFFSET           0x01f8 /* Position register 4 */
+#define LPC43_SGPIO_POS15_OFFSET           0x01fc /* Position register 5 */
+
+#define LPC43_SGPIO_MASKA_OFFSET           0x0200 /* Mask for pattern match function of slice A */
+#define LPC43_SGPIO_MASKH_OFFSET           0x0204 /* Mask for pattern match function of slice H */
+#define LPC43_SGPIO_MASKI_OFFSET           0x0208 /* Mask for pattern match function of slice I */
+#define LPC43_SGPIO_MASKP_OFFSET           0x020c /* Mask for pattern match function of slice P */
+#define LPC43_SGPIO_GPIO_INREG_OFFSET      0x0210 /* GPIO input status register */
+#define LPC43_SGPIO_GPIO_OUTREG_OFFSET     0x0214 /* GPIO output control register */
+#define LPC43_SGPIO_GPIO_OENREG_OFFSET     0x0218 /* GPIO OE control register */
+#define LPC43_SGPIO_CTRL_ENABLE_OFFSET     0x021c /* Enables the slice COUNT counter */
+#define LPC43_SGPIO_CTRL_DISABLE_OFFSET    0x0220 /* Disables the slice POS counter */
+
+#define LPC43_SGPIO_INT_OFFSET(n)          (0xf00 + ((n) << 5))
+#define LPC43_SGPIO_CLREN_INTOFFSET        0x0000 /* Interrupt clear mask */
+#define LPC43_SGPIO_SETEN_INTOFFSET        0x0004 /* Interrupt set mask */
+#define LPC43_SGPIO_ENABLE_INTOFFSET       0x0008 /* Interrupt enable */
+#define LPC43_SGPIO_STATUS_INTOFFSET       0x000c /* Interrupt status */
+#define LPC43_SGPIO_CLRSTAT_INTOFFSET      0x0010 /* Interrupt clear status */
+#define LPC43_SGPIO_SETSTAT_INTOFFSET      0x0014 /* Interrupt set status */
+
+#define LPC43_SGPIO_CLREN_OFFSET(n)        (LPC43_SGPIO_INT_OFFSET(n)+LPC43_SGPIO_CLREN_INTOFFSET)
+#define LPC43_SGPIO_SETEN_OFFSET(n)        (LPC43_SGPIO_INT_OFFSET(n)+LPC43_SGPIO_SETEN_INTOFFSET)
+#define LPC43_SGPIO_ENABLE_OFFSET(n)       (LPC43_SGPIO_INT_OFFSET(n)+LPC43_SGPIO_ENABLE_INTOFFSET)
+#define LPC43_SGPIO_STATUS_OFFSET(n)       (LPC43_SGPIO_INT_OFFSET(n)+LPC43_SGPIO_STATUS_INTOFFSET)
+#define LPC43_SGPIO_CLRSTAT_OFFSET(n)      (LPC43_SGPIO_INT_OFFSET(n)+LPC43_SGPIO_CLRSTAT_INTOFFSET)
+#define LPC43_SGPIO_SETSTAT_OFFSET(n)      (LPC43_SGPIO_INT_OFFSET(n)+LPC43_SGPIO_SETSTAT_INTOFFSET)
+
+#define LPC43_SGPIO_CLREN0_OFFSET          0x0f00 /* Shift clock interrupt clear mask */
+#define LPC43_SGPIO_SETEN0_OFFSET          0x0f04 /* Shift clock interrupt set mask */
+#define LPC43_SGPIO_ENABLE0_OFFSET         0x0f08 /* Shift clock interrupt enable */
+#define LPC43_SGPIO_STATUS0_OFFSET         0x0f0c /* Shift clock interrupt status */
+#define LPC43_SGPIO_CLRSTAT0_OFFSET        0x0f10 /* Shift clock interrupt clear status */
+#define LPC43_SGPIO_SETSTAT0_OFFSET        0x0f14 /* Shift clock interrupt set status */
+
+#define LPC43_SGPIO_CLREN1_OFFSET          0x0f20 /* Exchange clock interrupt clear mask */
+#define LPC43_SGPIO_SETEN1_OFFSET          0x0f24 /* Exchange clock interrupt set mask */
+#define LPC43_SGPIO_ENABLE1_OFFSET         0x0f28 /* Exchange clock interrupt enable */
+#define LPC43_SGPIO_STATUS1_OFFSET         0x0f2c /* Exchange clock interrupt status */
+#define LPC43_SGPIO_CLRSTAT1_OFFSET        0x0f30 /* Exchange clock interrupt clear status */
+#define LPC43_SGPIO_SETSTAT1_OFFSET        0x0f34 /* Exchange clock interrupt set status */
+
+#define LPC43_SGPIO_CLREN2_OFFSET          0x0f40 /* Pattern match interrupt clear mask */
+#define LPC43_SGPIO_SETEN2_OFFSET          0x0f44 /* Pattern match interrupt set mask */
+#define LPC43_SGPIO_ENABLE2_OFFSET         0x0f48 /* Pattern match interrupt enable */
+#define LPC43_SGPIO_STATUS2_OFFSET         0x0f4c /* Pattern match interrupt status */
+#define LPC43_SGPIO_CLRSTAT2_OFFSET        0x0f50 /* Pattern match interrupt clear status */
+#define LPC43_SGPIO_SETSTAT2_OFFSET        0x0f54 /* Pattern match interrupt set status */
+
+#define LPC43_SGPIO_CLREN3_OFFSET          0x0f60 /* Input interrupt clear mask */
+#define LPC43_SGPIO_SETEN3_OFFSET          0x0f64 /* Input bit match interrupt set mask */
+#define LPC43_SGPIO_ENABLE3_OFFSET         0x0f68 /* Input bit match interrupt enable */
+#define LPC43_SGPIO_STATUS3_OFFSET         0x0f6c /* Input bit match interrupt status */
+#define LPC43_SGPIO_CLRSTAT3_OFFSET        0x0f70 /* Input bit match interrupt clear status */
+#define LPC43_SGPIO_SETSTAT3_OFFSET        0x0f74 /* Input bit match interrupt set status */
+
+/* Register Addresses *******************************************************************************/
+
+#define LPC43_SGPIO_OUT_MUXCFG(n)          (LPC43_SGPIO_BASE+LPC43_SGPIO_OUT_MUXCFG_OFFSET(n))
+#define LPC43_SGPIO_OUT_MUXCFG0            (LPC43_SGPIO_BASE+LPC43_SGPIO_OUT_MUXCFG0_OFFSET)
+#define LPC43_SGPIO_OUT_MUXCFG1            (LPC43_SGPIO_BASE+LPC43_SGPIO_OUT_MUXCFG1_OFFSET)
+#define LPC43_SGPIO_OUT_MUXCFG2            (LPC43_SGPIO_BASE+LPC43_SGPIO_OUT_MUXCFG2_OFFSET)
+#define LPC43_SGPIO_OUT_MUXCFG3            (LPC43_SGPIO_BASE+LPC43_SGPIO_OUT_MUXCFG3_OFFSET)
+#define LPC43_SGPIO_OUT_MUXCFG4            (LPC43_SGPIO_BASE+LPC43_SGPIO_OUT_MUXCFG4_OFFSET)
+#define LPC43_SGPIO_OUT_MUXCFG5            (LPC43_SGPIO_BASE+LPC43_SGPIO_OUT_MUXCFG5_OFFSET)
+#define LPC43_SGPIO_OUT_MUXCFG6            (LPC43_SGPIO_BASE+LPC43_SGPIO_OUT_MUXCFG6_OFFSET)
+#define LPC43_SGPIO_OUT_MUXCFG7            (LPC43_SGPIO_BASE+LPC43_SGPIO_OUT_MUXCFG7_OFFSET)
+#define LPC43_SGPIO_OUT_MUXCFG8            (LPC43_SGPIO_BASE+LPC43_SGPIO_OUT_MUXCFG8_OFFSET)
+#define LPC43_SGPIO_OUT_MUXCFG9            (LPC43_SGPIO_BASE+LPC43_SGPIO_OUT_MUXCFG9_OFFSET)
+#define LPC43_SGPIO_OUT_MUXCFG10           (LPC43_SGPIO_BASE+LPC43_SGPIO_OUT_MUXCFG10_OFFSET)
+#define LPC43_SGPIO_OUT_MUXCFG11           (LPC43_SGPIO_BASE+LPC43_SGPIO_OUT_MUXCFG11_OFFSET)
+#define LPC43_SGPIO_OUT_MUXCFG12           (LPC43_SGPIO_BASE+LPC43_SGPIO_OUT_MUXCFG12_OFFSET)
+#define LPC43_SGPIO_OUT_MUXCFG13           (LPC43_SGPIO_BASE+LPC43_SGPIO_OUT_MUXCFG13_OFFSET)
+#define LPC43_SGPIO_OUT_MUXCFG14           (LPC43_SGPIO_BASE+LPC43_SGPIO_OUT_MUXCFG14_OFFSET)
+#define LPC43_SGPIO_OUT_MUXCFG15           (LPC43_SGPIO_BASE+LPC43_SGPIO_OUT_MUXCFG15_OFFSET)
+
+#define LPC43_SGPIO_MUXCFG(n)              (LPC43_SGPIO_BASE+LPC43_SGPIO_MUXCFG_OFFSET(n))
+#define LPC43_SGPIO_MUXCFG0                (LPC43_SGPIO_BASE+LPC43_SGPIO_MUXCFG0_OFFSET)
+#define LPC43_SGPIO_MUXCFG1                (LPC43_SGPIO_BASE+LPC43_SGPIO_MUXCFG1_OFFSET)
+#define LPC43_SGPIO_MUXCFG2                (LPC43_SGPIO_BASE+LPC43_SGPIO_MUXCFG2_OFFSET)
+#define LPC43_SGPIO_MUXCFG3                (LPC43_SGPIO_BASE+LPC43_SGPIO_MUXCFG3_OFFSET)
+#define LPC43_SGPIO_MUXCFG4                (LPC43_SGPIO_BASE+LPC43_SGPIO_MUXCFG4_OFFSET)
+#define LPC43_SGPIO_MUXCFG5                (LPC43_SGPIO_BASE+LPC43_SGPIO_MUXCFG5_OFFSET)
+#define LPC43_SGPIO_MUXCFG6                (LPC43_SGPIO_BASE+LPC43_SGPIO_MUXCFG6_OFFSET)
+#define LPC43_SGPIO_MUXCFG7                (LPC43_SGPIO_BASE+LPC43_SGPIO_MUXCFG7_OFFSET)
+#define LPC43_SGPIO_MUXCFG8                (LPC43_SGPIO_BASE+LPC43_SGPIO_MUXCFG8_OFFSET)
+#define LPC43_SGPIO_MUXCFG9                (LPC43_SGPIO_BASE+LPC43_SGPIO_MUXCFG9_OFFSET)
+#define LPC43_SGPIO_MUXCFG10               (LPC43_SGPIO_BASE+LPC43_SGPIO_MUXCFG10_OFFSET)
+#define LPC43_SGPIO_MUXCFG11               (LPC43_SGPIO_BASE+LPC43_SGPIO_MUXCFG11_OFFSET)
+#define LPC43_SGPIO_MUXCFG12               (LPC43_SGPIO_BASE+LPC43_SGPIO_MUXCFG12_OFFSET)
+#define LPC43_SGPIO_MUXCFG13               (LPC43_SGPIO_BASE+LPC43_SGPIO_MUXCFG13_OFFSET)
+#define LPC43_SGPIO_MUXCFG14               (LPC43_SGPIO_BASE+LPC43_SGPIO_MUXCFG14_OFFSET)
+#define LPC43_SGPIO_MUXCFG15               (LPC43_SGPIO_BASE+LPC43_SGPIO_MUXCFG15_OFFSET)
+
+#define LPC43_SGPIO_SLICE_MUXCFG(n)        (LPC43_SGPIO_BASE+LPC43_SGPIO_SLICE_MUXCFG_OFFSET(n))
+#define LPC43_SGPIO_SLICE_MUXCFG0          (LPC43_SGPIO_BASE+LPC43_SGPIO_SLICE_MUXCFG0_OFFSET)
+#define LPC43_SGPIO_SLICE_MUXCFG1          (LPC43_SGPIO_BASE+LPC43_SGPIO_SLICE_MUXCFG1_OFFSET)
+#define LPC43_SGPIO_SLICE_MUXCFG2          (LPC43_SGPIO_BASE+LPC43_SGPIO_SLICE_MUXCFG2_OFFSET)
+#define LPC43_SGPIO_SLICE_MUXCFG3          (LPC43_SGPIO_BASE+LPC43_SGPIO_SLICE_MUXCFG3_OFFSET)
+#define LPC43_SGPIO_SLICE_MUXCFG4          (LPC43_SGPIO_BASE+LPC43_SGPIO_SLICE_MUXCFG4_OFFSET)
+#define LPC43_SGPIO_SLICE_MUXCFG5          (LPC43_SGPIO_BASE+LPC43_SGPIO_SLICE_MUXCFG5_OFFSET)
+#define LPC43_SGPIO_SLICE_MUXCFG6          (LPC43_SGPIO_BASE+LPC43_SGPIO_SLICE_MUXCFG6_OFFSET)
+#define LPC43_SGPIO_SLICE_MUXCFG7          (LPC43_SGPIO_BASE+LPC43_SGPIO_SLICE_MUXCFG7_OFFSET)
+#define LPC43_SGPIO_SLICE_MUXCFG8          (LPC43_SGPIO_BASE+LPC43_SGPIO_SLICE_MUXCFG8_OFFSET)
+#define LPC43_SGPIO_SLICE_MUXCFG9          (LPC43_SGPIO_BASE+LPC43_SGPIO_SLICE_MUXCFG9_OFFSET)
+#define LPC43_SGPIO_SLICE_MUXCFG10         (LPC43_SGPIO_BASE+LPC43_SGPIO_SLICE_MUXCFG10_OFFSET)
+#define LPC43_SGPIO_SLICE_MUXCFG11         (LPC43_SGPIO_BASE+LPC43_SGPIO_SLICE_MUXCFG11_OFFSET)
+#define LPC43_SGPIO_SLICE_MUXCFG12         (LPC43_SGPIO_BASE+LPC43_SGPIO_SLICE_MUXCFG12_OFFSET)
+#define LPC43_SGPIO_SLICE_MUXCFG13         (LPC43_SGPIO_BASE+LPC43_SGPIO_SLICE_MUXCFG13_OFFSET)
+#define LPC43_SGPIO_SLICE_MUXCFG14         (LPC43_SGPIO_BASE+LPC43_SGPIO_SLICE_MUXCFG14_OFFSET)
+#define LPC43_SGPIO_SLICE_MUXCFG15         (LPC43_SGPIO_BASE+LPC43_SGPIO_SLICE_MUXCFG15_OFFSET)
+
+#define LPC43_SGPIO_REG(n)                 (LPC43_SGPIO_BASE+LPC43_SGPIO_REG_OFFSET(n))
+#define LPC43_SGPIO_REG0                   (LPC43_SGPIO_BASE+LPC43_SGPIO_REG0_OFFSET)
+#define LPC43_SGPIO_REG1                   (LPC43_SGPIO_BASE+LPC43_SGPIO_REG1_OFFSET)
+#define LPC43_SGPIO_REG2                   (LPC43_SGPIO_BASE+LPC43_SGPIO_REG2_OFFSET)
+#define LPC43_SGPIO_REG3                   (LPC43_SGPIO_BASE+LPC43_SGPIO_REG3_OFFSET)
+#define LPC43_SGPIO_REG4                   (LPC43_SGPIO_BASE+LPC43_SGPIO_REG4_OFFSET)
+#define LPC43_SGPIO_REG5                   (LPC43_SGPIO_BASE+LPC43_SGPIO_REG5_OFFSET)
+#define LPC43_SGPIO_REG6                   (LPC43_SGPIO_BASE+LPC43_SGPIO_REG6_OFFSET)
+#define LPC43_SGPIO_REG7                   (LPC43_SGPIO_BASE+LPC43_SGPIO_REG7_OFFSET)
+#define LPC43_SGPIO_REG8                   (LPC43_SGPIO_BASE+LPC43_SGPIO_REG8_OFFSET)
+#define LPC43_SGPIO_REG9                   (LPC43_SGPIO_BASE+LPC43_SGPIO_REG9_OFFSET)
+#define LPC43_SGPIO_REG10                  (LPC43_SGPIO_BASE+LPC43_SGPIO_REG10_OFFSET)
+#define LPC43_SGPIO_REG11                  (LPC43_SGPIO_BASE+LPC43_SGPIO_REG11_OFFSET)
+#define LPC43_SGPIO_REG12                  (LPC43_SGPIO_BASE+LPC43_SGPIO_REG12_OFFSET)
+#define LPC43_SGPIO_REG13                  (LPC43_SGPIO_BASE+LPC43_SGPIO_REG13_OFFSET)
+#define LPC43_SGPIO_REG14                  (LPC43_SGPIO_BASE+LPC43_SGPIO_REG14_OFFSET)
+#define LPC43_SGPIO_REG15                  (LPC43_SGPIO_BASE+LPC43_SGPIO_REG15_OFFSET)
+
+#define LPC43_SGPIO_REG_SS(n)              (LPC43_SGPIO_BASE+LPC43_SGPIO_REG_SS_OFFSET(n))
+#define LPC43_SGPIO_REG_SS0                (LPC43_SGPIO_BASE+LPC43_SGPIO_REG_SS0_OFFSET)
+#define LPC43_SGPIO_REG_SS1                (LPC43_SGPIO_BASE+LPC43_SGPIO_REG_SS1_OFFSET)
+#define LPC43_SGPIO_REG_SS2                (LPC43_SGPIO_BASE+LPC43_SGPIO_REG_SS2_OFFSET)
+#define LPC43_SGPIO_REG_SS3                (LPC43_SGPIO_BASE+LPC43_SGPIO_REG_SS3_OFFSET)
+#define LPC43_SGPIO_REG_SS4                (LPC43_SGPIO_BASE+LPC43_SGPIO_REG_SS4_OFFSET)
+#define LPC43_SGPIO_REG_SS5                (LPC43_SGPIO_BASE+LPC43_SGPIO_REG_SS5_OFFSET)
+#define LPC43_SGPIO_REG_SS6                (LPC43_SGPIO_BASE+LPC43_SGPIO_REG_SS6_OFFSET)
+#define LPC43_SGPIO_REG_SS7                (LPC43_SGPIO_BASE+LPC43_SGPIO_REG_SS7_OFFSET)
+#define LPC43_SGPIO_REG_SS8                (LPC43_SGPIO_BASE+LPC43_SGPIO_REG_SS8_OFFSET)
+#define LPC43_SGPIO_REG_SS9                (LPC43_SGPIO_BASE+LPC43_SGPIO_REG_SS9_OFFSET)
+#define LPC43_SGPIO_REG_SS10               (LPC43_SGPIO_BASE+LPC43_SGPIO_REG_SS10_OFFSET)
+#define LPC43_SGPIO_REG_SS11               (LPC43_SGPIO_BASE+LPC43_SGPIO_REG_SS11_OFFSET)
+#define LPC43_SGPIO_REG_SS12               (LPC43_SGPIO_BASE+LPC43_SGPIO_REG_SS12_OFFSET)
+#define LPC43_SGPIO_REG_SS13               (LPC43_SGPIO_BASE+LPC43_SGPIO_REG_SS13_OFFSET)
+#define LPC43_SGPIO_REG_SS14               (LPC43_SGPIO_BASE+LPC43_SGPIO_REG_SS14_OFFSET)
+#define LPC43_SGPIO_REG_SS15               (LPC43_SGPIO_BASE+LPC43_SGPIO_REG_SS15_OFFSET)
+
+#define LPC43_SGPIO_PRESET(n)              (LPC43_SGPIO_BASE+LPC43_SGPIO_PRESET_OFFSET(n))
+#define LPC43_SGPIO_PRESET0                (LPC43_SGPIO_BASE+LPC43_SGPIO_PRESET0_OFFSET)
+#define LPC43_SGPIO_PRESET1                (LPC43_SGPIO_BASE+LPC43_SGPIO_PRESET1_OFFSET)
+#define LPC43_SGPIO_PRESET2                (LPC43_SGPIO_BASE+LPC43_SGPIO_PRESET2_OFFSET)
+#define LPC43_SGPIO_PRESET3                (LPC43_SGPIO_BASE+LPC43_SGPIO_PRESET3_OFFSET)
+#define LPC43_SGPIO_PRESET4                (LPC43_SGPIO_BASE+LPC43_SGPIO_PRESET4_OFFSET)
+#define LPC43_SGPIO_PRESET5                (LPC43_SGPIO_BASE+LPC43_SGPIO_PRESET5_OFFSET)
+#define LPC43_SGPIO_PRESET6                (LPC43_SGPIO_BASE+LPC43_SGPIO_PRESET6_OFFSET)
+#define LPC43_SGPIO_PRESET7                (LPC43_SGPIO_BASE+LPC43_SGPIO_PRESET7_OFFSET)
+#define LPC43_SGPIO_PRESET8                (LPC43_SGPIO_BASE+LPC43_SGPIO_PRESET8_OFFSET)
+#define LPC43_SGPIO_PRESET9                (LPC43_SGPIO_BASE+LPC43_SGPIO_PRESET9_OFFSET)
+#define LPC43_SGPIO_PRESET10               (LPC43_SGPIO_BASE+LPC43_SGPIO_PRESET10_OFFSET)
+#define LPC43_SGPIO_PRESET11               (LPC43_SGPIO_BASE+LPC43_SGPIO_PRESET11_OFFSET)
+#define LPC43_SGPIO_PRESET12               (LPC43_SGPIO_BASE+LPC43_SGPIO_PRESET12_OFFSET)
+#define LPC43_SGPIO_PRESET13               (LPC43_SGPIO_BASE+LPC43_SGPIO_PRESET13_OFFSET)
+#define LPC43_SGPIO_PRESET14               (LPC43_SGPIO_BASE+LPC43_SGPIO_PRESET14_OFFSET)
+#define LPC43_SGPIO_PRESET15               (LPC43_SGPIO_BASE+LPC43_SGPIO_PRESET15_OFFSET)
+
+#define LPC43_SGPIO_COUNT(n)               (LPC43_SGPIO_BASE+LPC43_SGPIO_COUNT_OFFSET(n))
+#define LPC43_SGPIO_COUNT0                 (LPC43_SGPIO_BASE+LPC43_SGPIO_COUNT0_OFFSET)
+#define LPC43_SGPIO_COUNT1                 (LPC43_SGPIO_BASE+LPC43_SGPIO_COUNT1_OFFSET)
+#define LPC43_SGPIO_COUNT2                 (LPC43_SGPIO_BASE+LPC43_SGPIO_COUNT2_OFFSET)
+#define LPC43_SGPIO_COUNT3                 (LPC43_SGPIO_BASE+LPC43_SGPIO_COUNT3_OFFSET)
+#define LPC43_SGPIO_COUNT4                 (LPC43_SGPIO_BASE+LPC43_SGPIO_COUNT4_OFFSET)
+#define LPC43_SGPIO_COUNT5                 (LPC43_SGPIO_BASE+LPC43_SGPIO_COUNT5_OFFSET)
+#define LPC43_SGPIO_COUNT6                 (LPC43_SGPIO_BASE+LPC43_SGPIO_COUNT6_OFFSET)
+#define LPC43_SGPIO_COUNT7                 (LPC43_SGPIO_BASE+LPC43_SGPIO_COUNT7_OFFSET)
+#define LPC43_SGPIO_COUNT8                 (LPC43_SGPIO_BASE+LPC43_SGPIO_COUNT8_OFFSET)
+#define LPC43_SGPIO_COUNT9                 (LPC43_SGPIO_BASE+LPC43_SGPIO_COUNT9_OFFSET)
+#define LPC43_SGPIO_COUNT10                (LPC43_SGPIO_BASE+LPC43_SGPIO_COUNT10_OFFSET)
+#define LPC43_SGPIO_COUNT11                (LPC43_SGPIO_BASE+LPC43_SGPIO_COUNT11_OFFSET)
+#define LPC43_SGPIO_COUNT12                (LPC43_SGPIO_BASE+LPC43_SGPIO_COUNT12_OFFSET)
+#define LPC43_SGPIO_COUNT13                (LPC43_SGPIO_BASE+LPC43_SGPIO_COUNT13_OFFSET)
+#define LPC43_SGPIO_COUNT14                (LPC43_SGPIO_BASE+LPC43_SGPIO_COUNT14_OFFSET)
+#define LPC43_SGPIO_COUNT15                (LPC43_SGPIO_BASE+LPC43_SGPIO_COUNT15_OFFSET)
+
+#define LPC43_SGPIO_POS(n)                 (LPC43_SGPIO_BASE+LPC43_SGPIO_POS_OFFSET(n))
+#define LPC43_SGPIO_POS0                   (LPC43_SGPIO_BASE+LPC43_SGPIO_POS0_OFFSET)
+#define LPC43_SGPIO_POS1                   (LPC43_SGPIO_BASE+LPC43_SGPIO_POS1_OFFSET)
+#define LPC43_SGPIO_POS2                   (LPC43_SGPIO_BASE+LPC43_SGPIO_POS2_OFFSET)
+#define LPC43_SGPIO_POS3                   (LPC43_SGPIO_BASE+LPC43_SGPIO_POS3_OFFSET)
+#define LPC43_SGPIO_POS4                   (LPC43_SGPIO_BASE+LPC43_SGPIO_POS4_OFFSET)
+#define LPC43_SGPIO_POS5                   (LPC43_SGPIO_BASE+LPC43_SGPIO_POS5_OFFSET)
+#define LPC43_SGPIO_POS6                   (LPC43_SGPIO_BASE+LPC43_SGPIO_POS6_OFFSET)
+#define LPC43_SGPIO_POS7                   (LPC43_SGPIO_BASE+LPC43_SGPIO_POS7_OFFSET)
+#define LPC43_SGPIO_POS8                   (LPC43_SGPIO_BASE+LPC43_SGPIO_POS8_OFFSET)
+#define LPC43_SGPIO_POS9                   (LPC43_SGPIO_BASE+LPC43_SGPIO_POS9_OFFSET)
+#define LPC43_SGPIO_POS10                  (LPC43_SGPIO_BASE+LPC43_SGPIO_POS10_OFFSET)
+#define LPC43_SGPIO_POS11                  (LPC43_SGPIO_BASE+LPC43_SGPIO_POS11_OFFSET)
+#define LPC43_SGPIO_POS12                  (LPC43_SGPIO_BASE+LPC43_SGPIO_POS12_OFFSET)
+#define LPC43_SGPIO_POS13                  (LPC43_SGPIO_BASE+LPC43_SGPIO_POS13_OFFSET)
+#define LPC43_SGPIO_POS14                  (LPC43_SGPIO_BASE+LPC43_SGPIO_POS14_OFFSET)
+#define LPC43_SGPIO_POS15                  (LPC43_SGPIO_BASE+LPC43_SGPIO_POS15_OFFSET)
+
+#define LPC43_SGPIO_MASKA                  (LPC43_SGPIO_BASE+LPC43_SGPIO_MASKA_OFFSET)
+#define LPC43_SGPIO_MASKH                  (LPC43_SGPIO_BASE+LPC43_SGPIO_MASKH_OFFSET)
+#define LPC43_SGPIO_MASKI                  (LPC43_SGPIO_BASE+LPC43_SGPIO_MASKI_OFFSET)
+#define LPC43_SGPIO_MASKP                  (LPC43_SGPIO_BASE+LPC43_SGPIO_MASKP_OFFSET)
+#define LPC43_SGPIO_GPIO_INREG             (LPC43_SGPIO_BASE+LPC43_SGPIO_GPIO_INREG_OFFSET)
+#define LPC43_SGPIO_GPIO_OUTREG            (LPC43_SGPIO_BASE+LPC43_SGPIO_GPIO_OUTREG_OFFSET)
+#define LPC43_SGPIO_GPIO_OENREG            (LPC43_SGPIO_BASE+LPC43_SGPIO_GPIO_OENREG_OFFSET)
+#define LPC43_SGPIO_CTRL_ENABLE            (LPC43_SGPIO_BASE+LPC43_SGPIO_CTRL_ENABLE_OFFSET)
+#define LPC43_SGPIO_CTRL_DISABLE           (LPC43_SGPIO_BASE+LPC43_SGPIO_CTRL_DISABLE_OFFSET)
+
+#define LPC43_SGPIO_INT(n)                 (LPC43_SGPIO_BASE+LPC43_SGPIO_INT_OFFSET(n))
+#define LPC43_SGPIO_CLREN(n)               (LPC43_SGPIO_BASE+LPC43_SGPIO_CLREN_OFFSET(n))
+#define LPC43_SGPIO_SETEN(n)               (LPC43_SGPIO_BASE+LPC43_SGPIO_SETEN_OFFSET(n))
+#define LPC43_SGPIO_ENABLE(n)              (LPC43_SGPIO_BASE+LPC43_SGPIO_ENABLE_OFFSET(n))
+#define LPC43_SGPIO_STATUS(n)              (LPC43_SGPIO_BASE+LPC43_SGPIO_STATUS_OFFSET(n))
+#define LPC43_SGPIO_CLRSTAT(n)             (LPC43_SGPIO_BASE+LPC43_SGPIO_CLRSTAT_OFFSET(n))
+#define LPC43_SGPIO_SETSTAT(n)             (LPC43_SGPIO_BASE+LPC43_SGPIO_SETSTAT_OFFSET(n))
+
+#define LPC43_SGPIO_CLREN0                 (LPC43_SGPIO_BASE+LPC43_SGPIO_CLREN0_OFFSET)
+#define LPC43_SGPIO_SETEN0                 (LPC43_SGPIO_BASE+LPC43_SGPIO_SETEN0_OFFSET)
+#define LPC43_SGPIO_ENABLE0                (LPC43_SGPIO_BASE+LPC43_SGPIO_ENABLE0_OFFSET)
+#define LPC43_SGPIO_STATUS0                (LPC43_SGPIO_BASE+LPC43_SGPIO_STATUS0_OFFSET)
+#define LPC43_SGPIO_CLRSTAT0               (LPC43_SGPIO_BASE+LPC43_SGPIO_CLRSTAT0_OFFSET)
+#define LPC43_SGPIO_SETSTAT0               (LPC43_SGPIO_BASE+LPC43_SGPIO_SETSTAT0_OFFSET)
+
+#define LPC43_SGPIO_CLREN1                 (LPC43_SGPIO_BASE+LPC43_SGPIO_CLREN1_OFFSET)
+#define LPC43_SGPIO_SETEN1                 (LPC43_SGPIO_BASE+LPC43_SGPIO_SETEN1_OFFSET)
+#define LPC43_SGPIO_ENABLE1                (LPC43_SGPIO_BASE+LPC43_SGPIO_ENABLE1_OFFSET)
+#define LPC43_SGPIO_STATUS1                (LPC43_SGPIO_BASE+LPC43_SGPIO_STATUS1_OFFSET)
+#define LPC43_SGPIO_CLRSTAT1               (LPC43_SGPIO_BASE+LPC43_SGPIO_CLRSTAT1_OFFSET)
+#define LPC43_SGPIO_SETSTAT1               (LPC43_SGPIO_BASE+LPC43_SGPIO_SETSTAT1_OFFSET)
+
+#define LPC43_SGPIO_CLREN2                 (LPC43_SGPIO_BASE+LPC43_SGPIO_CLREN2_OFFSET)
+#define LPC43_SGPIO_SETEN2                 (LPC43_SGPIO_BASE+LPC43_SGPIO_SETEN2_OFFSET)
+#define LPC43_SGPIO_ENABLE2                (LPC43_SGPIO_BASE+LPC43_SGPIO_ENABLE2_OFFSET)
+#define LPC43_SGPIO_STATUS2                (LPC43_SGPIO_BASE+LPC43_SGPIO_STATUS2_OFFSET)
+#define LPC43_SGPIO_CLRSTAT2               (LPC43_SGPIO_BASE+LPC43_SGPIO_CLRSTAT2_OFFSET)
+#define LPC43_SGPIO_SETSTAT2               (LPC43_SGPIO_BASE+LPC43_SGPIO_SETSTAT2_OFFSET)
+
+#define LPC43_SGPIO_CLREN3                 (LPC43_SGPIO_BASE+LPC43_SGPIO_CLREN3_OFFSET)
+#define LPC43_SGPIO_SETEN3                 (LPC43_SGPIO_BASE+LPC43_SGPIO_SETEN3_OFFSET)
+#define LPC43_SGPIO_ENABLE3                (LPC43_SGPIO_BASE+LPC43_SGPIO_ENABLE3_OFFSET)
+#define LPC43_SGPIO_STATUS3                (LPC43_SGPIO_BASE+LPC43_SGPIO_STATUS3_OFFSET)
+#define LPC43_SGPIO_CLRSTAT3               (LPC43_SGPIO_BASE+LPC43_SGPIO_CLRSTAT3_OFFSET)
+#define LPC43_SGPIO_SETSTAT3               (LPC43_SGPIO_BASE+LPC43_SGPIO_SETSTAT3_OFFSET)
+
+/* Register Bit Definitions *************************************************************************/
+
+/* Pin multiplexer configuration registers */
+
+#define SGPIO_OUT_MUXCFG_OUTCFG_SHIFT      (0)       /* Bits 0-3: P_OUT_CFG Output control SGPIOn */
+#define SGPIO_OUT_MUXCFG_OUTCFG_MASK       (15 << SGPIO_OUT_MUXCFG_OUTCFG_SHIFT)
+#  define SGPIO_OUT_MUXCFG_OUTCFG_DOUTM1   (0 << SGPIO_OUT_MUXCFG_OUTCFG_SHIFT)  /* dout_doutm1 (1-bit mode) */
+#  define SGPIO_OUT_MUXCFG_OUTCFG_ DOUTM2A (1 << SGPIO_OUT_MUXCFG_OUTCFG_SHIFT)  /* dout_doutm2a (2-bit mode 2a) */
+#  define SGPIO_OUT_MUXCFG_OUTCFG_DOUTM2B  (2 << SGPIO_OUT_MUXCFG_OUTCFG_SHIFT)  /* dout_doutm2b (2-bit mode 2b) */
+#  define SGPIO_OUT_MUXCFG_OUTCFG_DOUTM2C  (3 << SGPIO_OUT_MUXCFG_OUTCFG_SHIFT)  /* dout_doutm2c (2-bit mode 2c) */
+#  define SGPIO_OUT_MUXCFG_OUTCFG_GPIOOUT  (4 << SGPIO_OUT_MUXCFG_OUTCFG_SHIFT)  /* gpio_out (level set by GPIO_OUTREG) */
+#  define SGPIO_OUT_MUXCFG_OUTCFG_DOUTM4A  (5 << SGPIO_OUT_MUXCFG_OUTCFG_SHIFT)  /* dout_doutm4a (4-bit mode 4a) */
+#  define SGPIO_OUT_MUXCFG_OUTCFG_DOUTM4B  (6 << SGPIO_OUT_MUXCFG_OUTCFG_SHIFT)  /* dout_doutm4b (4-bit mode 4b) */
+#  define SGPIO_OUT_MUXCFG_OUTCFG_DOUTM4C  (7 << SGPIO_OUT_MUXCFG_OUTCFG_SHIFT)  /* dout_doutm4c (4-bit mode 4c) */
+#  define SGPIO_OUT_MUXCFG_OUTCFG_CLKOUT   (8 << SGPIO_OUT_MUXCFG_OUTCFG_SHIFT)  /* clk_out */
+#  define SGPIO_OUT_MUXCFG_OUTCFG_DOUTM8A  (9 << SGPIO_OUT_MUXCFG_OUTCFG_SHIFT)  /* dout_doutm8a (8-bit mode 8a) */
+#  define SGPIO_OUT_MUXCFG_OUTCFG_DOUTM8B  (10 << SGPIO_OUT_MUXCFG_OUTCFG_SHIFT) /* dout_doutm8b (8-bit mode 8b) */
+#  define SGPIO_OUT_MUXCFG_OUTCFG_DOUTM8C  (11 << SGPIO_OUT_MUXCFG_OUTCFG_SHIFT) /* dout_doutm8c (8-bit mode 8c) */
+#define SGPIO_OUT_MUXCFG_OECFG_SHIFT       (4)       /* Bits 4-6: P_OE_CFG Output enable source */
+#define SGPIO_OUT_MUXCFG_OECFG_MASK        (7 << SGPIO_OUT_MUXCFG_OECFG_SHIFT)
+#  define SGPIO_OUT_MUXCFG_OECFG_GPIOOE    (0 << SGPIO_OUT_MUXCFG_OECFG_SHIFT) /* gpio_oe (state set by GPIO_OEREG) */
+#  define SGPIO_OUT_MUXCFG_OECFG_OEM1      (4 << SGPIO_OUT_MUXCFG_OECFG_SHIFT) /* dout_oem1 (1-bit mode) */
+#  define SGPIO_OUT_MUXCFG_OECFG_OEM2      (5 << SGPIO_OUT_MUXCFG_OECFG_SHIFT) /* dout_oem2 (2-bit mode) */
+#  define SGPIO_OUT_MUXCFG_OECFG_OEM4      (6 << SGPIO_OUT_MUXCFG_OECFG_SHIFT) /* dout_oem4 (4-bit mode) */
+#  define SGPIO_OUT_MUXCFG_OECFG_OEM8      (7 << SGPIO_OUT_MUXCFG_OECFG_SHIFT) /* dout_oem8 (8-bit mode) */
+                                                     /* Bits 7-31:  Reserved */
+/* SGPIO multiplexer configuration registers */
+
+#define SGPIO_MUXCFG_EXTCLK                (1 << 9)  /* Bit 9:  Select clock signal */
+#define SGPIO_MUXCFG_CS_PMODE_SHIFT        (1)       /* Bits 1-2: Select source clock pin */
+#define SGPIO_MUXCFG_CS_PMODE_MASK         (3 << SGPIO_MUXCFG_CS_PMODE_SHIFT)
+#  define SGPIO_MUXCFG_CS_PMODE_SGPIO8     (0 << SGPIO_MUXCFG_CS_PMODE_SHIFT)
+#  define SGPIO_MUXCFG_CS_PMODE_SGPIO9     (1 << SGPIO_MUXCFG_CS_PMODE_SHIFT)
+#  define SGPIO_MUXCFG_CS_PMODE_SGPIO10    (2 << SGPIO_MUXCFG_CS_PMODE_SHIFT)
+#  define SGPIO_MUXCFG_CS_PMODE_SGPIO11    (3 << SGPIO_MUXCFG_CS_PMODE_SHIFT)
+#define SGPIO_MUXCFG_CS_SMODE_SHIFT        (3)       /* Bits 3-4: CLK_SOURCE_SLICE_MODE Select clock source slice */
+#define SGPIO_MUXCFG_CS_SMODE_MASK         (3 << SGPIO_MUXCFG_CS_SMODE_SHIFT)
+#  define SGPIO_MUXCFG_CS_SMODE_SLICED     (0 << SGPIO_MUXCFG_CS_SMODE_SHIFT)
+#  define SGPIO_MUXCFG_CS_SMODE_SLICEH     (1 << SGPIO_MUXCFG_CS_SMODE_SHIFT)
+#  define SGPIO_MUXCFG_CS_SMODE_SLICEO     (2 << SGPIO_MUXCFG_CS_SMODE_SHIFT)
+#  define SGPIO_MUXCFG_CS_SMODE_SLICEP     (3 << SGPIO_MUXCFG_CS_SMODE_SHIFT)
+#define SGPIO_MUXCFG_QUAL_MODE_SHIFT       (5)       /* Bits 5-6: Select qualifier mode */
+#define SGPIO_MUXCFG_QUAL_MODE_MASK        (3 << SGPIO_MUXCFG_QUAL_MODE_SHIFT)
+#  define SGPIO_MUXCFG_QUAL_MODE_ENABLE    (0 << SGPIO_MUXCFG_QUAL_MODE_SHIFT) /* Enable */
+#  define SGPIO_MUXCFG_QUAL_MODE_DISABLE   (1 << SGPIO_MUXCFG_QUAL_MODE_SHIFT) /* Disable */
+#  define SGPIO_MUXCFG_QUAL_MODE_SLICE     (2 << SGPIO_MUXCFG_QUAL_MODE_SHIFT) /* Slice */
+#  define SGPIO_MUXCFG_QUAL_MODE_SGPIO     (3 << SGPIO_MUXCFG_QUAL_MODE_SHIFT) /* External SGPIO pin (8, 9, 10, or 11) */
+#define SGPIO_MUXCFG_QUAL_PMODE_SHIFT      (7)       /* Bits 7-8: Select qualifier pin */
+#define SGPIO_MUXCFG_QUAL_PMODE_MASK       (3 << SGPIO_MUXCFG_QUAL_PMODE_SHIFT)
+#  define SGPIO_MUXCFG_QUAL_PMODE_SGPIO8   (0 << SGPIO_MUXCFG_QUAL_PMODE_SHIFT)
+#  define SGPIO_MUXCFG_QUAL_PMODE_SGPIO9   (1 << SGPIO_MUXCFG_QUAL_PMODE_SHIFT)
+#  define SGPIO_MUXCFG_QUAL_PMODE_SGPIO10  (2 << SGPIO_MUXCFG_QUAL_PMODE_SHIFT)
+#  define SGPIO_MUXCFG_QUAL_PMODE_SGPIO11  (3 << SGPIO_MUXCFG_QUAL_PMODE_SHIFT)
+#define SGPIO_MUXCFG_QUAL_SMODE_SHIFT      (9)       /* Bits 9-10: Select qualifier slice */
+#define SGPIO_MUXCFG_QUAL_SMODE_MASK       (3 << SGPIO_MUXCFG_QUAL_SMODE_SHIFT)
+#  define SGPIO_MUXCFG_QUAL_SMODE_SLICEA   (0 << SGPIO_MUXCFG_QUAL_SMODE_SHIFT) /* Slice A, but for slice A slice D is used */
+#  define SGPIO_MUXCFG_QUAL_SMODE_SLICEH   (1 << SGPIO_MUXCFG_QUAL_SMODE_SHIFT) /* Slice H, but for slice H slice O is used */
+#  define SGPIO_MUXCFG_QUAL_SMODE_SLICEI   (2 << SGPIO_MUXCFG_QUAL_SMODE_SHIFT) /* Slice I, but for slice I slice D is used */
+#  define SGPIO_MUXCFG_QUAL_SMODE_SLICEP   (3 << SGPIO_MUXCFG_QUAL_SMODE_SHIFT) /* Slice P, but for slice P slice O is used */
+#define SGPIO_MUXCFG_CONCAT                (1 << 11) /* Bit 11: Enable concatenation */
+#define SGPIO_MUXCFG_CONCAT_ORDER_SHIFT    (12)      /* Bits 12-13: CONCAT_ORDER Select concatenation order */
+#define SGPIO_MUXCFG_CONCAT_ORDER_MASK     (3 << SGPIO_MUXCFG_CONCAT_ORDER_SHIFT)
+#  define SGPIO_MUXCFG_CONCAT_ORDER_SELT   (0 << SGPIO_MUXCFG_CONCAT_ORDER_SHIFT) /* Self-loop */
+#  define SGPIO_MUXCFG_CONCAT_ORDER_S2     (1 << SGPIO_MUXCFG_CONCAT_ORDER_SHIFT) /* 2 slices */
+#  define SGPIO_MUXCFG_CONCAT_ORDER_S4     (2 << SGPIO_MUXCFG_CONCAT_ORDER_SHIFT) /* 4 slices */
+#  define SGPIO_MUXCFG_CONCAT_ORDER_S8     (3 << SGPIO_MUXCFG_CONCAT_ORDER_SHIFT) /* 8 slices */
+                                                     /* Bits 14-31:  Reserved */
+/* Slice multiplexer configuration register 0 */
+
+#define SGPIO_SLICE_MUXCFG_MATCH           (1 << 0)  /* Bit 0:  Match mode */
+#define SGPIO_SLICE_MUXCFG_CAPTURE         (1 << 1)  /* Bit 1:  Capture clock mode */
+#define SGPIO_SLICE_MUXCFG_CLKGEN          (1 << 2)  /* Bit 2:  Clock generation mode */
+#define SGPIO_SLICE_MUXCFG_INTOUTCLK       (1 << 3)  /* Bit 3:  Invert output clock */
+#define SGPIO_SLICE_MUXCFG_CAPMODE_SHIFT   (4)       /* Bits 4-5: Condition for input bit match interrupt */
+#define SGPIO_SLICE_MUXCFG_CAPMODE_MASK    (3 << SGPIO_SLICE_MUXCFG_CAPMODE_SHIFT)
+#  define SGPIO_SLICE_MUXCFG_CAPMODE_RISING  (0 << SGPIO_SLICE_MUXCFG_CAPMODE_SHIFT) /* Detect rising edge */
+#  define SGPIO_SLICE_MUXCFG_CAPMODE_FALLING (1 << SGPIO_SLICE_MUXCFG_CAPMODE_SHIFT) /* Detect falling edge */
+#  define SGPIO_SLICE_MUXCFG_CAPMODE_LOW     (2 << SGPIO_SLICE_MUXCFG_CAPMODE_SHIFT) /* Detect LOW level */
+#  define SGPIO_SLICE_MUXCFG_CAPMODE_HIGH    (3 << SGPIO_SLICE_MUXCFG_CAPMODE_SHIFT) /* Detect HIGH level */
+#define SGPIO_SLICE_MUXCFG_PARMODE_SHIFT   (6)       /* Bits 6-7: Parallel mode */
+#define SGPIO_SLICE_MUXCFG_PARMODE_MASK    (3 << SGPIO_SLICE_MUXCFG_PARMODE_SHIFT)
+#  define SGPIO_SLICE_MUXCFG_PARMODE_SHIFT1  (0 << SGPIO_SLICE_MUXCFG_PARMODE_SHIFT) /* Shift 1 bit per clock */
+#  define SGPIO_SLICE_MUXCFG_PARMODE_SHIFT2  (1 << SGPIO_SLICE_MUXCFG_PARMODE_SHIFT) /* Shift 2 bits per clock */
+#  define SGPIO_SLICE_MUXCFG_PARMODE_SHIFT4  (2 << SGPIO_SLICE_MUXCFG_PARMODE_SHIFT) /* Shift 4 bits per clock */
+#  define SGPIO_SLICE_MUXCFG_PARMODE_SHIFT8  (3 << SGPIO_SLICE_MUXCFG_PARMODE_SHIFT) /* Shift 1 byte per clock */
+#define SGPIO_SLICE_MUXCFG_INVQUAL         (1 << 8)  /* Bit 8:  Inversion qualifier */
+                                                     /* Bits 9-31: Reserved */
+/* Slice data registers (32-bit data) */
+/* Slice data shadow registers (32-bit data) */
+
+/* COUNTn reload value (32-bit data) */
+
+#define SGPIO_PRESET_MASK                  (0xfff)   /* Bits 0-11: Counter reload value */
+                                                     /* Bits 12-31: Reserved */
+/* Down counter registers */
+
+#define SGPIO_COUNT_MASK                   (0xfff)   /* Bits 0-11: Down counter */
+                                                     /* Bits 12-31: Reserved */
+/* Position registers */
+
+#define SGPIO_POS_POS_SHIFT                (0)       /* Bits 0-7: Each time COUNT reaches zero POS counts down */
+#define SGPIO_POS_POS_MASK                 (0xffff << SGPIO_POS_POS_SHIFT)
+#define SGPIO_POS_RESET_SHIFT              (8)       /* Bits 8-15: Reload value for POS after POS reaches zero */
+#define SGPIO_POS_RESET_MASK               (0xffff << SGPIO_POS_RESET_SHIFT)
+                                                     /* Bits 16-31: Reserved */
+/* Mask for pattern match function of slice A (32-bit bit mask) */
+/* Mask for pattern match function of slice H (32-bit bit mask) */
+/* Mask for pattern match function of slice I (32-bit bit mask) */
+/* Mask for pattern match function of slice P (32-bit bit mask) */
+
+/* Common bit mask that can be used in all interrupt registers */
+
+#define SGPIO_SLICE(n)                     (1 << (n)) /* Bits 0-15: Bit n corresponids to slice n */
+                                                      /* Bits 16-31: Reserved */
+/* GPIO input status register */
+
+#define SGPIO_GPIO_INREG(n)                (1 << (n)) /* Bits 0-15: Bit i reflects the input state of SGPIO pin  */
+                                                      /* Bits 16-31: Reserved */
+/* GPIO output control register */
+
+#define SGPIO_GPIO_OUTREG(n)               (1 << (n)) /* Bits 0-15: Bit i sets the output of SGPIO pin i */
+                                                      /* Bits 16-31: Reserved */
+/* GPIO output enable register */
+
+#define SGPIO_GPIO_OENREG(n)               (1 << (n)) /* Bits 0-15: Bit i selects the output enable state of SGPIO pin i */
+                                                      /* Bits 16-31: Reserved */
+/* Slice count enable register */
+
+#define SGPIO_CTRL_ENABLE(n)               (1 << (n)) /* Bits 0-15: Bit n controls slice n */
+                                                      /* Bits 16-31: Reserved */
+/* Slice count disable register */
+
+#define SGPIO_CTRL_DISABLE(n)              (1 << (n)) /* Bits 0-15: Bit n controls slice n */
+                                                      /* Bits 16-31: Reserved */
+/* Shift clock interrupt clear mask */
+
+#define SGPIO_CLREN0(n)                    (1 << (n)) /* Bits 0-15: Bit n shift clock interrupt clear mask of slice n */
+                                                      /* Bits 16-31: Reserved */
+/* Shift clock interrupt set mask */
+
+#define SGPIO_SETEN0(n)                    (1 << (n)) /* Bits 0-15: Bit n shift clock interrupt clear mask of slice n */
+                                                      /* Bits 16-31: Reserved */
+/* Shift clock interrupt enable */
+
+#define SGPIO_ENABLE0(n)                   (1 << (n)) /* Bits 0-15: Bit n shift clock interrupt enable of slice n */
+                                                      /* Bits 16-31: Reserved */
+/* Shift clock interrupt status */
+
+#define SGPIO_STATUS0(n)                   (1 << (n)) /* Bits 0-15: Bit n shift clock interrupt status of slice n */
+                                                      /* Bits 16-31: Reserved */
+/* Shift clock interrupt clear status */
+
+#define SGPIO_CLRSTAT0(n)                  (1 << (n)) /* Bits 0-15: Bit n shift clears interrupt status of slice n */
+                                                      /* Bits 16-31: Reserved */
+/* Shift clock interrupt set status */
+
+#define SGPIO_SETSTAT0(n)                  (1 << (n)) /* Bits 0-15: Bit n shift sets interrupt status of slice n */
+                                                      /* Bits 16-31: Reserved */
+/* Exchange clock interrupt clear mask */
+
+#define SGPIO_CLREN1(n)                    (1 << (n)) /* Bits 0-15: Bit n clears exchange clock interrupt mask of slice n */
+                                                      /* Bits 16-31: Reserved */
+/* Exchange clock interrupt set mask */
+
+#define SGPIO_SETEN1(n)                    (1 << (n)) /* Bits 0-15: Bit n sets exchange clock interrupt mask of slice n */
+                                                      /* Bits 16-31: Reserved */
+/* Exchange clock interrupt enable */
+
+#define SGPIO_ENABLE1(n)                   (1 << (n)) /* Bits 0-15: Bit n enables exchange clock interrupt of slice n */
+                                                      /* Bits 16-31: Reserved */
+/* Exchange clock interrupt status */
+
+#define SGPIO_STATUS1(n)                   (1 << (n)) /* Bits 0-15: Bit n status of exchange clock interrupt of slice n */
+                                                      /* Bits 16-31: Reserved */
+/* Exchange clock interrupt clear status */
+
+#define SGPIO_CLRSTAT1(n)                  (1 << (n)) /* Bits 0-15: Bit n clears exchange clock interrupt status of slice n */
+                                                      /* Bits 16-31: Reserved */
+/* Exchange clock interrupt set status */
+
+#define SGPIO_SETSTAT1(n)                  (1 << (n)) /* Bits 0-15: Bit n sets exchange clock interrupt status of slice n */
+                                                      /* Bits 16-31: Reserved */
+/* Pattern match interrupt clear mask */
+
+#define SGPIO_CLREN2(n)                    (1 << (n)) /* Bits 0-15: Bit n clears match interrupt mask of slice n */
+                                                      /* Bits 16-31: Reserved */
+/* Pattern match interrupt set mask */
+
+#define SGPIO_SETEN2(n)                    (1 << (n)) /* Bits 0-15: Bit n sets match interrupt mask of slice n */
+                                                      /* Bits 16-31: Reserved */
+/* Pattern match interrupt enable */
+
+#define SGPIO_ENABLE2(n)                   (1 << (n)) /* Bits 0-15: Bit n enables match interrupt of slice n */
+                                                      /* Bits 16-31: Reserved */
+/* Pattern match interrupt status */
+
+#define SGPIO_STATUS2(n)                   (1 << (n)) /* Bits 0-15: Bit n is match interrupt status of slice n */
+                                                      /* Bits 16-31: Reserved */
+/* Pattern match interrupt clear status */
+
+#define SGPIO_CLRSTAT2(n)                  (1 << (n)) /* Bits 0-15: Bit n sets match interrupt status of slice n */
+                                                      /* Bits 16-31: Reserved */
+/* Pattern match interrupt set status */
+
+#define SGPIO_SETSTAT2(n)                  (1 << (n)) /* Bits 0-15: Bit n sets match interrupt status of slice n */
+                                                      /* Bits 16-31: Reserved */
+/* Input interrupt clear mask */
+
+#define SGPIO_CLREN3(n)                    (1 << (n)) /* Bits 0-15: Bit n clears input interrupt mask of slice n */
+                                                      /* Bits 16-31: Reserved */
+/* Input bit match interrupt set mask */
+
+#define SGPIO_SETEN3(n)                    (1 << (n)) /* Bits 0-15: Bit n sets input interrupt mask of slice n */
+                                                      /* Bits 16-31: Reserved */
+/* Input bit match interrupt enable */
+
+#define SGPIO_ENABLE3(n)                   (1 << (n)) /* Bits 0-15: Bit n enables input interrupt of slice n */
+                                                      /* Bits 16-31: Reserved */
+/* Input bit match interrupt status */
+
+#define SGPIO_STATUS3(n)                   (1 << (n)) /* Bits 0-15: Bit n is input interrupt status of slice n */
+                                                      /* Bits 16-31: Reserved */
+/* Input bit match interrupt clear status */
+
+#define SGPIO_CLRSTAT3(n)                  (1 << (n)) /* Bits 0-15: Bit n clears input interrupt status of slice n */
+                                                      /* Bits 16-31: Reserved */
+/* Input bit match interrupt set status */
+
+#define SGPIO_SETSTAT3(n)                  (1 << (n)) /* Bits 0-15: Bit n sets match interrupt status of slice n */
+                                                      /* Bits 16-31: Reserved */
+
+/****************************************************************************************************
+ * Public Types
+ ****************************************************************************************************/
+
+/****************************************************************************************************
+ * Public Data
+ ****************************************************************************************************/
+
+/****************************************************************************************************
+ * Public Functions
+ ****************************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_SGPIO_H */
diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_spi.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_spi.h
new file mode 100644
index 000000000..5f6e26d6b
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_spi.h
@@ -0,0 +1,138 @@
+/************************************************************************************
+ * arch/arm/src/lpc43xx/lpc43_spi.h
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_SPI_H
+#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_SPI_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Register offsets *****************************************************************/
+
+#define LPC43_SPI_CR_OFFSET  0x0000  /* Control Register */
+#define LPC43_SPI_SR_OFFSET  0x0004  /* SPI Status Register */
+#define LPC43_SPI_DR_OFFSET  0x0008  /* SPI Data Register */
+#define LPC43_SPI_CCR_OFFSET 0x000c  /* SPI Clock Counter Register */
+#define LPC43_SPI_TCR_OFFSET 0x0010  /* SPI Test Control Register */
+#define LPC43_SPI_TSR_OFFSET 0x0014  /* SPI Test Status Register */
+#define LPC43_SPI_INT_OFFSET 0x001c  /* SPI Interrupt Register */
+
+/* Register addresses ***************************************************************/
+
+#define LPC43_SPI_CR         (LPC43_SPI_BASE+LPC43_SPI_CR_OFFSET)
+#define LPC43_SPI_SR         (LPC43_SPI_BASE+LPC43_SPI_SR_OFFSET)
+#define LPC43_SPI_DR         (LPC43_SPI_BASE+LPC43_SPI_DR_OFFSET)
+#define LPC43_SPI_CCR        (LPC43_SPI_BASE+LPC43_SPI_CCR_OFFSET)
+#define LPC43_TCR_CCR        (LPC43_SPI_BASE+LPC43_SPI_TCR_OFFSET)
+#define LPC43_TSR_CCR        (LPC43_SPI_BASE+LPC43_SPI_TSR_OFFSET)
+#define LPC43_SPI_INT        (LPC43_SPI_BASE+LPC43_SPI_INT_OFFSET)
+
+/* Register bit definitions *********************************************************/
+
+/* Control Register */
+                                       /* Bits 0-1: Reserved */
+#define SPI_CR_BITENABLE     (1 << 2)  /* Bit 2:  Enable word size selected by BITS */
+#define SPI_CR_CPHA          (1 << 3)  /* Bit 3:  Clock phase control */
+#define SPI_CR_CPOL          (1 << 4)  /* Bit 4:  Clock polarity control */
+#define SPI_CR_MSTR          (1 << 5)  /* Bit 5:  Master mode select */
+#define SPI_CR_LSBF          (1 << 6)  /* Bit 6:  SPI data is transferred LSB first */
+#define SPI_CR_SPIE          (1 << 7)  /* Bit 7:  Serial peripheral interrupt enable */
+#define SPI_CR_BITS_SHIFT    (8)       /* Bits 8-11: Number of bits per word (BITENABLE==1) */
+#define SPI_CR_BITS_MASK     (15 << SPI_CR_BITS_SHIFT)
+#  define SPI_CR_BITS_8BITS  (8 <<  SPI_CR_BITS_SHIFT) /* 8 bits per transfer */
+#  define SPI_CR_BITS_9BITS  (9 <<  SPI_CR_BITS_SHIFT) /* 9 bits per transfer */
+#  define SPI_CR_BITS_10BITS (10 << SPI_CR_BITS_SHIFT) /* 10 bits per transfer */
+#  define SPI_CR_BITS_11BITS (11 << SPI_CR_BITS_SHIFT) /* 11 bits per transfer */
+#  define SPI_CR_BITS_12BITS (12 << SPI_CR_BITS_SHIFT) /* 12 bits per transfer */
+#  define SPI_CR_BITS_13BITS (13 << SPI_CR_BITS_SHIFT) /* 13 bits per transfer */
+#  define SPI_CR_BITS_14BITS (14 << SPI_CR_BITS_SHIFT) /* 14 bits per transfer */
+#  define SPI_CR_BITS_15BITS (15 << SPI_CR_BITS_SHIFT) /* 15 bits per transfer */
+#  define SPI_CR_BITS_16BITS (0 <<  SPI_CR_BITS_SHIFT) /* 16 bits per transfer */
+                                       /* Bits 12-31: Reserved */
+/* SPI Status Register */
+                                       /* Bits 0-2: Reserved */
+#define SPI_SR_ABRT          (1 << 3)  /* Bit 3:  Slave abort */
+#define SPI_SR_MODF          (1 << 4)  /* Bit 4:  Mode fault */
+#define SPI_SR_ROVR          (1 << 5)  /* Bit 5:  Read overrun */
+#define SPI_SR_WCOL          (1 << 6)  /* Bit 6:  Write collision */
+#define SPI_SR_SPIF          (1 << 7)  /* Bit 7:  SPI transfer complete */
+                                       /* Bits 8-31: Reserved */
+/* SPI Data Register */
+
+#define SPI_DR_MASK          (0xff)    /* Bits 0-15: SPI Bi-directional data port */
+#define SPI_DR_MASKWIDE      (0xffff)  /* Bits 0-15: If SPI_CR_BITENABLE != 0 */
+                                       /* Bits 8-31: Reserved */
+/* SPI Clock Counter Register */
+
+#define SPI_CCR_MASK         (0xff)    /* Bits 0-7: SPI Clock counter setting */
+                                       /* Bits 8-31: Reserved */
+/* SPI Test Control Register */
+                                       /* Bit 0: Reserved */
+#define SPI_TCR_TEST_SHIFT   (1)       /* Bits 1-7: SPI test mode */
+#define SPI_TCR_TEST_MASK    (0x7f << SPI_TCR_TEST_SHIFT)
+                                       /* Bits 8-31: Reserved */
+/* SPI Test Status Register */
+                                       /* Bits 0-2: Reserved */
+#define SPI_TSR_ABRT         (1 << 3)  /* Bit 3:  Slave abort */
+#define SPI_TSR_MODF         (1 << 4)  /* Bit 4:  Mode fault */
+#define SPI_TSR_ROVR         (1 << 5)  /* Bit 5:  Read overrun */
+#define SPI_TSR_WCOL         (1 << 6)  /* Bit 6:  Write collision */
+#define SPI_TSR_SPIF         (1 << 7)  /* Bit 7:  SPI transfer complete */
+                                       /* Bits 8-31: Reserved */
+/* SPI Interrupt Register */
+
+#define SPI_INT_SPIF         (1 << 0)  /* SPI interrupt */
+                                       /* Bits 1-31: Reserved */
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_SPI_H */
diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_spifi.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_spifi.h
new file mode 100644
index 000000000..a0bec7592
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_spifi.h
@@ -0,0 +1,275 @@
+/****************************************************************************
+ *  arch/arm/src/lpc43/chip/lpc43_spifi.h
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************
+ *
+ * NOTE:  The SPIFI ROM interface is not defined in the LPC43xx user manual.
+ * Some information in this file drivers from the NXP header file
+ * spifi_rom_api.h.  I do not believe that any copyright restrictions apply.
+ * But just to be certain:
+ *
+ *   Copyright(C) 2011, NXP Semiconductor
+ *   All rights reserved.
+ *
+ * Software that is described herein is for illustrative purposes only which
+ * provides customers with programming information regarding the products.
+ * This software is supplied "AS IS" without any warranties. NXP
+ * Semiconductors assumes no responsibility or liability for the use of the
+ * software, conveys no license or title under any patent, copyright, or
+ * mask work right to the product. NXP Semiconductors reserves the right to
+ * make changes in the software without notification. NXP Semiconductors
+ * also make no representation or warranty that such application will be
+ * suitable for the specified use without further testing or modification.
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' relevant
+ * copyright in the software, without fee, provided that it is used in
+ * conjunction with NXP Semiconductors microcontrollers.  This copyright,
+ * permission, and disclaimer notice must appear in all copies of this code.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_SPIFI_H
+#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_SPIFI_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* The largest protection block of any serial flash that the ROM driver
+ * can handle
+ */
+
+#define SPIFI_LONGEST_PROTBLOCK 68
+
+/* Protection flag bit definitions */
+
+#define SPIFI_RWPROT            (1 << 0)
+
+/* Instruction classes for wait_busy */
+
+#define SPIFI_STAT_INST         0
+#define SPIFI_BLOCK_ERASE       1
+#define SPIFI_PROG_INST         2
+#define SPIFI_CHIP_ERASE        3
+
+/* Bit definitions in options operands (MODE3, RCVCLK, and FULLCLK 
+ * have the same relationship as in the Control register)
+ */
+
+#define S_MODE3                (1 << 0)
+#define S_MODE0                (0)
+#define S_MINIMAL              (1 << 1)
+#define S_MAXIMAL              (0)
+#define S_FORCE_ERASE          (1 << 2)
+#define S_ERASE_NOT_REQD       (1 << 3)
+#define S_CALLER_ERASE         (1 << 3)
+#define S_ERASE_AS_REQD        (0)
+#define S_VERIFY_PROG          (1 << 4)
+#define S_VERIFY_ERASE         (1 << 5)
+#define S_NO_VERIFY            (0)
+#define S_FULLCLK              (1 << 6)
+#define S_HALFCLK              (0)
+#define S_RCVCLK               (1 << 7)
+#define S_INTCLK               (0)
+#define S_DUAL                 (1 << 8)
+#define S_CALLER_PROT          (1 << 9)
+#define S_DRIVER_PROT          (0)
+
+/* The length of a standard program command is 256 on all devices */
+
+#define PROG_SIZE 256
+
+/* SPI ROM driver table pointer */
+
+#define SPIFI_ROM_PTR LPC43_ROM_DRIVER_TABLE6 
+#define pSPIFI *((struct spifi_driver_s **)SPIFI_ROM_PTR)
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/* Protection/sector descriptors */
+
+struct spfi_desc_s
+{
+  uint32_t base;
+  uint8_t  flags;
+  int8_t   log2;
+  uint16_t rept;
+};
+
+/* The SPFI device state structure, passed to all ROM driver methods. */
+
+struct spifi_dev_s
+{
+  uint32_t base;
+  uint32_t regbase;
+  uint32_t devsize;
+  uint32_t memsize;
+
+  uint8_t  mfger;
+  uint8_t  devtype;
+  uint8_t  devid;
+  uint8_t  busy;
+
+  union
+  {
+    uint16_t h;
+    uint8_t  b[2];
+  } stat;
+  uint16_t reserved;
+
+  uint16_t setprot;
+  uint16_t writeprot;
+
+  uint32_t memcmd;
+  uint32_t progcmd;
+
+  uint16_t sectors;
+  uint16_t protbytes;
+
+  uint32_t opts;
+  uint32_t errcheck;
+
+  uint8_t eraseshifts[4];
+  uint8_t eraseops[4];
+
+  struct spfi_desc_s *protents;
+  char    prot[SPIFI_LONGEST_PROTBLOCK];
+};
+
+/* Operands of program and erase ROM driver methods */
+
+struct spifi_operands_s
+{
+  uint8_t *dest;
+  uint32_t length;
+  uint8_t *scratch;
+  int32_t  protect;
+  uint32_t options;
+};
+
+/* Interface to SPIFI ROM driver */
+
+#ifndef CONFIG_SPIFI_LIBRARY
+struct spifi_driver_s
+{
+  int32_t  (*spifi_init)(struct spifi_dev_s *dev, uint32_t cshigh,
+               uint32_t options, uint32_t mhz);
+  int32_t  (*spifi_program)(struct spifi_dev_s *dev, const uint8_t *source,
+               struct spifi_operands_s *opers);
+  int32_t  (*spifi_erase)(struct spifi_dev_s *dev,
+               struct spifi_operands_s *opers);
+
+  /* Mode switching */
+
+  void     (*cancel_mem_mode)(struct spifi_dev_s *dev);
+  void     (*set_mem_mode)(struct spifi_dev_s *dev);
+
+  /* Mid level functions */
+
+  int32_t  (*checkAd)(struct spifi_dev_s *dev,
+               struct spifi_operands_s *opers);
+  int32_t  (*setProt)(struct spifi_dev_s *dev,
+               struct spifi_operands_s *opers, uint8_t *change, uint8_t *saveprot);
+  int32_t  (*check_block) (struct spifi_dev_s *dev, uint8_t *source,
+               struct spifi_operands_s *opers, uint32_t check_program);
+  int32_t  (*send_erase_cmd)(struct spifi_dev_s *dev, uint8_t op,
+               uint32_t addr);
+  uint32_t (*ck_erase) (struct spifi_dev_s *dev, uint32_t *addr,
+               uint32_t length);
+  int32_t  (*prog_block)(struct spifi_dev_s *dev, uint8_t *source,
+               struct spifi_operands_s *opers, uint32_t *left_in_page);
+  uint32_t (*ck_prog)(struct spifi_dev_s *dev, uint8_t *source, uint8_t *dest,
+               uint32_t length);
+
+  /* Low level functions */
+
+  void     (*setsize) (struct spifi_dev_s *dev, int32_t value);
+  int32_t  (*setdev)(struct spifi_dev_s *dev, uint32_t opts,
+               uint32_t mem_cmd, uint32_t prog_cmd);
+  uint32_t (*cmd)(uint8_t op, uint8_t addrlen, uint8_t intLen, uint16_t len);
+  uint32_t (*readad)(struct spifi_dev_s *dev, uint32_t cmd, uint32_t addr);
+  void     (*send04)(struct spifi_dev_s *dev, uint8_t op, uint8_t len,
+               uint32_t value);
+  void     (*wren_sendad)(struct spifi_dev_s *dev, uint32_t cmd,
+               uint32_t addr, uint32_t value);
+  int32_t  (*write_stat)(struct spifi_dev_s *dev, uint8_t len,
+               uint16_t value);
+  int32_t  (*wait_busy)(struct spifi_dev_s *dev, uint8_t prog_or_erase);
+};
+#endif
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C" {
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+EXTERN int32_t spifi_init(struct spifi_dev_s *dev, uint32_t cshigh,
+                   uint32_t options, uint32_t mhz);
+EXTERN int32_t spifi_program(struct spifi_dev_s *dev, const uint8_t *source,
+                   struct spifi_operands_s *opers);
+EXTERN int32_t spifi_erase(struct spifi_dev_s *dev,
+                   struct spifi_operands_s *opers);
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_SPIFI_H */
+
diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_ssp.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_ssp.h
new file mode 100644
index 000000000..2bf934097
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_ssp.h
@@ -0,0 +1,171 @@
+/************************************************************************************
+ * arch/arm/src/lpc43xx/lpc43_ssp.h
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_SSP_H
+#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_SSP_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+/* 8 frame FIFOs for both transmit and receive */
+
+#define LPC43_SSP_FIFOSZ        8
+
+/* Register offsets *****************************************************************/
+
+#define LPC43_SSP_CR0_OFFSET    0x0000 /* Control Register 0 */
+#define LPC43_SSP_CR1_OFFSET    0x0004 /* Control Register 1 */
+#define LPC43_SSP_DR_OFFSET     0x0008 /* Data Register */
+#define LPC43_SSP_SR_OFFSET     0x000c /* Status Register */
+#define LPC43_SSP_CPSR_OFFSET   0x0010 /* Clock Prescale Register */
+#define LPC43_SSP_IMSC_OFFSET   0x0014 /* Interrupt Mask Set and Clear Register */
+#define LPC43_SSP_RIS_OFFSET    0x0018 /* Raw Interrupt Status Register */
+#define LPC43_SSP_MIS_OFFSET    0x001c /* Masked Interrupt Status Register */
+#define LPC43_SSP_ICR_OFFSET    0x0020 /* Interrupt Clear Register */
+#define LPC43_SSP_DMACR_OFFSET  0x0024 /* DMA Control Register */
+
+/* Register addresses ***************************************************************/
+
+#define LPC43_SSP0_CR0          (LPC43_SSP0_BASE+LPC43_SSP_CR0_OFFSET)
+#define LPC43_SSP0_CR1          (LPC43_SSP0_BASE+LPC43_SSP_CR1_OFFSET)
+#define LPC43_SSP0_DR           (LPC43_SSP0_BASE+LPC43_SSP_DR_OFFSET)
+#define LPC43_SSP0_SR           (LPC43_SSP0_BASE+LPC43_SSP_SR_OFFSET)
+#define LPC43_SSP0_CPSR         (LPC43_SSP0_BASE+LPC43_SSP_CPSR_OFFSET)
+#define LPC43_SSP0_IMSC         (LPC43_SSP0_BASE+LPC43_SSP_IMSC_OFFSET)
+#define LPC43_SSP0_RIS          (LPC43_SSP0_BASE+LPC43_SSP_RIS_OFFSET)
+#define LPC43_SSP0_MIS          (LPC43_SSP0_BASE+LPC43_SSP_MIS_OFFSET)
+#define LPC43_SSP0_ICR          (LPC43_SSP0_BASE+LPC43_SSP_ICR_OFFSET)
+#define LPC43_SSP0_DMACR        (LPC43_SSP0_BASE+LPC43_SSP_DMACR_OFFSET)
+
+#define LPC43_SSP1_CR0          (LPC43_SSP1_BASE+LPC43_SSP_CR0_OFFSET)
+#define LPC43_SSP1_CR1          (LPC43_SSP1_BASE+LPC43_SSP_CR1_OFFSET)
+#define LPC43_SSP1_DR           (LPC43_SSP1_BASE+LPC43_SSP_DR_OFFSET)
+#define LPC43_SSP1_SR           (LPC43_SSP1_BASE+LPC43_SSP_SR_OFFSET)
+#define LPC43_SSP1_CPSR         (LPC43_SSP1_BASE+LPC43_SSP_CPSR_OFFSET)
+#define LPC43_SSP1_IMSC         (LPC43_SSP1_BASE+LPC43_SSP_IMSC_OFFSET)
+#define LPC43_SSP1_RIS          (LPC43_SSP1_BASE+LPC43_SSP_RIS_OFFSET)
+#define LPC43_SSP1_MIS          (LPC43_SSP1_BASE+LPC43_SSP_MIS_OFFSET)
+#define LPC43_SSP1_ICR          (LPC43_SSP1_BASE+LPC43_SSP_ICR_OFFSET)
+#define LPC43_SSP1_DMACR        (LPC43_SSP1_BASE+LPC43_SSP_DMACR_OFFSET)
+
+/* Register bit definitions *********************************************************/
+/* Control Register 0 */
+
+#define SSP_CR0_DSS_SHIFT       (0)       /* Bits 0-3: DSS Data Size Select */
+#define SSP_CR0_DSS_MASK        (15 << SSP_CR0_DSS_SHIFT)
+#  define SSP_CR0_DSS_4BIT      (3 << SSP_CR0_DSS_SHIFT)
+#  define SSP_CR0_DSS_5BIT      (4 << SSP_CR0_DSS_SHIFT)
+#  define SSP_CR0_DSS_6BIT      (5 << SSP_CR0_DSS_SHIFT)
+#  define SSP_CR0_DSS_7BIT      (6 << SSP_CR0_DSS_SHIFT)
+#  define SSP_CR0_DSS_8BIT      (7 << SSP_CR0_DSS_SHIFT)
+#  define SSP_CR0_DSS_9BIT      (8 << SSP_CR0_DSS_SHIFT)
+#  define SSP_CR0_DSS_10BIT     (9 << SSP_CR0_DSS_SHIFT)
+#  define SSP_CR0_DSS_11BIT     (10 << SSP_CR0_DSS_SHIFT)
+#  define SSP_CR0_DSS_12BIT     (11 << SSP_CR0_DSS_SHIFT)
+#  define SSP_CR0_DSS_13BIT     (12 << SSP_CR0_DSS_SHIFT)
+#  define SSP_CR0_DSS_14BIT     (13 << SSP_CR0_DSS_SHIFT)
+#  define SSP_CR0_DSS_15BIT     (14 << SSP_CR0_DSS_SHIFT)
+#  define SSP_CR0_DSS_16BIT     (15 << SSP_CR0_DSS_SHIFT)
+#define SSP_CR0_FRF_SHIFT       (4)       /* Bits 4-5: FRF Frame Format */
+#define SSP_CR0_FRF_MASK        (3 << SSP_CR0_FRF_SHIFT)
+#  define SSP_CR0_FRF_SPI       (0 << SSP_CR0_FRF_SHIFT)
+#  define SSP_CR0_FRF_TI        (1 << SSP_CR0_FRF_SHIFT)
+#  define SSP_CR0_FRF_UWIRE     (2 << SSP_CR0_FRF_SHIFT)
+#define SSP_CR0_CPOL            (1 << 6)  /* Bit 6:  Clock Out Polarity */
+#define SSP_CR0_CPHA            (1 << 7)  /* Bit 7:  Clock Out Phase */
+#define SSP_CR0_SCR_SHIFT       (8)       /* Bits 8-15: Serial Clock Rate */
+#define SSP_CR0_SCR_MASK        (0xff << SSP_CR0_SCR_SHIFT)
+                                          /* Bits 8-31: Reserved */
+/* Control Register 1 */
+
+#define SSP_CR1_LBM             (1 << 0)  /* Bit 0:  Loop Back Mode */
+#define SSP_CR1_SSE             (1 << 1)  /* Bit 1:  SSP Enable */
+#define SSP_CR1_MS              (1 << 2)  /* Bit 2:  Master/Slave Mode */
+#define SSP_CR1_SOD             (1 << 3)  /* Bit 3:  Slave Output Disable */
+                                          /* Bits 4-31: Reserved */
+/* Data Register */
+
+#define SSP_DR_MASK             (0xffff)  /* Bits 0-15: Data */
+                                          /* Bits 16-31: Reserved */
+/* Status Register */
+
+#define SSP_SR_TFE              (1 << 0)  /* Bit 0:  Transmit FIFO Empty */
+#define SSP_SR_TNF              (1 << 1)  /* Bit 1:  Transmit FIFO Not Full */
+#define SSP_SR_RNE              (1 << 2)  /* Bit 2:  Receive FIFO Not Empty */
+#define SSP_SR_RFF              (1 << 3)  /* Bit 3:  Receive FIFO Full */
+#define SSP_SR_BSY              (1 << 4)  /* Bit 4:  Busy */
+                                          /* Bits 5-31: Reserved */
+/* Clock Prescale Register */
+
+#define SSP_CPSR_DVSR_MASK      (0xff)    /* Bits 0-7: clock = SSP_PCLK/DVSR */
+                                          /* Bits 8-31: Reserved */
+/* Common format for interrupt control registers:
+ *
+ *   Interrupt Mask Set and Clear Register (IMSC)
+ *   Raw Interrupt Status Register (RIS)
+ *   Masked Interrupt Status Register (MIS)
+ *   Interrupt Clear Register (ICR)
+ */
+
+#define SSP_INT_ROR             (1 << 0)  /* Bit 0: RX FIFO overrun */
+#define SSP_INT_RT              (1 << 1)  /* Bit 1: RX FIFO timeout */
+#define SSP_INT_RX              (1 << 2)  /* Bit 2: RX FIFO at least half full (not ICR) */
+#define SSP_INT_TX              (1 << 3 ) /* Bit 3: TX FIFO at least half empy (not ICR) */
+                                          /* Bits 4-31: Reserved */
+/* DMA Control Register */
+
+#define SSP_DMACR_RXDMAE        (1 << 0)  /* Bit 0:  Receive DMA Enable */
+#define SSP_DMACR_TXDMAE        (1 << 1)  /* Bit 1:  Transmit DMA Enable */
+                                          /* Bits 2-31: Reserved */
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_SSP_H */
diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_timer.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_timer.h
new file mode 100644
index 000000000..7627b135d
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_timer.h
@@ -0,0 +1,269 @@
+/************************************************************************************
+ * arch/arm/src/lpc43xx/lpc43_timer.h
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_TIMER_H
+#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_TIMER_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Register offsets *****************************************************************/
+
+#define LPC43_TMR_IR_OFFSET       0x0000 /* Interrupt Register */
+#define LPC43_TMR_TCR_OFFSET      0x0004 /* Timer Control Register */
+#define LPC43_TMR_TC_OFFSET       0x0008 /* Timer Counter */
+#define LPC43_TMR_PR_OFFSET       0x000c /* Prescale Register */
+#define LPC43_TMR_PC_OFFSET       0x0010 /* Prescale Counter */
+#define LPC43_TMR_MCR_OFFSET      0x0014 /* Match Control Register */
+#define LPC43_TMR_MR0_OFFSET      0x0018 /* Match Register 0 */
+#define LPC43_TMR_MR1_OFFSET      0x001c /* Match Register 1 */
+#define LPC43_TMR_MR2_OFFSET      0x0020 /* Match Register 2 */
+#define LPC43_TMR_MR3_OFFSET      0x0024 /* Match Register 3 */
+#define LPC43_TMR_CCR_OFFSET      0x0028 /* Capture Control Register */
+#define LPC43_TMR_CR0_OFFSET      0x002c /* Capture Register 0 */
+#define LPC43_TMR_CR1_OFFSET      0x0030 /* Capture Register 1 */
+#define LPC43_TMR_CR2_OFFSET      0x0034 /* Capture Register 2 */
+#define LPC43_TMR_CR3_OFFSET      0x0038 /* Capture Register 3 */
+#define LPC43_TMR_EMR_OFFSET      0x003c /* External Match Register */
+#define LPC43_TMR_CTCR_OFFSET     0x0070 /* Count Control Register */
+
+/* Register addresses ***************************************************************/
+
+#define LPC43_TMR0_IR             (LPC43_TMR0_BASE+LPC43_TMR_IR_OFFSET)
+#define LPC43_TMR0_TCR            (LPC43_TMR0_BASE+LPC43_TMR_TCR_OFFSET)
+#define LPC43_TMR0_TC             (LPC43_TMR0_BASE+LPC43_TMR_TC_OFFSET)
+#define LPC43_TMR0_PR             (LPC43_TMR0_BASE+LPC43_TMR_PR_OFFSET)
+#define LPC43_TMR0_PC             (LPC43_TMR0_BASE+LPC43_TMR_PC_OFFSET)
+#define LPC43_TMR0_MCR            (LPC43_TMR0_BASE+LPC43_TMR_MCR_OFFSET)
+#define LPC43_TMR0_MR0            (LPC43_TMR0_BASE+LPC43_TMR_MR0_OFFSET)
+#define LPC43_TMR0_MR1            (LPC43_TMR0_BASE+LPC43_TMR_MR1_OFFSET)
+#define LPC43_TMR0_MR2            (LPC43_TMR0_BASE+LPC43_TMR_MR2_OFFSET)
+#define LPC43_TMR0_MR3            (LPC43_TMR0_BASE+LPC43_TMR_MR3_OFFSET)
+#define LPC43_TMR0_CCR            (LPC43_TMR0_BASE+LPC43_TMR_CCR_OFFSET)
+#define LPC43_TMR0_CR0            (LPC43_TMR0_BASE+LPC43_TMR_CR0_OFFSET)
+#define LPC43_TMR0_CR1            (LPC43_TMR0_BASE+LPC43_TMR_CR1_OFFSET)
+#define LPC43_TMR0_CR2            (LPC43_TMR0_BASE+LPC43_TMR_CR2_OFFSET)
+#define LPC43_TMR0_CR3            (LPC43_TMR0_BASE+LPC43_TMR_CR3_OFFSET)
+#define LPC43_TMR0_EMR            (LPC43_TMR0_BASE+LPC43_TMR_EMR_OFFSET)
+#define LPC43_TMR0_CTCR           (LPC43_TMR0_BASE+LPC43_TMR_CTCR_OFFSET)
+
+#define LPC43_TMR1_IR             (LPC43_TMR1_BASE+LPC43_TMR_IR_OFFSET)
+#define LPC43_TMR1_TCR            (LPC43_TMR1_BASE+LPC43_TMR_TCR_OFFSET)
+#define LPC43_TMR1_TC             (LPC43_TMR1_BASE+LPC43_TMR_TC_OFFSET)
+#define LPC43_TMR1_PR             (LPC43_TMR1_BASE+LPC43_TMR_PR_OFFSET)
+#define LPC43_TMR1_PC             (LPC43_TMR1_BASE+LPC43_TMR_PC_OFFSET)
+#define LPC43_TMR1_MCR            (LPC43_TMR1_BASE+LPC43_TMR_MCR_OFFSET)
+#define LPC43_TMR1_MR0            (LPC43_TMR1_BASE+LPC43_TMR_MR0_OFFSET)
+#define LPC43_TMR1_MR1            (LPC43_TMR1_BASE+LPC43_TMR_MR1_OFFSET)
+#define LPC43_TMR1_MR2            (LPC43_TMR1_BASE+LPC43_TMR_MR2_OFFSET)
+#define LPC43_TMR1_MR3            (LPC43_TMR1_BASE+LPC43_TMR_MR3_OFFSET)
+#define LPC43_TMR1_CCR            (LPC43_TMR1_BASE+LPC43_TMR_CCR_OFFSET)
+#define LPC43_TMR1_CR0            (LPC43_TMR1_BASE+LPC43_TMR_CR0_OFFSET)
+#define LPC43_TMR1_CR1            (LPC43_TMR1_BASE+LPC43_TMR_CR1_OFFSET)
+#define LPC43_TMR1_CR2            (LPC43_TMR1_BASE+LPC43_TMR_CR2_OFFSET)
+#define LPC43_TMR1_CR3            (LPC43_TMR1_BASE+LPC43_TMR_CR3_OFFSET)
+#define LPC43_TMR1_EMR            (LPC43_TMR1_BASE+LPC43_TMR_EMR_OFFSET)
+#define LPC43_TMR1_CTCR           (LPC43_TMR1_BASE+LPC43_TMR_CTCR_OFFSET)
+
+#define LPC43_TMR2_IR             (LPC43_TMR2_BASE+LPC43_TMR_IR_OFFSET)
+#define LPC43_TMR2_TCR            (LPC43_TMR2_BASE+LPC43_TMR_TCR_OFFSET)
+#define LPC43_TMR2_TC             (LPC43_TMR2_BASE+LPC43_TMR_TC_OFFSET)
+#define LPC43_TMR2_PR             (LPC43_TMR2_BASE+LPC43_TMR_PR_OFFSET)
+#define LPC43_TMR2_PC             (LPC43_TMR2_BASE+LPC43_TMR_PC_OFFSET)
+#define LPC43_TMR2_MCR            (LPC43_TMR2_BASE+LPC43_TMR_MCR_OFFSET)
+#define LPC43_TMR2_MR0            (LPC43_TMR2_BASE+LPC43_TMR_MR0_OFFSET)
+#define LPC43_TMR2_MR1            (LPC43_TMR2_BASE+LPC43_TMR_MR1_OFFSET)
+#define LPC43_TMR2_MR2            (LPC43_TMR2_BASE+LPC43_TMR_MR2_OFFSET)
+#define LPC43_TMR2_MR3            (LPC43_TMR2_BASE+LPC43_TMR_MR3_OFFSET)
+#define LPC43_TMR2_CCR            (LPC43_TMR2_BASE+LPC43_TMR_CCR_OFFSET)
+#define LPC43_TMR2_CR0            (LPC43_TMR2_BASE+LPC43_TMR_CR0_OFFSET)
+#define LPC43_TMR2_CR1            (LPC43_TMR2_BASE+LPC43_TMR_CR1_OFFSET)
+#define LPC43_TMR2_CR2            (LPC43_TMR2_BASE+LPC43_TMR_CR2_OFFSET)
+#define LPC43_TMR2_CR3            (LPC43_TMR2_BASE+LPC43_TMR_CR3_OFFSET)
+#define LPC43_TMR2_EMR            (LPC43_TMR2_BASE+LPC43_TMR_EMR_OFFSET)
+#define LPC43_TMR2_CTCR           (LPC43_TMR2_BASE+LPC43_TMR_CTCR_OFFSET)
+
+#define LPC43_TMR3_IR             (LPC43_TMR3_BASE+LPC43_TMR_IR_OFFSET)
+#define LPC43_TMR3_TCR            (LPC43_TMR3_BASE+LPC43_TMR_TCR_OFFSET)
+#define LPC43_TMR3_TC             (LPC43_TMR3_BASE+LPC43_TMR_TC_OFFSET)
+#define LPC43_TMR3_PR             (LPC43_TMR3_BASE+LPC43_TMR_PR_OFFSET)
+#define LPC43_TMR3_PC             (LPC43_TMR3_BASE+LPC43_TMR_PC_OFFSET)
+#define LPC43_TMR3_MCR            (LPC43_TMR3_BASE+LPC43_TMR_MCR_OFFSET)
+#define LPC43_TMR3_MR0            (LPC43_TMR3_BASE+LPC43_TMR_MR0_OFFSET)
+#define LPC43_TMR3_MR1            (LPC43_TMR3_BASE+LPC43_TMR_MR1_OFFSET)
+#define LPC43_TMR3_MR2            (LPC43_TMR3_BASE+LPC43_TMR_MR2_OFFSET)
+#define LPC43_TMR3_MR3            (LPC43_TMR3_BASE+LPC43_TMR_MR3_OFFSET)
+#define LPC43_TMR3_CCR            (LPC43_TMR3_BASE+LPC43_TMR_CCR_OFFSET)
+#define LPC43_TMR3_CR0            (LPC43_TMR3_BASE+LPC43_TMR_CR0_OFFSET)
+#define LPC43_TMR3_CR1            (LPC43_TMR3_BASE+LPC43_TMR_CR1_OFFSET)
+#define LPC43_TMR3_CR2            (LPC43_TMR3_BASE+LPC43_TMR_CR2_OFFSET)
+#define LPC43_TMR3_CR3            (LPC43_TMR3_BASE+LPC43_TMR_CR3_OFFSET)
+#define LPC43_TMR3_EMR            (LPC43_TMR3_BASE+LPC43_TMR_EMR_OFFSET)
+#define LPC43_TMR3_CTCR           (LPC43_TMR3_BASE+LPC43_TMR_CTCR_OFFSET)
+
+/* Register bit definitions *********************************************************/
+/* Registers holding 32-bit numeric values (no bit field definitions):
+ *
+ *   Timer Counter (TC)
+ *   Prescale Register (PR)
+ *   Prescale Counter (PC)
+ *   Match Register 0 (MR0)
+ *   Match Register 1 (MR1)
+ *   Match Register 2 (MR2)
+ *   Match Register 3 (MR3)
+ *   Capture Register 0 (CR0)
+ *   Capture Register 1 (CR1)
+ *   Capture Register 2 (CR2)
+ *   Capture Register 3 (CR3)
+ */
+
+/* Interrupt Register */
+
+#define TMR_IR_MR0                (1 << 0)  /* Bit 0:  Match channel 0 interrupt */
+#define TMR_IR_MR1                (1 << 1)  /* Bit 1:  Match channel 1 interrupt */
+#define TMR_IR_MR2                (1 << 2)  /* Bit 2:  Match channel 2 interrupt */
+#define TMR_IR_MR3                (1 << 3)  /* Bit 3:  Match channel 3 interrupt */
+#define TMR_IR_CR0                (1 << 4)  /* Bit 4:  Capture channel 0 interrupt */
+#define TMR_IR_CR1                (1 << 5)  /* Bit 5:  Capture channel 1 interrupt */
+#define TMR_IR_CR2                (1 << 6)  /* Bit 6:  Capture channel 2 interrupt */
+#define TMR_IR_CR3                (1 << 7)  /* Bit 7:  Capture channel 3 interrupt */
+                                            /* Bits 8-31: Reserved */
+/* Timer Control Register */
+
+#define TMR_TCR_EN                (1 << 0)  /* Bit 0:  Counter Enable */
+#define TMR_TCR_RESET             (1 << 1)  /* Bit 1:  Counter Reset */
+                                            /* Bits 2-31: Reserved */
+/* Match Control Register */
+
+#define TMR_MCR_MR0I              (1 << 0)  /* Bit 0:  Interrupt on MR0 */
+#define TMR_MCR_MR0R              (1 << 1)  /* Bit 1:  Reset on MR0 */
+#define TMR_MCR_MR0S              (1 << 2)  /* Bit 2:  Stop on MR0 */
+#define TMR_MCR_MR1I              (1 << 3)  /* Bit 3:  Interrupt on MR1 */
+#define TMR_MCR_MR1R              (1 << 4)  /* Bit 4:  Reset on MR1 */
+#define TMR_MCR_MR1S              (1 << 5)  /* Bit 5:  Stop on MR1 */
+#define TMR_MCR_MR2I              (1 << 6)  /* Bit 6:  Interrupt on MR2 */
+#define TMR_MCR_MR2R              (1 << 7)  /* Bit 7:  Reset on MR2 */
+#define TMR_MCR_MR2S              (1 << 8)  /* Bit 8:  Stop on MR2 */
+#define TMR_MCR_MR3I              (1 << 9)  /* Bit 9:  Interrupt on MR3 */
+#define TMR_MCR_MR3R              (1 << 10) /* Bit 10: Reset on MR3 */
+#define TMR_MCR_MR3S              (1 << 11) /* Bit 11: Stop on MR3 */
+                                            /* Bits 12-31: Reserved */
+/* Capture Control Register */
+
+#define TMR_CCR_CAP0RE            (1 << 0)  /* Bit 0:  Capture on CAPn.0 rising edge */
+#define TMR_CCR_CAP0FE            (1 << 1)  /* Bit 1:  Capture on CAPn.0 falling edg3 */
+#define TMR_CCR_CAP0I             (1 << 2)  /* Bit 2:  Interrupt on CAPn.0 */
+#define TMR_CCR_CAP1RE            (1 << 3)  /* Bit 3:  Capture on CAPn.1 rising edge */
+#define TMR_CCR_CAP1FE            (1 << 4)  /* Bit 4:  Capture on CAPn.1 falling edg3 */
+#define TMR_CCR_CAP1I             (1 << 5)  /* Bit 5:  Interrupt on CAPn.1 */
+#define TMR_CCR_CAP2RE            (1 << 6)  /* Bit 6:  Capture on CAPn.2 rising edge */
+#define TMR_CCR_CAP2FE            (1 << 7)  /* Bit 7:  Capture on CAPn.2 falling edg3 */
+#define TMR_CCR_CAP2I             (1 << 8)  /* Bit 8:  Interrupt on CAPn.2 */
+#define TMR_CCR_CAP3RE            (1 << 9)  /* Bit 9:  Capture on CAPn.3 rising edge */
+#define TMR_CCR_CAP3FE            (1 << 10) /* Bit 10: Capture on CAPn.3 falling edg3 */
+#define TMR_CCR_CAP3I             (1 << 11) /* Bit 11: Interrupt on CAPn.3 */
+                                            /* Bits 12-31: Reserved */
+/* External Match Register */
+
+#define TMR_EMR_NOTHING           (0)       /* Do Nothing */
+#define TMR_EMR_CLEAR             (1)       /* Clear external match bit MATn.m */
+#define TMR_EMR_SET               (2)       /* Set external match bit MATn.m */
+#define TMR_EMR_TOGGLE            (3)       /* Toggle external match bit MATn.m */
+
+#define TMR_EMR_EM0               (1 << 0)  /* Bit 0:  External Match 0 */
+#define TMR_EMR_EM1               (1 << 1)  /* Bit 1:  External Match 1 */
+#define TMR_EMR_EM2               (1 << 2)  /* Bit 2:  External Match 2 */
+#define TMR_EMR_EM3               (1 << 3)  /* Bit 3:  External Match 3 */
+#define TMR_EMR_EMC0_SHIFT        (4)       /* Bits 4-5: External Match Control 0 */
+#define TMR_EMR_EMC0_MASK         (3 << TMR_EMR_EMC0_SHIFTy)
+#  define TMR_EMR_EMC0_NOTHING    (TMR_EMR_NOTHING << TMR_EMR_EMC0_SHIFT)
+#  define TMR_EMR_EMC0_CLEAR      (TMR_EMR_CLEAR << TMR_EMR_EMC0_SHIFT)
+#  define TMR_EMR_EMC0_SET        (TMR_EMR_SET << TMR_EMR_EMC0_SHIFT)
+#  define TMR_EMR_EMC0_TOGGLE     (TMR_EMR_TOGGLE << TMR_EMR_EMC0_SHIFT)
+#define TMR_EMR_EMC1_SHIFT        (6)       /* Bits 6-7: External Match Control 1 */
+#define TMR_EMR_EMC1_MASK         (3 << TMR_EMR_EMC1_SHIFT)
+#  define TMR_EMR_EMC1_NOTHING    (TMR_EMR_NOTHING << TMR_EMR_EMC1_SHIFT)
+#  define TMR_EMR_EMC1_CLEAR      (TMR_EMR_CLEAR << TMR_EMR_EMC1_SHIFT)
+#  define TMR_EMR_EMC1_SET        (TMR_EMR_SET << TMR_EMR_EMC1_SHIFT)
+#  define TMR_EMR_EMC1_TOGGLE     (TMR_EMR_TOGGLE << TMR_EMR_EMC1_SHIFT)
+#define TMR_EMR_EMC2_SHIFT        (8)       /* Bits 8-9: External Match Control 2 */
+#define TMR_EMR_EMC2_MASK         (3 << TMR_EMR_EMC2_SHIFT)
+#  define TMR_EMR_EMC2_NOTHING    (TMR_EMR_NOTHING << TMR_EMR_EMC2_SHIFT)
+#  define TMR_EMR_EMC2_CLEAR      (TMR_EMR_CLEAR << TMR_EMR_EMC2_SHIFT)
+#  define TMR_EMR_EMC2_SET        (TMR_EMR_SET << TMR_EMR_EMC2_SHIFT)
+#  define TMR_EMR_EMC2_TOGGLE     (TMR_EMR_TOGGLE << TMR_EMR_EMC2_SHIFT)
+#define TMR_EMR_EMC3_SHIFT        (10)      /* Bits 10-11: External Match Control 3 */
+#define TMR_EMR_EMC3_MASK         (3 << TMR_EMR_EMC3_SHIFT)
+#  define TMR_EMR_EMC3_NOTHING    (TMR_EMR_NOTHING << TMR_EMR_EMC3_SHIFT)
+#  define TMR_EMR_EMC3_CLEAR      (TMR_EMR_CLEAR << TMR_EMR_EMC3_SHIFT)
+#  define TMR_EMR_EMC3_SET        (TMR_EMR_SET << TMR_EMR_EMC3_SHIFT)
+#  define TMR_EMR_EMC3_TOGGLE     (TMR_EMR_TOGGLE << TMR_EMR_EMC3_SHIFT)
+                                            /* Bits 12-31: Reserved */
+/* Count Control Register */
+
+#define TMR_CTCR_MODE_SHIFT       (0)       /* Bits 0-1: Counter/Timer Mode */
+#define TMR_CTCR_MODE_MASK        (3 << TMR_CTCR_MODE_SHIFT)
+#  define TMR_CTCR_MODE_TIMER     (0 << TMR_CTCR_MODE_SHIFT) /* Timer ModeMode: Rising PCLK edge */
+#  define TMR_CTCR_MODE_CNTRRE    (1 << TMR_CTCR_MODE_SHIFT) /* Counter Mode, CAP rising edge */
+#  define TMR_CTCR_MODE_CNTRFE    (2 << TMR_CTCR_MODE_SHIFT) /* Counter Mode, CAP falling edge */
+#  define TMR_CTCR_MODE_CNTRBE    (3 << TMR_CTCR_MODE_SHIFT) /* Counter Mode, CAP both edges */
+#define TMR_CTCR_INSEL_SHIFT      (2)       /* Bits 2-3: Count Input Select */
+#define TMR_CTCR_INSEL_MASK       (3 << TMR_CTCR_INSEL_SHIFT)
+#  define TMR_CTCR_INSEL_CAPNp0   (0 << TMR_CTCR_INSEL_SHIFT) /* CAPn.0 for TIMERn */
+#  define TMR_CTCR_INSEL_CAPNp1   (1 << TMR_CTCR_INSEL_SHIFT) /* CAPn.1 for TIMERn */
+#  define TMR_CTCR_INSEL_CAPNp2   (2 << TMR_CTCR_INSEL_SHIFT) /* CAPn.2 for TIMERn */
+#  define TMR_CTCR_INSEL_CAPNp3   (3 << TMR_CTCR_INSEL_SHIFT) /* CAPn.3 for TIMERn */
+                                            /* Bits 4-31: Reserved */
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_TIMER_H */
diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_uart.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_uart.h
new file mode 100644
index 000000000..a0ea29718
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_uart.h
@@ -0,0 +1,397 @@
+/********************************************************************************************
+ * arch/arm/src/lpc43xx/lpc43_uart.h
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ********************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_UART_H
+#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_UART_H
+
+/********************************************************************************************
+ * Included Files
+ ********************************************************************************************/
+
+#include <nuttx/config.h>
+
+/********************************************************************************************
+ * Pre-processor Definitions
+ ********************************************************************************************/
+
+/* Register offsets *************************************************************************/
+/* Common Register Offsets */
+
+#define LPC43_UART_RBR_OFFSET        0x0000 /* (DLAB =0) Receiver Buffer Register */
+#define LPC43_UART_THR_OFFSET        0x0000 /* (DLAB =0) Transmit Holding Register */
+#define LPC43_UART_DLL_OFFSET        0x0000 /* (DLAB =1) Divisor Latch LSB */
+#define LPC43_UART_DLM_OFFSET        0x0004 /* (DLAB =1) Divisor Latch MSB */
+#define LPC43_UART_IER_OFFSET        0x0004 /* (DLAB =0) Interrupt Enable Register */
+#define LPC43_UART_IIR_OFFSET        0x0008 /* Interrupt ID Register */
+#define LPC43_UART_FCR_OFFSET        0x0008 /* FIFO Control Register */
+#define LPC43_UART_LCR_OFFSET        0x000c /* Line Control Register */
+#define LPC43_UART_LSR_OFFSET        0x0014 /* Line Status Register */
+#define LPC43_UART_SCR_OFFSET        0x001c /* Scratch Pad Register */
+#define LPC43_UART_ACR_OFFSET        0x0020 /* Auto-baud Control Register */
+#define LPC43_UART_FDR_OFFSET        0x0028 /* Fractional Divider Register */
+
+#define LPC43_UART_RS485CTRL_OFFSET  0x004c /* RS-485/EIA-485 Control */
+#define LPC43_UART_ADRMATCH_OFFSET   0x0050 /* RS-485/EIA-485 address match */
+#define LPC43_UART_RS485DLY_OFFSET   0x0054 /* RS-485/EIA-485 direction control delay */
+
+/* Registers available only on UART1 */
+
+#define LPC43_UART_MCR_OFFSET        0x0010 /* Modem Control Register */
+#define LPC43_UART_MSR_OFFSET        0x0018 /* Modem Status Register */
+#define LPC43_UART_TER_OFFSET        0x0030 /* Transmit Enable Register */
+
+/* Registers available only on USART0,2,3 */
+
+#define LPC43_USART_ICR_OFFSET       0x0024 /* IrDA Control Register */
+#define LPC43_USART_OSR_OFFSET       0x002c /* Oversampling Register */
+#define LPC43_USART_HDEN_OFFSET      0x0040 /* Half-duplex enable Register */
+#define LPC43_USART_SCICTRL_OFFSET   0x0048 /* Smart card interface control register */
+#define LPC43_USART_SYNCCTRL_OFFSET  0x0058 /* Synchronous mode control register */
+#define LPC43_USART_TER_OFFSET       0x005c /* Transmit Enable Register */
+
+/* Register addresses ***********************************************************************/
+
+#define LPC43_USART0_RBR             (LPC43_USART0_BASE+LPC43_UART_RBR_OFFSET)
+#define LPC43_USART0_THR             (LPC43_USART0_BASE+LPC43_UART_THR_OFFSET)
+#define LPC43_USART0_DLL             (LPC43_USART0_BASE+LPC43_UART_DLL_OFFSET)
+#define LPC43_USART0_DLM             (LPC43_USART0_BASE+LPC43_UART_DLM_OFFSET)
+#define LPC43_USART0_IER             (LPC43_USART0_BASE+LPC43_UART_IER_OFFSET)
+#define LPC43_USART0_IIR             (LPC43_USART0_BASE+LPC43_UART_IIR_OFFSET)
+#define LPC43_USART0_FCR             (LPC43_USART0_BASE+LPC43_UART_FCR_OFFSET)
+#define LPC43_USART0_LCR             (LPC43_USART0_BASE+LPC43_UART_LCR_OFFSET)
+#define LPC43_USART0_LSR             (LPC43_USART0_BASE+LPC43_UART_LSR_OFFSET)
+#define LPC43_USART0_SCR             (LPC43_USART0_BASE+LPC43_UART_SCR_OFFSET)
+#define LPC43_USART0_ACR             (LPC43_USART0_BASE+LPC43_UART_ACR_OFFSET)
+#define LPC43_USART0_ICR             (LPC43_USART0_BASE+LPC43_USART_ICR_OFFSET)
+#define LPC43_USART0_FDR             (LPC43_USART0_BASE+LPC43_UART_FDR_OFFSET)
+#define LPC43_USART0_OSR             (LPC43_USART0_BASE+LPC43_USART_OSR_OFFSET)
+#define LPC43_USART0_HDEM            (LPC43_USART0_BASE+LPC43_USART_HDEN_OFFSET)
+#define LPC43_USART0_SCICTRL         (LPC43_USART0_BASE+LPC43_USART_SCICTRL_OFFSET)
+#define LPC43_USART0_RS485CTRL       (LPC43_USART0_BASE+LPC43_UART_RS485CTRL_OFFSET)
+#define LPC43_USART0_ADRMATCH        (LPC43_USART0_BASE+LPC43_UART_ADRMATCH_OFFSET)
+#define LPC43_USART0_RS485DLY        (LPC43_USART0_BASE+LPC43_UART_RS485DLY_OFFSET)
+#define LPC43_USART0_SYNCCTRL        (LPC43_USART0_BASE+LPC43_USART_SYNCCTRL_OFFSET)
+#define LPC43_USART0_TER             (LPC43_USART0_BASE+LPC43_USART_TER_OFFSET)
+
+#define LPC43_UART1_RBR              (LPC43_UART1_BASE+LPC43_UART_RBR_OFFSET)
+#define LPC43_UART1_THR              (LPC43_UART1_BASE+LPC43_UART_THR_OFFSET)
+#define LPC43_UART1_DLL              (LPC43_UART1_BASE+LPC43_UART_DLL_OFFSET)
+#define LPC43_UART1_DLM              (LPC43_UART1_BASE+LPC43_UART_DLM_OFFSET)
+#define LPC43_UART1_IER              (LPC43_UART1_BASE+LPC43_UART_IER_OFFSET)
+#define LPC43_UART1_IIR              (LPC43_UART1_BASE+LPC43_UART_IIR_OFFSET)
+#define LPC43_UART1_FCR              (LPC43_UART1_BASE+LPC43_UART_FCR_OFFSET)
+#define LPC43_UART1_LCR              (LPC43_UART1_BASE+LPC43_UART_LCR_OFFSET)
+#define LPC43_UART1_MCR              (LPC43_UART1_BASE+LPC43_UART_MCR_OFFSET)
+#define LPC43_UART1_LSR              (LPC43_UART1_BASE+LPC43_UART_LSR_OFFSET)
+#define LPC43_UART1_MSR              (LPC43_UART1_BASE+LPC43_UART_MSR_OFFSET)
+#define LPC43_UART1_SCR              (LPC43_UART1_BASE+LPC43_UART_SCR_OFFSET)
+#define LPC43_UART1_ACR              (LPC43_UART1_BASE+LPC43_UART_ACR_OFFSET)
+#define LPC43_UART1_FDR              (LPC43_UART1_BASE+LPC43_UART_FDR_OFFSET)
+#define LPC43_UART1_TER              (LPC43_UART1_BASE+LPC43_UART_TER_OFFSET)
+#define LPC43_UART1_RS485CTRL        (LPC43_UART1_BASE+LPC43_UART_RS485CTRL_OFFSET)
+#define LPC43_UART1_ADRMATCH         (LPC43_UART1_BASE+LPC43_UART_ADRMATCH_OFFSET)
+#define LPC43_UART1_RS485DLY         (LPC43_UART1_BASE+LPC43_UART_RS485DLY_OFFSET)
+
+#define LPC43_USART1_RBR             (LPC43_USART1_BASE+LPC43_UART_RBR_OFFSET)
+#define LPC43_USART1_THR             (LPC43_USART1_BASE+LPC43_UART_THR_OFFSET)
+#define LPC43_USART1_DLL             (LPC43_USART1_BASE+LPC43_UART_DLL_OFFSET)
+#define LPC43_USART1_DLM             (LPC43_USART1_BASE+LPC43_UART_DLM_OFFSET)
+#define LPC43_USART1_IER             (LPC43_USART1_BASE+LPC43_UART_IER_OFFSET)
+#define LPC43_USART1_IIR             (LPC43_USART1_BASE+LPC43_UART_IIR_OFFSET)
+#define LPC43_USART1_FCR             (LPC43_USART1_BASE+LPC43_UART_FCR_OFFSET)
+#define LPC43_USART1_LCR             (LPC43_USART1_BASE+LPC43_UART_LCR_OFFSET)
+#define LPC43_USART1_LSR             (LPC43_USART1_BASE+LPC43_UART_LSR_OFFSET)
+#define LPC43_USART1_SCR             (LPC43_USART1_BASE+LPC43_UART_SCR_OFFSET)
+#define LPC43_USART1_ACR             (LPC43_USART1_BASE+LPC43_UART_ACR_OFFSET)
+#define LPC43_USART1_ICR             (LPC43_USART1_BASE+LPC43_USART_ICR_OFFSET)
+#define LPC43_USART1_FDR             (LPC43_USART1_BASE+LPC43_UART_FDR_OFFSET)
+#define LPC43_USART1_OSR             (LPC43_USART1_BASE+LPC43_USART_OSR_OFFSET)
+#define LPC43_USART1_HDEM            (LPC43_USART1_BASE+LPC43_USART_HDEN_OFFSET)
+#define LPC43_USART1_SCICTRL         (LPC43_USART1_BASE+LPC43_USART_SCICTRL_OFFSET)
+#define LPC43_USART1_RS485CTRL       (LPC43_USART1_BASE+LPC43_UART_RS485CTRL_OFFSET)
+#define LPC43_USART1_ADRMATCH        (LPC43_USART1_BASE+LPC43_UART_ADRMATCH_OFFSET)
+#define LPC43_USART1_RS485DLY        (LPC43_USART1_BASE+LPC43_UART_RS485DLY_OFFSET)
+#define LPC43_USART1_SYNCCTRL        (LPC43_USART1_BASE+LPC43_USART_SYNCCTRL_OFFSET)
+#define LPC43_USART1_TER             (LPC43_USART1_BASE+LPC43_USART_TER_OFFSET)
+
+#define LPC43_USART2_RBR             (LPC43_USART2_BASE+LPC43_UART_RBR_OFFSET)
+#define LPC43_USART2_THR             (LPC43_USART2_BASE+LPC43_UART_THR_OFFSET)
+#define LPC43_USART2_DLL             (LPC43_USART2_BASE+LPC43_UART_DLL_OFFSET)
+#define LPC43_USART2_DLM             (LPC43_USART2_BASE+LPC43_UART_DLM_OFFSET)
+#define LPC43_USART2_IER             (LPC43_USART2_BASE+LPC43_UART_IER_OFFSET)
+#define LPC43_USART2_IIR             (LPC43_USART2_BASE+LPC43_UART_IIR_OFFSET)
+#define LPC43_USART2_FCR             (LPC43_USART2_BASE+LPC43_UART_FCR_OFFSET)
+#define LPC43_USART2_LCR             (LPC43_USART2_BASE+LPC43_UART_LCR_OFFSET)
+#define LPC43_USART2_LSR             (LPC43_USART2_BASE+LPC43_UART_LSR_OFFSET)
+#define LPC43_USART2_SCR             (LPC43_USART2_BASE+LPC43_UART_SCR_OFFSET)
+#define LPC43_USART2_ACR             (LPC43_USART2_BASE+LPC43_UART_ACR_OFFSET)
+#define LPC43_USART2_ICR             (LPC43_USART2_BASE+LPC43_USART_ICR_OFFSET)
+#define LPC43_USART2_FDR             (LPC43_USART2_BASE+LPC43_UART_FDR_OFFSET)
+#define LPC43_USART2_OSR             (LPC43_USART2_BASE+LPC43_USART_OSR_OFFSET)
+#define LPC43_USART2_HDEM            (LPC43_USART2_BASE+LPC43_USART_HDEN_OFFSET)
+#define LPC43_USART2_SCICTRL         (LPC43_USART2_BASE+LPC43_USART_SCICTRL_OFFSET)
+#define LPC43_USART2_RS485CTRL       (LPC43_USART2_BASE+LPC43_UART_RS485CTRL_OFFSET)
+#define LPC43_USART2_ADRMATCH        (LPC43_USART2_BASE+LPC43_UART_ADRMATCH_OFFSET)
+#define LPC43_USART2_RS485DLY        (LPC43_USART2_BASE+LPC43_UART_RS485DLY_OFFSET)
+#define LPC43_USART2_SYNCCTRL        (LPC43_USART2_BASE+LPC43_USART_SYNCCTRL_OFFSET)
+#define LPC43_USART2_TER             (LPC43_USART2_BASE+LPC43_USART_TER_OFFSET)
+
+/* Register bit definitions *****************************************************************/
+
+/* RBR (DLAB =0) Receiver Buffer Register */
+
+#define UART_RBR_MASK                (0xff)    /* Bits 0-7: Oldest received byte in RX FIFO */
+                                               /* Bits 8-31: Reserved */
+
+/* THR (DLAB =0) Transmit Holding Register */
+
+#define UART_THR_MASK                (0xff)    /* Bits 0-7: Adds byte to TX FIFO */
+                                               /* Bits 8-31: Reserved */
+
+/* DLL (DLAB =1) Divisor Latch LSB */
+
+#define UART_DLL_MASK                (0xff)    /* Bits 0-7: DLL */
+                                               /* Bits 8-31: Reserved */
+
+/* DLM (DLAB =1) Divisor Latch MSB */
+
+#define UART_DLM_MASK                (0xff)    /* Bits 0-7: DLM */
+                                               /* Bits 8-31: Reserved */
+
+/* IER (DLAB =0) Interrupt Enable Register */
+
+#define UART_IER_RBRIE               (1 << 0)  /* Bit 0: RBR Interrupt Enable */
+#define UART_IER_THREIE              (1 << 1)  /* Bit 1: THRE Interrupt Enable */
+#define UART_IER_RXIE                (1 << 2)  /* Bit 2: RX Line Status Interrupt Enable */
+#define UART_IER_MSIE                (1 << 3)  /* Bit 3: Modem Status Interrupt Enable (UART only) */
+                                               /* Bits 4-6: Reserved */
+#define UART_IER_CTSIE               (1 << 7)  /* Bit 7: CTS transition interrupt (UART only) */
+#define UART_IER_ABEOIE              (1 << 8)  /* Bit 8: Enables the end of auto-baud interrupt */
+#define UART_IER_ABTOIE              (1 << 9)  /* Bit 9: Enables the auto-baud time-out interrupt */
+                                               /* Bits 10-31: Reserved */
+#define UART_IER_ALLIE               (0x038f)
+#define USART_IER_ALLIE              (0x0307)
+
+/* IIR Interrupt ID Register */
+
+#define UART_IIR_INTSTATUS           (1 << 0)  /* Bit 0:  Interrupt status (active low) */
+#define UART_IIR_INTID_SHIFT         (1)       /* Bits 1-3: Interrupt identification */
+#define UART_IIR_INTID_MASK          (7 << UART_IIR_INTID_SHIFT)
+#  define UART_IIR_INTID_MSI         (0 << UART_IIR_INTID_SHIFT) /* Modem Status (UART only) */
+#  define UART_IIR_INTID_THRE        (1 << UART_IIR_INTID_SHIFT) /* THRE Interrupt */
+#  define UART_IIR_INTID_RDA         (2 << UART_IIR_INTID_SHIFT) /* 2a - Receive Data Available (RDA) */
+#  define UART_IIR_INTID_RLS         (3 << UART_IIR_INTID_SHIFT) /* 1 - Receive Line Status (RLS) */
+#  define UART_IIR_INTID_CTI         (6 << UART_IIR_INTID_SHIFT) /* 2b - Character Time-out Indicator (CTI) */
+                                               /* Bits 4-5: Reserved */
+#define UART_IIR_FIFOEN_SHIFT        (6)       /* Bits 6-7: Copies of FCR[0] */
+#define UART_IIR_FIFOEN_MASK         (3 << UART_IIR_FIFOEN_SHIFT)
+#define UART_IIR_ABEOINT             (1 << 8)  /* Bit 8:  End of auto-baud interrupt */
+#define UART_IIR_ABTOINT             (1 << 9)  /* Bit 9:  Auto-baud time-out interrupt */
+                                               /* Bits 10-31: Reserved */
+/* FCR FIFO Control Register */
+
+#define UART_FCR_FIFOEN              (1 << 0)  /* Bit 0:  Enable FIFOs */
+#define UART_FCR_RXRST               (1 << 1)  /* Bit 1:  RX FIFO Reset */
+#define UART_FCR_TXRST               (1 << 2)  /* Bit 2:  TX FIFO Reset */
+#define UART_FCR_DMAMODE             (1 << 3)  /* Bit 3:  DMA Mode Select */
+                                               /* Bits 4-5: Reserved */
+#define UART_FCR_RXTRIGGER_SHIFT     (6)       /* Bits 6-7: RX Trigger Level */
+#define UART_FCR_RXTRIGGER_MASK      (3 << UART_FCR_RXTRIGGER_SHIFT)
+#  define UART_FCR_RXTRIGGER_0       (0 << UART_FCR_RXTRIGGER_SHIFT) /* Trigger level 0 (1 char) */
+#  define UART_FCR_RXTRIGGER_4       (1 << UART_FCR_RXTRIGGER_SHIFT) /* Trigger level 1 (4 chars) */
+#  define UART_FCR_RXTRIGGER_8       (2 << UART_FCR_RXTRIGGER_SHIFT) /* Trigger level 2 (8 chars) */
+#  define UART_FCR_RXTRIGGER_14      (3 << UART_FCR_RXTRIGGER_SHIFT) /* Trigger level 3 (14 chars) */
+                                               /* Bits 8-31: Reserved */
+/* LCR Line Control Register */
+
+#define UART_LCR_WLS_SHIFT           (0)       /* Bit 0-1: Word Length Select */
+#define UART_LCR_WLS_MASK            (3 << UART_LCR_WLS_SHIFT)
+#  define UART_LCR_WLS_5BIT          (0 << UART_LCR_WLS_SHIFT)
+#  define UART_LCR_WLS_6BIT          (1 << UART_LCR_WLS_SHIFT)
+#  define UART_LCR_WLS_7BIT          (2 << UART_LCR_WLS_SHIFT)
+#  define UART_LCR_WLS_8BIT          (3 << UART_LCR_WLS_SHIFT)
+#define UART_LCR_STOP                (1 << 2)  /* Bit 2:  Stop Bit Select */
+#define UART_LCR_PE                  (1 << 3)  /* Bit 3:  Parity Enable */
+#define UART_LCR_PS_SHIFT            (4)       /* Bits 4-5: Parity Select */
+#define UART_LCR_PS_MASK             (3 << UART_LCR_PS_SHIFT)
+#  define UART_LCR_PS_ODD            (0 << UART_LCR_PS_SHIFT) /* Odd parity */
+#  define UART_LCR_PS_EVEN           (1 << UART_LCR_PS_SHIFT) /* Even Parity */
+#  define UART_LCR_PS_STICKY1        (2 << UART_LCR_PS_SHIFT) /* Forced "1" stick parity */
+#  define UART_LCR_PS_STICKY0        (3 << UART_LCR_PS_SHIFT) /* Forced "0" stick parity */
+#define UART_LCR_BRK                 (1 << 6)  /* Bit 6: Break Control */
+#define UART_LCR_DLAB                (1 << 7)  /* Bit 7: Divisor Latch Access Bit (DLAB) */
+                                               /* Bits 8-31: Reserved */
+/* MCR Modem Control Register (UART only) */
+
+#define UART_MCR_DTR                 (1 << 0)  /* Bit 0:  DTR Control Source for DTR output */
+#define UART_MCR_RTS                 (1 << 1)  /* Bit 1:  Control Source for  RTS output */
+                                               /* Bits 2-3: Reserved */
+#define UART_MCR_LPBK                (1 << 4)  /* Bit 4:  Loopback Mode Select */
+                                               /* Bit 5: Reserved */
+#define UART_MCR_RTSEN               (1 << 6)  /* Bit 6:  Enable auto-RTS flow control */
+#define UART_MCR_CTSEN               (1 << 7)  /* Bit 7:  Enable auto-CTS flow control */
+                                               /* Bits 8-31: Reserved */
+/* LSR Line Status Register */
+
+#define UART_LSR_RDR                 (1 << 0)  /* Bit 0:  Receiver Data Ready */
+#define UART_LSR_OE                  (1 << 1)  /* Bit 1:  Overrun Error */
+#define UART_LSR_PE                  (1 << 2)  /* Bit 2:  Parity Error */
+#define UART_LSR_FE                  (1 << 3)  /* Bit 3:  Framing Error */
+#define UART_LSR_BI                  (1 << 4)  /* Bit 4:  Break Interrupt */
+#define UART_LSR_THRE                (1 << 5)  /* Bit 5:  Transmitter Holding Register Empty */
+#define UART_LSR_TEMT                (1 << 6)  /* Bit 6:  Transmitter Empty */
+#define UART_LSR_RXFE                (1 << 7)  /* Bit 7:  Error in RX FIFO (RXFE) */
+#define USART_LSR_RXFE               (1 << 8)  /* Bit 8:  Error in transmitted char (USART onlY) */
+                                               /* Bits 8-31: Reserved */
+/* MSR Modem Status Register (UART only) */
+
+#define UART_MSR_DCTS                (1 << 0)  /* Bit 0:  Delta CTS. CTS state change */
+#define UART_MSR_DDSR                (1 << 1)  /* Bit 1:  Delta DSR. DSR state change */
+#define UART_MSR_TERI                (1 << 2)  /* Bit 2:  Trailing Edge RI */
+#define UART_MSR_DDCD                (1 << 3)  /* Bit 3:  Delta DCD. DCD state change */
+#define UART_MSR_CTS                 (1 << 4)  /* Bit 4:  CTS State */
+#define UART_MSR_DSR                 (1 << 5)  /* Bit 5:  DSR State */
+#define UART_MSR_RI                  (1 << 6)  /* Bit 6:  Ring Indicator State */
+#define UART_MSR_DCD                 (1 << 7)  /* Bit 7:  Data Carrier Detect State */
+                                               /* Bits 8-31: Reserved */
+/* SCR Scratch Pad Register */
+
+#define UART_SCR_MASK                (0xff)    /* Bits 0-7: SCR data */
+                                               /* Bits 8-31: Reserved */
+/* ACR Auto-baud Control Register */
+
+#define UART_ACR_START               (1 << 0)  /* Bit 0:  Auto-baud start/running */
+#define UART_ACR_MODE                (1 << 1)  /* Bit 1:  Auto-baud mode select */
+#define UART_ACR_AUTORESTART         (1 << 2)  /* Bit 2:  Restart in case of time-out */
+                                               /* Bits 3-7: Reserved */
+#define UART_ACR_ABEOINTCLR          (1 << 8)  /* Bit 8:  End of auto-baud interrupt clear */
+#define UART_ACR_ABTOINTCLRT         (1 << 9)  /* Bit 9:  Auto-baud time-out interrupt clear */
+                                               /* Bits 10-31: Reserved */
+/* ICA IrDA Control Register (USART0,2,3 only) */
+
+#define UART_ICR_IRDAEN              (1 << 0)  /* Bit 0:  Enable IrDA mode */
+#define UART_ICR_IRDAINV             (1 << 1)  /* Bit 1:  Invert serial input */
+#define UART_ICR_FIXPULSEEN          (1 << 2)  /* Bit 2: Enable IrDA fixed pulse width mode */
+#define UART_ICR_PULSEDIV_SHIFT      (3)       /* Bits 3-5: Configures the pulse when FixPulseEn = 1 */
+#define UART_ICR_PULSEDIV_MASK       (7 << UART_ICR_PULSEDIV_SHIFT)
+#  define UART_ICR_PULSEDIV_2TPCLK   (0 << UART_ICR_PULSEDIV_SHIFT) /* 2 x TPCLK */
+#  define UART_ICR_PULSEDIV_4TPCLK   (1 << UART_ICR_PULSEDIV_SHIFT) /* 4 x TPCLK */
+#  define UART_ICR_PULSEDIV_8TPCLK   (2 << UART_ICR_PULSEDIV_SHIFT) /* 8 x TPCLK */
+#  define UART_ICR_PULSEDIV_16TPCLK  (3 << UART_ICR_PULSEDIV_SHIFT) /* 16 x TPCLK */
+#  define UART_ICR_PULSEDIV_32TPCLK  (4 << UART_ICR_PULSEDIV_SHIFT) /* 32 x TPCLK */
+#  define UART_ICR_PULSEDIV_64TPCLK  (5 << UART_ICR_PULSEDIV_SHIFT) /* 64 x TPCLK */
+#  define UART_ICR_PULSEDIV_128TPCLK (6 << UART_ICR_PULSEDIV_SHIFT) /* 128 x TPCLK */
+#  define UART_ICR_PULSEDIV_256TPCLK (7 << UART_ICR_PULSEDIV_SHIFT) /* 256 x TPCLK */
+                                               /* Bits 6-31: Reserved */
+/* FDR Fractional Divider Register */
+
+#define UART_FDR_DIVADDVAL_SHIFT     (0)       /* Bits 0-3: Baud-rate generation pre-scaler divisor value */
+#define UART_FDR_DIVADDVAL_MASK      (15 << UART_FDR_DIVADDVAL_SHIFT)
+#define UART_FDR_MULVAL_SHIFT        (4)       /* Bits 4-7 Baud-rate pre-scaler multiplier value */
+#define UART_FDR_MULVAL_MASK         (15 << UART_FDR_MULVAL_SHIFT)
+                                               /* Bits 8-31: Reserved */
+/* Oversampling Register (USART only) */
+                                               /* Bit 0:  Reserved */
+#define USART_OSR_OSFRAC_SHIFT       (1)       /* Bits 1-3: Fractional part of the oversampling ratio */
+#define USART_OSR_OSFRAC_MASK        (7 << USART_OSR_OSFRAC_SHIFT)
+#define USART_OSR_OSINT_SHIFT        (4)       /* Bits 4-7: Integer part of the oversampling ratio */
+#define USART_OSR_OSINT_MASK         (15 << USART_OSR_OSINT_SHIFT)
+#define USART_OSR_FDINT_SHIFT        (8)       /* Bits 8-14: Extension for Smart Card mode */
+#define USART_OSR_FDINT_MASK         (0x7f << USART_OSR_FDINT_SHIFT)
+                                               /* Bits 15-31: Reserved */
+/* TER Transmit Enable Register (UART only) */
+                                               /* Bits 0-6: Reserved */
+#define UART_TER_TXEN                (1 << 7)  /* Bit 7:  TX Enable */
+                                               /* Bits 8-31: Reserved */
+/* Half-duplex enable Register (USART only) */
+
+#define USART_HDEN_TXEN              (1 << 0)  /* Bit 0:  Half-duplex mode enable */
+                                               /* Bits 1-31: Reserved */
+/* Smart card interface control register (USART only) */
+
+#define USART_SCICTRL_SCIEN          (1 << 0)  /* Bit 0:  Smart Card Interface Enable */
+#define USART_SCICTRL_NACKDIS        (1 << 1)  /* Bit 1:  NACK response disable */
+#define USART_SCICTRL_PROTSEL        (1 << 2)  /* Bit 2:  Protocol selection */
+                                               /* Bits 3-4: Reserved */
+#define USART_SCICTRL_TXRETRY_SHIFT  (5)       /* Bits 5-7: Maximum number of retransmissions */
+#define USART_SCICTRL_TXRETRY_MASK   (7 << USART_SCICTRL_TXRETRY_SHIFT)
+#define USART_SCICTRL_GUARDTIME_SHIFT (8)      /* Bits 8-15: Extra guard time */
+#define USART_SCICTRL_GUARDTIME_MASK  (0xff << USART_SCICTRL_GUARDTIME_SHIFT)
+                                               /* Bits 16-31: Reserved */
+/* RS-485/EIA-485 Control */
+
+#define UART_RS485CTRL_NMMEN         (1 << 0)  /* Bit 0: RS-485/EIA-485 Normal Multidrop Mode (NMM) enabled */
+#define UART_RS485CTRL_RXDIS         (1 << 1)  /* Bit 1: Receiver is disabled */
+#define UART_RS485CTRL_AADEN         (1 << 2)  /* Bit 2: Auto Address Detect (AAD) is enabled */
+#define UART_RS485CTRL_SEL           (1 << 3)  /* Bit 3: RTS/DTR used for direction control (DCTRL=1) */
+#define UART_RS485CTRL_DCTRL         (1 << 4)  /* Bit 4: Enable Auto Direction Control */
+#define UART_RS485CTRL_OINV          (1 << 5)  /* Bit 5: Polarity of the direction control signal on RTS/DTR */
+                                               /* Bits 6-31: Reserved */
+/* RS-485/EIA-485 address match */
+
+#define UART_ADRMATCH_MASK           (0xff)    /* Bits 0-7: Address match value */
+                                               /* Bits 8-31: Reserved */
+/* RS-485/EIA-485 direction control delay */
+
+#define UART_RS485DLY_MASK           (0xff)    /* Bits 0-7: Firection control (RTS/DTR) delay */
+                                               /* Bits 8-31: Reserved */
+/* Synchronous mode control register (USART only) */
+
+#define USART_SYNCCTRL_SYNC          (1 << 0)  /* Bit 0: Enables synchronous mode */
+#define USART_SYNCCTRL_CSRC          (1 << 1)  /* Bit 1: Clock source select */
+#define USART_SYNCCTRL_FES           (1 << 2)  /* Bit 2: Falling edge sampling */
+#define USART_SYNCCTRL_TSBYPASS      (1 << 3)  /* Bit 3: Transmit synchronization bypass */
+#define USART_SYNCCTRL_CSCEN         (1 << 4)  /* Bit 4: Continuous master clock enable */
+#define USART_SYNCCTRL_SSSDIS        (1 << 5)  /* Bit 5: Start/stop bits */
+#define USART_SYNCCTRL_CCCLR         (1 << 6)  /* Bit 6: Continuous clock clear */
+                                               /* Bits 7-31: Reserved */
+/* TER Transmit Enable Register (USART only) */
+
+#define USART_TER_TXEN               (1 << 0)  /* Bit 0:  TX Enable */
+                                               /* Bits 1-31: Reserved */
+
+/********************************************************************************************
+ * Public Types
+ ********************************************************************************************/
+
+/********************************************************************************************
+ * Public Data
+ ********************************************************************************************/
+
+/********************************************************************************************
+ * Public Functions
+ ********************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_UART_H */
diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_usb0.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_usb0.h
new file mode 100644
index 000000000..6d18dd41c
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_usb0.h
@@ -0,0 +1,716 @@
+/************************************************************************************************
+ * arch/arm/src/lpc43xx/lpc43_usb0.h
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_USB0_H
+#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_USB0_H
+
+/************************************************************************************************
+ * Included Files
+ ************************************************************************************************/
+
+#include <nuttx/config.h>
+
+/************************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************************/
+
+/* Register Offsets *****************************************************************************/
+                                                    /* 0x000 - 0x0ff: Reserved */
+/* Device/host capability registers */
+
+#define LPC43_USBOTG_CAPLENGTH_OFFSET        0x0100 /* Capability length register */
+#define LPC43_USBHOST_HCSPARAMS_OFFSET       0x0104 /* Host controller structural parameters */
+#define LPC43_USBHOST_HCCPARAMS_OFFSET       0x0108 /* Host controller capability parameters */
+#define LPC43_USBDEV_DCIVERSION_OFFSET       0x0120 /* Device interface version number */
+#define LPC43_USBDEV_DCCPARAMS_OFFSET        0x0124 /* Device controller capability parameters */
+
+/* Device/host/OTG operational registers */
+
+#define LPC43_USBOTG_USBCMD_OFFSET           0x0140 /* USB command (both) */
+#define LPC43_USBOTG_USBSTS_OFFSET           0x0144 /* USB status (both) */
+#define LPC43_USBOTG_USBINTR_OFFSET          0x0148 /* USB interrupt enable (both) */
+#define LPC43_USBOTG_FRINDEX_OFFSET          0x014c /* USB frame index (both) */
+#define LPC43_USBHOST_PERIODICLIST_OFFSET    0x0154 /* Frame list base address (host) */
+#define LPC43_USBDEV_DEVICEADDR_OFFSET       0x0154 /* USB device address (device) */
+#define LPC43_USBHOST_ASYNCLISTADDR_OFFSET   0x0158 /* Next asynchronous list address (host) */
+#define LPC43_USBDEV_ENDPOINTLIST_OFFSET     0x0158 /* Address of endpoint list in memory (device) */
+#define LPC43_USBHOST_TTCTRL_OFFSET          0x015c /* Asynchronous buffer status for embedded TT (host) */
+#define LPC43_USBOTG_BURSTSIZE_OFFSET        0x0160 /* Programmable burst size (both) */
+#define LPC43_USBHOST_TXFILLTUNING_OFFSET    0x0164 /* Host transmit pre-buffer packet tuning (host) */
+#define LPC43_USBOTG_BINTERVAL_OFFSET        0x0174 /* Length of virtual frame (both) */
+#define LPC43_USBDEV_ENDPTNAK_OFFSET         0x0178 /* Endpoint NAK (device) */
+#define LPC43_USBDEV_ENDPTNAKEN_OFFSET       0x017c /* Endpoint NAK Enable (device) */
+#define LPC43_USBOTG_PORTSC1_OFFSET          0x0184 /* Port status/control 1 (both) */
+#define LPC43_USBOTG_OTGSC_OFFSET            0x01a4 /* OTG status and control (otg) */
+#define LPC43_USBOTG_USBMODE_OFFSET          0x01a8 /* USB device mode (both) */
+
+/* Device side naming of common register offsets */
+
+#define LPC43_USBDEV_USBCMD_OFFSET           LPC43_USBOTG_USBCMD_OFFSET
+#define LPC43_USBDEV_USBSTS_OFFSET           LPC43_USBOTG_USBSTS_OFFSET
+#define LPC43_USBDEV_USBINTR_OFFSET          LPC43_USBOTG_USBINTR_OFFSET
+#define LPC43_USBDEV_FRINDEX_OFFSET          LPC43_USBOTG_FRINDEX_OFFSET
+#define LPC43_USBDEV_BURSTSIZE_OFFSET        LPC43_USBOTG_BURSTSIZE_OFFSET
+#define LPC43_USBDEV_BINTERVAL_OFFSET        LPC43_USBOTG_BINTERVAL_OFFSET
+#define LPC43_USBDEV_PORTSC1_OFFSET          LPC43_USBOTG_USBMODE_OFFSET
+#define LPC43_USBDEV_USBMODE_OFFSET          LPC43_USBOTG_USBMODE_OFFSET
+
+/* Host side naming of common registers */
+
+#define LPC43_USBHOST_USBCMD_OFFSET          LPC43_USBOTG_USBCMD_OFFSET
+#define LPC43_USBHOST_USBSTS_OFFSET          LPC43_USBOTG_USBSTS_OFFSET
+#define LPC43_USBHOST_USBINTR_OFFSET         LPC43_USBOTG_USBINTR_OFFSET
+#define LPC43_USBHOST_FRINDEX_OFFSET         LPC43_USBOTG_FRINDEX_OFFSET
+#define LPC43_USBHOST_BURSTSIZE_OFFSET       LPC43_USBOTG_BURSTSIZE_OFFSET
+#define LPC43_USBHOST_BINTERVAL_OFFSET       LPC43_USBOTG_BINTERVAL_OFFSET
+#define LPC43_USBHOST_PORTSC1_OFFSET         LPC43_USBOTG_USBMODE_OFFSET
+#define LPC43_USBHOST_USBMODE_OFFSET         LPC43_USBOTG_USBMODE_OFFSET
+
+/* Device endpoint registers */
+
+#define LPC43_USBDEV_ENDPTSETUPSTAT_OFFSET   0x01ac /* Endpoint setup status */
+#define LPC43_USBDEV_ENDPTPRIME_OFFSET       0x01b0 /* Endpoint initialization */
+#define LPC43_USBDEV_ENDPTFLUSH_OFFSET       0x01b4 /* Endpoint de-initialization */
+#define LPC43_USBDEV_ENDPTSTATUS_OFFSET      0x01b8 /* Endpoint status */
+#define LPC43_USBDEV_ENDPTCOMPLETE_OFFSET    0x01bc /* Endpoint complete */
+
+#define LPC43_USBDEV_ENDPTCTRL_OFFSET(n)     (0x01c0 + ((n) << 2))
+#define LPC43_USBDEV_ENDPTCTRL0_OFFSET       0x01c0 /* Endpoint control 0 */
+#define LPC43_USBDEV_ENDPTCTRL1_OFFSET       0x01c4 /* Endpoint control 1 */
+#define LPC43_USBDEV_ENDPTCTRL2_OFFSET       0x01c8 /* Endpoint control 2 */
+#define LPC43_USBDEV_ENDPTCTRL3_OFFSET       0x01cc /* Endpoint control 3 */
+#define LPC43_USBDEV_ENDPTCTRL4_OFFSET       0x01d0 /* Endpoint control 4 */
+#define LPC43_USBDEV_ENDPTCTRL5_OFFSET       0x01d4 /* Endpoint control 5 */
+
+/* USB0 register (virtual) addresses **********************************************************/
+
+/* Device/host capability registers */
+
+#define LPC43_USBOTG_CAPLENGTH               (LPC43_USBOTG_BASE+LPC43_USBOTG_CAPLENGTH_OFFSET)
+#define LPC43_USBHOST_HCIVERSION             (LPC43_USBOTG_BASE+LPC43_USBHOST_HCIVERSION_OFFSET)
+#define LPC43_USBHOST_HCSPARAMS              (LPC43_USBOTG_BASE+LPC43_USBHOST_HCSPARAMS_OFFSET)
+#define LPC43_USBHOST_HCCPARAMS              (LPC43_USBOTG_BASE+LPC43_USBHOST_HCCPARAMS_OFFSET)
+#define LPC43_USBDEV_DCIVERSION              (LPC43_USBOTG_BASE+LPC43_USBDEV_DCIVERSION_OFFSET)
+#define LPC43_USBDEV_DCCPARAMS               (LPC43_USBOTG_BASE+LPC43_USBDEV_DCCPARAMS_OFFSET)
+
+/* Device/host operational registers */
+
+#define LPC43_USBOTG_USBCMD                  (LPC43_USBOTG_BASE+LPC43_USBOTG_USBCMD_OFFSET)
+#define LPC43_USBOTG_USBSTS                  (LPC43_USBOTG_BASE+LPC43_USBOTG_USBSTS_OFFSET)
+#define LPC43_USBOTG_USBINTR                 (LPC43_USBOTG_BASE+LPC43_USBOTG_USBINTR_OFFSET)
+#define LPC43_USBOTG_FRINDEX                 (LPC43_USBOTG_BASE+LPC43_USBOTG_FRINDEX_OFFSET)
+#define LPC43_USBHOST_PERIODICLIST           (LPC43_USBOTG_BASE+LPC43_USBHOST_PERIODICLIST_OFFSET)
+#define LPC43_USBDEV_DEVICEADDR              (LPC43_USBOTG_BASE+LPC43_USBDEV_DEVICEADDR_OFFSET)
+#define LPC43_USBHOST_ASYNCLISTADDR          (LPC43_USBOTG_BASE+LPC43_USBHOST_ASYNCLISTADDR_OFFSET)
+#define LPC43_USBDEV_ENDPOINTLIST            (LPC43_USBOTG_BASE+LPC43_USBDEV_ENDPOINTLIST_OFFSET)
+#define LPC43_USBHOST_TTCTRL                 (LPC43_USBOTG_BASE+LPC43_USBHOST_TTCTRL_OFFSET)
+#define LPC43_USBOTG_BURSTSIZE               (LPC43_USBOTG_BASE+LPC43_USBOTG_BURSTSIZE_OFFSET)
+#define LPC43_USBHOST_TXFILLTUNING           (LPC43_USBOTG_BASE+LPC43_USBHOST_TXFILLTUNING_OFFSET)
+#define LPC43_USBOTG_BINTERVAL               (LPC43_USBOTG_BASE+LPC43_USBOTG_BINTERVAL_OFFSET)
+#define LPC43_USBDEV_ENDPTNAK                (LPC43_USBOTG_BASE+LPC43_USBDEV_ENDPTNAK_OFFSET)
+#define LPC43_USBDEV_ENDPTNAKEN              (LPC43_USBOTG_BASE+LPC43_USBDEV_ENDPTNAKEN_OFFSET)
+#define LPC43_USBOTG_PORTSC1                 (LPC43_USBOTG_BASE+LPC43_USBOTG_PORTSC1_OFFSET)
+#define LPC43_USBOTG_OTGSC                   (LPC43_USBOTG_BASE+LPC43_USBOTG_OTGSC_OFFSET)
+#define LPC43_USBOTG_USBMODE                 (LPC43_USBOTG_BASE+LPC43_USBOTG_USBMODE_OFFSET)
+
+/* Device side naming of common register offsets */
+
+#define LPC43_USBDEV_USBCMD                  LPC43_USBOTG_USBCMD       
+#define LPC43_USBDEV_USBSTS                  LPC43_USBOTG_USBSTS       
+#define LPC43_USBDEV_USBINTR                 LPC43_USBOTG_USBINTR       
+#define LPC43_USBDEV_FRINDEX                 LPC43_USBOTG_FRINDEX       
+#define LPC43_USBDEV_BURSTSIZE               LPC43_USBOTG_BURSTSIZE       
+#define LPC43_USBDEV_BINTERVAL               LPC43_USBOTG_BINTERVAL       
+#define LPC43_USBDEV_PORTSC1                 LPC43_USBOTG_USBMODE       
+#define LPC43_USBDEV_USBMODE                 LPC43_USBOTG_USBMODE       
+
+/* Host side naming of common registers */
+
+#define LPC43_USBHOST_USBCMD                 LPC43_USBOTG_USBCMD       
+#define LPC43_USBHOST_USBSTS                 LPC43_USBOTG_USBSTS       
+#define LPC43_USBHOST_USBINTR                LPC43_USBOTG_USBINTR       
+#define LPC43_USBHOST_FRINDEX                LPC43_USBOTG_FRINDEX       
+#define LPC43_USBHOST_BURSTSIZE              LPC43_USBOTG_BURSTSIZE       
+#define LPC43_USBHOST_BINTERVAL              LPC43_USBOTG_BINTERVAL       
+#define LPC43_USBHOST_PORTSC1                LPC43_USBOTG_USBMODE       
+#define LPC43_USBHOST_USBMODE                LPC43_USBOTG_USBMODE       
+
+/* Device endpoint registers */
+
+#define LPC43_USBDEV_ENDPTSETUPSTAT          (LPC43_USBOTG_BASE+LPC43_USBDEV_ENDPTSETUPSTAT_OFFSET)
+#define LPC43_USBDEV_ENDPTPRIME              (LPC43_USBOTG_BASE+LPC43_USBDEV_ENDPTPRIME_OFFSET)
+#define LPC43_USBDEV_ENDPTFLUSH              (LPC43_USBOTG_BASE+LPC43_USBDEV_ENDPTFLUSH_OFFSET)
+#define LPC43_USBDEV_ENDPTSTATUS             (LPC43_USBOTG_BASE+LPC43_USBDEV_ENDPTSTATUS_OFFSET)
+#define LPC43_USBDEV_ENDPTCOMPLETE           (LPC43_USBOTG_BASE+LPC43_USBDEV_ENDPTCOMPLETE_OFFSET)
+
+#define LPC43_USBDEV_ENDPTCTRL(n)            (LPC43_USBOTG_BASE+LPC43_USBDEV_ENDPTCTRL_OFFSET(n))
+#define LPC43_USBDEV_ENDPTCTRL0              (LPC43_USBOTG_BASE+LPC43_USBDEV_ENDPTCTRL0_OFFSET)
+#define LPC43_USBDEV_ENDPTCTRL1              (LPC43_USBOTG_BASE+LPC43_USBDEV_ENDPTCTRL1_OFFSET)
+#define LPC43_USBDEV_ENDPTCTRL2              (LPC43_USBOTG_BASE+LPC43_USBDEV_ENDPTCTRL2_OFFSET)
+#define LPC43_USBDEV_ENDPTCTRL3              (LPC43_USBOTG_BASE+LPC43_USBDEV_ENDPTCTRL3_OFFSET)
+#define LPC43_USBDEV_ENDPTCTRL4              (LPC43_USBOTG_BASE+LPC43_USBDEV_ENDPTCTRL4_OFFSET)
+#define LPC43_USBDEV_ENDPTCTRL5              (LPC43_USBOTG_BASE+LPC43_USBDEV_ENDPTCTRL5_OFFSET)
+
+/* USB0 register bit definitions **************************************************************/
+
+/* Device/host capability registers */
+/* Capability length register */
+
+#define USBOTG_CAPLENGTH_SHIFT               (0)       /* Bits 0-7: Offset from register base to operational regs */
+#define USBOTG_CAPLENGTH_MASK                (0xff << USBOTG_CAPLENGTH_SHIFT)
+#define USBHOST_HCIVERSION_SHIFT             (8)       /* Bits 8-23: BCD encoding of the EHCI revision number */
+#define USBHOST_HCIVERSION_MASK              (0xffff << USBHOST_HCIVERSION_SHIFT)
+                                                       /* Bits 24-31: Reserved */
+/* Host controller structural parameters */
+
+#define USBHOST_HCSPARAMS_NPORTS_SHIF        (0)       /* Bits 0-3: Number of downstream ports */
+#define USBHOST_HCSPARAMS_NPORTS_MASK        (15 << USBHOST_HCSPARAMS_NPORTS_SHIFT)
+#define USBHOST_HCSPARAMS_PPC                (1 >> 4)  /* Bit 4:  Port Power Control */
+                                                       /* Bits 5-7: Reserved */
+#define USBHOST_HCSPARAMS_NPCC_SHIFT         (8)       /* Bits 8-11: Number of Ports per Companion Controller */
+#define USBHOST_HCSPARAMS_NPCC_MASK          (15 << USBHOST_HCSPARAMS_NPCC_SHIFT)
+#define USBHOST_HCSPARAMS_NCC_SHIFT          (15)      /* Bits 12-15: Number of Companion Controller */
+#define USBHOST_HCSPARAMS_NCC_MASK           (15 << USBHOST_HCSPARAMS_NCC_SHIFT)
+#define USBHOST_HCSPARAMS_PI                 (1 >> 16) /* Bit 16: Port indicators */
+                                                       /* Bits 17-19: Reserved */
+#define USBHOST_HCSPARAMS_NPTT_SHIFT         (20)      /* Bits 20-23: Number of Ports per Transaction Translator */
+#define USBHOST_HCSPARAMS_NPTT_MASK          (15 << USBHOST_HCSPARAMS_NPTT_SHIFT)
+#define USBHOST_HCSPARAMS_NTT_SHIFT          (24)      /* Bits 24-27: Number of Transaction Translators */
+#define USBHOST_HCSPARAMS_NTT_MASK           (15 << USBHOST_HCSPARAMS_NTT_SHIFT)
+                                                       /* Bits 28-31: Reserved */
+/* Host controller capability parameters */
+
+#define USBHOST_HCCPARAMS_ADC                (1 >> 0)  /* Bit 0:  64-bit Addressing Capability */
+#define USBHOST_HCCPARAMS_PFL                (1 >> 1)  /* Bit 1:  Programmable Frame List Flag */
+#define USBHOST_HCCPARAMS_ASP                (1 >> 2)  /* Bit 2:  Asynchronous Schedule Park Capability */
+#define USBHOST_HCCPARAMS_IST_SHIFT          (4)       /* Bits 4-7: Isochronous Scheduling Threshold */
+#define USBHOST_HCCPARAMS_IST_MASK           (15 << USBHOST_HCCPARAMS_IST_SHIFT)
+#define USBHOST_HCCPARAMS_EECP_SHIFT         (8)       /* Bits 8-15: EHCI Extended Capabilities Pointer */
+#define USBHOST_HCCPARAMS_EECP_MASK          (255 << USBHOST_HCCPARAMS_EECP_SHIFT)
+                                                       /* Bits 16-31: Reserved */
+/* Device interface version number */
+
+#define USBDEV_DCIVERSION_SHIFT              (0)       /* Bits 0-15: BCD encoding of the device interface */
+#define USBDEV_DCIVERSION_MASK               (0xffff << USBDEV_DCIVERSION_SHIFT)
+                                                       /* Bits 16-31: Reserved */
+
+/* Device controller capability parameters */
+
+#define USBDEV_DCCPARAMS_DEN_SHIFT           (0)       /* Bits 0-4: DEN Device Endpoint Number */
+#define USBDEV_DCCPARAMS_DEN_MASK            (31 << USBDEV_DCCPARAMS_DEN_SHIFT)
+                                                       /* Bits 5-6: Reserved */
+#define USBDEV_DCCPARAMS_DC                  (1 >> 7)  /* Bit 7:  Device Capable */
+#define USBDEV_DCCPARAMS_HC                  (1 >> 8)  /* Bit 8:  Host Capable */
+                                                       /* Bits 9-31: Reserved */
+/* Device/host operational registers */
+/* USB Command register USBCMD -- Device Mode */
+
+#define USBDEV_USBCMD_RS                     (1 << 0)  /* Bit 0:  0 Run/Stop */
+#define USBDEV_USBCMD_RST                    (1 << 1)  /* Bit 1:  Controller reset */
+                                                       /* Bits 2-12: Reserved OR not used in device mode */
+#define USBDEV_USBCMD_SUTW                   (1 << 13) /* Bit 13: Setup trip wire */
+#define USBDEV_USBCMD_ATDTW                  (1 << 14) /* Bit 14: Add dTD trip wire */
+                                                       /* Bit 15: Reserved OR not used in device mode */
+#define USBDEV_USBCMD_ITC_SHIFT              (16)      /* Bits 16-23: Interrupt threshold control */
+#define USBDEV_USBCMD_ITC_MASK               (255 << USBDEV_USBCMD_ITC_SHIFT)
+#  define USBDEV_USBCMD_ITCIMME              (0  << USBDEV_USBCMD_ITC_SHIFT) /* Immediate (no threshold) */
+#  define USBDEV_USBCMD_ITC1UF               (1  << USBDEV_USBCMD_ITC_SHIFT) /* 1 micro frame */
+#  define USBDEV_USBCMD_ITC2UF               (2  << USBDEV_USBCMD_ITC_SHIFT) /* 2 micro frames */
+#  define USBDEV_USBCMD_ITC4UF               (4  << USBDEV_USBCMD_ITC_SHIFT) /* 4 micro frames */
+#  define USBDEV_USBCMD_ITC8UF               (8  << USBDEV_USBCMD_ITC_SHIFT) /* 8 micro frames */
+#  define USBDEV_USBCMD_ITC16UF              (16 << USBDEV_USBCMD_ITC_SHIFT) /* 16 micro frames */
+#  define USBDEV_USBCMD_ITC32UF              (32 << USBDEV_USBCMD_ITC_SHIFT) /* 32 micro frames */
+#  define USBDEV_USBCMD_ITC64UF              (64 << USBDEV_USBCMD_ITC_SHIFT) /* 64 micro frames */
+                                                       /* Bits 24-31: Reserved */
+/* USB Command register USBCMD -- Host Mode */
+
+#define USBHOST_USBCMD_RS                    (1 << 0)  /* Bit 0:  Run/Stop */
+#define USBHOST_USBCMD_RST                   (1 << 1)  /* Bit 1:  Controller reset */
+#define USBHOST_USBCMD_FS0                   (1 << 2)  /* Bit 2:  Bit 0 of the Frame List Size bits */
+#define USBHOST_USBCMD_FS1                   (1 << 3)  /* Bit 3:  Bit 1 of the Frame List Size bits */
+#define USBHOST_USBCMD_PSE                   (1 << 4)  /* Bit 4:  Skips processing periodic schedule */
+#define USBHOST_USBCMD_ASE                   (1 << 5)  /* Bit 5:  Skips processing asynchronous schedule */
+#define USBHOST_USBCMD_IAA                   (1 << 6)  /* Bit 6:  Interrupt next asynchronous schedule */
+                                                       /* Bit 7: Reserved OR not used in host mode */
+#define USBHOST_USBCMD_ASP_SHIFT             (8)       /* Bits 8-9: Asynchronous schedule park mode */
+#define USBHOST_USBCMD_ASP_MASK              (3 << USBHOST_USBCMD_ASP_SHIFT)
+                                                       /* Bit 10: Reserved OR not used in host mode */
+#define USBHOST_USBCMD_ASPE                  (1 << 11) /* Bit 11: Asynchronous Schedule Park Mode Enable */
+                                                       /* Bits 12-14: Reserved OR not used in host mode */
+#define USBHOST_USBCMD_FS2                   (1 << 15) /* Bit 15: Bit 2 of the Frame List Size bits */
+#define USBHOST_USBCMD_ITC_SHIFT             (16)      /* Bits 16-13: Interrupt threshold control */
+#define USBHOST_USBCMD_ITC_MASK              (255 << USBHOST_USBCMD_ITC_SHIFT)
+#  define USBHOST_USBCMD_ITCIMMED            (0  << USBHOST_USBCMD_ITC_SHIFT) /* Immediate (no threshold) */
+#  define USBHOST_USBCMD_ITC1UF              (1  << USBHOST_USBCMD_ITC_SHIFT) /* 1 micro frame */
+#  define USBHOST_USBCMD_ITC2UF              (2  << USBHOST_USBCMD_ITC_SHIFT) /* 2 micro frames */
+#  define USBHOST_USBCMD_ITC4UF              (4  << USBHOST_USBCMD_ITC_SHIFT) /* 4 micro frames */
+#  define USBHOST_USBCMD_ITC8UF              (8  << USBHOST_USBCMD_ITC_SHIFT) /* 8 micro frames */
+#  define USBHOST_USBCMD_ITC16UF             (16 << USBHOST_USBCMD_ITC_SHIFT) /* 16 micro frames */
+#  define USBHOST_USBCMD_ITC32UF             (32 << USBHOST_USBCMD_ITC_SHIFT) /* 32 micro frames */
+#  define USBHOST_USBCMD_ITC64UF             (64 << USBHOST_USBCMD_ITC_SHIFT) /* 64 micro frames */
+                                                       /* Bits 24-31: Reserved */
+/* USB Status register USBSTS -- Device Mode */
+
+#define USBDEV_USBSTS_UI                     (1 << 0)  /* Bit 0:  USB interrupt */
+#define USBDEV_USBSTS_UEI                    (1 << 1)  /* Bit 1:  USB error interrupt */
+#define USBDEV_USBSTS_PCI                    (1 << 2)  /* Bit 2:  Port change detect */
+                                                       /* Bits 3-5: Reserved OR not used in device mode */
+#define USBDEV_USBSTS_URI                    (1 << 6)  /* Bit 6:  USB reset received */
+#define USBDEV_USBSTS_SRI                    (1 << 7)  /* Bit 7:  SOF received */
+#define USBDEV_USBSTS_SLI                    (1 << 8)  /* Bit 8:  DCSuspend */
+                                                       /* Bits 9-15: Reserved OR not used in device mode */
+#define USBDEV_USBSTS_NAKI                   (1 << 16) /* Bit 16: NAK interrupt bit */
+                                                       /* Bits 17-31: Reserved OR not used in device mode */
+/* USB Status register USBSTS -- Host Mode */
+
+#define USBHOST_USBSTS_UI                    (1 << 0)  /* Bit 0:  USB interrupt */
+#define USBHOST_USBSTS_UEI                   (1 << 1)  /* Bit 1:  USB error interrupt */
+#define USBHOST_USBSTS_PCI                   (1 << 2)  /* Bit 2:  Port change detect */
+#define USBHOST_USBSTS_FRI                   (1 << 3)  /* Bit 3:  Frame list roll-over */
+                                                       /* Bit 4:  Reserved */
+#define USBHOST_USBSTS_AAI                   (1 << 5)  /* Bit 5:  Interrupt on async advance */
+                                                       /* Bit 6:  Not used in host mode */
+#define USBHOST_USBSTS_SRI                   (1 << 7)  /* Bit 7:  SOF received */
+                                                       /* Bit 8-11: Reserved OR Not used in host mode */
+#define USBHOST_USBSTS_HCH                   (1 << 12) /* Bit 12: HCHalted */
+#define USBHOST_USBSTS_RCL                   (1 << 13) /* Bit 13: Reclamation */
+#define USBHOST_USBSTS_PS                    (1 << 14) /* Bit 14: Periodic schedule status */
+#define USBHOST_USBSTS_AS                    (1 << 15) /* Bit 15: Asynchronous schedule status */
+                                                       /* Bit 16-17: Reserved OR Not used in host mode */
+#define USBHOST_USBSTS_UAI                   (1 << 18) /* Bit 18: USB host asynchronous interrupt */
+#define USBHOST_USBSTS_UPI                   (1 << 19) /* Bit 19: USB host periodic interrupt */
+                                                       /* Bits 20-31: Reserved */
+/* USB interrupt register USBINTR -- Device Mode */
+
+#define USBDEV_USBINTR_UE                    (1 << 0)  /* Bit 0:  USB interrupt enable */
+#define USBDEV_USBINTR_UEE                   (1 << 1)  /* Bit 1:  USB error interrupt enable */
+#define USBDEV_USBINTR_PCE                   (1 << 2)  /* Bit 2:  Port change detect enable */
+                                                       /* Bits 3-5: Reserved OR Not used in device mode */
+#define USBDEV_USBINTR_URE                   (1 << 6)  /* Bit 6:  USB reset enable */
+#define USBDEV_USBINTR_SRE                   (1 << 7)  /* Bit 7:  SOF received enable */
+#define USBDEV_USBINTR_SLE                   (1 << 8)  /* Bit 8:  Sleep enable */
+                                                       /* Bits 8-15: Reserved */
+#define USBDEV_USBINTR_NAKE                  (1 << 16) /* Bit 16: NAK interrupt enable */
+                                                       /* Bits 17-31: Reserved OR Not used in device mode */
+/* USB interrupt register USBINTR -- Host Mode */
+
+#define USBHOST_USBINTR_UE                   (1 << 0)  /* Bit 0:  USB interrupt enable */
+#define USBHOST_USBINTR_UEE                  (1 << 1)  /* Bit 1:  USB error interrupt enable */
+#define USBHOST_USBINTR_PCE                  (1 << 2)  /* Bit 2:  Port change detect enable */
+#define USBHOST_USBINTR_FRE                  (1 << 3)  /* Bit 3:  Frame list rollover enable */
+                                                       /* Bit 4:  Reserved */
+#define USBHOST_USBINTR_AAE                  (1 << 5)  /* Bit 5:  Interrupt on asynchronous advance enable */
+                                                       /* Bit 6:  Not used in host mode */
+#define USBHOST_USBINTR_SRE                  (1 << 7)  /* Bit 7:  SOF timer interrupt enable */
+                                                       /* Bits 8-17: Reserved OR Not used in host mode */
+#define USBHOST_USBINTR_UAIE                 (1 << 18) /* Bit 18: USB host asynchronous interrupt enable */
+#define USBHOST_USBINTR_UPIA                 (1 << 19) /* Bit 19: USB host periodic interrupt enable */
+                                                       /* Bits 20-31:  Reserved */
+/* Frame index register FRINDEX -- Device Mode */
+
+#define USBDEV_FRINDEX_CUFN_SHIFT            (0)       /* Bits 0-2: Current micro frame number */
+#define USBDEV_FRINDEX_CUFN_MASK             (7 << USBDEV_FRINDEX_CUFN_SHIFT)
+#define USBDEV_FRINDEX_LFN_SHIFT             (3)       /* Bits 3-13: Frame number of last frame transmitted */
+#define USBDEV_FRINDEX_LFN_MASK              (0x7ff << USBDEV_FRINDEX_LFN_SHIFT)
+                                                       /* Bits 14-31:  Reserved */
+/* Frame index register FRINDEX -- Host Mode */
+
+#define USBHOST_FRINDEX_CUFN_SHIFT           (0)       /* Bits 0-2: Current micro frame number */
+#define USBHOST_FRINDEX_CUFN_MASK            (7 << USBHOST_FRINDEX_CUFN_SHIFT)
+#define USBHOST_FRINDEX_FLI_SHIFT            (3)       /* Bits 3-12: Frame list current index */
+#define USBHOST_FRINDEX_FLI_MASK             (0x3ff << USBHOST_FRINDEX_FLI_SHIFT)
+                                                       /* Bits 13-31:  Reserved */
+/* USB Device Address register DEVICEADDR -- Device Mode */
+                                                       /* Bits 0-23:  Reserved */
+#define USBDEV_DEVICEADDR_USBADRA            (1 << 24) /* Bit 24: Device address advance */
+#define USBDEV_DEVICEADDR_SHIFT              (25)      /* Bits 25-31: USBADR USB device address */
+#define USBDEV_DEVICEADDR_MASK               (0x3f << USBDEV_DEVICEADDR_SHIFT)
+
+/* USB Periodic List Base register PERIODICLIST -- Host Mode */
+                                                       /* Bits 0-11:  Reserved */
+#define USBHOST_PERIODICLIST_PERBASE_SHIFT   (12)      /* Bits 12-31: Base Address (Low) */
+#define USBHOST_PERIODICLIST_PERBASE_MASK    (0x000fffff << USBHOST_PERIODICLIST_PERBASE_SHIFT)
+
+/* USB Endpoint List Address register ENDPOINTLISTADDR -- Device Mode */
+                                                       /* Bits 0-10:  Reserved */
+#define USBDEV_ENDPOINTLIST_EPBASE_SHIFT     (11)      /* Bits 11-31: Endpoint list pointer (low) */
+#define USBDEV_ENDPOINTLIST_EPBASE_MASK      (0x001fffff << USBDEV_ENDPOINTLIST_EPBASE_SHIFT)
+
+/* USB Asynchronous List Address register ASYNCLISTADDR -- Host Mode */
+                                                       /* Bits 0-4:  Reserved */
+#define USBHOST_ASYNCLISTADDR_ASYBASE_SHIFT  (5)       /* Bits 5-31: Link pointer (Low) LPL */
+#define USBHOST_ASYNCLISTADDR_ASYBASE_MASK   (0x07ffffff << USBHOST_ASYNCLISTADDR_ASYBASE_SHIFT)
+
+/* USB TT Control register TTCTRL -- Host Mode */
+                                                       /* Bits 0-23:  Reserved */
+#define USBHOST_TTCTRL_TTHA_SHIFT            (24)      /* Bits 24-30: Hub address */
+#define USBHOST_TTCTRL_TTHA_MASK             (0x7f << USBHOST_TTCTRL_TTHA_SHIFT)
+
+/* USB burst size register BURSTSIZE -- Device/Host Mode */
+
+#define USBHOST_BURSTSIZE_RXPBURST_SHIFT     (0)       /* Bits 0-7: RXPBURST Programmable RX burst length */
+#define USBHOST_BURSTSIZE_RXPBURST_MASK      (255 << USBHOST_BURSTSIZE_RXPBURST_SHIFT) 
+#define USBHOST_BURSTSIZE_TXPBURST_SHIFT     (8)       /* Bits 8-15: Programmable TX burst length */
+#define USBHOST_BURSTSIZE_TXPBURST_MASK      (255 << USBHOST_BURSTSIZE_TXPBURST_SHIFT)
+                                                       /* Bits 16-31: Reserved */
+
+#define USBDEV_BURSTSIZE_RXPBURST_SHIFT      (0)       /* Bits 0-7: RXPBURST Programmable RX burst length */
+#define USBDEV_BURSTSIZE_RXPBURST_MASK       (255 << USBDEV_BURSTSIZE_RXPBURST_SHIFT) 
+#define USBDEV_BURSTSIZE_TXPBURST_SHIFT      (8)       /* Bits 8-15: Programmable TX burst length */
+#define USBDEV_BURSTSIZE_TXPBURST_MASK       (255 << USBDEV_BURSTSIZE_TXPBURST_SHIFT)
+                                                       /* Bits 16-31: Reserved */
+/* USB Transfer buffer Fill Tuning register TXFIFOFILLTUNING -- Host Mode */
+
+#define USBHOST_TXFILLTUNING_SCHOH_SHIFT     (0)       /* Bits 0-7: FIFO burst threshold */
+#define USBHOST_TXFILLTUNING_SCHOH_MASK      (0xff << USBHOST_TXFILLTUNING_SCHOH_SHIFT)
+#define USBHOST_TXFILLTUNING_SCHEATLTH_SHIFT (8)       /* Bits 8-12: Scheduler health counter */
+#define USBHOST_TXFILLTUNING_SCHEATLTH_MASK  (0x1f << USBHOST_TXFILLTUNING_SCHEATLTH_SHIFT)
+#define USBHOST_TXFILLTUNING_FIFOTHRES_SHIFT (16)      /* Bits 16-21: Scheduler overhead */
+#define USBHOST_TXFILLTUNING_FIFOTHRES_MASK  (0x3f << USBHOST_TXFILLTUNING_FIFOTHRES_SHIFT)
+                                                       /* Bits 22-31: Reserved */
+/* USB BINTERVAL register BINTERVAL -- Device/Host Mode */
+
+#define USBDEV_BINTERVAL_SHIFT               (0)       /* Bits 0-3: bInterval value */
+#define USBDEV_BINTERVAL_MASK                (15 << USBDEV_BINTERVAL_SHIFT)
+                                                       /* Bits 4-31: Reserved */
+
+#define USBHOST_BINTERVAL_SHIFT              (0)       /* Bits 0-3: bInterval value */
+#define USBHOST_BINTERVAL_MASK               (15 << USBHOST_BINTERVAL_SHIFT)
+                                                       /* Bits 4-31: Reserved */
+/* USB endpoint NAK register ENDPTNAK -- Device Mode */
+
+#define USBDEV_ENDPTNAK_EPRN_SHIFT           (0)       /* Bits 0-5: Rx endpoint NAK */
+#define USBDEV_ENDPTNAK_EPRN_MASK            (0x3f << USBDEV_ENDPTNAK_EPRN_SHIFT)
+                                                       /* Bits 6-15: Reserved */
+#define USBDEV_ENDPTNAK_EPTN_SHIFT           (16)      /* Bits 16-21: Tx endpoint NAK */
+#define USBDEV_ENDPTNAK_EPTN_MASK            (0x3f << USBDEV_ENDPTNAK_EPTN_SHIFT)
+                                                       /* Bits 22-31: Reserved */
+/* USB Endpoint NAK Enable register ENDPTNAKEN -- Device Mode */
+
+#define USBDEV_ENDPTNAK_EPRNE_SHIFT          (0)       /* Bits 0-5: Rx endpoint NAK enable */
+#define USBDEV_ENDPTNAK_EPRNE_MASK           (0x3f << USBDEV_ENDPTNAK_EPRNE_SHIFT)
+                                                       /* Bits 6-15: Reserved */
+#define USBDEV_ENDPTNAK_EPTNE_SHIFT          (16)      /* Bits 16-21: Tx endpoint NAK enable */
+#define USBDEV_ENDPTNAK_EPTNE_MASK           (0x3f << USBDEV_ENDPTNAK_EPTNE_SHIFT)
+                                                       /* Bits 22-31: Reserved */
+/* Port Status and Control register PRTSC1 -- Device Mode */
+
+#define USBDEV_PRTSC1_CCS                    (1 << 0)  /* Bit 0:  Current connect status */
+                                                       /* Bit 1:  Not used in device mode */
+#define USBDEV_PRTSC1_PE                     (1 << 2)  /* Bit 2:  Port enable */
+#define USBDEV_PRTSC1_PEC                    (1 << 3)  /* Bit 3:  Port enable/disable change */
+#define USBDEV_PRTSC1_FPR                    (1 << 6)  /* Bit 6:  Force port resume */
+#define USBDEV_PRTSC1_SUSP                   (1 << 7)  /* Bit 7:  Suspend */
+#define USBDEV_PRTSC1_PR                     (1 << 8)  /* Bit 8:  Port reset */
+#define USBDEV_PRTSC1_HSP                    (1 << 9)  /* Bit 9:  High-speed status */
+                                                       /* Bits 10-13: Reserved OR not used in device mode */
+#define USBDEV_PRTSC1_PIC_SHIFT              (14)      /* Bits 14-15: Port indicator control */
+#define USBDEV_PRTSC1_PIC_MASK               (3 << USBDEV_PRTSC1_PIC_SHIFT)
+#  define USBDEV_PRTSC1_PIC_OFF              (0 << USBDEV_PRTSC1_PIC_SHIFT) /* 00 Port indicators are off */
+#  define USBDEV_PRTSC1_PIC_AMBER            (1 << USBDEV_PRTSC1_PIC_SHIFT) /* 01 amber */
+#  define USBDEV_PRTSC1_PIC_GREEN            (2 << USBDEV_PRTSC1_PIC_SHIFT) /* 10 green */
+#define USBDEV_PRTSC1_PTC_SHIFT              (16)      /* Bits 16-19: 19: Port test control */
+#define USBDEV_PRTSC1_PTC_MASK               (15 << USBDEV_PRTSC1_PTC_SHIFT)
+#  define USBDEV_PRTSC1_PTC_DISABLE          (0 << USBDEV_PRTSC1_PTC_SHIFT) /* TEST_MODE_DISABLE */
+#  define USBDEV_PRTSC1_PTC_JSTATE           (1 << USBDEV_PRTSC1_PTC_SHIFT) /* J_STATE */
+#  define USBDEV_PRTSC1_PTC_KSTATE           (2 << USBDEV_PRTSC1_PTC_SHIFT) /* K_STATE */
+#  define USBDEV_PRTSC1_PTC_SE0              (3 << USBDEV_PRTSC1_PTC_SHIFT) /* SE0 (host)/NAK (device) */
+#  define USBDEV_PRTSC1_PTC_PACKET           (4 << USBDEV_PRTSC1_PTC_SHIFT) /* Packet */
+#  define USBDEV_PRTSC1_PTC_HS               (5 << USBDEV_PRTSC1_PTC_SHIFT) /* FORCE_ENABLE_HS */
+#  define USBDEV_PRTSC1_PTC_FS               (6 << USBDEV_PRTSC1_PTC_SHIFT) /* FORCE_ENABLE_FS */
+                                                       /* Bits 20-22:  Not used in device mode */
+#define USBDEV_PRTSC1_PHCD                   (1 << 23) /* Bit 23: PHY low power suspend - clock disable (PLPSCD) */
+#  define USBDEV_PRTSC1_PFSC                 (1 << 24) /* Bit 24: Port force full speed connect */
+                                                       /* Bit 25: Reserved */
+#define USBDEV_PRTSC1_PSPD_SHIFT             (26)      /* Bits 26-27: Port speed */
+#define USBDEV_PRTSC1_PSPD_MASK              (3 << USBDEV_PRTSC1_PSPD_SHIFT)
+#  define USBDEV_PRTSC1_PSPD_FS              (0 << USBDEV_PRTSC1_PSPD_SHIFT) /* Full-speed */
+#  define USBDEV_PRTSC1_PSPD_HS              (2 << USBDEV_PRTSC1_PSPD_SHIFT) /* High-speed */
+                                                       /* Bits 28-31: Reserved */
+/* Port Status and Control register PRTSC1 -- Host Mode */
+
+#define USBHOST_PRTSC1_CCS                   (1 << 0)  /* Bit 0:  Current connect status */
+#define USBHOST_PRTSC1_CSC                   (1 << 1)  /* Bit 1:  Connect status change */
+#define USBHOST_PRTSC1_PE                    (1 << 2)  /* Bit 2:  Port enable */
+#define USBHOST_PRTSC1_PEC                   (1 << 3)  /* Bit 3:  Port disable/enable change */
+#define USBHOST_PRTSC1_OCA                   (1 << 4)  /* Bit 4:  Over-current active */
+#define USBHOST_PRTSC1_OCC                   (1 << 5)  /* Bit 5:  Over-current change */
+#define USBHOST_PRTSC1_FPR                   (1 << 6)  /* Bit 6:  Force port resume */
+#define USBHOST_PRTSC1_SUSP                  (1 << 7)  /* Bit 7:  Suspend */
+#define USBHOST_PRTSC1_PR                    (1 << 8)  /* Bit 8:  Port reset */
+#define USBHOST_PRTSC1_HSP                   (1 << 9)  /* Bit 9:  High-speed status */
+#define USBHOST_PRTSC1_LS_SHIFT              (10)      /* Bits 10-11: Line status */
+#define USBHOST_PRTSC1_LS_MASK               (3 << USBHOST_PRTSC1_LS_SHIFT)
+#  define USBHOST_PRTSC1_LS_SE0              (0 << USBHOST_PRTSC1_LS_SHIFT) /* SE0 (USB_DP and USB_DM LOW) */
+#  define USBHOST_PRTSC1_LS_JSTATE           (2 << USBHOST_PRTSC1_LS_SHIFT) /* J-state (USB_DP HIGH and USB_DM LOW) */
+#  define USBHOST_PRTSC1_LS_KSTATE           (1 << USBHOST_PRTSC1_LS_SHIFT) /* K-state (USB_DP LOW and USB_DM HIGH) */
+#define USBHOST_PRTSC1_PP                    (1 << 12) /* Bit 12: Port power control */
+                                                       /* Bit 13: Reserved */
+#define USBHOST_PRTSC1_PIC_SHIFT             (14)      /* Bits 14-15: Port indicator control */
+#define USBHOST_PRTSC1_PIC_MASK              (3 << USBHOST_PRTSC1_PIC_SHIFT)
+#  define USBHOST_PRTSC1_PIC_OFF             (0 << USBHOST_PRTSC1_PIC_SHIFT) /* 00 Port indicators are off */
+#  define USBHOST_PRTSC1_PIC_AMBER           (1 << USBHOST_PRTSC1_PIC_SHIFT) /* 01 Amber */
+#  define USBHOST_PRTSC1_PIC_GREEN           (2 << USBHOST_PRTSC1_PIC_SHIFT) /* 10 Green */
+#define USBHOST_PRTSC1_PTC_SHIFT             (16)      /* Bits 16-19: Port test control */
+#define USBHOST_PRTSC1_PTC_MASK              (15 << USBHOST_PRTSC1_PTC_SHIFT)
+#  define USBHOST_PRTSC1_PTC_DISABLE         (0 << USBHOST_PRTSC1_PTC_SHIFT) /* 0000 TEST_MODE_DISABLE */
+#  define USBHOST_PRTSC1_PTC_JSTATE          (1 << USBHOST_PRTSC1_PTC_SHIFT) /* 0001 J_STATE */
+#  define USBHOST_PRTSC1_PTC_KSTATE          (2 << USBHOST_PRTSC1_PTC_SHIFT) /* 0010 K_STATE */
+#  define USBHOST_PRTSC1_PTC_SE0             (3 << USBHOST_PRTSC1_PTC_SHIFT) /* 0011 SE0 (host)/NAK (device) */
+#  define USBHOST_PRTSC1_PTC_PACKET          (4 << USBHOST_PRTSC1_PTC_SHIFT) /* 0100 Packet */
+#  define USBHOST_PRTSC1_PTC_HS              (5 << USBHOST_PRTSC1_PTC_SHIFT) /* 0101 FORCE_ENABLE_HS */
+#  define USBHOST_PRTSC1_PTC_FS              (6 << USBHOST_PRTSC1_PTC_SHIFT) /* 0110 FORCE_ENABLE_FS */
+#  define USBHOST_PRTSC1_PTC_LS              (7 << USBHOST_PRTSC1_PTC_SHIFT) /* 0111 FORCE_ENABLE_LS */
+#define USBHOST_PRTSC1_WKCN                  (1 << 20) /* Bit 20: Wake on connect enable (WKCNNT_E) */
+#define USBHOST_PRTSC1_WKDC                  (1 << 21) /* Bit 21: Wake on disconnect enable (WKDSCNNT_E) */
+#define USBHOST_PRTSC1_WKOC                  (1 << 22) /* Bit 22: Wake on over-current enable (WKOC_E) */
+#define USBHOST_PRTSC1_PHCD                  (1 << 23) /* Bit 23: PHY low power suspend - clock disable (PLPSCD) */
+#define USBHOST_PRTSC1_PFSC                  (1 << 24) /* Bit 24: Port force full speed connect */
+                                                       /* Bit 25: Reserved */
+#define USBHOST_PRTSC1_PSPD_SHIFT            (26)      /* Bits 26-27: Port speed */
+#define USBHOST_PRTSC1_PSPD_MASK             (3 << USBHOST_PRTSC1_PSPD_SHIFT)
+#  define USBHOST_PRTSC1_PSPD_FS             (0 << USBHOST_PRTSC1_PSPD_SHIFT) /* Full-speed */
+#  define USBHOST_PRTSC1_PSPD_LS             (1 << USBHOST_PRTSC1_PSPD_SHIFT) /* Low-speed */
+#  define USBHOST_PRTSC1_PSPD_HS             (2 << USBHOST_PRTSC1_PSPD_SHIFT) /* High-speed */
+                                                       /* Bits 28-31: Reserved */
+/* OTG Status and Control register */
+/* OTG controls */
+
+#define USBOTG_OTGSC_VD                      (1 << 0)  /* Bit 0:  VBUS_Discharge */
+#define USBOTG_OTGSC_VC                      (1 << 1)  /* Bit 1:  VBUS_Charge */
+#define USBOTG_OTGSC_HAAR                    (1 << 2)  /* Bit 2:  Hardware assist auto_reset */
+#define USBOTG_OTGSC_OT                      (1 << 3)  /* Bit 3:  OTG termination */
+#define USBOTG_OTGSC_DP                      (1 << 4)  /* Bit 4:  Data pulsing */
+#define USBOTG_OTGSC_IDPU                    (1 << 5)  /* Bit 5:  ID pull-up */
+#define USBOTG_OTGSC_HADP                    (1 << 6)  /* Bit 6:  Hardware assist data pulse */
+#define USBOTG_OTGSC_HABA                    (1 << 7)  /* Bit 7:  Hardware assist B-disconnect to A-connect */
+
+/* OTG status inputs */
+
+#define USBOTG_OTGSC_ID                      (1 << 8)  /* Bit 8:  USB ID */
+#define USBOTG_OTGSC_AVV                     (1 << 9)  /* Bit 9:  A-VBUS valid */
+#define USBOTG_OTGSC_ASV                     (1 << 10) /* Bit 10: A-session valid */
+#define USBOTG_OTGSC_BSV                     (1 << 11) /* Bit 11: B-session valid */
+#define USBOTG_OTGSC_BSE                     (1 << 12) /* Bit 12: B-session end */
+#define USBOTG_OTGSC_1MST                    (1 << 13) /* Bit 13: 1 millisecond timer toggle */
+#define USBOTG_OTGSC_DPS                     (1 << 14) /* Bit 14: Data bus pulsing status */
+                                                       /* Bit 15: Reserved *.
+/* OTG interrupt status */
+
+#define USBOTG_OTGSC_IDIS                    (1 << 16) /* Bit 16: USB ID interrupt status */
+#define USBOTG_OTGSC_AVVIS                   (1 << 17) /* Bit 17: A-VBUS valid interrupt status */
+#define USBOTG_OTGSC_ASVIS                   (1 << 18) /* Bit 18: A-Session valid interrupt status */
+#define USBOTG_OTGSC_BSVIS                   (1 << 19) /* Bit 19: B-Session valid interrupt status */
+#define USBOTG_OTGSC_BSEIS                   (1 << 20) /* Bit 20: B-Session end interrupt status */
+#define USBOTG_OTGSC_MS1S                    (1 << 21) /* Bit 21: 1 millisecond timer interrupt status */
+#define USBOTG_OTGSC_DPIS                    (1 << 22) /* Bit 22: Data pulse interrupt status */
+                                                       /* Bit 23: Reserved */
+/* OTG interrupt enable */
+
+#define USBOTG_OTGSC_IDIE                    (1 << 24) /* Bit 24: USB ID interrupt enable */
+#define USBOTG_OTGSC_AVVIE                   (1 << 25) /* Bit 25: A-VBUS valid interrupt enable */
+#define USBOTG_OTGSC_ASVIE                   (1 << 26) /* Bit 26: A-session valid interrupt enable */
+#define USBOTG_OTGSC_BSVIE                   (1 << 27) /* Bit 27: B-session valid interrupt enable */
+#define USBOTG_OTGSC_BSEIE                   (1 << 28) /* Bit 28: B-session end interrupt enable */
+#define USBOTG_OTGSC_MS1E                    (1 << 29) /* Bit 29: 1 millisecond timer interrupt enable */
+#define USBOTG_OTGSC_DPIE                    (1 << 30) /* Bit 30: Data pulse interrupt enable */
+                                                       /* Bit 31: Reserved */
+/* USB Mode register USBMODE -- Device Mode */
+
+#define USBDEV_USBMODE_CM_SHIFT              (0)       /* Bits 0-1: Controller mode */
+#define USBDEV_USBMODE_CM_MASK               (3 << USBDEV_USBMODE_CM_SHIFT)
+#  define USBDEV_USBMODE_CM_IDLE             (0 << USBDEV_USBMODE_CM_SHIFT) /* Idle */
+#  define USBDEV_USBMODE_CM_DEVICE           (2 << USBDEV_USBMODE_CM_SHIFT) /* Device controller */
+#  define USBDEV_USBMODE_CM_HOST             (3 << USBDEV_USBMODE_CM_SHIFT) /* Host controller */
+#define USBDEV_USBMODE_ES                    (1 << 2)  /* Bit 2:  Endian select */
+#define USBDEV_USBMODE_SLOM                  (1 << 3)  /* Bit 3:  Setup Lockout mode */
+#define USBDEV_USBMODE_SDIS                  (1 << 4)  /* Bit 4:  Stream disable mode */
+                                                       /* Bits 5-31:  Reserved OR not used in device mode */
+
+/* USB Mode register USBMODE -- Host Mode */
+
+#define USBHOST_USBMODE_CM_SHIFT             (0)       /* Bits 0-1: Controller mode */
+#define USBHOST_USBMODE_CM_MASK              (3 << USBHOST_USBMODE_CM_SHIFT)
+#  define USBHOST_USBMODE_CMIDLE             (0 << USBHOST_USBMODE_CM_SHIFT) /* Idle */
+#  define USBHOST_USBMODE_CMDEVICE           (2 << USBHOST_USBMODE_CM_SHIFT) /* Device controller */
+#  define USBHOST_USBMODE_CMHOST             (3 << USBHOST_USBMODE_CM_SHIFT) /* Host controller */
+#define USBHOST_USBMODE_ES                   (1 << 2)  /* Bit 2:  Endian select */
+                                                       /* Bit 3:  Not used in host mode */
+#define USBHOST_USBMODE_SDIS                 (1 << 4)  /* Bit 4:  Stream disable mode */
+#define USBHOST_USBMODE_VBPS                 (1 << 5)  /* Bit 5:  VBUS power select */
+                                                       /* Bits 6-31: Reserved */
+/* Device endpoint registers */
+
+/* USB Endpoint Setup Status register ENDPTSETUPSTAT */
+
+#define USBDEV_ENDPTSETSTAT_STAT(n)          (1 << (n))
+#define USBDEV_ENDPTSETSTAT_STAT0            (1 << 0)  /* Bit 0:  Setup EP status for logical EP 0 */
+#define USBDEV_ENDPTSETSTAT_STAT1            (1 << 1)  /* Bit 1:  Setup EP status for logical EP 1 */
+#define USBDEV_ENDPTSETSTAT_STAT2            (1 << 2)  /* Bit 2:  Setup EP status for logical EP 2 */
+#define USBDEV_ENDPTSETSTAT_STAT3            (1 << 3)  /* Bit 3:  Setup EP status for logical EP 3 */
+#define USBDEV_ENDPTSETSTAT_STAT4            (1 << 4)  /* Bit 4:  Setup EP status for logical EP 4 */
+#define USBDEV_ENDPTSETSTAT_STAT5            (1 << 5)  /* Bit 5:  Setup EP status for logical EP 5 */
+                                                       /* Bits 6-31: Reserved */
+/* USB Endpoint Prime register ENDPTPRIME */
+
+#define USBDEV_ENDPTPRIM_PERB(n)             (1 << (n))
+#define USBDEV_ENDPTPRIM_PERB0               (1 << 0)  /* Bit 0:  Prime EP recv buffer for physical OUT EP 0 */
+#define USBDEV_ENDPTPRIM_PERB1               (1 << 1)  /* Bit 1:  Prime EP recv buffer for physical OUT EP 1 */
+#define USBDEV_ENDPTPRIM_PERB2               (1 << 2)  /* Bit 2:  Prime EP recv buffer for physical OUT EP 2 */
+#define USBDEV_ENDPTPRIM_PERB3               (1 << 3)  /* Bit 3:  Prime EP recv buffer for physical OUT EP 3 */
+#define USBDEV_ENDPTPRIM_PERB4               (1 << 4)  /* Bit 4:  Prime EP recv buffer for physical OUT EP 4 */
+#define USBDEV_ENDPTPRIM_PERB5               (1 << 5)  /* Bit 5:  Prime EP recv buffer for physical OUT EP 5 */
+                                                       /* Bits 6-15: Reserved */
+#define USBDEV_ENDPTPRIM_PETB(n)             (1 << ((n) + 16))
+#define USBDEV_ENDPTPRIM_PETB0               (1 << 16) /* Bit 16: Prime EP xmt buffer for physical IN EP 0 */
+#define USBDEV_ENDPTPRIM_PETB1               (1 << 17) /* Bit 17: Prime EP xmt buffer for physical IN EP 1 */
+#define USBDEV_ENDPTPRIM_PETB2               (1 << 18) /* Bit 18: Prime EP xmt buffer for physical IN EP 2 */
+#define USBDEV_ENDPTPRIM_PETB3               (1 << 19) /* Bit 19: Prime EP xmt buffer for physical IN EP 3 */
+#define USBDEV_ENDPTPRIM_PETB4               (1 << 20) /* Bit 20: Prime EP xmt buffer for physical IN EP 4 */
+#define USBDEV_ENDPTPRIM_PETB5               (1 << 21) /* Bit 21: Prime EP xmt buffer for physical IN EP 5 */
+                                                       /* Bits 22-31: Reserved */
+/* USB Endpoint Flush register ENDPTFLUSH */
+
+#define USBDEV_ENDPTFLUSH_FERB(n)            (1 << (n))
+#define USBDEV_ENDPTFLUSH_FERB0              (1 << 0)  /* Bit 0:  Flush EP recv buffer for physical OUT EP 0 */
+#define USBDEV_ENDPTFLUSH_FERB1              (1 << 1)  /* Bit 1:  Flush EP recv buffer for physical OUT EP 1 */
+#define USBDEV_ENDPTFLUSH_FERB2              (1 << 2)  /* Bit 2:  Flush EP recv buffer for physical OUT EP 2 */
+#define USBDEV_ENDPTFLUSH_FERB3              (1 << 3)  /* Bit 3:  Flush EP recv buffer for physical OUT EP 3 */
+#define USBDEV_ENDPTFLUSH_FERB4              (1 << 4)  /* Bit 4:  Flush EP recv buffer for physical OUT EP 4 */
+#define USBDEV_ENDPTFLUSH_FERB5              (1 << 5)  /* Bit 5:  Flush EP recv buffer for physical OUT EP 5 */
+                                                       /* Bits 6-15: Reserved */
+#define USBDEV_ENDPTFLUSH_FETB(n)            (1 << ((n) + 16))
+#define USBDEV_ENDPTFLUSH_FETB0              (1 << 16) /* Bit 16: Flush EP xmt buffer for physical IN EP 0 */
+#define USBDEV_ENDPTFLUSH_FETB1              (1 << 17) /* Bit 17: Flush EP xmt buffer for physical IN EP 1 */
+#define USBDEV_ENDPTFLUSH_FETB2              (1 << 18) /* Bit 18: Flush EP xmt buffer for physical IN EP 2 */
+#define USBDEV_ENDPTFLUSH_FETB3              (1 << 19) /* Bit 19: Flush EP xmt buffer for physical IN EP 3 */
+#define USBDEV_ENDPTFLUSH_FETB4              (1 << 20) /* Bit 20: Flush EP xmt buffer for physical IN EP 4 */
+#define USBDEV_ENDPTFLUSH_FETB5              (1 << 21) /* Bit 21: Flush EP xmt buffer for physical IN EP 5 */
+                                                       /* Bits 22-31: Reserved */
+/* USB Endpoint Status register ENDPTSTATUS */
+
+#define USBDEV_ENDPTSTATUS_ERBR(n)           (1 << (n))
+#define USBDEV_ENDPTSTATUS_ERBR0             (1 << 0)  /* Bit 0:  EP recv buffer ready for physical OUT EP 0 */
+#define USBDEV_ENDPTSTATUS_ERBR1             (1 << 1)  /* Bit 1:  EP recv buffer ready for physical OUT EP 1 */
+#define USBDEV_ENDPTSTATUS_ERBR2             (1 << 2)  /* Bit 2:  EP recv buffer ready for physical OUT EP 2 */
+#define USBDEV_ENDPTSTATUS_ERBR3             (1 << 3)  /* Bit 3:  EP recv buffer ready for physical OUT EP 3 */
+#define USBDEV_ENDPTSTATUS_ERBR4             (1 << 4)  /* Bit 4:  EP recv buffer ready for physical OUT EP 4 */
+#define USBDEV_ENDPTSTATUS_ERBR5             (1 << 5)  /* Bit 5:  EP recv buffer ready for physical OUT EP 5 */
+                                                       /* Bits 6-15: Reserved */
+#define USBDEV_ENDPTSTATUS_ETBR(n)           (1 << ((n) + 16))
+#define USBDEV_ENDPTSTATUS_ETBR0             (1 << 16) /* Bit 16: EP xmt buffer ready for physical IN EP 0 */
+#define USBDEV_ENDPTSTATUS_ETBR1             (1 << 17) /* Bit 17: EP xmt buffer ready for physical IN EP 1 */
+#define USBDEV_ENDPTSTATUS_ETBR2             (1 << 18) /* Bit 18: EP xmt buffer ready for physical IN EP 2 */
+#define USBDEV_ENDPTSTATUS_ETBR3             (1 << 19) /* Bit 19: EP xmt buffer ready for physical IN EP 3 */
+#define USBDEV_ENDPTSTATUS_ETBR4             (1 << 20) /* Bit 20: EP xmt buffer ready for physical IN EP 4 */
+#define USBDEV_ENDPTSTATUS_ETBR5             (1 << 21) /* Bit 21: EP xmt buffer ready for physical IN EP 5 */
+                                                       /* Bits 22-31: Reserved */
+/* USB Endpoint Complete register ENDPTCOMPLETE */
+
+#define USBDEV_ENDPTCOMPLETE_ERCE(n)         (1 << (n))
+#define USBDEV_ENDPTCOMPLETE_ERCE0           (1 << 0)  /* Bit 0:  EP recv complete event for physical OUT EP 0 */
+#define USBDEV_ENDPTCOMPLETE_ERCE1           (1 << 1)  /* Bit 1:  EP recv complete event for physical OUT EP 1 */
+#define USBDEV_ENDPTCOMPLETE_ERCE2           (1 << 2)  /* Bit 2:  EP recv complete event for physical OUT EP 2 */
+#define USBDEV_ENDPTCOMPLETE_ERCE3           (1 << 3)  /* Bit 3:  EP recv complete event for physical OUT EP 3 */
+#define USBDEV_ENDPTCOMPLETE_ERCE4           (1 << 4)  /* Bit 4:  EP recv complete event for physical OUT EP 4 */
+#define USBDEV_ENDPTCOMPLETE_ERCE5           (1 << 5)  /* Bit 4:  EP recv complete event for physical OUT EP 5 */
+                                                       /* Bits 6-15: Reserved */
+#define USBDEV_ENDPTCOMPLETE_ETCE(n)         (1 << ((n) + 16))
+#define USBDEV_ENDPTCOMPLETE_ETCE0           (1 << 16) /* Bit 16: EP xmt complete event for physical IN EP 0 */
+#define USBDEV_ENDPTCOMPLETE_ETCE1           (1 << 17) /* Bit 17: EP xmt complete event for physical IN EP 1 */
+#define USBDEV_ENDPTCOMPLETE_ETCE2           (1 << 18) /* Bit 18: EP xmt complete event for physical IN EP 2 */
+#define USBDEV_ENDPTCOMPLETE_ETCE3           (1 << 19) /* Bit 19: EP xmt complete event for physical IN EP 3 */
+#define USBDEV_ENDPTCOMPLETE_ETCE4           (1 << 20) /* Bit 20: EP xmt complete event for physical IN EP 4 */
+#define USBDEV_ENDPTCOMPLETE_ETCE5           (1 << 21) /* Bit 21: EP xmt complete event for physical IN EP 5 */
+                                                       /* Bits 22-31: Reserved */
+/* USB Endpoint 0 Control register ENDPTCTRL0 */
+
+#define USBDEV_ENDPTCTRL0_RXS                (1 << 0)  /* Bit 0:  Rx endpoint stall */
+                                                       /* Bit 1:  Reserved */
+#define USBDEV_ENDPTCTRL0_RXT_SHIFT          (2)       /* Bits 2-3: Endpoint type */
+#define USBDEV_ENDPTCTR0L_RXT_MASK           (3 << USBDEV_ENDPTCTRL0_RXT_SHIFT)
+#  define USBDEV_ENDPTCTRL0_RXT_CTRL         (0 << USBDEV_ENDPTCTRL0_RXT_SHIFT) /* Control */
+                                                       /* Bits 4-6: Reserved */
+#define USBDEV_ENDPTCTRL0_RXE                (1 << 7)  /* Bit 7:  Rx endpoint enable */
+                                                       /* Bits 8-15: Reserved */
+#define USBDEV_ENDPTCTRL0_TXS                (1 << 16) /* Bit 16: Tx endpoint stall */
+                                                       /* Bit 17: Reserved */
+#define USBDEV_ENDPTCTRL0_TXT_SHIFT          (18)      /* Bits 18-19: Tx endpoint type */
+#define USBDEV_ENDPTCTRL0_TXT_MASK           (3 << USBDEV_ENDPTCTRL0_TXT_SHIFT)
+#  define USBDEV_ENDPTCTRL0_TXT_CTRL         (0 << USBDEV_ENDPTCTRL0_TXT_SHIFT) /* Control */
+#define USBDEV_ENDPTCTRL0_TXE                (1 << 23) /* Bit 23: Tx endpoint enable */
+                                                       /* Bits 24-31: Reserved */
+/* USB Endpoint 1-3 control registers ENDPTCTRL1-ENDPPTCTRL5 */
+
+#define USBDEV_ENDPTCTRL_RXS                 (1 << 0)  /* Bit 0:  Rx endpoint stall */
+                                                       /* Bit 1:  Reserved */
+#define USBDEV_ENDPTCTRL_RXT_SHIFT           (2)       /* Bits 2-3: Endpoint type */
+#define USBDEV_ENDPTCTRL_RXT_MASK            (3 << USBDEV_ENDPTCTRL_RXT_SHIFT)
+#  define USBDEV_ENDPTCTRL_RXT_CTRL          (0 << USBDEV_ENDPTCTRL_RXT_SHIFT) /* Control */
+#  define USBDEV_ENDPTCTRL_RXT_ISOC          (1 << USBDEV_ENDPTCTRL_RXT_SHIFT) /* Isochronous */
+#  define USBDEV_ENDPTCTRL_RXT_BULK          (2 << USBDEV_ENDPTCTRL_RXT_SHIFT) /* Bulk */
+#  define USBDEV_ENDPTCTRL_RXT_INTR          (3 << USBDEV_ENDPTCTRL_RXT_SHIFT) /* Interrupt */
+                                                       /* Bit 4:  Reserved */
+#define USBDEV_ENDPTCTRL_RXI                 (1 << 5)  /* Bit 5:  Rx data toggle inhibit */
+#define USBDEV_ENDPTCTRL_RXR                 (1 << 6)  /* Bit 6:  Rx data toggle reset */
+#define USBDEV_ENDPTCTRL_RXE                 (1 << 7)  /* Bit 7:  Rx endpoint enable */
+                                                       /* Bits 8-15: Reserved */
+#define USBDEV_ENDPTCTRL_TXS                 (1 << 16) /* Bit 16: Tx endpoint stall */
+                                                       /* Bit 17: Reserved */
+#define USBDEV_ENDPTCTRL_TXT_SHIFT           (18)      /* Bits 18-19: Tx endpoint type */
+#define USBDEV_ENDPTCTRL_TXT_MASK            (3 << USBDEV_ENDPTCTRL_TXT_SHIFT)
+#  define USBDEV_ENDPTCTRL_TXT_CTRL          (0 << USBDEV_ENDPTCTRL_TXT_SHIFT) /* Control */
+#  define USBDEV_ENDPTCTRL_TXT_ISOC          (1 << USBDEV_ENDPTCTRL_TXT_SHIFT) /* Isochronous */
+#  define USBDEV_ENDPTCTRL_TXT_BULK          (2 << USBDEV_ENDPTCTRL_TXT_SHIFT) /* Bulk */
+#  define USBDEV_ENDPTCTRL_TXT_INTR          (3 << USBDEV_ENDPTCTRL_TXT_SHIFT) /* Interrupt */
+                                                       /* Bit 20: Reserved */
+#define USBDEV_ENDPTCTRL_TXI                 (1 << 21) /* Bit 21: Tx data toggle inhibit */
+#define USBDEV_ENDPTCTRL_TXR                 (1 << 22) /* Bit 22: Tx data toggle reset */
+#define USBDEV_ENDPTCTRL_TXE                 (1 << 23) /* Bit 23: Tx endpoint enable */
+                                                       /* Bits 24-31: Reserved */
+
+/************************************************************************************************
+ * Public Types
+ ************************************************************************************************/
+
+/************************************************************************************************
+ * Public Data
+ ************************************************************************************************/
+
+/************************************************************************************************
+ * Public Functions
+ ************************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_USB0_H */
diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_wwdt.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_wwdt.h
new file mode 100644
index 000000000..df9d172c7
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_wwdt.h
@@ -0,0 +1,111 @@
+/************************************************************************************
+ * arch/arm/src/lpc43xx/lpc43_wwdt.h
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_WWDT_H
+#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_WWDT_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Register offsets *****************************************************************/
+
+#define LPC43_WWDT_MOD_OFFSET       0x0000  /* Watchdog mode register */
+#define LPC43_WWDT_TC_OFFSET        0x0004  /* Watchdog timer constant register */
+#define LPC43_WWDT_FEED_OFFSET      0x0008  /* Watchdog feed sequence register */
+#define LPC43_WWDT_TV_OFFSET        0x000c  /* Watchdog timer value register */
+#define LPC43_WWDT_WARNINT_OFFSET   0x0014  /* Watchdog warning interrupt register */
+#define LPC43_WWDT_WINDOW_OFFSET    0x0018  /* Watchdog timer window register */
+
+/* Register addresses ***************************************************************/
+
+#define LPC43_WWDT_MOD              (LPC43_WWDT_BASE+LPC43_WWDT_MOD_OFFSET)
+#define LPC43_WWDT_TC               (LPC43_WWDT_BASE+LPC43_WWDT_TC_OFFSET)
+#define LPC43_WWDT_FEED             (LPC43_WWDT_BASE+LPC43_WWDT_FEED_OFFSET)
+#define LPC43_WWDT_TV               (LPC43_WWDT_BASE+LPC43_WWDT_TV_OFFSET)
+#define LPC43_WWDT_WDCLKSEL         (LPC43_WWDT_BASE+LPC43_WWDT_WDCLKSEL_OFFSET)
+#define LPC43_WWDT_WARNINT          (LPC43_WWDT_BASE+LPC43_WWDT_WARNINT_OFFSET)
+#define LPC43_WWDT_WINDOW           (LPC43_WWDT_BASE+LPC43_WWDT_WINDOW_OFFSET)
+
+/* Register bit definitions *********************************************************/
+
+/* Watchdog mode register */
+
+#define WWDT_MOD_WDEN               (1 << 0)   /* Bit 0: Watchdog enable */
+#define WWDT_MOD_WDRESET            (1 << 1)   /* Bit 1: Watchdog reset enable */
+#define WWDT_MOD_WDTOF              (1 << 2)   /* Bit 2: Watchdog time-out */
+#define WWDT_MOD_WDINT              (1 << 3)   /* Bit 3: Watchdog interrupt */
+#define WWDT_MOD_WDPROTECT          (1 << 4)   /* Bit 4: Watchdog update mode */
+                                               /* Bits 5-31: Reserved */
+/* Watchdog timer constant register */
+
+#define WWDT_TC_MASK                0x00ffffff /* Bits 0-23: Watchdog time-out value */
+                                               /* Bits 24-31: Reserved */
+/* Watchdog feed sequence register  */
+
+#define WWDT_FEED_MASK              0xff      /* Bits 0-7: Feed value: 0xaa followed by 0x55 */
+                                              /* Bits 14-31: Reserved */
+/* Watchdog timer value register */
+
+#define WWDT_TV_MASK                0x00ffffff /* Bits 0-23: Counter timer value */
+                                               /* Bits 24-31: Reserved */
+/* Watchdog warning interrupt register */
+
+#define WWDT_WARNINT_MASK           0x03ff     /* Bits 0-9: Watchdog warning compare value */
+                                               /* Bits 10-31: Reserved */
+/* Watchdog timer window register */
+
+#define WWDT_WINDOW_MASK            0x00ffffff /* Bits 0-23: Watchdog window value */
+                                               /* Bits 24-31: Reserved */
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_WWDT_H */
diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_adc.c b/nuttx/arch/arm/src/lpc43xx/lpc43_adc.c
new file mode 100644
index 000000000..d9165ba75
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/lpc43_adc.c
@@ -0,0 +1,283 @@
+/************************************************************************************
+ * arch/arm/src/lpc43xx/lpc43_adc.c
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Ported from from the LPC17 version:
+ *
+ *   Copyright (C) 2011 Li Zhuoyi. All rights reserved.
+ *   Author: Li Zhuoyi <lzyy.cn@gmail.com>
+ *   History: 0.1 2011-08-05 initial version
+ * 
+ * This file is a part of NuttX:
+ *
+ *   Copyright (C) 2010-2012 Gregory Nutt. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdio.h>
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <semaphore.h>
+#include <errno.h>
+#include <debug.h>
+
+#include <arch/board/board.h>
+#include <nuttx/arch.h>
+#include <nuttx/analog/adc.h>
+
+#include "up_internal.h"
+#include "up_arch.h"
+
+#include "chip.h"
+#include "lpc43_syscon.h"
+#include "lpc43_pinconn.h"
+#include "lpc43_adc.h"
+
+#if defined(CONFIG_LPC43_ADC)
+
+#ifndef CONFIG_ADC0_MASK
+#define CONFIG_ADC0_MASK     0x01
+#endif
+#ifndef CONFIG_ADC0_SPS
+#define CONFIG_ADC0_SPS      1000
+#endif
+#ifndef CONFIG_ADC0_AVERAGE
+#define CONFIG_ADC0_AVERAGE  200
+#endif
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+struct up_dev_s
+{
+  uint8_t mask;
+  uint32_t sps;
+  int irq;
+  int32_t buf[8];
+  uint8_t count[8];
+};
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/* ADC methods */
+
+static void adc_reset(FAR struct adc_dev_s *dev);
+static int  adc_setup(FAR struct adc_dev_s *dev);
+static void adc_shutdown(FAR struct adc_dev_s *dev);
+static void adc_rxint(FAR struct adc_dev_s *dev, bool enable);
+static int  adc_ioctl(FAR struct adc_dev_s *dev, int cmd, unsigned long arg);
+static int  adc_interrupt(int irq, void *context);
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static const struct adc_ops_s g_adcops =
+{
+  .ao_reset =adc_reset,
+  .ao_setup = adc_setup,
+  .ao_shutdown = adc_shutdown,
+  .ao_rxint = adc_rxint,
+  .ao_ioctl = adc_ioctl,
+};
+
+static struct up_dev_s g_adcpriv =
+{
+  .sps  = CONFIG_ADC0_SPS,
+  .mask = CONFIG_ADC0_MASK,
+  .irq  = LPC43_IRQ_ADC,
+};
+
+static struct adc_dev_s g_adcdev =
+{
+  .ad_ops = &g_adcops,
+  .ad_priv= &g_adcpriv,
+};
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/* Reset the ADC device.  Called early to initialize the hardware. This
+ * is called, before ao_setup() and on error conditions.
+ */
+
+static void adc_reset(FAR struct adc_dev_s *dev)
+{
+  irqstate_t flags;
+  uint32_t regval;
+  FAR struct up_dev_s *priv = (FAR struct up_dev_s *)dev->ad_priv;
+
+  flags = irqsave();
+
+  regval  = getreg32(LPC43_SYSCON_PCONP);
+  regval |= SYSCON_PCONP_PCADC;
+  putreg32(regval, LPC43_SYSCON_PCONP);
+
+  putreg32(ADC_CR_PDN,LPC43_ADC_CR);
+
+  regval  = getreg32(LPC43_SYSCON_PCLKSEL0);
+  regval &= ~SYSCON_PCLKSEL0_ADC_MASK;
+  regval |= (SYSCON_PCLKSEL_CCLK8 << SYSCON_PCLKSEL0_ADC_SHIFT);
+  putreg32(regval, LPC43_SYSCON_PCLKSEL0);
+
+  uint32_t clkdiv=LPC43_CCLK/8/65/priv->sps;
+  clkdiv<<=8;
+  clkdiv&=0xff00;
+  putreg32(ADC_CR_PDN|ADC_CR_BURST|clkdiv|priv->mask,LPC43_ADC_CR);
+
+  if(priv->mask&0x01)
+    lpc43_configgpio(GPIO_AD0p0);
+  else if(priv->mask&0x02)
+    lpc43_configgpio(GPIO_AD0p1);
+  else if(priv->mask&0x04)
+    lpc43_configgpio(GPIO_AD0p2);
+  else if(priv->mask&0x08)
+    lpc43_configgpio(GPIO_AD0p3);
+  else if(priv->mask&0x10)
+    lpc43_configgpio(GPIO_AD0p4);
+  else if(priv->mask&0x20)
+    lpc43_configgpio(GPIO_AD0p5);
+  else if(priv->mask&0x40)
+    lpc43_configgpio(GPIO_AD0p6);
+  else if(priv->mask&0x80)
+    lpc43_configgpio(GPIO_AD0p7);
+    
+  irqrestore(flags);
+}
+
+/* Configure the ADC. This method is called the first time that the ADC
+ * device is opened.  This will occur when the port is first opened.
+ * This setup includes configuring and attaching ADC interrupts.  Interrupts
+ * are all disabled upon return.
+ */
+
+static int  adc_setup(FAR struct adc_dev_s *dev)
+{
+  int i;
+  FAR struct up_dev_s *priv = (FAR struct up_dev_s *)dev->ad_priv;
+  int ret = irq_attach(priv->irq, adc_interrupt);
+  if (ret == OK)
+    {
+      for (i = 0; i < 8; i++)
+        {
+          priv->buf[i]=0;
+          priv->count[i]=0;
+        }
+      up_enable_irq(priv->irq);
+    }
+  return ret;
+}
+
+/* Disable the ADC.  This method is called when the ADC device is closed.
+ * This method reverses the operation the setup method.
+ */
+
+static void adc_shutdown(FAR struct adc_dev_s *dev)
+{
+  FAR struct up_dev_s *priv = (FAR struct up_dev_s *)dev->ad_priv;
+  up_disable_irq(priv->irq);
+  irq_detach(priv->irq);
+}
+
+/* Call to enable or disable RX interrupts */
+
+static void adc_rxint(FAR struct adc_dev_s *dev, bool enable)
+{
+  FAR struct up_dev_s *priv = (FAR struct up_dev_s *)dev->ad_priv;
+  if (enable)
+    putreg32(ADC_INTEN_GLOBAL, LPC43_ADC_INTEN);
+  else
+    putreg32(0x00, LPC43_ADC_INTEN);
+}
+
+/* All ioctl calls will be routed through this method */
+
+static int  adc_ioctl(FAR struct adc_dev_s *dev, int cmd, unsigned long arg)
+{
+  dbg("Fix me:Not Implemented\n");
+  return 0;
+}
+
+static int adc_interrupt(int irq, void *context)
+{
+  uint32_t regval;
+  FAR struct up_dev_s *priv = (FAR struct up_dev_s *)g_adcdev.ad_priv;
+  unsigned char ch;
+  int32_t value;
+    
+  regval = getreg32(LPC43_ADC_GDR);
+  ch = (regval >> 24) & 0x07;
+  priv->buf[ch] += regval & 0xfff0;
+  priv->count[ch]++;
+  if (priv->count[ch] >= CONFIG_ADC0_AVERAGE)
+    {
+      value = priv->buf[ch] / priv->count[ch];
+      value <<= 15;
+      adc_receive(&g_adcdev,ch,value);
+      priv->buf[ch] = 0;
+      priv->count[ch] = 0;
+    }
+  return OK;
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: stm32_adcinitialize
+ *
+ * Description:
+ *   Initialize the adc
+ *
+ * Returned Value:
+ *   Valid can device structure reference on succcess; a NULL on failure
+ *
+ ****************************************************************************/
+
+FAR struct adc_dev_s *lpc43_adcinitialize(void)
+{
+  return &g_adcdev;
+}
+#endif
+
diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_adc.h b/nuttx/arch/arm/src/lpc43xx/lpc43_adc.h
new file mode 100644
index 000000000..ae8cef6c1
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/lpc43_adc.h
@@ -0,0 +1,95 @@
+/****************************************************************************
+ * arch/arm/src/lpc43xx/lpc43_adc.h
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LPC43XX_LPC43_ADC_H
+#define __ARCH_ARM_SRC_LPC43XX_LPC43_ADC_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/analog/adc.h>
+#include "chip/lpc43_adc.h"
+
+#ifdef CONFIG_LPC43_ADC
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C" {
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: lpc43_adcinitialize
+ *
+ * Description:
+ *   Initialize the adc
+ *
+ * Returned Value:
+ *   Valid can device structure reference on succcess; a NULL on failure
+ *
+ ****************************************************************************/
+
+FAR struct adc_dev_s *lpc43_adcinitialize(void);
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* CONFIG_LPC43_ADC */
+#endif /* __ARCH_ARM_SRC_LPC43XX_LPC43_ADC_H */
diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_allocateheap.c b/nuttx/arch/arm/src/lpc43xx/lpc43_allocateheap.c
new file mode 100644
index 000000000..7912f6c6e
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/lpc43_allocateheap.c
@@ -0,0 +1,290 @@
+/****************************************************************************
+ * arch/arm/src/lpc43xx/lpc43_allocateheap.c
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+#include <debug.h>
+
+#include <nuttx/arch.h>
+#include <nuttx/mm.h>
+#include <arch/board/board.h>
+
+#include "chip.h"
+#include "up_arch.h"
+#include "up_internal.h"
+
+#include "lpc43_emacram.h"
+#include "lpc43_usbram.h"
+
+/****************************************************************************
+ * Private Definitions
+ ****************************************************************************/
+/* Get customizations for each supported chip.
+ *
+ * SRAM Resources
+ * --------------------- -------- ------- ------- ------- ------- -------
+ * Local SRAM            LPC4310  LPC4320 LPC4330 LPC4350 LPC4353 LPC4357
+ * --------------------- -------- ------- ------- ------- ------- -------
+ * BANK 0 (0x1000 0000)     96Kb    96Kb   128Kb   128Kb    32Kb    32Kb
+ * BANK 1 (0x1008 0000)     40Kb    40Kb    72Kb    72Kb    40Kb    40Kb
+ * --------------------- -------- ------- ------- ------- ------- -------
+ * SUBTOTAL                136Kb   136Kb   200Kb   200Kb    72Kb    72Kb
+ * --------------------- -------- ------- ------- ------- ------- -------
+ * AHB SRAM              LPC4310  LPC4320 LPC4330 LPC4350 LPC4353 LPC4357
+ * --------------------- -------- ------- ------- ------- ------- -------
+ * BANK 0 (0x2000 0000)     16Kb    48Kb   48Kb    48Kb     48Kb    48Kb
+ * BANK 1 (0x2000 8000)             NOTE 1 NOTE 1  NOTE 1  NOTE 1  NOTE 1
+ * BANK 2 (0x2000 c000)     16Kb    16Kb   16Kb    16Kb    16Kb    16Kb
+ * --------------------- -------- ------- ------- ------- ------- -------
+ * SUBTOTAL                 32Kb    64Kb   64Kb    64Kb     64Kb    64Kb
+ * --------------------- -------- ------- ------- ------- ------- -------
+ * TOTAL                   168Kb   200Kb  264Kb   264Kb    136Kb   136Kb
+ * --------------------- -------- ------- ------- ------- ------- -------
+ *
+ * --------------------- -------- ------- ------- ------- ------- -------
+ * FLASH                 LPC4310  LPC4320 LPC4330 LPC4350 LPC4353 LPC4357
+ * --------------------- -------- ------- ------- ------- ------- -------
+ * BANK A (0x1a00 0000)                                    256Kb   512Kb
+ * BANK B (0x1b00 8000)                                    256Kb   512Kb
+ * --------------------- -------- ------- ------- ------- ------- -------
+ * TOTAL                   None    None    None    None    512Kb  1024Kb
+ * --------------------- -------- ------- ------- ------- ------- -------
+ *
+ * NOTE 1: The 64Kb of AHB of SRAM on the LPC4350/30/20 span all AHB SRAM
+ * banks but are treated as two banks of 48 an 16Kb by the NuttX memory
+ * manager.  This gives some symmetry to all of the members of the family.
+ */
+
+/* Configuration ************************************************************/
+
+/* Two configurations are supported:
+ *
+ * Configuration A:
+ *   Program memory     = FLASH
+ *   Data memory        = Local RAM Bank 0
+ *   Additional regions = Local RAM Bank 1 + AHB SRAM (exluding DMA buffers)
+ *
+ * Configuration B:
+ *   Program memory     = Local RAM Bank 0
+ *   Data memory        = Local RAM Bank 1
+ *   Additional regions = AHB SRAM (exluding DMA buffers)
+ *
+ * This file supports only memory configuration A.
+ *
+ * These should be defined in the memory map header file:
+ *
+ *    LPC43_LOCSRAM_BANK0_BASE   0x10000000
+ *    LPC43_LOCSRAM_BANK1_BASE   0x10080000
+ *    LPC43_AHBSRAM_BANK0_BASE   0x20000000
+ *    LPC43_AHBSRAM_BANK1_BASE   0x20008000
+ *    LPC43_AHBSRAM_BANK2_BASE   0x2000c000
+ *
+ * These should be defined for the specific chip in the chip.h header file.
+ * The value will be defined to be zero in size of the bank does not exist.
+ * If two banks are contiguous, the combined size will be added to the
+ * first bank and the size of the second bank will be defined to be zero.
+ *
+ *    LPC43_LOCSRAM_BANK0_SIZE
+ *    LPC43_LOCSRAM_BANK1_SIZE
+ *    LPC43_AHBSRAM_BANK0_SIZE
+ *    LPC43_AHBSRAM_BANK1_SIZE
+ *    LPC43_AHBSRAM_BANK2_SIZE
+ *
+ * The config.h file will define only:
+ *
+ *    CONFIG_DRAM_START = The start of the data RAM region which may be
+ *      either local SRAM bank 0 (Configuration A) or 1 (Configuration B).
+ *    CONFIG_DRAM_START = The size of the data RAM region.
+ *    CONFIG_DRAM_END   = The sum of the above
+ */
+
+/* Check for Configuration A. */
+
+#ifndef CONFIG_BOOT_SRAM
+
+/* Configuration A */
+/* CONFIG_DRAM_START should be set to the base of AHB SRAM, local 0. */
+
+#  if CONFIG_DRAM_START != LPC43_LOCSRAM_BANK0_BASE
+#    error "CONFIG_DRAM_START must be set to the base address of AHB SRAM Bank 0"
+#  endif
+
+/* The configured RAM size should be equal to the size of local SRAM Bank 0 */
+
+#  if CONFIG_DRAM_SIZE != LPC43_LOCSRAM_BANK0_SIZE
+#    error "CONFIG_DRAM_SIZE must be set to size of AHB SRAM Bank 0"
+#  endif
+
+/* Now we can assign all of the memory regions for configuration A */
+
+#  define MM_REGION1_BASE  LPC43_LOCSRAM_BANK0_BASE
+#  define MM_REGION1_SIZE  LPC43_LOCSRAM_BANK0_SIZE
+#  define MM_REGION2_BASE  LPC43_LOCSRAM_BANK1_BASE
+#  define MM_REGION2_SIZE  LPC43_LOCSRAM_BANK1_SIZE
+#  define MM_REGION3_BASE  LPC43_AHBSRAM_BANK0_BASE
+#  define MM_REGION3_SIZE  LPC43_AHBSRAM_BANK0_SIZE
+#else
+
+/* Configuration B */
+/* CONFIG_DRAM_START should be set to the base of local SRAM, bank 1. */
+
+#  if CONFIG_DRAM_START != LPC43_LOCSRAM_BANK1_BASE
+#    error "CONFIG_DRAM_START must be set to the base address of AHB SRAM Bank 0"
+#  endif
+
+/* The configured RAM size should be equal to the size of local SRAM Bank 1 */
+
+#  if CONFIG_DRAM_SIZE != LPC43_LOCSRAM_BANK1_SIZE
+#    error "CONFIG_DRAM_SIZE must be set to size of AHB SRAM Bank 0"
+#  endif
+
+/* Now we can assign all of the memory regions for configuration B */
+
+#  define MM_REGION1_BASE  LPC43_LOCSRAM_BANK1_BASE
+#  define MM_REGION1_SIZE  LPC43_LOCSRAM_BANK1_SIZE
+#  define MM_REGION2_BASE  LPC43_AHBSRAM_BANK0_BASE
+#  define MM_REGION2_SIZE  LPC43_AHBSRAM_BANK0_SIZE
+#  undef  MM_REGION3_BASE
+#  undef  MM_REGION3_SIZE
+#endif
+
+#define MM_DMAREGION_BASE  LPC43_AHBSRAM_BANK2_BASE
+#define MM_DMAREGION_SIZE  LPC43_AHBSRAM_BANK2_SIZE
+
+/* Figure out how much heap we have in the DMA region that is not being
+ * used by USB and/or Ethernet (if any).
+ */
+
+#warning "Missing Logic"
+
+#define MM_DMAHEAP_BASE MM_DMAREGION_BASE /* For now... use it all */
+#define MM_DMAHEAP_SIZE MM_DMAREGION_SIZE
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/* _sbss is the start of the BSS region (see the linker script) _ebss is the
+ * end of the BSS regsion (see the linker script). The idle task stack starts
+ * at the end of BSS and is of size CONFIG_IDLETHREAD_STACKSIZE.  The IDLE
+ * thread is the thread that the system boots on and, eventually, becomes the
+ * idle, do nothing task that runs only when there is nothing else to run.
+ * The heap continues from there until the configured end of memory.
+ * g_heapbase is the beginning of this heap region (not necessarily aligned).
+ */
+
+const uint32_t g_heapbase = (uint32_t)&_ebss + CONFIG_IDLETHREAD_STACKSIZE;
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_allocate_heap
+ *
+ * Description:
+ *   The heap may be statically allocated by
+ *   defining CONFIG_HEAP_BASE and CONFIG_HEAP_SIZE.  If these
+ *   are not defined, then this function will be called to
+ *   dynamically set aside the heap region.
+ *
+ ****************************************************************************/
+
+void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
+{
+  /* Start with the first SRAM region */
+
+  up_ledon(LED_HEAPALLOCATE);
+  *heap_start = (FAR void*)g_heapbase;
+  *heap_size = CONFIG_DRAM_END - g_heapbase;
+}
+
+/************************************************************************
+ * Name: up_addregion
+ *
+ * Description:
+ *   Memory may be added in non-contiguous chunks.  Additional chunks are
+ *   added by calling this function.
+ *
+ ************************************************************************/
+
+#if CONFIG_MM_REGIONS > 1
+void up_addregion(void)
+{
+#if CONFIG_MM_REGIONS > 1
+ /* Add the next SRAM region (which should exist) */
+ 
+ mm_addregion((FAR void*)MM_REGION2_BASE, MM_REGION2_SIZE);
+
+#ifdef MM_REGION3_BASE
+ /* Add the third SRAM region (which will not exist in configuration B) */
+
+#if CONFIG_MM_REGIONS > 2
+ /* Add the third SRAM region (which may not exist) */
+ 
+ mm_addregion((FAR void*)MM_REGION3_BASE, MM_REGION3_SIZE);
+
+#if CONFIG_MM_REGIONS > 3 && defined(MM_DMAHEAP_BASE)
+ /* Add the DMA region (which may not be available) */
+ 
+ mm_addregion((FAR void*)MM_DMAHEAP_BASE, MM_DMAHEAP_SIZE);
+
+#endif /* CONFIG_MM_REGIONS > 3 && defined(MM_DMAHEAP_BASE) */
+#endif /* CONFIG_MM_REGIONS > 2 */
+#else  /* MM_REGION3_BASE */
+
+#if CONFIG_MM_REGIONS > 2 && defined(MM_DMAHEAP_BASE)
+ /* Add the DMA region (which may not be available) */
+ 
+ mm_addregion((FAR void*)MM_DMAHEAP_BASE, MM_DMAHEAP_SIZE);
+
+#endif /* CONFIG_MM_REGIONS > 3 && defined(MM_DMAHEAP_BASE) */
+#endif /* MM_REGION3_BASE */
+#endif /* CONFIG_MM_REGIONS > 1 */
+}
+#endif
diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_cgu.c b/nuttx/arch/arm/src/lpc43xx/lpc43_cgu.c
new file mode 100644
index 000000000..61c4112ae
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/lpc43_cgu.c
@@ -0,0 +1,482 @@
+/****************************************************************************
+ *  arch/arm/src/lpc43/lpc43_cgu.c
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <nuttx/arch.h>
+#include <errno.h>
+
+#include "up_arch.h"
+#include "lpc43_cgu.h"
+#include <arch/board/board.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+/* Maximum/Threashold Frequencies *******************************************/
+
+#define LOW_XTAL_FREQUENCY     15000000
+#define MAX_XTAL_FREQUENCY     25000000
+
+#define MAX_FCLKOUT_FREQUENCY 204000000
+#define MAX_FCLKOUT_DIRECT    156000000
+#define MAX_FCCO_FRQUENCY     320000000
+
+/* Configuration ************************************************************/
+/* This supports configuration of CGU clocking from board-specific parameters
+ * that must be provided in the board.h header file.
+ *
+ * That header file must provided the following values:
+ *
+ * BOARD_XTAL_FREQUENCY - The LPC43xx XTAL oscillator input frequency
+ */
+
+#ifndef BOARD_XTAL_FREQUENCY
+#  error "board.h must provide the LPC43xx cystal input frequency (BOARD_XTAL_FREQUENCY)"
+#endif
+
+#if BOARD_XTAL_FREQUENCY >= MAX_XTAL_FREQUENCY
+#  error "BOARD_XTAL_FREQUENCY exceeds the maximum value"
+#endif
+
+#if BOARD_FCLKOUT_FREQUENCY > MAX_FCLKOUT_FREQUENCY
+#  error "BOARD_FCLKOUT_FREQUENCY exceed the maximum"
+#endif
+
+#if BOARD_FCCO_FREQUENCY > MAX_FCCO_FRQUENCY
+#  error "BOARD_FCCO_FREQUENCY exceed the maximum"
+#endif
+
+/* Convert the user-friendly definitions in board.h to register bit settings */
+
+/* Check if we are using a RAMP */
+
+#undef PLL_RAMP
+
+#ifdef BOARD_PLL_RAMP_MSEL
+
+#  define PLL_RAMP 1
+
+   /* Get initial PLL values */
+
+#  define INIT_MSEL_VALUE PLL1_CTRL_MSEL(1)
+#  define INIT_NSEL_VALUE PLL1_CTRL_NSEL_DIV1
+
+   /* Pick the initial PSEL value (integer mode) */
+
+#  ifndef BOARD_XTAL_FREQUENCY
+#    error "BOARD_XTAL_FREQUENCY is not defined in board.h"
+#  endif
+
+#  if BOARD_XTAL_FREQUENCY >= MAX_FCLKOUT_DIRECT
+#    error "BOARD_XTAL_FREQUENCY value is not supported"
+#  endif
+
+#  if (2 * BOARD_XTAL_FREQUENCY) > MAX_FCCO_FRQUENCY
+#    error "Impossible value for BOARD_XTAL_FREQUENCY"
+#  elif (2 * 2 * BOARD_XTAL_FREQUENCY) > MAX_FCCO_FRQUENCY
+#    define INIT_PSEL_VALUE PLL1_CTRL_PSEL_DIV1
+#  elif (2 * 4 * BOARD_XTAL_FREQUENCY) > MAX_FCCO_FRQUENCY
+#    define INIT_PSEL_VALUE PLL1_CTRL_PSEL_DIV2
+#  elif (2 * 8 * BOARD_XTAL_FREQUENCY) > MAX_FCCO_FRQUENCY
+#    define INIT_PSEL_VALUE PLL1_CTRL_PSEL_DIV4
+#  else
+#    define INIT_PSEL_VALUE PLL1_CTRL_PSEL_DIV8
+#  endif
+
+   /* Select initial integer mode controls */
+
+#  define INIT_PLL_CONTROLS \
+   (PLL1_CTRL_FBSEL | INIT_PSEL_VALUE  | INIT_NSEL_VALUE | INIT_MSEL_VALUE)
+
+   /* Select a value close to a 10 millisecond delay */
+
+#  define XTAL_DELAY \
+   (10 * BOARD_XTAL_FREQUENCY + (LPC43_CCLK - 1)) / LPC43_CCLK
+
+   /* Check the ramp-up MSEL value */
+
+#  if (BOARD_PLL_RAMP_MSEL > 0) && (BOARD_PLL_RAMP_MSEL < 256)
+#    define RAMP_MSEL_VALUE PLL1_CTRL_MSEL(BOARD_PLL_RAMP_MSEL)
+#  else
+#    error "Unsupported value of BOARD_PLL_RAMP_NSEL"
+#  endif
+
+   /* Check the ramp-up NSEL value */
+
+#  ifndef BOARD_PLL_RAMP_NSEL
+#    error "BOARD_PLL_RAMP_NSEL is not defined in board.h"
+#  endif
+
+#  if BOARD_PLL_RAMP_NSEL == 1
+#   define RAMP_NSEL_VALUE PLL1_CTRL_NSEL_DIV1
+#  elif BOARD_PLL_RAMP_NSEL == 2
+#    define RAMP_NSEL_VALUE PLL1_CTRL_NSEL_DIV2
+#  elif BOARD_PLL_RAMP_NSEL == 3
+#    define RAMP_NSEL_VALUE PLL1_CTRL_NSEL_DIV3
+#  elif BOARD_PLL_RAMP_NSEL == 4
+#    define RAMP_NSEL_VALUE PLL1_CTRL_NSEL_DIV4
+#  else
+#    error "Unsupported value of BOARD_PLL_RAMP_NSEL"
+#  endif
+
+   /* Check for direct mode */
+
+#  ifndef BOARD_RAMP_FCLKOUT
+#    error "BOARD_RAMP_FCLKOUT is not defined in board.h"
+#  endif
+
+#  if BOARD_RAMP_FCLKOUT >= MAX_FCLKOUT_DIRECT
+
+     /* Select direct mode controls */
+
+#    define RAMP_PLL_CONTROLS \
+    (PLL1_CTRL_FBSEL | PLL1_CTRL_DIRECT  | RAMP_NSEL_VALUE | RAMP_MSEL_VALUE)
+
+#  else
+
+   /* Check the ramp-up PSEL value */
+
+#    ifndef BOARD_PLL_RAMP_PSEL
+#     error "BOARD_PLL_RAMP_PSEL is not defined in board.h"
+#    endif
+
+#    if BOARD_PLL_RAMP_PSEL == 1
+#      define RAMP_PSEL_VALUE PLL1_CTRL_PSEL_DIV1
+#    elif BOARD_PLL_RAMP_PSEL == 2
+#      define RAMP_PSEL_VALUE PLL1_CTRL_PSEL_DIV2
+#    elif BOARD_PLL_RAMP_PSEL == 4
+#      define RAMP_PSEL_VALUE PLL1_CTRL_PSEL_DIV4
+#    elif BOARD_PLL_RAMP_PSEL == 8
+#      define RAMP_PSEL_VALUE PLL1_CTRL_PSEL_DIV8
+#    else
+#      error "Unsupported value of BOARD_PLL_RAMP_PSEL"
+#    endif
+#  endif
+
+     /* Select integer mode controls */
+
+#    define RAMP_PLL_CONTROLS \
+     (PLL1_CTRL_FBSEL | RAMP_PSEL_VALUE  | RAMP_NSEL_VALUE | RAMP_MSEL_VALUE)
+
+   /* Select a value close to a 10 millisecond delay */
+
+#endif
+
+   /* Check the Final MSEL value */
+
+#ifndef BOARD_PLL_MSEL
+#  error "BOARD_PLL_MSEL is not defined in board.h"
+#endif
+
+#if (BOARD_PLL_MSEL > 0) && (BOARD_PLL_MSEL < 256)
+#  define CTRL_MSEL_VALUE PLL1_CTRL_MSEL(BOARD_PLL_MSEL)
+#else
+#  error "Unsupported value of BOARD_PLL_MSEL"
+#endif
+
+   /* Check the Final NSEL value */
+
+#ifndef BOARD_PLL_NSEL
+#  error "BOARD_PLL_NSEL is not defined in board.h"
+#endif
+
+#if BOARD_PLL_NSEL == 1
+#  define CTRL_NSEL_VALUE PLL1_CTRL_NSEL_DIV1
+#elif BOARD_PLL_NSEL == 2
+#  define CTRL_NSEL_VALUE PLL1_CTRL_NSEL_DIV2
+#elif BOARD_PLL_NSEL == 3
+#  define CTRL_NSEL_VALUE PLL1_CTRL_NSEL_DIV3
+#elif BOARD_PLL_NSEL == 4
+#  define CTRL_NSEL_VALUE PLL1_CTRL_NSEL_DIV4
+#else
+#  error "Unsupported value of BOARD_PLL_NSEL"
+#endif
+
+   /* Check for direct mode */
+
+#ifndef BOARD_FCLKOUT_FREQUENCY
+#  error "BOARD_FCLKOUT_FREQUENCY is not defined in board.h"
+#endif
+
+#if BOARD_FCLKOUT_FREQUENCY >= MAX_FCLKOUT_DIRECT
+
+     /* Select direct mode controls */
+
+#    define PLL_CONTROLS \
+     (PLL1_CTRL_FBSEL | PLL1_CTRL_DIRECT | CTRL_NSEL_VALUE | CTRL_MSEL_VALUE)
+
+#  else
+
+   /* Check the Final PSEL value */
+
+#  ifndef BOARD_PLL_PSEL
+#    error "BOARD_PLL_PSEL is not defined in board.h"
+#  endif
+
+#  if BOARD_PLL_PSEL == 1
+#    define CTRL_PSEL_VALUE PLL1_CTRL_PSEL_DIV1
+#  elif BOARD_PLL_PSEL == 2
+#    define CTRL_PSEL_VALUE PLL1_CTRL_PSEL_DIV2
+#  elif BOARD_PLL_PSEL == 4
+#    define CTRL_PSEL_VALUE PLL1_CTRL_PSEL_DIV4
+#  elif BOARD_PLL_PSEL == 8
+#    define CTRL_PSEL_VALUE PLL1_CTRL_PSEL_DIV8
+#  else
+#    error "Unsupported value of BOARD_PLL_PSEL"
+#  endif
+
+     /* Select integer mode controls */
+
+#    define PLL_CONTROLS \
+     (PLL1_CTRL_FBSEL | CTRL_PSEL_VALUE  | CTRL_NSEL_VALUE | CTRL_MSEL_VALUE)
+
+#endif
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: lpc43_xtalconfig
+ *
+ * Description:
+ *   Configure the cystal input to PLL1 using the settings provided in
+ *   the board.h file.
+ *
+ ****************************************************************************/
+
+static inline void lpc43_xtalconfig(void)
+{
+  /* Configure the crystal input to PLL1 */
+
+  uint32_t regval;
+
+  /* Set/clear the HF bit in the crystal oscillator control register.
+   * - The bit must be cleared if low-frequency oscillators (<=15MHz)
+   * - The HF bit must be set for high-frequency osciallators (>20MHz)
+   * - For oscillators in the range 15-20 MHz, the HF setting does not matter.
+   */
+
+  regval = getreg32(LPC43_XTAL_OSC_CTRL);
+#if BOARD_XTAL_FREQUENCY <= LOW_XTAL_FREQUENCY
+  regval &= ~XTAL_OSC_CTRL_HF;
+#else
+  regval |= XTAL_OSC_CTRL_HF;
+#endif
+  putreg32(regval, LPC43_XTAL_OSC_CTRL);
+
+  /* Enable the crystal oscillator by taking it out of power down mode */
+
+  regval &= ~XTAL_OSC_CTRL_ENABLE;
+  putreg32(regval, LPC43_XTAL_OSC_CTRL);
+
+  /* Delay for stable clock input */
+
+  up_mdelay(20);
+
+  /* Select the crystal oscillator as the input to PLL1 */
+
+  regval  = getreg32(LPC43_PLL1_CTRL);
+  regval &= ~PLL1_CTRL_CLKSEL_MASK;
+  regval |= PLL1_CLKSEL_XTAL | PLL1_CTRL_AUTOBLOCK;
+  putreg32(regval, LPC43_PLL1_CTRL);
+}
+
+/****************************************************************************
+ * Name: lpc43_pll1config
+ *
+ * Description:
+ *   Configure PLL1 dividers and multipliers per the settings in the board.h
+ *   file to generate the desired Fclkcout and Fcco frequencies.
+ *
+ ****************************************************************************/
+
+static inline void lpc43_pll1config(uint32_t ctrlvalue)
+{
+  uint32_t regval;
+
+  /* Clear PLL1 controls:
+   *
+   *   - PLL1_CTRL_BYPASS:    Input clock bypass control
+   *   - PLL1_CTRL_FBSEL:     PLL1 feedback select
+   *   - PLL1_CTRL_DIRECT:    PLL1 direct CCO output
+   *   - PLL1_CTRL_PSEL_MASK: Post-divider division ratio P (psel)
+   *   - PLL1_CTRL_NSEL_MASK: Pre-divider division ratio N (nsel)
+   *   - PLL1_CTRL_MSEL_MASK: Feedback-divider division ratio M (msel)
+   */
+
+  regval  = getreg32(LPC43_PLL1_CTRL);
+  regval &= ~(PLL1_CTRL_BYPASS    | PLL1_CTRL_FBSEL     | PLL1_CTRL_DIRECT |
+              PLL1_CTRL_PSEL_MASK | PLL1_CTRL_NSEL_MASK |
+              PLL1_CTRL_MSEL_MASK);
+  
+  /* Set selected PLL1 controls:
+   *
+   *   - PLL1_CTRL_FBSEL:     Set in both integer and direct modes
+   *   - PLL1_CTRL_DIRECT:    Set in direct mode
+   *   - PLL1_CTRL_PSEL:      Set to the value from board.h (integer mode only)
+   *   - PLL1_CTRL_NSEL:      Set to the value from board.h
+   *   - PLL1_CTRL_MSEL:      Set to the value from board.h
+   */
+
+  regval    |= ctrlvalue;
+  putreg32(regval, LPC43_PLL1_CTRL);
+}
+
+/****************************************************************************
+ * Name: lpc43_pll1enable
+ *
+ * Description:
+ *   Take PLL1 out of power-down mode and wait until it is locked onto the
+ *   input clock.
+ *
+ ****************************************************************************/
+
+static inline void lpc43_pll1enable(void)
+{
+  uint32_t regval;
+
+  /* Take PLL1 out of power down mode.  The reset state of the PD bit
+   * is one, i.e., powered down.
+   */
+  
+  regval  = getreg32(LPC43_PLL1_CTRL);
+  regval &= ~PLL1_CTRL_PD;
+  putreg32(regval, LPC43_PLL1_CTRL);
+
+  /* When the power-down mode is terminated, PPL1 will resume its normal
+   * operation and will make the lock signal high once it has regained
+   * lock on the input clock
+   *
+   * Wait for PLL1 to report that it is locked.
+   */
+
+  while ((getreg32(LPC43_PLL1_STAT) & PLL1_STAT_LOCK) == 0);
+}
+
+/****************************************************************************
+ * Name: lpc43_m4clkselect
+ *
+ * Description:
+ *   Select PLL1 output as the Cortex-M4 source clock.
+ *
+ ****************************************************************************/
+
+static inline void lpc43_m4clkselect(uint32_t clksel)
+{
+  uint32_t regval;
+
+  regval = getreg32(LPC43_BASE_M4_CLK);
+  regval &= ~BASE_M4_CLK_CLKSEL_MASK;
+  regval |= clksel;
+  putreg32(regval, LPC43_BASE_M4_CLK);
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: lpc43_clockconfig
+ *
+ * Description:
+ *   Called to initialize the LPC43XX.  This does whatever setup is needed
+ *   to put the MCU in a usable state.  This includes the initialization of
+ *   clocking using the settings in board.h.
+ *
+ ****************************************************************************/
+
+void lpc43_clockconfig(void)
+{
+  /* Configure the crystal input to PLL1 */
+
+  lpc43_xtalconfig();
+
+#ifndef PLL_RAMP
+  /* Configure PLL1 */
+
+  lpc43_pll1config(PLL_CONTROLS);
+
+  /* Enable PLL1 */
+
+  lpc43_pll1enable();
+ 
+  /* Set up PLL1 output as the M4 clock */
+
+  lpc43_m4clkselect(BASE_M4_CLKSEL_PLL1);
+#else
+
+  /* Drive the M4 clock from the XTAL until the PLL is configured */
+
+  lpc43_m4clkselect(BASE_M4_CLKSEL_XTAL);
+
+  /* Select the initial PLL1 configured (BOARD_XTAL_FREQUENCY x 1) */
+
+  lpc43_pll1config(INIT_PLL_CONTROLS);
+
+  /* Enable PLL1 */
+
+  lpc43_pll1enable();
+
+  /* Delay around 10 milliseconds */
+
+  up_mdelay(XTAL_DELAY);
+
+  /* Configure the intermediate, ramp-up configuration for PLL1 */
+
+  lpc43_pll1config(RAMP_PLL_CONTROLS);
+
+  /* Set up PLL1 output as the M4 clock */
+
+  lpc43_m4clkselect(BASE_M4_CLKSEL_PLL1);
+
+  /* Delay around 10 milliseconds */
+
+  up_mdelay(XTAL_DELAY);
+
+  /* Go to the final, full-speed PLL1 configuration */
+
+  lpc43_pll1config(PLL_CONTROLS);  
+#endif
+}
diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_cgu.h b/nuttx/arch/arm/src/lpc43xx/lpc43_cgu.h
new file mode 100644
index 000000000..94254c648
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/lpc43_cgu.h
@@ -0,0 +1,91 @@
+/************************************************************************************
+ * arch/arm/src/lpc43xx/lpc43_cgu.h
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LPC43XX_CGU_H
+#define __ARCH_ARM_SRC_LPC43XX_CGU_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+#include "chip.h"
+#include "chip/lpc43_cgu.h"
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C" {
+#else
+#define EXTERN extern
+#endif
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Name: lpc43_clockconfig
+ *
+ * Description:
+ *   Called to initialize the LPC43XX.  This does whatever setup is needed to put the
+ *   MCU in a usable state.  This includes the initialization of clocking using the
+ *   settings in board.h.
+ *
+ ************************************************************************************/
+
+EXTERN void lpc43_clockconfig(void);
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_ARM_SRC_LPC43XX_CGU_H */
diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_clrpend.c b/nuttx/arch/arm/src/lpc43xx/lpc43_clrpend.c
new file mode 100644
index 000000000..ca7189103
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/lpc43_clrpend.c
@@ -0,0 +1,99 @@
+/****************************************************************************
+ * arch/arm/src/lpc43/lpc43_clrpend.c
+ * arch/arm/src/chip/lpc43_clrpend.c
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <arch/irq.h>
+
+#include "nvic.h"
+#include "up_arch.h"
+
+#include "lpc43_irq.h"
+
+/****************************************************************************
+ * Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: lpc43_clrpend
+ *
+ * Description:
+ *   Clear a pending interrupt at the NVIC.  This does not seem to be required
+ *   for most interrupts.  Don't know why... but the LPC4366 Ethernet EMAC
+ *   interrupt definitely needs it!
+ *
+ *   This function is logically a part of lpc43_irq.c, but I will keep it in
+ *   a separate file so that it will not increase the footprint on LPC43xx
+ *   platforms that do not need this function.
+ *
+ ****************************************************************************/
+
+void lpc43_clrpend(int irq)
+{
+  /* Check for external interrupt */
+
+  if (irq >= LPC43_IRQ_EXTINT)
+    {
+      if (irq < (LPC43_IRQ_EXTINT + 32))
+        {
+          putreg32(1 << (irq - LPC43_IRQ_EXTINT), NVIC_IRQ0_31_CLRPEND);
+        }
+      else if (irq < LPC43M4_IRQ_NIRQS)
+        {
+          putreg32(1 << (irq - LPC43_IRQ_EXTINT - 32), NVIC_IRQ32_63_CLRPEND);
+        }
+    }
+}
diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_config.h b/nuttx/arch/arm/src/lpc43xx/lpc43_config.h
new file mode 100644
index 000000000..fb5773682
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/lpc43_config.h
@@ -0,0 +1,153 @@
+/************************************************************************************
+ * arch/arm/src/lpc43xx/lpc43_config.h
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LPC43XX_LPC43XX_CONFIG_H
+#define __ARCH_ARM_SRC_LPC43XX_LPC43XX_CONFIG_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Required configuration settings */
+
+/* There are two version of the FPU support built into the most NuttX Cortex-M4 ports.
+ * The current LPC43xx port support only one of these options, the "Non-Lazy Floating
+ * Point Register Save".  As a consequence, CONFIG_ARMV7M_CMNVECTOR must be defined
+ * in *all* LPC43xx configuration files.
+ */
+
+#ifndef CONFIG_ARMV7M_CMNVECTOR
+#  error "CONFIG_ARMV7M_CMNVECTOR must be defined for the LPC43xx"
+#endif
+
+/* Are any UARTs enabled? */
+
+#undef HAVE_UART
+#if defined(CONFIG_LPC43_USART0) || defined(CONFIG_LPC43_UART1) || \
+    defined(CONFIG_LPC43_USART2) || defined(CONFIG_LPC43_USART3)
+#  define HAVE_UART 1
+#endif
+
+/* Make sure all features are disabled for diabled U[S]ARTs.  This simplifies
+ * checking later.
+ */
+
+#ifndef CONFIG_LPC43_USART0
+#  undef CONFIG_USART0_SERIAL_CONSOLE
+#  undef CONFIG_USART0_RS485MODE
+#endif
+
+#ifndef CONFIG_LPC43_UART1
+#  undef CONFIG_UART1_SERIAL_CONSOLE
+#endif
+
+#ifndef CONFIG_LPC43_USART2
+#  undef CONFIG_USART2_SERIAL_CONSOLE
+#  undef CONFIG_USART2_RS485MODE
+#endif
+
+#ifndef CONFIG_LPC43_USART3
+#  undef CONFIG_USART3_SERIAL_CONSOLE
+#  undef CONFIG_USART3_RS485MODE
+#endif
+
+/* Is there a serial console? There should be at most one defined.  It could be on
+ * any UARTn, n=0,1,2,3 - OR - there might not be any serial console at all.
+ */
+
+#if defined(CONFIG_USART0_SERIAL_CONSOLE)
+#  undef CONFIG_UART1_SERIAL_CONSOLE
+#  undef CONFIG_USART2_SERIAL_CONSOLE
+#  undef CONFIG_USART3_SERIAL_CONSOLE
+#  define HAVE_CONSOLE 1
+#elif defined(CONFIG_UART1_SERIAL_CONSOLE)
+#  undef CONFIG_USART0_SERIAL_CONSOLE
+#  undef CONFIG_USART2_SERIAL_CONSOLE
+#  undef CONFIG_USART3_SERIAL_CONSOLE
+#  define HAVE_CONSOLE 1
+#elif defined(CONFIG_USART2_SERIAL_CONSOLE)
+#  undef CONFIG_USART0_SERIAL_CONSOLE
+#  undef CONFIG_UART1_SERIAL_CONSOLE
+#  undef CONFIG_USART3_SERIAL_CONSOLE
+#  define HAVE_CONSOLE 1
+#elif defined(CONFIG_USART3_SERIAL_CONSOLE)
+#  undef CONFIG_USART0_SERIAL_CONSOLE
+#  undef CONFIG_UART1_SERIAL_CONSOLE
+#  undef CONFIG_USART2_SERIAL_CONSOLE
+#  define HAVE_CONSOLE 1
+#else
+#  undef CONFIG_USART0_SERIAL_CONSOLE
+#  undef CONFIG_UART1_SERIAL_CONSOLE
+#  undef CONFIG_USART2_SERIAL_CONSOLE
+#  undef CONFIG_USART3_SERIAL_CONSOLE
+#  undef HAVE_CONSOLE
+#endif
+
+/* Check UART flow control (Only supported by UART1) */
+
+# undef CONFIG_USART0_FLOWCONTROL
+# undef CONFIG_USART2_FLOWCONTROL
+# undef CONFIG_USART3_FLOWCONTROL
+#ifndef CONFIG_LPC43_UART1
+# undef CONFIG_UART1_FLOWCONTROL
+#endif
+
+/* Check for RS-485 support (USART0,2,3 only) */
+
+#undef HAVE_RS485
+#if defined(CONFIG_USART0_RS485MODE) || defined(CONFIG_USART2_RS485MODE) || \
+    defined(CONFIG_USART3_RS485MODE)
+#  define HAVE_RS485 1
+#endif
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_LPC43XX_LPC43XX_CONFIG_H */
diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_dac.c b/nuttx/arch/arm/src/lpc43xx/lpc43_dac.c
new file mode 100644
index 000000000..5fcceaa1e
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/lpc43_dac.c
@@ -0,0 +1,204 @@
+/************************************************************************************
+ * arch/arm/src/lpc43xx/lpc43_dac.c
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Ported from from the LPC17 version:
+ *
+ *   Copyright (C) 2011 Li Zhuoyi. All rights reserved.
+ *   Author: Li Zhuoyi <lzyy.cn@gmail.com>
+ *   History: 0.1 2011-08-05 initial version
+ * 
+ * This file is a part of NuttX:
+ *
+ *   Copyright (C) 2010-2012 Gregory Nutt. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdio.h>
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <semaphore.h>
+#include <errno.h>
+#include <debug.h>
+
+#include <arch/board/board.h>
+#include <nuttx/arch.h>
+#include <nuttx/analog/dac.h>
+
+#include "up_internal.h"
+#include "up_arch.h"
+
+#include "chip.h"
+
+#include "lpc43_syscon.h"
+#include "lpc43_pinconn.h"
+#include "lpc43_dac.h"
+
+#ifdef CONFIG_LPC43_DAC
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/* DAC methods */
+
+static void dac_reset(FAR struct dac_dev_s *dev);
+static int  dac_setup(FAR struct dac_dev_s *dev);
+static void dac_shutdown(FAR struct dac_dev_s *dev);
+static void dac_txint(FAR struct dac_dev_s *dev, bool enable);
+static int  dac_send(FAR struct dac_dev_s *dev, FAR struct dac_msg_s *msg);
+static int  dac_ioctl(FAR struct dac_dev_s *dev, int cmd, unsigned long arg);
+static int  dac_interrupt(int irq, void *context);
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static const struct dac_ops_s g_dacops =
+{
+  .ao_reset =dac_reset,
+  .ao_setup = dac_setup,
+  .ao_shutdown = dac_shutdown,
+  .ao_txint = dac_txint,
+  .ao_send = dac_send,
+  .ao_ioctl = dac_ioctl,
+};
+
+static struct dac_dev_s g_dacdev =
+{
+  .ad_ops = &g_dacops,
+};
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/* Reset the DAC device.  Called early to initialize the hardware. This
+ * is called, before ao_setup() and on error conditions.
+ */
+
+static void dac_reset(FAR struct dac_dev_s *dev)
+{
+  irqstate_t flags;
+  uint32_t regval;
+    
+  flags = irqsave();
+
+  regval  = getreg32(LPC43_SYSCON_PCLKSEL0);
+  regval &= ~SYSCON_PCLKSEL0_DAC_MASK;
+  regval |= (SYSCON_PCLKSEL_CCLK8 << SYSCON_PCLKSEL0_DAC_SHIFT);
+  putreg32(regval, LPC43_SYSCON_PCLKSEL0);
+
+  //putreg32(DAC_CTRL_DBLBUFEN,LPC43_DAC_CTRL); ?
+
+  lpc43_configgpio(GPIO_AOUT);
+
+  irqrestore(flags);
+}
+
+/* Configure the DAC. This method is called the first time that the DAC
+ * device is opened.  This will occur when the port is first opened.
+ * This setup includes configuring and attaching DAC interrupts.  Interrupts
+ * are all disabled upon return.
+ */
+
+static int  dac_setup(FAR struct dac_dev_s *dev)
+{
+  return OK;
+}
+
+/* Disable the DAC.  This method is called when the DAC device is closed.
+ * This method reverses the operation the setup method.
+ */
+
+static void dac_shutdown(FAR struct dac_dev_s *dev)
+{
+}
+
+/* Call to enable or disable TX interrupts */
+
+static void dac_txint(FAR struct dac_dev_s *dev, bool enable)
+{
+}
+
+static int  dac_send(FAR struct dac_dev_s *dev, FAR struct dac_msg_s *msg)
+{
+  putreg32((msg->am_data>>16)&0xfffff,LPC43_DAC_CR);
+  dac_txdone(&g_dacdev);
+  return 0;
+}
+
+/* All ioctl calls will be routed through this method */
+
+static int  dac_ioctl(FAR struct dac_dev_s *dev, int cmd, unsigned long arg)
+{
+  dbg("Fix me:Not Implemented\n");
+  return 0;
+}
+
+static int  dac_interrupt(int irq, void *context)
+{
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: lpc43_dacinitialize
+ *
+ * Description:
+ *   Initialize the DAC
+ *
+ * Returned Value:
+ *   Valid dac device structure reference on succcess; a NULL on failure
+ *
+ ****************************************************************************/
+
+FAR struct dac_dev_s *lpc43_dacinitialize(void)
+{
+  return &g_dacdev;
+}
+
+#endif /* CONFIG_LPC43_DAC */
+
diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_dac.h b/nuttx/arch/arm/src/lpc43xx/lpc43_dac.h
new file mode 100644
index 000000000..310e29f51
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/lpc43_dac.h
@@ -0,0 +1,95 @@
+/****************************************************************************
+ * arch/arm/src/lpc43xx/lpc43_dac.h
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LPC43XX_LPC43_DAC_H
+#define __ARCH_ARM_SRC_LPC43XX_LPC43_DAC_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/analog/dac.h>
+#include "chip/lpc43_dac.h"
+
+#ifdef CONFIG_LPC43_DAC
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C" {
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: lpc43_dacinitialize
+ *
+ * Description:
+ *   Initialize the DAC
+ *
+ * Returned Value:
+ *   Valid dac device structure reference on succcess; a NULL on failure
+ *
+ ****************************************************************************/
+
+EXTERN FAR struct dac_dev_s *lpc43_dacinitialize(void);
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* CONFIG_LPC43_DAC */
+#endif /* __ARCH_ARM_SRC_LPC43XX_LPC43_DAC_H */
diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_debug.c b/nuttx/arch/arm/src/lpc43xx/lpc43_debug.c
new file mode 100644
index 000000000..51cf94706
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/lpc43_debug.c
@@ -0,0 +1,96 @@
+/****************************************************************************
+ *  arch/arm/src/lpc43/lpc43_debug.c
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <errno.h>
+
+#include <arch/board/board.h>
+
+#include "up_arch.h"
+#include "lpc43_pinconfig.h"
+#include "lpc43_gpio.h"
+
+#ifdef CONFIG_DEBUG
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+/****************************************************************************
+ * Function:  lpc43_pin_dump
+ *
+ * Description:
+ *   Dump all pin configuration registers associated with the provided pin
+ *   configuration
+ *
+ ****************************************************************************/
+
+int lpc43_pin_dump(uint32_t pinconf, const char *msg)
+{
+#warning "Missing logic"
+  return -ENOSYS;
+}
+
+/********************************************************************************************
+ * Function:  lpc43_gpio_dump
+ *
+ * Description:
+ *   Dump all pin configuration registers associated with the provided base address
+ *
+ ********************************************************************************************/
+
+int lpc43_gpio_dump(uint16_t gpiocfg, const char *msg)
+{
+#warning "Missing logic"
+  return -ENOSYS;
+}
+
+#endif /* CONFIG_DEBUG */
diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_emacram.h b/nuttx/arch/arm/src/lpc43xx/lpc43_emacram.h
new file mode 100644
index 000000000..2c472b616
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/lpc43_emacram.h
@@ -0,0 +1,62 @@
+/************************************************************************************
+ * arch/arm/src/lpc43xx/lpc43_emacram.h
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LPC43XX_LPC43_EMACRAM_H
+#define __ARCH_ARM_SRC_LPC43XX_LPC43_EMACRAM_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+#include "chip.h"
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_LPC43XX_LPC43_EMACRAM_H */
diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_emc.h b/nuttx/arch/arm/src/lpc43xx/lpc43_emc.h
new file mode 100644
index 000000000..3c2bd2496
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/lpc43_emc.h
@@ -0,0 +1,63 @@
+/************************************************************************************
+ * arch/arm/src/lpc43xx/lpc43_emc.h
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LPC43XX_LPC43_EMC_H
+#define __ARCH_ARM_SRC_LPC43XX_LPC43_EMC_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+#include "chip.h"
+#include "chip/lpc43_emc.h"
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_LPC43XX_LPC43_EMC_H */
diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_gpdma.c b/nuttx/arch/arm/src/lpc43xx/lpc43_gpdma.c
new file mode 100644
index 000000000..4cfc0327f
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/lpc43_gpdma.c
@@ -0,0 +1,226 @@
+/****************************************************************************
+ * arch/arm/src/lpc43xx/lpc43_gpdma.c
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <errno.h>
+#include <debug.h>
+
+#include <nuttx/arch.h>
+
+#include "up_internal.h"
+#include "up_arch.h"
+
+#include "chip.h"
+
+#include "lpc43_syscon.h"
+#include "lpc43_gpdma.h"
+
+#ifdef CONFIG_LPC43_GPDMA
+
+/****************************************************************************
+ * Definitions
+ ****************************************************************************/
+
+/* Enables debug output from this file (needs CONFIG_DEBUG too) */
+
+#undef DMA_DEBUG     /* Define to enable debug */
+#undef DMA_VERBOSE   /* Define to enable verbose debug */
+
+#ifdef DMA_DEBUG
+#  define dmadbg  lldbg
+#  ifdef DMA_VERBOSE
+#    define spivdbg lldbg
+#  else
+#    define spivdbg(x...)
+#  endif
+#else
+#  undef DMA_VERBOSE
+#  define dmadbg(x...)
+#  define spivdbg(x...)
+#endif
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: lpc43_dmainitialize
+ *
+ * Description:
+ *   Initialize the GPDMA subsystem.
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+void lpc43_dmainitilaize(void)
+{
+}
+
+/****************************************************************************
+ * Name: lpc43_dmachannel
+ *
+ * Description:
+ *   Allocate a DMA channel.  This function sets aside a DMA channel and
+ *   gives the caller exclusive access to the DMA channel.
+ *
+ * Returned Value:
+ *   One success, this function returns a non-NULL, void* DMA channel
+ *   handle.  NULL is returned on any failure.  This function can fail only
+ *   if no DMA channel is available.
+ *
+ ****************************************************************************/
+
+DMA_HANDLE lpc43_dmachannel(void)
+{
+  return NULL;
+}
+
+/****************************************************************************
+ * Name: lpc43_dmafree
+ *
+ * Description:
+ *   Release a DMA channel.  NOTE:  The 'handle' used in this argument must
+ *   NEVER be used again until lpc43_dmachannel() is called again to re-gain
+ *   a valid handle.
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+void lpc43_dmafree(DMA_HANDLE handle)
+{
+}
+
+/****************************************************************************
+ * Name: lpc43_dmasetup
+ *
+ * Description:
+ *   Configure DMA for one transfer.
+ *
+ ****************************************************************************/
+
+int lpc43_dmarxsetup(DMA_HANDLE handle, uint32_t control, uint32_t config,
+                     uint32_t srcaddr, uint32_t destaddr, size_t nbytes)
+{
+  return -ENOSYS;
+}
+
+/****************************************************************************
+ * Name: lpc43_dmastart
+ *
+ * Description:
+ *   Start the DMA transfer
+ *
+ ****************************************************************************/
+
+int lpc43_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg)
+{
+  return -ENOSYS;
+}
+
+/****************************************************************************
+ * Name: lpc43_dmastop
+ *
+ * Description:
+ *   Cancel the DMA.  After lpc43_dmastop() is called, the DMA channel is
+ *   reset and lpc43_dmasetup() must be called before lpc43_dmastart() can be
+ *   called again
+ *
+ ****************************************************************************/
+
+void lpc43_dmastop(DMA_HANDLE handle)
+{
+}
+
+/****************************************************************************
+ * Name: lpc43_dmasample
+ *
+ * Description:
+ *   Sample DMA register contents
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_DEBUG_DMA
+void lpc43_dmasample(DMA_HANDLE handle, struct lpc43_dmaregs_s *regs)
+{
+}
+#endif /* CONFIG_DEBUG_DMA */
+
+/****************************************************************************
+ * Name: lpc43_dmadump
+ *
+ * Description:
+ *   Dump previously sampled DMA register contents
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_DEBUG_DMA
+void lpc43_dmadump(DMA_HANDLE handle, const struct lpc43_dmaregs_s *regs, const char *msg)
+{
+}
+#endif /* CONFIG_DEBUG_DMA */
+
+#endif /* CONFIG_LPC43_GPDMA */
diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_gpdma.h b/nuttx/arch/arm/src/lpc43xx/lpc43_gpdma.h
new file mode 100644
index 000000000..68469d9b6
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/lpc43_gpdma.h
@@ -0,0 +1,236 @@
+/****************************************************************************
+ * arch/arm/src/lpc43xx/lpc43_gpdma.h
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LPC43XX_LP43_GPDMA_H
+#define __ARCH_ARM_SRC_LPC43XX_LP43_GPDMA_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include "chip/lpc43_gpdma.h"
+
+#ifdef CONFIG_LPC43_GPDMA
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+typedef FAR void *DMA_HANDLE;
+typedef void (*dma_callback_t)(DMA_HANDLE handle, void *arg, int result);
+
+/* The following is used for sampling DMA registers when CONFIG DEBUG_DMA is selected */
+
+#ifdef CONFIG_DEBUG_DMA
+struct lpc43_dmaglobalregs_s
+{
+  /* Global Registers */
+
+  uint32_t intst;       /* DMA Interrupt Status Register */
+  uint32_t inttcst;     /* DMA Interrupt Terminal Count Request Status Register */
+  uint32_t interrst;    /* DMA Interrupt Error Status Register */
+  uint32_t rawinttcst;  /* DMA Raw Interrupt Terminal Count Status Register */
+  uint32_t rawinterrst; /* DMA Raw Error Interrupt Status Register */
+  uint32_t enbldchns;   /* DMA Enabled Channel Register */
+  uint32_t softbreq;    /* DMA Software Burst Request Register */
+  uint32_t softsreq;    /* DMA Software Single Request Register */
+  uint32_t softlbreq;   /* DMA Software Last Burst Request Register */
+  uint32_t softlsreq;   /* DMA Software Last Single Request Register */
+  uint32_t config;      /* DMA Configuration Register */
+  uint32_t sync;        /* DMA Synchronization Register */
+};
+
+struct lpc43_dmachanregs_s
+{
+  /* Channel Registers */
+
+  uint32_t srcaddr;  /* DMA Channel Source Address Register */
+  uint32_t destaddr; /* DMA Channel Destination Address Register */
+  uint32_t lli;      /* DMA Channel Linked List Item Register */
+  uint32_t control;  /* DMA Channel Control Register */
+  uint32_t config;   /* DMA Channel Configuration Register */
+};
+
+struct lpc43_dmaregs_s
+{
+  /* Global Registers */
+
+  struct lpc43_dmaglobalregs_s gbl;
+
+  /* Channel Registers */
+
+  struct lpc43_dmachanregs_s   ch;
+};
+#endif
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C" {
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: lpc43_dmainitialize
+ *
+ * Description:
+ *   Initialize the GPDMA subsystem.
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+EXTERN void lpc43_dmainitilaize(void);
+
+/****************************************************************************
+ * Name: lpc43_dmachannel
+ *
+ * Description:
+ *   Allocate a DMA channel.  This function sets aside a DMA channel and
+ *   gives the caller exclusive access to the DMA channel.
+ *
+ * Returned Value:
+ *   One success, this function returns a non-NULL, void* DMA channel
+ *   handle.  NULL is returned on any failure.  This function can fail only
+ *   if no DMA channel is available.
+ *
+ ****************************************************************************/
+
+EXTERN DMA_HANDLE lpc43_dmachannel(void);
+
+/****************************************************************************
+ * Name: lpc43_dmafree
+ *
+ * Description:
+ *   Release a DMA channel.  NOTE:  The 'handle' used in this argument must
+ *   NEVER be used again until lpc43_dmachannel() is called again to re-gain
+ *   a valid handle.
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+EXTERN void lpc43_dmafree(DMA_HANDLE handle);
+
+/****************************************************************************
+ * Name: lpc43_dmasetup
+ *
+ * Description:
+ *   Configure DMA for one transfer.
+ *
+ ****************************************************************************/
+
+EXTERN int lpc43_dmarxsetup(DMA_HANDLE handle,
+                            uint32_t control, uint32_t config,
+                            uint32_t srcaddr, uint32_t destaddr,
+                            size_t nbytes);
+
+/****************************************************************************
+ * Name: lpc43_dmastart
+ *
+ * Description:
+ *   Start the DMA transfer
+ *
+ ****************************************************************************/
+
+EXTERN int lpc43_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg);
+
+/****************************************************************************
+ * Name: lpc43_dmastop
+ *
+ * Description:
+ *   Cancel the DMA.  After lpc43_dmastop() is called, the DMA channel is
+ *   reset and lpc43_dmasetup() must be called before lpc43_dmastart() can be
+ *   called again
+ *
+ ****************************************************************************/
+
+EXTERN void lpc43_dmastop(DMA_HANDLE handle);
+
+/****************************************************************************
+ * Name: lpc43_dmasample
+ *
+ * Description:
+ *   Sample DMA register contents
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_DEBUG_DMA
+EXTERN void lpc43_dmasample(DMA_HANDLE handle, struct lpc43_dmaregs_s *regs);
+#else
+#  define lpc43_dmasample(handle,regs)
+#endif
+
+/****************************************************************************
+ * Name: lpc43_dmadump
+ *
+ * Description:
+ *   Dump previously sampled DMA register contents
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_DEBUG_DMA
+EXTERN void lpc43_dmadump(DMA_HANDLE handle, const struct lpc43_dmaregs_s *regs,
+                          const char *msg);
+#else
+#  define lpc43_dmadump(handle,regs,msg)
+#endif
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* CONFIG_LPC43_GPDMA */
+#endif /* __ARCH_ARM_SRC_LPC43XX_LP43_GPDMA_H */
diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_gpio.c b/nuttx/arch/arm/src/lpc43xx/lpc43_gpio.c
new file mode 100644
index 000000000..2b2c88f31
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/lpc43_gpio.c
@@ -0,0 +1,251 @@
+/****************************************************************************
+ *  arch/arm/src/lpc43/lpc43_gpio.c
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <arch/board/board.h>
+#include <nuttx/config.h>
+
+#include <nuttx/arch.h>
+#include <errno.h>
+#include <debug.h>
+
+#include "up_arch.h"
+#include "lpc43_gpio.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: lpc43_configinput
+ *
+ * Description:
+ *   Configure a GPIO pin as an input (or pre-configured the pin for an
+ *   interrupt).
+ *
+ * Returned Value:
+ *   None
+ *
+ * Assumptions:
+ *   Interrupts are disabled so that read-modify-write operations are safe.
+ *
+ ****************************************************************************/
+
+static inline void lpc43_configinput(uint16_t gpiocfg,
+                                     unsigned int port, unsigned int pin)
+{
+  uintptr_t regaddr;
+  uint32_t regval;
+
+  /* Then configure the pin as a normal input by clearing the corresponding
+   * bit in the GPIO DIR register for the port.
+   */
+
+  regaddr = LPC43_GPIO_DIR(port);
+  regval  = getreg32(regaddr);
+  regval &= ~GPIO_DIR(pin);
+  putreg32(regval, regaddr);
+  
+  /* To be able to read the signal on the GPIO input, the input
+   * buffer must be enabled in the syscon block for the corresponding pin.
+   * This should have been done when the pin was configured as a GPIO.
+   */
+}
+
+/****************************************************************************
+ * Name: lpc43_configoutput
+ *
+ * Description:
+ *   Configure a GPIO pin as an output.
+ *
+ * Returned Value:
+ *   None
+ *
+ * Assumptions:
+ *   Interrupts are disabled so that read-modify-write operations are safe.
+ *
+ ****************************************************************************/
+
+static inline void lpc43_configoutput(uint16_t gpiocfg,
+                                      unsigned int port, unsigned int pin)
+{
+  uintptr_t regaddr;
+  uint32_t regval;
+
+  /* Then configure the pin as an output by setting the corresponding
+   * bit in the GPIO DIR register for the port.
+   */
+
+  regaddr = LPC43_GPIO_DIR(port);
+  regval  = getreg32(regaddr);
+  regval |= GPIO_DIR(pin);
+  putreg32(regval, regaddr);
+
+  /* Set the initial value of the output */
+
+  lpc43_gpio_write(gpiocfg, GPIO_IS_ONE(gpiocfg));
+
+  /* To be able to read the signal on the GPIO input, the input
+   * buffer must be enabled in the syscon block for the corresponding pin.
+   * This should have been done when the pin was configured as a GPIO.
+   */
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: lpc43_gpio_config
+ *
+ * Description:
+ *   Configure a GPIO based on bit-encoded description of the pin.  NOTE:
+ *   The pin *must* have first been configured for GPIO usage with a 
+ *   corresponding call to lpc43_pin_config().
+ *
+ * Returned Value:
+ *   OK on success; A negated errno value on failure.
+ *
+ ****************************************************************************/
+
+int lpc43_gpio_config(uint16_t gpiocfg)
+{
+  unsigned int port  = ((gpiocfg & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT);
+  unsigned int pin   = ((gpiocfg & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT);
+  irqstate_t   flags;
+  int          ret   = OK;
+
+  DEBUGASSERT(port < NUM_GPIO_PORTS && pin < NUM_GPIO_PINS);
+
+  /* Handle the GPIO configuration by the basic mode of the pin */
+
+  flags = irqsave();
+  switch (gpiocfg & GPIO_MODE_MASK)
+    {
+      case GPIO_MODE_INPUT:     /* GPIO input pin */
+        lpc43_configinput(gpiocfg, port, pin);
+        break;
+
+      case GPIO_MODE_OUTPUT:     /* GPIO output pin */
+        lpc43_configoutput(gpiocfg, port, pin);
+        break;
+
+      case GPIO_MODE_PININTR:    /* GPIO pin interrupt */
+        lpc43_configinput(gpiocfg, port, pin);
+#ifdef CONFIG_GPIO_IRQ
+        ret = lpc43_gpioint_pinconfig(gpiocfg);
+#endif
+        break;
+
+      case GPIO_MODE_GRPINTR:    /* GPIO group interrupt */
+        lpc43_configinput(gpiocfg, port, pin);
+#ifdef CONFIG_GPIO_IRQ
+        ret = lpc43_gpioint_grpconfig(gpiocfg);
+#endif
+        break;
+
+      default :
+        sdbg("ERROR: Unrecognized pin mode: %04x\n", gpiocfg);
+        ret = -EINVAL;
+        break;
+    }
+
+  irqrestore(flags);
+  return ret;
+}
+
+/****************************************************************************
+ * Name: lpc43_gpio_write
+ *
+ * Description:
+ *   Write one or zero to the selected GPIO pin
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+void lpc43_gpio_write(uint16_t gpiocfg, bool value)
+{
+  unsigned int port = ((gpiocfg & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT);
+  unsigned int pin  = ((gpiocfg & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT);
+
+  DEBUGASSERT(port < NUM_GPIO_PORTS && pin < NUM_GPIO_PINS);
+
+  /* Write the value (0 or 1).  To the pin byte register */
+
+  putreg8((uint8_t)value, LPC43_GPIO_B(port, pin));
+}
+
+/****************************************************************************
+ * Name: lpc43_gpio_read
+ *
+ * Description:
+ *   Read one or zero from the selected GPIO pin
+ *
+ * Returned Value:
+ *   The boolean state of the input pin
+ *
+ ****************************************************************************/
+
+bool lpc43_gpio_read(uint16_t gpiocfg)
+{
+  unsigned int port = ((gpiocfg & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT);
+  unsigned int pin  = ((gpiocfg & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT);
+
+  DEBUGASSERT(port < NUM_GPIO_PORTS && pin < NUM_GPIO_PINS);
+
+  /* Get the value of the pin from the pin byte register */
+
+  return (getreg8(LPC43_GPIO_B(port, pin)) & GPIO_B) != 0;
+}
+
+
+
diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_gpio.h b/nuttx/arch/arm/src/lpc43xx/lpc43_gpio.h
new file mode 100644
index 000000000..8f8460966
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/lpc43_gpio.h
@@ -0,0 +1,324 @@
+/********************************************************************************************
+ * arch/arm/src/lpc43xx/lpc43_gpio.h
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ********************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LPC43XX_GPIO_H
+#define __ARCH_ARM_SRC_LPC43XX_GPIO_H
+
+/********************************************************************************************
+ * Included Files
+ ********************************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/irq.h>
+
+/* Include the chip capabilities and GPIO definitions file */
+
+#include "chip.h"
+#include "chip/lpc43_gpio.h"
+
+/********************************************************************************************
+ * Pre-processor Definitions
+ ********************************************************************************************/
+
+/* Max number of GPIO ports and the maximum number of pins per port */
+
+#define NUM_GPIO_PORTS                8
+#define NUM_GPIO_PINS                 32
+#define NUM_GPIO_NGROUPS              2
+
+/* Each configurable pin can be individually configured by software in several modes. The
+ * following definitions provide the bit encoding that is used to define a pin configuration.
+ * Note that these pins do not corresponding GPIO ports and pins.
+ *
+ * 16-bit Encoding:
+ *                   1111 1100 0000 0000
+ *                   5432 1098 7654 3210
+ *                   ---- ---- ---- ----
+ * Normal GPIO:      MMV. .... PPPB BBBB
+ * Normal Interrupt: MMCC CIII PPPB BBBB
+ * Group  Interrupt: MM.N P... PPPB BBBB
+ */
+
+/* GPIO mode:
+ *
+ * 1111 1100 0000 0000
+ * 5432 1098 7654 3210
+ * ---- ---- ---- ----
+ * MM.. .... .... ....
+ */
+
+#define GPIO_MODE_SHIFT            (14)       /* Bits 14-15: Mode of the GPIO pin */
+#define GPIO_MODE_MASK             (3 << GPIO_MODE_SHIFT)
+#  define GPIO_MODE_INPUT          (0 << GPIO_MODE_SHIFT) /* GPIO input */
+#  define GPIO_MODE_OUTPUT         (1 << GPIO_MODE_SHIFT) /* GPIO output */
+#  define GPIO_MODE_PININTR        (2 << GPIO_MODE_SHIFT) /* GPIO pin interrupt */
+#  define GPIO_MODE_GRPINTR        (3 << GPIO_MODE_SHIFT) /* GPIO group interrupt */
+
+#define GPIO_IS_OUTPUT(p)          (((p) & GPIO_MODE_MASK) == GPIO_MODE_INPUT)
+#define GPIO_IS_INPUT(p)           (((p) & GPIO_MODE_MASK) == GPIO_MODE_OUTPUT)
+#define GPIO_IS_PININT(p)          (((p) & GPIO_MODE_MASK) == GPIO_MODE_PININTR)
+#define GPIO_IS_GRPINTR(p)         (((p) & GPIO_MODE_MASK) == GPIO_MODE_GRPINTR)
+
+/* Initial value (for GPIO outputs only)
+ *
+ * 1111 1100 0000 0000
+ * 5432 1098 7654 3210
+ * ---- ---- ---- ----
+ * ..V. .... .... ....
+ */
+
+#define GPIO_VALUE_ONE             (1 << 13) /* Bit 13: 1=High */
+#define GPIO_VALUE_ZERO            (0)       /* Bit 13: 0=Low */
+
+#define GPIO_IS_ONE(p)             (((p) & GPIO_VALUE_ONE) != 0)
+#define GPIO_IS_ZERO(p)            (((p) & GPIO_VALUE_ONE) == 0)
+
+/* Group Interrupt Group Selection (valid only for GPIO group interrupts):
+ *
+ * 1111 1100 0000 0000
+ * 5432 1098 7654 3210
+ * ---- ---- ---- ----
+ * ...N .... .... ....
+ */
+
+#define GPIO_GRPINT_GROUPNO        (1 << 12) /* Bit 12: 1=Member of group 1 */
+#define GPIO_GRPINT_GROUP0         (0)
+#define GPIO_GRPINT_GROUP1         GPIO_GRPINT_GROUPNO
+
+#define GPIO_IS_GROUP0(p)          (((p) & GPIO_GRPINT_GROUPNO) == 0)
+#define GPIO_IS_GROUP1(p)          (((p) & GPIO_GRPINT_GROUPNO) != 0)
+
+/* Group Interrupt Polarity (valid only for GPIO group interrupts):
+ *
+ * 1111 1100 0000 0000
+ * 5432 1098 7654 3210
+ * ---- ---- ---- ----
+ * .... P... .... ....
+ */
+
+#define GPIO_POLARITY              (1 << 11) /* Bit 11: Group Polarity */
+#define GPIO_POLARITY_HI           GPIO_POLARITY
+#define GPIO_POLARITY_LOW          0
+
+#define GPIO_IS_POLARITY_HI(p)     (((p) & GPIO_POLARITY) != 0)
+#define GPIO_IS_POLARITY_LOW(p)    (((p) & GPIO_POLARITY) == 0)
+
+/* Pin interrupt number (valid only for GPIO pin interrupts)
+ *
+ * 1111 1100 0000 0000
+ * 5432 1098 7654 3210
+ * ---- ---- ---- ----
+ * ..CC C... .... ....
+ */
+
+#define GPIO_PININT_SHIFT          (10)        /* Bits 11-13: Pin interrupt number */
+#define GPIO_PININT_MASK           (7 << GPIO_PININT_SHIFT)
+#  define GPIO_PININT0             (0 << GPIO_PININT_SHIFT)
+#  define GPIO_PININT1             (1 << GPIO_PININT_SHIFT)
+#  define GPIO_PININT2             (2 << GPIO_PININT_SHIFT)
+#  define GPIO_PININT3             (3 << GPIO_PININT_SHIFT)
+#  define GPIO_PININT4             (4 << GPIO_PININT_SHIFT)
+#  define GPIO_PININT5             (5 << GPIO_PININT_SHIFT)
+#  define GPIO_PININT6             (6 << GPIO_PININT_SHIFT)
+#  define GPIO_PININT7             (7 << GPIO_PININT_SHIFT)
+
+/* Pin interrupt configuration (valid only for GPIO pin interrupts)
+ *
+ * 1111 1100 0000 0000
+ * 5432 1098 7654 3210
+ * ---- ---- ---- ----
+ * .... .III .... ....
+ */
+
+#define _GPIO_INT_LEVEL            (1 << 10)  /* Bit 10: 1=Level (vs edge) */
+#define _GPIO_INT_HIGH             (1 << 9)   /* Bit 9:  1=High level or rising edge */
+#define _GPIO_INT_LOW              (1 << 8)   /* Bit 8:  1=Low level or falling edge */
+
+#define GPIO_INT_SHIFT             (8)        /* Bits 8-10: Interrupt mode */
+#define GPIO_INT_MASK              (7 << GPIO_INT_SHIFT)
+#  define GPIO_INT_LEVEL_HI        (1 << GPIO_INT_SHIFT) /* 001 Edge=NO  LOW=0 HIGH=1 */
+#  define GPIO_INT_LEVEL_LOW       (2 << GPIO_INT_SHIFT) /* 010 Edge=NO  LOW=1 HIGH=0 */
+#  define GPIO_INT_EDGE_RISING     (5 << GPIO_INT_SHIFT) /* 101 Edge=YES LOW=0 HIGH=1 */
+#  define GPIO_INT_EDGE_FALLING    (6 << GPIO_INT_SHIFT) /* 110 Edge=YES LOW=1 HIGH=0 */
+#  define GPIO_INT_EDGE_BOTH       (7 << GPIO_INT_SHIFT) /* 111 Edge=YES LOW=1 HIGH=1 */
+
+#define GPIO_IS_ACTIVE_HI(p)       (((p) & _GPIO_INT_HIGH)  != 0)
+#define GPIO_IS_ACTIVE_LOW(p)      (((p) & _GPIO_INT_LOW)   != 0)
+#define GPIO_IS_EDGE(p)            (((p) & _GPIO_INT_LEVEL) == 0)
+#define GPIO_IS_LEVEL(p)           (((p) & _GPIO_INT_LEVEL) != 0)
+
+/* GPIO Port Number:
+ *
+ * 1111 1100 0000 0000
+ * 5432 1098 7654 3210
+ * ---- ---- ---- ----
+ * .... .... PPP. ....
+ */
+
+#define GPIO_PORT_SHIFT            (5)        /* Bits 5-7: Port number */
+#define GPIO_PORT_MASK             (7 << GPIO_PORT_SHIFT)
+#  define GPIO_PORT0               (0 << GPIO_PORT_SHIFT)
+#  define GPIO_PORT1               (1 << GPIO_PORT_SHIFT)
+#  define GPIO_PORT2               (2 << GPIO_PORT_SHIFT)
+#  define GPIO_PORT3               (3 << GPIO_PORT_SHIFT)
+#  define GPIO_PORT4               (4 << GPIO_PORT_SHIFT)
+#  define GPIO_PORT5               (5 << GPIO_PORT_SHIFT)
+#  define GPIO_PORT6               (6 << GPIO_PORT_SHIFT)
+#  define GPIO_PORT7               (7 << GPIO_PORT_SHIFT)
+
+/* GPIO Pin Number:
+ *
+ * 1111 1100 0000 0000
+ * 5432 1098 7654 3210
+ * ---- ---- ---- ----
+ * .... .... ...B BBBB
+ */
+
+#define GPIO_PIN_SHIFT             (0)        /* Bits 0-5: Pin number */
+#define GPIO_PIN_MASK              (31 << GPIO_PIN_SHIFT)
+#  define GPIO_PIN0                (0 << GPIO_PIN_SHIFT)
+#  define GPIO_PIN1                (1 << GPIO_PIN_SHIFT)
+#  define GPIO_PIN2                (2 << GPIO_PIN_SHIFT)
+#  define GPIO_PIN3                (3 << GPIO_PIN_SHIFT)
+#  define GPIO_PIN4                (4 << GPIO_PIN_SHIFT)
+#  define GPIO_PIN5                (5 << GPIO_PIN_SHIFT)
+#  define GPIO_PIN6                (6 << GPIO_PIN_SHIFT)
+#  define GPIO_PIN7                (7 << GPIO_PIN_SHIFT)
+#  define GPIO_PIN8                (8 << GPIO_PIN_SHIFT)
+#  define GPIO_PIN9                (9 << GPIO_PIN_SHIFT)
+#  define GPIO_PIN10               (10 << GPIO_PIN_SHIFT)
+#  define GPIO_PIN11               (11 << GPIO_PIN_SHIFT)
+#  define GPIO_PIN12               (12 << GPIO_PIN_SHIFT)
+#  define GPIO_PIN13               (13 << GPIO_PIN_SHIFT)
+#  define GPIO_PIN14               (14 << GPIO_PIN_SHIFT)
+#  define GPIO_PIN15               (15 << GPIO_PIN_SHIFT)
+#  define GPIO_PIN16               (16 << GPIO_PIN_SHIFT)
+#  define GPIO_PIN17               (17 << GPIO_PIN_SHIFT)
+#  define GPIO_PIN18               (18 << GPIO_PIN_SHIFT)
+#  define GPIO_PIN19               (19 << GPIO_PIN_SHIFT)
+#  define GPIO_PIN20               (20 << GPIO_PIN_SHIFT)
+#  define GPIO_PIN21               (21 << GPIO_PIN_SHIFT)
+#  define GPIO_PIN22               (22 << GPIO_PIN_SHIFT)
+#  define GPIO_PIN23               (23 << GPIO_PIN_SHIFT)
+#  define GPIO_PIN24               (24 << GPIO_PIN_SHIFT)
+#  define GPIO_PIN25               (25 << GPIO_PIN_SHIFT)
+#  define GPIO_PIN26               (26 << GPIO_PIN_SHIFT)
+#  define GPIO_PIN27               (27 << GPIO_PIN_SHIFT)
+#  define GPIO_PIN28               (28 << GPIO_PIN_SHIFT)
+#  define GPIO_PIN29               (29 << GPIO_PIN_SHIFT)
+#  define GPIO_PIN30               (30 << GPIO_PIN_SHIFT)
+#  define GPIO_PIN31               (31 << GPIO_PIN_SHIFT)
+
+/********************************************************************************************
+ * Public Types
+ ********************************************************************************************/
+
+/********************************************************************************************
+ * Public Data
+ ********************************************************************************************/
+
+#ifndef __ASSEMBLY__
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C" {
+#else
+#define EXTERN extern
+#endif
+
+/********************************************************************************************
+ * Public Functions
+ ********************************************************************************************/
+
+/********************************************************************************************
+ * Name: lpc43_gpio_config
+ *
+ * Description:
+ *   Configure a GPIO based on bit-encoded description of the pin.  NOTE: The pin *must*
+ *   have first been configured for GPIO usage with a corresponding call to lpc43_pin_config.
+ *
+ * Returned Value:
+ *   OK on success; A negated errno value on failure.
+ *
+ ********************************************************************************************/
+
+EXTERN int lpc43_gpio_config(uint16_t gpiocfg);
+
+/********************************************************************************************
+ * Name: lpc43_gpio_write
+ *
+ * Description:
+ *   Write one or zero to the selected GPIO pin
+ *
+ * Returned Value:
+ *   None
+ *
+ ********************************************************************************************/
+
+EXTERN void lpc43_gpio_write(uint16_t gpiocfg, bool value);
+
+/********************************************************************************************
+ * Name: lpc43_gpio_read
+ *
+ * Description:
+ *   Read one or zero from the selected GPIO pin
+ *
+ * Returned Value:
+ *   The boolean state of the input pin
+ *
+ ********************************************************************************************/
+
+EXTERN bool lpc43_gpio_read(uint16_t gpiocfg);
+
+/********************************************************************************************
+ * Function:  lpc43_gpio_dump
+ *
+ * Description:
+ *   Dump all pin configuration registers associated with the provided base address
+ *
+ ********************************************************************************************/
+
+#ifdef CONFIG_DEBUG
+EXTERN int lpc43_gpio_dump(uint16_t gpiocfg, const char *msg);
+#else
+#  define lpc43_gpio_dump(p,m)
+#endif
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+#endif /* __ASSEMBLY__ */
+
+#endif /* __ARCH_ARM_SRC_LPC43XX_GPIO_H */
diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_gpioint.c b/nuttx/arch/arm/src/lpc43xx/lpc43_gpioint.c
new file mode 100644
index 000000000..d33d2dfa9
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/lpc43_gpioint.c
@@ -0,0 +1,317 @@
+/****************************************************************************
+ *  arch/arm/src/lpc43/lpc43_gpioint.c
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+/* GPIO pin interrupts
+ *
+ * From all available GPIO pins, up to eight pins can be selected in the system
+ * control block to serve as external interrupt pins. The external interrupt pins
+ * are connected to eight individual interrupts in the NVIC and are created based
+ * on rising or falling edges or on the input level on the pin.
+ *
+ * GPIO group interrupt
+ *
+ * For each port/pin connected to one of the two the GPIO Grouped Interrupt blocks
+ * (GROUP0 and GROUP1), the GPIO grouped interrupt registers determine which pins are
+ * enabled to generate interrupts and what the active polarities of each of those
+ * inputs are. The GPIO grouped interrupt registers also select whether the interrupt
+ * output will be level or edge triggered and whether it will be based on the OR or
+ * the AND of all of the enabled inputs.
+ */
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <arch/board/board.h>
+#include <nuttx/config.h>
+
+#include <nuttx/arch.h>
+#include <errno.h>
+
+#include "chip.h"
+#include "chip/lpc43_scu.h"
+#include "lpc43_gpioint.h"
+
+#ifdef CONFIG_GPIO_IRQ
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: lpc43_gpioint_grpinitialize
+ *
+ * Description:
+ *   Initialize the properties of a GPIO group.  The properties of the group
+ *   should be configured before any pins are added to the group by
+ *   lpc32_gpioint_grpconfig().  As side effects, this call also removes
+ *   all pins from the group and disables the group interrupt.  On return,
+ *   this is a properly configured, empty GPIO interrupt group.
+ *
+ * Returned Value:
+ *   Zero on success; a negated errno value on failure.
+ *
+ * Assumptions:
+ *   Interrupts are disabled so that read-modify-write operations are safe.
+ *
+ ****************************************************************************/
+
+int lpc43_gpioint_grpinitialize(int group, bool anded, bool level)
+{
+  irqstate_t flags;
+  uintptr_t grpbase;
+  uint32_t regval;
+  int i;
+
+  DEBUGASSERT(group >= 0 && group < NUM_GPIO_NGROUPS);
+
+  /* Select the group register base address and disable the group interrupt */
+
+  flags = irqsave();
+  if (group == 0)
+    {
+      grpbase = LPC43_GRP0INT_BASE;
+      up_disable_irq(LPC43M4_IRQ_GINT0);
+    }
+  else
+    {
+      grpbase = LPC43_GRP1INT_BASE;
+      up_disable_irq(LPC43M4_IRQ_GINT1);
+    }
+
+  /* Clear all group polarity and membership settings */
+
+  for (i = 0; i < NUM_GPIO_PORTS; i++)
+    {
+      putreg32(0, grpbase + LPC43_GRPINT_POL_OFFSET(i));
+      putreg32(0, grpbase + LPC43_GRPINT_ENA_OFFSET(i));
+    }
+
+  /* Configure the group.  Note that writing "1" to the status bit will also
+   * clear any pending group interrupts.
+   */
+
+  regval = GRPINT_CTRL_INT;
+  if (anded)
+    {
+      regval |= GRPINT_CTRL_COMB;
+    }
+
+  if (level)
+    {
+      regval |= GRPINT_CTRL_TRIG;
+    }
+  putreg32(regbal, grpbase + LPC43_GRP1INT_CTRL_OFFSET);
+
+  irqrestore(flags);
+  return OK;
+}
+
+/****************************************************************************
+ * Name: lpc43_gpioint_pinconfig
+ *
+ * Description:
+ *   Configure a GPIO pin as an GPIO pin interrupt source (after it has been
+ *   configured as an input).
+ *
+ * Returned Value:
+ *   Zero on success; a negated errno value on failure.
+ *
+ * Assumptions:
+ *   Interrupts are disabled so that read-modify-write operations are safe.
+ *
+ ****************************************************************************/
+
+int lpc43_gpioint_pinconfig(uint16_t gpiocfg)
+{
+  unsigned int port    = ((gpiocfg & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT);
+  unsigned int pin     = ((gpiocfg & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT);
+  unsigned int pinint  = ((gpiocfg & GPIO_PININT_MASK) >> GPIO_PININT_SHIFT);
+  uint32_t     bitmask = (1 << pinint);
+  uint32_t     regval;
+  int          ret     = OK;
+
+  DEBUGASSERT(port < NUM_GPIO_PORTS && pin < NUM_GPIO_PINS && GPIO_IS_PININT(gpiocfg));
+
+  /* Make sure that pin interrupts are initially disabled at the NVIC.
+   * After the pin is configured, the caller will need to manually enable
+   * the pin interrupt.
+   */
+
+  up_disable_irq(LPC43M4_IRQ_PININT0 + pinint);
+
+  /* Select the pin as the input in the SCU PINTSELn register (overwriting any
+   * previous selection).
+   */
+
+  if (pinint < 4)
+    {
+      regval = getreg32(LPC43_SCU_PINTSEL0);
+      regval &= ~SCU_PINTSEL0_MASK(pinint);
+      regval |= ((pin  << SCU_PINTSEL0_INTPIN_SHIFT(pinint)) |
+                 (port << SCU_PINTSEL0_PORTSEL_SHIFT(pinint)));
+      putreg32(regval, LPC43_SCU_PINTSEL0);
+    }
+  else
+    {
+      regval = getreg32(LPC43_SCU_PINTSEL1);
+      regval &= ~SCU_PINTSEL1_MASK(pinint);
+      regval |= ((pin  << SCU_PINTSEL1_INTPIN_SHIFT(pinint)) |
+                 (port << SCU_PINTSEL1_PORTSEL_SHIFT(pinint)));
+      putreg32(regval, LPC43_SCU_PINTSEL1);
+    }
+
+  /* Set level or edge sensitive */
+
+  regval = getreg32(LPC43_GPIOINT_ISEL);
+  if (GPIO_IS_LEVEL(gpiocfg))
+    {
+      regval |= bitmask;
+    }
+  else
+    {
+      regval &= ~bitmask;
+    }
+  putreg32(regval, LPC43_GPIOINT_ISEL);
+
+  /* Configure the active high level or rising edge */
+
+  regval = getreg32(LPC43_GPIOINT_IENR);
+  if (GPIO_IS_ACTIVE_HI(gpiocfg))
+    {
+      regval |= bitmask;
+    }
+  else
+    {
+      regval &= ~bitmask;
+    }
+  putreg32(regval, LPC43_GPIOINT_IENR);
+
+  /* Configure the active high low or falling edge */
+
+  regval = getreg32(LPC43_GPIOINT_IENF);
+  if (GPIO_IS_ACTIVE_LOW(gpiocfg))
+    {
+      regval |= bitmask;
+    }
+  else
+    {
+      regval &= ~bitmask;
+    }
+  putreg32(regval, LPC43_GPIOINT_IENF);
+
+  return OK;
+}
+
+/****************************************************************************
+ * Name: lpc43_gpioint_grpconfig
+ *
+ * Description:
+ *   Configure a GPIO pin as an GPIO group interrupt member (after it has been
+ *   configured as an input).
+ *
+ * Returned Value:
+ *   Zero on success; a negated errno value on failure.
+ *
+ * Assumptions:
+ *   Interrupts are disabled so that read-modify-write operations are safe.
+ *
+ ****************************************************************************/
+
+int lpc43_gpioint_grpconfig(uint16_t gpiocfg)
+{
+  unsigned int port    = ((gpiocfg & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT);
+  unsigned int pin     = ((gpiocfg & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT);
+  irqstate_t   flags;
+  uintptr_t    grpbase;
+  uintptr_t    regaddr;
+  uint32_t     regval;
+  uint32_t     bitmask = (1 << pin);
+  int          ret     = OK;
+
+  /* Select the group register base address */
+
+  flags = irqsave();
+  if (GPIO_IS_GROUP0(gpiocfg))
+    {
+      grpbase = LPC43_GRP0INT_BASE;
+    }
+  else
+    {
+      grpbase = LPC43_GRP1INT_BASE;
+    }
+
+  /* Set/clear the polarity for this pin */
+
+  regaddr = grpbase + LPC43_GRPINT_POL_OFFSET(port);
+  regval  = getreg32(regaddr);
+
+  if (GPIO_IS_POLARITY_HI(gpiocfg))
+    {
+      regval |= bitmask;
+    }
+  else
+    {
+      regval &= ~bitmask;
+    }
+
+  putreg32(regval, regaddr);
+
+  /* Set the corresponding bit in the port enable register so that this pin
+   * will contribute to the group interrupt.
+   */
+
+  regaddr = grpbase + LPC43_GRPINT_ENA_OFFSET(port);
+  regval  = getreg32(regaddr);
+  regval |= bitmask;
+  putreg32(regval, regaddr);
+
+  irqrestore(flags);
+  return OK;
+}
+
+#endif /* CONFIG_GPIO_IRQ */
+
diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_gpioint.h b/nuttx/arch/arm/src/lpc43xx/lpc43_gpioint.h
new file mode 100644
index 000000000..ef83d147f
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/lpc43_gpioint.h
@@ -0,0 +1,140 @@
+/************************************************************************************
+ * arch/arm/src/lpc43xx/lpc43_gpioint.h
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+/* GPIO pin interrupts
+ *
+ * From all available GPIO pins, up to eight pins can be selected in the system
+ * control block to serve as external interrupt pins. The external interrupt pins
+ * are connected to eight individual interrupts in the NVIC and are created based
+ * on rising or falling edges or on the input level on the pin.
+ *
+ * GPIO group interrupt
+ *
+ * For each port/pin connected to one of the two the GPIO Grouped Interrupt blocks
+ * (GROUP0 and GROUP1), the GPIO grouped interrupt registers determine which pins are
+ * enabled to generate interrupts and what the active polarities of each of those
+ * inputs are. The GPIO grouped interrupt registers also select whether the interrupt
+ * output will be level or edge triggered and whether it will be based on the OR or
+ * the AND of all of the enabled inputs.
+ */
+
+#ifndef __ARCH_ARM_SRC_LPC43XX_LPC43_GPIOINT_H
+#define __ARCH_ARM_SRC_LPC43XX_LPC43_GPIOINT_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+#include "chip.h"
+#include "chip/lpc43_gpio.h"
+
+#ifdef CONFIG_GPIO_IRQ
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+/****************************************************************************
+ * Name: lpc43_gpioint_grpinitialize
+ *
+ * Description:
+ *   Initialize the properties of a GPIO group.  The properties of the group
+ *   should be configured before any pins are added to the group by
+ *   lpc32_gpioint_grpconfig().  As side effects, this call also removes
+ *   all pins from the group and disables the group interrupt.  On return,
+ *   this is a properly configured, empty GPIO interrupt group.
+ *
+ * Returned Value:
+ *   Zero on success; a negated errno value on failure.
+ *
+ * Assumptions:
+ *   Interrupts are disabled so that read-modify-write operations are safe.
+ *
+ ****************************************************************************/
+
+EXTERN int lpc43_gpioint_grpinitialize(int group, bool anded, bool level);
+
+/****************************************************************************
+ * Name: lpc43_gpioint_pinconfig
+ *
+ * Description:
+ *   Configure a GPIO pin as an GPIO pin interrupt source (after it has been
+ *   configured as an input).  This function should *not* be called directly
+ *   from user application code; user code should call this function only
+ *   indirectly through lpc32_gpio_config().
+ *
+ * Returned Value:
+ *   Zero on success; a negated errno value on failure.
+ *
+ * Assumptions:
+ *   Interrupts are disabled so that read-modify-write operations are safe.
+ *
+ ****************************************************************************/
+
+EXTERN int lpc43_gpioint_pinconfig(uint16_t gpiocfg);
+
+/****************************************************************************
+ * Name: lpc43_gpioint_grpconfig
+ *
+ * Description:
+ *   Configure a GPIO pin as an GPIO group interrupt member (after it has been
+ *   configured as an input).  This function should *not* be called directly
+ *   from user application code; user code should call this function only
+ *   indirectly through lpc32_gpio_config().
+ *
+ * Returned Value:
+ *   Zero on success; a negated errno value on failure.
+ *
+ * Assumptions:
+ *   Interrupts are disabled so that read-modify-write operations are safe.
+ *
+ ****************************************************************************/
+
+EXTERN int lpc43_gpioint_grpconfig(uint16_t gpiocfg);
+
+#endif /* CONFIG_GPIO_IRQ */
+#endif /* __ARCH_ARM_SRC_LPC43XX_LPC43_GPIOINT_H */
diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_i2c.c b/nuttx/arch/arm/src/lpc43xx/lpc43_i2c.c
new file mode 100644
index 000000000..64a044f13
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/lpc43_i2c.c
@@ -0,0 +1,567 @@
+/*******************************************************************************
+ * arch/arm/src/lpc43xx/lpc43_i2c.c
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Ported from from the LPC17 version:
+ *
+ *   Copyright (C) 2011 Li Zhuoyi. All rights reserved.
+ *   Author: Li Zhuoyi <lzyy.cn@gmail.com>
+ *   History: 0.1 2011-08-20 initial version
+ *
+ * Derived from arch/arm/src/lpc31xx/lpc31_i2c.c
+ *
+ *   Author: David Hewson
+ *
+ *   Copyright (C) 2010-2011 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ *******************************************************************************/
+
+/*******************************************************************************
+ * Included Files
+ *******************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <stdlib.h>
+#include <string.h>
+#include <errno.h>
+#include <debug.h>
+
+#include <nuttx/arch.h>
+#include <nuttx/i2c.h>
+
+#include <arch/irq.h>
+#include <arch/board/board.h>
+
+#include "wdog.h"
+#include "chip.h"
+#include "up_arch.h"
+#include "up_internal.h"
+#include "os_internal.h"
+
+#include "lpc43_syscon.h"
+#include "lpc43_pinconn.h"
+#include "lpc43_i2c.h"
+
+#if defined(CONFIG_LPC43_I2C0) || defined(CONFIG_LPC43_I2C1)
+
+#ifndef GPIO_I2C1_SCL
+ #define GPIO_I2C1_SCL GPIO_I2C1_SCL_1
+ #define GPIO_I2C1_SDA GPIO_I2C1_SDA_1
+#endif
+#ifndef CONFIG_I2C0_FREQ
+ #define CONFIG_I2C0_FREQ 100000
+#endif
+#ifndef CONFIG_I2C1_FREQ
+ #define CONFIG_I2C1_FREQ 100000
+#endif
+#ifndef CONFIG_I2C2_FREQ
+ #define CONFIG_I2C2_FREQ 100000
+#endif
+
+/*******************************************************************************
+ * Definitions
+ *******************************************************************************/
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define I2C_TIMEOUT     ((20 * CLK_TCK) / 1000) /* 20 mS */
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+struct lpc43_i2cdev_s
+{
+  struct i2c_dev_s dev;        /* Generic I2C device */
+  struct i2c_msg_s msg;        /* a single message for legacy read/write */
+  unsigned int     base;       /* Base address of registers */
+  uint16_t         irqid;      /* IRQ for this device */
+
+  sem_t            mutex;      /* Only one thread can access at a time */
+  sem_t            wait;       /* Place to wait for state machine completion */
+  volatile uint8_t state;      /* State of state machine */
+  WDOG_ID          timeout;    /* watchdog to timeout when bus hung */
+
+  uint16_t         wrcnt;      /* number of bytes sent to tx fifo */
+  uint16_t         rdcnt;      /* number of bytes read from rx fifo */
+};
+
+#ifdef CONFIG_LPC43_I2C0
+static struct lpc43_i2cdev_s g_i2c0dev;
+#endif
+#ifdef CONFIG_LPC43_I2C1
+static struct lpc43_i2cdev_s g_i2c1dev;
+#endif
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+static int i2c_start(struct lpc43_i2cdev_s *priv);
+static void i2c_stop(struct lpc43_i2cdev_s *priv);
+static int  i2c_interrupt(int irq, FAR void *context);
+static void i2c_timeout(int argc, uint32_t arg, ...);
+
+/****************************************************************************
+ * I2C device operations
+ ****************************************************************************/
+
+static uint32_t i2c_setfrequency(FAR struct i2c_dev_s *dev,
+                                 uint32_t frequency);
+static int      i2c_setaddress(FAR struct i2c_dev_s *dev, int addr,
+                               int nbits);
+static int      i2c_write(FAR struct i2c_dev_s *dev, const uint8_t *buffer,
+                          int buflen);
+static int      i2c_read(FAR struct i2c_dev_s *dev, uint8_t *buffer,
+                         int buflen);
+static int      i2c_transfer(FAR struct i2c_dev_s *dev,
+                             FAR struct i2c_msg_s *msgs, int count);
+
+struct i2c_ops_s lpc43_i2c_ops =
+{
+  .setfrequency = i2c_setfrequency,
+  .setaddress   = i2c_setaddress,
+  .write        = i2c_write,
+  .read         = i2c_read,
+#ifdef CONFIG_I2C_TRANSFER
+  .transfer     = i2c_transfer
+#endif
+};
+
+/*******************************************************************************
+ * Name: lpc43_i2c_setfrequency
+ *
+ * Description:
+ *   Set the frequence for the next transfer
+ *
+ *******************************************************************************/
+
+static uint32_t i2c_setfrequency(FAR struct i2c_dev_s *dev, uint32_t frequency)
+{
+  struct lpc43_i2cdev_s *priv = (struct lpc43_i2cdev_s *) dev;
+
+  if (frequency > 100000)
+    {
+      /* asymetric per 400Khz I2C spec */
+
+      putreg32(LPC43_CCLK / (83 + 47) * 47 / frequency, priv->base + LPC43_I2C_SCLH_OFFSET);
+      putreg32(LPC43_CCLK / (83 + 47) * 83 / frequency, priv->base + LPC43_I2C_SCLL_OFFSET);
+    }
+  else
+    {
+      /* 50/50 mark space ratio */
+
+      putreg32(LPC43_CCLK / 100 * 50 / frequency, priv->base + LPC43_I2C_SCLH_OFFSET);
+      putreg32(LPC43_CCLK / 100 * 50 / frequency, priv->base + LPC43_I2C_SCLL_OFFSET);
+    }
+
+  /* FIXME: This function should return the actual selected frequency */
+
+  return frequency;
+}
+
+/*******************************************************************************
+ * Name: lpc43_i2c_setaddress
+ *
+ * Description:
+ *   Set the I2C slave address for a subsequent read/write
+ *
+ *******************************************************************************/
+
+static int i2c_setaddress(FAR struct i2c_dev_s *dev, int addr, int nbits)
+{
+  struct lpc43_i2cdev_s *priv = (struct lpc43_i2cdev_s *)dev;
+
+  DEBUGASSERT(dev != NULL);
+  DEBUGASSERT(nbits == 7);
+
+  priv->msg.addr  = addr << 1;
+  priv->msg.flags = 0 ;
+
+  return OK;
+}
+
+/*******************************************************************************
+ * Name: lpc43_i2c_write
+ *
+ * Description:
+ *   Send a block of data on I2C using the previously selected I2C
+ *   frequency and slave address.
+ *
+ *******************************************************************************/
+
+static int i2c_write(FAR struct i2c_dev_s *dev, const uint8_t *buffer,
+                     int buflen)
+{
+  struct lpc43_i2cdev_s *priv = (struct lpc43_i2cdev_s *)dev;
+  int ret;
+
+  DEBUGASSERT(dev != NULL);
+
+  priv->wrcnt      = 0;
+  priv->rdcnt      = 0;
+  priv->msg.addr  &= ~0x01;
+  priv->msg.buffer = (uint8_t*)buffer;
+  priv->msg.length = buflen;
+
+  ret = i2c_start(priv);
+
+  return ret > 0 ? OK : -ETIMEDOUT;
+}
+
+/*******************************************************************************
+ * Name: lpc43_i2c_read
+ *
+ * Description:
+ *   Receive a block of data on I2C using the previously selected I2C
+ *   frequency and slave address.
+ *
+ *******************************************************************************/
+
+static int i2c_read(FAR struct i2c_dev_s *dev, uint8_t *buffer, int buflen)
+{
+  struct lpc43_i2cdev_s *priv = (struct lpc43_i2cdev_s *)dev;
+  int ret;
+
+  DEBUGASSERT(dev != NULL);
+
+  priv->wrcnt=0;
+  priv->rdcnt=0;
+  priv->msg.addr |= 0x01;
+  priv->msg.buffer = buffer;
+  priv->msg.length = buflen;
+
+  ret = i2c_start(priv);
+
+  return ret >0 ? OK : -ETIMEDOUT;
+}
+
+/*******************************************************************************
+ * Name: i2c_start
+ *
+ * Description:
+ *   Perform a I2C transfer start
+ *
+ *******************************************************************************/
+
+static int i2c_start(struct lpc43_i2cdev_s *priv)
+{
+  int ret = -1;
+
+  sem_wait(&priv->mutex);
+
+  putreg32(I2C_CONCLR_STAC|I2C_CONCLR_SIC,priv->base+LPC43_I2C_CONCLR_OFFSET);
+  putreg32(I2C_CONSET_STA,priv->base+LPC43_I2C_CONSET_OFFSET);
+
+  wd_start(priv->timeout, I2C_TIMEOUT, i2c_timeout, 1, (uint32_t)priv);
+  sem_wait(&priv->wait);
+  wd_cancel(priv->timeout);
+  sem_post(&priv->mutex);
+
+  if (priv-> state == 0x18 || priv->state == 0x28)
+    {
+      ret = priv->wrcnt;
+    }
+  else if (priv-> state == 0x50 || priv->state == 0x58)
+    {
+      ret = priv->rdcnt;
+    }
+
+  return ret;
+}
+
+/*******************************************************************************
+ * Name: i2c_stop
+ *
+ * Description:
+ *   Perform a I2C transfer stop
+ *
+ *******************************************************************************/
+
+static void i2c_stop(struct lpc43_i2cdev_s *priv)
+{
+  if (priv->state != 0x38)
+    {
+      putreg32(I2C_CONSET_STO|I2C_CONSET_AA,priv->base+LPC43_I2C_CONSET_OFFSET);
+    }
+
+  sem_post(&priv->wait);
+}
+
+/*******************************************************************************
+ * Name: i2c_timeout
+ *
+ * Description:
+ *   Watchdog timer for timeout of I2C operation
+ *
+ *******************************************************************************/
+
+static void i2c_timeout(int argc, uint32_t arg, ...)
+{
+  struct lpc43_i2cdev_s *priv = (struct lpc43_i2cdev_s *)arg;
+
+  irqstate_t flags = irqsave();
+  priv->state = 0xff;
+  sem_post(&priv->wait);
+  irqrestore(flags);
+}
+
+/*******************************************************************************
+ * Name: i2c_interrupt
+ *
+ * Description:
+ *   The I2C Interrupt Handler
+ *
+ *******************************************************************************/
+
+static int i2c_interrupt(int irq, FAR void *context)
+{
+  struct lpc43_i2cdev_s *priv;
+  uint32_t state;
+
+#ifdef CONFIG_LPC43_I2C0
+  if (irq == LPC43_IRQ_I2C0)
+    {
+      priv = &g_i2c0dev;
+    }
+  else
+#endif
+#ifdef CONFIG_LPC43_I2C1
+  if (irq == LPC43_IRQ_I2C1)
+    {
+      priv = &g_i2c1dev;
+    }
+    else
+#endif
+    {
+      PANIC(OSERR_INTERNAL);
+    }
+
+  /* Reference UM10360 19.10.5 */
+
+  state = getreg32(priv->base+LPC43_I2C_STAT_OFFSET);
+  putreg32(I2C_CONCLR_SIC, priv->base + LPC43_I2C_CONCLR_OFFSET);
+
+  priv->state = state;
+  state &= 0xf8;
+  switch (state)
+    {
+    case 0x00:      /* Bus Error */
+    case 0x20:
+    case 0x30:
+    case 0x38:
+    case 0x48:
+      i2c_stop(priv);
+      break;
+
+    case 0x08:     /* START */
+    case 0x10:     /* Repeated START */
+      putreg32(priv->msg.addr, priv->base + LPC43_I2C_DAT_OFFSET);
+      putreg32(I2C_CONCLR_STAC, priv->base + LPC43_I2C_CONCLR_OFFSET);
+      break;
+
+    case 0x18:
+      priv->wrcnt=0;
+      putreg32(priv->msg.buffer[0], priv->base + LPC43_I2C_DAT_OFFSET);
+      break;
+
+    case 0x28:
+      priv->wrcnt++;
+      if (priv->wrcnt < priv->msg.length)
+        {
+          putreg32(priv->msg.buffer[priv->wrcnt],priv->base+LPC43_I2C_DAT_OFFSET);
+        }
+      else
+        {
+          i2c_stop(priv);
+        }
+      break;
+
+    case 0x40:
+      priv->rdcnt = -1;
+      putreg32(I2C_CONSET_AA, priv->base + LPC43_I2C_CONSET_OFFSET);
+      break;
+
+    case 0x50:
+      priv->rdcnt++;
+      if (priv->rdcnt < priv->msg.length)
+        {
+          priv->msg.buffer[priv->rdcnt]=getreg32(priv->base+LPC43_I2C_BUFR_OFFSET);
+        }
+
+      if (priv->rdcnt >= priv->msg.length - 1)
+        {
+          putreg32(I2C_CONCLR_AAC|I2C_CONCLR_SIC,priv->base+LPC43_I2C_CONCLR_OFFSET);
+        }
+      break;
+
+    case 0x58:
+      i2c_stop(priv);
+      break;
+
+    default:
+      i2c_stop(priv);
+      break;
+    }
+
+  return OK;
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/*******************************************************************************
+ * Name: up_i2cinitialize
+ *
+ * Description:
+ *   Initialise an I2C device
+ *
+ *******************************************************************************/
+
+struct i2c_dev_s *up_i2cinitialize(int port)
+{
+  struct lpc43_i2cdev_s *priv;
+
+  if (port>2)
+    {
+      dbg("lpc I2C Only support 0,1,2\n");
+      return NULL;
+    }
+
+  irqstate_t flags;
+  uint32_t regval;
+
+  flags = irqsave();
+
+#ifdef CONFIG_LPC43_I2C0
+  if (port == 0)
+    {
+      priv        = &g_i2c0dev;
+      priv->base  = LPC43_I2C0_BASE;
+      priv->irqid = LPC43_IRQ_I2C0;
+
+      regval  = getreg32(LPC43_SYSCON_PCONP);
+      regval |= SYSCON_PCONP_PCI2C0;
+      putreg32(regval, LPC43_SYSCON_PCONP);
+
+      regval  = getreg32(LPC43_SYSCON_PCLKSEL0);
+      regval &= ~SYSCON_PCLKSEL0_I2C0_MASK;
+      regval |= (SYSCON_PCLKSEL_CCLK << SYSCON_PCLKSEL0_I2C0_SHIFT);
+      putreg32(regval, LPC43_SYSCON_PCLKSEL0);
+
+      lpc43_configgpio(GPIO_I2C0_SCL);
+      lpc43_configgpio(GPIO_I2C0_SDA);
+
+      putreg32(LPC43_CCLK/CONFIG_I2C0_FREQ/2, priv->base + LPC43_I2C_SCLH_OFFSET);
+      putreg32(LPC43_CCLK/CONFIG_I2C0_FREQ/2, priv->base + LPC43_I2C_SCLL_OFFSET);
+    }
+  else
+#endif
+#ifdef CONFIG_LPC43_I2C1
+  if (port == 1)
+    {
+      priv        = &g_i2c1dev;
+      priv->base  = LPC43_I2C1_BASE;
+      priv->irqid = LPC43_IRQ_I2C1;
+
+      regval  = getreg32(LPC43_SYSCON_PCONP);
+      regval |= SYSCON_PCONP_PCI2C1;
+      putreg32(regval, LPC43_SYSCON_PCONP);
+
+      regval  = getreg32(LPC43_SYSCON_PCLKSEL1);
+      regval &= ~SYSCON_PCLKSEL1_I2C1_MASK;
+      regval |= (SYSCON_PCLKSEL_CCLK << SYSCON_PCLKSEL1_I2C1_SHIFT);
+      putreg32(regval, LPC43_SYSCON_PCLKSEL1);
+
+      lpc43_configgpio(GPIO_I2C1_SCL);
+      lpc43_configgpio(GPIO_I2C1_SDA);
+
+      putreg32(LPC43_CCLK/CONFIG_I2C1_FREQ/2, priv->base + LPC43_I2C_SCLH_OFFSET);
+      putreg32(LPC43_CCLK/CONFIG_I2C1_FREQ/2, priv->base + LPC43_I2C_SCLL_OFFSET);
+    }
+  else
+#endif
+    {
+        return NULL;
+    }
+
+  putreg32(I2C_CONSET_I2EN,priv->base+LPC43_I2C_CONSET_OFFSET);
+
+  sem_init(&priv->mutex, 0, 1);
+  sem_init(&priv->wait, 0, 0);
+
+  /* Allocate a watchdog timer */
+
+  priv->timeout = wd_create();
+  DEBUGASSERT(priv->timeout != 0);
+
+  /* Attach Interrupt Handler */
+
+  irq_attach(priv->irqid, i2c_interrupt);
+
+  /* Enable Interrupt Handler */
+
+  up_enable_irq(priv->irqid);
+
+  /* Install our operations */
+
+  priv->dev.ops = &lpc43_i2c_ops;
+  return &priv->dev;
+}
+
+/*******************************************************************************
+ * Name: up_i2cuninitalize
+ *
+ * Description:
+ *   Uninitialise an I2C device
+ *
+ *******************************************************************************/
+
+int up_i2cuninitialize(FAR struct i2c_dev_s * dev)
+{
+  struct lpc43_i2cdev_s *priv = (struct lpc43_i2cdev_s *) dev;
+
+  putreg32(I2C_CONCLRT_I2ENC,priv->base+LPC43_I2C_CONCLR_OFFSET);
+  up_disable_irq(priv->irqid);
+  irq_detach(priv->irqid);
+  return OK;
+}
+
+#endif
diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_idle.c b/nuttx/arch/arm/src/lpc43xx/lpc43_idle.c
new file mode 100644
index 000000000..72541eed8
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/lpc43_idle.c
@@ -0,0 +1,187 @@
+/****************************************************************************
+ *  arch/arm/src/lpc43/lpc43_idle.c
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <arch/board/board.h>
+#include <nuttx/config.h>
+
+#include <nuttx/arch.h>
+#include <nuttx/power/pm.h>
+
+#include <arch/irq.h>
+
+#include "up_internal.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Does the board support an IDLE LED to indicate that the board is in the
+ * IDLE state?
+ */
+
+#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE)
+#  define BEGIN_IDLE() up_ledon(LED_IDLE)
+#  define END_IDLE()   up_ledoff(LED_IDLE)
+#else
+#  define BEGIN_IDLE()
+#  define END_IDLE()
+#endif
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_idlepm
+ *
+ * Description:
+ *   Perform IDLE state power management.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_PM
+static void up_idlepm(void)
+{
+  static enum pm_state_e oldstate = PM_NORMAL;
+  enum pm_state_e newstate;
+  irqstate_t flags;
+  int ret;
+  
+  /* Decide, which power saving level can be obtained */
+
+  newstate = pm_checkstate();
+
+  /* Check for state changes */
+
+  if (newstate != oldstate)
+    {
+      flags = irqsave();
+
+      /* Perform board-specific, state-dependent logic here */
+
+      llvdbg("newstate= %d oldstate=%d\n", newstate, oldstate);
+
+      /* Then force the global state change */
+
+      ret = pm_changestate(newstate);
+      if (ret < 0)
+        {
+          /* The new state change failed, revert to the preceding state */
+
+          (void)pm_changestate(oldstate);
+        }
+      else
+        {
+          /* Save the new state */
+
+          oldstate = newstate;
+        }
+
+      /* MCU-specific power management logic */
+
+      switch (newstate)
+        {
+        case PM_NORMAL:
+          break;
+
+        case PM_IDLE:
+          break;
+
+        case PM_STANDBY:
+          lpc43_pmstandby(true);
+          break;
+
+        case PM_SLEEP:
+          (void)lpc43_pmsleep();
+          break;
+
+        default:
+          break;
+        }
+
+      irqrestore(flags);
+    }
+}
+#else
+#  define up_idlepm()
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_idle
+ *
+ * Description:
+ *   up_idle() is the logic that will be executed when their is no other
+ *   ready-to-run task.  This is processor idle time and will continue until
+ *   some interrupt occurs to cause a context switch from the idle task.
+ *
+ *   Processing in this state may be processor-specific. e.g., this is where
+ *   power management operations might be performed.
+ *
+ ****************************************************************************/
+
+void up_idle(void)
+{
+#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS)
+  /* If the system is idle and there are no timer interrupts, then process
+   * "fake" timer interrupts. Hopefully, something will wake up.
+   */
+
+  sched_process_timer();
+#else
+
+  /* Perform IDLE mode power management */
+
+  up_idlepm();
+
+  /* Sleep until an interrupt occurs to save power */
+
+  BEGIN_IDLE();
+  asm("WFI");
+  END_IDLE();
+#endif
+}
+
diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_irq.c b/nuttx/arch/arm/src/lpc43xx/lpc43_irq.c
new file mode 100644
index 000000000..9cbb8238c
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/lpc43_irq.c
@@ -0,0 +1,503 @@
+/****************************************************************************
+ * arch/arm/src/lpc43/lpc43_irq.c
+ * arch/arm/src/chip/lpc43_irq.c
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <debug.h>
+
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+#include <arch/irq.h>
+
+#include "chip.h"
+#include "nvic.h"
+#include "up_arch.h"
+#include "os_internal.h"
+#include "up_internal.h"
+
+#include "lpc43_irq.h"
+
+/****************************************************************************
+ * Definitions
+ ****************************************************************************/
+
+/* Get a 32-bit version of the default priority */
+
+#define DEFPRIORITY32 \
+  (LPC43M4_SYSH_PRIORITY_DEFAULT << 24 |\
+   LPC43M4_SYSH_PRIORITY_DEFAULT << 16 |\
+   LPC43M4_SYSH_PRIORITY_DEFAULT << 8  |\
+   LPC43M4_SYSH_PRIORITY_DEFAULT)
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+volatile uint32_t *current_regs;
+
+/* This is the address of the vector table */
+
+extern unsigned _vectors[];
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: lpc43_dumpnvic
+ *
+ * Description:
+ *   Dump some interesting NVIC registers
+ *
+ ****************************************************************************/
+
+#if defined(CONFIG_DEBUG_IRQ) && defined (CONFIG_DEBUG)
+static void lpc43_dumpnvic(const char *msg, int irq)
+{
+  irqstate_t flags;
+
+  flags = irqsave();
+  slldbg("NVIC (%s, irq=%d):\n", msg, irq);
+  slldbg("  INTCTRL:    %08x VECTAB: %08x\n",
+         getreg32(NVIC_INTCTRL), getreg32(NVIC_VECTAB));
+#if 0
+  slldbg("  SYSH ENABLE MEMFAULT: %08x BUSFAULT: %08x USGFAULT: %08x SYSTICK: %08x\n",
+         getreg32(NVIC_SYSHCON_MEMFAULTENA), getreg32(NVIC_SYSHCON_BUSFAULTENA),
+         getreg32(NVIC_SYSHCON_USGFAULTENA), getreg32(NVIC_SYSTICK_CTRL_ENABLE));
+#endif
+  slldbg("  IRQ ENABLE: %08x %08x\n",
+         getreg32(NVIC_IRQ0_31_ENABLE), getreg32(NVIC_IRQ32_63_ENABLE));
+  slldbg("  SYSH_PRIO:  %08x %08x %08x\n",
+         getreg32(NVIC_SYSH4_7_PRIORITY), getreg32(NVIC_SYSH8_11_PRIORITY),
+         getreg32(NVIC_SYSH12_15_PRIORITY));
+  slldbg("  IRQ PRIO:   %08x %08x %08x %08x\n", 
+        getreg32(NVIC_IRQ0_3_PRIORITY), getreg32(NVIC_IRQ4_7_PRIORITY),
+        getreg32(NVIC_IRQ8_11_PRIORITY), getreg32(NVIC_IRQ12_15_PRIORITY));
+  slldbg("              %08x %08x %08x %08x\n", 
+        getreg32(NVIC_IRQ16_19_PRIORITY), getreg32(NVIC_IRQ20_23_PRIORITY),
+        getreg32(NVIC_IRQ24_27_PRIORITY), getreg32(NVIC_IRQ28_31_PRIORITY));
+  slldbg("              %08x %08x %08x %08x\n", 
+        getreg32(NVIC_IRQ32_35_PRIORITY), getreg32(NVIC_IRQ36_39_PRIORITY),
+        getreg32(NVIC_IRQ40_43_PRIORITY), getreg32(NVIC_IRQ44_47_PRIORITY));
+  slldbg("              %08x %08x %08x\n", 
+        getreg32(NVIC_IRQ48_51_PRIORITY), getreg32(NVIC_IRQ52_55_PRIORITY),
+        getreg32(NVIC_IRQ56_59_PRIORITY));
+  irqrestore(flags);
+}
+#else
+#  define lpc43_dumpnvic(msg, irq)
+#endif
+
+/****************************************************************************
+ * Name: lpc43_nmi, lpc43_busfault, lpc43_usagefault, lpc43_pendsv,
+ *       lpc43_dbgmonitor, lpc43_pendsv, lpc43_reserved
+ *
+ * Description:
+ *   Handlers for various execptions.  None are handled and all are fatal
+ *   error conditions.  The only advantage these provided over the default
+ *   unexpected interrupt handler is that they provide a diagnostic output.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_DEBUG
+static int lpc43_nmi(int irq, FAR void *context)
+{
+  (void)irqsave();
+  dbg("PANIC!!! NMI received\n");
+  PANIC(OSERR_UNEXPECTEDISR);
+  return 0;
+}
+
+static int lpc43_busfault(int irq, FAR void *context)
+{
+  (void)irqsave();
+  dbg("PANIC!!! Bus fault recived\n");
+  PANIC(OSERR_UNEXPECTEDISR);
+  return 0;
+}
+
+static int lpc43_usagefault(int irq, FAR void *context)
+{
+  (void)irqsave();
+  dbg("PANIC!!! Usage fault received\n");
+  PANIC(OSERR_UNEXPECTEDISR);
+  return 0;
+}
+
+static int lpc43_pendsv(int irq, FAR void *context)
+{
+  (void)irqsave();
+  dbg("PANIC!!! PendSV received\n");
+  PANIC(OSERR_UNEXPECTEDISR);
+  return 0;
+}
+
+static int lpc43_dbgmonitor(int irq, FAR void *context)
+{
+  (void)irqsave();
+  dbg("PANIC!!! Debug Monitor receieved\n");
+  PANIC(OSERR_UNEXPECTEDISR);
+  return 0;
+}
+
+static int lpc43_reserved(int irq, FAR void *context)
+{
+  (void)irqsave();
+  dbg("PANIC!!! Reserved interrupt\n");
+  PANIC(OSERR_UNEXPECTEDISR);
+  return 0;
+}
+#endif
+
+/****************************************************************************
+ * Name: lpc43_irqinfo
+ *
+ * Description:
+ *   Given an IRQ number, provide the register and bit setting to enable or
+ *   disable the irq.
+ *
+ ****************************************************************************/
+
+static int lpc43_irqinfo(int irq, uint32_t *regaddr, uint32_t *bit)
+{
+  DEBUGASSERT(irq >= LPC43_IRQ_NMI && irq < NR_IRQS);
+
+  /* Check for external interrupt */
+
+  if (irq >= LPC43_IRQ_EXTINT)
+    {
+      if (irq < (LPC43_IRQ_EXTINT + 32))
+        {
+           *regaddr = NVIC_IRQ0_31_ENABLE;
+           *bit     = 1 << (irq - LPC43_IRQ_EXTINT);
+        }
+      else if (irq < LPC43M4_IRQ_NIRQS)
+        {
+           *regaddr = NVIC_IRQ32_63_ENABLE;
+           *bit     = 1 << (irq - LPC43_IRQ_EXTINT - 32);
+        }
+      else
+        {
+          return ERROR; /* Invalid interrupt */
+        }
+    }
+
+  /* Handle processor exceptions.  Only a few can be disabled */
+
+  else
+    {
+       *regaddr = NVIC_SYSHCON;
+       if (irq == LPC43_IRQ_MEMFAULT)
+        {
+          *bit = NVIC_SYSHCON_MEMFAULTENA;
+        }
+      else if (irq == LPC43_IRQ_BUSFAULT)
+        {
+          *bit = NVIC_SYSHCON_BUSFAULTENA;
+        }
+      else if (irq == LPC43_IRQ_USAGEFAULT)
+        {
+          *bit = NVIC_SYSHCON_USGFAULTENA;
+        }
+      else if (irq == LPC43_IRQ_SYSTICK)
+        {
+          *regaddr = NVIC_SYSTICK_CTRL;
+          *bit = NVIC_SYSTICK_CTRL_ENABLE;
+        }
+      else
+        {
+          return ERROR; /* Invalid or unsupported exception */
+        }
+    }
+
+  return OK;
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_irqinitialize
+ *
+ * Description:
+ *   Complete initialization of the interrupt system and enable normal,
+ *   interrupt processing.
+ *
+ ****************************************************************************/
+
+void up_irqinitialize(void)
+{
+  uint32_t regaddr;
+#ifdef CONFIG_DEBUG
+  uint32_t regval;
+#endif
+  int num_priority_registers;
+
+  /* Disable all interrupts */
+
+  putreg32(0, NVIC_IRQ0_31_ENABLE);
+  putreg32(0, NVIC_IRQ32_63_ENABLE);
+
+  /* Make sure that we are using the correct vector table.  The default
+   * vector address is 0x0000:0000 but if we are executing code that is
+   * positioned in SRAM or in external FLASH, then we may need to reset
+   * the interrupt vector so that it refers to the table in SRAM or in
+   * external FLASH.
+   */
+
+  putreg32((uint32_t)_vectors, NVIC_VECTAB);
+
+  /* Set all interrupts (and exceptions) to the default priority */
+
+  putreg32(DEFPRIORITY32, NVIC_SYSH4_7_PRIORITY);
+  putreg32(DEFPRIORITY32, NVIC_SYSH8_11_PRIORITY);
+  putreg32(DEFPRIORITY32, NVIC_SYSH12_15_PRIORITY);
+
+  /* The NVIC ICTR register (bits 0-4) holds the number of of interrupt
+   * lines that the NVIC supports:
+   *
+   *  0 -> 32 interrupt lines,  8 priority registers
+   *  1 -> 64 "       " "   ", 16 priority registers
+   *  2 -> 96 "       " "   ", 32 priority registers
+   *  ...
+   */
+
+  num_priority_registers = (getreg32(NVIC_ICTR) + 1) * 8;
+
+  /* Now set all of the interrupt lines to the default priority */
+
+  regaddr = NVIC_IRQ0_3_PRIORITY;
+  while (num_priority_registers--)
+    {
+      putreg32(DEFPRIORITY32, regaddr);
+      regaddr += 4;
+    }
+
+  /* currents_regs is non-NULL only while processing an interrupt */
+
+  current_regs = NULL;
+
+  /* Attach the SVCall and Hard Fault exception handlers.  The SVCall
+   * exception is used for performing context switches; The Hard Fault
+   * must also be caught because a SVCall may show up as a Hard Fault
+   * under certain conditions.
+   */
+
+  irq_attach(LPC43_IRQ_SVCALL, up_svcall);
+  irq_attach(LPC43_IRQ_HARDFAULT, up_hardfault);
+
+  /* Set the priority of the SVCall interrupt */
+
+#ifdef CONFIG_ARCH_IRQPRIO
+/* up_prioritize_irq(LPC43_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */
+#endif
+
+  /* If the MPU is enabled, then attach and enable the Memory Management
+   * Fault handler.
+   */
+
+#ifdef CONFIG_ARMV7M_MPU
+  irq_attach(LPC43_IRQ_MEMFAULT, up_memfault);
+  up_enable_irq(LPC43_IRQ_MEMFAULT);
+#endif
+
+  /* Attach all other processor exceptions (except reset and sys tick) */
+
+#ifdef CONFIG_DEBUG
+  irq_attach(LPC43_IRQ_NMI, lpc43_nmi);
+#ifndef CONFIG_ARMV7M_MPU
+  irq_attach(LPC43_IRQ_MEMFAULT, up_memfault);
+#endif
+  irq_attach(LPC43_IRQ_BUSFAULT, lpc43_busfault);
+  irq_attach(LPC43_IRQ_USAGEFAULT, lpc43_usagefault);
+  irq_attach(LPC43_IRQ_PENDSV, lpc43_pendsv);
+  irq_attach(LPC43_IRQ_DBGMONITOR, lpc43_dbgmonitor);
+  irq_attach(LPC43_IRQ_RESERVED, lpc43_reserved);
+#endif
+
+  lpc43_dumpnvic("initial", LPC43M4_IRQ_NIRQS);
+
+  /* If a debugger is connected, try to prevent it from catching hardfaults */
+
+#ifdef CONFIG_DEBUG
+  regval  = getreg32(NVIC_DEMCR);
+  regval &= ~NVIC_DEMCR_VCHARDERR;
+  putreg32(regval, NVIC_DEMCR);
+#endif
+
+  /* And finally, enable interrupts */
+
+#ifndef CONFIG_SUPPRESS_INTERRUPTS
+  setbasepri(LPC43M4_SYSH_PRIORITY_MAX);
+  irqrestore(0);
+#endif
+}
+
+/****************************************************************************
+ * Name: up_disable_irq
+ *
+ * Description:
+ *   Disable the IRQ specified by 'irq'
+ *
+ ****************************************************************************/
+
+void up_disable_irq(int irq)
+{
+  uint32_t regaddr;
+  uint32_t regval;
+  uint32_t bit;
+
+  if (lpc43_irqinfo(irq, &regaddr, &bit) == 0)
+    {
+      /* Clear the appropriate bit in the register to enable the interrupt */
+
+      regval  = getreg32(regaddr);
+      regval &= ~bit;
+      putreg32(regval, regaddr);
+    }
+#ifdef CONFIG_GPIO_IRQ
+  else if (irq >= LPC43_VALID_FIRST0L)
+    {
+      /* Maybe it is a (derived) GPIO IRQ */
+
+      lpc43_gpioint_disable(irq);
+    }
+#endif
+  lpc43_dumpnvic("disable", irq);
+}
+
+/****************************************************************************
+ * Name: up_enable_irq
+ *
+ * Description:
+ *   Enable the IRQ specified by 'irq'
+ *
+ ****************************************************************************/
+
+void up_enable_irq(int irq)
+{
+  uint32_t regaddr;
+  uint32_t regval;
+  uint32_t bit;
+
+  if (lpc43_irqinfo(irq, &regaddr, &bit) == 0)
+    {
+      /* Set the appropriate bit in the register to enable the interrupt */
+
+      regval  = getreg32(regaddr);
+      regval |= bit;
+      putreg32(regval, regaddr);
+    }
+#ifdef CONFIG_GPIO_IRQ
+  else if (irq >= LPC43_VALID_FIRST0L)
+    {
+      /* Maybe it is a (derived) GPIO IRQ */
+
+      lpc43_gpioint_enable(irq);
+    }
+#endif
+  lpc43_dumpnvic("enable", irq);
+}
+
+/****************************************************************************
+ * Name: up_maskack_irq
+ *
+ * Description:
+ *   Mask the IRQ and acknowledge it
+ *
+ ****************************************************************************/
+
+void up_maskack_irq(int irq)
+{
+  up_disable_irq(irq);
+
+#if 0 /* Does not appear to be necessary in most cases */
+  lpc43_clrpend(irq);
+#endif
+}
+
+/****************************************************************************
+ * Name: up_prioritize_irq
+ *
+ * Description:
+ *   Set the priority of an IRQ.
+ *
+ *   Since this API is not supported on all architectures, it should be
+ *   avoided in common implementations where possible.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_ARCH_IRQPRIO
+int up_prioritize_irq(int irq, int priority)
+{
+  uint32_t regaddr;
+  uint32_t regval;
+  int shift;
+
+  DEBUGASSERT(irq >= LPC43_IRQ_MEMFAULT && irq < NR_IRQS &&
+             (unsigned)priority <= LPC43M4_SYSH_PRIORITY_MIN);
+
+  if (irq < LPC43_IRQ_EXTINT)
+    {
+      irq    -= 4;
+      regaddr = NVIC_SYSH_PRIORITY(irq);
+    }
+  else
+    {
+      irq    -= LPC43_IRQ_EXTINT;
+      regaddr = NVIC_IRQ_PRIORITY(irq);
+    }
+
+  regval      = getreg32(regaddr);
+  shift       = ((irq & 3) << 3);
+  regval     &= ~(0xff << shift);
+  regval     |= (priority << shift);
+  putreg32(regval, regaddr);
+
+  lpc43_dumpnvic("prioritize", irq);
+  return OK;
+}
+#endif
diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_irq.h b/nuttx/arch/arm/src/lpc43xx/lpc43_irq.h
new file mode 100644
index 000000000..201081169
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/lpc43_irq.h
@@ -0,0 +1,92 @@
+/****************************************************************************
+ * arch/arm/src/lpc43xx/lpc43_irq.h
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LPC43XX_LPC43_IRQ_H
+#define __ARCH_ARM_SRC_LPC43XX_LPC43_IRQ_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C" {
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Inline Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: lpc43_clrpend
+ *
+ * Description:
+ *   Clear a pending interrupt at the NVIC.  This does not seem to be
+ *   required for most interrupts.
+ *
+ ****************************************************************************/
+
+EXTERN void lpc43_clrpend(int irq);
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_ARM_SRC_LPC43XX_LPC43_IRQ_H */
diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_pinconfig.c b/nuttx/arch/arm/src/lpc43xx/lpc43_pinconfig.c
new file mode 100644
index 000000000..fb5173339
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/lpc43_pinconfig.c
@@ -0,0 +1,154 @@
+/****************************************************************************
+ *  arch/arm/src/lpc43/lpc43_pin_config.c
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <arch/board/board.h>
+#include <nuttx/config.h>
+
+#include <nuttx/arch.h>
+#include <errno.h>
+
+#include "up_arch.h"
+#include "lpc43_pinconfig.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: lpc43_pin_config
+ *
+ * Description:
+ *   Configure a pin based on bit-encoded description of the pin.
+ *
+ * Input Value:
+ *   20-bit encoded value describing the pin.
+ *
+ * Returned Value:
+ *   OK on success; A negated errno value on failure.
+ *
+ ****************************************************************************/
+
+int lpc43_pin_config(uint32_t pinconf)
+{
+  unsigned int pinset = ((pinconf & PINCONF_PINS_MASK) >> PINCONF_PINS_SHIFT);
+  unsigned int pin    = ((pinconf & PINCONF_PIN_MASK) >> PINCONF_PIN_SHIFT);
+  unsigned int func   = ((pinconf & PINCONF_FUNC_MASK) >> PINCONF_FUNC_SHIFT);
+  uintptr_t regaddr;
+  uint32_t  regval;
+
+  /* Set up common pin configurations */
+
+  regval = (func << SCU_PIN_MODE_SHIFT);
+
+  /* Enable/disable pull-down resistor */
+
+  if (PINCONF_IS_PULLDOWN(pinconf))
+    {
+      regval |= SCU_PIN_EPD;  /* Set bit to enable */
+    }
+
+  if (!PINCONF_IS_PULLUP(pinconf))
+    {
+      regval |= SCU_PIN_EPUN; /* Set bit to disable */
+    }
+
+  /* Enable/disable input buffering */
+
+  if (PINCONF_INBUFFER_ENABLED(pinconf))
+   {
+     regval |= SCU_PIN_EZI; /* Set bit to enable */
+   }
+
+  /* Enable/disable glitch filtering */
+
+  if (!PINCONF_GLITCH_ENABLE(pinconf))
+   {
+     regval |= SCU_PIN_ZIF; /* Set bit to disable */
+   }
+
+  /* Only normal and high speed pins support the slew rate setting */
+
+  if (PINCONF_IS_SLEW_FAST(pinconf))
+   {
+     regval |= SCU_NDPIN_EHS; /* 0=slow; 1=fast */
+   }
+ 
+  /* Only high drive pins suppose drive strength */
+
+  switch (pinconf & PINCONF_DRIVE_MASK)
+    {
+      default:
+      case PINCONF_DRIVE_NORMAL: /* Normal-drive: 4 mA drive strength (or not high drive pin) */
+        regval |= SCU_HDPIN_EHD_NORMAL;
+        break;
+
+      case PINCONF_DRIVE_MEDIUM: /* Medium-drive: 8 mA drive strength */
+        regval |= SCU_HDPIN_EHD_MEDIUM;
+        break;
+
+      case PINCONF_DRIVE_HIGH: /* High-drive: 14 mA drive strength */
+        regval |= SCU_HDPIN_EHD_HIGH;
+        break;
+
+      case PINCONF_DRIVE_ULTRA: /* Ultra high-drive: 20 mA drive strength */
+        regval |= SCU_HDPIN_EHD_ULTRA;
+        break;
+    }
+
+  /* Get the address of the pin configuration register and save the new
+   * pin configuration.
+   */
+
+  regaddr =  LPC43_SCU_SFSP(pinset, pin);
+  putreg32(regval, regaddr);
+
+  return OK;
+}
diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_pinconfig.h b/nuttx/arch/arm/src/lpc43xx/lpc43_pinconfig.h
new file mode 100644
index 000000000..293f838e9
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/lpc43_pinconfig.h
@@ -0,0 +1,278 @@
+/********************************************************************************************
+ * arch/arm/src/lpc43xx/lpc43_pinconfig.h
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ********************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LPC43XX_PINCONFIG_H
+#define __ARCH_ARM_SRC_LPC43XX_PINCONFIG_H
+
+/********************************************************************************************
+ * Included Files
+ ********************************************************************************************/
+
+#include <nuttx/config.h>
+
+/* Include the chip capabilities and SCU definitions file */
+
+#include "chip.h"
+#include "chip/lpc43_scu.h"
+
+/********************************************************************************************
+ * Pre-processor Definitions
+ ********************************************************************************************/
+/* Each configurable pin can be individually configured by software in several modes. The
+ * following definitions provide the bit encoding that is used to define a pin configuration.
+ * Note that these pins do not corresponding GPIO ports and pins.
+ *
+ * 20-bit Encoding:
+ * 1111 1111 1100 0000 0000
+ * 9876 5432 1098 7654 3210
+ * ---- ---- ---- ---- ----
+ * .FFF UUDD IGWS SSSP PPPP
+ */
+
+/* Alternate function number:
+ *
+ * 1111 1111 1100 0000 0000
+ * 9876 5432 1098 7654 3210
+ * ---- ---- ---- ---- ----
+ * .FFF .... .... .... ....
+ */
+
+#define PINCONF_FUNC_SHIFT            (16)       /* Bits 16-18: Alternate function number */
+#define PINCONF_FUNC_MASK             (7 << PINCONF_FUNC_SHIFT)
+#  define PINCONF_FUNC(n)             ((n) << PINCONF_FUNC_SHIFT)
+#  define PINCONF_FUNC0               (0 << PINCONF_FUNC_SHIFT)
+#  define PINCONF_FUNC1               (1 << PINCONF_FUNC_SHIFT)
+#  define PINCONF_FUNC2               (2 << PINCONF_FUNC_SHIFT)
+#  define PINCONF_FUNC3               (3 << PINCONF_FUNC_SHIFT)
+#  define PINCONF_FUNC4               (4 << PINCONF_FUNC_SHIFT)
+#  define PINCONF_FUNC5               (5 << PINCONF_FUNC_SHIFT)
+#  define PINCONF_FUNC6               (6 << PINCONF_FUNC_SHIFT)
+#  define PINCONF_FUNC7               (7 << PINCONF_FUNC_SHIFT)
+
+/* Pull-up/down resisters.  These selections are available for all pins but may not
+ * make sense for all pins.  NOTE: that both pull up and down is not precluded.
+ *
+ * 1111 1111 1100 0000 0000
+ * 9876 5432 1098 7654 3210
+ * ---- ---- ---- ---- ----
+ * .... UU.. .... .... ....
+ */
+
+#define PINCONF_PULLUP                (1 << 15) /* Bit 15: 1=Pull-up */
+#define PINCONF_PULLDOWN              (1 << 14) /* Bit 14: 1=Pull-down */
+#define PINCONF_FLOAT                 (0)       /* Bit 14-15=0 if neither */
+
+#define PINCONF_IS_PULLUP(p)          (((p) & PINCONF_PULLUP) != 0)
+#define PINCONF_IS_PULLDOWN(p)        (((p) & PINCONF_PULLDOWN) != 0)
+#define PINCONF_IS_FLOAT(p)           (((p) & (PINCONF_PULLUP|PINCONF_PULLDOWN) == 0)
+
+/* Drive strength.  These selections are available only for high-drive pins
+ *
+ * 1111 1111 1100 0000 0000
+ * 9876 5432 1098 7654 3210
+ * ---- ---- ---- ---- ----
+ * .... ..DD .... .... ....
+ */
+
+#define PINCONF_DRIVE_SHIFT           (12)       /* Bits 12-13 = Pin drive strength */
+#define PINCONF_DRIVE_MASK            (3 << PINCONF_DRIVE_SHIFT)
+#  define PINCONF_DRIVE_NORMAL        (0 << PINCONF_DRIVE_SHIFT)
+#  define PINCONF_DRIVE_MEDIUM        (1 << PINCONF_DRIVE_SHIFT)
+#  define PINCONF_DRIVE_HIGH          (2 << PINCONF_DRIVE_SHIFT)
+#  define PINCONF_DRIVE_ULTRA         (3 << PINCONF_DRIVE_SHIFT)
+
+/* Input buffer enable
+ *
+ * 1111 1111 1100 0000 0000
+ * 9876 5432 1098 7654 3210
+ * ---- ---- ---- ---- ----
+ * .... .... I... .... ....
+ */
+
+#define PINCONF_INBUFFER              (1 << 11)  /* Bit 11: 1=Enabled input buffer */
+#define PINCONF_INBUFFER_ENABLED(p)   (((p) & PINCONF_INBUFFER) != 0)
+
+/* Glitch filter enable
+ *
+ * 1111 1111 1100 0000 0000
+ * 9876 5432 1098 7654 3210
+ * ---- ---- ---- ---- ----
+ * .... .... .G.. .... ....
+ */
+
+#define PINCONF_GLITCH                (1 << 10)  /* Bit 10: 1=Glitch filter enable */
+#define PINCONF_GLITCH_ENABLE(p)      (((p) & PINCONF_GLITCH) == 0)
+
+/* Slew rate
+ *
+ * 1111 1111 1100 0000 0000
+ * 9876 5432 1098 7654 3210
+ * ---- ---- ---- ---- ----
+ * .... .... ..W. .... ....
+ */
+
+#define PINCONF_SLEW_FAST             (1 << 9)   /* Bit 9: 1=Alternate function */
+#define PINCONF_SLEW_SLOW             (0)        /* Bit 9: 0=Normal function */
+
+#define PINCONF_IS_SLEW_FAST(p)       (((p) & PINCONF_SLEW_FAST) != 0)
+#define PINCONF_IS_SLOW_SLOW(p)       (((p) & PINCONF_SLEW_FAST) == 0)
+
+/* Pin configuration sets:
+ *
+ * 1111 1111 1100 0000 0000
+ * 9876 5432 1098 7654 3210
+ * ---- ---- ---- ---- ----
+ * .... .... ...S SSS. ....
+ */
+
+#define PINCONF_PINS_SHIFT            (5)        /* Bits 5-8: Pin set */
+#define PINCONF_PINS_MASK             (15 << PINCONF_PINS_SHIFT)
+#  define PINCONF_PINS0               (0 << PINCONF_PINS_SHIFT)
+#  define PINCONF_PINS1               (1 << PINCONF_PINS_SHIFT)
+#  define PINCONF_PINS2               (2 << PINCONF_PINS_SHIFT)
+#  define PINCONF_PINS3               (3 << PINCONF_PINS_SHIFT)
+#  define PINCONF_PINS4               (4 << PINCONF_PINS_SHIFT)
+#  define PINCONF_PINS5               (5 << PINCONF_PINS_SHIFT)
+#  define PINCONF_PINS6               (6 << PINCONF_PINS_SHIFT)
+#  define PINCONF_PINS7               (7 << PINCONF_PINS_SHIFT)
+#  define PINCONF_PINS8               (8 << PINCONF_PINS_SHIFT)
+#  define PINCONF_PINS9               (9 << PINCONF_PINS_SHIFT)
+#  define PINCONF_PINSA               (10 << PINCONF_PINS_SHIFT)
+#  define PINCONF_PINSB               (11 << PINCONF_PINS_SHIFT)
+#  define PINCONF_PINSC               (12 << PINCONF_PINS_SHIFT)
+#  define PINCONF_PINSD               (13 << PINCONF_PINS_SHIFT)
+#  define PINCONF_PINSE               (14 << PINCONF_PINS_SHIFT)
+#  define PINCONF_PINSF               (15 << PINCONF_PINS_SHIFT)
+
+/* Pin numbers:
+ *
+ * 1111 1111 1100 0000 0000
+ * 9876 5432 1098 7654 3210
+ * ---- ---- ---- ---- ----
+ * .... .... .... ...P PPPP
+ */
+ 
+#define PINCONF_PIN_SHIFT             (0)        /* Bits 0-4: Pin number */
+#define PINCONF_PIN_MASK              (31 << PINCONF_PIN_SHIFT)
+#  define PINCONF_PIN_0               (0 << PINCONF_PIN_SHIFT)
+#  define PINCONF_PIN_1               (1 << PINCONF_PIN_SHIFT)
+#  define PINCONF_PIN_2               (2 << PINCONF_PIN_SHIFT)
+#  define PINCONF_PIN_3               (3 << PINCONF_PIN_SHIFT)
+#  define PINCONF_PIN_4               (4 << PINCONF_PIN_SHIFT)
+#  define PINCONF_PIN_5               (5 << PINCONF_PIN_SHIFT)
+#  define PINCONF_PIN_6               (6 << PINCONF_PIN_SHIFT)
+#  define PINCONF_PIN_7               (7 << PINCONF_PIN_SHIFT)
+#  define PINCONF_PIN_8               (8 << PINCONF_PIN_SHIFT)
+#  define PINCONF_PIN_9               (9 << PINCONF_PIN_SHIFT)
+#  define PINCONF_PIN_10              (10 << PINCONF_PIN_SHIFT)
+#  define PINCONF_PIN_11              (11 << PINCONF_PIN_SHIFT)
+#  define PINCONF_PIN_12              (12 << PINCONF_PIN_SHIFT)
+#  define PINCONF_PIN_13              (13 << PINCONF_PIN_SHIFT)
+#  define PINCONF_PIN_14              (14 << PINCONF_PIN_SHIFT)
+#  define PINCONF_PIN_15              (15 << PINCONF_PIN_SHIFT)
+#  define PINCONF_PIN_16              (16 << PINCONF_PIN_SHIFT)
+#  define PINCONF_PIN_17              (17 << PINCONF_PIN_SHIFT)
+#  define PINCONF_PIN_18              (18 << PINCONF_PIN_SHIFT)
+#  define PINCONF_PIN_19              (19 << PINCONF_PIN_SHIFT)
+#  define PINCONF_PIN_20              (20 << PINCONF_PIN_SHIFT)
+#  define PINCONF_PIN_21              (21 << PINCONF_PIN_SHIFT)
+#  define PINCONF_PIN_22              (22 << PINCONF_PIN_SHIFT)
+#  define PINCONF_PIN_23              (23 << PINCONF_PIN_SHIFT)
+#  define PINCONF_PIN_24              (24 << PINCONF_PIN_SHIFT)
+#  define PINCONF_PIN_25              (25 << PINCONF_PIN_SHIFT)
+#  define PINCONF_PIN_26              (26 << PINCONF_PIN_SHIFT)
+#  define PINCONF_PIN_27              (27 << PINCONF_PIN_SHIFT)
+#  define PINCONF_PIN_28              (28 << PINCONF_PIN_SHIFT)
+#  define PINCONF_PIN_29              (29 << PINCONF_PIN_SHIFT)
+#  define PINCONF_PIN_30              (30 << PINCONF_PIN_SHIFT)
+#  define PINCONF_PIN_31              (31 << PINCONF_PIN_SHIFT)
+
+/********************************************************************************************
+ * Public Types
+ ********************************************************************************************/
+
+/********************************************************************************************
+ * Public Data
+ ********************************************************************************************/
+
+#ifndef __ASSEMBLY__
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C" {
+#else
+#define EXTERN extern
+#endif
+
+/********************************************************************************************
+ * Public Functions
+ ********************************************************************************************/
+
+/********************************************************************************************
+ * Name: lpc43_pin_config
+ *
+ * Description:
+ *   Configure a pin based on bit-encoded description of the pin.
+ *
+ * Input Value:
+ *   20-bit encoded value describing the pin.
+ *
+ * Returned Value:
+ *   OK on success; A negated errno value on failure.
+ *
+ ********************************************************************************************/
+
+EXTERN int lpc43_pin_config(uint32_t pinconf);
+
+/********************************************************************************************
+ * Function:  lpc43_pin_dump
+ *
+ * Description:
+ *   Dump all pin configuration registers associated with the provided pin configuration
+ *
+ ********************************************************************************************/
+
+#ifdef CONFIG_DEBUG
+EXTERN int lpc43_pin_dump(uint32_t pinconf, const char *msg);
+#else
+#  define lpc43_pin_dump(p,m)
+#endif
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+#endif /* __ASSEMBLY__ */
+
+#endif /* __ARCH_ARM_SRC_LPC43XX_PINCONFIG_H */
diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_rgu.c b/nuttx/arch/arm/src/lpc43xx/lpc43_rgu.c
new file mode 100644
index 000000000..d5ab819dc
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/lpc43_rgu.c
@@ -0,0 +1,125 @@
+/****************************************************************************
+ * arch/arm/src/lpc43/lpc43_rgu.c
+ * arch/arm/src/chip/lpc43_rgu.c
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <arch/irq.h>
+#include <nuttx/arch.h>
+
+#include "nvic.h"
+#include "up_arch.h"
+
+#include "chip.h"
+#include "lpc43_rgu.h"
+
+/****************************************************************************
+ * Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: lpc43_softreset
+ *
+ * Description:
+ *   Reset as many of the LPC43 peripherals as possible. This is necessary
+ *   because the LPC43 does not provide any way of performing a full system
+ *   reset under debugger control.  So, if CONFIG_DEBUG is set (indicating
+ *   that a debugger is being used?), the the boot logic will call this 
+ *   function on all restarts.
+ *
+ * Assumptions:
+ *   Since this function is called early in the boot sequence, it cannot
+ *   depend on anything such as initialization of .bss or .data.  It can
+ *   only assume that it has a stack.
+ *
+ ****************************************************************************/
+
+void lpc43_softreset(void)
+{
+  irqstate_t flags;
+
+  /* Disable interrupts */
+
+  flags = irqsave();
+ 
+  /* Reset all of the peripherals that we can (safely) */
+
+  putreg32((RGU_CTRL0_LCD_RST     | RGU_CTRL0_USB0_RST     |
+            RGU_CTRL0_USB1_RST    | RGU_CTRL0_DMA_RST      |
+            RGU_CTRL0_SDIO_RST    | RGU_CTRL0_ETHERNET_RST |
+            RGU_CTRL0_GPIO_RST), LPC43_RGU_CTRL0);
+  putreg32((RGU_CTRL1_TIMER0_RST  | RGU_CTRL1_TIMER1_RST   |
+            RGU_CTRL1_TIMER2_RST  | RGU_CTRL1_TIMER3_RST   |
+            RGU_CTRL1_RITIMER_RST | RGU_CTRL1_SCT_RST      |
+            RGU_CTRL1_MCPWM_RST   | RGU_CTRL1_QEI_RST      |
+            RGU_CTRL1_ADC0_RST    | RGU_CTRL1_ADC1_RST     |
+            RGU_CTRL1_USART0_RST  | RGU_CTRL1_UART1_RST    |
+            RGU_CTRL1_USART2_RST  | RGU_CTRL1_USART3_RST   |
+            RGU_CTRL1_I2C0_RST    | RGU_CTRL1_I2C1_RST     |
+            RGU_CTRL1_SSP0_RST    | RGU_CTRL1_SSP1_RST     |
+            RGU_CTRL1_I2S_RST     | RGU_CTRL1_CAN1_RST     |
+            RGU_CTRL1_CAN0_RST    | RGU_CTRL1_M0APP_RST),
+            LPC43_RGU_CTRL1);
+
+  /* A delay seems to be necessary somewhere around here */
+
+  up_mdelay(20);
+
+  /* Clear all pending interupts */
+
+  putreg32(0xffffffff, NVIC_IRQ0_31_CLRPEND);
+  putreg32(0xffffffff, NVIC_IRQ32_63_CLRPEND);
+  irqrestore(flags);
+}
diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_rgu.h b/nuttx/arch/arm/src/lpc43xx/lpc43_rgu.h
new file mode 100644
index 000000000..364b4d066
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/lpc43_rgu.h
@@ -0,0 +1,92 @@
+/****************************************************************************
+ * arch/arm/src/lpc43xx/lpc43_rgu.h
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LPC43XX_LPC43_RGU_H
+#define __ARCH_ARM_SRC_LPC43XX_LPC43_RGU_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include "chip/lpc43_rgu.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C" {
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: lpc43_softreset
+ *
+ * Description:
+ *   Reset as many of the LPC43 peripherals as possible. This is necessary
+ *   because the LPC43 does not provide any way of performing a full system
+ *   reset under debugger control.  So, if CONFIG_DEBUG is set (indicating
+ *   that a debugger is being used?), the the boot logic will call this 
+ *   function on all restarts.
+ *
+ ****************************************************************************/
+
+EXTERN void lpc43_softreset(void);
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_ARM_SRC_LPC43XX_LPC43_RGU_H */
diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_serial.c b/nuttx/arch/arm/src/lpc43xx/lpc43_serial.c
new file mode 100644
index 000000000..6e2e19f35
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/lpc43_serial.c
@@ -0,0 +1,1460 @@
+/****************************************************************************
+ * arch/arm/src/lpc43xx/lpc43_serial.c
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <unistd.h>
+#include <semaphore.h>
+#include <string.h>
+#include <errno.h>
+#include <debug.h>
+
+#ifdef CONFIG_SERIAL_TERMIOS
+#  include <termios.h>
+#endif
+
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+#include <nuttx/serial/serial.h>
+
+#include <arch/serial.h>
+#include <arch/board/board.h>
+
+#include "chip.h"
+#include "up_arch.h"
+#include "os_internal.h"
+#include "up_internal.h"
+
+#include "lpc43_config.h"
+#include "lpc43_serial.h"
+
+/****************************************************************************
+ * Pre-processor definitions
+ ****************************************************************************/
+
+/* If we are not using the serial driver for the console, then we still must
+ * provide some minimal implementation of up_putc.
+ */
+
+#if defined(USE_SERIALDRIVER) && defined(HAVE_UART)
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+struct up_dev_s
+{
+  uintptr_t uartbase;  /* Base address of UART registers */
+  uint32_t  basefreq;  /* Base frequency of input clock */
+  uint32_t  baud;      /* Configured baud */
+  uint32_t  ier;       /* Saved IER value */
+  uint8_t   id;        /* ID=0,1,2,3 */
+  uint8_t   irq;       /* IRQ associated with this UART */
+  uint8_t   parity;    /* 0=none, 1=odd, 2=even */
+  uint8_t   bits;      /* Number of bits (7 or 8) */
+  bool      stopbits2; /* true: Configure with 2 stop bits instead of 1 */
+};
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+static int  up_setup(struct uart_dev_s *dev);
+static void up_shutdown(struct uart_dev_s *dev);
+static int  up_attach(struct uart_dev_s *dev);
+static void up_detach(struct uart_dev_s *dev);
+static int  up_interrupt(int irq, void *context);
+static int  up_ioctl(struct file *filep, int cmd, unsigned long arg);
+static int  up_receive(struct uart_dev_s *dev, uint32_t *status);
+static void up_rxint(struct uart_dev_s *dev, bool enable);
+static bool up_rxavailable(struct uart_dev_s *dev);
+static void up_send(struct uart_dev_s *dev, int ch);
+static void up_txint(struct uart_dev_s *dev, bool enable);
+static bool up_txready(struct uart_dev_s *dev);
+static bool up_txempty(struct uart_dev_s *dev);
+
+/****************************************************************************
+ * Private Variables
+ ****************************************************************************/
+
+struct uart_ops_s g_uart_ops =
+{
+  .setup          = up_setup,
+  .shutdown       = up_shutdown,
+  .attach         = up_attach,
+  .detach         = up_detach,
+  .ioctl          = up_ioctl,
+  .receive        = up_receive,
+  .rxint          = up_rxint,
+  .rxavailable    = up_rxavailable,
+  .send           = up_send,
+  .txint          = up_txint,
+  .txready        = up_txready,
+  .txempty        = up_txempty,
+};
+
+/* I/O buffers */
+
+#ifdef CONFIG_LPC43_USART0
+static char g_uart0rxbuffer[CONFIG_USART0_RXBUFSIZE];
+static char g_uart0txbuffer[CONFIG_USART0_TXBUFSIZE];
+#endif
+#ifdef CONFIG_LPC43_UART1
+static char g_uart1rxbuffer[CONFIG_UART1_RXBUFSIZE];
+static char g_uart1txbuffer[CONFIG_UART1_TXBUFSIZE];
+#endif
+#ifdef CONFIG_LPC43_USART2
+static char g_uart2rxbuffer[CONFIG_USART2_RXBUFSIZE];
+static char g_uart2txbuffer[CONFIG_USART2_TXBUFSIZE];
+#endif
+#ifdef CONFIG_LPC43_USART3
+static char g_uart3rxbuffer[CONFIG_USART3_RXBUFSIZE];
+static char g_uart3txbuffer[CONFIG_USART3_TXBUFSIZE];
+#endif
+
+/* This describes the state of the LPC43xx uart0 port. */
+
+#ifdef CONFIG_LPC43_USART0
+static struct up_dev_s g_uart0priv =
+{
+  .uartbase       = LPC43_USART0_BASE,
+  .basefreq       = BOARD_USART0_BASEFREQ,
+  .baud           = CONFIG_USART0_BAUD,
+  .id             = 0,
+  .irq            = LPC43M4_IRQ_USART0,
+  .parity         = CONFIG_USART0_PARITY,
+  .bits           = CONFIG_USART0_BITS,
+  .stopbits2      = CONFIG_USART0_2STOP,
+};
+
+static uart_dev_t g_uart0port =
+{
+  .recv     =
+  {
+    .size   = CONFIG_USART0_RXBUFSIZE,
+    .buffer = g_uart0rxbuffer,
+  },
+  .xmit     =
+  {
+    .size   = CONFIG_USART0_TXBUFSIZE,
+    .buffer = g_uart0txbuffer,
+  },
+  .ops      = &g_uart_ops,
+  .priv     = &g_uart0priv,
+};
+#endif
+
+/* This describes the state of the LPC43xx uart1 port. */
+
+#ifdef CONFIG_LPC43_UART1
+static struct up_dev_s g_uart1priv =
+{
+  .uartbase       = LPC43_UART1_BASE,
+  .basefreq       = BOARD_UART1_BASEFREQ,
+  .baud           = CONFIG_UART1_BAUD,
+  .id             = 1,
+  .irq            = LPC43M4_IRQ_UART1,
+  .parity         = CONFIG_UART1_PARITY,
+  .bits           = CONFIG_UART1_BITS,
+  .stopbits2      = CONFIG_UART1_2STOP,
+};
+
+static uart_dev_t g_uart1port =
+{
+  .recv     =
+  {
+    .size   = CONFIG_UART1_RXBUFSIZE,
+    .buffer = g_uart1rxbuffer,
+  },
+  .xmit     =
+  {
+    .size   = CONFIG_UART1_TXBUFSIZE,
+    .buffer = g_uart1txbuffer,
+  },
+  .ops      = &g_uart_ops,
+  .priv     = &g_uart1priv,
+};
+#endif
+
+/* This describes the state of the LPC43xx uart1 port. */
+
+#ifdef CONFIG_LPC43_USART2
+static struct up_dev_s g_uart2priv =
+{
+  .uartbase       = LPC43_USART2_BASE,
+  .basefreq       = BOARD_USART2_BASEFREQ,
+  .baud           = CONFIG_USART2_BAUD,
+  .id             = 2,
+  .irq            = LPC43M4_IRQ_USART2,
+  .parity         = CONFIG_USART2_PARITY,
+  .bits           = CONFIG_USART2_BITS,
+  .stopbits2      = CONFIG_USART2_2STOP,
+};
+
+static uart_dev_t g_uart2port =
+{
+  .recv     =
+  {
+    .size   = CONFIG_USART2_RXBUFSIZE,
+    .buffer = g_uart2rxbuffer,
+  },
+  .xmit     =
+  {
+    .size   = CONFIG_USART2_TXBUFSIZE,
+    .buffer = g_uart2txbuffer,
+  },
+  .ops      = &g_uart_ops,
+  .priv     = &g_uart2priv,
+};
+#endif
+
+/* This describes the state of the LPC43xx uart1 port. */
+
+#ifdef CONFIG_LPC43_USART3
+static struct up_dev_s g_uart3priv =
+{
+  .uartbase       = LPC43_USART3_BASE,
+  .basefreq       = BOARD_USART3_BASEFREQ,
+  .baud           = CONFIG_USART3_BAUD,
+  .id             = 3,
+  .irq            = LPC43M4_IRQ_USART3,
+  .parity         = CONFIG_USART3_PARITY,
+  .bits           = CONFIG_USART3_BITS,
+  .stopbits2      = CONFIG_USART3_2STOP,
+};
+
+static uart_dev_t g_uart3port =
+{
+  .recv     =
+  {
+    .size   = CONFIG_USART3_RXBUFSIZE,
+    .buffer = g_uart3rxbuffer,
+  },
+  .xmit     =
+  {
+    .size   = CONFIG_USART3_TXBUFSIZE,
+    .buffer = g_uart3txbuffer,
+  },
+  .ops      = &g_uart_ops,
+  .priv     = &g_uart3priv,
+};
+#endif
+
+/* Which UART with be tty0/console and which tty1? tty2? tty3? */
+
+#ifdef HAVE_CONSOLE
+#  if defined(CONFIG_USART0_SERIAL_CONSOLE)
+#    define CONSOLE_DEV     g_uart0port      /* USART0=console */
+#    define TTYS0_DEV       g_uart0port      /* USART0=ttyS0 */
+#    ifdef CONFIG_LPC43_UART1
+#      define TTYS1_DEV     g_uart1port      /* USART0=ttyS0;UART1=ttyS1 */
+#      ifdef CONFIG_LPC43_USART2
+#        define TTYS2_DEV   g_uart2port      /* USART0=ttyS0;UART1=ttyS1;USART2=ttyS2 */
+#        ifdef CONFIG_LPC43_USART3
+#          define TTYS3_DEV g_uart3port      /* USART0=ttyS0;UART1=ttyS1;USART2=ttyS2;USART3=ttyS3 */
+#        else
+#          undef TTYS3_DEV                   /* USART0=ttyS0;UART1=ttyS1;USART2=ttyS;No ttyS3 */
+#        endif
+#      else
+#        ifdef CONFIG_LPC43_USART3
+#          define TTYS2_DEV g_uart3port     /* USART0=ttyS0;UART1=ttyS1;USART3=ttys2;No ttyS3 */
+#        else
+#          undef TTYS2_DEV                  /* USART0=ttyS0;UART1=ttyS1;No ttyS2;No ttyS3 */
+#        endif
+#        undef TTYS3_DEV                    /* No ttyS3 */
+#      endif
+#    else
+#      ifdef CONFIG_LPC43_USART2
+#        define TTYS1_DEV   g_uart2port    /* USART0=ttyS0;USART2=ttyS1;No ttyS3 */
+#        ifdef CONFIG_LPC43_USART3
+#          define TTYS2_DEV g_uart3port    /* USART0=ttyS0;USART2=ttyS1;USART3=ttyS2;No ttyS3 */
+#        else
+#          undef TTYS2_DEV                 /* USART0=ttyS0;USART2=ttyS1;No ttyS2;No ttyS3 */
+#        endif
+#        undef TTYS3_DEV                   /* No ttyS3 */
+#      else
+#        ifdef CONFIG_LPC43_USART3
+#          define TTYS1_DEV g_uart3port    /* USART0=ttyS0;USART3=ttyS1;No ttyS2;No ttyS3 */
+#        else
+#          undef TTYS1_DEV                 /* USART0=ttyS0;No ttyS1;No ttyS2;No ttyS3 */
+#        endif
+#          undef TTYS2_DEV                  /* No ttyS2 */
+#        undef TTYS3_DEV                    /* No ttyS3 */
+#      endif
+#    endif
+#  elif defined(CONFIG_UART1_SERIAL_CONSOLE)
+#    define CONSOLE_DEV     g_uart1port     /* UART1=console */
+#    define TTYS0_DEV       g_uart1port     /* UART1=ttyS0 */
+#    ifdef CONFIG_LPC43_USART0
+#      define TTYS1_DEV     g_uart0port     /* UART1=ttyS0;USART0=ttyS1 */
+#      ifdef CONFIG_LPC43_USART2
+#        define TTYS2_DEV   g_uart2port     /* UART1=ttyS0;USART0=ttyS1;USART2=ttyS2 */
+#        ifdef CONFIG_LPC43_USART3
+#          define TTYS3_DEV g_uart3port     /* UART1=ttyS0;USART0=ttyS1;USART2=ttyS2;USART3=ttyS3 */
+#        else
+#          undef TTYS3_DEV                  /* UART1=ttyS0;USART0=ttyS1;USART2=ttyS;No ttyS3 */
+#        endif
+#      else
+#        ifdef CONFIG_LPC43_USART3
+#          define TTYS2_DEV g_uart3port     /* UART1=ttyS0;USART0=ttyS1;USART3=ttys2;No ttyS3 */
+#        else
+#          undef TTYS2_DEV                  /* UART1=ttyS0;USART0=ttyS1;No ttyS2;No ttyS3 */
+#        endif
+#        undef TTYS3_DEV                    /* No ttyS3 */
+#      endif
+#    else
+#      ifdef CONFIG_LPC43_USART2
+#        define TTYS1_DEV   g_uart2port     /* UART1=ttyS0;USART2=ttyS1 */
+#        ifdef CONFIG_LPC43_USART3
+#          define TTYS2_DEV g_uart3port     /* UART1=ttyS0;USART2=ttyS1;USART3=ttyS2;No ttyS3 */
+#        else
+#          undef TTYS2_DEV                  /* UART1=ttyS0;USART2=ttyS1;No ttyS2;No ttyS3 */
+#        endif
+#        undef TTYS3_DEV                    /* No ttyS3 */
+#      else
+#        ifdef CONFIG_LPC43_USART3
+#          define TTYS1_DEV   g_uart3port   /* UART1=ttyS0;USART3=ttyS1;No ttyS2;No ttyS3 */
+#        else
+#          undef TTYS1_DEV                  /* UART1=ttyS0;No ttyS1;No ttyS2;No ttyS3 */
+#        endif
+#        undef TTYS2_DEV                    /* No ttyS2 */
+#        undef TTYS3_DEV                    /* No ttyS3 */
+#      endif
+#    endif
+#  elif defined(CONFIG_USART2_SERIAL_CONSOLE)
+#    define CONSOLE_DEV     g_uart2port     /* USART2=console */
+#    define TTYS0_DEV       g_uart2port     /* USART2=ttyS0 */
+#    ifdef CONFIG_LPC43_USART2
+#      define TTYS1_DEV     g_uart0port     /* USART2=ttyS0;USART0=ttyS1 */
+#      ifdef CONFIG_LPC43_UART1
+#        define TTYS2_DEV   g_uart1port     /* USART2=ttyS0;USART0=ttyS1;UART1=ttyS2 */
+#        ifdef CONFIG_LPC43_USART3
+#          define TTYS3_DEV g_uart3port     /* USART2=ttyS0;USART0=ttyS1;UART1=ttyS2;USART3=ttyS3 */
+#        else
+#          undef TTYS3_DEV                  /* USART2=ttyS0;USART0=ttyS1;UART1=ttyS;No ttyS3 */
+#        endif
+#      else
+#        ifdef CONFIG_LPC43_USART3
+#          define TTYS2_DEV g_uart3port     /* USART2=ttyS0;USART0=ttyS1;USART3=ttys2;No ttyS3 */
+#        else
+#          undef TTYS2_DEV                  /* USART2=ttyS0;USART0=ttyS1;No ttyS2;No ttyS3 */
+#        endif
+#        undef TTYS3_DEV                    /* No ttyS3 */
+#      endif
+#    else
+#      ifdef CONFIG_LPC43_UART1
+#        define TTYS1_DEV   g_uart1port    /* USART2=ttyS0;UART1=ttyS1 */
+#        ifdef CONFIG_LPC43_USART3
+#          define TTYS2_DEV g_uart3port    /* USART2=ttyS0;UART1=ttyS1;USART3=ttyS2 */
+#        else
+#          undef TTYS2_DEV                 /* USART2=ttyS0;UART1=ttyS1;No ttyS2;No ttyS3 */
+#        endif
+#        undef TTYS3_DEV                   /* No ttyS3 */
+#      else
+#        ifdef CONFIG_LPC43_USART3
+#          define TTYS1_DEV g_uart3port    /* USART2=ttyS0;USART3=ttyS1;No ttyS3 */
+#        else
+#          undef TTYS1_DEV                 /* USART2=ttyS0;No ttyS1;No ttyS2;No ttyS3 */
+#        endif
+#        undef TTYS2_DEV                   /* No ttyS2 */
+#        undef TTYS3_DEV                   /* No ttyS3 */
+#      endif
+#    endif
+#  elif defined(CONFIG_USART3_SERIAL_CONSOLE)
+#    define CONSOLE_DEV     g_uart3port    /* USART3=console */
+#    define TTYS0_DEV       g_uart3port    /* USART3=ttyS0 */
+#    ifdef CONFIG_LPC43_USART0
+#      define TTYS1_DEV     g_uart0port    /* USART3=ttyS0;USART0=ttyS1 */
+#      ifdef CONFIG_LPC43_UART1
+#        define TTYS2_DEV   g_uart1port    /* USART3=ttyS0;USART0=ttyS1;UART1=ttyS2 */
+#        ifdef CONFIG_LPC43_USART2
+#          define TTYS3_DEV g_uart2port    /* USART3=ttyS0;USART0=ttyS1;UART1=ttyS2;USART2=ttyS3 */
+#        else
+#          undef TTYS3_DEV                 /* USART3=ttyS0;USART0=ttyS1;UART1=ttyS;No ttyS3 */
+#        endif
+#      else
+#        ifdef CONFIG_LPC43_USART2
+#          define TTYS2_DEV g_uart2port    /* USART3=ttyS0;USART0=ttyS1;USART2=ttys2;No ttyS3 */
+#        else
+#          undef TTYS2_DEV                 /* USART3=ttyS0;USART0=ttyS1;No ttyS2;No ttyS3 */
+#        endif
+#          undef TTYS3_DEV                 /* No ttyS3 */
+#      endif
+#    else
+#      ifdef CONFIG_LPC43_UART1
+#        define TTYS1_DEV   g_uart1port    /* USART3=ttyS0;UART1=ttyS1 */
+#        ifdef CONFIG_LPC43_USART2
+#          define TTYS2_DEV g_uart2port    /* USART3=ttyS0;UART1=ttyS1;USART2=ttyS2;No ttyS3 */
+#        else
+#          undef TTYS2_DEV                 /* USART3=ttyS0;UART1=ttyS1;No ttyS2;No ttyS3 */
+#        endif
+#        undef TTYS3_DEV                   /* No ttyS3 */
+#      else
+#        ifdef CONFIG_LPC43_USART2
+#          define TTYS1_DEV   g_uart2port  /* USART3=ttyS0;USART2=ttyS1;No ttyS3;No ttyS3 */
+#          undef TTYS3_DEV                 /* USART3=ttyS0;USART2=ttyS1;No ttyS2;No ttyS3 */
+#        else
+#          undef TTYS1_DEV                 /* USART3=ttyS0;No ttyS1;No ttyS2;No ttyS3 */
+#        endif
+#        undef TTYS2_DEV                   /* No ttyS2 */
+#        undef TTYS3_DEV                   /* No ttyS3 */
+#      endif
+#    endif
+#  endif
+#else /* No console */
+#  define TTYS0_DEV       g_uart0port      /* USART0=ttyS0 */
+#  ifdef CONFIG_LPC43_UART1
+#    define TTYS1_DEV     g_uart1port      /* USART0=ttyS0;UART1=ttyS1 */
+#    ifdef CONFIG_LPC43_USART2
+#      define TTYS2_DEV   g_uart2port      /* USART0=ttyS0;UART1=ttyS1;USART2=ttyS2 */
+#      ifdef CONFIG_LPC43_USART3
+#        define TTYS3_DEV g_uart3port      /* USART0=ttyS0;UART1=ttyS1;USART2=ttyS2;USART3=ttyS3 */
+#      else
+#        undef TTYS3_DEV                   /* USART0=ttyS0;UART1=ttyS1;USART2=ttyS;No ttyS3 */
+#      endif
+#    else
+#      ifdef CONFIG_LPC43_USART3
+#        define TTYS2_DEV g_uart3port      /* USART0=ttyS0;UART1=ttyS1;USART3=ttys2;No ttyS3 */
+#      else
+#        undef TTYS2_DEV                   /* USART0=ttyS0;UART1=ttyS1;No ttyS2;No ttyS3 */
+#      endif
+#      undef TTYS3_DEV                     /* No ttyS3 */
+#    endif
+#  else
+#    ifdef CONFIG_LPC43_USART2
+#      define TTYS1_DEV   g_uart2port     /* USART0=ttyS0;USART2=ttyS1;No ttyS3 */
+#      ifdef CONFIG_LPC43_USART3
+#        define TTYS2_DEV g_uart3port     /* USART0=ttyS0;USART2=ttyS1;USART3=ttyS2;No ttyS3 */
+#      else
+#        undef TTYS2_DEV                  /* USART0=ttyS0;USART2=ttyS1;No ttyS2;No ttyS3 */
+#      endif
+#      undef TTYS3_DEV                    /* No ttyS3 */
+#    else
+#      ifdef CONFIG_LPC43_USART3
+#        define TTYS1_DEV g_uart3port     /* USART0=ttyS0;USART3=ttyS1;No ttyS2;No ttyS3 */
+#      else
+#        undef TTYS1_DEV                  /* USART0=ttyS0;No ttyS1;No ttyS2;No ttyS3 */
+#      endif
+#        undef TTYS2_DEV                  /* No ttyS2 */
+#      undef TTYS3_DEV                    /* No ttyS3 */
+#    endif
+#  endif
+#endif /*HAVE_CONSOLE*/
+
+/****************************************************************************
+ * Inline Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_serialin
+ ****************************************************************************/
+
+static inline uint32_t up_serialin(struct up_dev_s *priv, int offset)
+{
+  return getreg32(priv->uartbase + offset);
+}
+
+/****************************************************************************
+ * Name: up_serialout
+ ****************************************************************************/
+
+static inline void up_serialout(struct up_dev_s *priv, int offset, uint32_t value)
+{
+  putreg32(value, priv->uartbase + offset);
+}
+
+/****************************************************************************
+ * Name: up_disableuartint
+ ****************************************************************************/
+
+static inline void up_disableuartint(struct up_dev_s *priv, uint32_t *ier)
+{
+  if (ier)
+    {
+      *ier = priv->ier & UART_IER_ALLIE;
+    }
+
+  priv->ier &= ~UART_IER_ALLIE;
+  up_serialout(priv, LPC43_UART_IER_OFFSET, priv->ier);
+}
+
+/****************************************************************************
+ * Name: up_restoreuartint
+ ****************************************************************************/
+
+static inline void up_restoreuartint(struct up_dev_s *priv, uint32_t ier)
+{
+  priv->ier |= ier & UART_IER_ALLIE;
+  up_serialout(priv, LPC43_UART_IER_OFFSET, priv->ier);
+}
+
+/****************************************************************************
+ * Name: up_enablebreaks
+ ****************************************************************************/
+
+static inline void up_enablebreaks(struct up_dev_s *priv, bool enable)
+{
+  uint32_t lcr = up_serialin(priv, LPC43_UART_LCR_OFFSET);
+  if (enable)
+    {
+      lcr |= UART_LCR_BRK;
+    }
+  else
+    {
+      lcr &= ~UART_LCR_BRK;
+    }
+  up_serialout(priv, LPC43_UART_LCR_OFFSET, lcr);
+}
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_setup
+ *
+ * Description:
+ *   Configure the UART baud, bits, parity, fifos, etc. This method is
+ *   called the first time that the serial port is opened.
+ *
+ ****************************************************************************/
+
+static int up_setup(struct uart_dev_s *dev)
+{
+#ifndef CONFIG_SUPPRESS_LPC43_UART_CONFIG
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  uint32_t lcr;
+
+  /* Clear fifos */
+
+  up_serialout(priv, LPC43_UART_FCR_OFFSET, (UART_FCR_RXRST|UART_FCR_TXRST));
+
+  /* Set trigger */
+
+  up_serialout(priv, LPC43_UART_FCR_OFFSET, (UART_FCR_FIFOEN|UART_FCR_RXTRIGGER_8));
+
+  /* Set up the IER */
+
+  priv->ier = up_serialin(priv, LPC43_UART_IER_OFFSET);
+
+  /* Set up the LCR */
+
+  lcr = 0;
+
+  if (priv->bits == 7)
+    {
+      lcr |= UART_LCR_WLS_7BIT;
+    }
+  else
+    {
+      lcr |= UART_LCR_WLS_8BIT;
+    }
+
+  if (priv->stopbits2)
+    {
+      lcr |= UART_LCR_STOP;
+    }
+
+  if (priv->parity == 1)
+    {
+      lcr |= (UART_LCR_PE|UART_LCR_PS_ODD);
+    }
+  else if (priv->parity == 2)
+    {
+      lcr |= (UART_LCR_PE|UART_LCR_PS_EVEN);
+    }
+
+  /* Save the LCR */
+
+  up_serialout(priv, LPC43_UART_LCR_OFFSET, lcr);
+
+  /* Set the BAUD divisor */
+
+  lpc43_setbaud(priv->uartbase, priv->basefreq, priv->baud);
+
+  /* Configure the FIFOs */
+
+  up_serialout(priv, LPC43_UART_FCR_OFFSET,
+               (UART_FCR_RXTRIGGER_8|UART_FCR_TXRST|UART_FCR_RXRST|UART_FCR_FIFOEN));
+
+  /* Enable Auto-RTS and Auto-CS Flow Control in the Modem Control Register */
+  
+#ifdef CONFIG_UART1_FLOWCONTROL
+  if (priv->id == 1)
+    {
+      up_serialout(priv, LPC43_UART_MCR_OFFSET, (UART_MCR_RTSEN|UART_MCR_CTSEN));
+    }
+#endif
+
+#endif
+  return OK;
+}
+
+/****************************************************************************
+ * Name: up_shutdown
+ *
+ * Description:
+ *   Disable the UART.  This method is called when the serial port is closed
+ *
+ ****************************************************************************/
+
+static void up_shutdown(struct uart_dev_s *dev)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+
+  /* Disable further interrupts from the U[S]ART */
+
+  up_disableuartint(priv, NULL);
+
+  /* Put the U[S]ART hardware back its reset state */
+
+  switch (priv->id)
+    {
+  #ifdef CONFIG_LPC43_USART0
+      case 0:
+        lpc43_usart0_reset();
+        break;
+  #endif
+
+  #ifdef CONFIG_LPC43_UART1
+      case 1:
+        lpc43_uart1_reset();
+        break;
+  #endif
+
+  #ifdef CONFIG_LPC43_USART2
+      case 2:
+        lpc43_usart2_reset();
+        break;
+  #endif
+
+  #ifdef CONFIG_LPC43_USART3
+      case 3:
+        lpc43_usart3_reset();
+        break;
+  #endif
+
+      default:
+        break;
+    }
+}
+
+/****************************************************************************
+ * Name: up_attach
+ *
+ * Description:
+ *   Configure the UART to operation in interrupt driven mode.  This method is
+ *   called when the serial port is opened.  Normally, this is just after the
+ *   the setup() method is called, however, the serial console may operate in
+ *   a non-interrupt driven mode during the boot phase.
+ *
+ *   RX and TX interrupts are not enabled when by the attach method (unless the
+ *   hardware supports multiple levels of interrupt enabling).  The RX and TX
+ *   interrupts are not enabled until the txint() and rxint() methods are called.
+ *
+ ****************************************************************************/
+
+static int up_attach(struct uart_dev_s *dev)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  int ret;
+
+  /* Attach and enable the IRQ */
+
+  ret = irq_attach(priv->irq, up_interrupt);
+  if (ret == OK)
+    {
+       /* Enable the interrupt (RX and TX interrupts are still disabled
+        * in the UART
+        */
+
+       up_enable_irq(priv->irq);
+    }
+  return ret;
+}
+
+/****************************************************************************
+ * Name: up_detach
+ *
+ * Description:
+ *   Detach UART interrupts.  This method is called when the serial port is
+ *   closed normally just before the shutdown method is called.  The exception is
+ *   the serial console which is never shutdown.
+ *
+ ****************************************************************************/
+
+static void up_detach(struct uart_dev_s *dev)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  up_disable_irq(priv->irq);
+  irq_detach(priv->irq);
+}
+
+/****************************************************************************
+ * Name: up_interrupt
+ *
+ * Description:
+ *   This is the UART interrupt handler.  It will be invoked when an
+ *   interrupt received on the 'irq'  It should call uart_transmitchars or
+ *   uart_receivechar to perform the appropriate data transfers.  The
+ *   interrupt handling logic must be able to map the 'irq' number into the
+ *   appropriate uart_dev_s structure in order to call these functions.
+ *
+ ****************************************************************************/
+
+static int up_interrupt(int irq, void *context)
+{
+  struct uart_dev_s *dev = NULL;
+  struct up_dev_s   *priv;
+  uint32_t           status;
+  int                passes;
+
+#ifdef CONFIG_LPC43_USART0
+  if (g_uart0priv.irq == irq)
+    {
+      dev = &g_uart0port;
+    }
+  else
+#endif
+#ifdef CONFIG_LPC43_UART1
+  if (g_uart1priv.irq == irq)
+    {
+      dev = &g_uart1port;
+    }
+  else
+#endif
+#ifdef CONFIG_LPC43_USART2
+  if (g_uart2priv.irq == irq)
+    {
+      dev = &g_uart2port;
+    }
+  else
+#endif
+#ifdef CONFIG_LPC43_USART3
+  if (g_uart3priv.irq == irq)
+    {
+      dev = &g_uart3port;
+    }
+  else
+#endif
+    {
+      PANIC(OSERR_INTERNAL);
+    }
+  priv = (struct up_dev_s*)dev->priv;
+
+  /* Loop until there are no characters to be transferred or,
+   * until we have been looping for a long time.
+   */
+
+  for (passes = 0; passes < 256; passes++)
+    {
+      /* Get the current UART status and check for loop
+       * termination conditions
+       */
+
+       status = up_serialin(priv, LPC43_UART_IIR_OFFSET);
+
+      /* The UART_IIR_INTSTATUS bit should be zero if there are pending
+       * interrupts
+       */
+
+      if ((status & UART_IIR_INTSTATUS) != 0)
+        {
+          /* Break out of the loop when there is no longer a
+           * pending interrupt
+           */
+
+          break;
+        }
+
+      /* Handle the interrupt by its interrupt ID field */
+
+      switch (status & UART_IIR_INTID_MASK)
+        {
+          /* Handle incoming, receive bytes (with or without timeout) */
+
+          case UART_IIR_INTID_RDA:
+          case UART_IIR_INTID_CTI:
+            {
+              uart_recvchars(dev);
+              break;
+            }
+
+          /* Handle outgoing, transmit bytes */
+
+          case UART_IIR_INTID_THRE:
+            {
+              uart_xmitchars(dev);
+              break;
+            }
+
+          /* Just clear modem status interrupts (UART1 only) */
+
+          case UART_IIR_INTID_MSI:
+            {
+              /* Read the modem status register (MSR) to clear */
+
+              status = up_serialin(priv, LPC43_UART_MSR_OFFSET);
+              vdbg("MSR: %02x\n", status);
+              break;
+            }
+
+          /* Just clear any line status interrupts */
+
+          case UART_IIR_INTID_RLS:
+            {
+              /* Read the line status register (LSR) to clear */
+
+              status = up_serialin(priv, LPC43_UART_LSR_OFFSET);
+              vdbg("LSR: %02x\n", status);
+              break;
+            }
+
+          /* There should be no other values */
+
+          default:
+            {
+              dbg("Unexpected IIR: %02x\n", status);
+              break;
+            }
+        }
+    }
+    return OK;
+}
+
+/****************************************************************************
+ * Name: up_set_rs485_mode
+ *
+ * Description:
+ *   Handle LPC43xx USART0,2,3 RS485 mode set ioctl (TIOCSRS485) to enable
+ *   and disable RS-485 mode.  This is part of the serial ioctl logic.
+ *
+ *   Supported and un-supported LPC43 RS-485 features:
+ *
+ *     RS-485/EIA-485 Normal Multidrop Mode (NMM) -- NOT suppored
+ *
+ *       In this mode, an address is detected when a received byte causes the
+ *       USART to set the parity error and generate an interrupt.  When the
+ *       parity error interrupt will be generated and the processor can decide
+ *       whether or not to disable the receiver.
+ *
+ *     RS-485/EIA-485 Auto Address Detection (AAD) mode -- NOT supported
+ *
+ *       In this mode, the receiver will compare any address byte received
+ *       (parity = ‘1’) to the 8-bit value programmed into the RS485ADRMATCH
+ *       register.  When a matching address character is detected it will be
+ *       pushed onto the RXFIFO along with the parity bit, and the receiver
+ *       will be automatically enabled.
+ *
+ *       When an address byte which does not match the RS485ADRMATCH value
+ *       is received, the receiver will be automatically disabled in hardware.
+ *
+ *     RS-485/EIA-485 Auto Direction Control -- Supported
+ *
+ *       Allow the transmitter to automatically control the state of the DIR
+ *       pin as a direction control output signal.  The DIR pin will be asserted
+ *       (driven LOW) when the CPU writes data into the TXFIFO. The pin will be
+ *       de-asserted (driven HIGH) once the last bit of data has been transmitted.
+ *
+ *     RS485/EIA-485 driver delay time -- Supported
+ * 
+ *       The driver delay time is the delay between the last stop bit leaving
+ *       the TXFIFO and the de-assertion of the DIR pin. This delay time can be
+ *       programmed in the 8-bit RS485DLY register. The delay time is in periods
+ *       of the baud clock.
+ *
+ *     RS485/EIA-485 output inversion -- Supported
+ *
+ *       The polarity of the direction control signal on the DIR pin can be
+ *       reversed by programming bit 5 in the RS485CTRL register.
+ *
+ ****************************************************************************/
+
+#ifdef HAVE_RS485
+static inline int up_set_rs485_mode(struct up_dev_s *priv,
+                                    const struct serial_rs485 *mode)
+{
+  irqstate_t flags;
+  uint32_t   regval;
+  uint64_t   tmp;
+
+  DEBUGASSERT(priv && mode);
+  flags = irqsave();
+
+  /* Are we enabling or disabling RS-485 support? */
+
+  if ((mode->flags && SER_RS485_RTS_ON_SEND) != 0)
+    {
+      /* Disable all RS-485 features */
+
+      up_serialout(priv, LPC43_UART_RS485CTRL_OFFSET, 0);
+    }
+  else
+    {
+      /* Set the RS-485/EIA-485 Control register:
+       * 
+       *  NMMEN 0 = Normal Multidrop Mode (NMM) disabled
+       *  RXDIS 0 = Receiver is not disabled
+       *  AADEN 0 = Auto Address Detect (ADD) is disabled
+       *  DCTRL 1 = Auto Direction Control is enabled
+       *  OINV  ? = Value control by user mode settings   
+       */
+
+      regval = UART_RS485CTRL_DCTRL;
+
+      /* Logic levels are controlled by the SER_RS485_RTS_ON_SEND and
+       * SER_RS485_RTS_AFTER_SEND bits in the mode flags. 
+       * SER_RS485_RTS_AFTER_SEND is ignored.
+       *
+       * By default, DIR will go logic low on send, but this can 
+       * be inverted.
+       */
+
+      if ((mode->flags && SER_RS485_RTS_ON_SEND) != 0)
+        {
+          regval |= UART_RS485CTRL_OINV;
+        }
+
+      up_serialout(priv, LPC43_UART_RS485CTRL_OFFSET, regval);
+
+      /* We only have control of the delay after send.  Time provided
+       * is in milliseconds; this must be converted to the baud clock.
+       * The baud clock should be 16 times the currently selected BAUD.
+       *
+       * Eg. Given BAUD=115,200, then a delay of n milliseconds would be:
+       *
+       *  115,200 * n / 1000 = 11525 clocks.
+       *
+       *    n=1: 115 (OK)
+       *    n=2: 230 (OK)
+       *    n>2: Out of range
+       *
+       * The valid range is 0 to 255 bit times.
+       *
+       * REVISIT:  Is this time in bit time or in terms of the baud clock?
+       * The text says either interchange-ably.  Baud clock is 16 x BAUD
+       * and a bit time is 1/BAUD.  The value range of values 0-255 suggests
+       * BAUD bit times, not the baud clock.
+       */
+
+      if (mode->delay_rts_after_send > 0)
+        {
+          regval = 0;
+        }
+      else
+        {
+           tmp = ((priv->baud << 4) * mode->delay_rts_after_send) / 1000;
+           if (tmp > 255)
+             {
+               regval = 255;
+             }
+           else
+             {
+               regval = (uint32_t)tmp;
+             }
+        }
+
+
+      up_serialout(priv, LPC43_UART_RS485DLY_OFFSET, regval);
+    }
+
+  irqrestore(flags);
+  return OK;
+}
+#endif
+
+/****************************************************************************
+ * Name: up_get_rs485_mode
+ *
+ * Description:
+ *   Handle LPC43xx USART0,2,3 RS485 mode get ioctl (TIOCGRS485) to get the
+ *   current RS-485 mode.
+ *
+ ****************************************************************************/
+
+#ifdef HAVE_RS485
+static inline int up_get_rs485_mode(struct up_dev_s *priv,
+                                    struct serial_rs485 *mode)
+{
+  irqstate_t flags;
+  uint32_t regval;
+
+  DEBUGASSERT(priv && mode);
+  flags = irqsave();
+
+  /* Assume disabled */
+
+   memset(mode, 0, sizeof(struct serial_rs485));
+
+  /* If RS-485 mode is enabled, then the DCTRL will be set in the RS485CTRL
+   * register.
+   */
+
+  regval = up_serialin(priv, LPC43_UART_RS485CTRL_OFFSET);
+  if ((regval & UART_RS485CTRL_DCTRL) != 0)
+    {
+      /* RS-485 mode is enabled */
+
+      mode->flags = SER_RS485_ENABLED;
+
+      /* Check if DIR is inverted */
+
+      if ((regval & UART_RS485CTRL_OINV) != 0)
+        {
+          mode->flags = (SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND);
+        }
+      else
+        {
+          mode->flags = SER_RS485_ENABLED;
+        }
+
+      /* We only have control of the delay after send.  Time must be
+       * returned in milliseconds; this must be converted from the baud clock.
+       * (The baud clock should be 16 times the currently selected BAUD.)
+       *
+       *   msec = 1000 * dly / baud
+       */
+
+       regval = up_serialin(priv, LPC43_UART_RS485DLY_OFFSET);
+       mode->delay_rts_after_send = (1000 * regval) / priv->baud;
+    }
+
+  irqrestore(flags);
+  return OK;
+}
+#endif
+
+/****************************************************************************
+ * Name: up_ioctl
+ *
+ * Description:
+ *   All ioctl calls will be routed through this method
+ *
+ ****************************************************************************/
+
+static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
+{
+  struct inode      *inode = filep->f_inode;
+  struct uart_dev_s *dev   = inode->i_private;
+  struct up_dev_s   *priv  = (struct up_dev_s*)dev->priv;
+  int                ret    = OK;
+
+  switch (cmd)
+    {
+    case TIOCSERGSTRUCT:
+      {
+         struct up_dev_s *user = (struct up_dev_s*)arg;
+         if (!user)
+           {
+             ret = -EINVAL;
+           }
+         else
+           {
+             memcpy(user, dev, sizeof(struct up_dev_s));
+           }
+       }
+       break;
+
+#ifdef CONFIG_SERIAL_TERMIOS
+    case TCGETS:
+      {
+        struct termios *termiosp = (struct termios*)arg;
+
+        if (!termiosp)
+          {
+            ret = -EINVAL;
+            break;
+          }
+
+        /* TODO:  Other termios fields are not yet returned.
+         * Note that only cfsetospeed is not necessary because we have
+         * knowledge that only one speed is supported.
+         */
+
+        cfsetispeed(termiosp, priv->baud);
+      }
+      break;
+
+    case TCSETS:
+      {
+        struct termios *termiosp = (struct termios*)arg;
+
+        if (!termiosp)
+          {
+            ret = -EINVAL;
+            break;
+          }
+
+        /* TODO:  Handle other termios settings.
+         * Note that only cfgetispeed is used besued we have knowledge
+         * that only one speed is supported.
+         */
+
+        priv->baud = cfgetispeed(termiosp);
+        lpc43_setbaud(priv->uartbase, priv->basefreq, priv->baud);
+      }
+      break;
+#endif
+
+    case TIOCSBRK:  /* BSD compatibility: Turn break on, unconditionally */
+      {
+        irqstate_t flags = irqsave();
+        up_enablebreaks(priv, true);
+        irqrestore(flags);
+      }
+      break;
+
+    case TIOCCBRK:  /* BSD compatibility: Turn break off, unconditionally */
+      {
+        irqstate_t flags;
+        flags = irqsave();
+        up_enablebreaks(priv, false);
+        irqrestore(flags);
+      }
+      break;
+
+#ifdef HAVE_RS485
+    case TIOCSRS485:  /* Set RS485 mode, arg: pointer to struct serial_rs485 */
+      {
+        ret = up_set_rs485_mode(priv,
+                                (const struct serial_rs485 *)((uintptr_t)arg));
+      }
+      break;
+
+    case TIOCGRS485:  /* Get RS485 mode, arg: pointer to struct serial_rs485 */
+      {
+        ret = up_get_rs485_mode(priv,
+                                (struct serial_rs485 *)((uintptr_t)arg));
+      }
+      break;
+#endif
+
+    default:
+      ret = -ENOTTY;
+      break;
+    }
+
+  return ret;
+}
+
+/****************************************************************************
+ * Name: up_receive
+ *
+ * Description:
+ *   Called (usually) from the interrupt level to receive one
+ *   character from the UART.  Error bits associated with the
+ *   receipt are provided in the return 'status'.
+ *
+ ****************************************************************************/
+
+static int up_receive(struct uart_dev_s *dev, uint32_t *status)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  uint32_t rbr;
+
+  *status = up_serialin(priv, LPC43_UART_LSR_OFFSET);
+  rbr     = up_serialin(priv, LPC43_UART_RBR_OFFSET);
+  return rbr;
+}
+
+/****************************************************************************
+ * Name: up_rxint
+ *
+ * Description:
+ *   Call to enable or disable RX interrupts
+ *
+ ****************************************************************************/
+
+static void up_rxint(struct uart_dev_s *dev, bool enable)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  if (enable)
+    {
+#ifndef CONFIG_SUPPRESS_SERIAL_INTS
+      priv->ier |= UART_IER_RBRIE;
+#endif
+    }
+  else
+    {
+      priv->ier &= ~UART_IER_RBRIE;
+    }
+
+  up_serialout(priv, LPC43_UART_IER_OFFSET, priv->ier);
+}
+
+/****************************************************************************
+ * Name: up_rxavailable
+ *
+ * Description:
+ *   Return true if the receive fifo is not empty
+ *
+ ****************************************************************************/
+
+static bool up_rxavailable(struct uart_dev_s *dev)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  return ((up_serialin(priv, LPC43_UART_LSR_OFFSET) & UART_LSR_RDR) != 0);
+}
+
+/****************************************************************************
+ * Name: up_send
+ *
+ * Description:
+ *   This method will send one byte on the UART
+ *
+ ****************************************************************************/
+
+static void up_send(struct uart_dev_s *dev, int ch)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  up_serialout(priv, LPC43_UART_THR_OFFSET, (uint32_t)ch);
+}
+
+/****************************************************************************
+ * Name: up_txint
+ *
+ * Description:
+ *   Call to enable or disable TX interrupts
+ *
+ ****************************************************************************/
+
+static void up_txint(struct uart_dev_s *dev, bool enable)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  irqstate_t flags;
+
+  flags = irqsave();
+  if (enable)
+    {
+#ifndef CONFIG_SUPPRESS_SERIAL_INTS
+      priv->ier |= UART_IER_THREIE;
+      up_serialout(priv, LPC43_UART_IER_OFFSET, priv->ier);
+
+      /* Fake a TX interrupt here by just calling uart_xmitchars() with
+       * interrupts disabled (note this may recurse).
+       */
+
+      uart_xmitchars(dev);
+#endif
+    }
+  else
+    {
+      priv->ier &= ~UART_IER_THREIE;
+      up_serialout(priv, LPC43_UART_IER_OFFSET, priv->ier);
+    }
+  irqrestore(flags);
+}
+
+/****************************************************************************
+ * Name: up_txready
+ *
+ * Description:
+ *   Return true if the tranmsit fifo is not full
+ *
+ ****************************************************************************/
+
+static bool up_txready(struct uart_dev_s *dev)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  return ((up_serialin(priv, LPC43_UART_LSR_OFFSET) & UART_LSR_THRE) != 0);
+}
+
+/****************************************************************************
+ * Name: up_txempty
+ *
+ * Description:
+ *   Return true if the transmit fifo is empty
+ *
+ ****************************************************************************/
+
+static bool up_txempty(struct uart_dev_s *dev)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  return ((up_serialin(priv, LPC43_UART_LSR_OFFSET) & UART_LSR_THRE) != 0);
+}
+
+/****************************************************************************
+ * Public Funtions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_serialinit
+ *
+ * Description:
+ *   Performs the low level UART initialization early in debug so that the
+ *   serial console will be available during bootup.  This must be called
+ *   before up_serialinit.
+ *
+ *   NOTE: Configuration of the CONSOLE UART was performed by up_lowsetup()
+ *   very early in the boot sequence.
+ *
+ ****************************************************************************/
+
+void up_earlyserialinit(void)
+{
+  /* Configure all UARTs (except the CONSOLE UART) and disable interrupts */
+
+#ifdef CONFIG_LPC43_USART0
+#ifndef CONFIG_USART0_SERIAL_CONSOLE
+  lpc43_usart0_setup();
+#endif
+  up_disableuartint(&g_uart0priv, NULL);
+#endif
+
+#ifdef CONFIG_LPC43_UART1
+#ifndef CONFIG_UART1_SERIAL_CONSOLE
+  lpc43_uart1_setup();
+#endif
+  up_disableuartint(&g_uart1priv, NULL);
+#endif
+
+#ifdef CONFIG_LPC43_USART2
+#ifndef CONFIG_USART2_SERIAL_CONSOLE
+  lpc43_usart2_setup();
+#endif
+  up_disableuartint(&g_uart2priv, NULL);
+#endif
+
+#ifdef CONFIG_LPC43_USART3
+#ifndef CONFIG_USART3_SERIAL_CONSOLE
+  lpc43_usart3_setup();
+#endif
+  up_disableuartint(&g_uart3priv, NULL);
+#endif
+
+  /* Configuration whichever one is the console */
+
+#ifdef CONSOLE_DEV
+  CONSOLE_DEV.isconsole = true;
+  up_setup(&CONSOLE_DEV);
+#endif
+}
+
+/****************************************************************************
+ * Name: up_serialinit
+ *
+ * Description:
+ *   Register serial console and serial ports.  This assumes that
+ *   up_earlyserialinit was called previously.
+ *
+ ****************************************************************************/
+
+void up_serialinit(void)
+{
+#ifdef CONSOLE_DEV
+  (void)uart_register("/dev/console", &CONSOLE_DEV);
+#endif
+#ifdef TTYS0_DEV
+  (void)uart_register("/dev/ttyS0", &TTYS0_DEV);
+#endif
+#ifdef TTYS1_DEV
+  (void)uart_register("/dev/ttyS1", &TTYS1_DEV);
+#endif
+#ifdef TTYS2_DEV
+  (void)uart_register("/dev/ttyS2", &TTYS2_DEV);
+#endif
+#ifdef TTYS3_DEV
+  (void)uart_register("/dev/ttyS3", &TTYS3_DEV);
+#endif
+}
+
+/****************************************************************************
+ * Name: up_putc
+ *
+ * Description:
+ *   Provide priority, low-level access to support OS debug  writes
+ *
+ ****************************************************************************/
+
+int up_putc(int ch)
+{
+#ifdef HAVE_CONSOLE
+  struct up_dev_s *priv = (struct up_dev_s*)CONSOLE_DEV.priv;
+  uint32_t ier;
+  up_disableuartint(priv, &ier);
+#endif
+
+  /* Check for LF */
+
+  if (ch == '\n')
+    {
+      /* Add CR */
+
+      up_lowputc('\r');
+    }
+
+  up_lowputc(ch);
+#ifdef HAVE_CONSOLE
+  up_restoreuartint(priv, ier);
+#endif
+
+  return ch;
+}
+
+#else /* USE_SERIALDRIVER */
+
+/****************************************************************************
+ * Name: up_putc
+ *
+ * Description:
+ *   Provide priority, low-level access to support OS debug writes
+ *
+ ****************************************************************************/
+
+int up_putc(int ch)
+{
+#ifdef HAVE_UART
+  /* Check for LF */
+
+  if (ch == '\n')
+    {
+      /* Add CR */
+
+      up_lowputc('\r');
+    }
+
+  up_lowputc(ch);
+#endif
+  return ch;
+}
+
+#endif /* USE_SERIALDRIVER */
diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_serial.h b/nuttx/arch/arm/src/lpc43xx/lpc43_serial.h
new file mode 100644
index 000000000..f29a99023
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/lpc43_serial.h
@@ -0,0 +1,66 @@
+/****************************************************************************
+ * arch/arm/src/lpc43xx/lpc43_serial.h
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LPC43XX_LPC43_SERIAL_H
+#define __ARCH_ARM_SRC_LPC43XX_LPC43_SERIAL_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include "lpc43_uart.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Inline Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_LPC43XX_LPC43_SERIAL_H */
diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_spi.c b/nuttx/arch/arm/src/lpc43xx/lpc43_spi.c
new file mode 100644
index 000000000..52910a4a1
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/lpc43_spi.c
@@ -0,0 +1,604 @@
+/****************************************************************************
+ * arch/arm/src/lpc43xx/lpc43_spi.c
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <semaphore.h>
+#include <errno.h>
+#include <debug.h>
+
+#include <arch/board/board.h>
+#include <nuttx/arch.h>
+#include <nuttx/spi.h>
+
+#include "up_internal.h"
+#include "up_arch.h"
+
+#include "chip.h"
+#include "lpc43_syscon.h"
+#include "lpc43_pinconn.h"
+#include "lpc43_spi.h"
+
+#ifdef CONFIG_LPC43_SPI
+
+/****************************************************************************
+ * Definitions
+ ****************************************************************************/
+
+/* Enables debug output from this file (needs CONFIG_DEBUG too) */
+
+#ifdef CONFIG_DEBUG_SPI
+#  define spidbg  lldbg
+#  ifdef CONFIG_DEBUG_VERBOSE
+#    define spivdbg lldbg
+#  else
+#    define spivdbg(x...)
+#  endif
+#else
+#  undef CONFIG_DEBUG_VERBOSE
+#  define spidbg(x...)
+#  define spivdbg(x...)
+#endif
+
+/* SPI Clocking.
+ *
+ * The CPU clock by 1, 2, 4, or 8 to get the SPI peripheral clock (SPI_CLOCK).
+ * SPI_CLOCK may be further divided by 8-254 to get the SPI clock.  If we
+ * want a usable range of 4KHz to 25MHz for the SPI, then:
+ *
+ * 1. SPICLK must be greater than (8*25MHz) = 200MHz (so we can't reach 25MHz),
+ *    and
+ * 2. SPICLK must be less than (254*40Khz) = 101.6MHz.
+ *
+ * If we assume that CCLK less than or equal to 100MHz, we can just
+ * use the CCLK undivided to get the SPI_CLOCK.
+ */
+
+#define SPI_PCLKSET_DIV    SYSCON_PCLKSEL_CCLK
+#define SPI_CLOCK          LPC43_CCLK
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/* This structure descibes the state of the SSP driver */
+
+struct lpc43_spidev_s
+{
+  struct spi_dev_s spidev;     /* Externally visible part of the SPI interface */
+#ifndef CONFIG_SPI_OWNBUS
+  sem_t            exclsem;    /* Held while chip is selected for mutual exclusion */
+  uint32_t         frequency;  /* Requested clock frequency */
+  uint32_t         actual;     /* Actual clock frequency */
+  uint8_t          nbits;      /* Width of word in bits (8 to 16) */
+  uint8_t          mode;       /* Mode 0,1,2,3 */
+#endif
+};
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/* SPI methods */
+
+#ifndef CONFIG_SPI_OWNBUS
+static int      spi_lock(FAR struct spi_dev_s *dev, bool lock);
+#endif
+static void     spi_select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected);
+static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency);
+static void     spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode);
+static void     spi_setbits(FAR struct spi_dev_s *dev, int nbits);
+static uint16_t spi_send(FAR struct spi_dev_s *dev, uint16_t ch);
+static void     spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size_t nwords);
+static void     spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nwords);
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static const struct spi_ops_s g_spiops =
+{
+#ifndef CONFIG_SPI_OWNBUS
+  .lock              = spi_lock,
+#endif
+  .select            = lpc43_spiselect,
+  .setfrequency      = spi_setfrequency,
+  .setmode           = spi_setmode,
+  .setbits           = spi_setbits,
+  .status            = lpc43_spistatus,
+#ifdef CONFIG_SPI_CMDDATA
+  .cmddata           = lpc43_spicmddata,
+#endif
+  .send              = spi_send,
+  .sndblock          = spi_sndblock,
+  .recvblock         = spi_recvblock,
+#ifdef CONFIG_SPI_CALLBACK
+  .registercallback  = lpc43_spiregister, /* Provided externally */
+#else
+  .registercallback  = 0,                 /* Not implemented */
+#endif
+};
+
+static struct lpc43_spidev_s g_spidev =
+{
+  .spidev            = { &g_spiops },
+}; 
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: spi_lock
+ *
+ * Description:
+ *   On SPI busses where there are multiple devices, it will be necessary to
+ *   lock SPI to have exclusive access to the busses for a sequence of
+ *   transfers.  The bus should be locked before the chip is selected. After
+ *   locking the SPI bus, the caller should then also call the setfrequency,
+ *   setbits, and setmode methods to make sure that the SPI is properly
+ *   configured for the device.  If the SPI buss is being shared, then it
+ *   may have been left in an incompatible state.
+ *
+ * Input Parameters:
+ *   dev  - Device-specific state data
+ *   lock - true: Lock spi bus, false: unlock SPI bus
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+#ifndef CONFIG_SPI_OWNBUS
+static int spi_lock(FAR struct spi_dev_s *dev, bool lock)
+{
+  FAR struct lpc43_spidev_s *priv = (FAR struct lpc43_spidev_s *)dev;
+
+  if (lock)
+    {
+      /* Take the semaphore (perhaps waiting) */
+
+      while (sem_wait(&priv->exclsem) != 0)
+        {
+          /* The only case that an error should occur here is if the wait was awakened
+           * by a signal.
+           */
+
+          ASSERT(errno == EINTR);
+        }
+    }
+  else
+    {
+      (void)sem_post(&priv->exclsem);
+    }
+  return OK;
+}
+#endif
+
+/****************************************************************************
+ * Name: spi_setfrequency
+ *
+ * Description:
+ *   Set the SPI frequency.
+ *
+ * Input Parameters:
+ *   dev -       Device-specific state data
+ *   frequency - The SPI frequency requested
+ *
+ * Returned Value:
+ *   Returns the actual frequency selected
+ *
+ ****************************************************************************/
+
+static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency)
+{
+  FAR struct lpc43_spidev_s *priv = (FAR struct lpc43_spidev_s *)dev;
+  uint32_t divisor;
+  uint32_t actual;
+
+  /* Check if the requested frequence is the same as the frequency selection */
+
+  DEBUGASSERT(priv && frequency <= SPI_CLOCK / 2);
+#ifndef CONFIG_SPI_OWNBUS
+  if (priv->frequency == frequency)
+    {
+      /* We are already at this frequency.  Return the actual. */
+
+      return priv->actual;
+    }
+#endif
+
+  /* frequency = SPI_CLOCK / divisor, or divisor = SPI_CLOCK / frequency */
+
+  divisor = SPI_CLOCK / frequency;
+
+   /* The SPI CCR register must contain an even number greater than or equal to 8. */
+
+  if (divisor < 8)
+    {
+      divisor = 8;
+    }
+  else if (divisor > 254)
+    {
+      divisor = 254;
+    }
+
+  divisor = (divisor + 1) & ~1;
+
+  /* Save the new divisor value */
+  
+  putreg32(divisor, LPC43_SPI_CCR);
+
+  /* Calculate the new actual */
+
+  actual = SPI_CLOCK / divisor;
+
+  /* Save the frequency setting */
+
+#ifndef CONFIG_SPI_OWNBUS
+  priv->frequency = frequency;
+  priv->actual    = actual;
+#endif
+
+  spidbg("Frequency %d->%d\n", frequency, actual);
+  return actual;
+}
+
+/****************************************************************************
+ * Name: spi_setmode
+ *
+ * Description:
+ *   Set the SPI mode. Optional.  See enum spi_mode_e for mode definitions
+ *
+ * Input Parameters:
+ *   dev -  Device-specific state data
+ *   mode - The SPI mode requested
+ *
+ * Returned Value:
+ *   none
+ *
+ ****************************************************************************/
+
+static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)
+{
+  FAR struct lpc43_spidev_s *priv = (FAR struct lpc43_spidev_s *)dev;
+  uint32_t regval;
+
+  /* Has the mode changed? */
+
+#ifndef CONFIG_SPI_OWNBUS
+  if (mode != priv->mode)
+    {
+#endif
+      /* Yes... Set CR appropriately */
+
+      regval = getreg32(LPC43_SPI_CR);
+      regval &= ~(SPI_CR_CPOL|SPI_CR_CPHA);
+
+      switch (mode)
+        {
+        case SPIDEV_MODE0: /* CPOL=0; CPHA=0 */
+          break;
+ 
+        case SPIDEV_MODE1: /* CPOL=0; CPHA=1 */
+          regval |= SPI_CR_CPHA;
+          break;
+ 
+        case SPIDEV_MODE2: /* CPOL=1; CPHA=0 */
+          regval |= SPI_CR_CPOL;
+          break;
+ 
+        case SPIDEV_MODE3: /* CPOL=1; CPHA=1 */
+          regval |= (SPI_CR_CPOL|SPI_CR_CPHA);
+          break;
+ 
+        default:
+          DEBUGASSERT(FALSE);
+          return;
+        }
+
+      putreg32(regval, LPC43_SPI_CR);
+
+      /* Save the mode so that subsequent re-configuratins will be faster */
+
+#ifndef CONFIG_SPI_OWNBUS
+      priv->mode = mode;
+    }
+#endif
+}
+
+/****************************************************************************
+ * Name: spi_setbits
+ *
+ * Description:
+ *   Set the number if bits per word.
+ *
+ * Input Parameters:
+ *   dev -  Device-specific state data
+ *   nbits - The number of bits requests
+ *
+ * Returned Value:
+ *   none
+ *
+ ****************************************************************************/
+
+static void spi_setbits(FAR struct spi_dev_s *dev, int nbits)
+{
+  FAR struct lpc43_spidev_s *priv = (FAR struct lpc43_spidev_s *)dev;
+  uint32_t regval;
+
+  /* Has the number of bits changed? */
+
+  DEBUGASSERT(priv && nbits > 7 && nbits < 17);
+#ifndef CONFIG_SPI_OWNBUS
+  if (nbits != priv->nbits)
+    {
+#endif
+      /* Yes... Set CR appropriately */
+
+      regval = getreg32(LPC43_SPI_CR);
+      regval &= ~SPI_CR_BITS_MASK;
+      regval |= (nbits << SPI_CR_BITS_SHIFT) & SPI_CR_BITS_MASK;
+      regval |= SPI_CR_BITENABLE;
+      regval = getreg32(LPC43_SPI_CR);
+
+      /* Save the selection so the subsequence re-configurations will be faster */
+
+#ifndef CONFIG_SPI_OWNBUS
+      priv->nbits = nbits;
+    }
+#endif
+}
+
+/****************************************************************************
+ * Name: spi_send
+ *
+ * Description:
+ *   Exchange one word on SPI
+ *
+ * Input Parameters:
+ *   dev - Device-specific state data
+ *   wd  - The word to send.  the size of the data is determined by the
+ *         number of bits selected for the SPI interface.
+ *
+ * Returned Value:
+ *   response
+ *
+ ****************************************************************************/
+
+static uint16_t spi_send(FAR struct spi_dev_s *dev, uint16_t wd)
+{
+  /* Write the data to transmitted to the SPI Data Register */
+
+  putreg32((uint32_t)wd, LPC43_SPI_DR);
+
+  /* Wait for the SPIF bit in the SPI Status Register to be set to 1. The
+   * SPIF bit will be set after the last sampling clock edge of the SPI
+   * data transfer.
+   */
+
+ while ((getreg32(LPC43_SPI_SR) & SPI_SR_SPIF) == 0);
+
+ /* Read the SPI Status Register again to clear the status bit */
+
+ (void)getreg32(LPC43_SPI_SR);
+  return (uint16_t)getreg32(LPC43_SPI_DR);
+}
+
+/*************************************************************************
+ * Name: spi_sndblock
+ *
+ * Description:
+ *   Send a block of data on SPI
+ *
+ * Input Parameters:
+ *   dev -    Device-specific state data
+ *   buffer - A pointer to the buffer of data to be sent
+ *   nwords - the length of data to send from the buffer in number of words.
+ *            The wordsize is determined by the number of bits-per-word
+ *            selected for the SPI interface.  If nbits <= 8, the data is
+ *            packed into uint8_t's; if nbits >8, the data is packed into uint16_t's
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size_t nwords)
+{
+  FAR uint8_t *ptr = (FAR uint8_t*)buffer;
+  uint8_t data;
+
+  spidbg("nwords: %d\n", nwords);
+  while (nwords)
+    {
+      /* Write the data to transmitted to the SPI Data Register */
+
+      data = *ptr++;
+      putreg32((uint32_t)data, LPC43_SPI_DR);
+
+      /* Wait for the SPIF bit in the SPI Status Register to be set to 1. The
+       * SPIF bit will be set after the last sampling clock edge of the SPI
+       * data transfer.
+       */
+
+     while ((getreg32(LPC43_SPI_SR) & SPI_SR_SPIF) == 0);
+
+     /* Read the SPI Status Register again to clear the status bit */
+
+     (void)getreg32(LPC43_SPI_SR);
+     nwords--;
+    }
+}
+
+/****************************************************************************
+ * Name: spi_recvblock
+ *
+ * Description:
+ *   Revice a block of data from SPI
+ *
+ * Input Parameters:
+ *   dev -    Device-specific state data
+ *   buffer - A pointer to the buffer in which to recieve data
+ *   nwords - the length of data that can be received in the buffer in number
+ *            of words.  The wordsize is determined by the number of bits-per-word
+ *            selected for the SPI interface.  If nbits <= 8, the data is
+ *            packed into uint8_t's; if nbits >8, the data is packed into uint16_t's
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nwords)
+{
+  FAR uint8_t *ptr = (FAR uint8_t*)buffer;
+
+  spidbg("nwords: %d\n", nwords);
+  while (nwords)
+    {
+      /* Write some dummy data to the SPI Data Register in order to clock the
+       * read data.
+       */
+
+      putreg32(0xff, LPC43_SPI_DR);
+
+      /* Wait for the SPIF bit in the SPI Status Register to be set to 1. The
+       * SPIF bit will be set after the last sampling clock edge of the SPI
+       * data transfer.
+       */
+
+     while ((getreg32(LPC43_SPI_SR) & SPI_SR_SPIF) == 0);
+
+     /* Read the SPI Status Register again to clear the status bit */
+
+     (void)getreg32(LPC43_SPI_SR);
+
+     /* Read the received data from the SPI Data Register */   
+
+     *ptr++ = (uint8_t)getreg32(LPC43_SPI_DR);
+     nwords--;
+    }
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: lpc43_spiinitialize
+ *
+ * Description:
+ *   Initialize the SPI port
+ *
+ * Input Parameter:
+ *   port Port number (must be zero)
+ *
+ * Returned Value:
+ *   Valid SPI device structure reference on succcess; a NULL on failure
+ *
+ ****************************************************************************/
+
+FAR struct spi_dev_s *lpc43_spiinitialize(int port)
+{
+  FAR struct lpc43_spidev_s *priv = &g_spidev;
+  irqstate_t flags;
+  uint32_t regval;
+
+  /* Configure multiplexed pins as connected on the board.  Chip select
+   * pins must be configured by board-specific logic.  All SPI pins and
+   * one SPI1 pin (SCK) have multiple, alternative pin selection.
+   * Definitions in the board.h file must be provided to resolve the
+   * board-specific pin configuration like:
+   *
+   * #define GPIO_SPI_SCK GPIO_SPI_SCK_1
+   */
+
+  flags = irqsave();
+  lpc43_configgpio(GPIO_SPI_SCK);
+  lpc43_configgpio(GPIO_SPI_MISO);
+  lpc43_configgpio(GPIO_SPI_MOSI);
+
+  /* Configure clocking */
+
+  regval  = getreg32(LPC43_SYSCON_PCLKSEL0);
+  regval &= ~SYSCON_PCLKSEL0_SPI_MASK;
+  regval |= (SPI_PCLKSET_DIV << SYSCON_PCLKSEL0_SPI_SHIFT);
+  putreg32(regval, LPC43_SYSCON_PCLKSEL0);
+
+  /* Enable peripheral clocking to SPI and SPI1 */
+
+  regval  = getreg32(LPC43_SYSCON_PCONP);
+  regval |= SYSCON_PCONP_PCSPI;
+  putreg32(regval, LPC43_SYSCON_PCONP);
+  irqrestore(flags);
+  
+  /* Configure 8-bit SPI mode and master mode */
+
+  putreg32(SPI_CR_BITS_8BITS|SPI_CR_BITENABLE|SPI_CR_MSTR, LPC43_SPI_CR);
+
+  /* Set the initial SPI configuration */
+
+#ifndef CONFIG_SPI_OWNBUS
+  priv->frequency = 0;
+  priv->nbits     = 8;
+  priv->mode      = SPIDEV_MODE0;
+#endif
+
+  /* Select a default frequency of approx. 400KHz */
+
+  spi_setfrequency((FAR struct spi_dev_s *)priv, 400000);
+
+  /* Initialize the SPI semaphore that enforces mutually exclusive access */
+
+#ifndef CONFIG_SPI_OWNBUS
+  sem_init(&priv->exclsem, 0, 1);
+#endif
+  return &priv->spidev;
+}
+
+#endif /* CONFIG_LPC43_SPI */
+
diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_spi.h b/nuttx/arch/arm/src/lpc43xx/lpc43_spi.h
new file mode 100644
index 000000000..28c833826
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/lpc43_spi.h
@@ -0,0 +1,180 @@
+/************************************************************************************
+ * arch/arm/src/lpc43xx/lpc43_spi.h
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LPC43XX_SPI_H
+#define __ARCH_ARM_SRC_LPC43XX_SPI_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/spi.h>
+#include "chip/lpc43_spi.h"
+
+#ifdef CONFIG_LPC43_SPI
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+/* This header file defines interfaces to common SPI logic.  To use this common SPI
+ * logic on your board:
+ *
+ * 1. Provide logic in lpc43_boardinitialize() to configure SPI chip select pins.
+ * 2. Provide the lpc43_spiselect() and lpc43_spistatus() functions in your
+ *    board-specific logic.  These functions will perform chip selection
+ *    and status operations using GPIOs in the way your board is configured.
+ * 3. If CONFIG_SPI_CMDDATA is defined in the NuttX configuration, provide
+ *    lpc43_spicmddata() functions in your board-specific logic.  This
+ *    function will perform cmd/data selection operations using GPIOs in the
+ *    way your board is configured.
+ * 4. Your low level board initialization logic should call lpc43_sspiinitialize.
+ * 5. The handle returned by lpc43_spiinitialize() may then be used to bind the
+ *    SPI driver to higher level logic (e.g., calling  mmcsd_spislotinitialize(),
+ *    for example, will bind the SPI driver to the SPI MMC/SD driver).
+ */
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C" {
+#else
+#define EXTERN extern
+#endif
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Name: lpc43_spiinitialize
+ *
+ * Description:
+ *   Initialize the SPI port
+ *
+ * Input Parameter:
+ *   port Port number (must be zero)
+ *
+ * Returned Value:
+ *   Valid SPI device structure reference on succcess; a NULL on failure
+ *
+ ************************************************************************************/
+
+EXTERN FAR struct spi_dev_s *lpc43_spiinitialize(int port);
+
+/************************************************************************************
+ * Name:  lpc43_spiselect, lpc43_spistatus, and lpc43_spicmddata
+ *
+ * Description:
+ *   These functions must be provided in your board-specific logic.  The
+ *   lpc43_spiselect function will perform chip selection and the lpc43_spistatus
+ *   will perform status operations using GPIOs in the way your board is configured.
+ *
+ *   If CONFIG_SPI_CMDDATA is defined in the NuttX configuration, then
+ *   lpc43_spicmddata must also be provided.  This functions performs cmd/data
+ *   selection operations using GPIOs in the way your board is configured.
+ *
+ ************************************************************************************/
+
+EXTERN void  lpc43_spiselect(FAR struct spi_dev_s *dev, enum spi_dev_e devid,
+                             bool selected);
+EXTERN uint8_t lpc43_spistatus(FAR struct spi_dev_s *dev, enum spi_dev_e devid);
+
+#ifdef CONFIG_SPI_CMDDATA
+EXTERN int lpc43_spicmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid,
+                            bool cmd);
+#endif
+
+/****************************************************************************
+ * Name: spi_flush
+ *
+ * Description:
+ *   Flush and discard any words left in the RX fifo.  This can be called
+ *   from spiselect after a device is deselected (if you worry about such
+ *   things).
+ *
+ * Input Parameters:
+ *   dev - Device-specific state data
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+EXTERN void spi_flush(FAR struct spi_dev_s *dev);
+
+/****************************************************************************
+ * Name: lpc43_spi/spiregister
+ *
+ * Description:
+ *   If the board supports a card detect callback to inform the SPI-based
+ *   MMC/SD drvier when an SD card is inserted or removed, then
+ *   CONFIG_SPI_CALLBACK should be defined and the following function(s) must
+ *   must be implemented.  These functiosn implements the registercallback
+ *   method of the SPI interface (see include/nuttx/spi.h for details)
+ *
+ * Input Parameters:
+ *   dev -      Device-specific state data
+ *   callback - The funtion to call on the media change
+ *   arg -      A caller provided value to return with the callback
+ *
+ * Returned Value:
+ *   0 on success; negated errno on failure.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SPI_CALLBACK
+EXTERN int lpc43_spiregister(FAR struct spi_dev_s *dev,
+                             spi_mediachange_t callback, void *arg);
+#endif
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* CONFIG_LPC43_SPI */
+#endif /* __ARCH_ARM_SRC_LPC43XX_SPI_H */
diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_spifi.c b/nuttx/arch/arm/src/lpc43xx/lpc43_spifi.c
new file mode 100644
index 000000000..ad6ce0ad5
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/lpc43_spifi.c
@@ -0,0 +1,1268 @@
+/****************************************************************************
+ *  arch/arm/src/lpc43/lpc43_spifi.c
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <stdlib.h>
+#include <unistd.h>
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+
+#include <nuttx/kmalloc.h>
+#include <nuttx/fs/ioctl.h>
+#include <nuttx/mtd.h>
+
+#include <arch/irq.h>
+#include <arch/board/board.h>
+
+#include "up_arch.h"
+
+#include "chip.h"
+#include "lpc43_cgu.h"
+#include "lpc43_spifi.h"
+#include "lpc43_pinconfig.h"
+
+#ifdef CONFIG_LPC43_SPIFI
+
+/****************************************************************************
+ * Pre-Processor Definitions
+ ****************************************************************************/
+/* SPIFI Configuration ******************************************************/
+/* This logic supports some special options that can be used to create an
+ * mtd device on the SPIFI FLASH.  NOTE:  CONFIG_LPC43_SPIFI=y must also
+ * be defined to enable SPIFI setup support:
+ *
+ * CONFIG_SPIFI_RDONLY - Create a read only device on SPIFI.
+ * CONFIG_SPIFI_OFFSET - Offset the beginning of the block driver this many
+ *   bytes into the device address space.  This offset must be an exact
+ *   multiple of the erase block size. Default 0.
+ * CONFIG_SPIFI_BLKSIZE - The size of one device erase block.  If not defined
+ *   then the driver will try to determine the correct erase block size by
+ *   examining that data returned from spifi_initialize (which sometimes
+ *   seems bad).
+ * CONFIG_SPIFI_SECTOR512 - If defined, then the driver will report a more
+ *   FAT friendly 512 byte sector size and will manage the read-modify-write
+ *   operations on the larger erase block.
+ * CONFIG_SPIFI_READONLY - Define to support only read-only operations.
+ * CONFIG_SPIFI_LIBRARY - Don't use the LPC43xx ROM routines but, instead,
+ *   use an external library implementation of the SPIFI interface.
+ * CONFIG_SPIFI_VERIFY - Verify all spi_program() operations by reading
+ *   from the SPI address space after each write.
+ * CONFIG_DEBUG_SPIFI_DUMP - Debug option to dump read/write buffers.  You
+ *   probably do not want to enable this unless you want to dig through a
+ *   *lot* of debug output!  Also required CONFIG_DEBUG, CONFIG_DEBUG_VERBOSE,
+ *   and CONFIG_DEBUG_FS,
+ */
+
+/* This is where the LPC43xx address where random-access reads begin */
+
+#define SPIFI_BASE \
+       (FAR uint8_t *)(LPC43_SPIFI_DATA_BASE + CONFIG_SPIFI_OFFSET)
+
+/* Check if we are using a hard-coded block size */
+
+#ifdef CONFIG_SPIFI_BLKSIZE
+#  if CONFIG_SPIFI_BLKSIZE < 512
+#    error "CONFIG_SPIFI_BLKSIZE is too small"
+#  elif CONFIG_SPIFI_BLKSIZE == 512
+#    define SPIFI_BLKSHIFT 9
+#  elif CONFIG_SPIFI_BLKSIZE == 1024
+#    define SPIFI_BLKSHIFT 10
+#  elif CONFIG_SPIFI_BLKSIZE == (2*1024)
+#    define SPIFI_BLKSHIFT 11
+#  elif CONFIG_SPIFI_BLKSIZE == (4*1024)
+#    define SPIFI_BLKSHIFT 12
+#  elif CONFIG_SPIFI_BLKSIZE == (8*1024)
+#    define SPIFI_BLKSHIFT 13
+#  elif CONFIG_SPIFI_BLKSIZE == (16*1024)
+#    define SPIFI_BLKSHIFT 14
+#  elif CONFIG_SPIFI_BLKSIZE == (32*1024)
+#    define SPIFI_BLKSHIFT 15
+#  elif CONFIG_SPIFI_BLKSIZE == (64*1024)
+#    define SPIFI_BLKSHIFT 16
+#  elif CONFIG_SPIFI_BLKSIZE == (128*1024)
+#    define SPIFI_BLKSHIFT 17
+#  elif CONFIG_SPIFI_BLKSIZE == (256*1024)
+#    define SPIFI_BLKSHIFT 18
+#  else
+#    error "Unsupported value of CONFIG_SPIFI_BLKSIZE"
+#  endif
+#  define SPIFI_BLKSIZE  CONFIG_SPIFI_BLKSIZE
+#else
+#  define SPIFI_BLKSIZE  priv->blksize
+#  define SPIFI_BLKSHIFT priv->blkshift
+#endif
+
+/* Can use ROM driver or an external driver library */
+
+#ifndef CONFIG_SPIFI_LIBRARY
+#  define SPIFI_INIT(priv, rom, cshigh, options, mhz) \
+   priv->spifi->spifi_init(rom, cshigh, options, mhz)
+#  define SPIFI_PROGRAM(priv, rom, src, operands) \
+   priv->spifi->spifi_program(rom, src, operands)
+#  define SPIFI_ERASE(priv, rom, operands) \
+   priv->spifi->spifi_erase(rom, operands)
+#else
+#  define SPIFI_INIT(priv, rom, cshigh, options, mhz) \
+   spifi_init(rom, cshigh, options, mhz)
+#  define SPIFI_PROGRAM(priv, rom, src, operands) \
+   spifi_program(rom, src, operands)
+#  define SPIFI_ERASE(priv, rom, operands) \
+   spifi_erase(rom, operands)
+#endif
+
+/* 512 byte sector simulation */
+
+#ifdef CONFIG_SPIFI_SECTOR512                /* Emulate a 512 byte sector */
+#  define SPIFI_512SHIFT         9           /* Sector size 1 << 9 = 512 bytes */
+#  define SPIFI_512SIZE          512         /* Sector size = 512 bytes */
+#endif
+
+#define SPIFI_ERASED_STATE       0xff        /* State of FLASH when erased */
+
+/* Cache flags */
+
+#define SST25_CACHE_VALID        (1 << 0)    /* 1=Cache has valid data */
+#define SST25_CACHE_DIRTY        (1 << 1)    /* 1=Cache is dirty */
+#define SST25_CACHE_ERASED       (1 << 2)    /* 1=Backing FLASH is erased */
+
+#define IS_VALID(p)              ((((p)->flags) & SST25_CACHE_VALID) != 0)
+#define IS_DIRTY(p)              ((((p)->flags) & SST25_CACHE_DIRTY) != 0)
+#define IS_ERASED(p)             ((((p)->flags) & SST25_CACHE_ERASED) != 0)
+
+#define SET_VALID(p)             do { (p)->flags |= SST25_CACHE_VALID; } while (0)
+#define SET_DIRTY(p)             do { (p)->flags |= SST25_CACHE_DIRTY; } while (0)
+#define SET_ERASED(p)            do { (p)->flags |= SST25_CACHE_ERASED; } while (0)
+
+#define CLR_VALID(p)             do { (p)->flags &= ~SST25_CACHE_VALID; } while (0)
+#define CLR_DIRTY(p)             do { (p)->flags &= ~SST25_CACHE_DIRTY; } while (0)
+#define CLR_ERASED(p)            do { (p)->flags &= ~SST25_CACHE_ERASED; } while (0)
+
+/* Select the divider to use as SPIFI input based on definitions in the
+ * board.h header file.
+ */
+
+#if defined(BOARD_SPIFI_PLL1)
+#  define BASE_SPIFI_CLKSEL      BASE_SPIFI_CLKSEL_PLL1
+#elif defined(BOARD_SPIFI_DIVA)
+#  define LPC43_IDIV_CTRL        LPC43_IDIVA_CTRL
+#  define IDIV_CTRL_PD           IDIVA_CTRL_PD
+#  define IDIV_CTRL_IDIV_MASK    IDIVA_CTRL_IDIV_MASK
+#  define IDIV_CTRL_IDIV         IDIVA_CTRL_IDIV(BOARD_SPIFI_DIVIDER)
+#  define IDIV_CTRL_IDIV_MAX     4
+#  define IDIV_CTRL_CLKSEL_MASK  IDIVA_CTRL_CLKSEL_MASK
+#  define IDIV_CTRL_CLKSEL_PLL1  (IDIVA_CLKSEL_PLL1 | IDIVA_CTRL_AUTOBLOCK)
+#  define BASE_SPIFI_CLKSEL      BASE_SPIFI_CLKSEL_IDIVA
+#elif defined(BOARD_SPIFI_DIVB)
+#  define LPC43_IDIV_CTRL        LPC43_IDIVB_CTRL
+#  define IDIV_CTRL_PD           IDIVBCD_CTRL_PD
+#  define IDIV_CTRL_IDIV_MASK    IDIVBCD_CTRL_IDIV_MASK
+#  define IDIV_CTRL_IDIV         IDIVBCD_CTRL_IDIV(BOARD_SPIFI_DIVIDER)
+#  define IDIV_CTRL_IDIV_MAX     16
+#  define IDIV_CTRL_CLKSEL_MASK  IDIVBCD_CTRL_CLKSEL_MASK
+#  define IDIV_CTRL_CLKSEL_PLL1  (IDIVBCD_CLKSEL_PLL1 | IDIVBCD_CTRL_AUTOBLOCK)
+#  define BASE_SPIFI_CLKSEL      BASE_SPIFI_CLKSEL_IDIVB
+#elif defined(BOARD_SPIFI_DIVC)
+#  define LPC43_IDIV_CTRL        LPC43_IDIVC_CTRL
+#  define IDIV_CTRL_PD           IDIVBCD_CTRL_PD
+#  define IDIV_CTRL_IDIV_MASK    IDIVBCD_CTRL_IDIV_MASK
+#  define IDIV_CTRL_IDIV         IDIVBCD_CTRL_IDIV(BOARD_SPIFI_DIVIDER)
+#  define IDIV_CTRL_IDIV_MAX     16
+#  define IDIV_CTRL_CLKSEL_MASK  IDIVBCD_CTRL_CLKSEL_MASK
+#  define IDIV_CTRL_CLKSEL_PLL1  (IDIVBCD_CLKSEL_PLL1 | IDIVBCD_CTRL_AUTOBLOCK)
+#  define BASE_SPIFI_CLKSEL      BASE_SPIFI_CLKSEL_IDIVC
+#elif defined(BOARD_SPIFI_DIVD)
+#  define LPC43_IDIV_CTRL        LPC43_IDIVD_CTRL
+#  define IDIV_CTRL_PD           IDIVBCD_CTRL_PD
+#  define IDIV_CTRL_IDIV_MASK    IDIVBCD_CTRL_IDIV_MASK
+#  define IDIV_CTRL_IDIV         IDIVBCD_CTRL_IDIV(BOARD_SPIFI_DIVIDER)
+#  define IDIV_CTRL_IDIV_MAX     16
+#  define IDIV_CTRL_CLKSEL_MASK  IDIVBCD_CTRL_CLKSEL_MASK
+#  define IDIV_CTRL_CLKSEL_PLL1  (IDIVBCD_CLKSEL_PLL1 | IDIVBCD_CTRL_AUTOBLOCK)
+#  define BASE_SPIFI_CLKSEL      BASE_SPIFI_CLKSEL_IDIVD
+#elif defined(BOARD_SPIFI_DIVE)
+#  define LPC43_IDIV_CTRL        LPC43_IDIVE_CTRL
+#  define IDIV_CTRL_PD           IDIVE_CTRL_PD
+#  define IDIV_CTRL_IDIV_MASK    IDIVE_CTRL_IDIV_MASK
+#  define IDIV_CTRL_IDIV         IDIVE_CTRL_IDIV(BOARD_SPIFI_DIVIDER)
+#  define IDIV_CTRL_IDIV_MAX     256
+#  define IDIV_CTRL_CLKSEL_MASK  IDIVE_CTRL_CLKSEL_MASK
+#  define IDIV_CTRL_CLKSEL_PLL1  (IDIVE_CLKSEL_PLL1 | IDIVE_CTRL_AUTOBLOCK)
+#  define BASE_SPIFI_CLKSEL      BASE_SPIFI_CLKSEL_IDIVE
+#endif
+
+#if BOARD_SPIFI_DIVIDER < 1 || BOARD_SPIFI_DIVIDER > IDIV_CTRL_IDIV_MAX
+#  error "Invalid value for  BOARD_SPIFI_DIVIDER"
+#endif
+
+/* SPIFI_CSHIGH should be one less than the minimum number of clock cycles
+ * with the CS pin high, that the SPIFI should maintain between commands.
+ * Compute this from the SPIFI clock period and the minimum high time of CS
+ * from the serial flash data sheet:
+ *
+ *   csHigh = ceiling( min CS high / SPIFI clock period ) - 1 
+ *
+ * where ceiling means round up to the next higher integer if the argument
+ * isn’t an integer.
+ */
+
+#define SPIFI_CSHIGH 9
+
+/* The final parameter of the spifi_init() ROM driver call should be the
+ * serial clock rate divided by 1000000, rounded to an integer.  The SPIFI
+ * supports transfer rates of up to SPIFI_CLK/2 bytes per second.  The SPIF_CLK
+ * is the output of the LPC43_BASE_SPIFI_CLK configured above; The frequency should
+ * be given by BOARD_SPIFI_FREQUENCY as provided by the board.h header file.
+ */
+
+#define SCLK_MHZ (BOARD_SPIFI_FREQUENCY + (1000000 / 2)) / 1000000
+
+/* DEBUG options to dump read/write buffers.  You probably do not want to
+ * enable this unless you want to dig through a *lot* of debug output!
+ */
+
+#if !defined(CONFIG_DEBUG) || !defined(CONFIG_DEBUG_VERBOSE) || !defined(CONFIG_DEBUG_FS)
+#  undef CONFIG_DEBUG_SPIFI_DUMP
+#endif
+
+#ifdef CONFIG_DEBUG_SPIFI_DUMP
+#  define lpc43_dumpbuffer(m,b,n) lib_dumpbuffer(m,b,n);
+#else
+#  define lpc43_dumpbuffer(m,b,n)
+#endif
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/* This type represents the state of the MTD device.  The struct mtd_dev_s must
+ * appear at the beginning of the definition so that you can freely cast between
+ * pointers to struct mtd_dev_s and struct lpc43_dev_s.
+ */
+
+struct lpc43_dev_s
+{
+  struct mtd_dev_s mtd;             /* MTD interface */
+#ifndef CONFIG_SPIFI_LIBRARY
+  FAR struct spifi_driver_s *spifi; /* Pointer to ROM driver table */
+#endif
+  FAR struct spifi_dev_s rom;       /* Needed for communication with ROM driver */
+  struct spifi_operands_s operands; /* Needed for program and erase ROM calls */
+  uint16_t nblocks;                 /* Number of blocks of size blksize */
+#ifndef CONFIG_SPIFI_BLKSIZE
+  uint8_t blkshift;                 /* Log2 of erase block size */
+  uint32_t blksize;                 /* Size of one erase block (up to 256K) */
+#endif
+
+#if defined(CONFIG_SPIFI_SECTOR512) && !defined(CONFIG_SPIFI_READONLY)
+  uint8_t flags;                    /* Buffered sector flags */
+  uint16_t blkno;                   /* Erase block number in the cache */
+  FAR uint8_t *cache;               /* Allocated sector data */
+#endif
+};
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/* Helpers */
+
+static void lpc43_blockerase(FAR struct lpc43_dev_s *priv, off_t offset);
+static inline int lpc43_chiperase(FAR struct lpc43_dev_s *priv);
+static inline void lpc43_pageread(FAR struct lpc43_dev_s *priv,
+                                  FAR uint8_t *dest, FAR const uint8_t *src,
+                                  size_t nbytes);
+#ifndef CONFIG_SPIFI_READONLY
+#ifdef CONFIG_SPIFI_VERIFY
+static int lpc43_verify(FAR struct lpc43_dev_s *priv, FAR uint8_t *dest,
+                        FAR const uint8_t *src, size_t nbytes);
+#endif
+static int lpc43_pagewrite(FAR struct lpc43_dev_s *priv, FAR uint8_t *dest,
+                           FAR const uint8_t *src, size_t nbytes);
+#ifdef CONFIG_SPIFI_SECTOR512
+static void lpc43_cacheflush(struct lpc43_dev_s *priv);
+static FAR uint8_t *lpc43_cacheread(struct lpc43_dev_s *priv, off_t sector);
+static void lpc43_cacheerase(struct lpc43_dev_s *priv, off_t sector);
+static void lpc43_cachewrite(FAR struct lpc43_dev_s *priv, FAR const uint8_t *buffer,
+                             off_t sector, size_t nsectors);
+#endif
+#endif
+
+/* MTD driver methods */
+
+static int lpc43_erase(FAR struct mtd_dev_s *dev, off_t startblock, size_t nblocks);
+static ssize_t lpc43_bread(FAR struct mtd_dev_s *dev, off_t startblock,
+                           size_t nblocks, FAR uint8_t *buf);
+static ssize_t lpc43_bwrite(FAR struct mtd_dev_s *dev, off_t startblock,
+                            size_t nblocks, FAR const uint8_t *buf);
+static ssize_t lpc43_read(FAR struct mtd_dev_s *dev, off_t offset, size_t nbytes,
+                          FAR uint8_t *buffer);
+static int lpc43_ioctl(FAR struct mtd_dev_s *dev, int cmd, unsigned long arg);
+
+/* Initialization */
+
+#ifndef BOARD_SPIFI_PLL1
+static inline void lpc43_idiv_clkconfig(void);
+#endif
+
+static inline void lpc43_spifi_clkconfig(void);
+static inline void lpc43_spifi_pinconfig(void);
+static inline int lpc43_rominit(FAR struct lpc43_dev_s *priv);
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/* Only a single SPIFI driver instance is supported */
+
+static struct lpc43_dev_s g_spifi;
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name:  lpc43_blockerase
+ ****************************************************************************/
+
+static void lpc43_blockerase(struct lpc43_dev_s *priv, off_t sector)
+{
+  int result;
+
+  /* Erase one block on the chip:
+   *
+   * dest   - Specifies the first address to be programmed or erased, either in
+   *          the SPIFI memory area or as a zero-based device address.  It must
+   *          be at an offset that is an exact multiple of the erase block size.
+   * length - The number of bytes to be programmed or erased
+   */
+
+  priv->operands.dest   = SPIFI_BASE + (sector << SPIFI_BLKSHIFT);
+  priv->operands.length = SPIFI_BLKSIZE;
+
+  fvdbg("SPIFI_ERASE: dest=%p length=%d\n", 
+        priv->operands.dest, priv->operands.length);
+
+  result = SPIFI_ERASE(priv, &priv->rom, &priv->operands);
+  if (result != 0)
+    {
+      fdbg("ERROR: SPIFI_ERASE failed: %05x\n", result);
+    }
+}
+
+/****************************************************************************
+ * Name:  lpc43_chiperase
+ ****************************************************************************/
+
+static inline int lpc43_chiperase(struct lpc43_dev_s *priv)
+{
+  int result;
+
+  /* Erase the entire chip:
+   *
+   * dest   - Specifies the first address to be programmed or erased, either in
+   *          the SPIFI memory area or as a zero-based device address.  It must
+   *          be at an offset that is an exact multiple of the erase block size.
+   * length - The number of bytes to be programmed or erased
+   */
+
+  priv->operands.dest   = SPIFI_BASE;
+  priv->operands.length = SPIFI_BLKSIZE * priv->nblocks;
+
+  fvdbg("SPIFI_ERASE: dest=%p length=%d\n",
+        priv->operands.dest, priv->operands.length);
+
+  result = SPIFI_ERASE(priv, &priv->rom, &priv->operands);
+  if (result != 0)
+    {
+      fdbg("ERROR: SPIFI_ERASE failed: %05x\n", result);
+      return -EIO;
+    }
+
+  return OK;
+}
+
+/****************************************************************************
+ * Name: lpc43_pagewrite
+ ****************************************************************************/
+
+#if !defined(CONFIG_SPIFI_READONLY) && defined(CONFIG_SPIFI_VERIFY)
+static int lpc43_verify(FAR struct lpc43_dev_s *priv, FAR uint8_t *dest,
+                        FAR const uint8_t *src, size_t nbytes)
+{
+  return memcmp(src, dest, nbytes) != 0 ? -EIO : OK;
+}
+#endif
+
+/****************************************************************************
+ * Name: lpc43_pagewrite
+ ****************************************************************************/
+
+#ifndef CONFIG_SPIFI_READONLY
+static int lpc43_pagewrite(FAR struct lpc43_dev_s *priv, FAR uint8_t *dest,
+                           FAR const uint8_t *src, size_t nbytes)
+{
+  int result;
+
+  /* Write FLASH pages:
+   *
+   * dest   - Specifies the first address to be programmed or erased, either in
+   *          the SPIFI memory area or as a zero-based device address.  It must
+   *          be at an offset that is an exact multiple of the erase block size.
+   * length - The number of bytes to be programmed or erased
+   */
+
+  priv->operands.dest   = dest;
+  priv->operands.length = nbytes;
+
+  fvdbg("SPIFI_PROGRAM: src=%p dest=%p length=%d\n", 
+        src, priv->operands.dest, priv->operands.length);
+
+  result = SPIFI_PROGRAM(priv, &priv->rom, src, &priv->operands);
+  if (result != 0)
+    {
+      fdbg("ERROR: SPIFI_PROGRAM failed: %05x\n", result);
+      return -EIO;
+    }
+
+  /* Verify the data that was written by comparing to the data visible in the
+   * SPIFI address space.
+   */
+
+#ifdef CONFIG_SPIFI_VERIFY
+  result = lpc43_verify(priv, dest, src, nbytes);
+  if (result != 0)
+    {
+      fdbg("ERROR: lpc43_verify failed: %05x\n", result);
+      return -EIO;
+    }
+#endif
+
+  return OK;
+}
+#endif
+
+/****************************************************************************
+ * Name: lpc43_pageread
+ ****************************************************************************/
+
+static inline void lpc43_pageread(FAR struct lpc43_dev_s *priv,
+                                  FAR uint8_t *dest, FAR const uint8_t *src,
+                                  size_t nbytes)
+{
+  fvdbg("src=%p dest=%p length=%d\n", src, dest, nbytes);
+  memcpy(dest, src, nbytes);
+}
+
+/****************************************************************************
+ * Name: lpc43_cacheflush
+ ****************************************************************************/
+
+#if defined(CONFIG_SPIFI_SECTOR512) && !defined(CONFIG_SPIFI_READONLY)
+static void lpc43_cacheflush(struct lpc43_dev_s *priv)
+{
+  FAR uint8_t *dest;
+  int ret;
+
+  /* If the cached is dirty (meaning that it no longer matches the old FLASH contents)
+   * or was erased (with the cache containing the correct FLASH contents), then write
+   * the cached erase block to FLASH.
+   */
+
+  fvdbg("flags: %02x blkno: %d\n", priv->flags, priv->blkno);
+  if (IS_DIRTY(priv) || IS_ERASED(priv))
+    {
+      /* Get the SPIFI address corresponding to the cached erase block */
+
+      dest = SPIFI_BASE + ((off_t)priv->blkno << SPIFI_BLKSHIFT);
+
+      /* Write entire erase block to FLASH */
+
+      ret = lpc43_pagewrite(priv, dest, priv->cache, SPIFI_BLKSIZE);
+      if (ret < 0)
+        {
+          fdbg("ERROR: lpc43_pagewrite failed: %d\n", ret);
+        }
+
+      /* The case is no long dirty and the FLASH is no longer erased */
+
+      CLR_DIRTY(priv);
+      CLR_ERASED(priv);
+    }
+}
+#endif
+
+/****************************************************************************
+ * Name: lpc43_cacheread
+ ****************************************************************************/
+
+#if defined(CONFIG_SPIFI_SECTOR512) && !defined(CONFIG_SPIFI_READONLY)
+static FAR uint8_t *lpc43_cacheread(struct lpc43_dev_s *priv, off_t sector)
+{
+  FAR const uint8_t *src;
+  off_t blkno;
+  int   index;
+ 
+  /* Convert from the 512 byte sector to the erase sector size of the device.  For
+   * exmample, if the actual erase sector size if 4Kb (1 << 12), then we first
+   * shift to the right by 3 to get the sector number in 4096 increments.
+   */
+
+  blkno = sector >> (SPIFI_BLKSHIFT - SPIFI_512SHIFT);
+  fvdbg("sector: %ld blkno: %d\n", sector, blkno);
+
+  /* Check if the requested erase block is already in the cache */
+
+  if (!IS_VALID(priv) || blkno != (off_t)priv->blkno)
+    {
+      /* No.. Flush any dirty erase block currently in the cache */
+
+      lpc43_cacheflush(priv);
+
+      /* Read the new erase block into the cache */
+      /* Get the SPIFI address corresponding to the new erase block */
+
+      src = SPIFI_BASE + (blkno << SPIFI_BLKSHIFT);
+
+      /* Read the entire erase block from FLASH */
+
+      lpc43_pageread(priv, priv->cache, src, SPIFI_BLKSIZE);
+
+      /* Mark the sector as cached */
+
+      priv->blkno = (uint16_t)blkno;
+
+      SET_VALID(priv);          /* The data in the cache is valid */
+      CLR_DIRTY(priv);          /* It should match the FLASH contents */
+      CLR_ERASED(priv);         /* The underlying FLASH has not been erased */
+    }
+
+  /* Get the index to the 512 sector in the erase block that holds the argument */
+
+  index = sector & ((1 << (SPIFI_BLKSHIFT - SPIFI_512SHIFT)) - 1);
+
+  /* Return the address in the cache that holds this sector */
+
+  return &priv->cache[index << SPIFI_512SHIFT];
+}
+#endif
+
+/****************************************************************************
+ * Name: lpc43_cacheerase
+ ****************************************************************************/
+
+#if defined(CONFIG_SPIFI_SECTOR512) && !defined(CONFIG_SPIFI_READONLY)
+static void lpc43_cacheerase(struct lpc43_dev_s *priv, off_t sector)
+{
+  FAR uint8_t *dest;
+
+  /* First, make sure that the erase block containing the 512 byte sector is in
+   * the cache.
+   */
+
+  dest = lpc43_cacheread(priv, sector);
+
+  /* Erase the block containing this sector if it is not already erased.
+   * The erased indicated will be cleared when the data from the erase sector
+   * is read into the cache and set here when we erase the block.
+   */
+
+  if (!IS_ERASED(priv))
+    {
+      off_t blkno  = sector >> (SPIFI_BLKSHIFT - SPIFI_512SHIFT);
+      fvdbg("sector: %ld blkno: %d\n", sector, blkno);
+
+      lpc43_blockerase(priv, blkno);
+      SET_ERASED(priv);
+    }
+
+  /* Put the cached sector data into the erase state and mart the cache as dirty
+   * (but don't update the FLASH yet.  The caller will do that at a more optimal
+   * time).
+   */
+
+  memset(dest, SPIFI_ERASED_STATE, SPIFI_512SIZE);
+  SET_DIRTY(priv);
+}
+#endif
+
+/****************************************************************************
+ * Name: lpc43_cachewrite
+ ****************************************************************************/
+
+#if defined(CONFIG_SPIFI_SECTOR512) && !defined(CONFIG_SPIFI_READONLY)
+static void lpc43_cachewrite(FAR struct lpc43_dev_s *priv, FAR const uint8_t *buffer,
+                            off_t sector, size_t nsectors)
+{
+  FAR uint8_t *dest;
+
+  for (; nsectors > 0; nsectors--)
+    {
+      /* First, make sure that the erase block containing 512 byte sector is in
+       * memory.
+       */
+
+      dest = lpc43_cacheread(priv, sector);
+
+      fvdbg("dest=%p src=%p sector: %ld flags: %02x\n",
+            dest, buffer, sector, priv->flags);
+
+      /* Erase the block containing this sector if it is not already erased.
+       * The erased indicated will be cleared when the data from the erase sector
+       * is read into the cache and set here when we erase the sector.
+       */
+
+      if (!IS_ERASED(priv))
+        {
+          off_t blkno  = sector >> (SPIFI_BLKSHIFT - SPIFI_512SHIFT);
+          fvdbg("sector: %ld blkno: %d\n", sector, blkno);
+
+          lpc43_blockerase(priv, blkno);
+          SET_ERASED(priv);
+        }
+
+      /* Copy the new sector data into cached erase block */
+
+      memcpy(dest, buffer, SPIFI_512SIZE);
+      SET_DIRTY(priv);
+
+      /* Set up for the next 512 byte sector */
+
+      buffer += SPIFI_512SIZE;
+      sector++;
+    }
+
+  /* Flush the last erase block left in the cache */
+
+  lpc43_cacheflush(priv);
+}
+#endif
+
+/****************************************************************************
+ * Name: lpc43_erase
+ ****************************************************************************/
+
+static int lpc43_erase(FAR struct mtd_dev_s *dev, off_t startblock, size_t nblocks)
+{
+#ifdef CONFIG_SPIFI_READONLY
+  return -EACESS
+#else
+  FAR struct lpc43_dev_s *priv = (FAR struct lpc43_dev_s *)dev;
+  size_t blocksleft = nblocks;
+
+  fvdbg("startblock: %08lx nblocks: %d\n", (long)startblock, (int)nblocks);
+
+  while (blocksleft-- > 0)
+    {
+      /* Erase each sector */
+
+#ifdef CONFIG_SPIFI_SECTOR512
+      lpc43_cacheerase(priv, startblock);
+#else
+      lpc43_blockerase(priv, startblock);
+#endif
+      startblock++;
+    }
+
+#ifdef CONFIG_SPIFI_SECTOR512
+  /* Flush the last erase block left in the cache */
+
+  lpc43_cacheflush(priv);
+#endif
+
+  return (int)nblocks;
+#endif
+}
+
+/****************************************************************************
+ * Name: lpc43_bread
+ ****************************************************************************/
+
+static ssize_t lpc43_bread(FAR struct mtd_dev_s *dev, off_t startblock, size_t nblocks,
+                           FAR uint8_t *buffer)
+{
+#ifdef CONFIG_SPIFI_SECTOR512
+  ssize_t nbytes;
+
+  fvdbg("startblock: %08lx nblocks: %d\n", (long)startblock, (int)nblocks);
+
+  /* On this device, we can handle the block read just like the byte-oriented read */
+
+  nbytes = lpc43_read(dev, startblock << SPIFI_512SHIFT,
+                      nblocks << SPIFI_512SHIFT, buffer);
+  if (nbytes > 0)
+    {
+      lpc43_dumpbuffer(__func__, buffer, nbytes)
+      return nbytes >> SPIFI_512SHIFT;
+    }
+
+  return (int)nbytes;
+#else
+  FAR struct lpc43_dev_s *priv = (FAR struct lpc43_dev_s *)dev;
+  ssize_t nbytes;
+
+  fvdbg("startblock: %08lx nblocks: %d\n", (long)startblock, (int)nblocks);
+
+  /* On this device, we can handle the block read just like the byte-oriented read */
+
+  nbytes = lpc43_read(dev, startblock << SPIFI_BLKSHIFT,
+                      nblocks << SPIFI_BLKSHIFT, buffer);
+  if (nbytes > 0)
+    {
+      lpc43_dumpbuffer(__func__, buffer, nbytes)
+      return nbytes >> SPIFI_BLKSHIFT;
+    }
+
+  return (int)nbytes;
+#endif
+}
+
+/****************************************************************************
+ * Name: lpc43_bwrite
+ ****************************************************************************/
+
+static ssize_t lpc43_bwrite(FAR struct mtd_dev_s *dev, off_t startblock, size_t nblocks,
+                            FAR const uint8_t *buffer)
+{
+#if defined(CONFIG_SPIFI_READONLY)
+
+  return -EACCESS;
+
+#elif defined(CONFIG_SPIFI_SECTOR512)
+
+  FAR struct lpc43_dev_s *priv = (FAR struct lpc43_dev_s *)dev;
+
+  fvdbg("startblock: %08lx nblocks: %d\n", (long)startblock, (int)nblocks);
+
+  lpc43_cachewrite(priv, buffer, startblock, nblocks);
+
+  lpc43_dumpbuffer(__func__, buffer, nblocks << SPIFI_512SHIFT)
+  return nblocks;
+
+#else
+
+  FAR struct lpc43_dev_s *priv = (FAR struct lpc43_dev_s *)dev;
+  FAR uint8_t *dest;
+
+  fvdbg("startblock: %08lx nblocks: %d\n", (long)startblock, (int)nblocks);
+
+  /* Get the SPIFI address corresponding to the erase block */
+
+  dest = SPIFI_BASE + (startblock << SPIFI_BLKSHIFT);
+
+  /* Write all of the erase blocks to FLASH */
+
+  ret = lpc43_pagewrite(priv, dest, buffer, nblocks << SPIFI_512SHIFT);
+  if (ret < 0)
+    {
+      fdbg("ERROR: lpc43_pagewrite failed: %d\n", ret);
+      return ret;
+    }
+
+  lpc43_dumpbuffer(__func__, buffer, nblocks << SPIFI_BLKSHIFT)
+  return nblocks;
+
+#endif
+}
+
+/****************************************************************************
+ * Name: lpc43_read
+ ****************************************************************************/
+
+static ssize_t lpc43_read(FAR struct mtd_dev_s *dev, off_t offset, size_t nbytes,
+                          FAR uint8_t *buffer)
+{
+  FAR struct lpc43_dev_s *priv = (FAR struct lpc43_dev_s *)dev;
+  FAR const uint8_t *src;
+
+  fvdbg("offset: %08lx nbytes: %d\n", (long)offset, (int)nbytes);
+
+  /* Get the SPIFI address corresponding sector */
+
+  src = SPIFI_BASE + offset;
+
+  /* Read FLASH contents into  the user buffer */
+
+  lpc43_pageread(priv, buffer, src, nbytes);
+
+  fvdbg("return nbytes: %d\n", (int)nbytes);
+  return nbytes;
+}
+
+/****************************************************************************
+ * Name: lpc43_ioctl
+ ****************************************************************************/
+
+static int lpc43_ioctl(FAR struct mtd_dev_s *dev, int cmd, unsigned long arg)
+{
+  FAR struct lpc43_dev_s *priv = (FAR struct lpc43_dev_s *)dev;
+  int ret = -EINVAL; /* Assume good command with bad parameters */
+
+  fvdbg("cmd: %d \n", cmd);
+
+  switch (cmd)
+    {
+      case MTDIOC_GEOMETRY:
+        {
+          FAR struct mtd_geometry_s *geo = (FAR struct mtd_geometry_s *)((uintptr_t)arg);
+          if (geo)
+            {
+              /* Populate the geometry structure with information need to know
+               * the capacity and how to access the device.
+               *
+               * NOTE: that the device is treated as though it where just an array
+               * of fixed size blocks.  That is most likely not true, but the client
+               * will expect the device logic to do whatever is necessary to make it
+               * appear so.
+               */
+
+#ifdef CONFIG_SPIFI_SECTOR512
+              geo->blocksize    = 512;
+              geo->erasesize    = 512;
+              geo->neraseblocks = priv->nblocks << (SPIFI_BLKSHIFT - SPIFI_512SHIFT);
+#else
+              geo->blocksize    = SPIFI_BLKSIZE;
+              geo->erasesize    = SPIFI_BLKSIZE;
+              geo->neraseblocks = priv->nblocks;
+#endif
+              ret               = OK;
+
+              fvdbg("blocksize: %d erasesize: %d neraseblocks: %d\n",
+                    geo->blocksize, geo->erasesize, geo->neraseblocks);
+            }
+        }
+        break;
+
+      case MTDIOC_BULKERASE:
+        {
+            /* Erase the entire device */
+
+            ret = lpc43_chiperase(priv);
+        }
+        break;
+ 
+      case MTDIOC_XIPBASE:
+      default:
+        ret = -ENOTTY; /* Bad command */
+        break;
+    }
+
+  fvdbg("return %d\n", ret);
+  return ret;
+}
+
+/****************************************************************************
+ * Name: lpc43_idiv_clkconfig
+ *
+ * Description:
+ *   Configure PLL1 as the input to the selected divider and enable the
+ *   divider.
+ *
+ ****************************************************************************/
+
+#ifndef BOARD_SPIFI_PLL1
+static inline void lpc43_idiv_clkconfig(void)
+{
+  uint32_t regval;
+
+  /* Configure PLL1 as the input to the selected divider */
+
+  regval  = getreg32(LPC43_IDIV_CTRL);
+  regval &= ~IDIV_CTRL_CLKSEL_MASK;
+  regval |= IDIV_CTRL_CLKSEL_PLL1;
+  putreg32(regval, LPC43_IDIV_CTRL);
+
+  /* Enable the divider (by making sure that the power down bit is clear) */
+
+  regval &= ~IDIV_CTRL_PD;
+  putreg32(regval, LPC43_IDIV_CTRL);
+
+  /* Set the divider value */
+
+  regval &= ~IDIVA_CTRL_IDIV_MASK;
+  regval |= IDIV_CTRL_IDIV;
+  putreg32(regval, LPC43_IDIV_CTRL);
+}
+#else
+#  define lpc43_idiv_clkconfig()
+#endif
+
+/****************************************************************************
+ * Name: lpc43_spifi_clkconfig
+ *
+ * Description:
+ *   Configure the selected divider (or PLL1) as the input to the SPIFI
+ *   and enable the SPIFI clock.
+ *
+ ****************************************************************************/
+
+static inline void lpc43_spifi_clkconfig(void)
+{
+  uint32_t regval;
+
+  /* Configure the selected divider (or PLL1) as the input to the SPIFI */
+
+  regval  = getreg32(LPC43_BASE_SPIFI_CLK);
+  regval &= ~BASE_SPIFI_CLK_CLKSEL_MASK;
+  regval |= BASE_SPIFI_CLKSEL;
+  putreg32(regval, LPC43_BASE_SPIFI_CLK);
+
+  /* Enable the SPIFI clocking (by making sure that the power down bit is
+   * clear)
+   */
+
+  regval &= ~IDIVA_CTRL_PD;
+  putreg32(regval, LPC43_BASE_SPIFI_CLK);
+}
+
+/****************************************************************************
+ * Name: lpc43_spifi_pinconfig
+ *
+ * Description:
+ *   Configure SPIFI pins
+ *
+ ****************************************************************************/
+
+static inline void lpc43_spifi_pinconfig(void)
+{
+  /* Configure SPIFI pins */
+
+  lpc43_pin_config(PINCONF_SPIFI_CS);   /* Input buffering not needed */
+  lpc43_pin_config(PINCONF_SPIFI_MISO); /* High drive for SCLK */
+  lpc43_pin_config(PINCONF_SPIFI_MOSI);
+  lpc43_pin_config(PINCONF_SPIFI_SCK);
+  lpc43_pin_config(PINCONF_SPIFI_SIO2);
+  lpc43_pin_config(PINCONF_SPIFI_SIO3);
+}
+
+/****************************************************************************
+ * Name: lpc43_rominit
+ *
+ * Description:
+ *   Initialize the SPIFI ROM driver
+ *
+ ****************************************************************************/
+
+static inline int lpc43_rominit(FAR struct lpc43_dev_s *priv)
+{
+#ifndef CONFIG_SPIFI_BLKSIZE
+  FAR struct spfi_desc_s *desc;
+  uint16_t sectors;
+  uint8_t log2;
+#endif
+  int32_t result;
+
+  /* Get the pointer to the SPIFI ROM driver table. */
+
+#ifndef CONFIG_SPIFI_LIBRARY
+  priv->spifi = *((struct spifi_driver_s **)SPIFI_ROM_PTR);
+#endif
+
+  /* The final parameter of the spifi_init() ROM driver call should be the
+   * serial clock rate divided by 1000000, rounded to an integer.  The SPIFI
+   * supports transfer rates of up to SPIFI_CLK/2 bytes per second.  The SPIF_CLK
+   * is the output of the LPC43_BASE_SPIFI_CLK configured above; The frequency should
+   * be given by BOARD_SPIFI_FREQUENCY as provided by the board.h header file.
+   *
+   * A return value of zero frp spifi_init() indicates success.  Non-zero error
+   * codes include:
+   *
+   *   0x2000A  No operative serial flash (JEDEC ID all zeroes or all ones)
+   *   0x20009  Unknown manufacturer code
+   *   0x20008  Unknown device type code
+   *   0x20007  Unknown device ID code
+   *   0x20006  Unknown extended device ID value (only for Spansion 25FL12x
+   *            in the initial API)
+   *   0x20005  Device status error
+   *   0x20004  Operand error: S_MODE3+S_FULLCLK+S_RCVCLK in options
+   */
+
+  result = SPIFI_INIT(priv, &priv->rom, SPIFI_CSHIGH,
+                      S_RCVCLK | S_FULLCLK, SCLK_MHZ);
+  if (result != 0)
+    {
+      fdbg("ERROR: SPIFI_INIT failed: %05x\n", result);
+
+      /* Try again */
+
+      result = SPIFI_INIT(priv, &priv->rom, SPIFI_CSHIGH,
+                          S_RCVCLK | S_FULLCLK, SCLK_MHZ);
+      if (result != 0)
+        {
+          fdbg("ERROR: SPIFI_INIT failed: %05x\n", result);
+          return -ENODEV;
+        }
+    }
+
+  fvdbg("SPFI:\n");
+  fvdbg("      base: %08x\n", priv->rom.base);
+  fvdbg("   regbase: %08x\n", priv->rom.regbase);
+  fvdbg("   devsize: %08x\n", priv->rom.devsize);
+  fvdbg("   memsize: %08x\n", priv->rom.memsize);
+  fvdbg("     mfger: %02x\n", priv->rom.mfger);
+  fvdbg("   devtype: %02x\n", priv->rom.devtype);
+  fvdbg("     devid: %02x\n", priv->rom.devid);
+  fvdbg("      busy: %02x\n", priv->rom.busy);
+  fvdbg("      stat: %04x\n", priv->rom.stat.h);
+  fvdbg("   setprot: %04x\n", priv->rom.setprot);
+  fvdbg(" writeprot: %04x\n", priv->rom.writeprot);
+  fvdbg("    memcmd: %08x\n", priv->rom.memcmd);
+  fvdbg("   progcmd: %08x\n", priv->rom.progcmd);
+  fvdbg("   sectors: %04x\n", priv->rom.sectors);
+  fvdbg(" protbytes: %04x\n", priv->rom.protbytes);
+  fvdbg("      opts: %08x\n", priv->rom.opts);
+  fvdbg("  errcheck: %08x\n", priv->rom.errcheck);
+
+  /* Get the largest erase block size */
+
+#ifndef CONFIG_SPIFI_BLKSIZE
+
+  desc    = priv->rom.protents;
+  sectors = priv->rom.sectors;
+  log2    = 0;
+
+  fvdbg("FLASH Geometry:\n");
+
+  while (sectors > 0)
+    {
+      fvdbg("  log2: %d rept: %d\n", desc->log2, desc->rept);
+
+      /* Check if this is the largest erase block size seen */
+
+      if (desc->log2 > log2)
+        {
+          log2 = desc->log2;
+        }
+
+      /* Decrement the count of sectors we have checked */
+
+      sectors -= desc->rept;
+    }
+
+  DEBUGASSERT(log2 > 0);
+
+  /* Save the digested FLASH geometry info */
+
+  priv->blkshift = log2;
+  priv->blksize  = (1 << log2);
+  priv->nblocks  = (priv->rom.memsize - CONFIG_SPIFI_OFFSET) / priv->blksize;
+
+  fvdbg("Driver FLASH Geometry:\n");
+  fvdbg("  blkshift: %d\n", priv->blkshift);
+  fvdbg("   blksize: %08x\n", priv->blksize);
+  fvdbg("   nblocks: %d\n", priv->nblocks);
+
+#if CONFIG_SPIFI_SECTOR512
+  DEBUGASSERT(log2 > 9);
+#endif
+
+#else
+
+  /* Save the digested FLASH geometry info */
+
+  priv->nblocks  = ((priv->rom.memsize  - CONFIG_SPIFI_OFFSET) >> SPIFI_BLKSHIFT);
+
+  fvdbg("Driver FLASH Geometry:\n");
+  fvdbg("  blkshift: %d\n", SPIFI_BLKSHIFT);
+  fvdbg("   blksize: %08x\n", SPIFI_BLKSIZE);
+  fvdbg("   nblocks: %d\n", priv->nblocks);
+#endif
+
+  return OK;
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: lpc43_spifi_initialize
+ *
+ * Description:
+ *   Create an initialized MTD device instance for the SPIFI device.  MTD
+ *   devices are not registered in the file system, but are created as
+ *   instances that can be bound to other functions (such as a block or
+ *   character driver front end).
+ *
+ *   SPIFI interface clocking is configured per settings in the board.h file.
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned value:
+ *   One success, a reference to the initialized MTD device instance is
+ *   returned;  NULL is returned on any failure.
+ *
+ ****************************************************************************/
+
+FAR struct mtd_dev_s *lpc43_spifi_initialize(void)
+{
+  /* At present, only a single instance of the SPIFI driver is supported */
+
+  FAR struct lpc43_dev_s *priv = &g_spifi;
+  irqstate_t flags;
+  int ret;
+
+  /* Initialize the SPIFI driver structure.  Since the driver instance lies
+   * in .bss, it should have been already cleared to zero.
+   */
+
+  priv->mtd.erase  = lpc43_erase;
+  priv->mtd.bread  = lpc43_bread;
+  priv->mtd.bwrite = lpc43_bwrite;
+  priv->mtd.read   = lpc43_read;
+  priv->mtd.ioctl  = lpc43_ioctl;
+
+  priv->operands.protect = -1;              /* Save and restore protection */
+  priv->operands.options = S_CALLER_ERASE;  /* This driver will do erasure */
+  
+  /* Initialize the SPIFI.  Interrupts must be disabled here because shared
+   * CGU registers will be modified.
+   */
+
+  flags = irqsave();
+
+  /* The SPIFI will receive clocking from a divider per the settings
+   * provided in the board.h file.  Configure PLL1 as the input clock
+   * for the selected divider
+   */
+
+  lpc43_idiv_clkconfig();
+
+  /* Configure SPIFI to received clocking from the selected divider */
+
+  lpc43_spifi_clkconfig();
+
+  /* Configure SPIFI pins */
+
+  lpc43_spifi_pinconfig();
+  irqrestore(flags);
+
+  /* Initialize the SPIFI ROM driver */
+
+  ret = lpc43_rominit(priv);
+   if (ret != OK)
+     {
+       return NULL;
+     }
+
+  /* Check if we need to emulator a 512 byte sector */
+
+#ifdef CONFIG_SPIFI_SECTOR512
+
+  /* Allocate a buffer for the erase block cache */
+
+  priv->cache = (FAR uint8_t *)kmalloc(SPIFI_BLKSIZE);
+  if (!priv->cache)
+    {
+      /* Allocation failed! Discard all of that work we just did and return NULL */
+
+      fdbg("ERROR: Allocation failed\n");
+      return NULL;
+    }
+#endif
+
+  /* Return the implementation-specific state structure as the MTD device */
+
+  fvdbg("Return %p\n", priv);
+  return (FAR struct mtd_dev_s *)priv;
+}
+
+/****************************************************************************
+ * Name: pullMISO
+ *
+ * Description:
+ *   hardware-control routine used by spifi_rom_api.c
+ *
+ * Input Parameters:
+ *   high
+ *
+ * Returned value:
+ *   None.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SPIFI_LIBRARY
+void pullMISO(int high)
+{
+  uint32_t pinconfig;
+
+  /* Control MISO pull-up/down state  Assume pull down by clearing:
+   *
+   *  EPD = Enable pull-down connect (bit 
+   */
+
+  pinconfig = PINCONF_SPIFI_MISO & ~(PINCONF_PULLUP | PINCONF_PULLDOWN);
+  switch (high)
+    {
+      case 0:
+        {
+          /* Pull down */
+
+          pinconfig |= PINCONF_PULLDOWN;
+        }
+        break;
+
+      case 1:
+        {
+          /* Pull up */
+
+          pinconfig |= PINCONF_PULLUP;
+        }
+        break;
+
+      default:
+        {
+          /* Neither */
+        }
+        break;
+    }
+
+  /* Reconfigure MISO */
+
+  lpc43_pin_config(pinconfig);
+}
+#endif
+
+#endif /* CONFIG_LPC43_SPIFI */
diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_spifi.h b/nuttx/arch/arm/src/lpc43xx/lpc43_spifi.h
new file mode 100644
index 000000000..f7cc0d775
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/lpc43_spifi.h
@@ -0,0 +1,136 @@
+/****************************************************************************
+ *  arch/arm/src/lpc43/lpc43_spifi.h
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LPC43XX_LPC43_SPIFI_H
+#define __ARCH_ARM_SRC_LPC43XX_LPC43_SPIFI_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/mtd.h>
+
+#include "chip.h"
+#include "chip/lpc43_spifi.h"
+
+#ifdef CONFIG_LPC43_SPIFI
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+/* SPIFI Configuration ******************************************************/
+/* This logic supports some special options that can be used to create an
+ * MTD device on the SPIFI FLASH.
+ *
+ *    CONFIG_LPC43_SPIFI - Enable SPIFI support
+ *
+ * SPIFI device geometry:
+ *
+ *   CONFIG_SPIFI_OFFSET - Offset the beginning of the block driver this many
+ *     bytes into the device address space.  This offset must be an exact
+ *     multiple of the erase block size (CONFIG_SPIFI_BLKSIZE). Default 0.
+ *   CONFIG_SPIFI_BLKSIZE - The size of one device erase block.  If not defined
+ *     then the driver will try to determine the correct erase block size by
+ *     examining that data returned from spifi_initialize (which sometimes
+ *     seems bad).
+ *
+ * Other SPIFI options
+ *
+ *   CONFIG_SPIFI_LIBRARY - Don't use the LPC43xx ROM routines but, instead,
+ *     use an external library implementation of the SPIFI interface.
+ *   CONFIG_SPIFI_SECTOR512 - If defined, then the driver will report a more
+ *     FAT friendly 512 byte sector size and will manage the read-modify-write
+ *     operations on the larger erase block.
+ *   CONFIG_SPIFI_READONLY - Define to support only read-only operations.
+ */
+
+#ifndef CONFIG_SPIFI_OFFSET
+#  define CONFIG_SPIFI_OFFSET 0
+#endif
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C" {
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Name: lpc43_spifi_initialize
+ *
+ * Description:
+ *   Create an initialized MTD device instance for the SPIFI device.  MTD
+ *   devices are not registered in the file system, but are created as
+ *   instances that can be bound to other functions (such as a block or
+ *   character driver front end).
+ *
+ *   SPIFI interface clocking is configured per settings in the board.h file.
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned value:
+ *   One success, a reference to the initialized MTD device instance is
+ *   returned;  NULL is returned on any failure.
+ *
+ ****************************************************************************/
+
+FAR struct mtd_dev_s *lpc43_spifi_initialize(void);
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* CONFIG_LPC43_SPIFI */
+#endif /* __ARCH_ARM_SRC_LPC43XX_LPC43_SPIFI_H */
+
diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_ssp.c b/nuttx/arch/arm/src/lpc43xx/lpc43_ssp.c
new file mode 100644
index 000000000..4a749825a
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/lpc43_ssp.c
@@ -0,0 +1,930 @@
+/****************************************************************************
+ * arch/arm/src/lpc43xx/lpc43_ssp.c
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <semaphore.h>
+#include <errno.h>
+#include <debug.h>
+
+#include <arch/board/board.h>
+#include <nuttx/arch.h>
+#include <nuttx/spi.h>
+
+#include "up_internal.h"
+#include "up_arch.h"
+
+#include "chip.h"
+
+#include "lpc43_syscon.h"
+#include "lpc43_pinconn.h"
+#include "lpc43_ssp.h"
+
+#if defined(CONFIG_LPC43_SSP0) || defined(CONFIG_LPC43_SSP1)
+
+/****************************************************************************
+ * Definitions
+ ****************************************************************************/
+
+/* The following enable debug output from this file (needs CONFIG_DEBUG too).
+ * 
+ * CONFIG_SSP_DEBUG - Define to enable basic SSP debug
+ * CONFIG_SSP_VERBOSE - Define to enable verbose SSP debug
+ */
+
+#ifdef CONFIG_SSP_DEBUG
+#  define sspdbg  lldbg
+#  ifdef CONFIG_SSP_VERBOSE
+#    define spivdbg lldbg
+#  else
+#    define spivdbg(x...)
+#  endif
+#else
+#  undef CONFIG_SSP_VERBOSE
+#  define sspdbg(x...)
+#  define spivdbg(x...)
+#endif
+
+/* SSP Clocking.
+ *
+ * The CPU clock by 1, 2, 4, or 8 to get the SSP peripheral clock (SSP_CLOCK).
+ * SSP_CLOCK may be further divided by 2-254 to get the SSP clock.  If we
+ * want a usable range of 4KHz to 25MHz for the SSP, then:
+ *
+ * 1. SSPCLK must be greater than (2*25MHz) = 50MHz, and
+ * 2. SSPCLK must be less than (254*40Khz) = 101.6MHz.
+ *
+ * If we assume that CCLK less than or equal to 100MHz, we can just
+ * use the CCLK undivided to get the SSP_CLOCK.
+ */
+
+#if LPC43_CCLK > 100000000
+#  error "CCLK <= 100,000,000 assumed"
+#endif
+
+#define SSP_PCLKSET_DIV    SYSCON_PCLKSEL_CCLK
+#define SSP_CLOCK          LPC43_CCLK
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/* This structure descibes the state of the SSP driver */
+
+struct lpc43_sspdev_s
+{
+  struct spi_dev_s spidev;     /* Externally visible part of the SPI interface */
+  uint32_t         sspbase;    /* SPIn base address */
+#ifdef CONFIG_LPC43_SSP_INTERRUPTS
+  uint8_t          sspirq;     /* SPI IRQ number */
+#endif
+#ifndef CONFIG_SPI_OWNBUS
+  sem_t            exclsem;    /* Held while chip is selected for mutual exclusion */
+  uint32_t         frequency;  /* Requested clock frequency */
+  uint32_t         actual;     /* Actual clock frequency */
+  uint8_t          nbits;      /* Width of word in bits (4 to 16) */
+  uint8_t          mode;       /* Mode 0,1,2,3 */
+#endif
+};
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/* Helpers */
+
+static inline uint32_t ssp_getreg(FAR struct lpc43_sspdev_s *priv, uint8_t offset);
+static inline void ssp_putreg(FAR struct lpc43_sspdev_s *priv, uint8_t offset,
+                                 uint32_t value);
+
+/* SPI methods */
+
+#ifndef CONFIG_SPI_OWNBUS
+static int      ssp_lock(FAR struct spi_dev_s *dev, bool lock);
+#endif
+static uint32_t ssp_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency);
+static void     ssp_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode);
+static void     ssp_setbits(FAR struct spi_dev_s *dev, int nbits);
+static uint16_t ssp_send(FAR struct spi_dev_s *dev, uint16_t ch);
+static void     ssp_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size_t nwords);
+static void     ssp_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nwords);
+
+/* Initialization */
+
+#ifdef CONFIG_LPC43_SSP0
+static inline FAR struct lpc43_sspdev_s *lpc43_ssp0initialize(void);
+#endif
+#ifdef CONFIG_LPC43_SSP1
+static inline FAR struct lpc43_sspdev_s *lpc43_ssp1initialize(void);
+#endif
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+#ifdef CONFIG_LPC43_SSP0
+static const struct spi_ops_s g_spi0ops =
+{
+#ifndef CONFIG_SPI_OWNBUS
+  .lock              = ssp_lock,
+#endif
+  .select            = lpc43_ssp0select,   /* Provided externally */
+  .setfrequency      = ssp_setfrequency,
+  .setmode           = ssp_setmode,
+  .setbits           = ssp_setbits,
+  .status            = lpc43_ssp0status,   /* Provided externally */
+#ifdef CONFIG_SPI_CMDDATA
+  .cmddata           = lpc43_ssp0cmddata,  /* Provided externally */
+#endif
+  .send              = ssp_send,
+  .sndblock          = ssp_sndblock,
+  .recvblock         = ssp_recvblock,
+#ifdef CONFIG_SPI_CALLBACK
+  .registercallback  = lpc43_ssp0register, /* Provided externally */
+#else
+  .registercallback  = 0,                  /* Not implemented */
+#endif
+};
+
+static struct lpc43_sspdev_s g_ssp0dev =
+{
+  .spidev            = { &g_spi0ops },
+  .sspbase           = LPC43_SSP0_BASE,
+#ifdef CONFIG_LPC43_SSP_INTERRUPTS
+  .sspirq            = LPC43_IRQ_SSP0,
+#endif
+}; 
+#endif /* CONFIG_LPC43_SSP0 */
+
+#ifdef CONFIG_LPC43_SSP1
+static const struct spi_ops_s g_spi1ops =
+{
+#ifndef CONFIG_SPI_OWNBUS
+  .lock              = ssp_lock,
+#endif
+  .select            = lpc43_ssp1select,   /* Provided externally */
+  .setfrequency      = ssp_setfrequency,
+  .setmode           = ssp_setmode,
+  .setbits           = ssp_setbits,
+  .status            = lpc43_ssp1status,   /* Provided externally */
+#ifdef CONFIG_SPI_CMDDATA
+  .cmddata           = lpc43_ssp1cmddata,  /* Provided externally */
+#endif
+  .send              = ssp_send,
+  .sndblock          = ssp_sndblock,
+  .recvblock         = ssp_recvblock,
+#ifdef CONFIG_SPI_CALLBACK
+  .registercallback  = lpc43_ssp1register, /* Provided externally */
+#else
+  .registercallback  = 0,                  /* Not implemented */
+#endif
+};
+
+static struct lpc43_sspdev_s g_ssp1dev =
+{
+  .spidev            = { &g_spi1ops },
+  .sspbase           = LPC43_SSP1_BASE,
+#ifdef CONFIG_LPC43_SSP_INTERRUPTS
+  .sspirq            = LPC43_IRQ_SSP1,
+#endif
+}; 
+#endif /* CONFIG_LPC43_SSP1 */
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: ssp_getreg
+ *
+ * Description:
+ *   Get the contents of the SPI register at offset
+ *
+ * Input Parameters:
+ *   priv   - private SPI device structure
+ *   offset - offset to the register of interest
+ *
+ * Returned Value:
+ *   The contents of the 32-bit register
+ *
+ ****************************************************************************/
+
+static inline uint32_t ssp_getreg(FAR struct lpc43_sspdev_s *priv, uint8_t offset)
+{
+  return getreg32(priv->sspbase + (uint32_t)offset);
+}
+
+/****************************************************************************
+ * Name: ssp_putreg
+ *
+ * Description:
+ *   Write a 32-bit value to the SPI register at offset
+ *
+ * Input Parameters:
+ *   priv   - private SPI device structure
+ *   offset - offset to the register of interest
+ *   value  - the 16-bit value to be written
+ *
+ * Returned Value:
+ *   None
+ *
+ ***************************************************************************/
+
+static inline void ssp_putreg(FAR struct lpc43_sspdev_s *priv, uint8_t offset, uint32_t value)
+{
+  putreg32(value, priv->sspbase + (uint32_t)offset);
+}
+
+/****************************************************************************
+ * Name: ssp_lock
+ *
+ * Description:
+ *   On SPI busses where there are multiple devices, it will be necessary to
+ *   lock SPI to have exclusive access to the busses for a sequence of
+ *   transfers.  The bus should be locked before the chip is selected. After
+ *   locking the SPI bus, the caller should then also call the setfrequency,
+ *   setbits, and setmode methods to make sure that the SPI is properly
+ *   configured for the device.  If the SPI buss is being shared, then it
+ *   may have been left in an incompatible state.
+ *
+ * Input Parameters:
+ *   dev  - Device-specific state data
+ *   lock - true: Lock spi bus, false: unlock SPI bus
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+#ifndef CONFIG_SPI_OWNBUS
+static int ssp_lock(FAR struct spi_dev_s *dev, bool lock)
+{
+  FAR struct lpc43_sspdev_s *priv = (FAR struct lpc43_sspdev_s *)dev;
+
+  if (lock)
+    {
+      /* Take the semaphore (perhaps waiting) */
+
+      while (sem_wait(&priv->exclsem) != 0)
+        {
+          /* The only case that an error should occur here is if the wait was awakened
+           * by a signal.
+           */
+
+          ASSERT(errno == EINTR);
+        }
+    }
+  else
+    {
+      (void)sem_post(&priv->exclsem);
+    }
+  return OK;
+}
+#endif
+
+/****************************************************************************
+ * Name: ssp_setfrequency
+ *
+ * Description:
+ *   Set the SPI frequency.
+ *
+ * Input Parameters:
+ *   dev -       Device-specific state data
+ *   frequency - The SPI frequency requested
+ *
+ * Returned Value:
+ *   Returns the actual frequency selected
+ *
+ ****************************************************************************/
+
+static uint32_t ssp_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency)
+{
+  FAR struct lpc43_sspdev_s *priv = (FAR struct lpc43_sspdev_s *)dev;
+  uint32_t divisor;
+  uint32_t actual;
+
+  /* Check if the requested frequence is the same as the frequency selection */
+
+  DEBUGASSERT(priv && frequency <= SSP_CLOCK / 2);
+#ifndef CONFIG_SPI_OWNBUS
+  if (priv->frequency == frequency)
+    {
+      /* We are already at this frequency.  Return the actual. */
+
+      return priv->actual;
+    }
+#endif
+
+  /* frequency = SSP_CLOCK / divisor, or divisor = SSP_CLOCK / frequency */
+
+  divisor = SSP_CLOCK / frequency;
+
+   /* "In master mode, CPSDVSRmin = 2 or larger (even numbers only)" */
+
+  if (divisor < 2)
+    {
+      divisor = 2;
+    }
+  else if (divisor > 254)
+    {
+      divisor = 254;
+    }
+
+  divisor = (divisor + 1) & ~1;
+
+  /* Save the new divisor value */
+  
+  ssp_putreg(priv, LPC43_SSP_CPSR_OFFSET, divisor);
+
+  /* Calculate the new actual */
+
+  actual = SSP_CLOCK / divisor;
+
+  /* Save the frequency setting */
+
+#ifndef CONFIG_SPI_OWNBUS
+  priv->frequency = frequency;
+  priv->actual    = actual;
+#endif
+
+  sspdbg("Frequency %d->%d\n", frequency, actual);
+  return actual;
+}
+
+/****************************************************************************
+ * Name: ssp_setmode
+ *
+ * Description:
+ *   Set the SPI mode. Optional.  See enum spi_mode_e for mode definitions
+ *
+ * Input Parameters:
+ *   dev -  Device-specific state data
+ *   mode - The SPI mode requested
+ *
+ * Returned Value:
+ *   none
+ *
+ ****************************************************************************/
+
+static void ssp_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)
+{
+  FAR struct lpc43_sspdev_s *priv = (FAR struct lpc43_sspdev_s *)dev;
+  uint32_t regval;
+
+  /* Has the mode changed? */
+
+#ifndef CONFIG_SPI_OWNBUS
+  if (mode != priv->mode)
+    {
+#endif
+      /* Yes... Set CR0 appropriately */
+
+      regval = ssp_getreg(priv, LPC43_SSP_CR0_OFFSET);
+      regval &= ~(SSP_CR0_CPOL|SSP_CR0_CPHA);
+
+      switch (mode)
+        {
+        case SPIDEV_MODE0: /* CPOL=0; CPHA=0 */
+          break;
+ 
+        case SPIDEV_MODE1: /* CPOL=0; CPHA=1 */
+          regval |= SSP_CR0_CPHA;
+          break;
+ 
+        case SPIDEV_MODE2: /* CPOL=1; CPHA=0 */
+          regval |= SSP_CR0_CPOL;
+          break;
+ 
+        case SPIDEV_MODE3: /* CPOL=1; CPHA=1 */
+          regval |= (SSP_CR0_CPOL|SSP_CR0_CPHA);
+          break;
+ 
+        default:
+          sspdbg("Bad mode: %d\n", mode);
+          DEBUGASSERT(FALSE);
+          return;
+        }
+
+      ssp_putreg(priv, LPC43_SSP_CR0_OFFSET, regval);
+
+      /* Save the mode so that subsequent re-configurations will be faster */
+
+#ifndef CONFIG_SPI_OWNBUS
+      priv->mode = mode;
+    }
+#endif
+}
+
+/****************************************************************************
+ * Name: ssp_setbits
+ *
+ * Description:
+ *   Set the number if bits per word.
+ *
+ * Input Parameters:
+ *   dev -  Device-specific state data
+ *   nbits - The number of bits requests
+ *
+ * Returned Value:
+ *   none
+ *
+ ****************************************************************************/
+
+static void ssp_setbits(FAR struct spi_dev_s *dev, int nbits)
+{
+  FAR struct lpc43_sspdev_s *priv = (FAR struct lpc43_sspdev_s *)dev;
+  uint32_t regval;
+
+  /* Has the number of bits changed? */
+
+  DEBUGASSERT(priv && nbits > 3 && nbits < 17);
+#ifndef CONFIG_SPI_OWNBUS
+  if (nbits != priv->nbits)
+    {
+#endif
+      /* Yes... Set CR1 appropriately */
+
+      regval = ssp_getreg(priv, LPC43_SSP_CR0_OFFSET);
+      regval &= ~SSP_CR0_DSS_MASK;
+      regval |= ((nbits - 1) << SSP_CR0_DSS_SHIFT);
+      regval = ssp_getreg(priv, LPC43_SSP_CR0_OFFSET);
+
+      /* Save the selection so the subsequence re-configurations will be faster */
+
+#ifndef CONFIG_SPI_OWNBUS
+      priv->nbits = nbits;
+    }
+#endif
+}
+
+/****************************************************************************
+ * Name: ssp_send
+ *
+ * Description:
+ *   Exchange one word on SPI
+ *
+ * Input Parameters:
+ *   dev - Device-specific state data
+ *   wd  - The word to send.  the size of the data is determined by the
+ *         number of bits selected for the SPI interface.
+ *
+ * Returned Value:
+ *   response
+ *
+ ****************************************************************************/
+
+static uint16_t ssp_send(FAR struct spi_dev_s *dev, uint16_t wd)
+{
+  FAR struct lpc43_sspdev_s *priv = (FAR struct lpc43_sspdev_s *)dev;
+  register uint32_t regval;
+
+  /* Wait while the TX FIFO is full */
+
+  while (!(ssp_getreg(priv, LPC43_SSP_SR_OFFSET) & SSP_SR_TNF));
+
+  /* Write the byte to the TX FIFO */
+
+  ssp_putreg(priv, LPC43_SSP_DR_OFFSET, (uint32_t)wd);
+
+  /* Wait for the RX FIFO not empty */
+
+  while (!(ssp_getreg(priv, LPC43_SSP_SR_OFFSET) & SSP_SR_RNE));
+
+  /* Get the value from the RX FIFO and return it */
+
+  regval = ssp_getreg(priv, LPC43_SSP_DR_OFFSET);
+  sspdbg("%04x->%04x\n", wd, regval);
+  return (uint16_t)regval;
+}
+
+/*************************************************************************
+ * Name: ssp_sndblock
+ *
+ * Description:
+ *   Send a block of data on SPI
+ *
+ * Input Parameters:
+ *   dev -    Device-specific state data
+ *   buffer - A pointer to the buffer of data to be sent
+ *   nwords - the length of data to send from the buffer in number of words.
+ *            The wordsize is determined by the number of bits-per-word
+ *            selected for the SPI interface.  If nbits <= 8, the data is
+ *            packed into uint8_t's; if nbits >8, the data is packed into uint16_t's
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+static void ssp_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size_t nwords)
+{
+  FAR struct lpc43_sspdev_s *priv = (FAR struct lpc43_sspdev_s *)dev;
+  union
+  {
+    FAR const uint8_t  *p8;
+    FAR const uint16_t *p16;
+    FAR const void     *pv;
+  } u;
+  uint32_t data;
+  uint32_t sr;
+
+  /* Loop while thre are bytes remaining to be sent */
+
+  sspdbg("nwords: %d\n", nwords);
+  u.pv = buffer;
+  while (nwords > 0)
+    {
+      /* While the TX FIFO is not full and there are bytes left to send */
+
+      while ((ssp_getreg(priv, LPC43_SSP_SR_OFFSET) & SSP_SR_TNF) && nwords)
+        {
+          /* Fetch the data to send */
+
+          if (priv->nbits > 8)
+            {
+              data = (uint32_t)*u.p16++;
+            }
+          else
+            {
+              data = (uint32_t)*u.p8++;
+            }
+
+          /* Send the data */
+
+          ssp_putreg(priv, LPC43_SSP_DR_OFFSET, data);
+          nwords--;
+        }
+    }
+
+  /* Then discard all card responses until the RX & TX FIFOs are emptied. */
+
+  sspdbg("discarding\n");
+  do
+    {
+      /* Is there anything in the RX fifo? */
+
+      sr = ssp_getreg(priv, LPC43_SSP_SR_OFFSET);
+      if ((sr & SSP_SR_RNE) != 0)
+        {
+          /* Yes.. Read and discard */
+
+          (void)ssp_getreg(priv, LPC43_SSP_DR_OFFSET);
+        }
+
+      /* There is a race condition where TFE may go true just before
+       * RNE goes true and this loop terminates prematurely.  The nasty little
+       * delay in the following solves that (it could probably be tuned
+       * to improve performance).
+       */
+
+      else if ((sr & SSP_SR_TFE) != 0)
+        {
+          up_udelay(100);
+          sr = ssp_getreg(priv, LPC43_SSP_SR_OFFSET);
+        }
+    }
+  while ((sr & SSP_SR_RNE) != 0 || (sr & SSP_SR_TFE) == 0);
+}
+
+/****************************************************************************
+ * Name: ssp_recvblock
+ *
+ * Description:
+ *   Revice a block of data from SPI
+ *
+ * Input Parameters:
+ *   dev -    Device-specific state data
+ *   buffer - A pointer to the buffer in which to recieve data
+ *   nwords - the length of data that can be received in the buffer in number
+ *            of words.  The wordsize is determined by the number of bits-per-word
+ *            selected for the SPI interface.  If nbits <= 8, the data is
+ *            packed into uint8_t's; if nbits >8, the data is packed into uint16_t's
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+static void ssp_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nwords)
+{
+  FAR struct lpc43_sspdev_s *priv = (FAR struct lpc43_sspdev_s *)dev;
+  union
+  {
+    FAR uint8_t  *p8;
+    FAR uint16_t *p16;
+    FAR void     *pv;
+  } u;
+  uint32_t data;
+  uint32_t rxpending = 0;
+
+  /* While there is remaining to be sent (and no synchronization error has occurred) */
+
+  sspdbg("nwords: %d\n", nwords);
+  u.pv = buffer;
+  while (nwords || rxpending)
+    {
+      /* Fill the transmit FIFO with 0xffff...
+       * Write 0xff to the data register while (1) the TX FIFO is
+       * not full, (2) we have not exceeded the depth of the TX FIFO,
+       * and (3) there are more bytes to be sent.
+       */
+
+      spivdbg("TX: rxpending: %d nwords: %d\n", rxpending, nwords);
+      while ((ssp_getreg(priv, LPC43_SSP_SR_OFFSET) & SSP_SR_TNF) &&
+             (rxpending < LPC43_SSP_FIFOSZ) && nwords)
+        {
+          ssp_putreg(priv, LPC43_SSP_DR_OFFSET, 0xffff);
+          nwords--;
+          rxpending++;
+        }
+
+      /* Now, read the RX data from the RX FIFO while the RX FIFO is not empty */
+
+      spivdbg("RX: rxpending: %d\n", rxpending);
+      while (ssp_getreg(priv, LPC43_SSP_SR_OFFSET) & SSP_SR_RNE)
+        {
+          data = (uint8_t)ssp_getreg(priv, LPC43_SSP_DR_OFFSET);
+          if (priv->nbits > 8)
+            {
+              *u.p16++ = (uint16_t)data;
+            }
+          else
+            {
+              *u.p8++  = (uint8_t)data;
+            }
+          rxpending--;
+        }
+    }
+}
+
+/****************************************************************************
+ * Name: lpc43_ssp0initialize
+ *
+ * Description:
+ *   Initialize the SSP0
+ *
+ * Input Parameter:
+ *   None
+ *
+ * Returned Value:
+ *   Valid SPI device structure reference on succcess; a NULL on failure
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_LPC43_SSP0
+static inline FAR struct lpc43_sspdev_s *lpc43_ssp0initialize(void)
+{
+  irqstate_t flags;
+  uint32_t regval;
+
+  /* Configure multiplexed pins as connected on the board.  Chip select
+   * pins must be configured by board-specific logic.  All SSP0 pins and
+   * one SSP1 pin (SCK) have multiple, alternative pin selection.
+   * Definitions in the board.h file must be provided to resolve the
+   * board-specific pin configuration like:
+   *
+   * #define GPIO_SSP0_SCK GPIO_SSP0_SCK_1
+   */
+
+  flags = irqsave();
+  lpc43_configgpio(GPIO_SSP0_SCK);
+  lpc43_configgpio(GPIO_SSP0_MISO);
+  lpc43_configgpio(GPIO_SSP0_MOSI);
+
+  /* Configure clocking */
+
+  regval  = getreg32(LPC43_SYSCON_PCLKSEL1);
+  regval &= ~SYSCON_PCLKSEL1_SSP0_MASK;
+  regval |= (SSP_PCLKSET_DIV << SYSCON_PCLKSEL1_SSP0_SHIFT);
+  putreg32(regval, LPC43_SYSCON_PCLKSEL1);
+
+  /* Enable peripheral clocking to SSP0 */
+
+  regval  = getreg32(LPC43_SYSCON_PCONP);
+  regval |= SYSCON_PCONP_PCSSP0;
+  putreg32(regval, LPC43_SYSCON_PCONP);
+  irqrestore(flags);
+
+  return &g_ssp0dev;
+}
+#endif
+
+/****************************************************************************
+ * Name: lpc43_ssp1initialize
+ *
+ * Description:
+ *   Initialize the SSP1
+ *
+ * Input Parameter:
+ *   None
+ *
+ * Returned Value:
+ *   Valid SPI device structure reference on succcess; a NULL on failure
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_LPC43_SSP1
+static inline FAR struct lpc43_sspdev_s *lpc43_ssp1initialize(void)
+{
+  irqstate_t flags;
+  uint32_t regval;
+
+  /* Configure multiplexed pins as connected on the board.  Chip select
+   * pins must be configured by board-specific logic.  All SSP0 pins and
+   * one SSP1 pin (SCK) have multiple, alternative pin selection.
+   * Definitions in the board.h file must be provided to resolve the
+   * board-specific pin configuration like:
+   *
+   * #define GPIO_SSP0_SCK GPIO_SSP0_SCK_1
+   */
+
+  flags = irqsave();
+  lpc43_configgpio(GPIO_SSP1_SCK);
+  lpc43_configgpio(GPIO_SSP1_MISO);
+  lpc43_configgpio(GPIO_SSP1_MOSI);
+
+  /* Configure clocking */
+
+  regval  = getreg32(LPC43_SYSCON_PCLKSEL0);
+  regval &= ~SYSCON_PCLKSEL0_SSP1_MASK;
+  regval |= (SSP_PCLKSET_DIV << SYSCON_PCLKSEL0_SSP1_SHIFT);
+  putreg32(regval, LPC43_SYSCON_PCLKSEL0);
+
+  /* Enable peripheral clocking to SSP0 and SSP1 */
+
+  regval  = getreg32(LPC43_SYSCON_PCONP);
+  regval |= SYSCON_PCONP_PCSSP1;
+  putreg32(regval, LPC43_SYSCON_PCONP);
+  irqrestore(flags);
+
+  return &g_ssp1dev;
+}
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: lpc43_sspinitialize
+ *
+ * Description:
+ *   Initialize the selected SSP port (0=SSP0, 1=SSP1)
+ *
+ * Input Parameter:
+ *   port - Port number (0=SSP0, 1=SSP1)
+ *
+ * Returned Value:
+ *   Valid SPI device structure reference on succcess; a NULL on failure
+ *
+ ****************************************************************************/
+
+FAR struct spi_dev_s *lpc43_sspinitialize(int port)
+{
+  FAR struct lpc43_sspdev_s *priv;
+  uint32_t regval;
+  int i;
+
+  /* Only the SSP0 and SSP1 interfaces are supported */
+
+  switch (port)
+    {
+#ifdef CONFIG_LPC43_SSP0
+    case 0:
+      priv = lpc43_ssp0initialize();
+      break;
+#endif
+#ifdef CONFIG_LPC43_SSP1
+    case 1:
+      priv = lpc43_ssp1initialize();
+      break;
+#endif
+    default:
+      return NULL;
+    }
+
+  /* Configure 8-bit SPI mode */
+
+  ssp_putreg(priv, LPC43_SSP_CR0_OFFSET, SSP_CR0_DSS_8BIT|SSP_CR0_FRF_SPI);
+
+  /* Disable the SSP and all interrupts (we'll poll for all data) */
+
+  ssp_putreg(priv, LPC43_SSP_CR1_OFFSET, 0);
+  ssp_putreg(priv, LPC43_SSP_IMSC_OFFSET, 0);
+
+  /* Set the initial SSP configuration */
+
+#ifndef CONFIG_SPI_OWNBUS
+  priv->frequency = 0;
+  priv->nbits     = 8;
+  priv->mode      = SPIDEV_MODE0;
+#endif
+
+  /* Select a default frequency of approx. 400KHz */
+
+  ssp_setfrequency((FAR struct spi_dev_s *)priv, 400000);
+
+  /* Initialize the SPI semaphore that enforces mutually exclusive access */
+
+#ifndef CONFIG_SPI_OWNBUS
+  sem_init(&priv->exclsem, 0, 1);
+#endif
+
+  /* Enable the SPI */
+
+  regval = ssp_getreg(priv, LPC43_SSP_CR1_OFFSET);
+  ssp_putreg(priv, LPC43_SSP_CR1_OFFSET, regval | SSP_CR1_SSE);
+  for (i = 0; i < LPC43_SSP_FIFOSZ; i++)
+    {
+      (void)ssp_getreg(priv, LPC43_SSP_DR_OFFSET);
+    }
+
+  return &priv->spidev;
+}
+
+/****************************************************************************
+ * Name: ssp_flush
+ *
+ * Description:
+ *   Flush and discard any words left in the RX fifo.  This can be done
+ *   after a device is deselected if you worry about such things.
+ *
+ * Input Parameters:
+ *   dev - Device-specific state data
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+void ssp_flush(FAR struct spi_dev_s *dev)
+{
+  FAR struct lpc43_sspdev_s *priv = (FAR struct lpc43_sspdev_s *)dev;
+
+  /* Wait for the TX FIFO not full indication */
+
+  while (!(ssp_getreg(priv, LPC43_SSP_SR_OFFSET) & SSP_SR_TNF));
+  ssp_putreg(priv, LPC43_SSP_DR_OFFSET, 0xff);
+
+  /* Wait until TX FIFO and TX shift buffer are empty */
+
+  while (ssp_getreg(priv, LPC43_SSP_SR_OFFSET) & SSP_SR_BSY);
+
+  /* Wait until RX FIFO is not empty */
+
+  while (!(ssp_getreg(priv, LPC43_SSP_SR_OFFSET) & SSP_SR_RNE));
+
+  /* Then read and discard bytes until the RX FIFO is empty */
+
+  do
+    {
+      (void)ssp_getreg(priv, LPC43_SSP_DR_OFFSET);
+    }
+  while (ssp_getreg(priv, LPC43_SSP_SR_OFFSET) & SSP_SR_RNE);
+}
+
+#endif /* CONFIG_LPC43_SSP0/1 */
+
diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_ssp.h b/nuttx/arch/arm/src/lpc43xx/lpc43_ssp.h
new file mode 100644
index 000000000..cec08e5d0
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/lpc43_ssp.h
@@ -0,0 +1,197 @@
+/************************************************************************************
+ * arch/arm/src/lpc43xx/lpc43_ssp.h
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LPC43XX_SSP_H
+#define __ARCH_ARM_SRC_LPC43XX_SSP_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/spi.h>
+#include "chip/lpc43_ssp.h"
+
+#if defined(CONFIG_LPC43_SSP0) || defined(CONFIG_LPC43_SSP1)
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+/* This header file defines interfaces to common SSP logic.  To use this common SSP
+ * logic on your board:
+ *
+ * 1. Provide logic in lpc43_boardinitialize() to configure SSP chip select pins.
+ * 2. Provide lpc43_ssp0/1select() and lpc43_ssp0/1status() functions in your
+ *    board-specific logic.  These functions will perform chip selection
+ *    and status operations using GPIOs in the way your board is configured.
+ * 3. If CONFIG_SPI_CMDDATA is defined in the NuttX configuration, provide
+ *    lpc43_ssp0/1cmddata() functions in your board-specific logic.  These
+ *    functions will perform cmd/data selection operations using GPIOs in the
+ *    way your board is configured.
+ * 4. Your low level board initialization logic should call lpc43_sspinitialize.
+ * 5. The handle returned by lpc43_sspinitialize() may then be used to bind the
+ *    SSP driver to higher level logic (e.g., calling  mmcsd_spislotinitialize(),
+ *    for example, will bind the SPI driver to the SPI MMC/SD driver).
+ */
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C" {
+#else
+#define EXTERN extern
+#endif
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+/****************************************************************************
+ * Name: lpc43_sspinitialize
+ *
+ * Description:
+ *   Initialize the selected SSP port (0=SSP0, 1=SSP1)
+ *
+ * Input Parameter:
+ *   port - Port number (0=SSP0, 1=SSP1)
+ *
+ * Returned Value:
+ *   Valid SPI device structure reference on succcess; a NULL on failure
+ *
+ ****************************************************************************/
+
+FAR struct spi_dev_s *lpc43_sspinitialize(int port)
+
+/************************************************************************************
+ * Name:  lpc43_ssp0/1select, lpc43_ssp0/1status, and lpc43_ssp0/1cmddata
+ *
+ * Description:
+ *   These functions must be provided in your board-specific logic.  The
+ *   lpc43_ssp0/1select functions will perform chip selection and the
+ *   lpc43_ssp0/1status will perform status operations using GPIOs in the way your
+ *   board is configured.
+ *
+ *   If CONFIG_SPI_CMDDATA is defined in the NuttX configuration, then
+ *   lpc43_ssp0/1cmddata must also be provided.  This functions performs cmd/data
+ *   selection operations using GPIOs in the way your board is configured.
+ *
+ ************************************************************************************/
+
+#ifdef CONFIG_LPC43_SSP0
+EXTERN void  lpc43_ssp0select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected);
+EXTERN uint8_t lpc43_ssp0status(FAR struct spi_dev_s *dev, enum spi_dev_e devid);
+#ifdef CONFIG_SPI_CMDDATA
+EXTERN int lpc43_ssp0cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd);
+#endif
+#endif
+
+#ifdef CONFIG_LPC43_SSP1
+EXTERN void  lpc43_ssp1select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected);
+EXTERN uint8_t lpc43_ssp1status(FAR struct spi_dev_s *dev, enum spi_dev_e devid);
+#ifdef CONFIG_SPI_CMDDATA
+EXTERN int lpc43_ssp1cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd);
+#endif
+#endif
+
+/****************************************************************************
+ * Name: spi_flush
+ *
+ * Description:
+ *   Flush and discard any words left in the RX fifo.  This can be called
+ *   from ssp0/1select after a device is deselected (if you worry about such
+ *   things).
+ *
+ * Input Parameters:
+ *   dev - Device-specific state data
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+#if defined(CONFIG_LPC43_SSP0) || defined(CONFIG_LPC43_SSP1)
+EXTERN void ssp_flush(FAR struct spi_dev_s *dev);
+#endif
+
+/****************************************************************************
+ * Name: lpc43_spi/ssp0/1register
+ *
+ * Description:
+ *   If the board supports a card detect callback to inform the SPI-based
+ *   MMC/SD drvier when an SD card is inserted or removed, then
+ *   CONFIG_SPI_CALLBACK should be defined and the following function(s) must
+ *   must be implemented.  These functiosn implements the registercallback
+ *   method of the SPI interface (see include/nuttx/spi.h for details)
+ *
+ * Input Parameters:
+ *   dev -      Device-specific state data
+ *   callback - The funtion to call on the media change
+ *   arg -      A caller provided value to return with the callback
+ *
+ * Returned Value:
+ *   0 on success; negated errno on failure.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SPI_CALLBACK
+#ifdef CONFIG_LPC43_SSP0
+EXTERN int lpc43_ssp0register(FAR struct spi_dev_s *dev,
+                              spi_mediachange_t callback, void *arg);
+#endif
+
+#ifdef CONFIG_LPC43_SSP1
+EXTERN int lpc43_ssp1register(FAR struct spi_dev_s *dev,
+                              spi_mediachange_t callback, void *arg);
+#endif
+#endif
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* CONFIG_LPC43_SSP0/1 */
+#endif /* __ARCH_ARM_SRC_LPC43XX_SSP_H */
diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_start.c b/nuttx/arch/arm/src/lpc43xx/lpc43_start.c
new file mode 100644
index 000000000..88976e03d
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/lpc43_start.c
@@ -0,0 +1,349 @@
+/****************************************************************************
+ * arch/arm/src/lpc43xx/lpc43_start.c
+ * arch/arm/src/chip/lpc43_start.c
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+/*
+ * Power-Up Reset Overview
+ * -----------------------
+ *
+ * The ARM core starts executing code on reset with the program counter set
+ * to 0x0000:0000.  The LPC43xx contains a shadow pointer register that
+ * allows areas of memory to be mapped to address 0x0000:0000. The default,
+ * reset value of the shadow pointer is 0x1040:0000 so that on reset code in
+ * the boot ROM is always executed first.
+ *
+ * The boot starts after reset is released.  The IRC is selected as CPU clock
+ * and the Cortex-M4 starts the boot loader. By default the JTAG access to the
+ * chip is disabled at reset.  The boot ROM determines the boot mode based on
+ * the OTP BOOT_SRC value or reset state pins.  For flash-based parts, the part
+ * boots from internal flash by default.  Otherwse, the boot ROM copies the
+ * image to internal SRAM at location 0x1000:0000, sets the ARM's shadow
+ * pointer to 0x1000:0000, and jumps to that location.
+ *
+ * However, using JTAG the executable image can be also loaded directly into
+ * and executed from SRAM.
+ */
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <assert.h>
+#include <debug.h>
+
+#include <nuttx/init.h>
+#include <arch/board/board.h>
+
+#include "up_arch.h"
+#include "up_internal.h"
+#include "nvic.h"
+
+#include "chip/lpc43_creg.h"
+
+#include "lpc43_rgu.h"
+#include "lpc43_cgu.h"
+#include "lpc43_emc.h"
+#include "lpc43_uart.h"
+
+/****************************************************************************
+ * Preprocessor Definitions
+ ****************************************************************************/
+
+ /****************************************************************************
+ * Name: showprogress
+ *
+ * Description:
+ *   Print a character on the UART to show boot status.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_DEBUG
+#  define showprogress(c) up_lowputc(c)
+#else
+#  define showprogress(c)
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: lpc43_setbootrom
+ *
+ * Description:
+ *   Set the shadow register to 0x1040:0000 and the VTOR to 0x0000:0000 so
+ *   that any exceptions (particulary things like hard faults) that occur
+ *   before we are initialized are caught by the BOOT ROM.
+ *
+ ****************************************************************************/
+
+static inline void lpc43_setbootrom(void)
+{
+  /* Set the shadow register to the beginning of the boot ROM (Only bits 12-31) */
+
+  putreg32(LPC43_ROM_BASE, LPC43_CREG_M4MEMMAP);
+
+  /* Address zero now maps to the Boot ROM.  Make sure the the VTOR will
+   * use the ROM vector table at that address.
+   */
+
+  putreg32(0, NVIC_VECTAB);
+}
+
+/****************************************************************************
+ * Name: lpc43_enabuffering
+ *
+ * Description:
+ *   If we are executing from external FLASH, then enable buffering.
+ *
+ ****************************************************************************/
+
+#if defined(CONFIG_BOOT_CS0FLASH) || defined(CONFIG_BOOT_CS1FLASH) || \
+    defined(CONFIG_BOOT_CS2FLASH) || defined(CONFIG_BOOT_CS3FLASH)
+static inline void lpc43_enabuffering(void)
+{
+  uint32_t regval;
+
+#ifdef CONFIG_BOOT_CS0FLASH
+  regval = getreg32(LPC43_EMC_STATCONFIG0);
+  regval |= EMC_STATCONFIG_BENA
+  putreg32(regval, LPC43_EMC_STATCONFIG0);
+#endif
+
+#ifdef CONFIG_BOOT_CS1FLASH
+  regval = getreg32(LPC43_EMC_STATCONFIG1);
+  regval |= EMC_STATCONFIG_BENA
+  putreg32(regval, LPC43_EMC_STATCONFIG1);
+#endif
+
+#ifdef CONFIG_BOOT_CS2FLASH
+  regval = getreg32(LPC43_EMC_STATCONFIG2);
+  regval |= EMC_STATCONFIG_BENA
+  putreg32(regval, LPC43_EMC_STATCONFIG2);
+#endif
+
+#ifdef CONFIG_BOOT_CS3FLASH
+  regval = getreg32(LPC43_EMC_STATCONFIG3);
+  regval |= EMC_STATCONFIG_BENA
+  putreg32(regval, LPC43_EMC_STATCONFIG3);
+#endif
+}
+#else
+#  define lpc43_enabuffering()
+#endif
+
+/****************************************************************************
+ * Name: lpc43_fpuconfig
+ *
+ * Description:
+ *   Configure the FPU.  Relative bit settings:
+ *
+ *     CPACR:  Enables access to CP10 and CP11
+ *     CONTROL.FPCA: Determines whether the FP extension is active in the
+ *       current context:
+ *     FPCCR.ASPEN:  Enables automatic FP state preservation, then the
+ *       processor sets this bit to 1 on successful completion of any FP
+ *       instruction.
+ *     FPCCR.LSPEN:  Enables lazy context save of FP state. When this is
+ *       done, the processor reserves space on the stack for the FP state,
+ *       but does not save that state information to the stack.
+ *
+ *  Software must not change the value of the ASPEN bit or LSPEN bit while either:
+ *   - the CPACR permits access to CP10 and CP11, that give access to the FP
+ *     extension, or
+ *   - the CONTROL.FPCA bit is set to 1
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_ARCH_FPU
+#ifdef CONFIG_ARMV7M_CMNVECTOR
+
+static inline void lpc43_fpuconfig(void)
+{
+  uint32_t regval;
+
+  /* Set CONTROL.FPCA so that we always get the extended context frame
+   * with the volatile FP registers stacked above the basic context.
+   */
+
+  regval = getcontrol(); 
+  regval |= (1 << 2);
+  setcontrol(regval);
+
+  /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
+   * with the lazy FP context save behaviour.  Clear FPCCR.ASPEN since we
+   * are going to turn on CONTROL.FPCA for all contexts.
+   */
+
+  regval = getreg32(NVIC_FPCCR);
+  regval &= ~((1 << 31) | (1 << 30));
+  putreg32(regval, NVIC_FPCCR);
+
+  /* Enable full access to CP10 and CP11 */
+
+  regval = getreg32(NVIC_CPACR);
+  regval |= ((3 << (2*10)) | (3 << (2*11)));
+  putreg32(regval, NVIC_CPACR);
+}
+
+#else
+
+static inline void lpc43_fpuconfig(void)
+{
+  uint32_t regval;
+
+  /* Clear CONTROL.FPCA so that we do not get the extended context frame
+   * with the volatile FP registers stacked in the saved context.
+   */
+
+  regval = getcontrol(); 
+  regval &= ~(1 << 2);
+  setcontrol(regval);
+
+  /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
+   * with the lazy FP context save behaviour.  Clear FPCCR.ASPEN since we
+   * are going to keep CONTROL.FPCA off for all contexts.
+   */
+
+  regval = getreg32(NVIC_FPCCR);
+  regval &= ~((1 << 31) | (1 << 30));
+  putreg32(regval, NVIC_FPCCR);
+
+  /* Enable full access to CP10 and CP11 */
+
+  regval = getreg32(NVIC_CPACR);
+  regval |= ((3 << (2*10)) | (3 << (2*11)));
+  putreg32(regval, NVIC_CPACR);
+}
+
+#endif
+
+#else
+#  define lpc43_fpuconfig()
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: _start
+ *
+ * Description:
+ *   This is the reset entry point.
+ *
+ ****************************************************************************/
+
+void __start(void)
+{
+  const uint32_t *src;
+  uint32_t *dest;
+
+  /* Reset as many of the LPC43 peripherals as possible. This is necessary
+   * because the LPC43 does not provide any way of performing a full system
+   * reset under debugger control.  So, if CONFIG_DEBUG is set (indicating
+   * that a debugger is being used?), the the boot logic will call this 
+   * function on all restarts.
+   */
+
+#ifdef CONFIG_DEBUG
+  lpc43_softreset();
+#endif
+
+  /* Make sure that any exceptions (such as hard faults) that occur before
+   * we are initialized are caught by the BOOT ROM.
+   */
+
+  lpc43_setbootrom();
+
+  /* Configure the CGU clocking and the console uart so that we can get
+   * debug output as soon as possible.
+   */
+
+  lpc43_clockconfig();
+  lpc43_lowsetup();
+  showprogress('A');
+
+  /* If we are executing from external FLASH, then enable buffering */
+
+  lpc43_enabuffering();
+
+  /* Clear .bss.  We'll do this inline (vs. calling memset) just to be
+   * certain that there are no issues with the state of global variables.
+   */
+
+  for (dest = &_sbss; dest < &_ebss; )
+    {
+      *dest++ = 0;
+    }
+  showprogress('B');
+
+  /* Move the intialized data section from his temporary holding spot in
+   * FLASH into the correct place in SRAM.  The correct place in SRAM is
+   * give by _sdata and _edata.  The temporary location is in FLASH at the
+   * end of all of the other read-only data (.text, .rodata) at _eronly.
+   */
+
+  for (src = &_eronly, dest = &_sdata; dest < &_edata; )
+    {
+      *dest++ = *src++;
+    }
+  showprogress('C');
+
+  /* Initialize the FPU (if configured) */
+
+  lpc43_fpuconfig();
+  showprogress('D');
+
+  /* Perform early serial initialization */
+
+#ifdef USE_EARLYSERIALINIT
+  up_earlyserialinit();
+#endif
+  showprogress('E');
+
+  /* Initialize onboard resources */
+
+  lpc43_boardinitialize();
+  showprogress('F');
+
+  /* Then start NuttX */
+
+  showprogress('\r');
+  showprogress('\n');
+  os_start();
+
+  /* Shouldn't get here */
+
+  for(;;);
+}
diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_timerisr.c b/nuttx/arch/arm/src/lpc43xx/lpc43_timerisr.c
new file mode 100644
index 000000000..83a64e34f
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/lpc43_timerisr.c
@@ -0,0 +1,151 @@
+/****************************************************************************
+ * arch/arm/src/lpc43xx/lpc43_timerisr.c
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <time.h>
+#include <debug.h>
+
+#include <nuttx/arch.h>
+#include <arch/board/board.h>
+
+#include "nvic.h"
+#include "clock_internal.h"
+#include "up_internal.h"
+#include "up_arch.h"
+
+#include "chip.h"
+
+/****************************************************************************
+ * Definitions
+ ****************************************************************************/
+
+/* The desired timer interrupt frequency is provided by the definition
+ * CLK_TCK (see include/time.h).  CLK_TCK defines the desired number of
+ * system clock ticks per second.  That value is a user configurable setting
+ * that defaults to 100 (100 ticks per second = 10 MS interval).
+ *
+ * The Clock Source: Either the internal CCLK or external STCLK (P3.26) clock
+ * as the source in the STCTRL register.  This file alwyays configures the
+ * timer to use CCLK as its source.
+ */
+
+#define SYSTICK_RELOAD ((LPC43_CCLK / CLK_TCK) - 1)
+
+/* The size of the reload field is 24 bits.  Verify that the reload value
+ * will fit in the reload register.
+ */
+
+#if SYSTICK_RELOAD > 0x00ffffff
+#  error SYSTICK_RELOAD exceeds the range of the RELOAD register
+#endif
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Global Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Function:  up_timerisr
+ *
+ * Description:
+ *   The timer ISR will perform a variety of services for various portions
+ *   of the systems.
+ *
+ ****************************************************************************/
+
+int up_timerisr(int irq, uint32_t *regs)
+{
+  /* Process timer interrupt */
+
+  sched_process_timer();
+  return 0;
+}
+
+/****************************************************************************
+ * Function:  up_timerinit
+ *
+ * Description:
+ *   This function is called during start-up to initialize
+ *   the timer interrupt.
+ *
+ ****************************************************************************/
+
+void up_timerinit(void)
+{
+  uint32_t regval;
+
+  /* Set the SysTick interrupt to the default priority */
+
+  regval = getreg32(NVIC_SYSH12_15_PRIORITY);
+  regval &= ~NVIC_SYSH_PRIORITY_PR15_MASK;
+  regval |= (LPC43M4_SYSH_PRIORITY_DEFAULT << NVIC_SYSH_PRIORITY_PR15_SHIFT);
+  putreg32(regval, NVIC_SYSH12_15_PRIORITY);
+
+  /* Make sure that the SYSTICK clock source is set to use the LPC43xx CCLK */
+
+  regval = getreg32(NVIC_SYSTICK_CTRL);
+  regval |= NVIC_SYSTICK_CTRL_CLKSOURCE;
+  putreg32(regval, NVIC_SYSTICK_CTRL);
+
+  /* Configure SysTick to interrupt at the requested rate */
+
+  putreg32(SYSTICK_RELOAD, NVIC_SYSTICK_RELOAD);
+
+  /* Attach the timer interrupt vector */
+
+  (void)irq_attach(LPC43_IRQ_SYSTICK, (xcpt_t)up_timerisr);
+
+  /* Enable SysTick interrupts */
+
+  putreg32((NVIC_SYSTICK_CTRL_CLKSOURCE|NVIC_SYSTICK_CTRL_TICKINT|
+            NVIC_SYSTICK_CTRL_ENABLE), NVIC_SYSTICK_CTRL);
+
+  /* And enable the timer interrupt */
+
+  up_enable_irq(LPC43_IRQ_SYSTICK);
+}
diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_uart.c b/nuttx/arch/arm/src/lpc43xx/lpc43_uart.c
new file mode 100644
index 000000000..4491830f9
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/lpc43_uart.c
@@ -0,0 +1,600 @@
+/**************************************************************************
+ * arch/arm/src/lpc43xx/lpc43_uart.c
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ **************************************************************************/
+
+/**************************************************************************
+ * Included Files
+ **************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+
+#include <arch/irq.h>
+#include <arch/board/board.h>
+
+#include "up_internal.h"
+#include "up_arch.h"
+
+#include "chip.h"
+#include "lpc43_config.h"
+#include "lpc43_pinconfig.h"
+#include "lpc43_rgu.h"
+#include "lpc43_cgu.h"
+
+#include "lpc43_uart.h"
+
+/**************************************************************************
+ * Private Definitions
+ **************************************************************************/
+     
+/* Select UART parameters for the selected console */
+
+#if defined(CONFIG_USART0_SERIAL_CONSOLE)
+#  define CONSOLE_BASE     LPC43_USART0_BASE
+#  define CONSOLE_BASEFREQ BOARD_USART0_BASEFREQ
+#  define CONSOLE_BAUD     CONFIG_USART0_BAUD
+#  define CONSOLE_BITS     CONFIG_USART0_BITS
+#  define CONSOLE_PARITY   CONFIG_USART0_PARITY
+#  define CONSOLE_2STOP    CONFIG_USART0_2STOP
+#elif defined(CONFIG_UART1_SERIAL_CONSOLE)
+#  define CONSOLE_BASE     LPC43_UART1_BASE
+#  define CONSOLE_BASEFREQ BOARD_UART1_BASEFREQ
+#  define CONSOLE_BAUD     CONFIG_UART1_BAUD
+#  define CONSOLE_BITS     CONFIG_UART1_BITS
+#  define CONSOLE_PARITY   CONFIG_UART1_PARITY
+#  define CONSOLE_2STOP    CONFIG_UART1_2STOP
+#elif defined(CONFIG_USART2_SERIAL_CONSOLE)
+#  define CONSOLE_BASE     LPC43_USART2_BASE
+#  define CONSOLE_BASEFREQ BOARD_USART2_BASEFREQ
+#  define CONSOLE_BAUD     CONFIG_USART2_BAUD
+#  define CONSOLE_BITS     CONFIG_USART2_BITS
+#  define CONSOLE_PARITY   CONFIG_USART2_PARITY
+#  define CONSOLE_2STOP    CONFIG_USART2_2STOP
+#elif defined(CONFIG_USART3_SERIAL_CONSOLE)
+#  define CONSOLE_BASE     LPC43_USART3_BASE
+#  define CONSOLE_BASEFREQ BOARD_USART3_BASEFREQ
+#  define CONSOLE_BAUD     CONFIG_USART3_BAUD
+#  define CONSOLE_BITS     CONFIG_USART3_BITS
+#  define CONSOLE_PARITY   CONFIG_USART3_PARITY
+#  define CONSOLE_2STOP    CONFIG_USART3_2STOP
+#elif defined(HAVE_CONSOLE)
+#  error "No CONFIG_UARTn_SERIAL_CONSOLE Setting"
+#endif
+
+/* Get word length setting for the console */
+
+#if CONSOLE_BITS == 5
+#  define CONSOLE_LCR_WLS UART_LCR_WLS_5BIT
+#elif CONSOLE_BITS == 6
+#  define CONSOLE_LCR_WLS UART_LCR_WLS_6BIT
+#elif CONSOLE_BITS == 7
+#  define CONSOLE_LCR_WLS UART_LCR_WLS_7BIT
+#elif CONSOLE_BITS == 8
+#  define CONSOLE_LCR_WLS UART_LCR_WLS_8BIT
+#elif defined(HAVE_CONSOLE)
+#  error "Invalid CONFIG_UARTn_BITS setting for console "
+#endif
+
+/* Get parity setting for the console */
+
+#if CONSOLE_PARITY == 0
+#  define CONSOLE_LCR_PAR 0
+#elif CONSOLE_PARITY == 1
+#  define CONSOLE_LCR_PAR (UART_LCR_PE|UART_LCR_PS_ODD)
+#elif CONSOLE_PARITY == 2
+#  define CONSOLE_LCR_PAR (UART_LCR_PE|UART_LCR_PS_EVEN)
+#elif CONSOLE_PARITY == 3
+#  define CONSOLE_LCR_PAR (UART_LCR_PE|UART_LCR_PS_STICK1)
+#elif CONSOLE_PARITY == 4
+#  define CONSOLE_LCR_PAR (UART_LCR_PE|UART_LCR_PS_STICK0)
+#elif defined(HAVE_CONSOLE)
+#    error "Invalid CONFIG_UARTn_PARITY setting for CONSOLE"
+#endif
+
+/* Get stop-bit setting for the console and USART0/2/3, UART1 */
+
+#if CONSOLE_2STOP != 0
+#  define CONSOLE_LCR_STOP UART_LCR_STOP
+#else
+#  define CONSOLE_LCR_STOP 0
+#endif
+
+/* LCR and FCR values for the console */
+
+#define CONSOLE_LCR_VALUE (CONSOLE_LCR_WLS | CONSOLE_LCR_PAR | \
+                           CONSOLE_LCR_STOP)
+#define CONSOLE_FCR_VALUE (UART_FCR_RXTRIGGER_8 | UART_FCR_TXRST |\
+                           UART_FCR_RXRST | UART_FCR_FIFOEN)
+
+/**************************************************************************
+ * Private Types
+ **************************************************************************/
+
+/**************************************************************************
+ * Private Function Prototypes
+ **************************************************************************/
+
+/**************************************************************************
+ * Global Variables
+ **************************************************************************/
+
+/**************************************************************************
+ * Private Variables
+ **************************************************************************/
+
+/**************************************************************************
+ * Private Functions
+ **************************************************************************/
+
+/**************************************************************************
+ * Public Functions
+ **************************************************************************/
+
+/**************************************************************************
+ * Name: up_lowputc
+ *
+ * Description:
+ *   Output one byte on the serial console
+ *
+ **************************************************************************/
+
+void up_lowputc(char ch)
+{
+#if defined HAVE_UART && defined HAVE_CONSOLE
+  /* Wait for the transmitter to be available */
+
+  while ((getreg32(CONSOLE_BASE+LPC43_UART_LSR_OFFSET) & UART_LSR_THRE) == 0);
+
+  /* Send the character */
+
+  putreg32((uint32_t)ch, CONSOLE_BASE+LPC43_UART_THR_OFFSET);
+#endif
+}
+
+/**************************************************************************
+ * Name: lpc43_lowsetup
+ *
+ * Description:
+ *   This performs basic initialization of the UART used for the serial
+ *   console.  Its purpose is to get the console output availabe as soon
+ *   as possible.
+ *
+ *   The USART0/2/3 and UART1 peripherals are configured using the following registers:
+ *   1. Power: In the PCONP register, set bits PCUSART0/1/2/3.
+ *      On reset, USART0 and UART 1 are enabled (PCUSART0 = 1 and PCUART1 = 1)
+ *      and USART2/3 are disabled (PCUART1 = 0 and PCUSART3 = 0).
+ *   2. Peripheral clock: In the PCLKSEL0 register, select PCLK_USART0 and
+ *      PCLK_UART1; in the PCLKSEL1 register, select PCLK_USART2 and PCLK_USART3.
+ *   3. Baud rate: In the LCR register, set bit DLAB = 1. This enables access
+ *      to registers DLL and DLM for setting the baud rate. Also, if needed,
+ *      set the fractional baud rate in the fractional divider 
+ *   4. UART FIFO: Use bit FIFO enable (bit 0) in FCR register to
+ *      enable FIFO.
+ *   5. Pins: Select UART pins through the PINSEL registers and pin modes
+ *      through the PINMODE registers. UART receive pins should not have
+ *      pull-down resistors enabled.
+ *   6. Interrupts: To enable UART interrupts set bit DLAB = 0 in the LCRF
+ *      register. This enables access to IER. Interrupts are enabled
+ *      in the NVIC using the appropriate Interrupt Set Enable register.
+ *   7. DMA: UART transmit and receive functions can operate with the
+ *      GPDMA controller.
+ *
+ **************************************************************************/
+
+void lpc43_lowsetup(void)
+{
+#ifdef HAVE_UART
+  /* Enable clocking and  for all console UART and disable power for
+   * other UARTs
+   */
+
+#if defined(CONFIG_USART0_SERIAL_CONSOLE)
+  lpc43_usart0_setup();
+#elif defined(CONFIG_UART1_SERIAL_CONSOLE)
+  lpc43_uart1_setup();
+#elif defined(CONFIG_USART2_SERIAL_CONSOLE)
+  lpc43_usart2_setup();
+#elif defined(CONFIG_USART3_SERIAL_CONSOLE)
+  lpc43_usart3_setup();
+#endif
+
+  /* Configure the console (only) */
+
+#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG)
+
+  /* Clear fifos */
+
+  putreg32(UART_FCR_RXRST|UART_FCR_TXRST, CONSOLE_BASE+LPC43_UART_FCR_OFFSET);
+
+  /* Set trigger */
+
+  putreg32(UART_FCR_FIFOEN|UART_FCR_RXTRIGGER_8, CONSOLE_BASE+LPC43_UART_FCR_OFFSET);
+
+  /* Set up the LCR */
+
+  putreg32(CONSOLE_LCR_VALUE, CONSOLE_BASE+LPC43_UART_LCR_OFFSET);
+
+  /* Set the BAUD divisor */
+
+  lpc43_setbaud(CONSOLE_BASE, CONSOLE_BASEFREQ, CONSOLE_BAUD);
+
+  /* Configure the FIFOs */
+
+  putreg32(UART_FCR_RXTRIGGER_8|UART_FCR_TXRST|UART_FCR_RXRST|UART_FCR_FIFOEN,
+           CONSOLE_BASE+LPC43_UART_FCR_OFFSET);
+#endif
+#endif /* HAVE_UART */
+}
+
+/****************************************************************************
+ * Name: lpc43_u[s]art0/1/2/3_reset
+ *
+ * Description:
+ *   Reset a UART.  These functions are used by the serial driver when a
+ *   UART is closed.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_LPC43_USART0
+void lpc43_usart0_reset(void)
+{
+  putreg32(RGU_CTRL1_USART0_RST, LPC43_RGU_CTRL1);
+}
+#endif
+
+#ifdef CONFIG_LPC43_UART1
+void lpc43_uart1_reset(void)
+{
+  putreg32(RGU_CTRL1_UART1_RST, LPC43_RGU_CTRL1);
+}
+#endif
+
+#ifdef CONFIG_LPC43_USART2
+void lpc43_usart2_reset(void)
+{
+  putreg32(RGU_CTRL1_USART2_RST, LPC43_RGU_CTRL1);
+}
+#endif
+
+#ifdef CONFIG_LPC43_USART3
+void lpc43_usart3_reset(void)
+{
+  putreg32(RGU_CTRL1_USART3_RST, LPC43_RGU_CTRL1);
+}
+#endif
+
+/****************************************************************************
+ * Name: lpc43_usart0_setup, lpc43_uart1_setup, lpc43_usart2_setup, and
+ *       lpc43_usart3_setup
+ *
+ * Description:
+ *   Configure the U[S]ART.  This involves:
+ *
+ *   1. Connecting the input clock to the U[S]ART as specified in the
+ *      board.h file,
+ *   2. Configuring the U[S]ART pins
+ *
+ * USART0/2/3 and UART1 clocking and power control:
+ *
+ *    ----------------------------------- -------------- --------------
+ *                                        BASE CLOCK     BRANCH CLOCK
+ *    ----------------------------------- -------------- --------------
+ *    USART0 clock to register interface  BASE_M4_CLK    CLK_M4_USART0
+ *    USART0 peripheral clock (PCLK)      BASE_UART0_CLK CLK_APB0_UART0
+ *    UART1 clock to register interface   BASE_M4_CLK    CLK_M4_UART1
+ *    UART1 peripheral clock (PCLK)       BASE_UART1_CLK CLK_APB0_UART1
+ *    USART2 clock to register interface  BASE_M4_CLK    CLK_M4_USART2
+ *    USART2 peripheral clock (PCLK)      BASE_UART2_CLK CLK_APB2_UART2
+ *    USART3 clock to register interface  BASE_M4_CLK    CLK_M4_USART3
+ *    USART3 peripheral clock (PCLK)      BASE_UART3_CLK CLK_APB2_UART3
+ *    ----------------------------------- -------------- --------------
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_LPC43_USART0
+void lpc43_usart0_setup(void)
+{
+  uint32_t   regval;
+  irqstate_t flags;
+
+  /* Connect USART0 into the clock source specified in board.h */
+
+  flags   = irqsave();
+
+  regval  = getreg32(LPC43_BASE_USART0_CLK);
+  regval &= ~BASE_USART0_CLK_CLKSEL_MASK;
+  regval |= (BOARD_USART0_CLKSRC | BASE_USART0_CLK_AUTOBLOCK);
+  putreg32(regval, LPC43_BASE_USART0_CLK);
+
+  /* Configure I/O pins.  NOTE that multiple pin configuration options must
+   * be disambiguated by defining the pin configuration in the board.h
+   * header file.
+   */
+
+  lpc43_pin_config(PINCONF_U0_TXD);
+  lpc43_pin_config(PINCONF_U0_RXD);
+
+  /* If USART RS-485 mode is selected, then configure the DIR pin as well.
+   * NOTE, again, that multiple pin configuration options must be
+   * disambiguated by defining the pin configuration in the board.h header
+   * file.
+   */
+
+#ifdef CONFIG_USART0_RS485MODE
+  lpc43_pin_config(PINCONF_U0_DIR);
+#endif
+
+  irqrestore(flags);
+};
+#endif
+
+#ifdef CONFIG_LPC43_UART1
+void lpc43_uart1_setup(void)
+{
+  uint32_t   regval;
+  irqstate_t flags;
+
+  /* Connect UART1 into the clock source specified in board.h */
+
+  flags   = irqsave();
+
+  regval  = getreg32(LPC43_BASE_UART1_CLK);
+  regval &= ~BASE_UART1_CLK_CLKSEL_MASK;
+  regval |= (BOARD_UART1_CLKSRC | BASE_UART1_CLK_AUTOBLOCK);
+  putreg32(regval, LPC43_BASE_UART1_CLK);
+
+  /* Configure I/O pins.  NOTE that multiple pin configuration options must
+   * be disambiguated by defining the pin configuration in the board.h
+   * header file.
+   */
+
+  lpc43_pin_config(PINCONF_U1_TXD);
+  lpc43_pin_config(PINCONF_U1_RXD);
+#ifdef CONFIG_UART1_FLOWCONTROL
+  lpc43_pin_config(PINCONF_U1_CTS);
+  lpc43_pin_config(PINCONF_U1_DCD);
+  lpc43_pin_config(PINCONF_U1_DSR);
+  lpc43_pin_config(PINCONF_U1_DTR);
+  lpc43_pin_config(PINCONF_U1_RTS);
+#ifdef CONFIG_UART1_RINGINDICATOR
+  lpc43_pin_config(PINCONF_U1_RI);
+#endif
+#endif
+
+  irqrestore(flags);
+};
+#endif
+
+#ifdef CONFIG_LPC43_USART2
+void lpc43_usart2_setup(void)
+{
+  uint32_t   regval;
+  irqstate_t flags;
+
+  /* Connect USART2 the clock source specified in board.h */
+
+  flags   = irqsave();
+
+  regval  = getreg32(LPC43_BASE_USART2_CLK);
+  regval &= ~BASE_USART2_CLK_CLKSEL_MASK;
+  regval |= (BOARD_USART2_CLKSRC | BASE_USART2_CLK_AUTOBLOCK);
+  putreg32(regval, LPC43_BASE_USART2_CLK);
+
+  /* Configure I/O pins.  NOTE that multiple pin configuration options must
+   * be disambiguated by defining the pin configuration in the board.h
+   * header file.
+   */
+
+  lpc43_pin_config(PINCONF_U2_TXD);
+  lpc43_pin_config(PINCONF_U2_RXD);
+
+  /* If USART RS-485 mode is selected, then configure the DIR pin as well.
+   * NOTE, again, that multiple pin configuration options must be
+   * disambiguated by defining the pin configuration in the board.h header
+   * file.
+   */
+
+#ifdef CONFIG_USART2_RS485MODE
+  lpc43_pin_config(PINCONF_U2_DIR);
+#endif
+
+  irqrestore(flags);
+};
+#endif
+
+#ifdef CONFIG_LPC43_USART3
+void lpc43_usart3_setup(void)
+{
+  uint32_t   regval;
+  irqstate_t flags;
+
+  /* Connect USART3 into the clock source specified in board.h */
+
+  flags   = irqsave();
+
+  regval  = getreg32(LPC43_BASE_USART3_CLK);
+  regval &= ~BASE_USART3_CLK_CLKSEL_MASK;
+  regval |= (BOARD_USART3_CLKSRC | BASE_USART3_CLK_AUTOBLOCK);
+  putreg32(regval, LPC43_BASE_USART3_CLK);
+
+  /* Configure I/O pins.  NOTE that multiple pin configuration options must
+   * be disambiguated by defining the pin configuration in the board.h
+   * header file.
+   */
+
+  lpc43_pin_config(PINCONF_U3_TXD);
+  lpc43_pin_config(PINCONF_U3_RXD);
+
+  /* If USART RS-485 mode is selected, then configure the DIR pin as well.
+   * NOTE, again, that multiple pin configuration options must be
+   * disambiguated by defining the pin configuration in the board.h header
+   * file.
+   */
+
+#ifdef CONFIG_USART3_RS485MODE
+  lpc43_pin_config(PINCONF_U3_DIR);
+#endif
+
+  irqrestore(flags);
+};
+#endif
+
+/****************************************************************************
+ * Name: lpc43_setbaud
+ *
+ * Description:
+ *   Configure the U[S]ART divisors to accomplish the desired BAUD given the
+ *   U[S]ART base frequency.
+ *
+ *   This computationally intensive algorithm is based on the same logic
+ *   used in the NXP sample code.
+ *
+ ****************************************************************************/
+
+void lpc43_setbaud(uintptr_t uartbase, uint32_t basefreq, uint32_t baud)
+{
+  uint32_t lcr;      /* Line control register value */
+  uint32_t dl;       /* Best DLM/DLL full value */
+  uint32_t mul;      /* Best FDR MULVALL value */
+  uint32_t divadd;   /* Best FDR DIVADDVAL value */
+  uint32_t best;     /* Error value associated with best {dl, mul, divadd} */
+  uint32_t cdl;      /* Candidate DLM/DLL full value */
+  uint32_t cmul;     /* Candidate FDR MULVALL value */
+  uint32_t cdivadd;  /* Candidate FDR DIVADDVAL value */
+  uint32_t errval;   /* Error value associated with the candidate */
+
+ /* The U[S]ART buad is given by:
+  * 
+  * Fbaud =  Fbase * mul / (mul + divadd) / (16 * dl)
+  * dl    =  Fbase * mul / (mul + divadd) / Fbaud / 16
+  *       =  Fbase * mul / ((mul + divadd) * Fbaud * 16)
+  *       = ((Fbase * mul) >> 4) / ((mul + divadd) * Fbaud)
+  *
+  * Where the  value of MULVAL and DIVADDVAL comply with:
+  *
+  *  0 < mul < 16
+  *  0 <= divadd < mul
+  */
+ 
+  best   = UINT32_MAX;
+  divadd = 0;
+  mul    = 0;
+  dl     = 0;
+
+  /* Try each mulitplier value in the valid range */
+
+  for (cmul = 1 ; cmul < 16; cmul++)
+    {
+      /* Try each divider value in the valid range */
+
+      for (cdivadd = 0 ; cdivadd < cmul ; cdivadd++)
+        {
+          /* Candidate:
+           *   dl         = ((Fbase * mul) >> 4) / ((mul + cdivadd) * Fbaud)
+           *   (dl << 32) = (Fbase << 28) * cmul / ((mul + cdivadd) * Fbaud)
+          */
+
+          uint64_t dl64 = ((uint64_t)basefreq << 28) * cmul /
+                          ((cmul + cdivadd) * baud);
+
+          /* The lower 32-bits of this value is the error */
+
+          errval = (uint32_t)(dl64 & 0x00000000ffffffffull);
+
+          /* The upper 32-bits is the candidate DL value */
+
+          cdl = (uint32_t)(dl64 >> 32);
+
+          /* Round up */
+
+          if (errval > (1 << 31))
+            {
+              errval = -errval;
+              cdl++;
+            }
+
+          /* Check if the resulting candidate DL value is within range */
+
+          if (cdl < 1 || cdl > 65536)
+            {
+              /* No... try a different divadd value */
+
+              continue;
+            }
+
+          /* Is this the best combination that we have seen so far? */
+
+          if (errval < best)
+            {
+              /* Yes.. then the candidate is out best guess so far */
+
+              best   = errval;
+              dl     = cdl;
+              divadd = cdivadd;
+              mul    = cmul;
+
+              /* If the new best guess is exact (within our precision), then
+               * we are finished.
+               */
+
+              if (best == 0)
+                {
+                  break;
+                }
+            }
+        }
+    }
+
+  DEBUGASSERT(dl > 0);
+
+  /* Enter DLAB=1 */
+
+  lcr = getreg32(uartbase + LPC43_UART_LCR_OFFSET);
+  putreg32(lcr | UART_LCR_DLAB, uartbase + LPC43_UART_LCR_OFFSET);
+
+  /* Save then divider values */
+
+  putreg32(dl >> 8, uartbase + LPC43_UART_DLM_OFFSET);
+  putreg32(dl & 0xff, uartbase + LPC43_UART_DLL_OFFSET);
+
+  /* Clear DLAB */
+
+  putreg32(lcr & ~UART_LCR_DLAB, uartbase + LPC43_UART_LCR_OFFSET);
+
+  /* Then save the fractional divider values */
+
+  putreg32((mul << UART_FDR_MULVAL_SHIFT) | (divadd << UART_FDR_DIVADDVAL_SHIFT),
+           uartbase + LPC43_UART_FDR_OFFSET);
+}
diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_uart.h b/nuttx/arch/arm/src/lpc43xx/lpc43_uart.h
new file mode 100644
index 000000000..90216ff64
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/lpc43_uart.h
@@ -0,0 +1,156 @@
+/****************************************************************************
+ * arch/arm/src/lpc43xx/lpc43_uart.h
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LPC43XX_LPC43_LOWSETUP_H
+#define __ARCH_ARM_SRC_LPC43XX_LPC43_LOWSETUP_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include "chip.h"
+#include "chip/lpc43_uart.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C" {
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: lpc43_lowsetup
+ *
+ * Description:
+ *   Called at the very beginning of _start.  Performs low level
+ *   initialization of the serial console.
+ *
+ ****************************************************************************/
+
+EXTERN void lpc43_lowsetup(void);
+
+/****************************************************************************
+ * Name: lpc43_usart0_reset, lpc43_uart1_reset, lpc43_usart2_reset, and
+ *       lpc43_usart3_reset
+ *
+ * Description:
+ *   Reset a U[S]ART.  These functions are used by the serial driver when a
+ *   U[S]ART is closed.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_LPC43_USART0
+EXTERN void lpc43_usart0_reset(void);
+#endif
+#ifdef CONFIG_LPC43_UART1
+EXTERN void lpc43_uart1_reset(void);
+#endif
+#ifdef CONFIG_LPC43_USART2
+EXTERN void lpc43_usart2_reset(void);
+#endif
+#ifdef CONFIG_LPC43_USART3
+EXTERN void lpc43_usart3_reset(void);
+#endif
+
+/****************************************************************************
+ * Name: lpc43_usart0_setup, lpc43_uart1_setup, lpc43_usart2_setup, and
+ *       lpc43_usart3_setup
+ *
+ * Description:
+ *   Configure the U[S]ART.  This involves:
+ *
+ *   1. Connecting the input clock to the U[S]ART as specified in the
+ *      board.h file,
+ *   2. Configuring the U[S]ART pins
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_LPC43_USART0
+EXTERN void lpc43_usart0_setup(void);
+#endif
+
+#ifdef CONFIG_LPC43_UART1
+EXTERN void lpc43_uart1_setup(void);
+#endif
+
+#ifdef CONFIG_LPC43_USART2
+EXTERN void lpc43_usart2_setup(void);
+#endif
+
+#ifdef CONFIG_LPC43_USART3
+EXTERN void lpc43_usart3_setup(void);
+#endif
+
+/****************************************************************************
+ * Name: lpc43_setbaud
+ *
+ * Description:
+ *   Configure the U[S]ART divisors to accomplish the desired BAUD given the
+ *   U[S]ART base frequency.
+ *
+ *   This computationally intensive algorithm is based on the same logic
+ *   used in the NXP sample code.
+ *
+ ****************************************************************************/
+
+EXTERN void lpc43_setbaud(uintptr_t uartbase, uint32_t basefreq, uint32_t baud);
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_ARM_SRC_LPC43XX_LPC43_LOWSETUP_H */
diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_usb0dev.c b/nuttx/arch/arm/src/lpc43xx/lpc43_usb0dev.c
new file mode 100644
index 000000000..a40d6492d
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/lpc43_usb0dev.c
@@ -0,0 +1,2671 @@
+/*******************************************************************************
+ * arch/arm/src/lpc43xx/lpc43_usbdev.c
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Part of the NuttX OS and based, in part, on the LPC31xx USB driver:
+ *
+ *   Authors: David Hewson
+ *            Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Which, in turn, was based on the LPC2148 USB driver:
+ *
+ *   Copyright (C) 2010-2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ *******************************************************************************/
+
+/*******************************************************************************
+ * Included Files
+ *******************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <stdlib.h>
+#include <string.h>
+#include <errno.h>
+#include <debug.h>
+
+#include <nuttx/arch.h>
+#include <nuttx/usb/usb.h>
+#include <nuttx/usb/usbdev.h>
+#include <nuttx/usb/usbdev_trace.h>
+
+#include <arch/irq.h>
+#include <arch/board/board.h>
+
+#include "chip.h"
+#include "up_arch.h"
+#include "up_internal.h"
+
+#include "lpc43_usb0dev.h"
+
+/*******************************************************************************
+ * Definitions
+ *******************************************************************************/
+
+/* Configuration ***************************************************************/
+
+#ifndef CONFIG_USBDEV_EP0_MAXSIZE
+#  define CONFIG_USBDEV_EP0_MAXSIZE 64
+#endif
+
+#ifndef  CONFIG_USBDEV_MAXPOWER
+#  define CONFIG_USBDEV_MAXPOWER 100  /* mA */
+#endif
+
+/* Extremely detailed register debug that you would normally never want
+ * enabled.
+ */
+
+#undef CONFIG_LPC43_USBDEV_REGDEBUG
+
+/* Enable reading SOF from interrupt handler vs. simply reading on demand.  Probably
+ * a bad idea... Unless there is some issue with sampling the SOF from hardware
+ * asynchronously.
+ */
+
+#ifdef CONFIG_LPC43_USBDEV_FRAME_INTERRUPT
+#  define USB_FRAME_INT USBDEV_USBINTR_SRE
+#else
+#  define USB_FRAME_INT 0
+#endif
+
+#ifdef CONFIG_DEBUG
+#  define USB_ERROR_INT USBDEV_USBINTR_UEE
+#else
+#  define USB_ERROR_INT 0
+#endif
+
+/* Debug ***********************************************************************/
+
+/* Trace error codes */
+
+#define LPC43_TRACEERR_ALLOCFAIL            0x0001
+#define LPC43_TRACEERR_BADCLEARFEATURE      0x0002
+#define LPC43_TRACEERR_BADDEVGETSTATUS      0x0003
+#define LPC43_TRACEERR_BADEPNO              0x0004
+#define LPC43_TRACEERR_BADEPGETSTATUS       0x0005
+#define LPC43_TRACEERR_BADEPTYPE            0x0006
+#define LPC43_TRACEERR_BADGETCONFIG         0x0007
+#define LPC43_TRACEERR_BADGETSETDESC        0x0008
+#define LPC43_TRACEERR_BADGETSTATUS         0x0009
+#define LPC43_TRACEERR_BADSETADDRESS        0x000a
+#define LPC43_TRACEERR_BADSETCONFIG         0x000b
+#define LPC43_TRACEERR_BADSETFEATURE        0x000c
+#define LPC43_TRACEERR_BINDFAILED           0x000d
+#define LPC43_TRACEERR_DISPATCHSTALL        0x000e
+#define LPC43_TRACEERR_DRIVER               0x000f
+#define LPC43_TRACEERR_DRIVERREGISTERED     0x0010
+#define LPC43_TRACEERR_EP0SETUPSTALLED      0x0011
+#define LPC43_TRACEERR_EPINNULLPACKET       0x0012
+#define LPC43_TRACEERR_EPOUTNULLPACKET      0x0013
+#define LPC43_TRACEERR_INVALIDCTRLREQ       0x0014
+#define LPC43_TRACEERR_INVALIDPARMS         0x0015
+#define LPC43_TRACEERR_IRQREGISTRATION      0x0016
+#define LPC43_TRACEERR_NOEP                 0x0017
+#define LPC43_TRACEERR_NOTCONFIGURED        0x0018
+#define LPC43_TRACEERR_REQABORTED           0x0019
+
+/* Trace interrupt codes */
+
+#define LPC43_TRACEINTID_USB                0x0001
+#define LPC43_TRACEINTID_CLEARFEATURE       0x0002
+#define LPC43_TRACEINTID_DEVGETSTATUS       0x0003
+#define LPC43_TRACEINTID_DEVRESET           0x0004
+#define LPC43_TRACEINTID_DISPATCH           0x0005
+#define LPC43_TRACEINTID_EP0COMPLETE        0x0006
+#define LPC43_TRACEINTID_EP0NAK             0x0007
+#define LPC43_TRACEINTID_EP0SETUP           0x0008
+#define LPC43_TRACEINTID_EPGETSTATUS        0x0009
+#define LPC43_TRACEINTID_EPIN               0x000a
+#define LPC43_TRACEINTID_EPINQEMPTY         0x000b
+#define LPC43_TRACEINTID_EP0INSETADDRESS    0x000c
+#define LPC43_TRACEINTID_EPOUT              0x000d
+#define LPC43_TRACEINTID_EPOUTQEMPTY        0x000e
+#define LPC43_TRACEINTID_EP0SETUPSETADDRESS 0x000f
+#define LPC43_TRACEINTID_FRAME              0x0010
+#define LPC43_TRACEINTID_GETCONFIG          0x0011
+#define LPC43_TRACEINTID_GETSETDESC         0x0012
+#define LPC43_TRACEINTID_GETSETIF           0x0013
+#define LPC43_TRACEINTID_GETSTATUS          0x0014
+#define LPC43_TRACEINTID_IFGETSTATUS        0x0015
+#define LPC43_TRACEINTID_SETCONFIG          0x0016
+#define LPC43_TRACEINTID_SETFEATURE         0x0017
+#define LPC43_TRACEINTID_SUSPENDCHG         0x0018
+#define LPC43_TRACEINTID_SYNCHFRAME         0x0019
+
+/* Hardware interface **********************************************************/
+
+/* This represents a Endpoint Transfer Descriptor - note these must be 32 byte aligned */
+struct lpc43_dtd_s
+{
+  volatile uint32_t       nextdesc;      /* Address of the next DMA descripto in RAM */
+  volatile uint32_t       config;        /* Misc. bit encoded configuration information */
+  uint32_t                buffer0;       /* Buffer start address */
+  uint32_t                buffer1;       /* Buffer start address */
+  uint32_t                buffer2;       /* Buffer start address */
+  uint32_t                buffer3;       /* Buffer start address */
+  uint32_t                buffer4;       /* Buffer start address */
+  uint32_t                xfer_len;      /* Software only - transfer len that was queued */
+};
+
+/* DTD nextdesc field*/
+#define DTD_NEXTDESC_INVALID         (1 << 0)    /* Bit 0     : Next Descriptor Invalid */
+
+/* DTD config field */
+#define DTD_CONFIG_LENGTH(n)         ((n) << 16) /* Bits 16-31 : Total bytes to transfer */
+#define DTD_CONFIG_IOC               (1 << 15)   /* Bit 15     : Interrupt on Completion */
+#define DTD_CONFIG_MULT_VARIABLE     (0 << 10)   /* Bits 10-11 : Number of packets executed per transacation descriptor (override) */
+#define DTD_CONFIG_MULT_NUM(n)       ((n) << 10)
+#define DTD_CONFIG_ACTIVE            (1 << 7)    /* Bit 7      : Status Active */
+#define DTD_CONFIG_HALTED            (1 << 6)    /* Bit 6      : Status Halted */
+#define DTD_CONFIG_BUFFER_ERROR      (1 << 5)    /* Bit 6      : Status Buffer Error */
+#define DTD_CONFIG_TRANSACTION_ERROR (1 << 3)    /* Bit 3      : Status Transaction Error */
+
+/* This represents a queue head  - not these must be aligned to a 2048 byte boundary */
+struct lpc43_dqh_s
+{
+  uint32_t                capability;  /* Endpoint capability */
+  uint32_t                currdesc;    /* Current dTD pointer */
+  struct lpc43_dtd_s      overlay;     /* DTD overlay */
+  volatile uint32_t       setup[2];    /* Set-up buffer */
+  uint32_t                gap[4];      /* align to 64 bytes */
+};
+
+/* DQH capability field */
+#define DQH_CAPABILITY_MULT_VARIABLE (0 << 30)    /* Bits 30-31 : Number of packets executed per transaction descriptor */
+#define DQH_CAPABILITY_MULT_NUM(n)   ((n) << 30)
+#define DQH_CAPABILITY_ZLT           (1 << 29)    /* Bit 29     : Zero Length Termination Select */
+#define DQH_CAPABILITY_MAX_PACKET(n) ((n) << 16)  /* Bits 16-29 : Maximum packet size of associated endpoint (<1024) */
+#define DQH_CAPABILITY_IOS           (1 << 15)    /* Bit 15     : Interrupt on Setup */
+
+/* Endpoints ******************************************************************/
+
+/* Number of endpoints */
+#define LPC43_NLOGENDPOINTS          (4)          /* ep0-3 */
+#define LPC43_NPHYSENDPOINTS         (8)          /* x2 for IN and OUT */
+
+/* Odd physical endpoint numbers are IN; even are OUT */
+#define LPC43_EPPHYIN(epphy)         (((epphy)&1)!=0)
+#define LPC43_EPPHYOUT(epphy)        (((epphy)&1)==0)
+
+#define LPC43_EPPHYIN2LOG(epphy)     (((uint8_t)(epphy)>>1)|USB_DIR_IN)
+#define LPC43_EPPHYOUT2LOG(epphy)    (((uint8_t)(epphy)>>1)|USB_DIR_OUT)
+
+/* Endpoint 0 is special... */
+#define LPC43_EP0_OUT                (0)
+#define LPC43_EP0_IN                 (1)
+
+/* Each endpoint has somewhat different characteristics */
+#define LPC43_EPALLSET               (0xff)       /* All endpoints */
+#define LPC43_EPOUTSET               (0x55)       /* Even phy endpoint numbers are OUT EPs */
+#define LPC43_EPINSET                (0xaa)       /* Odd endpoint numbers are IN EPs */
+#define LPC43_EPCTRLSET              (0x03)       /* EP0 IN/OUT are control endpoints */
+#define LPC43_EPINTRSET              (0xa8)       /* Interrupt endpoints */
+#define LPC43_EPBULKSET              (0xfc)       /* Bulk endpoints */
+#define LPC43_EPISOCSET              (0xfc)       /* Isochronous endpoints */
+
+/* Maximum packet sizes for endpoints */
+#define LPC43_EP0MAXPACKET           (64)         /* EP0 max packet size (1-64) */
+#define LPC43_BULKMAXPACKET          (512)        /* Bulk endpoint max packet (8/16/32/64/512) */
+#define LPC43_INTRMAXPACKET          (1024)       /* Interrupt endpoint max packet (1 to 1024) */
+#define LPC43_ISOCMAXPACKET          (512)        /* Acutally 1..1023 */
+
+/* The address of the endpoint control register */
+#define LPC43_USBDEV_ENDPTCTRL(epphy) (LPC43_USBDEV_ENDPTCTRL0 + ((epphy)>>1)*4)
+
+/* Endpoint bit position in SETUPSTAT, PRIME, FLUSH, STAT, COMPLETE registers */
+#define LPC43_ENDPTSHIFT(epphy)      (LPC43_EPPHYIN(epphy) ? (16 + ((epphy) >> 1)) : ((epphy) >> 1))
+#define LPC43_ENDPTMASK(epphy)       (1 << LPC43_ENDPTSHIFT(epphy))
+#define LPC43_ENDPTMASK_ALL          0x000f000f
+
+/* Request queue operations ****************************************************/
+
+#define lpc43_rqempty(ep)            ((ep)->head == NULL)
+#define lpc43_rqpeek(ep)             ((ep)->head)
+
+/*******************************************************************************
+ * Private Types
+ *******************************************************************************/
+
+/* A container for a request so that the request may be retained in a list */
+
+struct lpc43_req_s
+{
+  struct usbdev_req_s  req;           /* Standard USB request */
+  struct lpc43_req_s  *flink;         /* Supports a singly linked list */
+};
+
+/* This is the internal representation of an endpoint */
+
+struct lpc43_ep_s
+{
+  /* Common endpoint fields.  This must be the first thing defined in the
+   * structure so that it is possible to simply cast from struct usbdev_ep_s
+   * to struct lpc43_ep_s.
+   */
+
+  struct usbdev_ep_s      ep;          /* Standard endpoint structure */
+
+  /* LPC43XX-specific fields */
+
+  struct lpc43_usbdev_s *dev;          /* Reference to private driver data */
+  struct lpc43_req_s    *head;         /* Request list for this endpoint */
+  struct lpc43_req_s    *tail;
+  uint8_t                epphy;        /* Physical EP address */
+  uint8_t                stalled:1;    /* 1: Endpoint is stalled */
+};
+
+/* This structure retains the state of the USB device controller */
+
+struct lpc43_usbdev_s
+{
+  /* Common device fields.  This must be the first thing defined in the
+   * structure so that it is possible to simply cast from struct usbdev_s
+   * to struct lpc43_usbdev_s.
+   */
+
+  struct usbdev_s         usbdev;
+
+  /* The bound device class driver */
+
+  struct usbdevclass_driver_s *driver;
+
+  /* LPC43XX-specific fields */
+
+  uint8_t                 ep0state;      /* State of certain EP0 operations */
+  uint8_t                 ep0buf[64];    /* buffer for EP0 short transfers */
+  uint8_t                 paddr;         /* Address assigned by SETADDRESS */
+  uint8_t                 stalled:1;     /* 1: Protocol stalled */
+  uint8_t                 selfpowered:1; /* 1: Device is self powered */
+  uint8_t                 paddrset:1;    /* 1: Peripheral addr has been set */
+  uint8_t                 attached:1;    /* 1: Host attached */
+  uint32_t                softprio;      /* Bitset of high priority interrupts */
+  uint32_t                epavail;       /* Bitset of available endpoints */
+#ifdef CONFIG_LPC43_USBDEV_FRAME_INTERRUPT
+  uint32_t                sof;           /* Last start-of-frame */
+#endif
+
+  /* The endpoint list */
+  struct lpc43_ep_s     eplist[LPC43_NPHYSENDPOINTS];
+};
+
+#define EP0STATE_IDLE             0        /* Idle State, leave on receiving a setup packet or epsubmit */
+#define EP0STATE_SETUP_OUT        1        /* Setup Packet received - SET/CLEAR */
+#define EP0STATE_SETUP_IN         2        /* Setup Packet received - GET */
+#define EP0STATE_SHORTWRITE       3        /* Short write without a usb_request */
+#define EP0STATE_WAIT_NAK_OUT     4        /* Waiting for Host to illicit status phase (GET) */
+#define EP0STATE_WAIT_NAK_IN      5        /* Waiting for Host to illicit status phase (SET/CLEAR) */
+#define EP0STATE_WAIT_STATUS_OUT  6        /* Wait for status phase to complete */
+#define EP0STATE_WAIT_STATUS_IN   7        /* Wait for status phase to complete */
+#define EP0STATE_DATA_IN          8
+#define EP0STATE_DATA_OUT         9
+
+/*******************************************************************************
+ * Private Function Prototypes
+ *******************************************************************************/
+
+/* Register operations ********************************************************/
+
+#if defined(CONFIG_LPC43_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG)
+static uint32_t lpc43_getreg(uint32_t addr);
+static void lpc43_putreg(uint32_t val, uint32_t addr);
+#else
+# define lpc43_getreg(addr)     getreg32(addr)
+# define lpc43_putreg(val,addr) putreg32(val,addr)
+#endif
+
+static inline void lpc43_clrbits(uint32_t mask, uint32_t addr);
+static inline void lpc43_setbits(uint32_t mask, uint32_t addr);
+static inline void lpc43_chgbits(uint32_t mask, uint32_t val, uint32_t addr);
+
+/* Request queue operations ****************************************************/
+
+static FAR struct lpc43_req_s *lpc43_rqdequeue(FAR struct lpc43_ep_s *privep);
+static bool       lpc43_rqenqueue(FAR struct lpc43_ep_s *privep,
+                    FAR struct lpc43_req_s *req);
+
+/* Low level data transfers and request operations *****************************/
+
+static inline void lpc43_writedtd(struct lpc43_dtd_s *dtd, const uint8_t *data,
+                     uint32_t nbytes);
+static inline void lpc43_queuedtd(uint8_t epphy, struct lpc43_dtd_s *dtd);
+static inline void lpc43_ep0xfer(uint8_t epphy, uint8_t *data, uint32_t nbytes);
+static void        lpc43_readsetup(uint8_t epphy, struct usb_ctrlreq_s *ctrl);
+
+static inline void lpc43_set_address(struct lpc43_usbdev_s *priv, uint16_t address);
+
+static void        lpc43_flushep(struct lpc43_ep_s *privep);
+
+static int         lpc43_progressep(struct lpc43_ep_s *privep);
+static inline void lpc43_abortrequest(struct lpc43_ep_s *privep,
+                     struct lpc43_req_s *privreq, int16_t result);
+static void        lpc43_reqcomplete(struct lpc43_ep_s *privep,
+                     struct lpc43_req_s *privreq, int16_t result);
+
+static void        lpc43_cancelrequests(struct lpc43_ep_s *privep, int16_t status);
+
+/* Interrupt handling **********************************************************/
+static struct lpc43_ep_s *lpc43_epfindbyaddr(struct lpc43_usbdev_s *priv,
+                     uint16_t eplog);
+static void        lpc43_dispatchrequest(struct lpc43_usbdev_s *priv,
+                     const struct usb_ctrlreq_s *ctrl);
+static void        lpc43_ep0configure(struct lpc43_usbdev_s *priv);
+static void        lpc43_usbreset(struct lpc43_usbdev_s *priv);
+
+static inline void lpc43_ep0state(struct lpc43_usbdev_s *priv, uint16_t state);
+static void        lpc43_ep0setup(struct lpc43_usbdev_s *priv);
+
+static void        lpc43_ep0complete(struct lpc43_usbdev_s *priv, uint8_t epphy);
+static void        lpc43_ep0nak(struct lpc43_usbdev_s *priv, uint8_t epphy);
+static bool        lpc43_epcomplete(struct lpc43_usbdev_s *priv, uint8_t epphy);
+
+static int         lpc43_usbinterrupt(int irq, FAR void *context);
+
+/* Endpoint operations *********************************************************/
+
+/* USB device controller operations ********************************************/
+
+static int  lpc43_epconfigure(FAR struct usbdev_ep_s *ep,
+              const struct usb_epdesc_s *desc, bool last);
+static int  lpc43_epdisable(FAR struct usbdev_ep_s *ep);
+static FAR struct usbdev_req_s *lpc43_epallocreq(FAR struct usbdev_ep_s *ep);
+static void lpc43_epfreereq(FAR struct usbdev_ep_s *ep,
+              FAR struct usbdev_req_s *);
+#ifdef CONFIG_USBDEV_DMA
+static void *lpc43_epallocbuffer(FAR struct usbdev_ep_s *ep, unsigned bytes);
+static void lpc43_epfreebuffer(FAR struct usbdev_ep_s *ep, FAR void *buf);
+#endif
+static int  lpc43_epsubmit(FAR struct usbdev_ep_s *ep,
+              struct usbdev_req_s *req);
+static int  lpc43_epcancel(FAR struct usbdev_ep_s *ep,
+              struct usbdev_req_s *req);
+static int  lpc43_epstall(FAR struct usbdev_ep_s *ep, bool resume);
+
+static FAR struct usbdev_ep_s *lpc43_allocep(FAR struct usbdev_s *dev,
+              uint8_t epno, bool in, uint8_t eptype);
+static void lpc43_freeep(FAR struct usbdev_s *dev, FAR struct usbdev_ep_s *ep);
+static int  lpc43_getframe(struct usbdev_s *dev);
+static int  lpc43_wakeup(struct usbdev_s *dev);
+static int  lpc43_selfpowered(struct usbdev_s *dev, bool selfpowered);
+static int  lpc43_pullup(struct usbdev_s *dev, bool enable);
+
+/*******************************************************************************
+ * Private Data
+ *******************************************************************************/
+
+/* Since there is only a single USB interface, all status information can be
+ * be simply retained in a single global instance.
+ */
+
+static struct lpc43_usbdev_s g_usbdev;
+
+static struct lpc43_dqh_s __attribute__((aligned(2048))) g_qh[LPC43_NPHYSENDPOINTS];
+static struct lpc43_dtd_s __attribute__((aligned(32)))   g_td[LPC43_NPHYSENDPOINTS];
+
+static const struct usbdev_epops_s g_epops =
+{
+  .configure   = lpc43_epconfigure,
+  .disable     = lpc43_epdisable,
+  .allocreq    = lpc43_epallocreq,
+  .freereq     = lpc43_epfreereq,
+#ifdef CONFIG_USBDEV_DMA
+  .allocbuffer = lpc43_epallocbuffer,
+  .freebuffer  = lpc43_epfreebuffer,
+#endif
+  .submit      = lpc43_epsubmit,
+  .cancel      = lpc43_epcancel,
+  .stall       = lpc43_epstall,
+};
+
+static const struct usbdev_ops_s g_devops =
+{
+  .allocep     = lpc43_allocep,
+  .freeep      = lpc43_freeep,
+  .getframe    = lpc43_getframe,
+  .wakeup      = lpc43_wakeup,
+  .selfpowered = lpc43_selfpowered,
+  .pullup      = lpc43_pullup,
+};
+
+/*******************************************************************************
+ * Public Data
+ *******************************************************************************/
+
+/*******************************************************************************
+ * Private Functions
+ *******************************************************************************/
+
+/*******************************************************************************
+ * Name: lpc43_getreg
+ *
+ * Description:
+ *   Get the contents of an LPC433x register
+ *
+ *******************************************************************************/
+
+#if defined(CONFIG_LPC43_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG)
+static uint32_t lpc43_getreg(uint32_t addr)
+{
+  static uint32_t prevaddr = 0;
+  static uint32_t preval = 0;
+  static uint32_t count = 0;
+
+  /* Read the value from the register */
+
+  uint32_t val = getreg32(addr);
+
+  /* Is this the same value that we read from the same registe last time?  Are
+   * we polling the register?  If so, suppress some of the output.
+   */
+
+  if (addr == prevaddr && val == preval)
+    {
+      if (count == 0xffffffff || ++count > 3)
+        {
+           if (count == 4)
+             {
+               lldbg("...\n");
+             }
+          return val;
+        }
+    }
+
+  /* No this is a new address or value */
+
+  else
+    {
+       /* Did we print "..." for the previous value? */
+
+       if (count > 3)
+         {
+           /* Yes.. then show how many times the value repeated */
+
+           lldbg("[repeats %d more times]\n", count-3);
+         }
+
+       /* Save the new address, value, and count */
+
+       prevaddr = addr;
+       preval   = val;
+       count    = 1;
+    }
+
+  /* Show the register value read */
+
+  lldbg("%08x->%08x\n", addr, val);
+  return val;
+}
+#endif
+
+/*******************************************************************************
+ * Name: lpc43_putreg
+ *
+ * Description:
+ *   Set the contents of an LPC433x register to a value
+ *
+ *******************************************************************************/
+
+#if defined(CONFIG_LPC43_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG)
+static void lpc43_putreg(uint32_t val, uint32_t addr)
+{
+  /* Show the register value being written */
+
+  lldbg("%08x<-%08x\n", addr, val);
+
+  /* Write the value */
+
+  putreg32(val, addr);
+}
+#endif
+
+/*******************************************************************************
+ * Name: lpc43_clrbits
+ *
+ * Description:
+ *   Clear bits in a register
+ *
+ *******************************************************************************/
+
+static inline void lpc43_clrbits(uint32_t mask, uint32_t addr)
+{
+  uint32_t reg = lpc43_getreg(addr);
+  reg &= ~mask;
+  lpc43_putreg(reg, addr);
+}
+
+/*******************************************************************************
+ * Name: lpc43_setbits
+ *
+ * Description:
+ *   Set bits in a register
+ *
+ *******************************************************************************/
+
+static inline void lpc43_setbits(uint32_t mask, uint32_t addr)
+{
+  uint32_t reg = lpc43_getreg(addr);
+  reg |= mask;
+  lpc43_putreg(reg, addr);
+}
+
+/*******************************************************************************
+ * Name: lpc43_chgbits
+ *
+ * Description:
+ *   Change bits in a register
+ *
+ *******************************************************************************/
+
+static inline void lpc43_chgbits(uint32_t mask, uint32_t val, uint32_t addr)
+{
+  uint32_t reg = lpc43_getreg(addr);
+  reg &= ~mask;
+  reg |= val;
+  lpc43_putreg(reg, addr);
+}
+
+/*******************************************************************************
+ * Name: lpc43_rqdequeue
+ *
+ * Description:
+ *   Remove a request from an endpoint request queue
+ *
+ *******************************************************************************/
+
+static FAR struct lpc43_req_s *lpc43_rqdequeue(FAR struct lpc43_ep_s *privep)
+{
+  FAR struct lpc43_req_s *ret = privep->head;
+
+  if (ret)
+    {
+      privep->head = ret->flink;
+      if (!privep->head)
+        {
+          privep->tail = NULL;
+        }
+
+      ret->flink = NULL;
+    }
+
+  return ret;
+}
+
+/*******************************************************************************
+ * Name: lpc43_rqenqueue
+ *
+ * Description:
+ *   Add a request from an endpoint request queue
+ *
+ *******************************************************************************/
+
+static bool lpc43_rqenqueue(FAR struct lpc43_ep_s *privep,
+                              FAR struct lpc43_req_s *req)
+{
+  bool is_empty = !privep->head;
+  
+  req->flink = NULL;
+  if (is_empty)
+    {
+      privep->head = req;
+      privep->tail = req;
+    }
+  else
+    {
+      privep->tail->flink = req;
+      privep->tail        = req;
+    }
+  return is_empty;
+}
+
+/*******************************************************************************
+ * Name: lpc43_writedtd
+ *
+ * Description:
+ *   Initialise a DTD to transfer the data
+ *
+ *******************************************************************************/
+
+static inline void lpc43_writedtd(struct lpc43_dtd_s *dtd, const uint8_t *data, uint32_t nbytes)
+{
+  dtd->nextdesc  = DTD_NEXTDESC_INVALID;
+  dtd->config    = DTD_CONFIG_LENGTH(nbytes) | DTD_CONFIG_IOC | DTD_CONFIG_ACTIVE;
+  dtd->buffer0   = ((uint32_t) data);
+  dtd->buffer1   = (((uint32_t) data) + 0x1000) & 0xfffff000;
+  dtd->buffer2   = (((uint32_t) data) + 0x2000) & 0xfffff000;
+  dtd->buffer3   = (((uint32_t) data) + 0x3000) & 0xfffff000;
+  dtd->buffer4   = (((uint32_t) data) + 0x4000) & 0xfffff000;
+  dtd->xfer_len  = nbytes;
+}
+
+/*******************************************************************************
+ * Name: lpc43_queuedtd
+ *
+ * Description:
+ *   Add the DTD to the device list
+ *
+ *******************************************************************************/
+
+static void lpc43_queuedtd(uint8_t epphy, struct lpc43_dtd_s *dtd)
+{
+  /* Queue the DTD onto the Endpoint */
+  /* NOTE - this only works when no DTD is currently queued */
+
+  g_qh[epphy].overlay.nextdesc = (uint32_t) dtd;
+  g_qh[epphy].overlay.config  &= ~(DTD_CONFIG_ACTIVE | DTD_CONFIG_HALTED);
+
+  uint32_t bit = LPC43_ENDPTMASK(epphy);
+
+  lpc43_setbits (bit, LPC43_USBDEV_ENDPTPRIME);
+    
+  while (lpc43_getreg (LPC43_USBDEV_ENDPTPRIME) & bit)
+    ;
+}
+
+/*******************************************************************************
+ * Name: lpc43_ep0xfer
+ *
+ * Description:
+ *   Schedule a short transfer for Endpoint 0 (IN or OUT)
+ *
+ *******************************************************************************/
+
+static inline void lpc43_ep0xfer(uint8_t epphy, uint8_t *buf, uint32_t nbytes)
+{
+  struct lpc43_dtd_s *dtd = &g_td[epphy];
+
+  lpc43_writedtd(dtd, buf, nbytes);
+    
+  lpc43_queuedtd(epphy, dtd);
+}
+
+/*******************************************************************************
+ * Name: lpc43_readsetup
+ *
+ * Description:
+ *   Read a Setup packet from the DTD.
+ *
+ *******************************************************************************/
+static void lpc43_readsetup(uint8_t epphy, struct usb_ctrlreq_s *ctrl)
+{
+    struct lpc43_dqh_s *dqh = &g_qh[epphy];
+    int i;
+
+    do {
+    /* Set the trip wire */
+    lpc43_setbits(USBDEV_USBCMD_SUTW, LPC43_USBDEV_USBCMD);
+
+    /* copy the request... */
+    for (i = 0; i < 8; i++)
+        ((uint8_t *) ctrl)[i] = ((uint8_t *) dqh->setup)[i];
+    
+    } while (!(lpc43_getreg(LPC43_USBDEV_USBCMD) & USBDEV_USBCMD_SUTW));
+    
+    /* Clear the trip wire */
+    lpc43_clrbits(USBDEV_USBCMD_SUTW, LPC43_USBDEV_USBCMD);
+
+    /* Clear the Setup Interrupt */
+    lpc43_putreg (LPC43_ENDPTMASK(LPC43_EP0_OUT), LPC43_USBDEV_ENDPTSETUPSTAT);
+}
+
+/*******************************************************************************
+ * Name: lpc43_set_address
+ *
+ * Description:
+ *   Set the devices USB address
+ *
+ *******************************************************************************/
+
+static inline void lpc43_set_address(struct lpc43_usbdev_s *priv, uint16_t address)
+{
+  priv->paddr    = address;
+  priv->paddrset = address != 0;
+
+  lpc43_chgbits(USBDEV_DEVICEADDR_MASK, priv->paddr << USBDEV_DEVICEADDR_SHIFT, 
+                LPC43_USBDEV_DEVICEADDR);
+}
+
+/*******************************************************************************
+ * Name: lpc43_flushep
+ *
+ * Description:
+ *   Flush any primed descriptors from this ep
+ *
+ *******************************************************************************/
+
+static void lpc43_flushep(struct lpc43_ep_s *privep)
+{
+  uint32_t mask = LPC43_ENDPTMASK(privep->epphy);
+  do
+    {
+      lpc43_putreg (mask, LPC43_USBDEV_ENDPTFLUSH);
+      while ((lpc43_getreg(LPC43_USBDEV_ENDPTFLUSH) & mask) != 0)
+      ;
+    }
+  while ((lpc43_getreg(LPC43_USBDEV_ENDPTSTATUS) & mask) != 0);
+}
+
+
+/*******************************************************************************
+ * Name: lpc43_progressep
+ *
+ * Description:
+ *   Progress the Endpoint by priming the first request into the queue head
+ *
+ *******************************************************************************/
+
+static int lpc43_progressep(struct lpc43_ep_s *privep)
+{
+  struct lpc43_dtd_s *dtd = &g_td[privep->epphy];
+  struct lpc43_req_s *privreq;
+
+  /* Check the request from the head of the endpoint request queue */
+
+  privreq = lpc43_rqpeek(privep);
+  if (!privreq)
+    {
+      usbtrace(TRACE_INTDECODE(LPC43_TRACEINTID_EPINQEMPTY), 0);
+      return OK;
+    }
+
+  /* Ignore any attempt to send a zero length packet */
+
+  if (privreq->req.len == 0)
+    {
+    /* If the class driver is responding to a setup packet, then wait for the 
+     * host to illicit thr response */
+
+    if (privep->epphy == LPC43_EP0_IN && privep->dev->ep0state == EP0STATE_SETUP_OUT)
+      lpc43_ep0state (privep->dev, EP0STATE_WAIT_NAK_IN);
+    else
+      {
+        if (LPC43_EPPHYIN(privep->epphy))
+        usbtrace(TRACE_DEVERROR(LPC43_TRACEERR_EPINNULLPACKET), 0);
+        else
+        usbtrace(TRACE_DEVERROR(LPC43_TRACEERR_EPOUTNULLPACKET), 0);
+      }
+      
+      lpc43_reqcomplete(privep, lpc43_rqdequeue(privep), OK);
+      return OK;
+    }
+
+  if (privep->epphy == LPC43_EP0_IN)
+    lpc43_ep0state (privep->dev,  EP0STATE_DATA_IN);
+  else if (privep->epphy == LPC43_EP0_OUT)
+    lpc43_ep0state (privep->dev, EP0STATE_DATA_OUT);
+
+  int bytesleft = privreq->req.len - privreq->req.xfrd;
+
+  if (LPC43_EPPHYIN(privep->epphy))
+    usbtrace(TRACE_WRITE(privep->epphy), privreq->req.xfrd);
+  else
+    usbtrace(TRACE_READ(privep->epphy), privreq->req.xfrd);
+
+  /* Initialise the DTD to transfer the next chunk */
+
+  lpc43_writedtd (dtd, privreq->req.buf + privreq->req.xfrd, bytesleft);
+
+  /* then queue onto the DQH */
+  lpc43_queuedtd(privep->epphy, dtd);
+
+  return OK;
+}
+
+/*******************************************************************************
+ * Name: lpc43_abortrequest
+ *
+ * Description:
+ *   Discard a request
+ *
+ *******************************************************************************/
+
+static inline void lpc43_abortrequest(struct lpc43_ep_s *privep,
+                                      struct lpc43_req_s *privreq,
+                                      int16_t result)
+{
+  usbtrace(TRACE_DEVERROR(LPC43_TRACEERR_REQABORTED), (uint16_t)privep->epphy);
+
+  /* Save the result in the request structure */
+
+  privreq->req.result = result;
+
+  /* Callback to the request completion handler */
+
+  privreq->req.callback(&privep->ep, &privreq->req);
+}
+
+/*******************************************************************************
+ * Name: lpc43_reqcomplete
+ *
+ * Description:
+ *   Handle termination of the request at the head of the endpoint request queue.
+ *
+ *******************************************************************************/
+
+static void lpc43_reqcomplete(struct lpc43_ep_s *privep,
+                              struct lpc43_req_s *privreq, int16_t result)
+{
+  /* If endpoint 0, temporarily reflect the state of protocol stalled
+   * in the callback.
+   */
+
+  bool stalled = privep->stalled;
+  if (privep->epphy == LPC43_EP0_IN)
+    privep->stalled = privep->dev->stalled;
+
+  /* Save the result in the request structure */
+
+  privreq->req.result = result;
+
+  /* Callback to the request completion handler */
+
+  privreq->req.callback(&privep->ep, &privreq->req);
+
+  /* Restore the stalled indication */
+
+  privep->stalled = stalled;
+}
+
+/*******************************************************************************
+ * Name: lpc43_cancelrequests
+ *
+ * Description:
+ *   Cancel all pending requests for an endpoint
+ *
+ *******************************************************************************/
+
+static void lpc43_cancelrequests(struct lpc43_ep_s *privep, int16_t status)
+{
+  if (!lpc43_rqempty(privep))
+      lpc43_flushep(privep);
+
+  while (!lpc43_rqempty(privep))
+    {
+      // FIXME: the entry at the head should be sync'd with the DTD
+      // FIXME: only report the error status if the transfer hasn't completed
+      usbtrace(TRACE_COMPLETE(privep->epphy),
+               (lpc43_rqpeek(privep))->req.xfrd);
+      lpc43_reqcomplete(privep, lpc43_rqdequeue(privep), status);
+    }
+}
+
+/*******************************************************************************
+ * Name: lpc43_epfindbyaddr
+ *
+ * Description:
+ *   Find the physical endpoint structure corresponding to a logic endpoint
+ *   address
+ *
+ *******************************************************************************/
+
+static struct lpc43_ep_s *lpc43_epfindbyaddr(struct lpc43_usbdev_s *priv,
+                         uint16_t eplog)
+{
+  struct lpc43_ep_s *privep;
+  int i;
+
+  /* Endpoint zero is a special case */
+
+  if (USB_EPNO(eplog) == 0)
+    {
+      return &priv->eplist[0];
+    }
+
+  /* Handle the remaining */
+
+  for (i = 1; i < LPC43_NPHYSENDPOINTS; i++)
+    {
+      privep = &priv->eplist[i];
+
+      /* Same logical endpoint number? (includes direction bit) */
+
+      if (eplog == privep->ep.eplog)
+        {
+          /* Return endpoint found */
+
+          return privep;
+        }
+    }
+
+  /* Return endpoint not found */
+
+  return NULL;
+}
+
+/*******************************************************************************
+ * Name: lpc43_dispatchrequest
+ *
+ * Description:
+ *   Provide unhandled setup actions to the class driver. This is logically part
+ *   of the USB interrupt handler.
+ *
+ *******************************************************************************/
+
+static void lpc43_dispatchrequest(struct lpc43_usbdev_s *priv,
+                                    const struct usb_ctrlreq_s *ctrl)
+{
+  int ret = -EIO;
+
+  usbtrace(TRACE_INTDECODE(LPC43_TRACEINTID_DISPATCH), 0);
+  if (priv->driver)
+    {
+      /* Forward to the control request to the class driver implementation */
+
+      ret = CLASS_SETUP(priv->driver, &priv->usbdev, ctrl, NULL, 0);
+    }
+
+  if (ret < 0)
+    {
+      /* Stall on failure */
+
+      usbtrace(TRACE_DEVERROR(LPC43_TRACEERR_DISPATCHSTALL), 0);
+      priv->stalled = true;
+    }
+}
+
+/*******************************************************************************
+ * Name: lpc43_ep0configure
+ *
+ * Description:
+ *   Reset Usb engine
+ *
+ *******************************************************************************/
+
+static void lpc43_ep0configure(struct lpc43_usbdev_s *priv)
+{
+  /* Enable ep0 IN and ep0 OUT */
+  g_qh[LPC43_EP0_OUT].capability = (DQH_CAPABILITY_MAX_PACKET(CONFIG_USBDEV_EP0_MAXSIZE) |
+                      DQH_CAPABILITY_IOS |
+                      DQH_CAPABILITY_ZLT);
+
+  g_qh[LPC43_EP0_IN ].capability = (DQH_CAPABILITY_MAX_PACKET(CONFIG_USBDEV_EP0_MAXSIZE) |
+                      DQH_CAPABILITY_IOS |
+                      DQH_CAPABILITY_ZLT);
+  
+  g_qh[LPC43_EP0_OUT].currdesc = DTD_NEXTDESC_INVALID;
+  g_qh[LPC43_EP0_IN ].currdesc = DTD_NEXTDESC_INVALID;
+  
+  /* Enable EP0 */
+  lpc43_setbits (USBDEV_ENDPTCTRL0_RXE | USBDEV_ENDPTCTRL0_TXE, LPC43_USBDEV_ENDPTCTRL0);
+}
+
+/*******************************************************************************
+ * Name: lpc43_usbreset
+ *
+ * Description:
+ *   Reset Usb engine
+ *
+ *******************************************************************************/
+
+static void lpc43_usbreset(struct lpc43_usbdev_s *priv)
+{
+  int epphy;
+
+  /* Disable all endpoints */
+
+  lpc43_clrbits (USBDEV_ENDPTCTRL_RXE | USBDEV_ENDPTCTRL_TXE, LPC43_USBDEV_ENDPTCTRL0);
+  lpc43_clrbits (USBDEV_ENDPTCTRL_RXE | USBDEV_ENDPTCTRL_TXE, LPC43_USBDEV_ENDPTCTRL1);
+  lpc43_clrbits (USBDEV_ENDPTCTRL_RXE | USBDEV_ENDPTCTRL_TXE, LPC43_USBDEV_ENDPTCTRL2);
+  lpc43_clrbits (USBDEV_ENDPTCTRL_RXE | USBDEV_ENDPTCTRL_TXE, LPC43_USBDEV_ENDPTCTRL3);
+
+  /* Clear all pending interrupts */
+
+  lpc43_putreg (lpc43_getreg(LPC43_USBDEV_ENDPTNAK),       LPC43_USBDEV_ENDPTNAK);
+  lpc43_putreg (lpc43_getreg(LPC43_USBDEV_ENDPTSETUPSTAT), LPC43_USBDEV_ENDPTSETUPSTAT);
+  lpc43_putreg (lpc43_getreg(LPC43_USBDEV_ENDPTCOMPLETE),  LPC43_USBDEV_ENDPTCOMPLETE);
+
+  /* Wait for all prime operations to have completed and then flush all DTDs */
+  while (lpc43_getreg (LPC43_USBDEV_ENDPTPRIME) != 0)
+    ;
+  lpc43_putreg (LPC43_ENDPTMASK_ALL, LPC43_USBDEV_ENDPTFLUSH);
+  while (lpc43_getreg (LPC43_USBDEV_ENDPTFLUSH))
+    ;
+
+  /* Reset endpoints */
+  for (epphy = 0; epphy < LPC43_NPHYSENDPOINTS; epphy++)
+    {
+      struct lpc43_ep_s *privep = &priv->eplist[epphy];
+
+      lpc43_cancelrequests (privep, -ESHUTDOWN);
+
+      /* Reset endpoint status */
+      privep->stalled = false;
+    }
+
+  /* Tell the class driver that we are disconnected. The class 
+   * driver should then accept any new configurations. */
+
+  if (priv->driver)
+      CLASS_DISCONNECT(priv->driver, &priv->usbdev);
+
+  /* Set the interrupt Threshold control interval to 0 */
+  lpc43_chgbits(USBDEV_USBCMD_ITC_MASK, USBDEV_USBCMD_ITCIMME, LPC43_USBDEV_USBCMD);
+
+  /* Zero out the Endpoint queue heads */
+  memset ((void *) g_qh, 0, sizeof (g_qh));
+  memset ((void *) g_td, 0, sizeof (g_td));
+
+  /* Set USB address to 0 */
+  lpc43_set_address (priv, 0);
+
+  /* Initialise the Enpoint List Address */
+  lpc43_putreg ((uint32_t)g_qh, LPC43_USBDEV_ENDPOINTLIST);
+
+  /* EndPoint 0 initialization */
+  lpc43_ep0configure(priv);
+
+  /* Enable Device interrupts */
+  lpc43_putreg(USB_FRAME_INT | USB_ERROR_INT | 
+         USBDEV_USBINTR_NAKE | USBDEV_USBINTR_SLE | USBDEV_USBINTR_URE | USBDEV_USBINTR_PCE | USBDEV_USBINTR_UE,
+         LPC43_USBDEV_USBINTR);
+}
+
+/*******************************************************************************
+ * Name: lpc43_setstate
+ *
+ * Description:
+ *   Sets the EP0 state and manages the NAK interrupts
+ *
+ *******************************************************************************/
+
+static inline void lpc43_ep0state(struct lpc43_usbdev_s *priv, uint16_t state)
+{
+  priv->ep0state = state;
+  
+  switch (state)
+    {
+    case EP0STATE_WAIT_NAK_IN:
+      lpc43_putreg (LPC43_ENDPTMASK(LPC43_EP0_IN), LPC43_USBDEV_ENDPTNAKEN);
+      break;
+    case EP0STATE_WAIT_NAK_OUT:
+      lpc43_putreg (LPC43_ENDPTMASK(LPC43_EP0_OUT), LPC43_USBDEV_ENDPTNAKEN);
+      break;
+    default:
+      lpc43_putreg(0, LPC43_USBDEV_ENDPTNAKEN);
+      break;
+    }
+}
+
+/*******************************************************************************
+ * Name: lpc43_ep0setup
+ *
+ * Description:
+ *   USB Ctrl EP Setup Event. This is logically part of the USB interrupt
+ *   handler.  This event occurs when a setup packet is receive on EP0 OUT.
+ *
+ *******************************************************************************/
+
+static inline void lpc43_ep0setup(struct lpc43_usbdev_s *priv)
+{
+  struct lpc43_ep_s *privep;
+  struct usb_ctrlreq_s ctrl;
+  uint16_t value;
+  uint16_t index;
+  uint16_t len;
+
+  /* Terminate any pending requests - since all DTDs will have been retired 
+   * because of the setup packet */
+
+  lpc43_cancelrequests(&priv->eplist[LPC43_EP0_OUT], -EPROTO);
+  lpc43_cancelrequests(&priv->eplist[LPC43_EP0_IN],  -EPROTO);
+
+  /* Assume NOT stalled */
+
+  priv->eplist[LPC43_EP0_OUT].stalled = false;
+  priv->eplist[LPC43_EP0_IN].stalled = false;
+  priv->stalled = false;
+
+  /* Read EP0 setup data */
+  lpc43_readsetup(LPC43_EP0_OUT, &ctrl);
+
+  /* Starting a control request - update state */
+  lpc43_ep0state (priv, (ctrl.type & USB_REQ_DIR_IN) ? EP0STATE_SETUP_IN : EP0STATE_SETUP_OUT);
+
+  /* And extract the little-endian 16-bit values to host order */
+  value = GETUINT16(ctrl.value);
+  index = GETUINT16(ctrl.index);
+  len   = GETUINT16(ctrl.len);
+
+  ullvdbg("type=%02x req=%02x value=%04x index=%04x len=%04x\n",
+          ctrl.type, ctrl.req, value, index, len);
+
+  /* Dispatch any non-standard requests */
+  if ((ctrl.type & USB_REQ_TYPE_MASK) != USB_REQ_TYPE_STANDARD)
+    lpc43_dispatchrequest(priv, &ctrl);
+  else
+    {
+    /* Handle standard request.  Pick off the things of interest to the USB
+     * device controller driver; pass what is left to the class driver */
+    switch (ctrl.req)
+      {
+      case USB_REQ_GETSTATUS:
+        {
+          /* type:  device-to-host; recipient = device, interface, endpoint
+           * value: 0
+           * index: zero interface endpoint
+           * len:   2; data = status
+           */
+  
+          usbtrace(TRACE_INTDECODE(LPC43_TRACEINTID_GETSTATUS), 0);
+          if (!priv->paddrset || len != 2 ||
+              (ctrl.type & USB_REQ_DIR_IN) == 0 || value != 0)
+            {
+              priv->stalled = true;
+            }
+          else
+            {
+              switch (ctrl.type & USB_REQ_RECIPIENT_MASK)
+                {
+                case USB_REQ_RECIPIENT_ENDPOINT:
+                  {
+                    usbtrace(TRACE_INTDECODE(LPC43_TRACEINTID_EPGETSTATUS), 0);
+                    privep = lpc43_epfindbyaddr(priv, index);
+                    if (!privep)
+                      {
+                        usbtrace(TRACE_DEVERROR(LPC43_TRACEERR_BADEPGETSTATUS), 0);
+                        priv->stalled = true;
+                      }
+                    else
+                      {
+                        if (privep->stalled)
+                          priv->ep0buf[0] = 1; /* Stalled */
+                        else
+                          priv->ep0buf[0] = 0; /* Not stalled */
+                        priv->ep0buf[1] = 0;
+  
+                        lpc43_ep0xfer (LPC43_EP0_IN, priv->ep0buf, 2);
+                        lpc43_ep0state (priv, EP0STATE_SHORTWRITE);
+                      }
+                    }
+                  break;
+  
+                case USB_REQ_RECIPIENT_DEVICE:
+                  {
+                    if (index == 0)
+                      {
+                        usbtrace(TRACE_INTDECODE(LPC43_TRACEINTID_DEVGETSTATUS), 0);
+  
+                        /* Features:  Remote Wakeup=YES; selfpowered=? */
+  
+                        priv->ep0buf[0] = (priv->selfpowered << USB_FEATURE_SELFPOWERED) |
+                              (1 << USB_FEATURE_REMOTEWAKEUP);
+                        priv->ep0buf[1] = 0;
+
+                        lpc43_ep0xfer(LPC43_EP0_IN, priv->ep0buf, 2);
+                        lpc43_ep0state (priv, EP0STATE_SHORTWRITE);
+                      }
+                    else
+                      {
+                        usbtrace(TRACE_DEVERROR(LPC43_TRACEERR_BADDEVGETSTATUS), 0);
+                        priv->stalled = true;
+                      }
+                  }
+                  break;
+  
+                case USB_REQ_RECIPIENT_INTERFACE:
+                  {
+                    usbtrace(TRACE_INTDECODE(LPC43_TRACEINTID_IFGETSTATUS), 0);
+                    priv->ep0buf[0] = 0;
+                    priv->ep0buf[1] = 0;
+
+                    lpc43_ep0xfer(LPC43_EP0_IN, priv->ep0buf, 2);
+                    lpc43_ep0state (priv, EP0STATE_SHORTWRITE);
+                  }
+                  break;
+  
+                default:
+                  {
+                    usbtrace(TRACE_DEVERROR(LPC43_TRACEERR_BADGETSTATUS), 0);
+                    priv->stalled = true;
+                  }
+                  break;
+                }
+            }
+        }
+        break;
+  
+      case USB_REQ_CLEARFEATURE:
+        {
+          /* type:  host-to-device; recipient = device, interface or endpoint
+           * value: feature selector
+           * index: zero interface endpoint;
+           * len:   zero, data = none
+           */
+  
+          usbtrace(TRACE_INTDECODE(LPC43_TRACEINTID_CLEARFEATURE), 0);
+          if ((ctrl.type & USB_REQ_RECIPIENT_MASK) != USB_REQ_RECIPIENT_ENDPOINT)
+            {
+              lpc43_dispatchrequest(priv, &ctrl);
+            }
+          else if (priv->paddrset != 0 && value == USB_FEATURE_ENDPOINTHALT && len == 0 &&
+                   (privep = lpc43_epfindbyaddr(priv, index)) != NULL)
+            {
+              lpc43_epstall(&privep->ep, true);
+              lpc43_ep0state (priv, EP0STATE_WAIT_NAK_IN);
+            }
+          else
+            {
+              usbtrace(TRACE_DEVERROR(LPC43_TRACEERR_BADCLEARFEATURE), 0);
+              priv->stalled = true;
+            }
+        }
+        break;
+  
+      case USB_REQ_SETFEATURE:
+        {
+          /* type:  host-to-device; recipient = device, interface, endpoint
+           * value: feature selector
+           * index: zero interface endpoint;
+           * len:   0; data = none
+           */
+  
+          usbtrace(TRACE_INTDECODE(LPC43_TRACEINTID_SETFEATURE), 0);
+          if (((ctrl.type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE) &&
+              value == USB_FEATURE_TESTMODE)
+            {
+              ullvdbg("test mode: %d\n", index);
+            }
+          else if ((ctrl.type & USB_REQ_RECIPIENT_MASK) != USB_REQ_RECIPIENT_ENDPOINT)
+            {
+              lpc43_dispatchrequest(priv, &ctrl);
+            }
+          else if (priv->paddrset != 0 && value == USB_FEATURE_ENDPOINTHALT && len == 0 &&
+                   (privep = lpc43_epfindbyaddr(priv, index)) != NULL)
+            {
+              lpc43_epstall(&privep->ep, false);
+              lpc43_ep0state (priv, EP0STATE_WAIT_NAK_IN);
+            }
+          else
+            {
+              usbtrace(TRACE_DEVERROR(LPC43_TRACEERR_BADSETFEATURE), 0);
+              priv->stalled = true;
+            }
+        }
+        break;
+  
+      case USB_REQ_SETADDRESS:
+        {
+          /* type:  host-to-device; recipient = device
+           * value: device address
+           * index: 0
+           * len:   0; data = none
+           */
+          usbtrace(TRACE_INTDECODE(LPC43_TRACEINTID_EP0SETUPSETADDRESS), value);
+          if ((ctrl.type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE &&
+              index  == 0 && len == 0 && value < 128)
+            {
+              /* Save the address.  We cannot actually change to the next address until
+               * the completion of the status phase. */
+  
+              priv->paddr = ctrl.value[0];
+              priv->paddrset = false;
+              lpc43_ep0state (priv, EP0STATE_WAIT_NAK_IN);
+            }
+          else
+            {
+              usbtrace(TRACE_DEVERROR(LPC43_TRACEERR_BADSETADDRESS), 0);
+              priv->stalled = true;
+            }
+        }
+        break;
+  
+      case USB_REQ_GETDESCRIPTOR:
+        /* type:  device-to-host; recipient = device
+         * value: descriptor type and index
+         * index: 0 or language ID;
+         * len:   descriptor len; data = descriptor
+         */
+      case USB_REQ_SETDESCRIPTOR:
+        /* type:  host-to-device; recipient = device
+         * value: descriptor type and index
+         * index: 0 or language ID;
+         * len:   descriptor len; data = descriptor
+         */
+        {
+          usbtrace(TRACE_INTDECODE(LPC43_TRACEINTID_GETSETDESC), 0);
+          if ((ctrl.type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE)
+            {
+              lpc43_dispatchrequest(priv, &ctrl);
+            }
+          else
+            {
+              usbtrace(TRACE_DEVERROR(LPC43_TRACEERR_BADGETSETDESC), 0);
+              priv->stalled = true;
+            }
+        }
+        break;
+  
+      case USB_REQ_GETCONFIGURATION:
+        /* type:  device-to-host; recipient = device
+         * value: 0;
+         * index: 0;
+         * len:   1; data = configuration value
+         */
+        {
+          usbtrace(TRACE_INTDECODE(LPC43_TRACEINTID_GETCONFIG), 0);
+          if (priv->paddrset && (ctrl.type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE &&
+              value == 0 && index == 0 && len == 1)
+            {
+              lpc43_dispatchrequest(priv, &ctrl);
+            }
+          else
+            {
+              usbtrace(TRACE_DEVERROR(LPC43_TRACEERR_BADGETCONFIG), 0);
+              priv->stalled = true;
+            }
+        }
+        break;
+  
+      case USB_REQ_SETCONFIGURATION:
+        /* type:  host-to-device; recipient = device
+         * value: configuration value
+         * index: 0;
+         * len:   0; data = none
+         */
+        {
+          usbtrace(TRACE_INTDECODE(LPC43_TRACEINTID_SETCONFIG), 0);
+          if ((ctrl.type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE &&
+              index == 0 && len == 0)
+            {
+              lpc43_dispatchrequest(priv, &ctrl);
+            }
+          else
+            {
+              usbtrace(TRACE_DEVERROR(LPC43_TRACEERR_BADSETCONFIG), 0);
+              priv->stalled = true;
+            }
+        }
+        break;
+  
+      case USB_REQ_GETINTERFACE:
+        /* type:  device-to-host; recipient = interface
+         * value: 0
+         * index: interface;
+         * len:   1; data = alt interface
+         */
+      case USB_REQ_SETINTERFACE:
+        /* type:  host-to-device; recipient = interface
+         * value: alternate setting
+         * index: interface;
+         * len:   0; data = none
+         */
+        {
+          usbtrace(TRACE_INTDECODE(LPC43_TRACEINTID_GETSETIF), 0);
+          lpc43_dispatchrequest(priv, &ctrl);
+        }
+        break;
+  
+      case USB_REQ_SYNCHFRAME:
+        /* type:  device-to-host; recipient = endpoint
+         * value: 0
+         * index: endpoint;
+         * len:   2; data = frame number
+         */
+        {
+          usbtrace(TRACE_INTDECODE(LPC43_TRACEINTID_SYNCHFRAME), 0);
+        }
+        break;
+  
+      default:
+        {
+          usbtrace(TRACE_DEVERROR(LPC43_TRACEERR_INVALIDCTRLREQ), 0);
+          priv->stalled = true;
+        }
+        break;
+      }
+  }
+
+  if (priv->stalled)
+    {
+      usbtrace(TRACE_DEVERROR(LPC43_TRACEERR_EP0SETUPSTALLED), priv->ep0state);
+      lpc43_epstall(&priv->eplist[LPC43_EP0_IN].ep, false);
+      lpc43_epstall(&priv->eplist[LPC43_EP0_OUT].ep, false);
+    }
+}
+
+/*******************************************************************************
+ * Name: lpc43_ep0complete
+ *
+ * Description:
+ *   Transfer complete handler for Endpoint 0
+ *
+ *******************************************************************************/
+
+static void lpc43_ep0complete(struct lpc43_usbdev_s *priv, uint8_t epphy)
+{
+  struct lpc43_ep_s *privep = &priv->eplist[epphy];
+
+  usbtrace(TRACE_INTDECODE(LPC43_TRACEINTID_EP0COMPLETE), (uint16_t)priv->ep0state);
+  
+  switch (priv->ep0state)
+    {
+    case EP0STATE_DATA_IN:
+      if (lpc43_rqempty(privep))
+        return;
+
+      if (lpc43_epcomplete (priv, epphy))
+        lpc43_ep0state (priv, EP0STATE_WAIT_NAK_OUT);
+      break;
+
+    case EP0STATE_DATA_OUT:
+      if (lpc43_rqempty(privep))
+    return;
+    
+      if (lpc43_epcomplete (priv, epphy))
+        lpc43_ep0state (priv, EP0STATE_WAIT_NAK_IN);
+      break;
+    
+    case EP0STATE_SHORTWRITE:
+      lpc43_ep0state (priv, EP0STATE_WAIT_NAK_OUT);
+      break;
+    
+    case EP0STATE_WAIT_STATUS_IN:
+      lpc43_ep0state (priv, EP0STATE_IDLE);
+
+      /* If we've received a SETADDRESS packet, then we set the address
+       * now that the status phase has completed */
+      if (! priv->paddrset && priv->paddr != 0)
+        {
+          usbtrace(TRACE_INTDECODE(LPC43_TRACEINTID_EP0INSETADDRESS), (uint16_t)priv->paddr);
+          lpc43_set_address (priv, priv->paddr);
+        }
+      break;
+
+    case EP0STATE_WAIT_STATUS_OUT:
+      lpc43_ep0state (priv, EP0STATE_IDLE);
+      break;
+
+    default:
+#ifdef CONFIG_DEBUG
+      DEBUGASSERT(priv->ep0state != EP0STATE_DATA_IN &&
+          priv->ep0state != EP0STATE_DATA_OUT        &&
+          priv->ep0state != EP0STATE_SHORTWRITE      &&
+          priv->ep0state != EP0STATE_WAIT_STATUS_IN  &&
+          priv->ep0state != EP0STATE_WAIT_STATUS_OUT);
+#endif
+      priv->stalled = true;
+      break;
+    }
+
+  if (priv->stalled)
+    {
+      usbtrace(TRACE_DEVERROR(LPC43_TRACEERR_EP0SETUPSTALLED), priv->ep0state);
+      lpc43_epstall(&priv->eplist[LPC43_EP0_IN].ep, false);
+      lpc43_epstall(&priv->eplist[LPC43_EP0_OUT].ep, false);
+    }
+}
+
+/*******************************************************************************
+ * Name: lpc43_ep0nak
+ *
+ * Description:
+ *   Handle a NAK interrupt on EP0
+ *
+ *******************************************************************************/
+
+static void lpc43_ep0nak(struct lpc43_usbdev_s *priv, uint8_t epphy)
+{
+  usbtrace(TRACE_INTDECODE(LPC43_TRACEINTID_EP0NAK), (uint16_t)priv->ep0state);
+
+  switch (priv->ep0state)
+    {
+    case EP0STATE_WAIT_NAK_IN:
+      lpc43_ep0xfer (LPC43_EP0_IN, NULL, 0);
+      lpc43_ep0state (priv, EP0STATE_WAIT_STATUS_IN);
+      break;
+    case EP0STATE_WAIT_NAK_OUT:
+      lpc43_ep0xfer (LPC43_EP0_OUT, NULL, 0);
+      lpc43_ep0state (priv, EP0STATE_WAIT_STATUS_OUT);
+      break;
+    default:
+#ifdef CONFIG_DEBUG
+      DEBUGASSERT(priv->ep0state != EP0STATE_WAIT_NAK_IN &&
+          priv->ep0state != EP0STATE_WAIT_NAK_OUT);
+#endif
+      priv->stalled = true;
+      break;
+    }
+
+  if (priv->stalled)
+    {
+      usbtrace(TRACE_DEVERROR(LPC43_TRACEERR_EP0SETUPSTALLED), priv->ep0state);
+      lpc43_epstall(&priv->eplist[LPC43_EP0_IN].ep, false);
+      lpc43_epstall(&priv->eplist[LPC43_EP0_OUT].ep, false);
+    }
+}
+
+/*******************************************************************************
+ * Name: lpc43_epcomplete
+ *
+ * Description:
+ *   Transfer complete handler for Endpoints other than 0
+ *   returns whether the request at the head has completed
+ *
+ *******************************************************************************/
+
+bool lpc43_epcomplete(struct lpc43_usbdev_s *priv, uint8_t epphy)
+{
+  struct lpc43_ep_s  *privep  = &priv->eplist[epphy];
+  struct lpc43_req_s *privreq = privep->head;
+  struct lpc43_dtd_s *dtd     = &g_td[epphy];
+
+  if (privreq == NULL)        /* This shouldn't really happen */
+  {
+    if (LPC43_EPPHYOUT(privep->epphy))
+      usbtrace(TRACE_INTDECODE(LPC43_TRACEINTID_EPINQEMPTY), 0);
+    else
+      usbtrace(TRACE_INTDECODE(LPC43_TRACEINTID_EPOUTQEMPTY), 0);
+    return true;
+  }
+    
+  int xfrd = dtd->xfer_len - (dtd->config >> 16);
+    
+  privreq->req.xfrd += xfrd;
+
+  bool complete = true;
+  if (LPC43_EPPHYOUT(privep->epphy))
+    {
+      /* read(OUT) completes when request filled, or a short transfer is received */
+
+      usbtrace(TRACE_INTDECODE(LPC43_TRACEINTID_EPIN), complete);
+    }
+  else
+    {
+      /* write(IN) completes when request finished, unless we need to terminate with a ZLP */
+
+      bool need_zlp = (xfrd == privep->ep.maxpacket) && ((privreq->req.flags & USBDEV_REQFLAGS_NULLPKT) != 0);
+
+      complete = (privreq->req.xfrd >= privreq->req.len && !need_zlp);
+
+      usbtrace(TRACE_INTDECODE(LPC43_TRACEINTID_EPOUT), complete);
+    }
+
+  /* If the transfer is complete, then dequeue and progress any further queued requests */
+
+  if (complete)
+    {
+      privreq = lpc43_rqdequeue (privep);
+    }
+    
+  if (!lpc43_rqempty(privep))
+    {
+      lpc43_progressep(privep);
+    }
+
+  /* Now it's safe to call the completion callback as it may well submit a new request */
+
+  if (complete)
+    {
+      usbtrace(TRACE_COMPLETE(privep->epphy), privreq->req.xfrd);
+      lpc43_reqcomplete(privep, privreq, OK);
+    }
+
+  return complete;
+}
+
+
+/*******************************************************************************
+ * Name: lpc43_usbinterrupt
+ *
+ * Description:
+ *   USB interrupt handler
+ *
+ *******************************************************************************/
+
+static int lpc43_usbinterrupt(int irq, FAR void *context)
+{
+  struct lpc43_usbdev_s *priv = &g_usbdev;
+  uint32_t disr, portsc1, n;
+
+  usbtrace(TRACE_INTENTRY(LPC43_TRACEINTID_USB), 0);
+
+  /* Read the interrupts and then clear them */
+  disr = lpc43_getreg(LPC43_USBDEV_USBSTS);
+  lpc43_putreg(disr, LPC43_USBDEV_USBSTS);
+
+  if (disr & USBDEV_USBSTS_URI)
+    {
+      usbtrace(TRACE_INTDECODE(LPC43_TRACEINTID_DEVRESET),0);
+
+      lpc43_usbreset(priv);
+
+      usbtrace(TRACE_INTEXIT(LPC43_TRACEINTID_USB), 0);
+      return OK;
+    }
+  
+  if (disr & USBDEV_USBSTS_SLI)
+    {
+      // FIXME: what do we need to do here...
+      usbtrace(TRACE_INTDECODE(LPC43_TRACEINTID_SUSPENDCHG),0);
+    }
+
+  if (disr & USBDEV_USBSTS_PCI)
+    {
+      portsc1 = lpc43_getreg(LPC43_USBDEV_PORTSC1);
+
+      if (portsc1 & USBDEV_PRTSC1_HSP)
+        priv->usbdev.speed = USB_SPEED_HIGH;
+      else
+        priv->usbdev.speed = USB_SPEED_FULL;
+
+      if (portsc1 & USBDEV_PRTSC1_FPR)
+        {
+          /* FIXME: this occurs because of a J-to-K transition detected
+           *         while the port is in SUSPEND state - presumambly this 
+           *         is where the host is resuming the device?
+           *
+           *  - but do we need to "ack" the interrupt
+           */
+        }
+    }
+  
+#ifdef CONFIG_LPC43_USBDEV_FRAME_INTERRUPT
+  if (disr & USBDEV_USBSTT_SRI)
+    {
+      usbtrace(TRACE_INTDECODE(LPC43_TRACEINTID_FRAME), 0);
+      
+      priv->sof = (int)lpc43_getreg(LPC43_USBDEV_FRINDEX_OFFSET); 
+    }
+#endif
+
+  if (disr & USBDEV_USBSTS_UEI)
+    {
+      /* FIXME: these occur when a transfer results in an error condition
+       *        it is set alongside USBINT if the DTD also had its IOC 
+       *        bit set. */
+    }
+  
+  if (disr & USBDEV_USBSTS_UI)
+    {
+      /* Handle completion interrupts */
+      uint32_t mask = lpc43_getreg (LPC43_USBDEV_ENDPTCOMPLETE);
+
+      if (mask)
+        {
+          /* Clear any NAK interrupt and completion interrupts */
+          lpc43_putreg (mask, LPC43_USBDEV_ENDPTNAK);
+          lpc43_putreg (mask, LPC43_USBDEV_ENDPTCOMPLETE);
+      
+          if (mask & LPC43_ENDPTMASK(0))
+            lpc43_ep0complete(priv, 0);
+          if (mask & LPC43_ENDPTMASK(1))
+            lpc43_ep0complete(priv, 1);
+      
+          for (n = 1; n < LPC43_NLOGENDPOINTS; n++)
+            {
+              if (mask & LPC43_ENDPTMASK((n<<1)))
+                lpc43_epcomplete (priv, (n<<1));
+              if (mask & LPC43_ENDPTMASK((n<<1)+1))
+                lpc43_epcomplete(priv, (n<<1)+1);
+            }
+        }
+
+      /* Handle setup interrupts */
+      uint32_t setupstat = lpc43_getreg(LPC43_USBDEV_ENDPTSETUPSTAT);
+      if (setupstat)
+        {
+          /* Clear the endpoint complete CTRL OUT and IN when a Setup is received */
+          lpc43_putreg(LPC43_ENDPTMASK(LPC43_EP0_IN) | LPC43_ENDPTMASK(LPC43_EP0_OUT), 
+                       LPC43_USBDEV_ENDPTCOMPLETE);
+      
+          if (setupstat & LPC43_ENDPTMASK(LPC43_EP0_OUT))
+            {
+              usbtrace(TRACE_INTDECODE(LPC43_TRACEINTID_EP0SETUP), setupstat);
+              lpc43_ep0setup(priv);
+            }
+        }
+    }
+
+  if (disr & USBDEV_USBSTS_NAKI)
+    {
+      uint32_t pending = lpc43_getreg(LPC43_USBDEV_ENDPTNAK) & lpc43_getreg(LPC43_USBDEV_ENDPTNAKEN);
+      if (pending)
+        {
+          /* We shouldn't see NAK interrupts except on Endpoint 0 */
+          if (pending & LPC43_ENDPTMASK(0))
+              lpc43_ep0nak(priv, 0);
+          if (pending & LPC43_ENDPTMASK(1))
+              lpc43_ep0nak(priv, 1);
+        }
+
+      /* Clear the interrupts */
+      lpc43_putreg(pending, LPC43_USBDEV_ENDPTNAK);
+    }
+
+  usbtrace(TRACE_INTEXIT(LPC43_TRACEINTID_USB), 0);
+  return OK;
+}
+
+/*******************************************************************************
+ * Endpoint operations
+ *******************************************************************************/
+
+/*******************************************************************************
+ * Name: lpc43_epconfigure
+ *
+ * Description:
+ *   Configure endpoint, making it usable
+ *
+ * Input Parameters:
+ *   ep   - the struct usbdev_ep_s instance obtained from allocep()
+ *   desc - A struct usb_epdesc_s instance describing the endpoint
+ *   last - true if this this last endpoint to be configured.  Some hardware
+ *          needs to take special action when all of the endpoints have been
+ *          configured.
+ *
+ *******************************************************************************/
+
+static int lpc43_epconfigure(FAR struct usbdev_ep_s *ep,
+                               FAR const struct usb_epdesc_s *desc,
+                               bool last)
+{
+  FAR struct lpc43_ep_s *privep = (FAR struct lpc43_ep_s *)ep;
+
+  usbtrace(TRACE_EPCONFIGURE, privep->epphy);
+  DEBUGASSERT(desc->addr == ep->eplog);
+
+  /* Initialise EP capabilities */
+  
+  uint16_t maxsize = GETUINT16(desc->mxpacketsize);
+  if ((desc->attr & USB_EP_ATTR_XFERTYPE_MASK) == USB_EP_ATTR_XFER_ISOC)
+    {
+      g_qh[privep->epphy].capability = (DQH_CAPABILITY_MAX_PACKET(maxsize) |
+                    DQH_CAPABILITY_IOS |
+                    DQH_CAPABILITY_ZLT);
+    }
+  else
+    {
+      g_qh[privep->epphy].capability = (DQH_CAPABILITY_MAX_PACKET(maxsize) |
+                    DQH_CAPABILITY_ZLT);
+    }
+
+  /* Setup Endpoint Control Register */
+
+  if (LPC43_EPPHYIN(privep->epphy))
+    {
+      /* Reset the data toggles */
+      uint32_t cfg = USBDEV_ENDPTCTRL_TXR;
+
+      /* Set the endpoint type */
+      switch (desc->attr & USB_EP_ATTR_XFERTYPE_MASK)
+        {
+          case USB_EP_ATTR_XFER_CONTROL: cfg |= USBDEV_ENDPTCTRL_TXT_CTRL; break;
+          case USB_EP_ATTR_XFER_ISOC:    cfg |= USBDEV_ENDPTCTRL_TXT_ISOC; break;
+          case USB_EP_ATTR_XFER_BULK:    cfg |= USBDEV_ENDPTCTRL_TXT_BULK; break;
+          case USB_EP_ATTR_XFER_INT:     cfg |= USBDEV_ENDPTCTRL_TXT_INTR; break;
+        }
+      lpc43_chgbits (0xFFFF0000, cfg, LPC43_USBDEV_ENDPTCTRL(privep->epphy));
+    }
+  else
+    {
+      /* Reset the data toggles */
+      uint32_t cfg = USBDEV_ENDPTCTRL_RXR;
+
+      /* Set the endpoint type */
+      switch (desc->attr & USB_EP_ATTR_XFERTYPE_MASK)
+        {
+          case USB_EP_ATTR_XFER_CONTROL: cfg |= USBDEV_ENDPTCTRL_RXT_CTRL; break;
+          case USB_EP_ATTR_XFER_ISOC:    cfg |= USBDEV_ENDPTCTRL_RXT_ISOC; break;
+          case USB_EP_ATTR_XFER_BULK:    cfg |= USBDEV_ENDPTCTRL_RXT_BULK; break;
+        }
+      lpc43_chgbits (0x0000FFFF, cfg, LPC43_USBDEV_ENDPTCTRL(privep->epphy));
+    }
+
+  /* Reset endpoint status */
+  privep->stalled = false;
+
+  /* Enable the endpoint */
+  if (LPC43_EPPHYIN(privep->epphy))
+    lpc43_setbits (USBDEV_ENDPTCTRL_TXE, LPC43_USBDEV_ENDPTCTRL(privep->epphy));
+  else
+    lpc43_setbits (USBDEV_ENDPTCTRL_RXE, LPC43_USBDEV_ENDPTCTRL(privep->epphy));
+  
+   return OK;
+}
+
+/*******************************************************************************
+ * Name: lpc43_epdisable
+ *
+ * Description:
+ *   The endpoint will no longer be used
+ *
+ *******************************************************************************/
+
+static int lpc43_epdisable(FAR struct usbdev_ep_s *ep)
+{
+  FAR struct lpc43_ep_s *privep = (FAR struct lpc43_ep_s *)ep;
+  irqstate_t flags;
+
+#ifdef CONFIG_DEBUG
+  if (!ep)
+    {
+      usbtrace(TRACE_DEVERROR(LPC43_TRACEERR_INVALIDPARMS), 0);
+      return -EINVAL;
+    }
+#endif
+  usbtrace(TRACE_EPDISABLE, privep->epphy);
+
+  flags = irqsave();
+
+  /* Disable Endpoint */
+  if (LPC43_EPPHYIN(privep->epphy))
+    lpc43_clrbits (USBDEV_ENDPTCTRL_TXE, LPC43_USBDEV_ENDPTCTRL(privep->epphy));
+  else
+    lpc43_clrbits (USBDEV_ENDPTCTRL_RXE, LPC43_USBDEV_ENDPTCTRL(privep->epphy));
+
+  privep->stalled = true;
+
+  /* Cancel any ongoing activity */
+  lpc43_cancelrequests(privep, -ESHUTDOWN);
+
+  irqrestore(flags);
+  return OK;
+}
+
+/*******************************************************************************
+ * Name: lpc43_epallocreq
+ *
+ * Description:
+ *   Allocate an I/O request
+ *
+ *******************************************************************************/
+
+static FAR struct usbdev_req_s *lpc43_epallocreq(FAR struct usbdev_ep_s *ep)
+{
+  FAR struct lpc43_req_s *privreq;
+
+#ifdef CONFIG_DEBUG
+  if (!ep)
+    {
+      usbtrace(TRACE_DEVERROR(LPC43_TRACEERR_INVALIDPARMS), 0);
+      return NULL;
+    }
+#endif
+  usbtrace(TRACE_EPALLOCREQ, ((FAR struct lpc43_ep_s *)ep)->epphy);
+
+  privreq = (FAR struct lpc43_req_s *)malloc(sizeof(struct lpc43_req_s));
+  if (!privreq)
+    {
+      usbtrace(TRACE_DEVERROR(LPC43_TRACEERR_ALLOCFAIL), 0);
+      return NULL;
+    }
+
+  memset(privreq, 0, sizeof(struct lpc43_req_s));
+  return &privreq->req;
+}
+
+/*******************************************************************************
+ * Name: lpc43_epfreereq
+ *
+ * Description:
+ *   Free an I/O request
+ *
+ *******************************************************************************/
+
+static void lpc43_epfreereq(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s *req)
+{
+  FAR struct lpc43_req_s *privreq = (FAR struct lpc43_req_s *)req;
+
+#ifdef CONFIG_DEBUG
+  if (!ep || !req)
+    {
+      usbtrace(TRACE_DEVERROR(LPC43_TRACEERR_INVALIDPARMS), 0);
+      return;
+    }
+#endif
+
+  usbtrace(TRACE_EPFREEREQ, ((FAR struct lpc43_ep_s *)ep)->epphy);
+  free(privreq);
+}
+
+/*******************************************************************************
+ * Name: lpc43_epallocbuffer
+ *
+ * Description:
+ *   Allocate an I/O buffer
+ *
+ *******************************************************************************/
+
+#ifdef CONFIG_USBDEV_DMA
+static void *lpc43_epallocbuffer(FAR struct usbdev_ep_s *ep, unsigned bytes)
+{
+  usbtrace(TRACE_EPALLOCBUFFER, privep->epphy);
+
+#ifdef CONFIG_USBDEV_DMAMEMORY
+  return usbdev_dma_alloc(bytes);
+#else
+  return malloc(bytes);
+#endif
+}
+#endif
+
+/*******************************************************************************
+ * Name: lpc43_epfreebuffer
+ *
+ * Description:
+ *   Free an I/O buffer
+ *
+ *******************************************************************************/
+
+#ifdef CONFIG_USBDEV_DMA
+static void lpc43_epfreebuffer(FAR struct usbdev_ep_s *ep, FAR void *buf)
+{
+  usbtrace(TRACE_EPFREEBUFFER, privep->epphy);
+
+#ifdef CONFIG_USBDEV_DMAMEMORY
+  usbdev_dma_free(buf);
+#else
+  free(buf);
+#endif
+}
+#endif
+
+/*******************************************************************************
+ * Name: lpc43_epsubmit
+ *
+ * Description:
+ *   Submit an I/O request to the endpoint
+ *
+ *******************************************************************************/
+
+static int lpc43_epsubmit(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s *req)
+{
+  FAR struct lpc43_req_s *privreq = (FAR struct lpc43_req_s *)req;
+  FAR struct lpc43_ep_s *privep = (FAR struct lpc43_ep_s *)ep;
+  FAR struct lpc43_usbdev_s *priv;
+  irqstate_t flags;
+  int ret = OK;
+
+#ifdef CONFIG_DEBUG
+  if (!req || !req->callback || !req->buf || !ep)
+    {
+      usbtrace(TRACE_DEVERROR(LPC43_TRACEERR_INVALIDPARMS), 0);
+      ullvdbg("req=%p callback=%p buf=%p ep=%p\n", req, req->callback, req->buf, ep);
+      return -EINVAL;
+    }
+#endif
+
+  usbtrace(TRACE_EPSUBMIT, privep->epphy);
+  priv = privep->dev;
+
+  if (!priv->driver || priv->usbdev.speed == USB_SPEED_UNKNOWN)
+    {
+      usbtrace(TRACE_DEVERROR(LPC43_TRACEERR_NOTCONFIGURED), priv->usbdev.speed);
+      return -ESHUTDOWN;
+    }
+
+  /* Handle the request from the class driver */
+
+  req->result = -EINPROGRESS;
+  req->xfrd   = 0;
+
+  /* Disable Interrupts */
+
+  flags = irqsave();
+
+  /* If we are stalled, then drop all requests on the floor */
+
+  if (privep->stalled)
+    {
+      ret = -EBUSY;
+    }
+  else 
+    {
+      /* Add the new request to the request queue for the endpoint */
+
+      if (LPC43_EPPHYIN(privep->epphy))
+        usbtrace(TRACE_INREQQUEUED(privep->epphy), privreq->req.len);
+      else
+        usbtrace(TRACE_OUTREQQUEUED(privep->epphy), privreq->req.len);
+
+      if (lpc43_rqenqueue(privep, privreq))
+        {
+          lpc43_progressep(privep);
+        }
+    }
+
+  irqrestore(flags);
+  return ret;
+}
+
+/*******************************************************************************
+ * Name: lpc43_epcancel
+ *
+ * Description:
+ *   Cancel an I/O request previously sent to an endpoint
+ *
+ *******************************************************************************/
+
+static int lpc43_epcancel(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s *req)
+{
+  FAR struct lpc43_ep_s *privep = (FAR struct lpc43_ep_s *)ep;
+  FAR struct lpc43_usbdev_s *priv;
+  irqstate_t flags;
+
+#ifdef CONFIG_DEBUG
+  if (!ep || !req)
+    {
+      usbtrace(TRACE_DEVERROR(LPC43_TRACEERR_INVALIDPARMS), 0);
+      return -EINVAL;
+    }
+#endif
+
+  usbtrace(TRACE_EPCANCEL, privep->epphy);
+  priv = privep->dev;
+
+  flags = irqsave();
+  
+  /* FIXME: if the request is the first, then we need to flush the EP
+   *         otherwise just remove it from the list
+   *
+   *  but ... all other implementations cancel all requests ...
+   */
+
+  lpc43_cancelrequests(privep, -ESHUTDOWN);
+  irqrestore(flags);
+  return OK;
+}
+
+/*******************************************************************************
+ * Name: lpc43_epstall
+ *
+ * Description:
+ *   Stall or resume and endpoint
+ *
+ *******************************************************************************/
+
+static int lpc43_epstall(FAR struct usbdev_ep_s *ep, bool resume)
+{
+  FAR struct lpc43_ep_s *privep = (FAR struct lpc43_ep_s *)ep;
+  irqstate_t flags;
+
+  /* STALL or RESUME the endpoint */
+
+  flags = irqsave();
+  usbtrace(resume ? TRACE_EPRESUME : TRACE_EPSTALL, privep->epphy);
+
+  uint32_t addr    = LPC43_USBDEV_ENDPTCTRL(privep->epphy);
+  uint32_t ctrl_xs = LPC43_EPPHYIN(privep->epphy) ? USBDEV_ENDPTCTRL_TXS : USBDEV_ENDPTCTRL_RXS;
+  uint32_t ctrl_xr = LPC43_EPPHYIN(privep->epphy) ? USBDEV_ENDPTCTRL_TXR : USBDEV_ENDPTCTRL_RXR;
+
+  if (resume)
+    {
+      privep->stalled = false;
+
+      /* Clear stall and reset the data toggle */
+
+      lpc43_chgbits (ctrl_xs | ctrl_xr, ctrl_xr, addr);
+    }
+  else
+    {
+      privep->stalled = true;
+
+      lpc43_setbits (ctrl_xs, addr);
+    }
+
+  irqrestore(flags);
+  return OK;
+}
+
+/*******************************************************************************
+ * Device operations
+ *******************************************************************************/
+
+/*******************************************************************************
+ * Name: lpc43_allocep
+ *
+ * Description:
+ *   Allocate an endpoint matching the parameters.
+ *
+ * Input Parameters:
+ *   eplog  - 7-bit logical endpoint number (direction bit ignored).  Zero means
+ *            that any endpoint matching the other requirements will suffice.  The
+ *            assigned endpoint can be found in the eplog field.
+ *   in     - true: IN (device-to-host) endpoint requested
+ *   eptype - Endpoint type.  One of {USB_EP_ATTR_XFER_ISOC, USB_EP_ATTR_XFER_BULK,
+ *            USB_EP_ATTR_XFER_INT}
+ *
+ *******************************************************************************/
+
+static FAR struct usbdev_ep_s *lpc43_allocep(FAR struct usbdev_s *dev, uint8_t eplog,
+                                               bool in, uint8_t eptype)
+{
+  FAR struct lpc43_usbdev_s *priv = (FAR struct lpc43_usbdev_s *)dev;
+  uint32_t epset = LPC43_EPALLSET & ~LPC43_EPCTRLSET;
+  irqstate_t flags;
+  int epndx = 0;
+
+  usbtrace(TRACE_DEVALLOCEP, (uint16_t)eplog);
+
+  /* Ignore any direction bits in the logical address */
+
+  eplog = USB_EPNO(eplog);
+
+  /* A logical address of 0 means that any endpoint will do */
+
+  if (eplog > 0)
+    {
+      /* Otherwise, we will return the endpoint structure only for the requested
+       * 'logical' endpoint.  All of the other checks will still be performed.
+       *
+       * First, verify that the logical endpoint is in the range supported by
+       * by the hardware.
+       */
+
+      if (eplog >= LPC43_NLOGENDPOINTS)
+        {
+          usbtrace(TRACE_DEVERROR(LPC43_TRACEERR_BADEPNO), (uint16_t)eplog);
+          return NULL;
+        }
+
+      /* Convert the logical address to a physical OUT endpoint address and
+       * remove all of the candidate endpoints from the bitset except for the
+       * the IN/OUT pair for this logical address.
+       */
+
+      epset &= 3 << (eplog << 1);
+    }
+
+  /* Get the subset matching the requested direction */
+
+  if (in)
+    {
+      epset &= LPC43_EPINSET;
+    }
+  else
+    {
+      epset &= LPC43_EPOUTSET;
+    }
+
+  /* Get the subset matching the requested type */
+
+  switch (eptype)
+    {
+    case USB_EP_ATTR_XFER_INT: /* Interrupt endpoint */
+      epset &= LPC43_EPINTRSET;
+      break;
+
+    case USB_EP_ATTR_XFER_BULK: /* Bulk endpoint */
+      epset &= LPC43_EPBULKSET;
+      break;
+
+    case USB_EP_ATTR_XFER_ISOC: /* Isochronous endpoint */
+      epset &= LPC43_EPISOCSET;
+      break;
+
+    case USB_EP_ATTR_XFER_CONTROL: /* Control endpoint -- not a valid choice */
+    default:
+      usbtrace(TRACE_DEVERROR(LPC43_TRACEERR_BADEPTYPE), (uint16_t)eptype);
+      return NULL;
+    }
+
+  /* Is the resulting endpoint supported by the LPC433x? */
+
+  if (epset)
+    {
+      /* Yes.. now see if any of the request endpoints are available */
+
+      flags = irqsave();
+      epset &= priv->epavail;
+      if (epset)
+        {
+          /* Select the lowest bit in the set of matching, available endpoints */
+
+          for (epndx = 2; epndx < LPC43_NPHYSENDPOINTS; epndx++)
+            {
+              uint32_t bit = 1 << epndx;
+              if ((epset & bit) != 0)
+                {
+                  /* Mark the IN/OUT endpoint no longer available */
+
+                  priv->epavail &= ~(3 << (bit & ~1));
+                  irqrestore(flags);
+
+                  /* And return the pointer to the standard endpoint structure */
+
+                  return &priv->eplist[epndx].ep;
+                }
+            }
+          /* Shouldn't get here */
+        }
+      irqrestore(flags);
+    }
+
+  usbtrace(TRACE_DEVERROR(LPC43_TRACEERR_NOEP), (uint16_t)eplog);
+  return NULL;
+}
+
+/*******************************************************************************
+ * Name: lpc43_freeep
+ *
+ * Description:
+ *   Free the previously allocated endpoint
+ *
+ *******************************************************************************/
+
+static void lpc43_freeep(FAR struct usbdev_s *dev, FAR struct usbdev_ep_s *ep)
+{
+  FAR struct lpc43_usbdev_s *priv = (FAR struct lpc43_usbdev_s *)dev;
+  FAR struct lpc43_ep_s *privep = (FAR struct lpc43_ep_s *)ep;
+  irqstate_t flags;
+
+  usbtrace(TRACE_DEVFREEEP, (uint16_t)privep->epphy);
+
+  if (priv && privep)
+    {
+      /* Mark the endpoint as available */
+
+      flags = irqsave();
+      priv->epavail |= (1 << privep->epphy);
+      irqrestore(flags);
+    }
+}
+
+/*******************************************************************************
+ * Name: lpc43_getframe
+ *
+ * Description:
+ *   Returns the current frame number
+ *
+ *******************************************************************************/
+
+static int lpc43_getframe(struct usbdev_s *dev)
+{
+#ifdef CONFIG_LPC43_USBDEV_FRAME_INTERRUPT
+  FAR struct lpc43_usbdev_s *priv = (FAR struct lpc43_usbdev_s *)dev;
+
+  /* Return last valid value of SOF read by the interrupt handler */
+
+  usbtrace(TRACE_DEVGETFRAME, (uint16_t)priv->sof);
+  return priv->sof;
+#else
+  /* Return the last frame number detected by the hardware */
+
+  usbtrace(TRACE_DEVGETFRAME, 0);
+
+  /* FIXME: this actually returns the micro frame number! */
+  return (int)lpc43_getreg(LPC43_USBDEV_FRINDEX_OFFSET);
+#endif
+}
+
+/*******************************************************************************
+ * Name: lpc43_wakeup
+ *
+ * Description:
+ *   Tries to wake up the host connected to this device
+ *
+ *******************************************************************************/
+
+static int lpc43_wakeup(struct usbdev_s *dev)
+{
+  irqstate_t flags;
+
+  usbtrace(TRACE_DEVWAKEUP, 0);
+
+  flags = irqsave();
+  lpc43_setbits(USBDEV_PRTSC1_FPR, LPC43_USBDEV_PORTSC1);
+  irqrestore(flags);
+  return OK;
+}
+
+/*******************************************************************************
+ * Name: lpc43_selfpowered
+ *
+ * Description:
+ *   Sets/clears the device selfpowered feature 
+ *
+ *******************************************************************************/
+
+static int lpc43_selfpowered(struct usbdev_s *dev, bool selfpowered)
+{
+  FAR struct lpc43_usbdev_s *priv = (FAR struct lpc43_usbdev_s *)dev;
+
+  usbtrace(TRACE_DEVSELFPOWERED, (uint16_t)selfpowered);
+
+#ifdef CONFIG_DEBUG
+  if (!dev)
+    {
+      usbtrace(TRACE_DEVERROR(LPC43_TRACEERR_INVALIDPARMS), 0);
+      return -ENODEV;
+    }
+#endif
+
+  priv->selfpowered = selfpowered;
+  return OK;
+}
+
+/*******************************************************************************
+ * Name: lpc43_pullup
+ *
+ * Description:
+ *   Software-controlled connect to/disconnect from USB host
+ *
+ *******************************************************************************/
+
+static int lpc43_pullup(struct usbdev_s *dev, bool enable)
+{
+  usbtrace(TRACE_DEVPULLUP, (uint16_t)enable);
+
+  irqstate_t flags = irqsave();
+  if (enable)
+    lpc43_setbits (USBDEV_USBCMD_RS, LPC43_USBDEV_USBCMD);
+  else
+    lpc43_clrbits (USBDEV_USBCMD_RS, LPC43_USBDEV_USBCMD);
+  irqrestore(flags);
+  return OK;
+}
+
+/*******************************************************************************
+ * Public Functions
+ *******************************************************************************/
+
+/*******************************************************************************
+ * Name: up_usbinitialize
+ *
+ * Description:
+ *   Initialize USB hardware.
+ *
+ * Assumptions:
+ * - This function is called very early in the initialization sequence
+ * - PLL and GIO pin initialization is not performed here but should been in
+ *   the low-level  boot logic:  PLL1 must be configured for operation at 48MHz
+ *   and P0.23 and PO.31 in PINSEL1 must be configured for Vbus and USB connect
+ *   LED.
+ *
+ *******************************************************************************/
+
+void up_usbinitialize(void)
+{
+  struct lpc43_usbdev_s *priv = &g_usbdev;
+  int i;
+
+  usbtrace(TRACE_DEVINIT, 0);
+
+  /* Disable USB interrupts */
+  
+  lpc43_putreg(0, LPC43_USBDEV_USBINTR);
+
+  /* Initialize the device state structure */
+
+  memset(priv, 0, sizeof(struct lpc43_usbdev_s));
+  priv->usbdev.ops = &g_devops;
+  priv->usbdev.ep0 = &priv->eplist[LPC43_EP0_IN].ep;
+  priv->epavail    = LPC43_EPALLSET;
+
+  /* Initialize the endpoint list */
+
+  for (i = 0; i < LPC43_NPHYSENDPOINTS; i++)
+    {
+      uint32_t bit = 1 << i;
+
+      /* Set endpoint operations, reference to driver structure (not
+       * really necessary because there is only one controller), and
+       * the physical endpoint number (which is just the index to the
+       * endpoint).
+       */
+      priv->eplist[i].ep.ops       = &g_epops;
+      priv->eplist[i].dev          = priv;
+
+      /* The index, i, is the physical endpoint address;  Map this
+       * to a logical endpoint address usable by the class driver.
+       */
+
+      priv->eplist[i].epphy        = i;
+      if (LPC43_EPPHYIN(i))
+        {
+          priv->eplist[i].ep.eplog = LPC43_EPPHYIN2LOG(i);
+        }
+      else
+        {
+          priv->eplist[i].ep.eplog = LPC43_EPPHYOUT2LOG(i);
+        }
+
+      /* The maximum packet size may depend on the type of endpoint */
+
+      if ((LPC43_EPCTRLSET & bit) != 0)
+        {
+          priv->eplist[i].ep.maxpacket = LPC43_EP0MAXPACKET;
+        }
+      else if ((LPC43_EPINTRSET & bit) != 0)
+        {
+          priv->eplist[i].ep.maxpacket = LPC43_INTRMAXPACKET;
+        }
+      else if ((LPC43_EPBULKSET & bit) != 0)
+        {
+          priv->eplist[i].ep.maxpacket = LPC43_BULKMAXPACKET;
+        }
+      else /* if ((LPC43_EPISOCSET & bit) != 0) */
+        {
+          priv->eplist[i].ep.maxpacket = LPC43_ISOCMAXPACKET;
+        }
+    }
+
+  /* Enable USB to AHB clock and to Event router*/
+
+  lpc43_enableclock (CLKID_USBOTGAHBCLK);
+  lpc43_enableclock (CLKID_EVENTROUTERPCLK);
+
+  /* Reset USB block */
+
+  lpc43_softreset (RESETID_USBOTGAHBRST);
+
+  /* Enable USB OTG PLL and wait for lock */
+
+  lpc43_putreg (0, LPC43_SYSCREG_USB_ATXPLLPDREG);
+  
+  uint32_t bank = EVNTRTR_BANK(EVENTRTR_USBATXPLLLOCK);
+  uint32_t bit  = EVNTRTR_BIT(EVENTRTR_USBATXPLLLOCK);
+
+  while (! (lpc43_getreg(LPC43_EVNTRTR_RSR(bank)) & (1 << bit)))
+    ;
+
+  /* Enable USB AHB clock */
+
+  lpc43_enableclock (CLKID_USBOTGAHBCLK);
+
+  /* Reset the controller */
+
+  lpc43_putreg (USBDEV_USBCMD_RST, LPC43_USBDEV_USBCMD);
+  while (lpc43_getreg (LPC43_USBDEV_USBCMD) & USBDEV_USBCMD_RST)
+      ;
+
+  /* Attach USB controller interrupt handler */
+
+  if (irq_attach(LPC43_IRQ_USBOTG, lpc43_usbinterrupt) != 0)
+    {
+      usbtrace(TRACE_DEVERROR(LPC43_TRACEERR_IRQREGISTRATION),
+               (uint16_t)LPC43_IRQ_USBOTG);
+      goto errout;
+    }
+
+
+  /* Program the controller to be the USB device controller */
+
+  lpc43_putreg (USBDEV_USBMODE_SDIS | USBDEV_USBMODE_SLOM | USBDEV_USBMODE_CMDEVICE,
+          LPC43_USBDEV_USBMODE);
+
+  /* Disconnect device */
+
+  lpc43_pullup(&priv->usbdev, false);
+
+  /* Reset/Re-initialize the USB hardware */
+
+  lpc43_usbreset(priv);
+
+  return;
+
+errout:
+  up_usbuninitialize();
+}
+
+/*******************************************************************************
+ * Name: up_usbuninitialize
+ *******************************************************************************/
+
+void up_usbuninitialize(void)
+{
+  struct lpc43_usbdev_s *priv = &g_usbdev;
+  irqstate_t flags;
+
+  usbtrace(TRACE_DEVUNINIT, 0);
+
+  if (priv->driver)
+    {
+      usbtrace(TRACE_DEVERROR(LPC43_TRACEERR_DRIVERREGISTERED), 0);
+      usbdev_unregister(priv->driver);
+    }
+
+  /* Disconnect device */
+
+  flags = irqsave();
+  lpc43_pullup(&priv->usbdev, false);
+  priv->usbdev.speed = USB_SPEED_UNKNOWN;
+
+  /* Disable and detach IRQs */
+
+  up_disable_irq(LPC43_IRQ_USBOTG);
+  irq_detach(LPC43_IRQ_USBOTG);
+
+  /* Reset the controller */
+
+  lpc43_putreg (USBDEV_USBCMD_RST, LPC43_USBDEV_USBCMD);
+  while (lpc43_getreg (LPC43_USBDEV_USBCMD) & USBDEV_USBCMD_RST)
+      ;
+
+  /* Turn off USB power and clocking */
+
+  lpc43_disableclock (CLKID_USBOTGAHBCLK);
+  lpc43_disableclock (CLKID_EVENTROUTERPCLK);
+
+
+  irqrestore(flags);
+}
+
+/*******************************************************************************
+ * Name: usbdev_register
+ *
+ * Description:
+ *   Register a USB device class driver. The class driver's bind() method will be
+ *   called to bind it to a USB device driver.
+ *
+ *******************************************************************************/
+
+int usbdev_register(struct usbdevclass_driver_s *driver)
+{
+  int ret;
+
+  usbtrace(TRACE_DEVREGISTER, 0);
+
+#ifdef CONFIG_DEBUG
+  if (!driver || !driver->ops->bind || !driver->ops->unbind ||
+      !driver->ops->disconnect || !driver->ops->setup)
+    {
+      usbtrace(TRACE_DEVERROR(LPC43_TRACEERR_INVALIDPARMS), 0);
+      return -EINVAL;
+    }
+
+  if (g_usbdev.driver)
+    {
+      usbtrace(TRACE_DEVERROR(LPC43_TRACEERR_DRIVER), 0);
+      return -EBUSY;
+    }
+#endif
+
+  /* First hook up the driver */
+
+  g_usbdev.driver = driver;
+
+  /* Then bind the class driver */
+
+  ret = CLASS_BIND(driver, &g_usbdev.usbdev);
+  if (ret)
+    {
+      usbtrace(TRACE_DEVERROR(LPC43_TRACEERR_BINDFAILED), (uint16_t)-ret);
+      g_usbdev.driver = NULL;
+    }
+  else
+    {
+      /* Enable USB controller interrupts */
+
+      up_enable_irq(LPC43_IRQ_USBOTG);
+
+      /* FIXME: nothing seems to call DEV_CONNECT(), but we need to set
+       *        the RS bit to enable the controller.  It kind of makes sense 
+       *        to do this after the class has bound to us...
+       * GEN:   This bug is really in the class driver.  It should make the
+       *        soft connect when it is ready to be enumerated.  I have added
+       *        that logic to the class drivers but left this logic here.
+       */
+
+      lpc43_pullup(&g_usbdev.usbdev, true);
+    }
+  return ret;
+}
+
+/*******************************************************************************
+ * Name: usbdev_unregister
+ *
+ * Description:
+ *   Un-register usbdev class driver.If the USB device is connected to a USB host,
+ *   it will first disconnect().  The driver is also requested to unbind() and clean
+ *   up any device state, before this procedure finally returns.
+ *
+ *******************************************************************************/
+
+int usbdev_unregister(struct usbdevclass_driver_s *driver)
+{
+  usbtrace(TRACE_DEVUNREGISTER, 0);
+
+#ifdef CONFIG_DEBUG
+  if (driver != g_usbdev.driver)
+    {
+      usbtrace(TRACE_DEVERROR(LPC43_TRACEERR_INVALIDPARMS), 0);
+      return -EINVAL;
+    }
+#endif
+
+  /* Unbind the class driver */
+
+  CLASS_UNBIND(driver, &g_usbdev.usbdev);
+
+  /* Disable USB controller interrupts */
+
+  up_disable_irq(LPC43_IRQ_USBOTG);
+
+  /* Unhook the driver */
+
+  g_usbdev.driver = NULL;
+  return OK;
+}
diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_usb0dev.h b/nuttx/arch/arm/src/lpc43xx/lpc43_usb0dev.h
new file mode 100644
index 000000000..fae22d323
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/lpc43_usb0dev.h
@@ -0,0 +1,98 @@
+/************************************************************************************
+ * arch/arm/src/lpc43xx/lpc43_usbdev.h
+ *
+ *   Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LPC43XX_LPC43_USB0DEV_H
+#define __ARCH_ARM_SRC_LPC43XX_LPC43_USB0DEV_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/usb/usbdev.h>
+#include <stdint.h>
+
+#include "chip.h"
+#include "chip/lpc43_usb0.h"
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C" {
+#else
+#define EXTERN extern
+#endif
+
+/************************************************************************************
+ * Name:  lpc43_usbpullup
+ *
+ * Description:
+ *   If USB is supported and the board supports a pullup via GPIO (for USB software
+ *   connect and disconnect), then the board software must provide lpc43_pullup.
+ *   See include/nuttx/usb/usbdev.h for additional description of this method.
+ *   Alternatively, if no pull-up GPIO the following EXTERN can be redefined to be
+ *   NULL.
+ *
+ ************************************************************************************/
+
+EXTERN int lpc43_usbpullup(FAR struct usbdev_s *dev,  bool enable);
+
+/************************************************************************************
+ * Name:  lpc43_usbsuspend
+ *
+ * Description:
+ *   Board logic must provide the lpc43_usbsuspend logic if the USBDEV driver is
+ *   used.  This function is called whenever the USB enters or leaves suspend mode.
+ *   This is an opportunity for the board logic to shutdown clocks, power, etc.
+ *   while the USB is suspended.
+ *
+ ************************************************************************************/
+
+EXTERN void lpc43_usbsuspend(FAR struct usbdev_s *dev, bool resume);
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_ARM_SRC_LPC43XX_LPC43_USB0DEV_H */
+
diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_usbram.h b/nuttx/arch/arm/src/lpc43xx/lpc43_usbram.h
new file mode 100644
index 000000000..7f23013e4
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc43xx/lpc43_usbram.h
@@ -0,0 +1,62 @@
+/************************************************************************************
+ * arch/arm/src/lpc43xx/lpc43_usbram.h
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LPC43XX_LPC43_USBRAM_H
+#define __ARCH_ARM_SRC_LPC43XX_LPC43_USBRAM_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+#include "chip.h"
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_LPC43XX_LPC43_USBRAM_H */