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authorpatacongo <patacongo@7fd9a85b-ad96-42d3-883c-3090e2eb8679>2012-08-02 21:48:54 +0000
committerpatacongo <patacongo@7fd9a85b-ad96-42d3-883c-3090e2eb8679>2012-08-02 21:48:54 +0000
commit44af31fc925d375add7afcde161fd7dd12dbb35b (patch)
tree43bcabdd8062bbd95eb746356950759d1a64c0b3 /nuttx/arch/arm/src/stm32/stm32_rcc.h
parenta9ba8355fbf4dd4a16ae1786167b91e2abd3880c (diff)
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Add stm32_clockenable() to support recovery from deep sleep low-power usage modes
git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@5000 7fd9a85b-ad96-42d3-883c-3090e2eb8679
Diffstat (limited to 'nuttx/arch/arm/src/stm32/stm32_rcc.h')
-rw-r--r--nuttx/arch/arm/src/stm32/stm32_rcc.h38
1 files changed, 37 insertions, 1 deletions
diff --git a/nuttx/arch/arm/src/stm32/stm32_rcc.h b/nuttx/arch/arm/src/stm32/stm32_rcc.h
index 3edf74782..c4d43db3a 100644
--- a/nuttx/arch/arm/src/stm32/stm32_rcc.h
+++ b/nuttx/arch/arm/src/stm32/stm32_rcc.h
@@ -156,7 +156,14 @@ static inline void stm32_mco2config(uint32_t source, uint32_t div)
* Name: stm32_clockconfig
*
* Description:
- * Called to change to new clock based on settings in board.h
+ * Called to establish the clock settings based on the values in board.h. This
+ * function (by default) will reset most everything, enable the PLL, and enable
+ * peripheral clocking for all periperipherals enabled in the NuttX configuration
+ * file.
+ *
+ * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking will
+ * be enabled by an externally provided, board-specific function called
+ * stm32_board_clockconfig().
*
* Input Parameters:
* None
@@ -169,6 +176,35 @@ static inline void stm32_mco2config(uint32_t source, uint32_t div)
EXTERN void stm32_clockconfig(void);
/************************************************************************************
+ * Name: stm32_clockenable
+ *
+ * Description:
+ * Re-enable the clock and restore the clock settings based on settings in board.h.
+ * This function is only available to support low-power modes of operation: When
+ * re-awakening from deep-sleep modes, it is necessary to re-enable/re-start the
+ * PLL
+ *
+ * This functional performs a subset of the operations performed by
+ * stm32_clockconfig(): It does not reset any devices, and it does not reset the
+ * currenlty enabled peripheral clocks.
+ *
+ * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking will
+ * be enabled by an externally provided, board-specific function called
+ * stm32_board_clockconfig().
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * None
+ *
+ ************************************************************************************/
+
+#ifdef CONFIG_PM
+EXTERN void stm32_clockenable(void);
+#endif
+
+/************************************************************************************
* Name: stm32_rcc_enablelse
*
* Description: