Pull NuttX up to the 6.24 release.

Merge branch 'nuttx-merge-5447'

28 files changed, 1504 insertions, 518 deletions

diff --git a/nuttx/arch/arm/src/stm32/Kconfig b/nuttx/arch/arm/src/stm32/Kconfig
index 2f9100236..99dde3209 100644
--- a/nuttx/arch/arm/src/stm32/Kconfig
+++ b/nuttx/arch/arm/src/stm32/Kconfig
@@ -34,6 +34,27 @@ config ARCH_CHIP_STM32F100RB
 	select STM32_STM32F10XX
 	select STM32_VALUELINE
 
+config ARCH_CHIP_STM32F100RC
+	bool "STM32F100RC"
+	select ARCH_CORTEXM3
+	select STM32_STM32F10XX
+	select STM32_VALUELINE
+	select STM32_HIGHDENSITY
+
+config ARCH_CHIP_STM32F100RD
+	bool "STM32F100RD"
+	select ARCH_CORTEXM3
+	select STM32_STM32F10XX
+	select STM32_VALUELINE
+	select STM32_HIGHDENSITY
+
+config ARCH_CHIP_STM32F100RE
+	bool "STM32F100RE"
+	select ARCH_CORTEXM3
+	select STM32_STM32F10XX
+	select STM32_VALUELINE
+	select STM32_HIGHDENSITY
+
 config ARCH_CHIP_STM32F100V8
 	bool "STM32F100V8"
 	select ARCH_CORTEXM3
@@ -46,6 +67,27 @@ config ARCH_CHIP_STM32F100VB
 	select STM32_STM32F10XX
 	select STM32_VALUELINE
 
+config ARCH_CHIP_STM32F100VC
+	bool "STM32F100VC"
+	select ARCH_CORTEXM3
+	select STM32_STM32F10XX
+	select STM32_VALUELINE
+	select STM32_HIGHDENSITY
+
+config ARCH_CHIP_STM32F100VD
+	bool "STM32F100VD"
+	select ARCH_CORTEXM3
+	select STM32_STM32F10XX
+	select STM32_VALUELINE
+	select STM32_HIGHDENSITY
+
+config ARCH_CHIP_STM32F100VE
+	bool "STM32F100VE"
+	select ARCH_CORTEXM3
+	select STM32_STM32F10XX
+	select STM32_VALUELINE
+	select STM32_HIGHDENSITY
+
 config ARCH_CHIP_STM32F103RET6
 	bool "STM32F103RET6"
 	select ARCH_CORTEXM3
@@ -108,7 +150,7 @@ config ARCH_CHIP_STM32F407VE
 
 config ARCH_CHIP_STM32F407VG
 	bool "STM32F407VG"
-	select ARCH_CORTEXM3
+	select ARCH_CORTEXM4
 	select STM32_STM32F40XX
 
 config ARCH_CHIP_STM32F407ZE
@@ -151,37 +193,10 @@ config STM32_STM32F20XX
 config STM32_STM32F40XX
 	bool
 
-choice
-	prompt "Toolchain Selection"
-	default STM32_CODESOURCERYW
-	depends on ARCH_CHIP_STM32
-
-config STM32_CODESOURCERYW
-	bool "CodeSourcery for Windows"
-
-config STM32_CODESOURCERYL
-	bool "CodeSourcery for Linux"
-
-config STM32_ATOLLIC_LITE
-	bool "Atollic Lite for Windows"
-
-config STM32_ATOLLIC_PRO
-	bool "Atollic Pro for Windows"
-
-config STM32_DEVKITARM
-	bool "DevkitARM (Windows)"
-
-config STM32_RAISONANCE
-	bool "STMicro Raisonance for Windows"
-
-config STM32_BUILDROOT
-	bool "NuttX buildroot (Cygwin or Linux)"
-
-endchoice
-
 config STM32_DFU
 	bool "DFU bootloader"
 	default n
+	depends on !STM32_VALUELINE
 	---help---
 		Configure and position code for use with the STMicro DFU bootloader.  Do
 		not select this option if you will load code using JTAG/SWM.
@@ -197,25 +212,13 @@ config STM32_ADC2
 	bool "ADC2"
 	default n
 	select STM32_ADC
+	depends on !STM32_VALUELINE
 
 config STM32_ADC3
 	bool "ADC3"
 	default n
 	select STM32_ADC
-
-config STM32_CRC
-	bool "CRC"
-	default n
-
-config STM32_DMA1
-	bool "DMA1"
-	default n
-	select ARCH_DMA
-
-config STM32_DMA2
-	bool "DMA2"
-	default n
-	select ARCH_DMA
+	depends on !STM32_VALUELINE
 
 config STM32_BKP
 	bool "BKP"
@@ -232,6 +235,7 @@ config STM32_CAN1
 	default n
 	select CAN
 	select STM32_CAN
+	depends on !STM32_VALUELINE
 
 config STM32_CAN2
 	bool "CAN2"
@@ -245,11 +249,31 @@ config STM32_CCMDATARAM
 	default n
 	depends on STM32_STM32F40XX
 
+config STM32_CEC
+	bool "CEC"
+	default n
+	depends on STM32_VALUELINE
+
+config STM32_CRC
+	bool "CRC"
+	default n
+
 config STM32_CRYP
 	bool "CRYP"
 	default n
 	depends on STM32_STM32F20XX || STM32_STM32F40XX
 
+config STM32_DMA1
+	bool "DMA1"
+	default n
+	select ARCH_DMA
+
+config STM32_DMA2
+	bool "DMA2"
+	default n
+	select ARCH_DMA
+	depends on !STM32_VALUELINE || (STM32_VALUELINE && STM32_HIGHDENSITY)
+
 config STM32_DAC1
 	bool "DAC1"
 	default n
@@ -274,7 +298,7 @@ config STM32_ETHMAC
 config STM32_FSMC
 	bool "FSMC"
 	default n
-	depends on !STM32_CONNECTIVITYLINE
+	depends on !STM32_CONNECTIVITYLINE && (STM32_HIGHDENSITY || STM32_STM32F20XX || STM32_STM32F40XX)
 
 config STM32_HASH
 	bool "HASH"
@@ -325,7 +349,7 @@ config STM32_RNG
 config STM32_SDIO
 	bool "SDIO"
 	default n
-	depends on !STM32_CONNECTIVITYLINE
+	depends on !STM32_CONNECTIVITYLINE && !STM32_VALUELINE
 
 config STM32_SPI1
 	bool "SPI1"
@@ -342,7 +366,7 @@ config STM32_SPI2
 config STM32_SPI3
 	bool "SPI3"
 	default n
-	depends on STM32_CONNECTIVITYLINE || STM32_STM32F20XX || STM32_STM32F40XX
+	depends on STM32_CONNECTIVITYLINE || STM32_STM32F20XX || STM32_STM32F40XX || (STM32_VALUELINE && STM32_HIGHDENSITY)
 	select SPI
 	select STM32_SPI
 
@@ -382,6 +406,7 @@ config STM32_TIM7
 config STM32_TIM8
 	bool "TIM8"
 	default n
+	depends on !STM32_VALUELINE
 
 config STM32_TIM9
 	bool "TIM9"
@@ -401,17 +426,32 @@ config STM32_TIM11
 config STM32_TIM12
 	bool "TIM12"
 	default n
-	depends on STM32_STM32F20XX || STM32_STM32F40XX
+	depends on STM32_STM32F20XX || STM32_STM32F40XX || STM32_VALUELINE
 
 config STM32_TIM13
 	bool "TIM13"
 	default n
-	depends on STM32_STM32F20XX || STM32_STM32F40XX
+	depends on STM32_STM32F20XX || STM32_STM32F40XX || STM32_VALUELINE
 
 config STM32_TIM14
 	bool "TIM14"
 	default n
-	depends on STM32_STM32F20XX || STM32_STM32F40XX
+	depends on STM32_STM32F20XX || STM32_STM32F40XX || STM32_VALUELINE
+
+config STM32_TIM15
+	bool "TIM15"
+	default n
+	depends on STM32_VALUELINE
+
+config STM32_TIM16
+	bool "TIM16"
+	default n
+	depends on STM32_VALUELINE
+
+config STM32_TIM17
+	bool "TIM17"
+	default n
+	depends on STM32_VALUELINE
 
 config STM32_USART1
 	bool "USART1"
@@ -447,7 +487,7 @@ config STM32_USART6
 config STM32_USB
 	bool "USB Device"
 	default n
-	depends on STM32_STM32F10XX
+	depends on STM32_STM32F10XX && !STM32_VALUELINE
 	select USBDEV
 
 config STM32_WWDG
@@ -475,6 +515,52 @@ config STM32_CAN
 menu "Alternate Pin Mapping"
 
 choice
+	prompt "CAN1 Alternate Pin Mappings"
+	depends on STM32_STM32F10XX && STM32_CAN1
+	default STM32_CAN1_NO_REMAP
+
+config STM32_CAN1_NO_REMAP
+	bool "No pin remapping"
+
+config STM32_CAN1_REMAP1
+	bool "CAN1 alternate pin remapping #1"
+
+config STM32_CAN1_REMAP2
+	bool "CAN1 alternate pin remapping #2"
+
+endchoice
+
+config STM32_CAN2_REMAP
+	bool "CAN2 Alternate Pin Mapping"
+	default n
+	depends on STM32_CONNECTIVITYLINE && STM32_CAN2
+
+config STM32_CEC_REMAP
+	bool "CEC Alternate Pin Mapping"
+	default n
+	depends on STM32_STM32F10XX && STM32_CEC
+
+config STM32_ETH_REMAP
+	bool "Ethernet Alternate Pin Mapping"
+	default n
+	depends on STM32_CONNECTIVITYLINE && STM32_ETHMAC
+
+config STM32_I2C1_REMAP
+	bool "I2C1 Alternate Pin Mapping"
+	default n
+	depends on STM32_STM32F10XX && STM32_I2C1
+
+config STM32_SPI1_REMAP
+	bool "SPI1 Alternate Pin Mapping"
+	default n
+	depends on STM32_STM32F10XX && STM32_SPI1
+
+config STM32_SPI3_REMAP
+	bool "SPI3 Alternate Pin Mapping"
+	default n
+	depends on STM32_STM32F10XX && STM32_SPI3 && !STM32_VALUELINE
+
+choice
 	prompt "TIM1 Alternate Pin Mappings"
 	depends on STM32_STM32F10XX && STM32_TIM1
 	default STM32_TIM1_NO_REMAP
@@ -530,6 +616,51 @@ config STM32_TIM4_REMAP
 	default n
 	depends on STM32_STM32F10XX && STM32_TIM4
 
+config STM32_TIM9_REMAP
+	bool "TIM9 Alternate Pin Mapping"
+	default n
+	depends on STM32_STM32F10XX && STM32_TIM9
+
+config STM32_TIM10_REMAP
+	bool "TIM10 Alternate Pin Mapping"
+	default n
+	depends on STM32_STM32F10XX && STM32_TIM10
+
+config STM32_TIM11_REMAP
+	bool "TIM11 Alternate Pin Mapping"
+	default n
+	depends on STM32_STM32F10XX && STM32_TIM11
+
+config STM32_TIM12_REMAP
+	bool "TIM12 Alternate Pin Mapping"
+	default n
+	depends on STM32_STM32F10XX && STM32_TIM12
+
+config STM32_TIM13_REMAP
+	bool "TIM13 Alternate Pin Mapping"
+	default n
+	depends on STM32_STM32F10XX && STM32_TIM13
+
+config STM32_TIM14_REMAP
+	bool "TIM14 Alternate Pin Mapping"
+	default n
+	depends on STM32_STM32F10XX && STM32_TIM14
+
+config STM32_TIM15_REMAP
+	bool "TIM15 Alternate Pin Mapping"
+	default n
+	depends on STM32_STM32F10XX && STM32_TIM15
+
+config STM32_TIM16_REMAP
+	bool "TIM16 Alternate Pin Mapping"
+	default n
+	depends on STM32_STM32F10XX && STM32_TIM16
+
+config STM32_TIM17_REMAP
+	bool "TIM17 Alternate Pin Mapping"
+	default n
+	depends on STM32_STM32F10XX && STM32_TIM17
+
 config STM32_USART1_REMAP
 	bool "USART1 Alternate Pin Mapping"
 	default n
@@ -556,48 +687,16 @@ config STM32_USART3_PARTIAL_REMAP
 
 endchoice
 
-config STM32_SPI1_REMAP
-	bool "SPI1 Alternate Pin Mapping"
-	default n
-	depends on STM32_STM32F10XX && STM32_SPI1
-
-config STM32_SPI3_REMAP
-	bool "SPI3 Alternate Pin Mapping"
-	default n
-	depends on STM32_STM32F10XX && STM32_SPI3
-
-config STM32_I2C1_REMAP
-	bool "I2C1 Alternate Pin Mapping"
-	default n
-	depends on STM32_STM32F10XX && STM32_I2C1
-
-choice
-	prompt "CAN1 Alternate Pin Mappings"
-	depends on STM32_STM32F10XX && STM32_CAN1
-	default STM32_CAN1_NO_REMAP
-
-config STM32_CAN1_NO_REMAP
-	bool "No pin remapping"
-
-config STM32_CAN1_REMAP1
-	bool "CAN1 alternate pin remapping #1"
-
-config STM32_CAN1_REMAP2
-	bool "CAN1 alternate pin remapping #2"
-
-endchoice
-
-config STM32_CAN2_REMAP
-	bool "CAN2 Alternate Pin Mapping"
-	default n
-	depends on STM32_CONNECTIVITYLINE && STM32_CAN2
+endmenu
 
-config STM32_ETH_REMAP
-	bool "Ethernet Alternate Pin Mapping"
+config STM32_FLASH_PREFETCH
+	bool "Enable FLASH Pre-fetch"
+	depends on STM32_STM32F20XX || STM32_STM32F40XX
 	default n
-	depends on STM32_CONNECTIVITYLINE && STM32_ETHMAC
-
-endmenu
+	---help---
+	Enable FLASH prefetch and F2 and F4 parts (FLASH pre-fetch is always enabled
+	on F1 parts).  Some early revisions of F4 parts do not support FLASH pre-fetch
+	properly and enabling this option may interfere with ADC accuracy.
 
 choice
 	prompt "JTAG Configuration"
@@ -636,9 +735,11 @@ config ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG
 config STM32_CCMEXCLUDE
 	bool "Exclude CCM SRAM from the heap"
 	depends on STM32_STM32F20XX || STM32_STM32F40XX
-	default y if  ARCH_DMA
+	default y if  ARCH_DMA || ELF
 	---help---
-		Exclude CCM SRAM from the HEAP because it cannot be used for DMA.
+		Exclude CCM SRAM from the HEAP because (1) it cannot be used for DMA
+		and (2) it appears to be impossible to execute ELF modules from CCM
+		RAM.
 
 config STM32_FSMC_SRAM
 	bool "External SRAM on FSMC"
@@ -663,6 +764,7 @@ config STM32_TIM1_PWM
 config STM32_TIM1_CHANNEL
 	int "TIM1 PWM Output Channel"
 	default 1
+	range 1 4
 	depends on STM32_TIM1_PWM
 	---help---
 		If TIM1 is enabled for PWM usage, you also need specifies the timer output
@@ -673,7 +775,7 @@ config STM32_TIM2_PWM
 	default n
 	depends on STM32_TIM2
 	---help---
-		Reserve timer 1 for use by PWM
+		Reserve timer 2 for use by PWM
 
 		Timer devices may be used for different purposes.  One special purpose is
 		to generate modulated outputs for such things as motor control.  If STM32_TIM2
@@ -683,6 +785,7 @@ config STM32_TIM2_PWM
 config STM32_TIM2_CHANNEL
 	int "TIM2 PWM Output Channel"
 	default 1
+	range 1 4
 	depends on STM32_TIM2_PWM
 	---help---
 		If TIM2 is enabled for PWM usage, you also need specifies the timer output
@@ -693,7 +796,7 @@ config STM32_TIM3_PWM
 	default n
 	depends on STM32_TIM3
 	---help---
-		Reserve timer 1 for use by PWM
+		Reserve timer 3 for use by PWM
 
 		Timer devices may be used for different purposes.  One special purpose is
 		to generate modulated outputs for such things as motor control.  If STM32_TIM3
@@ -703,6 +806,7 @@ config STM32_TIM3_PWM
 config STM32_TIM3_CHANNEL
 	int "TIM3 PWM Output Channel"
 	default 1
+	range 1 4
 	depends on STM32_TIM3_PWM
 	---help---
 		If TIM3 is enabled for PWM usage, you also need specifies the timer output
@@ -713,7 +817,7 @@ config STM32_TIM4_PWM
 	default n
 	depends on STM32_TIM4
 	---help---
-		Reserve timer 1 for use by PWM
+		Reserve timer 4 for use by PWM
 
 		Timer devices may be used for different purposes.  One special purpose is
 		to generate modulated outputs for such things as motor control.  If STM32_TIM4
@@ -723,6 +827,7 @@ config STM32_TIM4_PWM
 config STM32_TIM4_CHANNEL
 	int "TIM4 PWM Output Channel"
 	default 1
+	range 1 4
 	depends on STM32_TIM4_PWM
 	---help---
 		If TIM4 is enabled for PWM usage, you also need specifies the timer output
@@ -733,7 +838,7 @@ config STM32_TIM5_PWM
 	default n
 	depends on STM32_TIM5
 	---help---
-		Reserve timer 1 for use by PWM
+		Reserve timer 5 for use by PWM
 
 		Timer devices may be used for different purposes.  One special purpose is
 		to generate modulated outputs for such things as motor control.  If STM32_TIM5
@@ -743,6 +848,7 @@ config STM32_TIM5_PWM
 config STM32_TIM5_CHANNEL
 	int "TIM5 PWM Output Channel"
 	default 1
+	range 1 4
 	depends on STM32_TIM5_PWM
 	---help---
 		If TIM5 is enabled for PWM usage, you also need specifies the timer output
@@ -753,7 +859,7 @@ config STM32_TIM8_PWM
 	default n
 	depends on STM32_TIM8
 	---help---
-		Reserve timer 1 for use by PWM
+		Reserve timer 8 for use by PWM
 
 		Timer devices may be used for different purposes.  One special purpose is
 		to generate modulated outputs for such things as motor control.  If STM32_TIM8
@@ -763,6 +869,7 @@ config STM32_TIM8_PWM
 config STM32_TIM8_CHANNEL
 	int "TIM8 PWM Output Channel"
 	default 1
+	range 1 4
 	depends on STM32_TIM8_PWM
 	---help---
 		If TIM8 is enabled for PWM usage, you also need specifies the timer output
@@ -773,7 +880,7 @@ config STM32_TIM9_PWM
 	default n
 	depends on STM32_TIM9
 	---help---
-		Reserve timer 1 for use by PWM
+		Reserve timer 9 for use by PWM
 
 		Timer devices may be used for different purposes.  One special purpose is
 		to generate modulated outputs for such things as motor control.  If STM32_TIM9
@@ -783,6 +890,7 @@ config STM32_TIM9_PWM
 config STM32_TIM9_CHANNEL
 	int "TIM9 PWM Output Channel"
 	default 1
+	range 1 4
 	depends on STM32_TIM9_PWM
 	---help---
 		If TIM9 is enabled for PWM usage, you also need specifies the timer output
@@ -793,7 +901,7 @@ config STM32_TIM10_PWM
 	default n
 	depends on STM32_TIM10
 	---help---
-		Reserve timer 1 for use by PWM
+		Reserve timer 10 for use by PWM
 
 		Timer devices may be used for different purposes.  One special purpose is
 		to generate modulated outputs for such things as motor control.  If STM32_TIM10
@@ -803,6 +911,7 @@ config STM32_TIM10_PWM
 config STM32_TIM10_CHANNEL
 	int "TIM10 PWM Output Channel"
 	default 1
+	range 1 4
 	depends on STM32_TIM10_PWM
 	---help---
 		If TIM10 is enabled for PWM usage, you also need specifies the timer output
@@ -813,7 +922,7 @@ config STM32_TIM11_PWM
 	default n
 	depends on STM32_TIM11
 	---help---
-		Reserve timer 1 for use by PWM
+		Reserve timer 11 for use by PWM
 
 		Timer devices may be used for different purposes.  One special purpose is
 		to generate modulated outputs for such things as motor control.  If STM32_TIM11
@@ -823,6 +932,7 @@ config STM32_TIM11_PWM
 config STM32_TIM11_CHANNEL
 	int "TIM11 PWM Output Channel"
 	default 1
+	range 1 4
 	depends on STM32_TIM11_PWM
 	---help---
 		If TIM11 is enabled for PWM usage, you also need specifies the timer output
@@ -833,7 +943,7 @@ config STM32_TIM12_PWM
 	default n
 	depends on STM32_TIM12
 	---help---
-		Reserve timer 1 for use by PWM
+		Reserve timer 12 for use by PWM
 
 		Timer devices may be used for different purposes.  One special purpose is
 		to generate modulated outputs for such things as motor control.  If STM32_TIM12
@@ -843,6 +953,7 @@ config STM32_TIM12_PWM
 config STM32_TIM12_CHANNEL
 	int "TIM12 PWM Output Channel"
 	default 1
+	range 1 4
 	depends on STM32_TIM12_PWM
 	---help---
 		If TIM12 is enabled for PWM usage, you also need specifies the timer output
@@ -853,7 +964,7 @@ config STM32_TIM13_PWM
 	default n
 	depends on STM32_TIM13
 	---help---
-		Reserve timer 1 for use by PWM
+		Reserve timer 13 for use by PWM
 
 		Timer devices may be used for different purposes.  One special purpose is
 		to generate modulated outputs for such things as motor control.  If STM32_TIM13
@@ -863,6 +974,7 @@ config STM32_TIM13_PWM
 config STM32_TIM13_CHANNEL
 	int "TIM13 PWM Output Channel"
 	default 1
+	range 1 4
 	depends on STM32_TIM13_PWM
 	---help---
 		If TIM13 is enabled for PWM usage, you also need specifies the timer output
@@ -873,7 +985,7 @@ config STM32_TIM14_PWM
 	default n
 	depends on STM32_TIM14
 	---help---
-		Reserve timer 1 for use by PWM
+		Reserve timer 14 for use by PWM
 
 		Timer devices may be used for different purposes.  One special purpose is
 		to generate modulated outputs for such things as motor control.  If STM32_TIM14
@@ -883,11 +995,75 @@ config STM32_TIM14_PWM
 config STM32_TIM14_CHANNEL
 	int "TIM14 PWM Output Channel"
 	default 1
+	range 1 4
 	depends on STM32_TIM14_PWM
 	---help---
 		If TIM14 is enabled for PWM usage, you also need specifies the timer output
 		channel {1,..,4}
 
+config STM32_TIM15_PWM
+	bool "TIM15 PWM"
+	default n
+	depends on STM32_TIM15
+	---help---
+		Reserve timer 15 for use by PWM
+
+		Timer devices may be used for different purposes.  One special purpose is
+		to generate modulated outputs for such things as motor control.  If STM32_TIM15
+		is defined then THIS following may also be defined to indicate that
+		the timer is intended to be used for pulsed output modulation.
+
+config STM32_TIM15_CHANNEL
+	int "TIM15 PWM Output Channel"
+	default 1
+	range 1 2
+	depends on STM32_TIM15_PWM
+	---help---
+		If TIM15 is enabled for PWM usage, you also need specifies the timer output
+		channel {1,2}
+
+config STM32_TIM16_PWM
+	bool "TIM16 PWM"
+	default n
+	depends on STM32_TIM16
+	---help---
+		Reserve timer 16 for use by PWM
+
+		Timer devices may be used for different purposes.  One special purpose is
+		to generate modulated outputs for such things as motor control.  If STM32_TIM16
+		is defined then THIS following may also be defined to indicate that
+		the timer is intended to be used for pulsed output modulation.
+
+config STM32_TIM16_CHANNEL
+	int "TIM16 PWM Output Channel"
+	default 1
+	range 1 1
+	depends on STM32_TIM16_PWM
+	---help---
+		If TIM16 is enabled for PWM usage, you also need specifies the timer output
+		channel {1}
+
+config STM32_TIM17_PWM
+	bool "TIM17 PWM"
+	default n
+	depends on STM32_TIM17
+	---help---
+		Reserve timer 17 for use by PWM
+
+		Timer devices may be used for different purposes.  One special purpose is
+		to generate modulated outputs for such things as motor control.  If STM32_TIM17
+		is defined then THIS following may also be defined to indicate that
+		the timer is intended to be used for pulsed output modulation.
+
+config STM32_TIM17_CHANNEL
+	int "TIM17 PWM Output Channel"
+	default 1
+	range 1 1
+	depends on STM32_TIM17_PWM
+	---help---
+		If TIM17 is enabled for PWM usage, you also need specifies the timer output
+		channel {1}
+
 config STM32_TIM1_ADC
 	bool "TIM1 ADC"
 	default n
@@ -909,16 +1085,22 @@ choice
 
 config STM32_TIM1_ADC1
 	bool "TIM1 ADC channel 1"
+	depends on STM32_ADC1
+	select HAVE_ADC1_TIMER
 	---help---
 		Reserve TIM1 to trigger ADC1
 
 config STM32_TIM1_ADC2
 	bool "TIM1 ADC channel 2"
+	depends on STM32_ADC2
+	select HAVE_ADC2_TIMER
 	---help---
 		Reserve TIM1 to trigger ADC2
 
 config STM32_TIM1_ADC3
 	bool "TIM1 ADC channel 3"
+	depends on STM32_ADC3
+	select HAVE_ADC3_TIMER
 	---help---
 		Reserve TIM1 to trigger ADC3
 
@@ -945,16 +1127,22 @@ choice
 
 config STM32_TIM2_ADC1
 	bool "TIM2 ADC channel 1"
+	depends on STM32_ADC1
+	select HAVE_ADC1_TIMER
 	---help---
 		Reserve TIM2 to trigger ADC1
 
 config STM32_TIM2_ADC2
 	bool "TIM2 ADC channel 2"
+	depends on STM32_ADC2
+	select HAVE_ADC2_TIMER
 	---help---
 		Reserve TIM2 to trigger ADC2
 
 config STM32_TIM2_ADC3
 	bool "TIM2 ADC channel 3"
+	depends on STM32_ADC3
+	select HAVE_ADC3_TIMER
 	---help---
 		Reserve TIM2 to trigger ADC3
 
@@ -981,16 +1169,22 @@ choice
 
 config STM32_TIM3_ADC1
 	bool "TIM3 ADC channel 1"
+	depends on STM32_ADC1
+	select HAVE_ADC1_TIMER
 	---help---
 		Reserve TIM3 to trigger ADC1
 
 config STM32_TIM3_ADC2
 	bool "TIM3 ADC channel 2"
+	depends on STM32_ADC2
+	select HAVE_ADC2_TIMER
 	---help---
 		Reserve TIM3 to trigger ADC2
 
 config STM32_TIM3_ADC3
 	bool "TIM3 ADC channel 3"
+	depends on STM32_ADC3
+	select HAVE_ADC3_TIMER
 	---help---
 		Reserve TIM3 to trigger ADC3
 
@@ -1017,16 +1211,22 @@ choice
 
 config STM32_TIM4_ADC1
 	bool "TIM4 ADC channel 1"
+	depends on STM32_ADC1
+	select HAVE_ADC1_TIMER
 	---help---
 		Reserve TIM4 to trigger ADC1
 
 config STM32_TIM4_ADC2
 	bool "TIM4 ADC channel 2"
+	depends on STM32_ADC2
+	select HAVE_ADC2_TIMER
 	---help---
 		Reserve TIM4 to trigger ADC2
 
 config STM32_TIM4_ADC3
 	bool "TIM4 ADC channel 3"
+	depends on STM32_ADC3
+	select HAVE_ADC3_TIMER
 	---help---
 		Reserve TIM4 to trigger ADC3
 
@@ -1053,16 +1253,22 @@ choice
 
 config STM32_TIM5_ADC1
 	bool "TIM5 ADC channel 1"
+	depends on STM32_ADC1
+	select HAVE_ADC1_TIMER
 	---help---
 		Reserve TIM5 to trigger ADC1
 
 config STM32_TIM5_ADC2
 	bool "TIM5 ADC channel 2"
+	depends on STM32_ADC2
+	select HAVE_ADC2_TIMER
 	---help---
 		Reserve TIM5 to trigger ADC2
 
 config STM32_TIM5_ADC3
 	bool "TIM5 ADC channel 3"
+	depends on STM32_ADC3
+	select HAVE_ADC3_TIMER
 	---help---
 		Reserve TIM5 to trigger ADC3
 
@@ -1089,21 +1295,81 @@ choice
 
 config STM32_TIM8_ADC1
 	bool "TIM8 ADC channel 1"
+	depends on STM32_ADC1
+	select HAVE_ADC1_TIMER
 	---help---
 		Reserve TIM8 to trigger ADC1
 
 config STM32_TIM8_ADC2
 	bool "TIM8 ADC channel 2"
+	depends on STM32_ADC2
+	select HAVE_ADC2_TIMER
 	---help---
 		Reserve TIM8 to trigger ADC2
 
 config STM32_TIM8_ADC3
 	bool "TIM8 ADC channel 3"
+	depends on STM32_ADC3
+	select HAVE_ADC3_TIMER
 	---help---
 		Reserve TIM8 to trigger ADC3
 
 endchoice
 
+config HAVE_ADC1_TIMER
+	bool
+
+config HAVE_ADC2_TIMER
+	bool
+
+config HAVE_ADC3_TIMER
+	bool
+
+config STM32_ADC1_SAMPLE_FREQUENCY
+	int "ADC1 Sampling Frequency"
+	default 100
+	depends on HAVE_ADC1_TIMER
+	---help---
+		ADC1 sampling frequency.  Default:  100Hz
+
+config STM32_ADC1_TIMTRIG
+	int "ADC1 Timer Trigger"
+	default 0
+	range 0 4
+	depends on HAVE_ADC1_TIMER
+	---help---
+		Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO
+
+config STM32_ADC2_SAMPLE_FREQUENCY
+	int "ADC2 Sampling Frequency"
+	default 100
+	depends on HAVE_ADC2_TIMER
+	---help---
+		ADC2 sampling frequency.  Default:  100Hz
+
+config STM32_ADC2_TIMTRIG
+	int "ADC2 Timer Trigger"
+	default 0
+	range 0 4
+	depends on HAVE_ADC2_TIMER
+	---help---
+		Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO
+
+config STM32_ADC3_SAMPLE_FREQUENCY
+	int "ADC3 Sampling Frequency"
+	default 100
+	depends on HAVE_ADC3_TIMER
+	---help---
+		ADC3 sampling frequency.  Default:  100Hz
+
+config STM32_ADC3_TIMTRIG
+	int "ADC3 Timer Trigger"
+	default 0
+	range 0 4
+	depends on HAVE_ADC3_TIMER
+	---help---
+		Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO
+
 config STM32_TIM1_DAC
 	bool "TIM1 DAC"
 	default n
@@ -1140,7 +1406,7 @@ config STM32_TIM2_DAC
 	default n
 	depends on STM32_TIM2 && STM32_DAC
 	---help---
-		Reserve timer 1 for use by DAC
+		Reserve timer 2 for use by DAC
 
 		Timer devices may be used for different purposes.  If STM32_TIM2 is
 		defined then the following may also be defined to indicate that the
@@ -1171,7 +1437,7 @@ config STM32_TIM3_DAC
 	default n
 	depends on STM32_TIM3 && STM32_DAC
 	---help---
-		Reserve timer 1 for use by DAC
+		Reserve timer 3 for use by DAC
 
 		Timer devices may be used for different purposes.  If STM32_TIM3 is
 		defined then the following may also be defined to indicate that the
@@ -1202,7 +1468,7 @@ config STM32_TIM4_DAC
 	default n
 	depends on STM32_TIM4 && STM32_DAC
 	---help---
-		Reserve timer 1 for use by DAC
+		Reserve timer 4 for use by DAC
 
 		Timer devices may be used for different purposes.  If STM32_TIM4 is
 		defined then the following may also be defined to indicate that the
@@ -1233,7 +1499,7 @@ config STM32_TIM5_DAC
 	default n
 	depends on STM32_TIM5 && STM32_DAC
 	---help---
-		Reserve timer 1 for use by DAC
+		Reserve timer 5 for use by DAC
 
 		Timer devices may be used for different purposes.  If STM32_TIM5 is
 		defined then the following may also be defined to indicate that the
@@ -1264,7 +1530,7 @@ config STM32_TIM6_DAC
 	default n
 	depends on STM32_TIM6 && STM32_DAC
 	---help---
-		Reserve timer 1 for use by DAC
+		Reserve timer 6 for use by DAC
 
 		Timer devices may be used for different purposes.  If STM32_TIM6 is
 		defined then the following may also be defined to indicate that the
@@ -1295,7 +1561,7 @@ config STM32_TIM7_DAC
 	default n
 	depends on STM32_TIM7 && STM32_DAC
 	---help---
-		Reserve timer 1 for use by DAC
+		Reserve timer 7 for use by DAC
 
 		Timer devices may be used for different purposes.  If STM32_TIM7 is
 		defined then the following may also be defined to indicate that the
@@ -1326,7 +1592,7 @@ config STM32_TIM8_DAC
 	default n
 	depends on STM32_TIM8 && STM32_DAC
 	---help---
-		Reserve timer 1 for use by DAC
+		Reserve timer 8 for use by DAC
 
 		Timer devices may be used for different purposes.  If STM32_TIM8 is
 		defined then the following may also be defined to indicate that the
@@ -1357,7 +1623,7 @@ config STM32_TIM9_DAC
 	default n
 	depends on STM32_TIM9 && STM32_DAC
 	---help---
-		Reserve timer 1 for use by DAC
+		Reserve timer 9 for use by DAC
 
 		Timer devices may be used for different purposes.  If STM32_TIM9 is
 		defined then the following may also be defined to indicate that the
@@ -1388,7 +1654,7 @@ config STM32_TIM10_DAC
 	default n
 	depends on STM32_TIM10 && STM32_DAC
 	---help---
-		Reserve timer 1 for use by DAC
+		Reserve timer 10 for use by DAC
 
 		Timer devices may be used for different purposes.  If STM32_TIM10 is
 		defined then the following may also be defined to indicate that the
@@ -1419,7 +1685,7 @@ config STM32_TIM11_DAC
 	default n
 	depends on STM32_TIM11 && STM32_DAC
 	---help---
-		Reserve timer 1 for use by DAC
+		Reserve timer 11 for use by DAC
 
 		Timer devices may be used for different purposes.  If STM32_TIM11 is
 		defined then the following may also be defined to indicate that the
@@ -1450,7 +1716,7 @@ config STM32_TIM12_DAC
 	default n
 	depends on STM32_TIM12 && STM32_DAC
 	---help---
-		Reserve timer 1 for use by DAC
+		Reserve timer 12 for use by DAC
 
 		Timer devices may be used for different purposes.  If STM32_TIM12 is
 		defined then the following may also be defined to indicate that the
@@ -1481,7 +1747,7 @@ config STM32_TIM13_DAC
 	default n
 	depends on STM32_TIM13 && STM32_DAC
 	---help---
-		Reserve timer 1 for use by DAC
+		Reserve timer 13 for use by DAC
 
 		Timer devices may be used for different purposes.  If STM32_TIM13 is
 		defined then the following may also be defined to indicate that the
@@ -1512,7 +1778,7 @@ config STM32_TIM14_DAC
 	default n
 	depends on STM32_TIM14 && STM32_DAC
 	---help---
-		Reserve timer 1 for use by DAC
+		Reserve timer 14 for use by DAC
 
 		Timer devices may be used for different purposes.  If STM32_TIM14 is
 		defined then the following may also be defined to indicate that the
@@ -1538,6 +1804,27 @@ config STM32_TIM14_DAC2
 
 endchoice
 
+menu "U[S]ART Configuration"
+	depends on STM32_USART1 || STM32_USART2 || STM32_USART3 || STM32_USART4 || STM32_USART5 || STM32_USART6
+
+config USART1_RS485
+	bool "RS-485 on USART1"
+	default n
+	depends on STM32_USART1
+	---help---
+		Enable RS-485 interface on USART1. Your board config will have to
+		provide GPIO_USART1_RS485_DIR pin definition. Currently it cannot be
+		used with USART1_RXDMA.
+
+config USART1_RS485_DIR_POLARITY
+	int "USART1 RS-485 DIR pin polarity"
+	default 1
+	range 0 1
+	depends on USART1_RS485
+	---help---
+		Polarity of DIR pin for RS-485 on USART1. Set to state on DIR pin which
+		enables TX (0 - low / nTXEN, 1 - high / TXEN).		
+
 config USART1_RXDMA
 	bool "USART1 Rx DMA"
 	default n
@@ -1545,6 +1832,24 @@ config USART1_RXDMA
 	---help---
 		In high data rate usage, Rx DMA may eliminate Rx overrun errors
 
+config USART2_RS485
+	bool "RS-485 on USART2"
+	default n
+	depends on STM32_USART2
+	---help---
+		Enable RS-485 interface on USART2. Your board config will have to
+		provide GPIO_USART2_RS485_DIR pin definition. Currently it cannot be
+		used with USART2_RXDMA.
+
+config USART2_RS485_DIR_POLARITY
+	int "USART2 RS-485 DIR pin polarity"
+	default 1
+	range 0 1
+	depends on USART2_RS485
+	---help---
+		Polarity of DIR pin for RS-485 on USART2. Set to state on DIR pin which
+		enables TX (0 - low / nTXEN, 1 - high / TXEN).
+
 config USART2_RXDMA
 	bool "USART2 Rx DMA"
 	default n
@@ -1552,6 +1857,24 @@ config USART2_RXDMA
 	---help---
 		In high data rate usage, Rx DMA may eliminate Rx overrun errors
 
+config USART3_RS485
+	bool "RS-485 on USART3"
+	default n
+	depends on STM32_USART3
+	---help---
+		Enable RS-485 interface on USART3. Your board config will have to
+		provide GPIO_USART3_RS485_DIR pin definition. Currently it cannot be
+		used with USART3_RXDMA.
+
+config USART3_RS485_DIR_POLARITY
+	int "USART3 RS-485 DIR pin polarity"
+	default 1
+	range 0 1
+	depends on USART3_RS485
+	---help---
+		Polarity of DIR pin for RS-485 on USART3. Set to state on DIR pin which
+		enables TX (0 - low / nTXEN, 1 - high / TXEN).
+
 config USART3_RXDMA
 	bool "USART3 Rx DMA"
 	default n
@@ -1559,6 +1882,24 @@ config USART3_RXDMA
 	---help---
 		In high data rate usage, Rx DMA may eliminate Rx overrun errors
 
+config UART4_RS485
+	bool "RS-485 on UART4"
+	default n
+	depends on STM32_UART4
+	---help---
+		Enable RS-485 interface on UART4. Your board config will have to
+		provide GPIO_UART4_RS485_DIR pin definition. Currently it cannot be
+		used with UART4_RXDMA.
+
+config UART4_RS485_DIR_POLARITY
+	int "UART4 RS-485 DIR pin polarity"
+	default 1
+	range 0 1
+	depends on UART4_RS485
+	---help---
+		Polarity of DIR pin for RS-485 on UART4. Set to state on DIR pin which
+		enables TX (0 - low / nTXEN, 1 - high / TXEN).
+
 config UART4_RXDMA
 	bool "UART4 Rx DMA"
 	default n
@@ -1566,6 +1907,24 @@ config UART4_RXDMA
 	---help---
 		In high data rate usage, Rx DMA may eliminate Rx overrun errors
 
+config UART5_RS485
+	bool "RS-485 on UART5"
+	default n
+	depends on STM32_UART5
+	---help---
+		Enable RS-485 interface on UART5. Your board config will have to
+		provide GPIO_UART5_RS485_DIR pin definition. Currently it cannot be
+		used with UART5_RXDMA.
+
+config UART5_RS485_DIR_POLARITY
+	int "UART5 RS-485 DIR pin polarity"
+	default 1
+	range 0 1
+	depends on UART5_RS485
+	---help---
+		Polarity of DIR pin for RS-485 on UART5. Set to state on DIR pin which
+		enables TX (0 - low / nTXEN, 1 - high / TXEN).
+
 config UART5_RXDMA
 	bool "UART5 Rx DMA"
 	default n
@@ -1573,6 +1932,24 @@ config UART5_RXDMA
 	---help---
 		In high data rate usage, Rx DMA may eliminate Rx overrun errors
 
+config USART6_RS485
+	bool "RS-485 on USART6"
+	default n
+	depends on STM32_USART6
+	---help---
+		Enable RS-485 interface on USART6. Your board config will have to
+		provide GPIO_USART6_RS485_DIR pin definition. Currently it cannot be
+		used with USART6_RXDMA.
+
+config USART6_RS485_DIR_POLARITY
+	int "USART6 RS-485 DIR pin polarity"
+	default 1
+	range 0 1
+	depends on USART6_RS485
+	---help---
+		Polarity of DIR pin for RS-485 on USART6. Set to state on DIR pin which
+		enables TX (0 - low / nTXEN, 1 - high / TXEN).
+
 config USART6_RXDMA
 	bool "USART6 Rx DMA"
 	default n
@@ -1589,6 +1966,8 @@ config SERIAL_TERMIOS
 		If this is not defined, then the terminal settings (baud, parity, etc).
 		are not configurable at runtime; serial streams cannot be flushed, etc..
 
+endmenu
+
 menu "SPI Configuration"
 	depends on STM32_SPI
 
@@ -1688,6 +2067,16 @@ config STM32_PHYADDR
 	---help---
 		The 5-bit address of the PHY on the board.  Default: 1
 
+config STM32_PHYINIT
+	bool "Board-specific PHY Initialization"
+	default n
+	---help---
+		Some boards require specialized initialization of the PHY before it can be used.
+		This may include such things as configuring GPIOs, resetting the PHY, etc.  If
+		STM32_PHYINIT is defined in the configuration then the board specific logic must
+		provide stm32_phyinitialize();  The STM32 Ethernet driver will call this function
+		one time before it first uses the PHY.
+
 config STM32_MII
 	bool "Use MII interface"
 	default n
@@ -1899,14 +2288,14 @@ config STM32_OTGFS_NPTXFIFO_SIZE
 	depends on USBHOST && STM32_OTGFS
 	---help---
 		Size of the non-periodic Tx FIFO in 32-bit words.  Default 96 (384 bytes)
- 
+
 config STM32_OTGFS_PTXFIFO_SIZE
 	int "Periodic Tx FIFO size"
 	default 128
 	depends on USBHOST && STM32_OTGFS
 	---help---
 		Size of the periodic Tx FIFO in 32-bit words.  Default 96 (384 bytes)
- 
+
 config STM32_OTGFS_DESCSIZE
 	int "Descriptor Size"
 	default 128
@@ -1920,14 +2309,14 @@ config STM32_OTGFS_SOFINTR
 	depends on USBHOST && STM32_OTGFS
 	---help---
 		Enable SOF interrupts.  Why would you ever want to do that?
- 
+
 config STM32_USBHOST_REGDEBUG
 	bool "Register-Level Debug"
 	default n
 	depends on USBHOST && STM32_OTGFS
 	---help---
 		Enable very low-level register access debug.  Depends on DEBUG.
- 
+
 config STM32_USBHOST_PKTDUMP
 	bool "Packet Dump Debug"
 	default n
diff --git a/nuttx/arch/arm/src/stm32/Make.defs b/nuttx/arch/arm/src/stm32/Make.defs
index 54067a168..baa751c7d 100644
--- a/nuttx/arch/arm/src/stm32/Make.defs
+++ b/nuttx/arch/arm/src/stm32/Make.defs
@@ -41,36 +41,40 @@ endif
 
 CMN_ASRCS	= up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S
 CMN_CSRCS	= up_assert.c up_blocktask.c up_copystate.c \
-		  up_createstack.c up_mdelay.c up_udelay.c up_exit.c \
-		  up_initialize.c up_initialstate.c up_interruptcontext.c \
-		  up_memfault.c up_modifyreg8.c up_modifyreg16.c up_modifyreg32.c \
-		  up_releasepending.c up_releasestack.c up_reprioritizertr.c \
-		  up_schedulesigaction.c up_sigdeliver.c up_systemreset.c \
-		  up_unblocktask.c up_usestack.c up_doirq.c up_hardfault.c up_svcall.c \
-		  up_stackcheck.c
+			  up_createstack.c up_mdelay.c up_udelay.c up_exit.c \
+			  up_initialize.c up_initialstate.c up_interruptcontext.c \
+			  up_memfault.c up_modifyreg8.c up_modifyreg16.c up_modifyreg32.c \
+			  up_releasepending.c up_releasestack.c up_reprioritizertr.c \
+			  up_schedulesigaction.c up_sigdeliver.c up_systemreset.c \
+			  up_unblocktask.c up_usestack.c up_doirq.c up_hardfault.c up_svcall.c \
+			  up_stackcheck.c
 
 ifeq ($(CONFIG_ARMV7M_CMNVECTOR),y)
 CMN_ASRCS	+= up_exception.S
 CMN_CSRCS	+= up_vectors.c
 endif
 
+ifeq ($(CONFIG_ARCH_MEMCPY),y)
+CMN_ASRCS	+= up_memcpy.S
+endif
+
 ifeq ($(CONFIG_DEBUG_STACK),y)
 CMN_CSRCS	+= up_checkstack.c
 endif
 
-ifeq ($(CONFIG_ARCH_FPU),y)
-CMN_ASRCS	+= up_fpu.S
+ifeq ($(CONFIG_ELF),y)
+CMN_CSRCS += up_elf.c
 endif
 
-ifeq ($(CONFIG_ARCH_MEMCPY),y)
-CMN_ASRCS	+= memcpy.S
+ifeq ($(CONFIG_ARCH_FPU),y)
+CMN_ASRCS	+= up_fpu.S
 endif
 
 CHIP_ASRCS	= 
 CHIP_CSRCS	= stm32_allocateheap.c stm32_start.c stm32_rcc.c stm32_lse.c \
-		  stm32_lsi.c stm32_gpio.c stm32_exti_gpio.c stm32_flash.c stm32_irq.c \
-		  stm32_timerisr.c stm32_dma.c stm32_lowputc.c stm32_serial.c \
-		  stm32_spi.c stm32_sdio.c stm32_tim.c stm32_i2c.c stm32_waste.c
+			  stm32_lsi.c stm32_gpio.c stm32_exti_gpio.c stm32_flash.c stm32_irq.c \
+			  stm32_timerisr.c stm32_dma.c stm32_lowputc.c stm32_serial.c \
+			  stm32_spi.c stm32_sdio.c stm32_tim.c stm32_i2c.c stm32_waste.c
 
 ifeq ($(CONFIG_USBDEV),y)
 ifeq ($(CONFIG_STM32_USB),y)
diff --git a/nuttx/arch/arm/src/stm32/chip/stm32_eth.h b/nuttx/arch/arm/src/stm32/chip/stm32_eth.h
index a4a109d01..92a229ccc 100644
--- a/nuttx/arch/arm/src/stm32/chip/stm32_eth.h
+++ b/nuttx/arch/arm/src/stm32/chip/stm32_eth.h
@@ -835,14 +835,6 @@ struct eth_rxdesc_s
  * Public Functions
  ****************************************************************************************************/
 
-#undef EXTERN
-#if defined(__cplusplus)
-#define EXTERN extern "C"
-extern "C" {
-#else
-#define EXTERN extern
-#endif
-
 #endif /* __ASSEMBLY__ */
 #endif /* STM32_NETHERNET > 0 */
 #endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_ETH_H */
diff --git a/nuttx/arch/arm/src/stm32/chip/stm32_flash.h b/nuttx/arch/arm/src/stm32/chip/stm32_flash.h
index c2e440923..d6fcecc11 100644
--- a/nuttx/arch/arm/src/stm32/chip/stm32_flash.h
+++ b/nuttx/arch/arm/src/stm32/chip/stm32_flash.h
@@ -110,6 +110,7 @@
 #  define FLASH_ACR_HLFCYA          (1 << 3)                /* FLASH half cycle access */
 #  define FLASH_ACR_PRTFBE          (1 << 4)                /* FLASH prefetch enable */
 #elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
+#  define FLASH_ACR_PRFTEN          (1 << 8)                /* FLASH prefetch enable */
 #  define FLASH_ACR_ICEN            (1 << 9)                /* Bit 9: Instruction cache enable */
 #  define FLASH_ACR_DCEN            (1 << 10)               /* Bit 10: Data cache enable */
 #  define FLASH_ACR_ICRST           (1 << 11)               /* Bit 11: Instruction cache reset */
diff --git a/nuttx/arch/arm/src/stm32/chip/stm32f100_pinmap.h b/nuttx/arch/arm/src/stm32/chip/stm32f100_pinmap.h
index 01d6e1ce0..addef0265 100644
--- a/nuttx/arch/arm/src/stm32/chip/stm32f100_pinmap.h
+++ b/nuttx/arch/arm/src/stm32/chip/stm32f100_pinmap.h
@@ -6,6 +6,8 @@
  *   Copyright (C) 2012 Michael Smith. All Rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
  *           Uros Platise <uros.platise@isotel.eu>
+ *           Michael Smith
+ *           Freddie Chopin <freddie_chopin@op.pl>
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -49,6 +51,87 @@
  * Pre-processor Definitions
  ************************************************************************************/
 
+/* Alternate Pin Functions: */
+
+/* ADC */
+
+#define GPIO_ADC1_IN0       (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN0)
+#define GPIO_ADC1_IN1       (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN1)
+#define GPIO_ADC1_IN2       (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN2)
+#define GPIO_ADC1_IN3       (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN3)
+#define GPIO_ADC1_IN4       (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN4)
+#define GPIO_ADC1_IN5       (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN5)
+#define GPIO_ADC1_IN6       (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN6)
+#define GPIO_ADC1_IN7       (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN7)
+#define GPIO_ADC1_IN8       (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN0)
+#define GPIO_ADC1_IN9       (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN1)
+#define GPIO_ADC1_IN10      (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN0)
+#define GPIO_ADC1_IN11      (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN1)
+#define GPIO_ADC1_IN12      (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN2)
+#define GPIO_ADC1_IN13      (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN3)
+#define GPIO_ADC1_IN14      (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN4)
+#define GPIO_ADC1_IN15      (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN5)
+
+/* CEC */
+#if defined(CONFIG_STM32_CEC_REMAP)
+#  define GPIO_CEC          (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN10)
+#else
+#  define GPIO_CEC          (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN8)
+#endif
+
+/* DAC
+ * Note from RM0041, 11.2: "Once the DAC channelx is enabled, the corresponding
+ * GPIO pin (PA4 or PA5) is automatically connected to the analog converter
+ * output (DAC_OUTx). In order to avoid parasitic consumption, the PA4 or PA5
+ * pin should first be configured to analog (AIN)."
+ */
+
+#define GPIO_DAC_OUT1       (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN4)
+#define GPIO_DAC_OUT2       (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN5)
+
+/* FSMC */
+
+/* TODO - VL devices in 100- and 144-pin packages have FSMC */
+
+/* I2C */
+
+#if defined(CONFIG_STM32_I2C1_REMAP)
+#  define GPIO_I2C1_SCL     (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN8)
+#  define GPIO_I2C1_SDA     (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN9)
+#else
+#  define GPIO_I2C1_SCL     (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN6)
+#  define GPIO_I2C1_SDA     (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN7)
+#endif
+#define GPIO_I2C1_SMBA      (GPIO_ALT|GPIO_CNF_INFLOAT|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN5)
+
+#define GPIO_I2C2_SCL       (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN10)
+#define GPIO_I2C2_SDA       (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN11)
+#define GPIO_I2C2_SMBA      (GPIO_ALT|GPIO_CNF_INFLOAT|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN12)
+
+/* SPI */
+
+#if defined(CONFIG_STM32_SPI1_REMAP)
+#  define GPIO_SPI1_NSS     (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN15)
+#  define GPIO_SPI1_SCK     (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN3)
+#  define GPIO_SPI1_MISO    (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN4)
+#  define GPIO_SPI1_MOSI    (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN5)
+#else
+#  define GPIO_SPI1_NSS     (GPIO_INPUT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN4)
+#  define GPIO_SPI1_SCK     (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN5)
+#  define GPIO_SPI1_MISO    (GPIO_INPUT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN6)
+#  define GPIO_SPI1_MOSI    (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN7)
+#endif
+
+#define GPIO_SPI2_NSS       (GPIO_INPUT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN12)
+#define GPIO_SPI2_SCK       (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN13)
+#define GPIO_SPI2_MISO      (GPIO_INPUT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN14)
+#define GPIO_SPI2_MOSI      (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN15)
+
+#define GPIO_SPI3_NSS       (GPIO_INPUT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN15)
+#define GPIO_SPI3_SCK       (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN3)
+#define GPIO_SPI3_MISO      (GPIO_INPUT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN4)
+#define GPIO_SPI3_MOSI      (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN5)
+
 /* TIMERS */
 
 #if defined(CONFIG_STM32_TIM1_FULL_REMAP)
@@ -186,6 +269,77 @@
 #  define GPIO_TIM4_CH4OUT  (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN9)
 #endif
 
+#define GPIO_TIM5_CH1IN     (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN0)
+#define GPIO_TIM5_CH1OUT    (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN0)
+#define GPIO_TIM5_CH2IN     (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN1)
+#define GPIO_TIM5_CH2OUT    (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN1)
+#define GPIO_TIM5_CH3IN     (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN2)
+#define GPIO_TIM5_CH3OUT    (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN2)
+#define GPIO_TIM5_CH4IN     (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN3)
+#define GPIO_TIM5_CH4OUT    (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN3)
+
+#if defined(CONFIG_STM32_TIM12_REMAP)
+#  define GPIO_TIM12_CH1IN  (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN12)
+#  define GPIO_TIM12_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN12)
+#  define GPIO_TIM12_CH2IN  (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN13)
+#  define GPIO_TIM12_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN13)
+#else
+#  define GPIO_TIM12_CH1IN  (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN4)
+#  define GPIO_TIM12_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN4)
+#  define GPIO_TIM12_CH2IN  (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN5)
+#  define GPIO_TIM12_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN5)
+#endif
+
+#if defined(CONFIG_STM32_TIM13_REMAP)
+#  define GPIO_TIM13_CH1IN  (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN0)
+#  define GPIO_TIM13_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN0)
+#else
+#  define GPIO_TIM13_CH1IN  (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN8)
+#  define GPIO_TIM13_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN8)
+#endif
+
+#if defined(CONFIG_STM32_TIM14_REMAP)
+#  define GPIO_TIM14_CH1IN  (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN1)
+#  define GPIO_TIM14_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN1)
+#else
+#  define GPIO_TIM14_CH1IN  (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN9)
+#  define GPIO_TIM14_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN9)
+#endif
+
+#if defined(CONFIG_STM32_TIM15_REMAP)
+#  define GPIO_TIM15_CH1IN  (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN14)
+#  define GPIO_TIM15_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN14)
+#  define GPIO_TIM15_CH2IN  (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN15)
+#  define GPIO_TIM15_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN15)
+#else
+#  define GPIO_TIM15_CH1IN  (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN2)
+#  define GPIO_TIM15_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN2)
+#  define GPIO_TIM15_CH2IN  (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN3)
+#  define GPIO_TIM15_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN3)
+#endif
+#define GPIO_TIM15_BKIN     (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN9)
+#define GPIO_TIM15_CH1N     (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN15)
+
+#if defined(CONFIG_STM32_TIM16_REMAP)
+#  define GPIO_TIM16_CH1IN  (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN6)
+#  define GPIO_TIM16_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN6)
+#else
+#  define GPIO_TIM16_CH1IN  (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN8)
+#  define GPIO_TIM16_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN8)
+#endif
+#define GPIO_TIM16_BKIN     (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN5)
+#define GPIO_TIM16_CH1N     (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN6)
+
+#if defined(CONFIG_STM32_TIM17_REMAP)
+#  define GPIO_TIM17_CH1IN  (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN7)
+#  define GPIO_TIM17_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN7)
+#else
+#  define GPIO_TIM17_CH1IN  (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN9)
+#  define GPIO_TIM17_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN9)
+#endif
+#define GPIO_TIM17_BKIN     (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN10)
+#define GPIO_TIM17_CH1N     (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN7)
+
 /* USART */
 
 #if defined(CONFIG_STM32_USART1_REMAP)
@@ -230,38 +384,10 @@
 #  define GPIO_USART3_RTS   (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN14)
 #endif
 
-/* SPI */
-
-#if defined(CONFIG_STM32_SPI1_REMAP)
-#  define GPIO_SPI1_NSS     (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN15)
-#  define GPIO_SPI1_SCK     (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN3)
-#  define GPIO_SPI1_MISO    (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN4)
-#  define GPIO_SPI1_MOSI    (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN5)
-#else
-#  define GPIO_SPI1_NSS     (GPIO_INPUT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN4)
-#  define GPIO_SPI1_SCK     (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN5)
-#  define GPIO_SPI1_MISO    (GPIO_INPUT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN6)
-#  define GPIO_SPI1_MOSI    (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN7)
-#endif
-
-#define GPIO_SPI2_NSS       (GPIO_INPUT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN12)
-#define GPIO_SPI2_SCK       (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN13)
-#define GPIO_SPI2_MISO      (GPIO_INPUT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN14)
-#define GPIO_SPI2_MOSI      (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN15)
-
-/* I2C */
-
-#if defined(CONFIG_STM32_I2C1_REMAP)
-#  define GPIO_I2C1_SCL     (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN8)
-#  define GPIO_I2C1_SDA     (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN9)
-#else
-#  define GPIO_I2C1_SCL     (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN6)
-#  define GPIO_I2C1_SDA     (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN7)
-#endif
-#define GPIO_I2C1_SMBA    (GPIO_ALT|GPIO_CNF_INFLOAT|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN5)
+#define GPIO_UART4_TX       (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN10)
+#define GPIO_UART4_RX       (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN11)
 
-#define GPIO_I2C2_SCL     (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN10)
-#define GPIO_I2C2_SDA     (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN11)
-#define GPIO_I2C2_SMBA    (GPIO_ALT|GPIO_CNF_INFLOAT|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN12)
+#define GPIO_UART5_TX       (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN12)
+#define GPIO_UART5_RX       (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTD|GPIO_PIN2)
 
 #endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F100_PINMAP_H */
diff --git a/nuttx/arch/arm/src/stm32/chip/stm32f103vc_pinmap.h b/nuttx/arch/arm/src/stm32/chip/stm32f103vc_pinmap.h
index 160676802..52a513215 100644
--- a/nuttx/arch/arm/src/stm32/chip/stm32f103vc_pinmap.h
+++ b/nuttx/arch/arm/src/stm32/chip/stm32f103vc_pinmap.h
@@ -129,7 +129,7 @@
 
 
 #if 0 /* Needs further investigation */
-#define GPIO_DAC_OUT1           (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUTz|GPIO_PORTA|GPIO_PIN4)
+#define GPIO_DAC_OUT1           (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN4)
 #define GPIO_DAC_OUT2           (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN5)
 #endif
 
diff --git a/nuttx/arch/arm/src/stm32/chip/stm32f103ze_pinmap.h b/nuttx/arch/arm/src/stm32/chip/stm32f103ze_pinmap.h
index 9bcee49f5..581b026a0 100644
--- a/nuttx/arch/arm/src/stm32/chip/stm32f103ze_pinmap.h
+++ b/nuttx/arch/arm/src/stm32/chip/stm32f103ze_pinmap.h
@@ -50,53 +50,53 @@
 
 /* ADC */
 
-#define GPIO_ADC1_IN0       (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN0)
-#define GPIO_ADC1_IN1       (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN1)
-#define GPIO_ADC1_IN2       (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN2)
-#define GPIO_ADC1_IN3       (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN3)
-#define GPIO_ADC1_IN4       (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN4)
-#define GPIO_ADC1_IN5       (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN5)
-#define GPIO_ADC1_IN6       (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN6)
-#define GPIO_ADC1_IN7       (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN7)
-#define GPIO_ADC1_IN8       (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN0)
-#define GPIO_ADC1_IN9       (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN1)
-#define GPIO_ADC1_IN10      (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN0)
-#define GPIO_ADC1_IN11      (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN1)
-#define GPIO_ADC1_IN12      (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN2)
-#define GPIO_ADC1_IN13      (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN3)
-#define GPIO_ADC1_IN14      (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN4)
-#define GPIO_ADC1_IN15      (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN5)
-
-#define GPIO_ADC2_IN0       (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN0)
-#define GPIO_ADC2_IN1       (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN1)
-#define GPIO_ADC2_IN2       (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN2)
-#define GPIO_ADC2_IN3       (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN3)
-#define GPIO_ADC2_IN4       (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN4)
-#define GPIO_ADC2_IN5       (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN5)
-#define GPIO_ADC2_IN6       (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN6)
-#define GPIO_ADC2_IN7       (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN7)
-#define GPIO_ADC2_IN8       (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN0)
-#define GPIO_ADC2_IN9       (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN1)
-#define GPIO_ADC2_IN10      (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN0)
-#define GPIO_ADC2_IN11      (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN1)
-#define GPIO_ADC2_IN12      (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN2)
-#define GPIO_ADC2_IN13      (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN3)
-#define GPIO_ADC2_IN14      (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN4)
-#define GPIO_ADC2_IN15      (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN5)
-
-#define GPIO_ADC3_IN0       (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN0)
-#define GPIO_ADC3_IN1       (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN1)
-#define GPIO_ADC3_IN2       (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN2)
-#define GPIO_ADC3_IN3       (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN3)
-#define GPIO_ADC3_IN4       (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTF|GPIO_PIN6)
-#define GPIO_ADC3_IN5       (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTF|GPIO_PIN7)
-#define GPIO_ADC3_IN6       (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTF|GPIO_PIN8)
-#define GPIO_ADC3_IN7       (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTF|GPIO_PIN9)
-#define GPIO_ADC3_IN8       (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTF|GPIO_PIN10)
-#define GPIO_ADC3_IN10      (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN0)
-#define GPIO_ADC3_IN11      (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN1)
-#define GPIO_ADC3_IN12      (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN2)
-#define GPIO_ADC3_IN13      (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN3)
+#define GPIO_ADC1_IN0       (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN0)
+#define GPIO_ADC1_IN1       (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN1)
+#define GPIO_ADC1_IN2       (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN2)
+#define GPIO_ADC1_IN3       (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN3)
+#define GPIO_ADC1_IN4       (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN4)
+#define GPIO_ADC1_IN5       (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN5)
+#define GPIO_ADC1_IN6       (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN6)
+#define GPIO_ADC1_IN7       (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN7)
+#define GPIO_ADC1_IN8       (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN0)
+#define GPIO_ADC1_IN9       (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN1)
+#define GPIO_ADC1_IN10      (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN0)
+#define GPIO_ADC1_IN11      (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN1)
+#define GPIO_ADC1_IN12      (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN2)
+#define GPIO_ADC1_IN13      (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN3)
+#define GPIO_ADC1_IN14      (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN4)
+#define GPIO_ADC1_IN15      (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN5)
+
+#define GPIO_ADC2_IN0       (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN0)
+#define GPIO_ADC2_IN1       (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN1)
+#define GPIO_ADC2_IN2       (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN2)
+#define GPIO_ADC2_IN3       (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN3)
+#define GPIO_ADC2_IN4       (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN4)
+#define GPIO_ADC2_IN5       (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN5)
+#define GPIO_ADC2_IN6       (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN6)
+#define GPIO_ADC2_IN7       (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN7)
+#define GPIO_ADC2_IN8       (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN0)
+#define GPIO_ADC2_IN9       (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN1)
+#define GPIO_ADC2_IN10      (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN0)
+#define GPIO_ADC2_IN11      (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN1)
+#define GPIO_ADC2_IN12      (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN2)
+#define GPIO_ADC2_IN13      (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN3)
+#define GPIO_ADC2_IN14      (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN4)
+#define GPIO_ADC2_IN15      (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN5)
+
+#define GPIO_ADC3_IN0       (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN0)
+#define GPIO_ADC3_IN1       (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN1)
+#define GPIO_ADC3_IN2       (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN2)
+#define GPIO_ADC3_IN3       (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN3)
+#define GPIO_ADC3_IN4       (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTF|GPIO_PIN6)
+#define GPIO_ADC3_IN5       (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTF|GPIO_PIN7)
+#define GPIO_ADC3_IN6       (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTF|GPIO_PIN8)
+#define GPIO_ADC3_IN7       (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTF|GPIO_PIN9)
+#define GPIO_ADC3_IN8       (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTF|GPIO_PIN10)
+#define GPIO_ADC3_IN10      (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN0)
+#define GPIO_ADC3_IN11      (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN1)
+#define GPIO_ADC3_IN12      (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN2)
+#define GPIO_ADC3_IN13      (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN3)
 
 /* DAC - "Once the DAC channelx is enabled, the corresponding GPIO pin
  * (PA4 or PA5) is automatically connected to the analog converter output
@@ -104,8 +104,8 @@
  * should first be configured to analog (AIN)."
  */
 
-#define GPIO_DAC_OUT1       (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTF|GPIO_PIN10)
-#define GPIO_DAC_OUT2       (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PIN10)
+#define GPIO_DAC_OUT1       (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN4)
+#define GPIO_DAC_OUT2       (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN5)
 
 /* TIMERS */
 
diff --git a/nuttx/arch/arm/src/stm32/chip/stm32f105vb_pinmap.h b/nuttx/arch/arm/src/stm32/chip/stm32f105vb_pinmap.h
index 7a5ec3381..054a7337d 100644
--- a/nuttx/arch/arm/src/stm32/chip/stm32f105vb_pinmap.h
+++ b/nuttx/arch/arm/src/stm32/chip/stm32f105vb_pinmap.h
@@ -85,7 +85,7 @@
 #endif
 
 #if 0 /* Needs further investigation */
-#define GPIO_DAC_OUT1           (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUTz|GPIO_PORTA|GPIO_PIN4)
+#define GPIO_DAC_OUT1           (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN4)
 #define GPIO_DAC_OUT2           (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN5)
 #endif
 
diff --git a/nuttx/arch/arm/src/stm32/chip/stm32f107vc_pinmap.h b/nuttx/arch/arm/src/stm32/chip/stm32f107vc_pinmap.h
index 9bbc21479..2419620fc 100644
--- a/nuttx/arch/arm/src/stm32/chip/stm32f107vc_pinmap.h
+++ b/nuttx/arch/arm/src/stm32/chip/stm32f107vc_pinmap.h
@@ -85,7 +85,7 @@
 #endif
 
 #if 0 /* Needs further investigation */
-#define GPIO_DAC_OUT1           (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUTz|GPIO_PORTA|GPIO_PIN4)
+#define GPIO_DAC_OUT1           (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN4)
 #define GPIO_DAC_OUT2           (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN5)
 #endif
 
diff --git a/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_gpio.h b/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_gpio.h
index a95d13100..d339fc15e 100644
--- a/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_gpio.h
+++ b/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_gpio.h
@@ -59,6 +59,7 @@
 #define STM32_AFIO_EXTICR2_OFFSET    0x000c  /* External interrupt configuration register 2 */
 #define STM32_AFIO_EXTICR3_OFFSET    0x0010  /* External interrupt configuration register 3 */
 #define STM32_AFIO_EXTICR4_OFFSET    0x0014  /* External interrupt configuration register 4 */
+#define STM32_AFIO_MAPR2_OFFSET      0x001c  /* AF remap and debug I/O configuration register 2 */
 
 /* Register Addresses ***************************************************************/
 
@@ -373,5 +374,27 @@
 #define AFIO_EXTICR4_EXTI15_SHIFT    (12)      /* Bits 15-12: EXTI 15 configuration */
 #define AFIO_EXTICR4_EXTI15_MASK     (AFIO_EXTICR_PORT_MASK << AFIO_EXTICR4_EXTI15_SHIFT)
 
+/* AF remap and debug I/O configuration register 2 */
+
+#ifdef CONFIG_STM32_VALUELINE
+#  define AFIO_MAPR2_TIM15_REMAP         (1 << 0)   /* Bit 0: TIM15 remapping */
+#  define AFIO_MAPR2_TIM16_REMAP         (1 << 1)   /* Bit 1: TIM16 remapping */
+#  define AFIO_MAPR2_TIM17_REMAP         (1 << 2)   /* Bit 2: TIM17 remapping */
+#  define AFIO_MAPR2_CEC_REMAP           (1 << 3)   /* Bit 3: CEC remapping */
+#  define AFIO_MAPR2_TIM1_DMA_REMAP      (1 << 4)   /* Bit 4: TIM1 DMA remapping */
+#else
+#  define AFIO_MAPR2_TIM9_REMAP          (1 << 5)   /* Bit 5: TIM9 remapping */
+#  define AFIO_MAPR2_TIM10_REMAP         (1 << 6)   /* Bit 6: TIM10 remapping */
+#  define AFIO_MAPR2_TIM11_REMAP         (1 << 7)   /* Bit 7: TIM11 remapping */
+#endif
+#define AFIO_MAPR2_TIM13_REMAP           (1 << 8)   /* Bit 8: TIM13 remapping */
+#define AFIO_MAPR2_TIM14_REMAP           (1 << 9)   /* Bit 9: TIM14 remapping */
+#define AFIO_MAPR2_FSMC_NADV             (1 << 10)  /* Bit 10: NADV connect/disconnect */
+#ifdef CONFIG_STM32_VALUELINE
+#  define AFIO_MAPR2_TIM67_DAC_DMA_REMAP (1 << 11)  /* Bit 11: TIM67_DAC DMA remapping */
+#  define AFIO_MAPR2_TIM12_REMAP         (1 << 12)  /* Bit 12: TIM12 remapping */
+#  define AFIO_MAPR2_MISC_REMAP          (1 << 13)  /* Bit 13: Miscellaneous features remapping */
+#endif
+
 #endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F10XXX_GPIO_H */
 
diff --git a/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_memorymap.h b/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_memorymap.h
index ed1bc2625..a1d2e26d3 100644
--- a/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_memorymap.h
+++ b/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_memorymap.h
@@ -60,7 +60,9 @@
 #define STM32_TIM5_BASE      0x40000c00     /* 0x40000c00 - 0x40000fff: TIM5 timer */
 #define STM32_TIM6_BASE      0x40001000     /* 0x40001000 - 0x400013ff: TIM6 timer */
 #define STM32_TIM7_BASE      0x40001400     /* 0x40001400 - 0x400007ff: TIM7 timer */
-                                            /* 0x40001800 - 0x40000fff: Reserved */
+#define STM32_TIM12_BASE     0x40001800     /* 0x40001800 - 0x40001bff: TIM12 timer */
+#define STM32_TIM13_BASE     0x40001c00     /* 0x40001c00 - 0x40001fff: TIM13 timer */
+#define STM32_TIM14_BASE     0x40002000     /* 0x40002000 - 0x400023ff: TIM14 timer */
 #define STM32_RTC_BASE       0x40002800     /* 0x40002800 - 0x40002bff: RTC */
 #define STM32_WWDG_BASE      0x40002c00     /* 0x40002C00 - 0x40002fff: Window watchdog (WWDG) */
 #define STM32_IWDG_BASE      0x40003000     /* 0x40003000 - 0x400033ff: Independent watchdog (IWDG) */
@@ -83,8 +85,8 @@
 #define STM32_BKP_BASE       0x40006c00     /* 0x40006c00 - 0x40006fff: Backup registers (BKP) */
 #define STM32_PWR_BASE       0x40007000     /* 0x40007000 - 0x400073ff: Power control PWR */
 #define STM32_DAC_BASE       0x40007400     /* 0x40007400 - 0x400077ff: DAC */
-                                            /* 0x40007800 - 0x4000ffff: Reserved */
-
+#define STM32_CEC_BASE       0x40007800     /* 0x40007800 - 0x40007bff: CEC */
+                                            /* 0x40007c00 - 0x4000ffff: Reserved */
 /* APB2 bus */
 
 #define STM32_AFIO_BASE      0x40010000     /* 0x40010000 - 0x400103ff: AFIO */
@@ -102,44 +104,49 @@
 #define STM32_SPI1_BASE      0x40013000     /* 0x40013000 - 0x400133ff: SPI1 */
 #define STM32_TIM8_BASE      0x40013400     /* 0x40013400 - 0x400137ff: TIM8 timer */
 #define STM32_USART1_BASE    0x40013800     /* 0x40013800 - 0x40013bff: USART1 */
-#define STM32_ADC3_BASE      0x40012800     /* 0x40012800 - 0x40013fff: ADC3 */
-                                            /* 0x40014000 - 0x40017fff: Reserved */
+#define STM32_ADC3_BASE      0x40012800     /* 0x40012800 - 0x40013c00: ADC3 */
+                                            /* 0x40013c00 - 0x40013fff: Reserved */
+#define STM32_TIM15_BASE     0x40014400     /* 0x40014400 - 0x400147ff: TIM15 */
+#define STM32_TIM16_BASE     0x40014400     /* 0x40014400 - 0x400147ff: TIM16 */
+#define STM32_TIM17_BASE     0x40014800     /* 0x40014800 - 0x40014bff: TIM17 */
+                                            /* 0x40014c00 - 0x4001ffff: Reserved */
+
 /* AHB bus */
 
-#define STM32_SDIO_BASE     0x40018000     /* 0x40018000 - 0x400183ff: SDIO  */
-                                           /* 0x40018400 - 0x40017fff: Reserved */
-#define STM32_DMA1_BASE     0x40020000     /* 0x40020000 - 0x400203ff: DMA1  */
-#define STM32_DMA2_BASE     0x40020400     /* 0x40020000 - 0x400207ff: DMA2  */
-                                           /* 0x40020800 - 0x40020fff: Reserved */
-#define STM32_RCC_BASE      0x40021000     /* 0x40021000 - 0x400213ff: Reset and Clock control RCC */
-                                           /* 0x40021400 - 0x40021fff:  Reserved */
-#define STM32_OTGFS_BASE    0x50000000     /* 0x50000000 - 0x500003ff: USB OTG FS */
-#define STM32_FLASHIF_BASE  0x40022000     /* 0x40022000 - 0x400223ff: Flash memory interface */
-#define STM32_CRC_BASE      0x40028000     /* 0x40023000 - 0x400233ff: CRC */
-                                           /* 0x40023400 - 0x40027fff: Reserved */
-#define STM32_ETHERNET_BASE 0x40028000     /* 0x40028000 - 0x40029fff: Ethernet */
-                                           /* 0x40030000 - 0x4fffffff: Reserved */
+#define STM32_SDIO_BASE      0x40018000     /* 0x40018000 - 0x400183ff: SDIO  */
+                                            /* 0x40018400 - 0x40017fff: Reserved */
+#define STM32_DMA1_BASE      0x40020000     /* 0x40020000 - 0x400203ff: DMA1  */
+#define STM32_DMA2_BASE      0x40020400     /* 0x40020000 - 0x400207ff: DMA2  */
+                                            /* 0x40020800 - 0x40020fff: Reserved */
+#define STM32_RCC_BASE       0x40021000     /* 0x40021000 - 0x400213ff: Reset and Clock control RCC */
+                                            /* 0x40021400 - 0x40021fff:  Reserved */
+#define STM32_OTGFS_BASE     0x50000000     /* 0x50000000 - 0x500003ff: USB OTG FS */
+#define STM32_FLASHIF_BASE   0x40022000     /* 0x40022000 - 0x400223ff: Flash memory interface */
+#define STM32_CRC_BASE       0x40028000     /* 0x40023000 - 0x400233ff: CRC */
+                                            /* 0x40023400 - 0x40027fff: Reserved */
+#define STM32_ETHERNET_BASE  0x40028000     /* 0x40028000 - 0x40029fff: Ethernet */
+                                            /* 0x40030000 - 0x4fffffff: Reserved */
 
 /* Peripheral BB base */
 
-#define STM32_PERIPHBB_BASE 0x42000000
+#define STM32_PERIPHBB_BASE  0x42000000
 
 /* Flexible SRAM controller (FSMC) */
 
-#define STM32_FSMC_BANK1    0x60000000     /* 0x60000000-0x6fffffff: 256Mb NOR/SRAM */
-#define STM32_FSMC_BANK2    0x70000000     /* 0x70000000-0x7fffffff: 256Mb NAND FLASH */
-#define STM32_FSMC_BANK3    0x80000000     /* 0x80000000-0x8fffffff: 256Mb  NAND FLASH */
-#define STM32_FSMC_BANK4    0x90000000     /* 0x90000000-0x9fffffff: 256Mb PC CARD*/
-#define STM32_IS_EXTSRAM(a) ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_FSMC_BANK1)
+#define STM32_FSMC_BANK1     0x60000000     /* 0x60000000-0x6fffffff: 256Mb NOR/SRAM */
+#define STM32_FSMC_BANK2     0x70000000     /* 0x70000000-0x7fffffff: 256Mb NAND FLASH */
+#define STM32_FSMC_BANK3     0x80000000     /* 0x80000000-0x8fffffff: 256Mb  NAND FLASH */
+#define STM32_FSMC_BANK4     0x90000000     /* 0x90000000-0x9fffffff: 256Mb PC CARD*/
+#define STM32_IS_EXTSRAM(a)  ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_FSMC_BANK1)
 
-#define STM32_FSMC_BASE     0xa0000000     /* 0xa0000000-0xbfffffff: 512Mb FSMC register block */
+#define STM32_FSMC_BASE      0xa0000000     /* 0xa0000000-0xbfffffff: 512Mb FSMC register block */
 
 /* Other registers -- see armv7-m/nvic.h for standard Cortex-M3 registers in this
  * address range
  */
 
-#define STM32_SCS_BASE      0xe000e000
-#define STM32_DEBUGMCU_BASE 0xe0042000
+#define STM32_SCS_BASE       0xe000e000
+#define STM32_DEBUGMCU_BASE  0xe0042000
 
 #endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F10XXX_MEMORYMAP_H */
 
diff --git a/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_rcc.h b/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_rcc.h
index 60365b921..1a792b7eb 100644
--- a/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_rcc.h
+++ b/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_rcc.h
@@ -163,7 +163,9 @@
 #  define RCC_CFGR_PLLMUL_CLKx14    (12 << RCC_CFGR_PLLMUL_SHIFT) /* 1100: PLL input clock x 14 */
 #  define RCC_CFGR_PLLMUL_CLKx15    (13 << RCC_CFGR_PLLMUL_SHIFT) /* 1101: PLL input clock x 15 */
 #  define RCC_CFGR_PLLMUL_CLKx16    (14 << RCC_CFGR_PLLMUL_SHIFT) /* 111x: PLL input clock x 16 */
-#define RCC_CFGR_USBPRE             (1 << 22) /* Bit 22: USB prescaler */
+#ifndef CONFIG_STM32_VALUELINE
+#  define RCC_CFGR_USBPRE           (1 << 22) /* Bit 22: USB prescaler */
+#endif
 #define RCC_CFGR_MCO_SHIFT          (24)      /* Bits 26-24: Microcontroller Clock Output */
 #define RCC_CFGR_MCO_MASK           (0x0f << RCC_CFGR_MCO_SHIFT)
 #  define RCC_CFGR_NOCLK            (0 << RCC_CFGR_MCO_SHIFT)  /* 0xx: No clock */
@@ -207,12 +209,22 @@
 #define TCC_APB2RSTR_IOPFRST        (1 << 7)  /* Bit 7: IO port F reset */
 #define TCC_APB2RSTR_IOPGRST        (1 << 8)  /* Bit 8: IO port G reset */
 #define RCC_APB2RSTR_ADC1RST        (1 << 9)  /* Bit 9: ADC 1 interface reset */
-#define RCC_APB2RSTR_ADC2RST        (1 << 10) /* Bit 10: ADC 2 interface reset */
+#ifndef CONFIG_STM32_VALUELINE
+#  define RCC_APB2RSTR_ADC2RST      (1 << 10) /* Bit 10: ADC 2 interface reset */
+#endif
 #define RCC_APB2RSTR_TIM1RST        (1 << 11) /* Bit 11: TIM1 Timer reset */
 #define RCC_APB2RSTR_SPI1RST        (1 << 12) /* Bit 12: SPI 1 reset */
-#define RCC_APB2RSTR_TIM8RST        (1 << 13) /* Bit 13: TIM8 Timer reset */
+#ifndef CONFIG_STM32_VALUELINE
+#  define RCC_APB2RSTR_TIM8RST      (1 << 13) /* Bit 13: TIM8 Timer reset */
+#endif
 #define RCC_APB2RSTR_USART1RST      (1 << 14) /* Bit 14: USART1 reset */
-#define RCC_APB2RSTR_ADC3RST        (1 << 15) /* Bit 15: ADC3 interface reset */
+#ifndef CONFIG_STM32_VALUELINE
+#  define RCC_APB2RSTR_ADC3RST      (1 << 15) /* Bit 15: ADC3 interface reset */
+#else
+#  define RCC_APB2RSTR_TIM15RST     (1 << 16) /* Bit 16: TIM15 reset */
+#  define RCC_APB2RSTR_TIM16RST     (1 << 17) /* Bit 17: TIM16 reset */
+#  define RCC_APB2RSTR_TIM17RST     (1 << 18) /* Bit 18: TIM17 reset */
+#endif
 
 /* APB1 Peripheral reset register */
 
@@ -222,6 +234,11 @@
 #define RCC_APB1RSTR_TIM5RST        (1 << 3)  /* Bit 3: Timer 5 reset */
 #define RCC_APB1RSTR_TIM6RST        (1 << 4)  /* Bit 4: Timer 6 reset */
 #define RCC_APB1RSTR_TIM7RST        (1 << 5)  /* Bit 5: Timer 7 reset */
+#ifdef CONFIG_STM32_VALUELINE
+#  define RCC_APB1RSTR_TIM12RST     (1 << 6) /* Bit 6: TIM12 reset */
+#  define RCC_APB1RSTR_TIM13RST     (1 << 7) /* Bit 7: TIM13 reset */
+#  define RCC_APB1RSTR_TIM14RST     (1 << 8) /* Bit 8: TIM14 reset */
+#endif
 #define RCC_APB1RSTR_WWDGRST        (1 << 11) /* Bit 11: Window Watchdog reset */
 #define RCC_APB1RSTR_SPI2RST        (1 << 14) /* Bit 14: SPI 2 reset */
 #define RCC_APB1RSTR_SPI3RST        (1 << 15) /* Bit 15: SPI 3 reset */
@@ -231,12 +248,17 @@
 #define RCC_APB1RSTR_UART5RST       (1 << 20) /* Bit 18: UART 5 reset */
 #define RCC_APB1RSTR_I2C1RST        (1 << 21) /* Bit 21: I2C 1 reset */
 #define RCC_APB1RSTR_I2C2RST        (1 << 22) /* Bit 22: I2C 2 reset */
-#define RCC_APB1RSTR_USBRST         (1 << 23) /* Bit 23: USB reset */
-#define RCC_APB1RSTR_CAN1RST        (1 << 25) /* Bit 25: CAN1 reset */
-#define RCC_APB1RSTR_CAN2RST        (1 << 26) /* Bit 26: CAN2 reset */
+#ifndef CONFIG_STM32_VALUELINE
+#  define RCC_APB1RSTR_USBRST       (1 << 23) /* Bit 23: USB reset */
+#  define RCC_APB1RSTR_CAN1RST      (1 << 25) /* Bit 25: CAN1 reset */
+#  define RCC_APB1RSTR_CAN2RST      (1 << 26) /* Bit 26: CAN2 reset */
+#endif
 #define RCC_APB1RSTR_BKPRST         (1 << 27) /* Bit 27: Backup interface reset */
 #define RCC_APB1RSTR_PWRRST         (1 << 28) /* Bit 28: Power interface reset */
 #define RCC_APB1RSTR_DACRST         (1 << 29) /* Bit 29: DAC interface reset */
+#ifdef CONFIG_STM32_VALUELINE
+#  define RCC_APB1RSTR_CECRST       (1 << 30) /* Bit 30: CEC reset */
+#endif
 
 /* AHB Peripheral Clock enable register */
 
@@ -246,7 +268,9 @@
 #define RCC_AHBENR_FLITFEN          (1 << 4)  /* Bit 4: FLITF clock enable */
 #define RCC_AHBENR_CRCEN            (1 << 6)  /* Bit 6: CRC clock enable */
 #define RCC_AHBENR_FSMCEN           (1 << 8)  /* Bit 8: FSMC clock enable */
-#define RCC_AHBENR_SDIOEN           (1 << 10) /* Bit 10: SDIO clock enable */
+#ifndef CONFIG_STM32_VALUELINE
+#  define RCC_AHBENR_SDIOEN         (1 << 10) /* Bit 10: SDIO clock enable */
+#endif
 #ifdef CONFIG_STM32_CONNECTIVITYLINE
 #  define RCC_AHBENR_ETHMACEN       (1 << 14) /* Bit 14: Ethernet MAC clock enable */
 #  define RCC_AHBENR_ETHMACTXEN     (1 << 15) /* Bit 15: Ethernet MAC TX clock enable */
@@ -272,12 +296,22 @@
 #define RCC_APB2ENR_IOPFEN          (1 << 7)  /* Bit 7: I/O port F clock enable */
 #define RCC_APB2ENR_IOPGEN          (1 << 8)  /* Bit 8: I/O port G clock enable */
 #define RCC_APB2ENR_ADC1EN          (1 << 9)  /* Bit 9: ADC 1 interface clock enable */
-#define RCC_APB2ENR_ADC2EN          (1 << 10) /* Bit 10: ADC 2 interface clock enable */
+#ifndef CONFIG_STM32_VALUELINE
+#  define RCC_APB2ENR_ADC2EN        (1 << 10) /* Bit 10: ADC 2 interface clock enable */
+#endif
 #define RCC_APB2ENR_TIM1EN          (1 << 11) /* Bit 11: TIM1 Timer clock enable */
 #define RCC_APB2ENR_SPI1EN          (1 << 12) /* Bit 12: SPI 1 clock enable */
-#define RCC_APB2ENR_TIM8EN          (1 << 13) /* Bit 13: TIM8 Timer clock enable */
+#ifndef CONFIG_STM32_VALUELINE
+#  define RCC_APB2ENR_TIM8EN        (1 << 13) /* Bit 13: TIM8 Timer clock enable */
+#endif
 #define RCC_APB2ENR_USART1EN        (1 << 14) /* Bit 14: USART1 clock enable */
-#define RCC_APB2ENR_ADC3EN          (1 << 15) /* Bit 14: ADC3 interface clock enable */
+#ifndef CONFIG_STM32_VALUELINE
+#  define RCC_APB2ENR_ADC3EN        (1 << 15) /* Bit 14: ADC3 interface clock enable */
+#else
+#  define RCC_APB2ENR_TIM15EN       (1 << 16) /* Bit 16: TIM15 clock enable */
+#  define RCC_APB2ENR_TIM16EN       (1 << 17) /* Bit 17: TIM16 clock enable */
+#  define RCC_APB2ENR_TIM17EN       (1 << 18) /* Bit 18: TIM17 clock enable */
+#endif
 
 /* APB1 Peripheral Clock enable register */
 
@@ -287,6 +321,11 @@
 #define RCC_APB1ENR_TIM5EN          (1 << 3)  /* Bit 3: Timer 5 clock enable */
 #define RCC_APB1ENR_TIM6EN          (1 << 4)  /* Bit 4: Timer 6 clock enable */
 #define RCC_APB1ENR_TIM7EN          (1 << 5)  /* Bit 5: Timer 7 clock enable */
+#ifdef CONFIG_STM32_VALUELINE
+#  define RCC_APB1ENR_TIM12EN       (1 << 6)  /* Bit 6: Timer 12 clock enable */
+#  define RCC_APB1ENR_TIM13EN       (1 << 7)  /* Bit 7: Timer 13 clock enable */
+#  define RCC_APB1ENR_TIM14EN       (1 << 8)  /* Bit 8: Timer 14 clock enable */
+#endif
 #define RCC_APB1ENR_WWDGEN          (1 << 11) /* Bit 11: Window Watchdog clock enable */
 #define RCC_APB1ENR_SPI2EN          (1 << 14) /* Bit 14: SPI 2 clock enable */
 #define RCC_APB1ENR_SPI3EN          (1 << 15) /* Bit 15: SPI 3 clock enable */
@@ -296,12 +335,17 @@
 #define RCC_APB1ENR_UART5EN         (1 << 20) /* Bit 20: UART 5 clock enable */
 #define RCC_APB1ENR_I2C1EN          (1 << 21) /* Bit 21: I2C 1 clock enable */
 #define RCC_APB1ENR_I2C2EN          (1 << 22) /* Bit 22: I2C 2 clock enable */
-#define RCC_APB1ENR_USBEN           (1 << 23) /* Bit 23: USB clock enable */
-#define RCC_APB1ENR_CAN1EN          (1 << 25) /* Bit 25: CAN1 clock enable */
-#define RCC_APB1ENR_CAN2EN          (1 << 26) /* Bit 25: CAN2 clock enable */
+#ifndef CONFIG_STM32_VALUELINE
+#  define RCC_APB1ENR_USBEN         (1 << 23) /* Bit 23: USB clock enable */
+#  define RCC_APB1ENR_CAN1EN        (1 << 25) /* Bit 25: CAN1 clock enable */
+#  define RCC_APB1ENR_CAN2EN        (1 << 26) /* Bit 25: CAN2 clock enable */
+#endif
 #define RCC_APB1ENR_BKPEN           (1 << 27) /* Bit 27: Backup interface clock enable */
 #define RCC_APB1ENR_PWREN           (1 << 28) /* Bit 28: Power interface clock enable */
 #define RCC_APB1ENR_DACEN           (1 << 29) /* Bit 29: DAC interface clock enable */
+#ifdef CONFIG_STM32_VALUELINE
+#  define RCC_APB1ENR_CECEN         (1 << 30) /* Bit 30: CEC clock enable */
+#endif
 
 /* Backup domain control register */
 
@@ -331,7 +375,7 @@
 
 #if defined(CONFIG_STM32_VALUELINE) || defined(CONFIG_STM32_CONNECTIVITYLINE)
 
-/* Clock configuration register 2 (For connectivity line only) */
+/* Clock configuration register 2 (For value line and connectivity line only) */
 
 #define RCC_CFGR2_PREDIV1_SHIFT     (0)
 #define RCC_CFGR2_PREDIV1_MASK      (0x0f << RCC_CFGR2_PREDIV1_SHIFT)
@@ -352,6 +396,10 @@
 #  define RCC_CFGR2_PREDIV1d15      (14 << RCC_CFGR2_PREDIV1_SHIFT)
 #  define RCC_CFGR2_PREDIV1d16      (15 << RCC_CFGR2_PREDIV1_SHIFT)
 
+#endif
+
+#ifdef CONFIG_STM32_CONNECTIVITYLINE
+
 #define RCC_CFGR2_PREDIV2_SHIFT     (4)
 #define RCC_CFGR2_PREDIV2_MASK      (0x0f << RCC_CFGR2_PREDIV2_SHIFT)
 #  define RCC_CFGR2_PREDIV2d1       (0 << RCC_CFGR2_PREDIV2_SHIFT)
diff --git a/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_vectors.h b/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_vectors.h
index b8d71799f..24822c37d 100644
--- a/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_vectors.h
+++ b/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_vectors.h
@@ -49,15 +49,77 @@
  * definition that provides the number of supported vectors.
  */
 
-#ifdef CONFIG_ARMV7M_CMNVECTOR
+#  ifdef CONFIG_ARMV7M_CMNVECTOR
 
-/* Reserve 60 interrupt table entries for I/O interrupts. */
+/* Reserve 61 interrupt table entries for I/O interrupts. */
 
-#  define ARMV7M_PERIPHERAL_INTERRUPTS 60
+#    define ARMV7M_PERIPHERAL_INTERRUPTS 61
 
 #else
-#  error This target requires CONFIG_ARMV7M_CMNVECTOR
-#endif /* CONFIG_ARMV7M_CMNVECTOR */
+
+VECTOR(stm32_wwdg, STM32_IRQ_WWDG)                /* Vector 16+0:  Window Watchdog interrupt */
+VECTOR(stm32_pvd, STM32_IRQ_PVD)                  /* Vector 16+1:  PVD through EXTI Line detection interrupt */
+VECTOR(stm32_tamper, STM32_IRQ_TAMPER)            /* Vector 16+2:  Tamper interrupt */
+VECTOR(stm32_rtc, STM32_IRQ_RTC)                  /* Vector 16+3:  RTC Wakeup through EXTI line interrupt */
+VECTOR(stm32_flash, STM32_IRQ_FLASH)              /* Vector 16+4:  Flash global interrupt */
+VECTOR(stm32_rcc, STM32_IRQ_RCC)                  /* Vector 16+5:  RCC global interrupt */
+VECTOR(stm32_exti0, STM32_IRQ_EXTI0)              /* Vector 16+6:  EXTI Line 0 interrupt */
+VECTOR(stm32_exti1, STM32_IRQ_EXTI1)              /* Vector 16+7:  EXTI Line 1 interrupt */
+VECTOR(stm32_exti2, STM32_IRQ_EXTI2)              /* Vector 16+8:  EXTI Line 2 interrupt */
+VECTOR(stm32_exti3, STM32_IRQ_EXTI3)              /* Vector 16+9:  EXTI Line 3 interrupt */
+VECTOR(stm32_exti4, STM32_IRQ_EXTI4)              /* Vector 16+10: EXTI Line 4 interrupt */
+VECTOR(stm32_dma1ch1, STM32_IRQ_DMA1CH1)          /* Vector 16+11: DMA1 Channel 1 global interrupt */
+VECTOR(stm32_dma1ch2, STM32_IRQ_DMA1CH2)          /* Vector 16+12: DMA1 Channel 2 global interrupt */
+VECTOR(stm32_dma1ch3, STM32_IRQ_DMA1CH3)          /* Vector 16+13: DMA1 Channel 3 global interrupt */
+VECTOR(stm32_dma1ch4, STM32_IRQ_DMA1CH4)          /* Vector 16+14: DMA1 Channel 4 global interrupt */
+VECTOR(stm32_dma1ch5, STM32_IRQ_DMA1CH5)          /* Vector 16+15: DMA1 Channel 5 global interrupt */
+VECTOR(stm32_dma1ch6, STM32_IRQ_DMA1CH6)          /* Vector 16+16: DMA1 Channel 6 global interrupt */
+VECTOR(stm32_dma1ch7, STM32_IRQ_DMA1CH7)          /* Vector 16+17: DMA1 Channel 7 global interrupt */
+VECTOR(stm32_adc1, STM32_IRQ_ADC1)                /* Vector 16+18: ADC1 global interrupt */
+UNUSED(STM32_IRQ_RESERVED0)                       /* Vector 16+19: Reserved 0 */
+UNUSED(STM32_IRQ_RESERVED1)                       /* Vector 16+20: Reserved 1 */
+UNUSED(STM32_IRQ_RESERVED2)                       /* Vector 16+21: Reserved 2 */
+UNUSED(STM32_IRQ_RESERVED3)                       /* Vector 16+22: Reserved 3 */
+VECTOR(stm32_exti95, STM32_IRQ_EXTI95)            /* Vector 16+23: EXTI Line[9:5] interrupts */
+VECTOR(stm32_tim1brk, STM32_IRQ_TIM1BRK)          /* Vector 16+24: TIM1 Break interrupt; TIM15 global interrupt */
+VECTOR(stm32_tim1up, STM32_IRQ_TIM1UP)            /* Vector 16+25: TIM1 Update interrupt; TIM16 global interrupt */
+VECTOR(stm32_tim1trgcom, STM32_IRQ_TIM1TRGCOM)    /* Vector 16+26: TIM1 Trigger and Commutation interrupts; TIM17 global interrupt */
+VECTOR(stm32_tim1cc, STM32_IRQ_TIM1CC)            /* Vector 16+27: TIM1 Capture Compare interrupt */
+VECTOR(stm32_tim2, STM32_IRQ_TIM2)                /* Vector 16+28: TIM2 global interrupt */
+VECTOR(stm32_tim3, STM32_IRQ_TIM3)                /* Vector 16+29: TIM3 global interrupt */
+VECTOR(stm32_tim4, STM32_IRQ_TIM4)                /* Vector 16+30: TIM4 global interrupt */
+VECTOR(stm32_i2c1ev, STM32_IRQ_I2C1EV)            /* Vector 16+31: I2C1 event interrupt */
+VECTOR(stm32_i2c1er, STM32_IRQ_I2C1ER)            /* Vector 16+32: I2C1 error interrupt */
+VECTOR(stm32_i2c2ev, STM32_IRQ_I2C2EV)            /* Vector 16+33: I2C2 event interrupt */
+VECTOR(stm32_i2c2er, STM32_IRQ_I2C2ER)            /* Vector 16+34: I2C2 error interrupt */
+VECTOR(stm32_spi1, STM32_IRQ_SPI1)                /* Vector 16+35: SPI1 global interrupt */
+VECTOR(stm32_spi2, STM32_IRQ_SPI2)                /* Vector 16+36: SPI2 global interrupt */
+VECTOR(stm32_usart1, STM32_IRQ_USART1)            /* Vector 16+37: USART1 global interrupt */
+VECTOR(stm32_usart2, STM32_IRQ_USART2)            /* Vector 16+38: USART2 global interrupt */
+VECTOR(stm32_usart3, STM32_IRQ_USART3)            /* Vector 16+39: USART3 global interrupt */
+VECTOR(stm32_exti1510, STM32_IRQ_EXTI1510)        /* Vector 16+40: EXTI Line[15:10] interrupts */
+VECTOR(stm32_rtcalr, STM32_IRQ_RTCALR)            /* Vector 16+41: RTC alarms (A and B) through EXTI line interrupt */
+VECTOR(stm32_cec, STM32_IRQ_CEC)                  /* Vector 16+42: CEC global interrupt */
+VECTOR(stm32_tim12, STM32_IRQ_TIM12)              /* Vector 16+43: TIM12 global interrupt */
+VECTOR(stm32_tim13, STM32_IRQ_TIM13)              /* Vector 16+44: TIM13 global interrupt */
+VECTOR(stm32_tim14, STM32_IRQ_TIM14)              /* Vector 16+45: TIM14 global interrupt */
+UNUSED(STM32_IRQ_RESERVED4)                       /* Vector 16+46: Reserved 4 */
+UNUSED(STM32_IRQ_RESERVED5)                       /* Vector 16+47: Reserved 5 */
+VECTOR(stm32_fsmc, STM32_IRQ_FSMC)                /* Vector 16+48: FSMC global interrupt */
+UNUSED(STM32_IRQ_RESERVED6)                       /* Vector 16+49: Reserved 6 */
+VECTOR(stm32_tim5, STM32_IRQ_TIM5)                /* Vector 16+50: TIM5 global interrupt */
+VECTOR(stm32_spi3, STM32_IRQ_SPI3)                /* Vector 16+51: SPI3 global interrupt */
+VECTOR(stm32_uart4, STM32_IRQ_UART4)              /* Vector 16+52: USART2 global interrupt */
+VECTOR(stm32_uart5, STM32_IRQ_UART5)              /* Vector 16+53: USART5 global interrupt */
+VECTOR(stm32_tim6, STM32_IRQ_TIM6)                /* Vector 16+54: TIM6 global interrupt */
+VECTOR(stm32_tim7, STM32_IRQ_TIM7)                /* Vector 16+55: TIM7 global interrupt */
+VECTOR(stm32_dma2ch1, STM32_IRQ_DMA2CH1)          /* Vector 16+56: DMA2 Channel 1 global interrupt */
+VECTOR(stm32_dma2ch2, STM32_IRQ_DMA2CH2)          /* Vector 16+57: DMA2 Channel 2 global interrupt */
+VECTOR(stm32_dma2ch3, STM32_IRQ_DMA2CH3)          /* Vector 16+58: DMA2 Channel 3 global interrupt */
+VECTOR(stm32_dma2ch45, STM32_IRQ_DMA2CH45)        /* Vector 16+59: DMA2 Channel 4 and 5 global interrupt */
+VECTOR(stm32_dma2ch5, STM32_IRQ_DMA2CH5)          /* Vector 16+60: DMA2 Channel 5 global interrupt */
+
+#  endif /* CONFIG_ARMV7M_CMNVECTOR */
 
 #elif defined(CONFIG_STM32_CONNECTIVITYLINE)
 
diff --git a/nuttx/arch/arm/src/stm32/chip/stm32f20xxx_pinmap.h b/nuttx/arch/arm/src/stm32/chip/stm32f20xxx_pinmap.h
index 817e747f7..699ca4fdc 100644
--- a/nuttx/arch/arm/src/stm32/chip/stm32f20xxx_pinmap.h
+++ b/nuttx/arch/arm/src/stm32/chip/stm32f20xxx_pinmap.h
@@ -222,7 +222,7 @@
 #define GPIO_ETH_MII_TX_EN_2  (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN11)
 #define GPIO_ETH_PPS_OUT_1    (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN5)
 #define GPIO_ETH_PPS_OUT_2    (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN8)
-#define GPIO_ETH_RMII_CRS_DV  (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULLGPIO_PORTA|GPIO_PIN7)
+#define GPIO_ETH_RMII_CRS_DV  (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN7)
 #define GPIO_ETH_RMII_REF_CLK (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN1)
 #define GPIO_ETH_RMII_RXD0    (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN4)
 #define GPIO_ETH_RMII_RXD1    (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN5)
diff --git a/nuttx/arch/arm/src/stm32/chip/stm32f40xxx_pinmap.h b/nuttx/arch/arm/src/stm32/chip/stm32f40xxx_pinmap.h
index ae2436a70..31e51caf0 100644
--- a/nuttx/arch/arm/src/stm32/chip/stm32f40xxx_pinmap.h
+++ b/nuttx/arch/arm/src/stm32/chip/stm32f40xxx_pinmap.h
@@ -222,7 +222,7 @@
 #define GPIO_ETH_MII_TX_EN_2  (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN11)
 #define GPIO_ETH_PPS_OUT_1    (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN5)
 #define GPIO_ETH_PPS_OUT_2    (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN8)
-#define GPIO_ETH_RMII_CRS_DV  (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULLGPIO_PORTA|GPIO_PIN7)
+#define GPIO_ETH_RMII_CRS_DV  (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN7)
 #define GPIO_ETH_RMII_REF_CLK (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN1)
 #define GPIO_ETH_RMII_RXD0    (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN4)
 #define GPIO_ETH_RMII_RXD1    (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN5)
diff --git a/nuttx/arch/arm/src/stm32/stm32_adc.h b/nuttx/arch/arm/src/stm32/stm32_adc.h
index c25da3830..7b6c13b33 100644
--- a/nuttx/arch/arm/src/stm32/stm32_adc.h
+++ b/nuttx/arch/arm/src/stm32/stm32_adc.h
@@ -281,7 +281,7 @@
 
 #if defined(ADC1_HAVE_TIMER) || defined(ADC2_HAVE_TIMER) || defined(ADC3_HAVE_TIMER)
 #  define ADC_HAVE_TIMER 1
-#  if defined(CONFIG_STM32_STM32F10XX) && defined(CONFIG_STM32_FORCEPOWER)
+#  if defined(CONFIG_STM32_STM32F10XX) && !defined(CONFIG_STM32_FORCEPOWER)
 #    warning "CONFIG_STM32_FORCEPOWER must be defined to enable the timer(s)"
 #  endif
 #else
diff --git a/nuttx/arch/arm/src/stm32/stm32_eth.c b/nuttx/arch/arm/src/stm32/stm32_eth.c
index 3054142ce..006f67142 100644
--- a/nuttx/arch/arm/src/stm32/stm32_eth.c
+++ b/nuttx/arch/arm/src/stm32/stm32_eth.c
@@ -2594,6 +2594,17 @@ static int stm32_phyinit(FAR struct stm32_ethmac_s *priv)
     }
   up_mdelay(PHY_RESET_DELAY);
 
+  /* Perform any necessary, board-specific PHY initialization */
+
+#ifdef CONFIG_STM32_PHYINIT
+  ret = stm32_phy_boardinitialize(0);
+  if (ret < 0)
+    {
+      ndbg("Failed to initialize the PHY: %d\n", ret);
+      return ret;
+    }
+#endif
+
   /* Special workaround for the Davicom DM9161 PHY is required. */
 
 #ifdef CONFIG_PHY_DM9161
diff --git a/nuttx/arch/arm/src/stm32/stm32_eth.h b/nuttx/arch/arm/src/stm32/stm32_eth.h
index f0c14b5b1..4501712b1 100644
--- a/nuttx/arch/arm/src/stm32/stm32_eth.h
+++ b/nuttx/arch/arm/src/stm32/stm32_eth.h
@@ -66,14 +66,13 @@ extern "C" {
  * Function: stm32_ethinitialize
  *
  * Description:
- *   Initialize the Ethernet driver for one interface.  If the STM32 chip
- *   supports multiple Ethernet controllers, then board specific logic
- *   must implement up_netinitialize() and call this function to initialize
- *   the desired interfaces.
+ *   Initialize the Ethernet driver for one interface.  If the STM32 chip supports
+ *   multiple Ethernet controllers, then board specific logic must implement
+ *   up_netinitialize() and call this function to initialize the desired interfaces.
  *
  * Parameters:
- *   intf - In the case where there are multiple EMACs, this value
- *          identifies which EMAC is to be initialized.
+ *   intf - In the case where there are multiple EMACs, this value identifies which
+ *   EMAC is to be initialized.
  *
  * Returned Value:
  *   OK on success; Negated errno on failure.
@@ -86,6 +85,30 @@ extern "C" {
 EXTERN int stm32_ethinitialize(int intf);
 #endif
 
+/************************************************************************************
+ * Function: stm32_phy_boardinitialize
+ *
+ * Description:
+ *   Some boards require specialized initialization of the PHY before it can be used.
+ *   This may include such things as configuring GPIOs, resetting the PHY, etc.  If
+ *   CONFIG_STM32_PHYINIT is defined in the configuration then the board specific
+ *   logic must provide stm32_phyinitialize();  The STM32 Ethernet driver will call
+ *   this function one time before it first uses the PHY.
+ *
+ * Parameters:
+ *   intf - Always zero for now.
+ *
+ * Returned Value:
+ *   OK on success; Negated errno on failure.
+ *
+ * Assumptions:
+ *
+ ************************************************************************************/
+
+#ifdef CONFIG_STM32_PHYINIT
+EXTERN int stm32_phy_boardinitialize(int intf);
+#endif
+
 #undef EXTERN
 #if defined(__cplusplus)
 }
diff --git a/nuttx/arch/arm/src/stm32/stm32_i2c.c b/nuttx/arch/arm/src/stm32/stm32_i2c.c
index a4b10b55c..fd682cd5d 100644
--- a/nuttx/arch/arm/src/stm32/stm32_i2c.c
+++ b/nuttx/arch/arm/src/stm32/stm32_i2c.c
@@ -107,17 +107,23 @@
 
 #if !defined(CONFIG_STM32_I2CTIMEOSEC) && !defined(CONFIG_STM32_I2CTIMEOMS)
 #  define CONFIG_STM32_I2CTIMEOSEC 0
-#  define CONFIG_STM32_I2CTIMEOMS   500   /* Default is 500 milliseconds */
+#  define CONFIG_STM32_I2CTIMEOMS  500   /* Default is 500 milliseconds */
 #elif !defined(CONFIG_STM32_I2CTIMEOSEC)
 #  define CONFIG_STM32_I2CTIMEOSEC 0     /* User provided milliseconds */
 #elif !defined(CONFIG_STM32_I2CTIMEOMS)
-#  define CONFIG_STM32_I2CTIMEOMS   0     /* User provided seconds */
+#  define CONFIG_STM32_I2CTIMEOMS  0     /* User provided seconds */
 #endif
 
 /* Interrupt wait time timeout in system timer ticks */
 
-#define CONFIG_STM32_I2CTIMEOTICKS \
-  (SEC2TICK(CONFIG_STM32_I2CTIMEOSEC) + MSEC2TICK(CONFIG_STM32_I2CTIMEOMS))
+#ifndef CONFIG_STM32_I2CTIMEOTICKS
+#  define CONFIG_STM32_I2CTIMEOTICKS \
+    (SEC2TICK(CONFIG_STM32_I2CTIMEOSEC) + MSEC2TICK(CONFIG_STM32_I2CTIMEOMS))
+#endif
+
+#ifndef CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP
+#  define CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP TICK2USEC(CONFIG_STM32_I2CTIMEOTICKS)
+#endif
 
 /* On the STM32F103ZE, there is an internal conflict between I2C1 and FSMC.  In that
  * case, it is necessary to disable FSMC before each I2C1 access and re-enable FSMC
@@ -129,6 +135,18 @@
 #  define I2C1_FSMC_CONFLICT
 #endif
 
+/* Macros to convert a I2C pin to a GPIO output */
+
+#if defined(CONFIG_STM32_STM32F10XX)
+#  define I2C_OUTPUT (GPIO_OUTPUT | GPIO_OUTPUT_SET | GPIO_CNF_OUTOD | \
+                      GPIO_MODE_50MHz)
+#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
+#  define I2C_OUTPUT (GPIO_OUTPUT | GPIO_FLOAT | GPIO_OPENDRAIN |\
+                      GPIO_SPEED_50MHz | GPIO_OUTPUT_SET)
+#endif
+
+#define MKI2C_OUTPUT(p) (((p) & (GPIO_PORT_MASK | GPIO_PIN_MASK)) | I2C_OUTPUT)
+
 /* Debug ****************************************************************************/
 /* CONFIG_DEBUG_I2C + CONFIG_DEBUG enables general I2C debug output. */
 
@@ -200,18 +218,16 @@ struct stm32_trace_s
 
 struct stm32_i2c_config_s
 {
-  uint32_t    base;        /* I2C base address */
+  uint32_t base;              /* I2C base address */
+  uint32_t clk_bit;           /* Clock enable bit */
+  uint32_t reset_bit;         /* Reset bit */
+  uint32_t scl_pin;           /* GPIO configuration for SCL as SCL */
+  uint32_t sda_pin;           /* GPIO configuration for SDA as SDA */
 #ifndef CONFIG_I2C_POLLED
-  int         ( *isr)(int, void *); /* Interrupt handler */
+  int (*isr)(int, void *);    /* Interrupt handler */
+  uint32_t ev_irq;            /* Event IRQ */
+  uint32_t er_irq;            /* Error IRQ */
 #endif
-  uint32_t    clk_bit;     /* Clock enable bit */
-  uint32_t    reset_bit;   /* Reset bit */
-  uint32_t    scl_pin;     /* GPIO configuration for SCL as SCL */
-  uint32_t    scl_gpio;    /* GPIO configuration for SCL as a GPIO */
-  uint32_t    sda_pin;     /* GPIO configuration for SDA as SDA */
-  uint32_t    sda_gpio;    /* GPIO configuration for SDA as a GPIO */
-  uint32_t    ev_irq;      /* Event IRQ */
-  uint32_t    er_irq;      /* Error IRQ */
 };
 
 /* I2C Device Private Data */
@@ -219,31 +235,31 @@ struct stm32_i2c_config_s
 struct stm32_i2c_priv_s
 {
   const struct stm32_i2c_config_s *config; /* Port configuration */
-  int         refs;        /* Referernce count */
-  sem_t       sem_excl;    /* Mutual exclusion semaphore */
+  int refs;                    /* Referernce count */
+  sem_t sem_excl;              /* Mutual exclusion semaphore */
 #ifndef CONFIG_I2C_POLLED
-  sem_t       sem_isr;     /* Interrupt wait semaphore */
+  sem_t sem_isr;               /* Interrupt wait semaphore */
 #endif
-  volatile uint8_t intstate;  /* Interrupt handshake (see enum stm32_intstate_e) */
+  volatile uint8_t intstate;   /* Interrupt handshake (see enum stm32_intstate_e) */
     
-  uint8_t     msgc;        /* Message count */
-  struct i2c_msg_s *msgv;  /* Message list */
-  uint8_t    *ptr;         /* Current message buffer */
-  int         dcnt;        /* Current message length */
-  uint16_t    flags;       /* Current message flags */
+  uint8_t msgc;                /* Message count */
+  struct i2c_msg_s *msgv;      /* Message list */
+  uint8_t *ptr;                /* Current message buffer */
+  int dcnt;                    /* Current message length */
+  uint16_t flags;              /* Current message flags */
 
   /* I2C trace support */
 
 #ifdef CONFIG_I2C_TRACE
-  int         tndx;        /* Trace array index */
-  uint32_t    start_time;  /* Time when the trace was started */
+  int tndx;                    /* Trace array index */
+  uint32_t start_time;         /* Time when the trace was started */
 
   /* The actual trace data */
 
   struct stm32_trace_s trace[CONFIG_I2C_NTRACE];
 #endif
 
-  uint32_t    status;      /* End of transfer SR2|SR1 status */
+  uint32_t status;             /* End of transfer SR2|SR1 status */
 };
 
 /* I2C Device, Instance */
@@ -270,8 +286,11 @@ static inline void stm32_i2c_modifyreg(FAR struct stm32_i2c_priv_s *priv,
                                        uint8_t offset, uint16_t clearbits,
                                        uint16_t setbits);
 static inline void stm32_i2c_sem_wait(FAR struct i2c_dev_s *dev);
-static inline int  stm32_i2c_sem_waitdone(FAR struct stm32_i2c_priv_s *priv, int timeout_us);
-static inline void stm32_i2c_sem_waitstop(FAR struct stm32_i2c_priv_s *priv, int timeout_us);
+#ifdef CONFIG_STM32_I2C_DYNTIMEO
+static useconds_t stm32_i2c_tousecs(int msgc, FAR struct i2c_msg_s *msgs);
+#endif /* CONFIG_STM32_I2C_DYNTIMEO */
+static inline int  stm32_i2c_sem_waitdone(FAR struct stm32_i2c_priv_s *priv);
+static inline void stm32_i2c_sem_waitstop(FAR struct stm32_i2c_priv_s *priv);
 static inline void stm32_i2c_sem_post(FAR struct i2c_dev_s *dev);
 static inline void stm32_i2c_sem_init(FAR struct i2c_dev_s *dev);
 static inline void stm32_i2c_sem_destroy(FAR struct i2c_dev_s *dev);
@@ -281,7 +300,7 @@ static void stm32_i2c_tracenew(FAR struct stm32_i2c_priv_s *priv, uint32_t statu
 static void stm32_i2c_traceevent(FAR struct stm32_i2c_priv_s *priv,
                                enum stm32_trace_e event, uint32_t parm);
 static void stm32_i2c_tracedump(FAR struct stm32_i2c_priv_s *priv);
-#endif
+#endif /* CONFIG_I2C_TRACE */
 static void stm32_i2c_setclock(FAR struct stm32_i2c_priv_s *priv,
                                uint32_t frequency);
 static inline void stm32_i2c_sendstart(FAR struct stm32_i2c_priv_s *priv);
@@ -291,7 +310,7 @@ static inline uint32_t stm32_i2c_getstatus(FAR struct stm32_i2c_priv_s *priv);
 #ifdef I2C1_FSMC_CONFLICT
 static inline uint32_t stm32_i2c_disablefsmc(FAR struct stm32_i2c_priv_s *priv);
 static inline void stm32_i2c_enablefsmc(uint32_t ahbenr);
-#endif
+#endif /* I2C1_FSMC_CONFLICT */
 static int stm32_i2c_isr(struct stm32_i2c_priv_s * priv);
 #ifndef CONFIG_I2C_POLLED
 #ifdef CONFIG_STM32_I2C1
@@ -329,27 +348,18 @@ static int stm32_i2c_transfer(FAR struct i2c_dev_s *dev, FAR struct i2c_msg_s *m
  ************************************************************************************/
 
 #ifdef CONFIG_STM32_I2C1
-# ifndef GPIO_I2C1_SCL_GPIO
-#  define  GPIO_I2C1_SCL_GPIO 0
-# endif
-# ifndef GPIO_I2C1_SDA_GPIO
-#  define  GPIO_I2C1_SDA_GPIO 0
-# endif
-
 static const struct stm32_i2c_config_s stm32_i2c1_config = 
 {
   .base       = STM32_I2C1_BASE,
-#ifndef CONFIG_I2C_POLLED
-  .isr        = stm32_i2c1_isr,
-#endif
   .clk_bit    = RCC_APB1ENR_I2C1EN,
   .reset_bit  = RCC_APB1RSTR_I2C1RST,
   .scl_pin    = GPIO_I2C1_SCL,
-  .scl_gpio   = GPIO_I2C1_SCL_GPIO,
   .sda_pin    = GPIO_I2C1_SDA,
-  .sda_gpio   = GPIO_I2C1_SDA_GPIO,
+#ifndef CONFIG_I2C_POLLED
+  .isr        = stm32_i2c1_isr,
   .ev_irq     = STM32_IRQ_I2C1EV,
   .er_irq     = STM32_IRQ_I2C1ER
+#endif
 };
 
 struct stm32_i2c_priv_s stm32_i2c1_priv =
@@ -367,27 +377,18 @@ struct stm32_i2c_priv_s stm32_i2c1_priv =
 #endif
 
 #ifdef CONFIG_STM32_I2C2
-# ifndef GPIO_I2C2_SCL_GPIO
-#  define  GPIO_I2C2_SCL_GPIO 0
-# endif
-# ifndef GPIO_I2C2_SDA_GPIO
-#  define  GPIO_I2C2_SDA_GPIO 0
-# endif
-
 static const struct stm32_i2c_config_s stm32_i2c2_config = 
 {
   .base       = STM32_I2C2_BASE,
-#ifndef CONFIG_I2C_POLLED  
-  .isr        = stm32_i2c2_isr,
-#endif
   .clk_bit    = RCC_APB1ENR_I2C2EN,
   .reset_bit  = RCC_APB1RSTR_I2C2RST,
   .scl_pin    = GPIO_I2C2_SCL,
-  .scl_gpio   = GPIO_I2C2_SCL_GPIO,
   .sda_pin    = GPIO_I2C2_SDA,
-  .sda_gpio   = GPIO_I2C2_SDA_GPIO,
+#ifndef CONFIG_I2C_POLLED  
+  .isr        = stm32_i2c2_isr,
   .ev_irq     = STM32_IRQ_I2C2EV,
   .er_irq     = STM32_IRQ_I2C2ER
+#endif
 };
 
 struct stm32_i2c_priv_s stm32_i2c2_priv =
@@ -405,27 +406,18 @@ struct stm32_i2c_priv_s stm32_i2c2_priv =
 #endif
 
 #ifdef CONFIG_STM32_I2C3
-# ifndef GPIO_I2C3_SCL_GPIO
-#  define  GPIO_I2C3_SCL_GPIO 0
-# endif
-# ifndef GPIO_I2C3_SDA_GPIO
-#  define  GPIO_I2C3_SDA_GPIO 0
-# endif
-
 static const struct stm32_i2c_config_s stm32_i2c3_config = 
 {
   .base       = STM32_I2C3_BASE,
-#ifndef CONFIG_I2C_POLLED
-  .isr        = stm32_i2c3_isr,
-#endif
   .clk_bit    = RCC_APB1ENR_I2C3EN,
   .reset_bit  = RCC_APB1RSTR_I2C3RST,
   .scl_pin    = GPIO_I2C3_SCL,
-  .scl_gpio   = GPIO_I2C3_SCL_GPIO,
   .sda_pin    = GPIO_I2C3_SDA,
-  .sda_gpio   = GPIO_I2C3_SDA_GPIO,
+#ifndef CONFIG_I2C_POLLED
+  .isr        = stm32_i2c3_isr,
   .ev_irq     = STM32_IRQ_I2C3EV,
   .er_irq     = STM32_IRQ_I2C3ER
+#endif
 };
 
 struct stm32_i2c_priv_s stm32_i2c3_priv =
@@ -526,6 +518,35 @@ static inline void stm32_i2c_sem_wait(FAR struct i2c_dev_s *dev)
 }
 
 /************************************************************************************
+ * Name: stm32_i2c_tousecs
+ *
+ * Description:
+ *   Return a micro-second delay based on the number of bytes left to be processed.
+ *
+ ************************************************************************************/
+
+#ifdef CONFIG_STM32_I2C_DYNTIMEO
+static useconds_t stm32_i2c_tousecs(int msgc, FAR struct i2c_msg_s *msgs)
+{
+  size_t bytecount = 0;
+  int i;
+
+  /* Count the number of bytes left to process */
+
+  for (i = 0; i < msgc; i++)
+    {
+      bytecount += msgs[i].length;
+    }
+
+  /* Then return a number of microseconds based on a user provided scaling
+   * factor.
+   */
+
+  return (useconds_t)(CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE * bytecount);
+}
+#endif
+
+/************************************************************************************
  * Name: stm32_i2c_sem_waitdone
  *
  * Description:
@@ -534,7 +555,7 @@ static inline void stm32_i2c_sem_wait(FAR struct i2c_dev_s *dev)
  ************************************************************************************/
 
 #ifndef CONFIG_I2C_POLLED
-static inline int stm32_i2c_sem_waitdone(FAR struct stm32_i2c_priv_s *priv, int timeout_us)
+static inline int stm32_i2c_sem_waitdone(FAR struct stm32_i2c_priv_s *priv)
 {
   struct timespec abstime;
   irqstate_t flags;
@@ -566,31 +587,24 @@ static inline int stm32_i2c_sem_waitdone(FAR struct stm32_i2c_priv_s *priv, int
 #if CONFIG_STM32_I2CTIMEOSEC > 0
       abstime.tv_sec += CONFIG_STM32_I2CTIMEOSEC;
 #endif
-#if CONFIG_STM32_I2CTIMEOUS_PER_BYTE > 0
 
-      /* Count the number of bytes left to process */
-      int i;
-      int bytecount = 0;
-      for (i = 0; i < priv->msgc; i++)
+      /* Add a value proportional to the number of bytes in the transfer */
+
+#ifdef CONFIG_STM32_I2C_DYNTIMEO
+      abstime.tv_nsec += 1000 * stm32_i2c_tousecs(priv->msgc, priv->msgv);
+      if (abstime.tv_nsec > 1000 * 1000 * 1000)
         {
-          bytecount += priv->msgv[i].length;
+          abstime.tv_sec++;
+          abstime.tv_nsec -= 1000 * 1000 * 1000;
         }
 
-      abstime.tv_nsec += (CONFIG_STM32_I2CTIMEOUS_PER_BYTE * bytecount) * 1000;
+#elif CONFIG_STM32_I2CTIMEOMS > 0
+      abstime.tv_nsec += CONFIG_STM32_I2CTIMEOMS * 1000 * 1000;
       if (abstime.tv_nsec > 1000 * 1000 * 1000)
         {
           abstime.tv_sec++;
           abstime.tv_nsec -= 1000 * 1000 * 1000;
         }
-#else
-  #if CONFIG_STM32_I2CTIMEOMS > 0
-        abstime.tv_nsec += CONFIG_STM32_I2CTIMEOMS * 1000 * 1000;
-        if (abstime.tv_nsec > 1000 * 1000 * 1000)
-          {
-            abstime.tv_sec++;
-            abstime.tv_nsec -= 1000 * 1000 * 1000;
-          }
-  #endif
 #endif
       /* Wait until either the transfer is complete or the timeout expires */
 
@@ -624,12 +638,21 @@ static inline int stm32_i2c_sem_waitdone(FAR struct stm32_i2c_priv_s *priv, int
   return ret;
 }
 #else
-static inline int stm32_i2c_sem_waitdone(FAR struct stm32_i2c_priv_s *priv, int timeout_us)
+static inline int stm32_i2c_sem_waitdone(FAR struct stm32_i2c_priv_s *priv)
 {
+  uint32_t timeout;
   uint32_t start;
   uint32_t elapsed;
   int ret;
 
+  /* Get the timeout value */
+
+#ifdef CONFIG_STM32_I2C_DYNTIMEO
+  timeout = USEC2TICK(stm32_i2c_tousecs(priv->msgc, priv->msgv));
+#else
+  timeout = CONFIG_STM32_I2CTIMEOTICKS;
+#endif
+
   /* Signal the interrupt handler that we are waiting.  NOTE:  Interrupts
    * are currently disabled but will be temporarily re-enabled below when
    * sem_timedwait() sleeps.
@@ -652,10 +675,11 @@ static inline int stm32_i2c_sem_waitdone(FAR struct stm32_i2c_priv_s *priv, int
     }
 
   /* Loop until the transfer is complete. */
-  while (priv->intstate != INTSTATE_DONE && elapsed < USEC2TICK(timeout_us));
+
+  while (priv->intstate != INTSTATE_DONE && elapsed < timeout);
 
   i2cvdbg("intstate: %d elapsed: %d threshold: %d status: %08x\n",
-          priv->intstate, elapsed, USEC2TICK(timeout_us), priv->status);
+          priv->intstate, elapsed, timeout, priv->status);
 
   /* Set the interrupt state back to IDLE */
 
@@ -673,13 +697,22 @@ static inline int stm32_i2c_sem_waitdone(FAR struct stm32_i2c_priv_s *priv, int
  *
  ************************************************************************************/
 
-static inline void stm32_i2c_sem_waitstop(FAR struct stm32_i2c_priv_s *priv, int timeout_us)
+static inline void stm32_i2c_sem_waitstop(FAR struct stm32_i2c_priv_s *priv)
 {
   uint32_t start;
   uint32_t elapsed;
+  uint32_t timeout;
   uint32_t cr1;
   uint32_t sr1;
 
+  /* Select a timeout */
+
+#ifdef CONFIG_STM32_I2C_DYNTIMEO
+  timeout = USEC2TICK(CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP);
+#else
+  timeout = CONFIG_STM32_I2CTIMEOTICKS;
+#endif
+
   /* Wait as stop might still be in progress; but stop might also
    * be set because of a timeout error: "The [STOP] bit is set and
    * cleared by software, cleared by hardware when a Stop condition is
@@ -712,7 +745,7 @@ static inline void stm32_i2c_sem_waitstop(FAR struct stm32_i2c_priv_s *priv, int
 
   /* Loop until the stop is complete or a timeout occurs. */
 
-  while (elapsed < USEC2TICK(timeout_us));
+  while (elapsed < timeout);
 
   /* If we get here then a timeout occurred with the STOP condition
    * still pending.
@@ -932,7 +965,7 @@ static void stm32_i2c_setclock(FAR struct stm32_i2c_priv_s *priv, uint32_t frequ
     {
       /* Fast mode speed calculation with Tlow/Thigh = 16/9 */
 
-#ifdef CONFIG_I2C_DUTY16_9
+#ifdef CONFIG_STM32_I2C_DUTY16_9
       speed = (uint16_t)(STM32_PCLK1_FREQUENCY / (frequency * 25));
 
       /* Set DUTY and fast speed bits */
@@ -1071,7 +1104,7 @@ static inline uint32_t stm32_i2c_disablefsmc(FAR struct stm32_i2c_priv_s *priv)
 
   /* Is this I2C1 */
 
-#ifdef CONFIG_STM32_I2C2
+#if defined(CONFIG_STM32_I2C2) || defined(CONFIG_STM32_I2C3)
   if (priv->config->base == STM32_I2C1_BASE)
 #endif
     {
@@ -1198,10 +1231,14 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
         {
           stm32_i2c_traceevent(priv, I2CEVENT_RCVBYTE, priv->dcnt);
 
+          /* No interrupts or context switches may occur in the following
+           * sequence.  Otherwise, additional bytes may be sent by the
+           * device.
+           */
+
 #ifdef CONFIG_I2C_POLLED
           irqstate_t state = irqsave();
 #endif
-
           /* Receive a byte */
 
           *priv->ptr++ = stm32_i2c_getreg(priv, STM32_I2C_DR_OFFSET);
@@ -1217,7 +1254,6 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
 #ifdef CONFIG_I2C_POLLED
           irqrestore(state);
 #endif
-
         }
     }
     
@@ -1408,7 +1444,6 @@ static int stm32_i2c_init(FAR struct stm32_i2c_priv_s *priv)
   /* Enable power and reset the peripheral */
 
   modifyreg32(STM32_RCC_APB1ENR, 0, priv->config->clk_bit);
-
   modifyreg32(STM32_RCC_APB1RSTR, 0, priv->config->reset_bit);
   modifyreg32(STM32_RCC_APB1RSTR, priv->config->reset_bit, 0);
 
@@ -1428,10 +1463,10 @@ static int stm32_i2c_init(FAR struct stm32_i2c_priv_s *priv)
   /* Attach ISRs */
             
 #ifndef CONFIG_I2C_POLLED
-        irq_attach(priv->config->ev_irq, priv->config->isr);
-        irq_attach(priv->config->er_irq, priv->config->isr);
-        up_enable_irq(priv->config->ev_irq);
-        up_enable_irq(priv->config->er_irq);
+  irq_attach(priv->config->ev_irq, priv->config->isr);
+  irq_attach(priv->config->er_irq, priv->config->isr);
+  up_enable_irq(priv->config->ev_irq);
+  up_enable_irq(priv->config->er_irq);
 #endif
 
   /* Set peripheral frequency, where it must be at least 2 MHz  for 100 kHz
@@ -1461,17 +1496,23 @@ static int stm32_i2c_deinit(FAR struct stm32_i2c_priv_s *priv)
 
   stm32_i2c_putreg(priv, STM32_I2C_CR1_OFFSET, 0);
 
+  /* Unconfigure GPIO pins */
+
   stm32_unconfiggpio(priv->config->scl_pin);
   stm32_unconfiggpio(priv->config->sda_pin);
 
+  /* Disable and detach interrupts */
+
 #ifndef CONFIG_I2C_POLLED
   up_disable_irq(priv->config->ev_irq);
   up_disable_irq(priv->config->er_irq);
   irq_detach(priv->config->ev_irq);
   irq_detach(priv->config->er_irq);
 #endif
-  modifyreg32(STM32_RCC_APB1ENR, priv->config->clk_bit, 0);
 
+  /* Disable clocking */
+
+  modifyreg32(STM32_RCC_APB1ENR, priv->config->clk_bit, 0);
   return OK;
 }
 
@@ -1533,14 +1574,14 @@ static int stm32_i2c_process(FAR struct i2c_dev_s *dev, FAR struct i2c_msg_s *ms
   struct stm32_i2c_inst_s     *inst = (struct stm32_i2c_inst_s *)dev;
   FAR struct stm32_i2c_priv_s *priv = inst->priv;
   uint32_t    status = 0;
-  //uint32_t    ahbenr;
+  uint32_t    ahbenr;
   int         errval = 0;
 
   ASSERT(count);
 
   /* Disable FSMC that shares a pin with I2C1 (LBAR) */
 
-  (void)stm32_i2c_disablefsmc(priv);
+  ahbenr = stm32_i2c_disablefsmc(priv);
 
   /* Wait for any STOP in progress.  NOTE:  If we have to disable the FSMC
    * then we cannot do this at the top of the loop, unfortunately.  The STOP
@@ -1548,11 +1589,7 @@ static int stm32_i2c_process(FAR struct i2c_dev_s *dev, FAR struct i2c_msg_s *ms
    */
 
 #ifndef I2C1_FSMC_CONFLICT
-    #if CONFIG_STM32_I2CTIMEOUS_START_STOP > 0
-      stm32_i2c_sem_waitstop(priv, CONFIG_STM32_I2CTIMEOUS_START_STOP);
-    #else 
-      stm32_i2c_sem_waitstop(priv, CONFIG_STM32_I2CTIMEOMS + CONFIG_STM32_I2CTIMEOSEC * 1000000);
-    #endif
+  stm32_i2c_sem_waitstop(priv);
 #endif
 
   /* Clear any pending error interrupts */
@@ -1573,22 +1610,6 @@ static int stm32_i2c_process(FAR struct i2c_dev_s *dev, FAR struct i2c_msg_s *ms
   priv->msgv = msgs;
   priv->msgc = count;
 
-  /* Calculate timeout values */
-  int timeout_us = 0;
-  #if CONFIG_STM32_I2CTIMEOUS_PER_BYTE > 0
-    /* Count the number of bytes left to process */
-    int i;
-    int bytecount = 10;
-    for (i = 0; i < count; i++)
-      {
-        bytecount += msgs[i].length;
-      }
-    timeout_us = CONFIG_STM32_I2CTIMEOUS_PER_BYTE * bytecount;
-    //i2cvdbg("i2c wait: %d\n", timeout_us);
-  #else
-    timeout_us = CONFIG_STM32_I2CTIMEOMS + CONFIG_STM32_I2CTIMEOSEC * 1000000;
-  #endif
-
   /* Reset I2C trace logic */
 
   stm32_i2c_tracereset(priv);
@@ -1608,7 +1629,7 @@ static int stm32_i2c_process(FAR struct i2c_dev_s *dev, FAR struct i2c_msg_s *ms
    * the BUSY flag.
    */
 
-  if (stm32_i2c_sem_waitdone(priv, timeout_us) < 0)
+  if (stm32_i2c_sem_waitdone(priv) < 0)
     {
       status = stm32_i2c_getstatus(priv);
       errval = ETIMEDOUT;
@@ -1623,7 +1644,9 @@ static int stm32_i2c_process(FAR struct i2c_dev_s *dev, FAR struct i2c_msg_s *ms
        */
 
       stm32_i2c_clrstart(priv);
-      // XXX also clear busy flag in case of timeout
+
+      /* Clear busy flag in case of timeout */
+
       status = priv->status & 0xffff;
     }
   else
@@ -1953,11 +1976,14 @@ int up_i2cuninitialize(FAR struct i2c_dev_s * dev)
  *
  ************************************************************************************/
 
+#ifdef CONFIG_I2C_RESET
 int up_i2creset(FAR struct i2c_dev_s * dev)
 {
   struct stm32_i2c_priv_s * priv;
-  unsigned clock_count;
-  unsigned stretch_count;
+  unsigned int clock_count;
+  unsigned int stretch_count;
+  uint32_t scl_gpio;
+  uint32_t sda_gpio;
   int ret = ERROR;
   irqstate_t state;
 
@@ -1979,83 +2005,70 @@ int up_i2creset(FAR struct i2c_dev_s * dev)
 
   stm32_i2c_deinit(priv);
 
-  /* If possible, use GPIO configuration to un-wedge the bus */
+  /* Use GPIO configuration to un-wedge the bus */
 
-  if ((priv->config->scl_gpio != 0) && (priv->config->sda_gpio != 0))
+  scl_gpio = MKI2C_OUTPUT(priv->config->scl_pin);
+  sda_gpio = MKI2C_OUTPUT(priv->config->sda_pin);
+
+  /* Clock the bus until any slaves currently driving it let it go. */
+
+  clock_count = 0;
+  while (!stm32_gpioread(sda_gpio)) 
     {
-      stm32_configgpio(priv->config->scl_gpio);
-      stm32_configgpio(priv->config->sda_gpio);
+      /* Give up if we have tried too hard */
 
-      /*
-       * Clock the bus until any slaves currently driving it let it go.
-       */
+      if (clock_count++ > 1000)
+        { 
+          goto out;
+        }
 
-      clock_count = 0;
-      while (!stm32_gpioread(priv->config->sda_gpio)) 
-        {
+      /* Sniff to make sure that clock stretching has finished.
+       *
+       * If the bus never relaxes, the reset has failed.
+       */
 
+      stretch_count = 0;
+      while (!stm32_gpioread(scl_gpio))
+        { 
           /* Give up if we have tried too hard */
 
-          if (clock_count++ > 1000)
+          if (stretch_count++ > 1000)
             { 
               goto out;
             }
 
-          /*
-           * Sniff to make sure that clock stretching has finished.
-           *
-           * If the bus never relaxes, the reset has failed.
-           */
-
-          stretch_count = 0;
-          while (!stm32_gpioread(priv->config->scl_gpio))
-            { 
-
-              /* Give up if we have tried too hard */
-
-              if (stretch_count++ > 1000)
-                { 
-                  goto out;
-                }
-
-              up_udelay(10);
-
-            }
-
-            /* Drive SCL low */
-
-            stm32_gpiowrite(priv->config->scl_gpio, 0);
-            up_udelay(10);
-
-            /* Drive SCL high again */
-
-            stm32_gpiowrite(priv->config->scl_gpio, 1);
-            up_udelay(10);
-
+          up_udelay(10);
         }
 
-      /*
-       * Generate a start followed by a stop to reset slave
-       * state machines.
-       */
+      /* Drive SCL low */
 
-      stm32_gpiowrite(priv->config->sda_gpio, 0);
-      up_udelay(10);
-      stm32_gpiowrite(priv->config->scl_gpio, 0);
-      up_udelay(10);
-      stm32_gpiowrite(priv->config->scl_gpio, 1);
-      up_udelay(10);
-      stm32_gpiowrite(priv->config->sda_gpio, 1);
+      stm32_gpiowrite(scl_gpio, 0);
       up_udelay(10);
 
-      /*
-       * Revert the GPIO configuration.
-       */
-      stm32_unconfiggpio(priv->config->sda_gpio);
-      stm32_unconfiggpio(priv->config->scl_gpio);
+      /* Drive SCL high again */
 
+      stm32_gpiowrite(scl_gpio, 1);
+      up_udelay(10);
     }
 
+  /* Generate a start followed by a stop to reset slave
+   * state machines.
+   */
+
+  stm32_gpiowrite(sda_gpio, 0);
+  up_udelay(10);
+  stm32_gpiowrite(scl_gpio, 0);
+  up_udelay(10);
+  stm32_gpiowrite(scl_gpio, 1);
+  up_udelay(10);
+  stm32_gpiowrite(sda_gpio, 1);
+  up_udelay(10);
+
+  /* Revert the GPIO configuration. */
+ 
+  stm32_unconfiggpio(sda_gpio);
+  stm32_unconfiggpio(scl_gpio);
+
   /* Re-init the port */
 
   stm32_i2c_init(priv);
@@ -2063,11 +2076,11 @@ int up_i2creset(FAR struct i2c_dev_s * dev)
 
 out:
 
-  /* release the port for re-use by other clients */
+  /* Release the port for re-use by other clients */
 
   stm32_i2c_sem_post(dev);
-
   return ret;
 }
+#endif /* CONFIG_I2C_RESET */
 
-#endif /* defined(CONFIG_STM32_I2C1) || defined(CONFIG_STM32_I2C2) || defined(CONFIG_STM32_I2C3) */
+#endif /* CONFIG_STM32_I2C1 || CONFIG_STM32_I2C2 || CONFIG_STM32_I2C3 */
diff --git a/nuttx/arch/arm/src/stm32/stm32_lowputc.c b/nuttx/arch/arm/src/stm32/stm32_lowputc.c
index 7f7205672..6cb07dad9 100644
--- a/nuttx/arch/arm/src/stm32/stm32_lowputc.c
+++ b/nuttx/arch/arm/src/stm32/stm32_lowputc.c
@@ -67,6 +67,14 @@
 #  define STM32_CONSOLE_2STOP    CONFIG_USART1_2STOP
 #  define STM32_CONSOLE_TX       GPIO_USART1_TX
 #  define STM32_CONSOLE_RX       GPIO_USART1_RX
+#  ifdef CONFIG_USART1_RS485
+#    define STM32_CONSOLE_RS485_DIR GPIO_USART1_RS485_DIR
+#    if (CONFIG_USART1_RS485_DIR_POLARITY == 0)
+#      define STM32_CONSOLE_RS485_DIR_POLARITY false
+#    else
+#      define STM32_CONSOLE_RS485_DIR_POLARITY true
+#    endif
+#  endif
 #elif defined(CONFIG_USART2_SERIAL_CONSOLE)
 #  define STM32_CONSOLE_BASE     STM32_USART2_BASE
 #  define STM32_APBCLOCK         STM32_PCLK1_FREQUENCY
@@ -76,6 +84,14 @@
 #  define STM32_CONSOLE_2STOP    CONFIG_USART2_2STOP
 #  define STM32_CONSOLE_TX       GPIO_USART2_TX
 #  define STM32_CONSOLE_RX       GPIO_USART2_RX
+#  ifdef CONFIG_USART2_RS485
+#    define STM32_CONSOLE_RS485_DIR GPIO_USART2_RS485_DIR
+#    if (CONFIG_USART2_RS485_DIR_POLARITY == 0)
+#      define STM32_CONSOLE_RS485_DIR_POLARITY false
+#    else
+#      define STM32_CONSOLE_RS485_DIR_POLARITY true
+#    endif
+#  endif
 #elif defined(CONFIG_USART3_SERIAL_CONSOLE)
 #  define STM32_CONSOLE_BASE     STM32_USART3_BASE
 #  define STM32_APBCLOCK         STM32_PCLK1_FREQUENCY
@@ -85,6 +101,14 @@
 #  define STM32_CONSOLE_2STOP    CONFIG_USART3_2STOP
 #  define STM32_CONSOLE_TX       GPIO_USART3_TX
 #  define STM32_CONSOLE_RX       GPIO_USART3_RX
+#  ifdef CONFIG_USART3_RS485
+#    define STM32_CONSOLE_RS485_DIR GPIO_USART3_RS485_DIR
+#    if (CONFIG_USART3_RS485_DIR_POLARITY == 0)
+#      define STM32_CONSOLE_RS485_DIR_POLARITY false
+#    else
+#      define STM32_CONSOLE_RS485_DIR_POLARITY true
+#    endif
+#  endif
 #elif defined(CONFIG_UART4_SERIAL_CONSOLE)
 #  define STM32_CONSOLE_BASE     STM32_UART4_BASE
 #  define STM32_APBCLOCK         STM32_PCLK1_FREQUENCY
@@ -94,6 +118,14 @@
 #  define STM32_CONSOLE_2STOP    CONFIG_UART4_2STOP
 #  define STM32_CONSOLE_TX       GPIO_UART4_TX
 #  define STM32_CONSOLE_RX       GPIO_UART4_RX
+#  ifdef CONFIG_UART4_RS485
+#    define STM32_CONSOLE_RS485_DIR GPIO_UART4_RS485_DIR
+#    if (CONFIG_UART4_RS485_DIR_POLARITY == 0)
+#      define STM32_CONSOLE_RS485_DIR_POLARITY false
+#    else
+#      define STM32_CONSOLE_RS485_DIR_POLARITY true
+#    endif
+#  endif
 #elif defined(CONFIG_UART5_SERIAL_CONSOLE)
 #  define STM32_CONSOLE_BASE     STM32_UART5_BASE
 #  define STM32_APBCLOCK         STM32_PCLK1_FREQUENCY
@@ -103,6 +135,14 @@
 #  define STM32_CONSOLE_2STOP    CONFIG_UART5_2STOP
 #  define STM32_CONSOLE_TX       GPIO_UART5_TX
 #  define STM32_CONSOLE_RX       GPIO_UART5_RX
+#  ifdef CONFIG_UART5_RS485
+#    define STM32_CONSOLE_RS485_DIR GPIO_UART5_RS485_DIR
+#    if (CONFIG_UART5_RS485_DIR_POLARITY == 0)
+#      define STM32_CONSOLE_RS485_DIR_POLARITY false
+#    else
+#      define STM32_CONSOLE_RS485_DIR_POLARITY true
+#    endif
+#  endif
 #elif defined(CONFIG_USART6_SERIAL_CONSOLE)
 #  define STM32_CONSOLE_BASE     STM32_USART6_BASE
 #  define STM32_APBCLOCK         STM32_PCLK2_FREQUENCY
@@ -112,6 +152,14 @@
 #  define STM32_CONSOLE_2STOP    CONFIG_USART6_2STOP
 #  define STM32_CONSOLE_TX       GPIO_USART6_TX
 #  define STM32_CONSOLE_RX       GPIO_USART6_RX
+#  ifdef CONFIG_USART6_RS485
+#    define STM32_CONSOLE_RS485_DIR GPIO_USART6_RS485_DIR
+#    if (CONFIG_USART6_RS485_DIR_POLARITY == 0)
+#      define STM32_CONSOLE_RS485_DIR_POLARITY false
+#    else
+#      define STM32_CONSOLE_RS485_DIR_POLARITY true
+#    endif
+#  endif
 #endif
 
 /* CR1 settings */
@@ -230,10 +278,19 @@ void up_lowputc(char ch)
   /* Wait until the TX data register is empty */
 
   while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_SR_OFFSET) & USART_SR_TXE) == 0);
+#if STM32_CONSOLE_RS485_DIR
+  stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, STM32_CONSOLE_RS485_DIR_POLARITY);
+#endif
 
   /* Then send the character */
 
   putreg32((uint32_t)ch, STM32_CONSOLE_BASE + STM32_USART_DR_OFFSET);
+
+#if STM32_CONSOLE_RS485_DIR
+  while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_SR_OFFSET) & USART_SR_TC) == 0);
+  stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, !STM32_CONSOLE_RS485_DIR_POLARITY);
+#endif
+
 #endif
 }
 
@@ -328,7 +385,14 @@ void stm32_lowsetup(void)
 
 #ifdef STM32_CONSOLE_TX
   stm32_configgpio(STM32_CONSOLE_TX);
-  stm32_configgpio(STM32_CONSOLE_TX);
+#endif
+#ifdef STM32_CONSOLE_RX
+  stm32_configgpio(STM32_CONSOLE_RX);
+#endif
+
+#if STM32_CONSOLE_RS485_DIR
+  stm32_configgpio(STM32_CONSOLE_RS485_DIR);
+  stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, !STM32_CONSOLE_RS485_DIR_POLARITY);
 #endif
 
   /* Enable and configure the selected console device */
@@ -382,7 +446,14 @@ void stm32_lowsetup(void)
 
 #ifdef STM32_CONSOLE_TX
   stm32_configgpio(STM32_CONSOLE_TX);
-  stm32_configgpio(STM32_CONSOLE_TX);
+#endif
+#ifdef STM32_CONSOLE_RX
+  stm32_configgpio(STM32_CONSOLE_RX);
+#endif
+
+#if STM32_CONSOLE_RS485_DIR
+  stm32_configgpio(STM32_CONSOLE_RS485_DIR);
+  stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, !STM32_CONSOLE_RS485_DIR_POLARITY);
 #endif
 
   /* Enable and configure the selected console device */
diff --git a/nuttx/arch/arm/src/stm32/stm32_otgfsdev.c b/nuttx/arch/arm/src/stm32/stm32_otgfsdev.c
index 461d500ad..94772b693 100644
--- a/nuttx/arch/arm/src/stm32/stm32_otgfsdev.c
+++ b/nuttx/arch/arm/src/stm32/stm32_otgfsdev.c
@@ -3651,10 +3651,14 @@ static int stm32_epout_configure(FAR struct stm32_ep_s *privep, uint8_t eptype,
   regval  = stm32_getreg(regaddr);
   if ((regval & OTGFS_DOEPCTL_USBAEP) == 0)
     {
-      regval &= ~(OTGFS_DOEPCTL_MPSIZ_MASK | OTGFS_DIEPCTL_EPTYP_MASK | OTGFS_DIEPCTL_TXFNUM_MASK);
+      if (regval & OTGFS_DOEPCTL_NAKSTS)
+        {
+          regval |= OTGFS_DOEPCTL_CNAK;
+        }
+      
+      regval &= ~(OTGFS_DOEPCTL_MPSIZ_MASK | OTGFS_DOEPCTL_EPTYP_MASK);
       regval |= mpsiz;
       regval |= (eptype << OTGFS_DOEPCTL_EPTYP_SHIFT);
-      regval |= (eptype << OTGFS_DIEPCTL_TXFNUM_SHIFT);
       regval |= (OTGFS_DOEPCTL_SD0PID | OTGFS_DOEPCTL_USBAEP);
       stm32_putreg(regval, regaddr);
 
@@ -3743,6 +3747,11 @@ static int stm32_epin_configure(FAR struct stm32_ep_s *privep, uint8_t eptype,
   regval  = stm32_getreg(regaddr);
   if ((regval & OTGFS_DIEPCTL_USBAEP) == 0)
     {
+      if (regval & OTGFS_DIEPCTL_NAKSTS)
+        {
+          regval |= OTGFS_DIEPCTL_CNAK;
+        }
+      
       regval &= ~(OTGFS_DIEPCTL_MPSIZ_MASK | OTGFS_DIEPCTL_EPTYP_MASK | OTGFS_DIEPCTL_TXFNUM_MASK);
       regval |= mpsiz;
       regval |= (eptype << OTGFS_DIEPCTL_EPTYP_SHIFT);
@@ -3900,7 +3909,7 @@ static void stm32_epout_disable(FAR struct stm32_ep_s *privep)
  * Name: stm32_epin_disable
  *
  * Description:
- *   Diable an IN endpoint will no longer be used
+ *   Disable an IN endpoint when it will no longer be used
  *
  *******************************************************************************/
 
@@ -3912,6 +3921,17 @@ static void stm32_epin_disable(FAR struct stm32_ep_s *privep)
 
   usbtrace(TRACE_EPDISABLE, privep->epphy);
 
+  /* After USB reset, the endpoint will already be deactivated by the
+   * hardware. Trying to disable again will just hang in the wait.
+   */
+
+  regaddr = STM32_OTGFS_DIEPCTL(privep->epphy);
+  regval  = stm32_getreg(regaddr);
+  if ((regval & OTGFS_DIEPCTL_USBAEP) == 0)
+    {
+      return;
+    }
+
   /* Make sure that there is no pending IPEPNE interrupt (because we are
    * to poll this bit below).
    */
diff --git a/nuttx/arch/arm/src/stm32/stm32_otgfshost.c b/nuttx/arch/arm/src/stm32/stm32_otgfshost.c
index 02b12ec87..80a9392dc 100644
--- a/nuttx/arch/arm/src/stm32/stm32_otgfshost.c
+++ b/nuttx/arch/arm/src/stm32/stm32_otgfshost.c
@@ -51,6 +51,7 @@
 
 #include <nuttx/arch.h>
 #include <nuttx/kmalloc.h>
+#include <nuttx/clock.h>
 #include <nuttx/usb/usb.h>
 #include <nuttx/usb/usbhost.h>
 
@@ -149,8 +150,8 @@
 
 #define STM32_READY_DELAY         200000 /* In loop counts */
 #define STM32_FLUSH_DELAY         200000 /* In loop counts */
-#define STM32_SETUP_DELAY         5000   /* In frames */
-#define STM32_DATANAK_DELAY       5000   /* In frames */
+#define STM32_SETUP_DELAY         (5000 / MSEC_PER_TICK) /* 5 seconds in system ticks */
+#define STM32_DATANAK_DELAY       (5000 / MSEC_PER_TICK) /* 5 seconds in system ticks */
 
 /* Ever-present MIN/MAX macros */
 
@@ -305,7 +306,9 @@ static void stm32_chan_wakeup(FAR struct stm32_usbhost_s *priv,
 /* Control/data transfer logic *************************************************/
 
 static void stm32_transfer_start(FAR struct stm32_usbhost_s *priv, int chidx);
+#if 0 /* Not used */
 static inline uint16_t stm32_getframe(void);
+#endif
 static int stm32_ctrl_sendsetup(FAR struct stm32_usbhost_s *priv,
                                 FAR const struct usb_ctrlreq_s *req);
 static int stm32_ctrl_senddata(FAR struct stm32_usbhost_s *priv,
@@ -1182,14 +1185,18 @@ static void stm32_transfer_start(FAR struct stm32_usbhost_s *priv, int chidx)
  * Name: stm32_getframe
  *
  * Description:
- *   Get the current frame number.
+ *   Get the current frame number.  The frame number (FRNUM) field increments
+ *   when a new SOF is transmitted on the USB, and is cleared to 0 when it
+ *   reaches 0x3fff.
  *
  *******************************************************************************/
 
+#if 0 /* Not used */
 static inline uint16_t stm32_getframe(void)
 {
   return (uint16_t)(stm32_getreg(STM32_OTGFS_HFNUM) & OTGFS_HFNUM_FRNUM_MASK);
 }
+#endif
 
 /*******************************************************************************
  * Name: stm32_ctrl_sendsetup
@@ -1203,14 +1210,14 @@ static int stm32_ctrl_sendsetup(FAR struct stm32_usbhost_s *priv,
                                 FAR const struct usb_ctrlreq_s *req)
 {
   FAR struct stm32_chan_s *chan;
-  uint16_t start;
-  uint16_t elapsed;
+  uint32_t start;
+  uint32_t elapsed;
   int ret;
 
   /* Loop while the device reports NAK (and a timeout is not exceeded */
 
   chan  = &priv->chan[priv->ep0out];
-  start = stm32_getframe();
+  start = clock_systimer();
 
   do
     {
@@ -1258,7 +1265,7 @@ static int stm32_ctrl_sendsetup(FAR struct stm32_usbhost_s *priv,
 
      /* Get the elapsed time (in frames) */
 
-     elapsed = stm32_getframe() - start;
+     elapsed = clock_systimer() - start;
     }
   while (elapsed < STM32_SETUP_DELAY);
 
@@ -1367,8 +1374,8 @@ static int stm32_in_transfer(FAR struct stm32_usbhost_s *priv, int chidx,
                              FAR uint8_t *buffer, size_t buflen)
 {
   FAR struct stm32_chan_s *chan;
-  uint16_t start;
-  uint16_t elapsed;
+  uint32_t start;
+  uint32_t elapsed;
   int ret = OK;
 
   /* Loop until the transfer completes (i.e., buflen is decremented to zero)
@@ -1379,7 +1386,7 @@ static int stm32_in_transfer(FAR struct stm32_usbhost_s *priv, int chidx,
   chan->buffer = buffer;
   chan->buflen = buflen;
 
-  start = stm32_getframe();
+  start = clock_systimer();
   while (chan->buflen > 0)
     {
       /* Set up for the wait BEFORE starting the transfer */
@@ -1447,7 +1454,7 @@ static int stm32_in_transfer(FAR struct stm32_usbhost_s *priv, int chidx,
            * buffer pointer and buffer size will be unaltered.
            */
 
-          elapsed = stm32_getframe() - start;
+          elapsed = clock_systimer() - start;
           if (ret != -EAGAIN ||                       /* Not a NAK condition OR */
               elapsed >= STM32_DATANAK_DELAY ||       /* Timeout has elapsed OR */
               chan->buflen != buflen)                 /* Data has been partially transferred */
@@ -1474,8 +1481,8 @@ static int stm32_out_transfer(FAR struct stm32_usbhost_s *priv, int chidx,
                               FAR uint8_t *buffer, size_t buflen)
 {
   FAR struct stm32_chan_s *chan;
-  uint16_t start;
-  uint16_t elapsed;
+  uint32_t start;
+  uint32_t elapsed;
   size_t xfrlen;
   int ret = OK;
 
@@ -1484,7 +1491,7 @@ static int stm32_out_transfer(FAR struct stm32_usbhost_s *priv, int chidx,
    */
 
   chan         = &priv->chan[chidx];
-  start        = stm32_getframe();
+  start        = clock_systimer();
 
   while (buflen > 0)
     {
@@ -1569,7 +1576,7 @@ static int stm32_out_transfer(FAR struct stm32_usbhost_s *priv, int chidx,
            * buffer pointer and buffer size will be unaltered.
            */
 
-          elapsed = stm32_getframe() - start;
+          elapsed = clock_systimer() - start;
           if (ret != -EAGAIN ||                       /* Not a NAK condition OR */
               elapsed >= STM32_DATANAK_DELAY ||       /* Timeout has elapsed OR */
               chan->buflen != xfrlen)                 /* Data has been partially transferred */
@@ -3540,8 +3547,8 @@ static int stm32_ctrlin(FAR struct usbhost_driver_s *drvr,
 {
   struct stm32_usbhost_s *priv = (struct stm32_usbhost_s *)drvr;
   uint16_t buflen;
-  uint16_t start;
-  uint16_t elapsed;
+  uint32_t start;
+  uint32_t elapsed;
   int retries;
   int ret;
 
@@ -3573,7 +3580,7 @@ static int stm32_ctrlin(FAR struct usbhost_driver_s *drvr,
 
       /* Get the start time.  Loop again until the timeout expires */
 
-      start = stm32_getframe();
+      start = clock_systimer();
       do
         {
           /* Handle the IN data phase (if any) */
@@ -3606,7 +3613,7 @@ static int stm32_ctrlin(FAR struct usbhost_driver_s *drvr,
 
           /* Get the elapsed time (in frames) */
 
-          elapsed = stm32_getframe() - start;
+          elapsed = clock_systimer() - start;
         }
       while (elapsed < STM32_DATANAK_DELAY);
     }
@@ -3623,8 +3630,8 @@ static int stm32_ctrlout(FAR struct usbhost_driver_s *drvr,
 {
   struct stm32_usbhost_s *priv = (struct stm32_usbhost_s *)drvr;
   uint16_t buflen;
-  uint16_t start;
-  uint16_t elapsed;
+  uint32_t start;
+  uint32_t elapsed;
   int retries;
   int ret;
 
@@ -3658,7 +3665,7 @@ static int stm32_ctrlout(FAR struct usbhost_driver_s *drvr,
 
       /* Get the start time.  Loop again until the timeout expires */
 
-      start = stm32_getframe();
+      start = clock_systimer();
       do
         {
           /* Handle the data OUT phase (if any) */
@@ -3693,7 +3700,7 @@ static int stm32_ctrlout(FAR struct usbhost_driver_s *drvr,
 
           /* Get the elapsed time (in frames) */
 
-          elapsed = stm32_getframe() - start;
+          elapsed = clock_systimer() - start;
         }
       while (elapsed < STM32_DATANAK_DELAY);
     }
diff --git a/nuttx/arch/arm/src/stm32/stm32_qencoder.c b/nuttx/arch/arm/src/stm32/stm32_qencoder.c
index 8553296f9..d37614c03 100644
--- a/nuttx/arch/arm/src/stm32/stm32_qencoder.c
+++ b/nuttx/arch/arm/src/stm32/stm32_qencoder.c
@@ -607,6 +607,7 @@ static FAR struct stm32_lowerhalf_s *stm32_tim2lower(int tim)
 #endif
 #ifdef CONFIG_STM32_TIM3_QE
     case 3:
+      return &g_tim3lower;
 #endif
 #ifdef CONFIG_STM32_TIM4_QE
     case 4:
diff --git a/nuttx/arch/arm/src/stm32/stm32_serial.c b/nuttx/arch/arm/src/stm32/stm32_serial.c
index 0868c3cd3..aa46a8987 100644
--- a/nuttx/arch/arm/src/stm32/stm32_serial.c
+++ b/nuttx/arch/arm/src/stm32/stm32_serial.c
@@ -96,6 +96,19 @@
 #    endif
 #  endif
 
+/* Currently RS-485 support cannot be enabled when RXDMA is in use due to lack
+ * of testing - RS-485 support was developed on STM32F1x
+ */
+
+#  if (defined(CONFIG_USART1_RXDMA) && defined(CONFIG_USART1_RS485)) || \
+      (defined(CONFIG_USART2_RXDMA) && defined(CONFIG_USART2_RS485)) || \
+      (defined(CONFIG_USART3_RXDMA) && defined(CONFIG_USART3_RS485)) || \
+      (defined(CONFIG_UART4_RXDMA) && defined(CONFIG_UART4_RS485)) || \
+      (defined(CONFIG_UART5_RXDMA) && defined(CONFIG_UART5_RS485)) || \
+      (defined(CONFIG_USART6_RXDMA) && defined(CONFIG_USART6_RS485))
+#    error "RXDMA and RS-485 cannot be enabled at the same time for the same U[S]ART"
+#  endif
+
 /* For the F4, there are alternate DMA channels for USART1 and 6.
  * Logic in the board.h file make the DMA channel selection by defining
  * the following in the board.h file.
@@ -219,6 +232,11 @@ struct up_dev_s
   uint32_t          rxdmanext; /* Next byte in the DMA buffer to be read */
   char       *const rxfifo;    /* Receive DMA buffer */
 #endif
+
+#ifdef HAVE_RS485
+  const uint32_t    rs485_dir_gpio; /* U[S]ART RS-485 DIR GPIO pin configuration */
+  const bool        rs485_dir_polarity; /* U[S]ART RS-485 DIR pin state for TX enabled */
+#endif
 };
 
 /****************************************************************************
@@ -415,6 +433,15 @@ static struct up_dev_s g_usart1priv =
   .rxfifo        = g_usart1rxfifo,
 #endif
   .vector        = up_interrupt_usart1,
+
+#ifdef CONFIG_USART1_RS485
+  .rs485_dir_gpio = GPIO_USART1_RS485_DIR,
+#  if (CONFIG_USART1_RS485_DIR_POLARITY == 0)
+  .rs485_dir_polarity = false,
+#  else
+  .rs485_dir_polarity = true,
+#  endif
+#endif
 };
 #endif
 
@@ -468,6 +495,15 @@ static struct up_dev_s g_usart2priv =
   .rxfifo        = g_usart2rxfifo,
 #endif
   .vector        = up_interrupt_usart2,
+
+#ifdef CONFIG_USART2_RS485
+  .rs485_dir_gpio = GPIO_USART2_RS485_DIR,
+#  if (CONFIG_USART2_RS485_DIR_POLARITY == 0)
+  .rs485_dir_polarity = false,
+#  else
+  .rs485_dir_polarity = true,
+#  endif
+#endif
 };
 #endif
 
@@ -521,6 +557,15 @@ static struct up_dev_s g_usart3priv =
   .rxfifo        = g_usart3rxfifo,
 #endif
   .vector        = up_interrupt_usart3,
+
+#ifdef CONFIG_USART3_RS485
+  .rs485_dir_gpio = GPIO_USART3_RS485_DIR,
+#  if (CONFIG_USART3_RS485_DIR_POLARITY == 0)
+  .rs485_dir_polarity = false,
+#  else
+  .rs485_dir_polarity = true,
+#  endif
+#endif
 };
 #endif
 
@@ -570,6 +615,15 @@ static struct up_dev_s g_uart4priv =
   .rxfifo        = g_uart4rxfifo,
 #endif
   .vector        = up_interrupt_uart4,
+
+#ifdef CONFIG_UART4_RS485
+  .rs485_dir_gpio = GPIO_UART4_RS485_DIR,
+#  if (CONFIG_UART4_RS485_DIR_POLARITY == 0)
+  .rs485_dir_polarity = false,
+#  else
+  .rs485_dir_polarity = true,
+#  endif
+#endif
 };
 #endif
 
@@ -619,6 +673,15 @@ static struct up_dev_s g_uart5priv =
   .rxfifo        = g_uart5rxfifo,
 #endif
   .vector         = up_interrupt_uart5,
+
+#ifdef CONFIG_UART5_RS485
+  .rs485_dir_gpio = GPIO_UART5_RS485_DIR,
+#  if (CONFIG_UART5_RS485_DIR_POLARITY == 0)
+  .rs485_dir_polarity = false,
+#  else
+  .rs485_dir_polarity = true,
+#  endif
+#endif
 };
 #endif
 
@@ -672,6 +735,15 @@ static struct up_dev_s g_usart6priv =
   .rxfifo        = g_usart6rxfifo,
 #endif
   .vector         = up_interrupt_usart6,
+
+#ifdef CONFIG_USART6_RS485
+  .rs485_dir_gpio = GPIO_USART6_RS485_DIR,
+#  if (CONFIG_USART6_RS485_DIR_POLARITY == 0)
+  .rs485_dir_polarity = false,
+#  else
+  .rs485_dir_polarity = true,
+#  endif
+#endif
 };
 #endif
 
@@ -744,8 +816,8 @@ static void up_restoreusartint(struct up_dev_s *priv, uint16_t ie)
   /* And restore the interrupt state (see the interrupt enable/usage table above) */
 
   cr = up_serialin(priv, STM32_USART_CR1_OFFSET);
-  cr &= ~(USART_CR1_RXNEIE|USART_CR1_TXEIE|USART_CR1_PEIE);
-  cr |= (ie & (USART_CR1_RXNEIE|USART_CR1_TXEIE|USART_CR1_PEIE));
+  cr &= ~(USART_CR1_USED_INTS);
+  cr |= (ie & (USART_CR1_USED_INTS));
   up_serialout(priv, STM32_USART_CR1_OFFSET, cr);
 
   cr = up_serialin(priv, STM32_USART_CR3_OFFSET);
@@ -772,7 +844,7 @@ static inline void up_disableusartint(struct up_dev_s *priv, uint16_t *ie)
        * USART_CR1_IDLEIE    4  USART_SR_IDLE   Idle Line Detected             (not used)
        * USART_CR1_RXNEIE    5  USART_SR_RXNE   Received Data Ready to be Read
        * "              "       USART_SR_ORE    Overrun Error Detected
-       * USART_CR1_TCIE      6  USART_SR_TC     Transmission Complete          (not used)
+       * USART_CR1_TCIE      6  USART_SR_TC     Transmission Complete          (used only for RS-485)
        * USART_CR1_TXEIE     7  USART_SR_TXE    Transmit Data Register Empty
        * USART_CR1_PEIE      8  USART_SR_PE     Parity Error
        *
@@ -791,7 +863,7 @@ static inline void up_disableusartint(struct up_dev_s *priv, uint16_t *ie)
        * overlap.  This logic would fail if we needed the break interrupt!
        */
 
-      *ie = (cr1 & (USART_CR1_RXNEIE|USART_CR1_TXEIE|USART_CR1_PEIE)) | (cr3 & USART_CR3_EIE);
+      *ie = (cr1 & (USART_CR1_USED_INTS)) | (cr3 & USART_CR3_EIE);
     }
 
   /* Disable all interrupts */
@@ -853,18 +925,18 @@ static void up_set_format(struct uart_dev_s *dev)
    *   usartdiv32 = 32 * usartdiv = fCK / (baud/2)
    */
 
-  usartdiv32 = priv->apbclock / (priv->baud >> 1);
+   usartdiv32 = priv->apbclock / (priv->baud >> 1);
 
-  /* The mantissa part is then */
+   /* The mantissa part is then */
 
-  mantissa   = usartdiv32 >> 5;
-  brr        = mantissa << USART_BRR_MANT_SHIFT;
+   mantissa   = usartdiv32 >> 5;
+   brr        = mantissa << USART_BRR_MANT_SHIFT;
 
-  /* The fractional remainder (with rounding) */
+   /* The fractional remainder (with rounding) */
 
-  fraction   = (usartdiv32 - (mantissa << 5) + 1) >> 1;
-  brr       |= fraction << USART_BRR_FRAC_SHIFT;
-  up_serialout(priv, STM32_USART_BRR_OFFSET, brr);
+   fraction   = (usartdiv32 - (mantissa << 5) + 1) >> 1;
+   brr       |= fraction << USART_BRR_FRAC_SHIFT;
+   up_serialout(priv, STM32_USART_BRR_OFFSET, brr);
 
   /* Configure parity mode */
 
@@ -946,6 +1018,14 @@ static int up_setup(struct uart_dev_s *dev)
       stm32_configgpio(priv->rts_gpio);
     }
 
+#if HAVE_RS485
+  if (priv->rs485_dir_gpio != 0)
+    {
+      stm32_configgpio(priv->rs485_dir_gpio);
+      stm32_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity);
+    }
+#endif
+
   /* Configure CR2 */
   /* Clear CLKEN, CPOL, CPHA, LBCL, and interrupt enable bits */
 
@@ -990,13 +1070,11 @@ static int up_setup(struct uart_dev_s *dev)
   regval      = up_serialin(priv, STM32_USART_CR1_OFFSET);
   regval     |= (USART_CR1_UE|USART_CR1_TE|USART_CR1_RE);
   up_serialout(priv, STM32_USART_CR1_OFFSET, regval);
-
-#endif /* CONFIG_SUPPRESS_UART_CONFIG */
+#endif
 
   /* Set up the cached interrupt enables value */
 
-  up_restoreusartint(priv, 0);
-
+  priv->ie    = 0;
   return OK;
 }
 
@@ -1217,7 +1295,7 @@ static int up_interrupt_common(struct up_dev_s *priv)
        * USART_CR1_IDLEIE    4  USART_SR_IDLE   Idle Line Detected              (not used)
        * USART_CR1_RXNEIE    5  USART_SR_RXNE   Received Data Ready to be Read
        * "              "       USART_SR_ORE    Overrun Error Detected
-       * USART_CR1_TCIE      6  USART_SR_TC     Transmission Complete           (not used)
+       * USART_CR1_TCIE      6  USART_SR_TC     Transmission Complete           (used only for RS-485)
        * USART_CR1_TXEIE     7  USART_SR_TXE    Transmit Data Register Empty
        * USART_CR1_PEIE      8  USART_SR_PE     Parity Error
        *
@@ -1232,6 +1310,21 @@ static int up_interrupt_common(struct up_dev_s *priv)
        * being used.
        */
 
+#ifdef HAVE_RS485
+      /* Transmission of whole buffer is over - TC is set, TXEIE is cleared.
+       * Note - this should be first, to have the most recent TC bit value from
+       * SR register - sending data affects TC, but without refresh we will not
+       * know that...
+       */
+
+      if ((priv->sr & USART_SR_TC) != 0 && (priv->ie & USART_CR1_TCIE) != 0 &&
+          (priv->ie & USART_CR1_TXEIE) == 0)
+        {
+          stm32_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity);
+          up_restoreusartint(priv, priv->ie & ~USART_CR1_TCIE);
+        }
+#endif
+
       /* Handle incoming, receive bytes. */
 
       if ((priv->sr & USART_SR_RXNE) != 0 && (priv->ie & USART_CR1_RXNEIE) != 0)
@@ -1265,13 +1358,14 @@ static int up_interrupt_common(struct up_dev_s *priv)
 
       if ((priv->sr & USART_SR_TXE) != 0 && (priv->ie & USART_CR1_TXEIE) != 0)
         {
-           /* Transmit data regiser empty ... process outgoing bytes */
+           /* Transmit data register empty ... process outgoing bytes */
 
            uart_xmitchars(&priv->dev);
            handled = true;
         }
     }
-    return OK;
+
+  return OK;
 }
 
 /****************************************************************************
@@ -1611,6 +1705,10 @@ static bool up_dma_rxavailable(struct uart_dev_s *dev)
 static void up_send(struct uart_dev_s *dev, int ch)
 {
   struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+#ifdef HAVE_RS485
+  if (priv->rs485_dir_gpio != 0)
+    stm32_gpiowrite(priv->rs485_dir_gpio, priv->rs485_dir_polarity);
+#endif
   up_serialout(priv, STM32_USART_DR_OFFSET, (uint32_t)ch);
 }
 
@@ -1631,7 +1729,7 @@ static void up_txint(struct uart_dev_s *dev, bool enable)
    *
    * Enable             Bit Status          Meaning                      Usage
    * ------------------ --- --------------- ---------------------------- ----------
-   * USART_CR1_TCIE      6  USART_SR_TC     Transmission Complete        (not used)
+   * USART_CR1_TCIE      6  USART_SR_TC     Transmission Complete        (used only for RS-485)
    * USART_CR1_TXEIE     7  USART_SR_TXE    Transmit Data Register Empty
    * USART_CR3_CTSIE    10  USART_SR_CTS    CTS flag                     (not used)
    */
@@ -1642,7 +1740,20 @@ static void up_txint(struct uart_dev_s *dev, bool enable)
       /* Set to receive an interrupt when the TX data register is empty */
 
 #ifndef CONFIG_SUPPRESS_SERIAL_INTS
-      up_restoreusartint(priv, priv->ie | USART_CR1_TXEIE);
+      uint16_t ie = priv->ie | USART_CR1_TXEIE;
+
+      /* If RS-485 is supported on this U[S]ART, then also enable the
+       * transmission complete interrupt.
+       */
+
+#  ifdef HAVE_RS485
+      if (priv->rs485_dir_gpio != 0)
+        {
+          ie |= USART_CR1_TCIE;
+        }
+#  endif
+
+      up_restoreusartint(priv, ie);
 
       /* Fake a TX interrupt here by just calling uart_xmitchars() with
        * interrupts disabled (note this may recurse).
@@ -1657,6 +1768,7 @@ static void up_txint(struct uart_dev_s *dev, bool enable)
 
       up_restoreusartint(priv, priv->ie & ~USART_CR1_TXEIE);
     }
+
   irqrestore(flags);
 }
 
diff --git a/nuttx/arch/arm/src/stm32/stm32_uart.h b/nuttx/arch/arm/src/stm32/stm32_uart.h
index a70923cbf..8ff6a9975 100644
--- a/nuttx/arch/arm/src/stm32/stm32_uart.h
+++ b/nuttx/arch/arm/src/stm32/stm32_uart.h
@@ -223,6 +223,20 @@
 #  undef SERIAL_HAVE_ONLY_DMA
 #endif
 
+/* Is RS-485 used? */
+
+#if defined(CONFIG_USART1_RS485) || defined(CONFIG_USART2_RS485) || \
+    defined(CONFIG_USART3_RS485) || defined(CONFIG_UART4_RS485)  || \
+    defined(CONFIG_UART5_RS485) || defined(CONFIG_USART6_RS485)
+#  define HAVE_RS485 1
+#endif
+
+#ifdef HAVE_RS485
+#  define USART_CR1_USED_INTS    (USART_CR1_RXNEIE | USART_CR1_TXEIE | USART_CR1_PEIE | USART_CR1_TCIE)
+#else
+#  define USART_CR1_USED_INTS    (USART_CR1_RXNEIE | USART_CR1_TXEIE | USART_CR1_PEIE)
+#endif
+
 /************************************************************************************
  * Public Types
  ************************************************************************************/
diff --git a/nuttx/arch/arm/src/stm32/stm32f10xxx_rcc.c b/nuttx/arch/arm/src/stm32/stm32f10xxx_rcc.c
index 47ed5e016..ae3fa516e 100644
--- a/nuttx/arch/arm/src/stm32/stm32f10xxx_rcc.c
+++ b/nuttx/arch/arm/src/stm32/stm32f10xxx_rcc.c
@@ -92,7 +92,11 @@ static inline void rcc_reset(void)
   putreg32(regval, STM32_RCC_CR);
 
   regval  = getreg32(STM32_RCC_CFGR);       /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */
-  regval &= ~(RCC_CFGR_PLLSRC|RCC_CFGR_PLLXTPRE|RCC_CFGR_PLLMUL_MASK|RCC_CFGR_USBPRE);
+  regval &= ~(RCC_CFGR_PLLSRC|RCC_CFGR_PLLXTPRE|RCC_CFGR_PLLMUL_MASK
+#ifndef CONFIG_STM32_VALUELINE
+              |RCC_CFGR_USBPRE
+#endif
+              );
   putreg32(regval, STM32_RCC_CFGR);
 
   putreg32(0, STM32_RCC_CIR);               /* Disable all interrupts */
@@ -224,6 +228,27 @@ static inline void rcc_enableapb1(void)
 #endif
 #endif
 
+#ifdef CONFIG_STM32_TIM12
+  /* Timer 12 clock enable */
+#ifdef CONFIG_STM32_FORCEPOWER
+  regval |= RCC_APB1ENR_TIM12EN;
+#endif
+#endif
+
+#ifdef CONFIG_STM32_TIM13
+  /* Timer 13 clock enable */
+#ifdef CONFIG_STM32_FORCEPOWER
+  regval |= RCC_APB1ENR_TIM13EN;
+#endif
+#endif
+
+#ifdef CONFIG_STM32_TIM14
+  /* Timer 14 clock enable */
+#ifdef CONFIG_STM32_FORCEPOWER
+  regval |= RCC_APB1ENR_TIM14EN;
+#endif
+#endif
+
 #ifdef CONFIG_STM32_WWDG
   /* Window Watchdog clock enable */
 
@@ -315,6 +340,13 @@ static inline void rcc_enableapb1(void)
 
   regval |= RCC_APB1ENR_DACEN;
 #endif
+
+#ifdef CONFIG_STM32_CEC
+  /* CEC clock enable */
+
+  regval |= RCC_APB1ENR_CECEN;
+#endif
+
   putreg32(regval, STM32_RCC_APB1ENR);
 }
 
@@ -404,6 +436,28 @@ static inline void rcc_enableapb2(void)
 
   regval |= RCC_APB2ENR_ADC3EN;
 #endif
+
+#ifdef CONFIG_STM32_TIM15
+  /* TIM15 Timer clock enable */
+#ifdef CONFIG_STM32_FORCEPOWER
+  regval |= RCC_APB2ENR_TIM15EN;
+#endif
+#endif
+
+#ifdef CONFIG_STM32_TIM16
+  /* TIM16 Timer clock enable */
+#ifdef CONFIG_STM32_FORCEPOWER
+  regval |= RCC_APB2ENR_TIM16EN;
+#endif
+#endif
+
+#ifdef CONFIG_STM32_TIM17
+  /* TIM17 Timer clock enable */
+#ifdef CONFIG_STM32_FORCEPOWER
+  regval |= RCC_APB2ENR_TIM17EN;
+#endif
+#endif
+
   putreg32(regval, STM32_RCC_APB2ENR);
 }
 
diff --git a/nuttx/arch/arm/src/stm32/stm32f20xxx_rcc.c b/nuttx/arch/arm/src/stm32/stm32f20xxx_rcc.c
index 335992524..ac72fb60b 100644
--- a/nuttx/arch/arm/src/stm32/stm32f20xxx_rcc.c
+++ b/nuttx/arch/arm/src/stm32/stm32f20xxx_rcc.c
@@ -631,7 +631,11 @@ static void stm32_stdclockconfig(void)
 
       /* Enable FLASH prefetch, instruction cache, data cache, and 5 wait states */
 
+#ifdef STM32_FLASH_PREFETCH
+      regval = (FLASH_ACR_LATENCY_5 | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_PRFTEN);
+#else
       regval = (FLASH_ACR_LATENCY_5 | FLASH_ACR_ICEN | FLASH_ACR_DCEN);
+#endif
       putreg32(regval, STM32_FLASH_ACR);
 
       /* Select the main PLL as system clock source */
diff --git a/nuttx/arch/arm/src/stm32/stm32f40xxx_rcc.c b/nuttx/arch/arm/src/stm32/stm32f40xxx_rcc.c
index 45980f288..c6c0b2382 100644
--- a/nuttx/arch/arm/src/stm32/stm32f40xxx_rcc.c
+++ b/nuttx/arch/arm/src/stm32/stm32f40xxx_rcc.c
@@ -633,7 +633,11 @@ static void stm32_stdclockconfig(void)
  
       /* Enable FLASH prefetch, instruction cache, data cache, and 5 wait states */
 
+#ifdef STM32_FLASH_PREFETCH
+      regval = (FLASH_ACR_LATENCY_5 | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_PRFTEN);
+#else
       regval = (FLASH_ACR_LATENCY_5 | FLASH_ACR_ICEN | FLASH_ACR_DCEN);
+#endif
       putreg32(regval, STM32_FLASH_ACR);
 
       /* Select the main PLL as system clock source */